View SIP21106DVP-33-T1-E3_3821505.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

vishay siliconix sip21106/8 new product document number: 74442 s-62251?rev. a, 06-nov-06 www.vishay.com 1 150-ma low noise, low dropout regulator applications ? cellular phones, wireless handsets ?pdas ?mp3 players ? digital cameras ? pagers ? wireless modem ? noise-sensitive electronic systems description the sip21106 150 ma bicmos low noise ldo volt- age regulators are the perfect choice for low voltage low power applications. an ultra low ground current in addition to a low dropout voltage of 135 mv (at 150 ma load) helps to extend battery life and makes these ics attractive for battery operated power systems and por- table electronics. the sip21108 does not require external noise bypass capacitor and the output voltage can be adjusted with an external resistor divider. systems requiring a quiet voltage source, such as rf applications, will benefit fr om the sip21106's low out- put noise. these regulators allow stable operation with very small ceramic out put capacitors, reducing required board space and component cost. the sip21106/sip21108 series are designed to maintain regulation while delivering 33 0 ma peak current to sat- isfy systems that have a high surge current upon turn- on. an active pull-down circuit is built into the sip21106/ sip21108 to improve the output transient response and regulation. in shutdown mode, the output voltage is automatically discharged to ground by a 100 n-channel mosfet. the sip21106/sip21108 are available in a super thin lead (pb)-free tsc75-6l package for operation over the industrial operation range (- 40 c to 85 c). features ? tsc75-6l package (1.6 x 1.6 x 0.6 mm) ? 1.0 % output voltage accuracy at 25 c ? low dropout voltage: 135 mv at 150 ma ? sip21106 low noise: 60 v (rms) (10 hz to 100 khz bandwidth) with 10 nf in full load range ? 35 a (typical) ground current at 1 ma load ? 1 a maximum shutdown current at 85 c ? output auto discharge at shutdown mode ? built-in short circuit (330 ma typical) and thermal protection ? sip21108 adjustable output voltage option ? - 40 c to + 125 c junction temperature range for operation ? uses low esr ceramic capacitors ? fixed 1.3 v to 5 v with 50 mv steps typical application circuit t s c75-6l p a ck a ge c byp ass =10 nf v 5 nc v gnd en bp 4 6 2 3 1 c out =1 f v c in = 1 f v en ab le s ip21106 out in out in t s c75-6l p a ck a ge v 5 nc v gnd en adj 4 6 2 3 1 c out = 1 f v c in = 1 f v en ab le s ip2110 8 in out in out r 2 r 1 rohs compliant
www.vishay.com 2 document number: 74442 s-62251?rev. a, 06-nov-06 vishay siliconix sip21106/8 notes: a. derate 7.6 mw/c above t a = 70 c. b. device mounted with all leads soldered or welded to pc board. c. soldering for 5 sec. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating/conditions for extended periods may affect device reliability. absolute maximum ratings parameter limit unit input voltage, v in to gnd - 0.3 to 6 v v en (see detailed description) - 0.3 to 6 output current (i out ) short circuit protected output voltage (v out ) - 0.3 to v in + 0.3 v package power dissipation (p d ) a 420 mw package thermal resistance ( ja ) b 131 c/w maximum junction temperature, t j(max) 125 c storage temperature, t stg - 65 to 150 lead temperature, t l c 260 recommended operating range parameter limit unit input voltage, v in 2.2 to 5.5 v operating ambient temperature t a - 40 to 85 c specifications parameter symbol test conditions unless specified v in = v out(nom) + 1.0 v = v en i out = 1 ma, c in = 1 f, c out = 1 f - 40 c < t a < 85 c for full temp a unit min b typ c max b input voltage range v in full 2.2 5.5 v output voltage accuracy v out i out = 1 ma room - 1.0 1.0 % full - 2.5 2.5 line regulation all others full - 0.2 0.006 0.2 %/v for 4.6 v to 5.0 v - 0.4 0.4 dropout voltage d, g (v out(nom) 2.4 v) v do i out = 50 ma room 45 mv full 55 i out = 100 ma room 90 full 106 i out = 150 ma room 135 180 full 160 240 ground pin current e i gnd i out = 1 ma room 35 75 a full 38 85 i out = 100 ma room 38 full 39 i out = 150 ma room 41 75
document number: 74442 s-62251?rev. a, 06-nov-06 www.vishay.com 3 vishay siliconix sip21106/8 notes: a. room = 25 c, full = - 40 to 85 c. b. the algebraic convention whereby the most negative value is a mi nimum and the most positive a maximum. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. dropout voltage is defined as the input-to-output differential voltage at which the output voltage drops 2 % below its nomina l i value with constant load. for outputs = 2.2 v, dropout volt age is not applicable due to 2.2 v minimum input voltage requireme nt. e. ground current is specified for normal op eration as well as ?drop-out? operation. f. output noise is proportional to output voltage. use formula e n = 60 v(rms)*v out /2.8v. g. v out(nom) is v out when measured with a 1 v differential to v in . specifications parameter symbol test conditions unless specified v in = v out(nom) + 1.0 v i out = 1 ma, c in = 1 f, c out = 1 f - 40 c < t a < 85 c for full temp a unit min b typ c max b output noise voltage f (rms) e n v out(nom) = 2.8 v, bw = 10 hz to 100 khz, 1 ma < i out < 150 ma, c bp = 0.01 f room 60 v v out(nom) = 2.8 v, bw = 10 hz to 100 khz, 1 ma < i out < 150 ma room 350 v ripple rejection psrr i out = 150 ma f = 1 khz room 70 db f = 10 khz room 55 f = 100 khz room 25 load regulation ldr v out 2.5 v, i out : 1 ma to 150 ma room 0.003 0.006 %/ma v out < 2.5 v, i out : 1 ma to 150 ma room 0.005 0.009 auto discharge resistance r dis v out = 2 v room 100 thermal shutdown junction temperature t j(s/d) room 160 c thermal hysteresis t hyst room 20 output current limit i o_limit v out = 0 v room 170 330 600 ma shutdown supply current i cc(off) v en = 0 v room 0.02 1 a en pin input voltage v enh high = regulator on (rising) full 1.2 5.5 v v enl low = regulator off (falling) full 0.4 v en pin input current i en room 0.009 a output voltage turn-on time t on en to v out delay; i out = 1 ma 70 s adjustable voltage section (sip21108 version only) feedback voltage v adj room 1.188 1.2 1.212 v full 1.170 1.230
www.vishay.com 4 document number: 74442 s-62251?rev. a, 06-nov-06 vishay siliconix sip21106/8 timing waveforms pin configuration note: other fixed output voltage options are avail able. please contact your vishay sales r epresentative or distributor for details. figure 1. v en 0.95 v nom v out v nom t on 0 v v in t r 1 s figure 2. en gnd v v nc bp/adj in out top view 1 2 3 4 5 6 en gnd v v nc bp/adj in out bottom view t s c75-6l package (1.6 x 1.6 mm) pin description pin number name function 1 en by applying less than 0.4 v to this pin, the devi ce will be turned off. connect this pin to v in if unused. do not leave floating. 2 gnd ground pin. for better thermal capability , directly connected to large ground plane. 3 v in input supply pin. bypass this pin with a 1-f ceramic or tantal um capacitor to ground. 4 v out output voltage. connect c out between this pin and ground. 5 nc no connection. 6 bp/adj - bp (sip21106): noise bypass pin. for lo w noise applications, a 10 nf ceramic capacitor should be connected from this pin to ground. - adj (sip21108): adjust input pin. connect feedback resistors to program the output voltage for trim value of 1.2005 v. ordering information part number marking voltage temperature range package sip21108dvp-t1-e3 aa adjustable - 40 c to 85 c tsc75-6l sip21106dvp-18-t1-e3 bg 1.8 sip21106dvp-28-t1-e3 bt 2.8 SIP21106DVP-33-T1-E3 by 3.3 sip21106dvp-46-t1-e3 cm 4.6
document number: 74442 s-62251?rev. a, 06-nov-06 www.vishay.com 5 vishay siliconix sip21106/8 typical characteristics output voltage vs. input voltage dropout voltage vs. load current dropout voltage vs. temperature 0.00 0.50 1.00 1.50 2.00 2.50 3 .00 0.00 1.00 2.00 3 .00 4.00 5.00 v in ( v ) v out (v) i out = 0 ma i out = 150 ma s ip21106: 2. 8 v 0 20 40 60 8 0 100 120 140 160 1 8 0 0 25 50 75 100 125 150 i out (ma) v do (mv) t a = + 8 5 c t a = + 25 c t a = - 40 c s ip21106: 2. 8 v 20 40 60 8 0 100 120 140 160 1 8 0 - 40 - 15 10 3 560 8 5 temper a t u re (c) v do (mv) i out = 150 ma i out = 100 ma i out = 50 ma s ip21106: 2. 8 v output voltage accuracy vs. temperature dropout voltage vs. output voltage ground current vs. temperature - 1.50 - 1.00 - 0.50 0.00 0.50 1.00 - 40 - 15 10 3 560 8 5 temper a t u re (c) devi a tion( % ) i out = 1 ma s ip21106: 2. 8 v 60 8 0 100 120 140 160 1 8 0 22.5 33 .5 4 4.5 5 v out (v) v do (mv) i out = 150 ma i out = 100 ma s ip21106: 2. 8 v 3 4 3 5 3 6 3 7 38 3 9 40 41 - 40 - 15 10 3 560 8 5 temper a t u re (c) i out = 150 ma i out = 1 ma s ip21106: 2. 8 v
www.vishay.com 6 document number: 74442 s-62251?rev. a, 06-nov-06 vishay siliconix sip21106/8 typical characteristics ground current vs. output current psrr output noise vs. bp capacitance 25 3 0 3 5 40 45 50 0 25 50 75 100 125 150 i out (ma) i gnd ( a) v in = 5.5 v v in = 3 . 8 v s ip21106: 2. 8 v p s rr (db) fre qu ency (hz) 0.01k -10 0 10 20 3 0 40 50 60 70 8 0 s ip21106: 2. 8 v v in = 3 . 8 v v out = 3 .0 v c in = 1 f c out = 1 f c bp = 10 nf i out = 100 ma i out = 0 ma i out = 150 ma 0.1k 1k 10k 100k 1000k o u tp u t noi s e ( v) 0 0.001 0.0056 0.01 0.056 0.1 bp c a p a cit a nce ( f) s ip21106: 2. 8 v 50 100 150 200 250 3 00 3 50 400 ground current vs. input voltage at 25 c output voltage accuracy vs. load current 0 10 20 3 0 40 50 0.0 1.0 2.0 3 .0 4.0 5.0 v in (v) i gnd ( a) i out = 150 ma i out = 1 ma s ip21106: 2. 8 v v out (v) 2.720 2.740 2.760 2.7 8 0 2. 8 00 2. 8 20 - 40 - 15 10 3 560 8 5 temper a t u re (c) i out = 1 ma i out = 150 ma i out = 50 ma s ip21106: 2. 8 v v in = 3 . 8 v
sip21106/8 vishay siliconix document number: 74442 s-62251?rev. a, 06-nov-06 www.vishay.com 7 typical operating waveforms 50 s/div load transient response 200 s/div line transient response 200 s/div line transient response i out (100 ma/div) v out (50 mv/div) sip21106: 4.6 v v in = 5.5 v v out = 4.6 v c in = 1 f c out = 1 f c bp = 10 nf v out (10 mv/div) v in (200 mv/div) ac coupling sip21106: 4.6 v v in = 5.0 to 5.5 v i out = 150 ma c bp = 10 nf v out = 4.6 v c out = 1 f c in = 1 f v out (10 mv/div) v in (200 mv/div) ac coupling sip21106: 4.6 v v in = 5.0 to 5.5 v i out = 1 ma c in = 1 f c bp = 10 nf v out = 4.6 v c out = 1 f 50 s/div load transient response 200 s/div line transient response 200 s/div line transient response i out (100 ma/div) v out (50 mv/div) sip21106: 2.8 v v in = 3.8 v v out = 2.8 v c in = 1 f c out = 1 f c bp = 10 nf sip21106: 2.8 v v in = 3.8 to 4.8 v v out = 2.8 v i out = 150 ma c in = 1 f c out = 1 f c bp = 10 nf v in (1 v/div) ac coupling v out (10 mv/div) v in (1 v/div) ac coupling sip21106: 2.8 v v in = 3.8 to 4.8 v v out = 2.8 v i out = 1 ma c in = 1 f c out = 1 f c bp = 10 nf v out (10 mv/div)
www.vishay.com 8 document number: 74442 s-62251?rev. a, 06-nov-06 vishay siliconix sip21106/8 typical operating waveforms typical waveforms 50 ms/div output short circuit current 20 s/div output voltage power-down sip21106: 2.8 v v in = 3.8 v v out = 2.8 v c in = 1 f c out = 1 f c bp = 10 nf i out (50 ma/div) sip21106: 2.8 v v in = 3.8 v v out = 2.8 v c in = 1 f c out = 1 f c bp = 10 nf i out = 150 ma v en (500 mv/div) v out (500 mv/div) 50 ms/div output short thermal cycling 20 s/div output voltage start-up sip21106: 2.8 v v in = 3.8 v v out = 2.8 v c in = 1 f c out = 1 f c bp = 10 nf i out (100 ma/div) sip21106: 2.8 v v in = 3.8 v v out = 2.8 v c in = 1 f c out = 1 f c bp = 10 nf i out = 150 ma v out (500 mv/div) v en (1 v/div) 2 ms/div output noise sip21106: 2.8 v v in = 4.5 v v out = 2.8 v c in = 1 f c out = 1 f c bp = 10 nf i out = 150 ma v out (100 v/div) v noise = 60 v rms output noise spectral density 1 0.01 0.1 noi s e s pectr a l den s ity ( v/ hz) fre qu ency (hz) 10k 1m 1k 100 10 100k c out = 1 f c bp = 10 nf i out = 100 ma v out = 2.8 v c in = 1 f sip21106: 2.8 v v in = 3.8 v
sip21106/8 vishay siliconix document number: 74442 s-62251?rev. a, 06-nov-06 www.vishay.com 9 functional block diagram figure 3. v v in out en ab le b a ndg a p c u rrent limit & therm a l reference error-amp en * ** bp/adj gnd s ip21106: bp s ip2110 8 : adj * * s ip21106 ** s ip2110 8
www.vishay.com 10 document number: 74442 s-62251?rev. a, 06-nov-06 vishay siliconix sip21106/8 detailed description as shown in the block diagram, the circuit consists of a bandgap reference, error amplifier, p-channel pass transistor and internal feedback resistor voltage divider, which is used to monitor the output voltage. a constant 1.2 v bandgap reference voltage is applied to the inverting input of th e error amplifier. the error amplifier compares this reference with the feedback voltage on its non-inverting input and amplifies the difference. if the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled low. this increa ses the mosfet's gate to source voltage and allows more current to pass through the transistor to the output which increases the output voltage. conversely, if the feedback voltage is higher than the reference voltage, the pass transistor gate is pulled high, decreasing the gate-to-source voltage, thereby allowing less current to pass to the output and causing it to drop. an external 10 nf bypass capacitor connected to the bp pin of sip21106 reduces noise at the output. internal p-channel pass transistor a 0.9 (typical) p-channel mosfet is used as the pass transistor for the sip21106/sip21108 part series. the mosfet transistor offers many advantages over the more, formerly, common pnp pass transistor designs, which ultimately resu lt in longer battery life- time. the main disadvantage of pnp pass transistors is that they require a certain base current to stay on, which significantly increases under heavy load condi- tions. in addition, during dropout, when the pass tran- sistor saturates, the pnp regulators waste considerable current. in contrast, p-channel mos- fets require virtually zero-base drive and do not suf- fer from the stated problems. these savings in base drive current translate to lower quiescent current which is typical around 30 a as shown in the typical char- acteristics output voltage selection the sip21106 has fixed voltage outputs that are pre- set to voltages from 1.8 v to 4.6 v (see ordering infor- mation). the sip21108 has a user-adjustable output that can be set through the resistor feedback network consist- ing of r 1 and r 2 . r 2 range of 100k to 400k is recommended to be consistent with ground current specification. r 1 can then be determined by the follow- ing equation: where v ref is typically 1.2005 v. use 1 % or better resistors for better output voltage accuracy (see figure 4). current limit the sip21106/sip21108 include a current limit block which monitors the current passing through the pass transistor through a current mirror and controls the gate voltage of the mosfet, limiting the output cur- rent to 330 ma (typical). this current limit feature allows for the output to be shorted to ground for an indefinite amount of time without damaging the device. thermal-overload protection the thermal overload protection limits the total power dissipation and protects the device from being dam- aged. when the junction temperature exceeds t j = 150 c, the device turns the p-channel pass tran- sistor off allowing the device to cool down. once the temperature drops by about 20 c, the thermal sensor turns the pass transistor on again and resumes normal operation. consequently, a continuous thermal over- load condition will result in a pulsed output. it is gener- ally recommended to not exceed the junction temperature rating of 125 c for continuous operation. figure 4. error-amp + _ adj 1.2 v reference v r r out 1 2 v in r = r x - 1 1 2 v out v ref ( )
sip21106/8 vishay siliconix document number: 74442 s-62251?rev. a, 06-nov-06 www.vishay.com 11 noise reduction in sip21106 for the sip21106, an external 10 nf bypass capacitor at bp pin is used to create a low pass filter for noise reduction. the startup time is fast, since a power-on circuit pre-charges the bypa ss capacitor. after the power-up sequence the pre-charge circuit is switched to standby mode in order to save current. it is therefore not recommended to use larger bypass capacitor val- ues than 50 nf. when the circuit is used without a capacitor, stable operation is guaranteed. shutdown and auto-dischage/no-discharge bringing the en voltage low will place the part in shut- down mode where the device output enters a high- impedance state and the quiescent current is reduced to below 1 a, reducing the drain on the battery in standby mode and increasing standby time. connect en pin to input for normal operation. the output has an internal pull down to discharge the output to ground when the en pin is low. the internal pull down is a 100 typical resistor, which can discharge a 1 f in less than 1 ms. refer to typical operating waveforms for turn-off waveforms. application information input/output capacitor selection and regulator stability it is recommended that a low esr 1 f capacitor be used on the sip21106/sip21108 input. a larger input capacitance with lower esr would improve noise rejection and line-transient response. a larger input bypass capacitor may be required in applications involving long inductive traces between the source and ldo. the circuit is stable with only a small output capacitor equal to 6 nf/ma ( 1 f at 150 ma) of load. since the bandwidth of the error amplifier is around 1 - 3 mhz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150 ma load current, an esr < 0.4 is necessary. parasitic inductance of about 10 nh can be tolerated. applying a larger output capacitor would increase power supply rejection and improve load-transient response. some ceramic dielectrics such as the z5u and y5v exhibit large capacitance and esr variation over temperature. if such capacitors are used, a 2.2 f or larger value may be n eeded to ensure stability over the industrial temperature range. if using higher quality ceramic capacitors, such as those with x7r and y7r dielectrics, a 1 f capacitor will be sufficient at all oper- ating temperatures. operating region and power dissipation an important consideration when designing power supplies is the maximum a llowable power dissipation of a part. the maximum power dissipation in any appli- cation is dependant on the maximum junction temper- ature, tj (max) = 125 c, the ambient temperature, t a , and the junction-to-ambient thermal resistance for the package, which is the summation of j-c , the thermal resistance of the package, and c-a , the thermal resis- tance through the pc board and copper traces. power dissipation may be formulaically expressed as: the gnd pin of the sip21106/sip21108 acts as both the electrical connection to gnd as well as a path for channeling away heat. connect this pin to a gnd plane to maximize heat dissipation.once maximum powchanneler dissipation is calculated using the equation above, the maximum allowable output cur- rent for any input/output potential can be calculated as pcb layout the component placement around the ldo should be done carefully to achieve good dynamic line and load response. the input and noise capacitor should be kept close to the ldo. the rise in junction temperature depends on how efficiently the heat is carried away from junction-to-ambient. the junction-to-lead thermal impedance is a characteristic of the package and is fixed. the thermal impedance between lead-to-ambi- ent can be reduced by increasing the copper area on pcb. increase the input, output and ground trace area to reduce the junction-to-ambient thermal impedance. vishay siliconix maintains worldwide manufac turing capability. products ma y be manufactured at one of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?74442. p (m a x) = t (m a x) - t j + j-c c-a a i out(m a x) = p (m a x) v - in v out
legal disclaimer notice vishay document number: 91000 www.vishay.com revision: 08-apr-05 1 notice specifications of the products displayed herein are subjec t to change without notice. vishay intertechnology, inc., or anyone on its behalf, assume s no responsibility or liability fo r any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale.

▲Up To Search▲

Price & Availability of SIP21106DVP-33-T1-E3

	To Download SIP21106DVP-33-T1-E3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .