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1 features ? 25ns maximum (5 volt supply) address access time ? asynchronous operation for compatible with industry standard 512k x 8 srams ? ttl compatible inputs and output levels, three-state bidirectional data bus ? operational environment: - total dose: 50 krads(si) - sel immune >110 mev-cm 2 /mg - let th (0.25) = >52 mev-cm 2 /mg - saturated cross section (cm 2 ) per bit, 2.8e-8 - < 1.1e-9 errors/bit-day, adams 90% geosynchronous heavy ion ? packaging: - 68-lead dual cavity ceramic quad flatpack (cqfp) (11.0 grams) ? standard microcircuit drawing 5962-01511 - qml q compliant part introduction the ut9q512k32e radtol product is a high-performance 2m byte (16mbit) cmos static ra m multi-chip module (mcm), organized as four individual 524,288 x 8 bit srams with a common output enable. memory expansion is provided by an active low chip enable (e n), an active low output enable (g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to each memory is accomp lished by taking chip enable (e n) input low and write enable (w n) inputs low. data on the eight i/o pins (dq 0 through dq 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (e n) and output enable (g ) low while forcing write enable (w n) high. under these conditions, the cont ents of the memory location specified by the address pins wi ll appear on the i/o pins. the input/output pins are placed in a high impedance state when the device is deselected (e n high), the outputs are disabled (g high), or during a write operation (e n low and w n low). perform 8, 16, 24 or 32 bit accesses by making w n along with e n a common input to any combination of the discrete memory die. standard products ut9q512k32e 16 megabit rad sram mcm preliminary data sheet january, 2009 512k x 8 512k x 8 512k x 8 512k x 8 dq(31:24) or dq3(7:0) dq(23:16) or dq2(7:0) dq(15:8) or dq1(7:0) dq(7:0) or dq0(7:0) g a(18:0) w 3 e 3 e 2 e 1 e 0 w 2 w 1 w 0 figure 1. ut9q512k32e sram block diagram
2 pin names device operation the ut9q512k32e has three control inputs called enable 1 (e n), write enable (w n), and output enable (g ); 19 address inputs, a(18:0); and eight bidir ectional data lines, dq(7:0). e n device enable controls device se lection, active, and standby modes. asserting e n enables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. w n controls read and write operations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. read cycle a combination of w n greater than v ih (min) and e n less than v il (max) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 3a, is initiated by a change in address inputs while the chip is enabled with g asserted and w n deasserted. valid data appears on data outputs dq(7:0) after the specified t av q v is satisfied. outputs remain active throughout the entire cycle. as long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). sram read cycle 2, the chip enable - controlled access in figure 3b, is initiated by e n going active while g remains asserted, w n remains deasserted, and the addresses remain stable for the entire cycl e. after the specified t etqv is satisfied, the eight-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(7:0). sram read cycle 3, the output enable - controlled access in figure 3c, is initiated by g going active while e n is asserted, w n is deasserted, and the addresse s are stable. read access time is t glqv unless t avqv or t etqv have not been satisfied. a(18:0) address w n write enable dqn(7:0) data input/output g output enable e n enable v dd power v ss ground g w n e n i/o mode mode x 1 x 1 3-state standby x 0 0 data in write 1 1 0 3-state read 2 0 1 0 data out read 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 top view dq0(0) dq1(0) dq2(0) dq3(0) dq4(0) dq5(0) dq6(0) dq7(0) v ss dq0(1) dq1(1) dq2(1) dq3(1) dq4(1) dq5(1) dq6(1) dq7(1) nc a0 a1 a2 a3 a4 a5 e 2 v ss e 3 w 0 a6 a7 a8 a9 a10 v dd v dd a11 a12 a13 a14 a15 a16 e 0 g e 1 a17 w 1 w 2 w 3 a18 nc nc dq0(2) dq1(2) dq2(2) dq3(2) dq4(2) dq5(2) dq6(2) dq7(2) v ss dq0(3) dq1(3) dq2(3) dq3(3) dq4(3) dq5(3) dq6(3) dq7(3) figure 2. 25ns sram pinout (68)
3 write cycle a combination of w n less than v il (max) and e n less than v il (max) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w n is less than v il (max). write cycle 1, the write enable-controlled access is defined by a write terminated by w n going high, with e n still active. the write pulse width is defined by t wlwh when the write is initiated by w n, and by t etwh when the write is initiated by e n. unless the outputs have been previous ly placed in the high-impedance state by g , the user must wait t wlqz before applying data to the nine bidirectional pins dq(7:0) to avoid bus contention. write cycle 2, the chip enable-controlled access is defined by a write terminated by the latter of e n going inactive. the write pulse width is defined by t wlef when the write is initiated by w n, and by t etef when the write is initiated by the e n going active. for the w n initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. operational environment the ut9q512k32e sram incorpor ates features which allows operation in a limited environment. table 2. operation al environment design specifications 1 notes: 1. the sram will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environmen t, geosynchronous orbit, 100 mils of aluminum. to tal d ose 50 krad(si) heavy ion error rate 2 <1.1e-9 errors/bit-day
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may aff ect device reliability and performance. 2. maximum junction temperat ure may be increased to +175 c during burn-in an d steady-static life. 3. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.5 to 7.0v v i/o voltage on any pin -0.5 to 7.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.0w (per byte) t j maximum junction temperature 2 +150 c jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10 ma symbol parameter limits v dd positive supply voltage 4.5 to 5.5v t c case temperature range (w) screen - 40 c to 105 c v in dc input voltage 0v to v dd
5 dc electrical characteristics (pre/post-radiation)* -40 c to +105 c (v dd = 5.0v + 10% for (w) screening) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019. 1. measured only for in itial qualification and after process or design ch anges that could affect input/output capacitance. 2. supplied as a design limit bu t not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. symbol parameter condition min max unit v ih high-level input voltage (ttl) 2.0 v v il low-level input voltage (ttl) 0.8 v v ol1 low-level output voltage i ol = 8ma, v dd =4.5v (ttl) 0.4 v v ol2 low-level output voltage i ol = 200 a,v dd =4.5v (cmos) 0.08 v v oh1 high-level output voltage i oh = -4ma,v dd =4.5v (ttl) 2.4 v v oh2 high-level output voltage i oh = 200 a,v dd =4.5v (cmos) 3.0 v c in 1 input capacitance ? = 1mhz @ 0v 45 pf c io 1 bidirectional i/o capacitance ? = 1mhz @ 0v 25 pf i in input leakage current v in = v dd and v ss, v dd = v dd (max) -2 2 a i oz three-state output leakage current v o = v dd and v ss v dd = v dd (max) g = v dd (max) -2 2 a i os 2, 3 short-circuit output current v dd = v dd (max), v o = v dd v dd = v dd (max), v o = 0v -90 90 ma i dd (op) supply current operating @ 1mhz (per byte) inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 40 ma i dd1 (op) supply current operating @40mhz (per byte) inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 70 ma i dd2 (sb) supply current standby @0mhz (per byte) inputs: v il = v ss i out = 0ma e1 = v dd - 0.5, v dd = v dd (max) v ih = v dd - 0.5v 9 24 ma ma -40 c and 25 c 105 c
6 ac characteristics read cycle (pre/post-radiation)* -40 c to +105 c (v dd = 5.0v + 10% for (w) screening) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test. 2. three-state is defined as a 500mv ch ange from steady-state output voltage. 3. the et (enable true) notation refers to the fa lling edge of e n. seu immunity does not affect the read parameters. 4. the ef (enable false) notation refers to the rising edge of e n. seu immunity does not affect the read parameters. symbol parameter min max unit t avav 1 read cycle time 25 ns t av q v read access time 25 ns t axqx 2 output hold time 3 ns t glqx 2 g -controlled output enable time 0 ns t glqv g -controlled output enable time (read cycle 3) 10 ns t ghqz 2 g -controlled output three-state time 10 ns t etqx 2,3 e n-controlled output enable time 3 ns t etqv 3 e n-controlled access time 25 ns t efqz 1,2,4 e n-controlled output three-state time 10 ns { { } } v load + 500mv v load - 500mv v load v h - 500mv v l + 500mv active to high z levels high z to active levels figure 3. 5-volt sram loading
7 assumptions: 1. e n and g < v il (max) and w n > v ih (min) a(18:0) dqn(7:0) figure 4a. sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g < v il (max) and w n > v ih (min) a(18:0) figure 4b. sram read cycle 2: chip enable-controlled access e n data valid t efqz t etqv t etqx dqn(7:0) figure 4c. sram read cycle 3: output enable-controlled access a(18:0) qn(7:0) t ghqz ssumptions: e n < v il (max) and w n > v ih (min) t glqv t glqx t avqv data valid
8 ac characteristics write cycle (pre/post-radiation)* -40 c to +105 c (v dd = 5.0v + 10% for (w) screening) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test performe d with outputs disabled (g high). 2. three-state is defined as 500mv cha nge from steady-state output voltage. symbol parameter min max unit t avav 1 write cycle time 25 ns t etwh device enable to end of write 20 ns t av e t address setup time for write (e n - controlled) 1 ns t av w l address setup time for write (w n - controlled) 0 ns t wlwh write pulse width 20 ns t whax address hold time for write (w n - controlled) 0 ns t efax address hold time for device enable (e n - controlled) 0 ns t wlqz 2 w n - controlled three-state time 10 ns t whqx 2 w n - controlled output enable time 5 ns t etef device enable pulse width (e n - controlled) 20 ns t dvwh data setup time 15 ns t whdx data hold time 2 ns t wlef device enable controlled write pulse width 20 ns t dvef data setup time 15 ns t efdx data hold time 2 ns t av w h address valid to end of write 20 ns t whwl 1 write disable time 5 ns
9 assumptions: 1. g < v il (max). if g > v ih (min) then qn(7:0) will be in three-state for the entire cycle. 2. g high for t avav cycle. w n t av w l figure 5a. sram write cycle 1: write enable - controlled access a(18:0) qn(7:0) e n t avav 2 dn(7:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t av w h t whwl
10 t efdx assumptions & notes: 1. g < v il (max). if g > v ih (min) then qn(7:0) will be in three-state for the entire cycle. 2. either e n scenario above can occur. 3. g high for t avav cycle. a(18:0) figure 5b. sram write cycle 2: chip enable - controlled access w n e n dn(7:0) applied data e n qn(7:0) t wlqz t etef t wlef t dvef t avav 3 t av e t t av e t t etef t efax t efax or notes: 1. 50pf including scope prob e and test socket capacitance. 2. measurement of data output o ccurs at the low to high or hi gh to low transition mid-point (i.e., cmos input = v dd /2). 90% figure 6. ac test loads and input waveforms input pulses 10% < 5ns < 5ns v load = 1.55v 300 ohms 50pf cmos 0.5v v dd -0.05v 10%
11 data retention characteris tics (pre-radiation) *(v dd2 = v dd2 (min), 1 sec dr pulse) notes: * post-radiation performance guaranteed at 25 o c per mil- std-883 method 1019. 1. e n = v dd all other inputs = v dd or v ss v dd data retention mode t r 4.5v 4.5v v dr > 2.5v figure 7. low v dd data retention waveform t efr en v dd = v dr symbol parameter temp minimum maximum unit v dr v dd1 for data retention -- 2.5 -- v i ddr 1 data retention current (per byte) -40 o c 25 o c 105 o c -- -- -- 9 9 24 ma ma ma t efr 1 chip deselect to data retention time -- 0 -- ns t r 1 operation recovery time -- t avav -- ns
12 packaging notes: 1. all exposed metallized areas are gold plated over nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. packages may be shipped wi th repaired leads as shown. 4. coplanarity requirements do not apply in repaired area. 5. letter designations are to cross reference to mil-std-1835. 6. lead true position tolerances are coplanarity are not measured. 7. capacitor pads are sized to fit cdr32 (1206) capacitors. figure 8. 68-lead ceramic quad flatpack
13 ordering information 512k32 16megabit sram mcm: device type: - =25ns access time, 5.0v operation package type: (s) = 68-lead dual cavity cqfp screening: (p) = prototype flow (w) = -40 o c to +105 o c lead finish: (c) = gold notes: 1. prototype flow per aeroflex colorado springs manu facturing flows document. devices are tested at 25 o c. radiation neither tested nor guaranteed. gold lead finish only. 2. extended industrial temperature range fl ow per aeroflex colorado springs manufactur ing flows document. devices are tested at -40 c to +105 c. radiation neither tested nor guar anteed. gold lead finish only. ut9q512k32e -* * * * aeroflex utmc core part number
14 512k32e 16megabit sram mcm: smd 5962 - 01511 ** ** * notes: 1. total dose radiation must be specified when ordering. gold finish only. federal stock class designator: no options total dose (d) = 1e4 (10krad(si)) (p) = 3e4 (30krad(si)) (contact factory) (l) = 5e4 (50krad(si)) (contact factory) drawing number: 01511 device type 02 = 25 ns access time, 5.0v operation, (-40 o c to +105 o c) class designator: (q) = qml class q case outline: (y) = 68-lead dual cavity cqfp lead finish: (c) = gold
15 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hirel

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