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igloo ? plus handbook

igloo plus handbook table of contents low-power flash device handbooks introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i section i ? igloo plus datasheet igloo plus low-power flash fpgas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i igloo plus device family overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 igloo plus dc and switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 package pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 section ii ? core architecture low-power flash technology and flash*freeze mode fpga array architecture in low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1- 1 actel?s flash*freeze technology and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 global resources and clock conditioning global resources in actel low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 clock conditioning circuits in low-po wer flash devices and mixed-signal fpgas . . . . . . . . . . . . . . .4-1 embedded memories flashrom in actel?s low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 sram and fifo memories in actel's low- power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 i/o descriptions and usage i/o structures in igloo plus devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 i/o software control in low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 packaging and pin descriptions pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 programming and security programming flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 security in low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 in-system programming (isp) of actel? s low-power flash devices using flashpro3 . . . . . . . . . . . . .13-1 core voltage switching circuit for igloo and proasic3l in-system programming . . . . . . . . . . . . .14-1 boundary scan and ujtag
table of contents boundary scan in low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1 ujtag applications in actel?s low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1 board-level requirements power-up/-down behavior of low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1
v1.1 i-i low-power flash device handbooks introduction device handbooks contain all th e information available to help designers understand and use actel's devices. handbook chapters are groupe d into sections on th e website to simplify navigation. each chapter of the handbook may be viewed as an individual pdf file. at the top of the handbook web page, you will see a pdf file for each product family. this file contains the complete device handbook. please re gister for product updates to be notified when a section of the handbook changes. table i-1 ? differences between former data sheets and device handbooks description of change comparison between handbook and datasheet the silicon datasheet in the handbook does not contain the same chapters as the previous versions of the datasheets. the former version of the silicon datasheet contained the following: ? general description ? device architecture ? dc and switching characteristics ? packaging the current datasheet now contains: ? product brief (same information as the general description) ? dc and switching characteristics ? packaging the information previo usly contained in the device architecture chapter has been separated into individual chapters and merged with relevant application note co ntent to provide one location for information on each architectural feature. the general description section no longer exists in datasheets. the product brief and the general description consisted of basically the same information but with diff erent titles. to eliminate the duplicated information, we change d the document name to product brief. change tables were carried forward through this process; they contain information from the old datasheets and the new datasheets. it is important that all earlier te chnical changes from the datasheets are listed so customers can determine if any of the changes affect their designs. changes are liste d chronologically , with the most current at the top and the earl ier changes listed below them. version numbers were restarted. the version nu mbers were restarted when the handbooks were created. for example, a datasheet may have been v2.1 and is now v1.0. the category (i.e., advance or production) of the datasheet did not change. the only ch ange occurred to the actual numbering of the datasheet. all version numbers are located in the footer of the page. publication date the publication date indicates when the document was published and posted to the actel website. the former datasheets were two columns and the current datasheets and handbooks are formatted with one column. we changed the datasheet form at to accommodate the large graphics and to improve readability.
low-power flash device handbooks introduction i-ii v1.1 each chapter within a handbook can have a different version number. each chapter in the handbook ha s a its own version number. since the chapters are independent do cuments and can be updated at different times, the version number s for each chapter increment only when a change is made to that chapter. for ex ample, in the proasic3l handbook, the dc and switching section is advance v0.2, the packaging pin assignments is v1.0, and the global resources section is v1.1. the dc and switch ing section is advance because the data has not been fully characte rized. the packaging and global resources chapters are both production versions because the data is final. they have different version numbers because they were updated at different times. chapters can be numbered differently in each of the handbooks, but the version number for that chapter should be consistent throughout all handbooks. chapters are also published individually without chapter numbers. chapters with shared content are re used across multiple handbooks. the number of chapters in each handbook vari es depending on content, so the pin descriptions chapter could be chapter 7 in one handbook and chapter 9 in anothe r. this is shown only in the combined handbook version of the document. the content within the chapters and version numbers is the same across each handbook for that chapter. if the chapter is updated it will be reposted for all associated handbooks. there are three versions of the i/o structure chapter. there are several major differen ces between the following device groups: ? igloo plus ? igloo/proasic3/proasic3l ? iglooe/proasic 3el/proasic3e as a result, we have three different i/o structures chapters to describe the features in detail. the part number of the datasheet has changed. part numbers are used internally to track documents. each document has its own unique part number. the number after second the dash indicates the revision of the do cument. for example, in the part number, 51700094-006-1, 51700094-006 is the part number and 1 is the revision of the document. we start with 0 for all new documents. there is a part number for the cu rrent version of the datasheet on the back page with the addresses. in addition, all chapters in the datasheet and handbooks have their own unique part numbers. when we implemented the curr ent handbook format, existing documents were assigned new part numbers. the information contained in the core architecture section of the silicon handbook includes information previously found in application notes. the chapters in the silicon handbook combine application notes that previously had very detailed in formation about an architectural feature and information from the former datasheets. in addition, because the information was very similar among several of actel's low-power flash devices, we combined the information into one document. the supported families ta bles describe which devices are supported in the document. the ap plication notes that contained specific architecture information and were combined into the handbook and many no longer exist as standalone application notes. those that do exist in standalone version have been assigned an ac number (top right of first page ) to help identify them. the ac number appears in the standalo ne version and in the handbook chapters where they occur. table i-1 ? differences between former datasheets and device handbooks (continued) description of change comparison between handbook and datasheet
low-power flash device handbooks introduction v1.1 i -iii versions device handbook chapters may have different version numbers. actel?s goal is to provide customers with the latest information in a timely matter. as a result, the handbook chapters will be updated independently of the handbook. categories in order to provide the latest information to desi gners, some datasheets are published before data has been fully characteri zed. datasheets are designated as ?product brief,? ?advance,? and ?production?. the definition of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advance or production) and contains general product information. this document give s an overview of specific device and family information. advance this version contains initial estimated information based on simulation, ot her products, devices, or speed grades. this information can be used as estimates, but not for production. this label only applies to the dc and switching characteristics chapte r of the datasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on si mulation and/or initia l characterization. the information is believed to be co rrect, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this do cument are subject to the expo rt administration regulations (ear). they could require an ap proved export license prior to export from the united states. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. the location of the followin g information has changed in the current handbook format: former datasheet location current handbook location ccc/pll specification table core architec ture dc and switching section > clock conditioning circuits peak-to-peak jitter waveform core architec ture dc and switching section > clock conditioning circuits table i-1 ? differences between former datasheets and device handbooks (continued) description of change comparison between handbook and datasheet
low-power flash device handbooks introduction i-iv v1.1 part number and revision date part number 51700094-001-1 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) this document was rewritten to addr ess the differences between the former datasheets and new device handbooks. n/a
section i ? igloo plus datasheet

august 2008 i ? 2008 actel corporation igloo plus low-power flash fpgas with flash*freeze technology features and benefits low power ? 1.2 v to 1.5 v core voltage support for low power ? supports single-voltage system operation ? 5 w power consumption in flash*freeze mode ? low-power active fpga operation ? flash*freeze technology enables ultra-low power consumption while maintaining fpga content ? configurable hold previous state, tristate, high, or low state per i/o in flash*freeze mode ? easy entry to / exit from ultra-low-power flash*freeze mode feature rich ? 30 k to 125 k system gates ? up to 36 kbits of true dual-port sram ? up to 212 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal, flash-based cmos process ? live-at-power-up (lapu) level 0 support ? single-chip solution ? retains programmed design when powered off in-system programming (isp) and security ? secure isp using on-chip 128-bit advanced encryption standard (aes) decryption via jtag (ieee 1532?compliant) ? ?flashlock ? to secure fpga contents high-performance routing hierarchy ? segmented, hierarchical routing and clock structure advanced i/o ? 1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?4 banks per chip on all igloo ? plus devices ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v / 1.8 v / 1.5 v / 1.2 v ? selectable schmitt trigger inputs ? i/o registers on input, output, and enable paths ? hot-swappable and cold-sparing i/os ? programmable output slew rate and drive strength ? weak pull-up/-down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible small-footprin t packages across the igloo plus family clock conditioning circuit (ccc) and pll ? ? six ccc blocks, one with an integrated pll ? configurable phase shift, multiply/divide, delay capabilities, and external feedback ? wide input frequency range (1.5 mhz up to 250 mhz) embedded memory ? 1 kbit of flashrom user nonvolatile memory ? srams and fifos with variab le-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations) ? ? true dual-port sram (except 18) ? ? ? the aglp030 device does not support this feature. table 1-1 ? igloo plus product family igloo plus devices aglp030 aglp060 aglp125 system gates 30 k 60 k 125 k typical equivalent macrocells 256 512 1,024 versatiles (d-flip-flops) 792 1,584 3,120 flash*freeze mode (typical, w) 5 10 16 ram kbits (1,024 bits) ?1836 4,608-bit blocks ?48 secure (aes) isp ?yesyes flashrom bits 1 k1 k1 k integrated pll in cccs ? 1 1 versanet globals * 61818 i/o banks 444 maximum user i/os 120 157 212 package pins cs vq cs201, cs289 vq128 cs201, cs289 vq176 cs281, cs289 note: *six chip (main) and twelve quadrant global networks are available for aglp060 and aglp125. v1.2
ii v1.2 i/os per package 1 igloo plus devices aglp030 aglp060 aglp125 package single-ended i/os cs201 120 157 ? cs281 ? ? 212 cs289 120 157 212 vq128 101 ? ? vq176 ? 137 ? note: when the flash*freeze pin is used to directly enable fl ash*freeze mode and not used as a regular i/o, the number of single-ended user i/os ava ilable is reduced by one. table 1-2 ? package dimensions package cs201 cs281 cs289 vq128 vq176 length width (mm/mm) 8 8 10 10 14 14 14 14 20 20 nominal area (mm 2 ) 64 100 196 196 100 pitch (mm) 0.5 0.5 0.8 0.4 0.4 height (mm) 0.89 1.05 1.20 1.0 1.0
igloo plus low-pow er flash fpgas v1.2 iii igloo plus ordering information notes: 1. marking information: igloo plus v2 devices do not have a v2 marking, but igloo plus v5 devices are marked accordingly. 2. the dc and switching characteri stics for the ?f speed grade target s are based only on simulation. the characteristics provided for the ?f speed grade are subject to change after establishing fpga specifications. some restrictions might be added and will be reflected in future revisi ons of this document. th e ?f speed grade is only supported in the commercial temperature range. 3. "g" indicates rohs-compliant packages. s pee d g ra d e blank = s tan d ar d f = 20% s lower than s tan d ar d* s upply volta g e 2 = 1.2 v to 1.5 v 5 = 1.5 v only a g lp125 v2 cs _ part num b er pa c ka g e type 289 i pa c ka g e lea d c ount g lea d -free pa c ka g in g appli c ation (temperature ran g e) blank = c ommer c ial (0 c to +70 c am b ient temperature) i= in d ustrial ( ? 40 c to +85 c am b ient temperature) blank = s tan d ar d pa c ka g in g g = roh s - c ompliant pa c ka g in g pp = pre-pro d u c tion e s =en g ineerin g s ample (room temperature only) 30,000 s ystem g ates a g lp030 = 6 0,000 s ystem g ates a g lp0 6 0= 125,000 s ystem g ates a g lp125 = cs = c hip sc ale pa c ka g e (0.5 mm an d 0.8 mm pit c hes) vq = very thin qua d flat pa c k (0.4 mm pit c h)
iv v1.2 temperature grade offerings speed grade and temperature grade matrix contact your local actel represen tative for device availability: http://www.actel.com/compa ny/contact/default.aspx . package aglp030 aglp060 aglp125 cs201 c, i c, i ? cs281 ??c, i cs289 c, ic, ic, i vq128 c, i ? ? vq176 ?c, i? notes: 1. c = commercial temperature range: 0c to 70c ambient temperature. 2. i = industrial temperature range: ?40c to 85c ambient temperature. temperature grade ?f 1 std. c 2 ?? i 3 ? ? notes: 1. the characteristics prov ided for the ?f speed grade are subject to change a fter establishing fpga specifications. some restrictions might be added and will be reflected in future revisions of th is document. the ?f speed grade is only supported in the commerc ial temperature range. 2. c = commercial temperature range: 0c to 70c ambient temperature. 3. i = industrial temperature range: ?40c to 85c ambient temperature.
v1.2 1-1 1 ? igloo plus device family overview general description the igloo plus family of flash fpgas, based on a 130 nm flash process, offers the lowest power fpga, a single-chip solu tion, small-footprint packages, reprog rammability, and an abundance of advanced features. the flash*freeze technology used in igloo plus devices enables entering and ex iting an ultra- low-power mode that consumes as little as 5 w while retaining the de sign information, sram content, registers, and i/o states. flash*freeze technology si mplifies power ma nagement through i/o and clock management with rapid recovery to operation mode. the low power active capability (static idle) al lows for ultra-low-power consumption while the igloo plus device is completely functional in the system. this allows the igloo plus device to control system power management based on external inputs (e.g., scanni ng for keyboard stimulus) while consuming minimal power. nonvolatile flash technology gives igloo plus devices the advantage of being a secure, low- power, single-chip soluti on that is live at power-up (lapu) . igloo plus is reprogrammable and offers time-to-market benefits at an asic-level unit cost. these features enable designers to create high-den sity systems using existi ng asic or fpga design flows and tools. igloo plus devices offer 1 kbit of on-chip, repr ogrammable, nonvolatile fl ashrom storage as well as clock conditioning circuitry based on an integr ated phase-locked loop (pll). igloo plus devices have up to 125 k system gates, supp orted with up to 36 kbits of tr ue dual-port sram and up to 212 user i/os. the aglp030 devices have no pll or ram support. flash*freeze technology the igloo plus device offers unique flash*free ze technology, allowing th e device to enter and exit ultra-low-power flash*freeze mode. igloo pl us devices do not need additional components to turn off i/os or clocks while retaining the de sign information, sram content, registers, and i/o states. flash*freeze technology is combined wi th in-system programmabili ty, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. the ability of igloo pl us v2 devices to support a wide range of core and i/o voltages (1.2 v to 1.5 v) allows further reduction in powe r consumption, thus ac hieving the lowest total system power. during flash*freeze mode, each i/o can be set to the following configurations: hold previous state, tristate, or set as high or low. the availability of low-power mo des, combined with reprogrammabi lity, a single-chip and single- voltage solution, and availability of small-foot print, high-pin-count packages, make igloo plus devices the best fit fo r portable electronics. flash advantages low power igloo plus devices exhibit power ch aracteristics similar to those of an asic, making them an ideal choice for power-sensitive applications. igloo pl us devices have only a very limited power-on current surge and no hi gh-current transition period, both of which occur on many fpgas. igloo plus devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 v core voltage. low dynamic power consumption, combined with low static power consum ption and flash*freeze technology, gives the igloo plus device the lo west total system power offered by any fpga.
igloo plus device family overview 1-2 v1.2 security the nonvolatile, flash-based ig loo plus devices do not require a boot prom, so there is no vulnerable external bitstream that can be easily copied. igloo pl us devices incorporate flashlock, which provides a unique combination of reprogra mmability and design se curity without external overhead, advantages that only an fpga wi th nonvolatile flash programming can offer. igloo plus devices (except aglp030) utilize a 128- bit flash-based lock and a separate aes key to secure programmed intellectual property and configuration data. in addition, all flashrom data in igloo plus devices can be encrypted prior to loading, using the industry-leading aes-128 (fips192) bit block cipher encryption standard. aes was adopted by the national institute of standards and technology (nist) in 2000 and repl aces the 1977 des standard. igloo plus devices have a built-in aes decryption engine and a flash-based aes key that make them the most comprehensive programmable logic de vice security solution availa ble today. igloo plus devices with aes-based security allow for secure, remote field updates over public networks such as the internet, and ensure that valuable ip remains out of the hands of system overbuilders, system cloners, and ip thieves. the contents of a prog rammed igloo plus device cannot be read back, although secure design verificati on is possible. security, built into the fpga fabr ic, is an inherent component of the igloo plus family. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely diff icult. the igloo plus fa mily, with flashlock and aes security, is unique in being highly resistant to bo th invasive and noninvasive attacks. your valuable ip is protected and se cure, making remote isp possible. an igloo plus device provides the most impenetrable security for programmable logic designs. single chip flash-based fpgas store their configuration information in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga structure, and no external configuration data needs to be loaded at system power-up (u nlike sram-based fpgas). therefore, flash-based igloo plus fpgas do not require system conf iguration components such as eeproms or microcontrollers to load device configuration da ta. this reduces bill-of-materials costs and pcb area, and increases securi ty and system reliability. the igloo plus devices can be oper ated with a 1.2 v or 1.5 v sing le-voltage supply for core and i/os, eliminating the need for additional supp lies while minimizing to tal power consumption. live at power-up the actel flash-based igloo plus devices support le vel 0 of the lapu classification standard. this feature helps in system component initialization, executio n of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock genera tion, and bus activity management. the lapu feature of flash-based ig loo plus devices greatly simplifies total system design and reduces tota l system cost, often eliminating the need for cplds and clock generation plls. in addition, glitches and brownouts in syste m power will not corrupt the igloo plus device's flash configuration, and unlike sr am-based fpgas, the device will not have to be reloaded when system power is restored. this enables the reduction or complete removal of the configuration prom, expensive voltage monitor, brownout detection, and clock generator de vices from the pcb design. flash-based igloo plus devices simplify total system design and reduce cost and design risk while increasing system reliability an d improving system initialization time. igloo plus flash fpgas allow the user to quickl y enter and exit flash*freeze mode. this is done almost instantly (within 1 s), an d the device retains configuratio n and data in registers and ram. unlike sram-based fpgas, the device does not need to reload configuration and design state from external memory components; instead, it retain s all necessary information to resume operation immediately. reduced cost of ownership advantages to the designer extend beyond lo w unit cost, performance, and ease of use. unlike sram-based fpgas, flash-based ig loo plus devices allow all functi onality to be live at power-up; no external boot prom is required. on-board security mechanisms prevent access to all the programming information an d enable secure remote updates of the fpga logic. designers can perform secure remote in-system reprogramming to supp ort future design iterations and field
igloo plus low-power flash fpgas v1.2 1-3 upgrades with confidence that valuable intellec tual property cannot be compromised or copied. secure isp can be performed usin g the industry-standard aes algo rithm. the igloo plus family device architecture mitigates the need for asic mi gration at higher user volumes. this makes the igloo plus family a cost-effective asic replacem ent solution, espe cially for applic ations in the consumer, networking/communications, computing, and avionics markets. firm-error immunity firm errors occur most commonly when high-energ y neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energy of the coll ision can change the state of the configuration cell and thus change the logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prev ent in sram fpgas. the consequenc e of this type of error can be a complete system failure. firm errors do not exist in the configuration memory of igloo plus flash-based fpgas. once it is programmed, the flash cell configuration element of igloo plus fpgas cannot be altered by high -energy neutrons and is therefor e immune to them. recoverable (or soft) errors occur in the user data sram of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. advanced flash technology the igloo plus family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130 nm lvcmos process with seven layers of metal. standard cmos design techniques are used to implement logic and control functions. the combination of fine granularity, enhanced flexible routing reso urces, and abundant flash switches allows for very high logic utilization without compromising devi ce routability or perfo rmance. logi c functions within the device are interconnected through a four-level routing hierarchy. igloo plus family fpgas utilize design and process techniques to minimize power consumption in all modes of operation. advanced architecture the proprietary igloo plus architecture provides granularity comparable to standard-cell asics. the igloo plus device consists of five dist inct and programmable architectural features ( figure 1-1 on page 1-4 ): ? flash*freeze technology ? fpga versatiles ? dedicated flashrom ? dedicated sram/fifo memory ? ? extensive cccs and plls ? ? advanced i/o structure the fpga core consists of a sea of versatiles. ea ch versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnectio ns. the versatility of the igloo plus core tile as either a three-input lookup table (lut) equivalent or a d-flip-flop/latc h with enable allows for efficient use of the fpga fabric. the versatile capability is unique to the actel proasic family of third-generation- architecture flash fpgas. versatiles are connected wi th any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming . maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circ uitry allows for rapid, single-voltage (3.3 v) programming of igloo plus device s via an ieee 1532 jtag interface. ? the aglp030 device does not support pll or sram.
igloo plus device family overview 1-4 v1.2 flash*freeze technology the igloo plus device has an ultra-low-power static mode, called flash*freeze mode, which retains all sram and register in formation and can still quickl y return to normal operation. flash*freeze technology enables the user to quickl y (within 1 s) enter and exit flash*freeze mode by activating the flash*freeze pin while all powe r supplies are kept at their original values. in addition, i/os and global i/os can still be driv en and can be toggling without impact on power consumption, clocks can still be driven or can be toggling with out impact on power consumption, and the device retains all core registers, sram in formation, and i/o states. i/os can be individually configured to either hold th eir previous state or be trista ted during flash*freeze mode. alternatively, they can be set to a certain stat e using weak pull-up or pull-down i/o attribute configuration. no power is consumed by the i/o banks, clocks, jtag pins, or pll, and the device consumes as little as 5 w in this mode. flash*freeze technology allows the user to switch to ac tive mode on demand, thus simplifying the power management of the device. the flash*freeze pin (active low) can be routed inte rnally to the core to allow the user's logic to decide when it is safe to tra nsition to this mode. refer to figure 1-2 for an illustration of entering/exiting flash*free ze mode. it is also possible to use the flash*freeze pin as a regular i/o if flash*freeze mode usage is not planned. * not supported by aglp030 devices figure 1-1 ? igloo plus device architecture overview with four i/o banks (aglp030, aglp060, and aglp125) ram block 4,608-bit dual-port sram or fifo block* versatile ccc i/os isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps bank 0 bank 1 bank 1 bank 3 bank 3 bank 2 * figure 1-2 ? igloo plus flash*freeze mode a c tel i g loo plu s fp g a flash * freeze mo d e c ontrol flash * freeze pin
igloo plus low-power flash fpgas v1.2 1-5 versatiles the igloo plus core consists of versatiles, which have been enhanced beyond the proasic plus ? core tiles. the igloo plus ve rsatile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set refer to figure 1-3 for versatile configurations. user nonvolatile flashrom actel igloo plus devices have 1 kbit of on-chip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business mode ls (for example, set-top boxes) ? secure key storage for secu re communicati ons algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using the standard ig loo plus ieee 1532 jtag programming interface. the core can be individually pr ogrammed (erased and written), an d on-chip aes decryption can be used selectively to securely load data over pu blic networks (except in aglp030 devices), as in security keys stored in the flashrom for a user design. the flashrom can be programmed via the jtag pr ogramming interf ace, and its contents can be read back either throug h the jtag programming interface or vi a direct fpga core addressing. note that the flashrom can only be programmed fro m the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bi ts; however, reading is performed on a byte-by- byte basis using a synchronous interface. a 7-bit address from the fpga core defines which of the 8 banks and which of the 16 bytes within that ba nk are being read. the th ree most sign ificant bits (msbs) of the flashrom address determine the bank , and the four least sign ificant bits (lsbs) of the flashrom address define the byte. the actel igloo plus developm ent software solu tions, libero ? integrated design environment (ide) and designer, have extensive support for th e flashrom. one such feature is auto-generation of sequential programmin g files for applicat ions requiring a unique se rial number in each part. another feature allows the inclusion of static data for system version control. data for the flashrom can be generated quickl y and easily using actel libero ide and designer software tools. comprehensive programming file su pport is also included to allo w for easy programming of large numbers of parts with di ffering flashrom contents. figure 1-3 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
igloo plus device family overview 1-6 v1.2 sram and fifo igloo plus devices (except aglp030 devices) have embedd ed sram blocks along their north side. each variable-aspect-ratio sram block is 4,608 bi ts in size. available memo ry configurations are 25618, 5129, 1k4, 2k2, and 4k1 bits. the indi vidual blocks have independent read and write ports that can be configured with different bit widths on each port. for example, data can be sent through a 4-bit port and read as a single bitstream. the embedded sram blocks can be initialized via the device jtag port (rom emulation mo de) using the ujtag macro (except in aglp030 devices). in addition, every sram block has an embedded fifo control unit. the control unit allows the sram block to be configured as a synchronous fi fo without using additional core versatiles. the fifo width and depth are programmable. the fifo also features programmable almost empty (aempty) and almost full (afull) flags in additi on to the normal empt y and full flags. the embedded fifo control unit cont ains the counters necessary for ge neration of the read and write address pointers. the embedded sram /fifo blocks can be cascaded to create larger configurations. pll and ccc igloo plus devices provide designers with very flexible clock conditioning circuit (ccc) capabilities. each member of the igloo plus family contains six cccs. one ccc (center west side) has a pll. the aglp030 device does not have a pll or cccs; it contains only inputs to six globals. the six ccc blocks are located at the four corners and th e centers of the east and west sides. one ccc (center west side) has a pll. the four corner cccs and the east ccc allow simp le clock delay operations as well as clock spine access. the inputs of the six ccc blocks are accessible from the fpga core or fro m one of several inputs located near the ccc that have dedicated connections to the ccc block. the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz up to 250 mhz ? output frequency range (f out_ccc ) = 0.75 mhz up to 250 mhz ? 2 programmable delay types for clock skew minimization ? clock frequency synthesis (for pll only) additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270 . output phase shift depends on the output divider configuration (for pll only). ? output duty cycle = 50 % 1.5 % or better (for pll only) ? low output jitter: worst case < 2.5 % clock period peak-to-peak period jitter when single global network used (for pll only) ? maximum acquisition time is 300 s (for pll only) ? exceptional tolerance to input period jitter?allowable input jitter is up to 1.5 ns (for pll only) ? four precise phases; maximum misalignment be tween adjacent phases of 40 ps 250 mhz / f out_ccc (for pll only) global clocking igloo plus devices have extensive support for mult iple clocking domains. in addition to the ccc and pll support described above, there is a co mprehensive global cloc k distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the ve rsanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-s kew clock signals or for rapid distribution of high-fanout nets.
igloo plus low-power flash fpgas v1.2 1-7 i/os with advanced i/o standards the igloo plus family of fpgas features a flexib le i/o structure, supporti ng a range of voltages (1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v). igloo pl us fpgas support many different i/o standards. the i/os are organized into four banks. all devices in igloo plus have four banks. the configuration of these banks determ ines the i/o standards supported. each i/o module contains several input, output, and output enable registers. part number and revision date part number 51700102-001-2 revised august 2008 list of changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current version (v1.2) page v1.1 (july 2008) the vq128 and vq176 packages were added to table 1-1 igloo plus product family , the "i/os per package1" table, table 1-2 package dimensions , "igloo plus orde ring information" , and the "temperature grade offerings" table. i to iv v1.0 (march 2008) as a result of the libero ide v8.4 re lease, actel now offers a wide range of core voltage support. th e document was updated to change 1.2 v / 1.5 v to 1.2 v to 1.5 v. n/a
igloo plus device family overview 1-8 v1.2 datasheet categories categories in order to provide the latest information to desi gners, some datasheets are published before data has been fully characterized. datasheets are designated as "product brief," "advance," "preliminary," and "production." the definiti on of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advance or production) and contains general product information. this document give s an overview of specific device and family information. advance this version contains initial estimated information based on simulation, ot her products, devices, or speed grades. this information can be used as estimates, but not for production. this label only applies to the dc and switching characteristics chapte r of the datasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on si mulation and/or initia l characterization. the information is believed to be co rrect, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this do cument are subject to the expo rt administration regulations (ear). they could require an ap proved export license prior to export from the united states. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status document may not have completed actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. it is the responsibility of each customer to ensure the fitn ess of any actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. consult actel?s terms and cond itions for specific liability exclusions relating to life-support applications. a reliabilit y report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for addi tional reliability information.
advance v0.4 2-1 2 ? igloo plus dc and switching characteristics general specifications dc and switching characteristic s for ?f speed grade targets ar e based only on simulation. the characteristics provided fo r the ?f speed grade are subject to change after establishing fpga specifications. some restrict ions might be added and will be reflected in future revisions of this document. the ?f speed grade is only supported in th e commercial temperature range. operating conditions stresses beyond those listed in table 2-1 may cause permanent damage to the device. exposure to absolute maximum rati ng conditions for extended period s may affect device reliability. absolute maximum ratings are stress ratings only; fu nctional operation of the device at these or any other conditions beyond those listed unde r the recommended operat ing conditions specified in table 2-2 on page 2-2 is not implied. table 2-1 ? absolute maxi mum ratings symbol parameter limits units v cc dc core supply vo ltage ?0.3 to 1.65 v v jtag jtag dc voltage ?0.3 to 3.75 v v pump programming voltag e ?0.3 to 3.75 v v ccpll analog power supply (pll) ?0.3 to 1.65 v v cci dc i/o buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (v cci + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot-insertion mode is disabled) v t stg 2 storage temperature ?65 to +150 c t j 2 junction temperature +125 c notes: 1. the device should be operated with in the limits specified by the datash eet. during transi tions, the input signal may undershoot or overshoot according to the limits shown in table 2-4 on page 2-3 . 2. for flash programming and rete ntion maximum limits, refer to table 2-3 on page 2-2 , and for recommended operatin g limits, refer to table 2-2 on page 2-2 .
igloo plus dc and switching characteristics 2-2 advance v0.4 table 2-2 ? recommended operating conditions 4 symbol parameter commercial industrial units t a ambient temperature 0 to +70 6 ?40 to +85 7 c t j junction temperature 8 0 to + 85 ?40 to +100 c v cc 3 1.5 v dc core supply voltage 1 1.425 to 1.575 1.425 to 1.575 v 1.2 v?1.5 v wide range core voltage 2 1.14 to 1.575 1.14 to 1.575 v v jtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v v pump 5 programming voltage programming mode 3.15 to 3.45 3.15 to 3.45 v operation 0 to 3.45 0 to 3.45 v v ccpll 9 analog power supply (pll) 1. 5 v dc core supply voltage 1 1.4 to 1.6 1.4 to 1.6 v 1.2 v?1.5 v wide range core voltage 2 1.14 to 1.575 1.14 to 1.575 v v cci 1.2 v dc supply voltage 2 1.14 to 1.26 1.14 to 1.26 v 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1. 7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2. 3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3. 0 to 3.6 3.0 to 3.6 v notes: 1. for igloo ? plus v5 devices 2. for igloo plus v2 devices only, operating at v cci v cc 3. the ranges given here are for po wer supplies only. the recommended input voltage ranges specific to each i/o standard are given in table 2-20 on page 2-19 . v cci should be at the same voltage within a given i/o bank. 4. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 5. v pump can be left floating during operation (not programming mode). 6. maximum t j = 85c. 7. maximum t j = 100c. 8. to ensure targeted reliability standards are met across ambient and junction operating temperatures, actel recommends that the user follow best design practices using actel?s ti ming and power simulation tools. 9. v ccpll pins should be tied to v cc pins. see pin descriptions for further information. table 2-3 ? flash programming limits ? retention, storage, and operating temperature 1 product grade programming cycles program retention (biased/unbiased) maximum storage temperature t stg (c) 2 maximum operat ing junction temperature t j (c) 2 commercial 500 20 years 110 100 industrial 500 20 years 110 100 notes: 1. this is a stress rating only; functional operation at any condition other than t hose indicated is not implied. 2. these limits apply for program/ data retention only. refer to table 2-1 on page 2-1 and table 2-2 for device operating conditions and absolute limits.
igloo plus dc and switching characteristics advance v0.4 2-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is designed into every igloo plus device. these circuits ensure eas y transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any se quence with minimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-1 on page 2-4 . there are five regions to consider during power-up. igloo plus i/os are activate d only if all of the followi ng three conditions are met: 1. v cc and v cci are above the minimum specified trip points ( figure 2-1 and figure 2-2 on page 2-5 ). 2. v cci > v cc ? 0.75 v (typical) 3. chip is in the operating mode. v cci trip point: ramping up (v5 devices): 0.6 v < trip_point_up < 1.2 v ramping down (v5 devices): 0.5 v < trip_point_down < 1.1 v ramping up (v2 devices): 0.75 v < trip_point_up < 1.05 v ramping down (v2 devices): 0.65 v < trip_point_down < 0.95 v v cc trip point: ramping up (v5 devices): 0.6 v < trip_point_up < 1.1 v ramping down (v5 devices): 0.5 v < trip_point_down < 1.0 v ramping up (v2 devices): 0.65 v < trip_point_up < 1.05 v ramping down (v2 devices): 0.55 v < trip_point_down < 0.95 v v cc and v cci ramp-up trip points are about 100 mv hi gher than ramp-dow n trip points. this specifically built-in hysteresis pr events undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tri stated and weakly pulled up to v cci . ? jtag supply, pll power supplies, and charge pump v pump supply have no influence on i/o behavior. table 2-4 ? overshoot and undershoot limits 1 v cci average v cci ?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10 % 1.4 v 5 % 1.49 v 3 v 10 % 1.1 v 5 % 1.19 v 3.3 v 10 % 0.79 v 5 % 0.88 v 3.6 v 10 % 0.45 v 5 % 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one out of six clock cycles. if the ove rshoot/undershoot occurs at one out of two cycles, the maximum overshoot/unders hoot has to be reduced by 0.15 v.
igloo plus dc and switching characteristics 2-4 advance v0.4 pll behavior at br ownout condition actel recommends using monotonic power supplies or voltage regula tors to ensure proper power- up behavior. power ramp-up should be monotonic at least until v cc and v ccplx exceed brownout activation levels (see figure 2-1 and figure 2-2 on page 2-5 for more details). when pll power supply voltage and/or v cc levels drop below the v cc brownout levels (0.75 v 0.25 v for v5 devices, and 0.75 v 0.2 v for v2 devices), the pll output lock signal goes low and/or the output clock is lost. refer to the "brownout voltage" section in the power-up/-down behavior of low-pow er flash devices chapter of the proasic3 and proasic3e handbooks for information on clock and lock recovery. internal power-up activation sequence 1. core 2. input buffers 3. output buffers, after 200 ns de lay from input buffer activation to make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns from input buff er to output buffer in your design. figure 2-1 ? v5 devices ? i/o state as a function of v cci and v cc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v v cc v cc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification. v cc = v cci + vt
igloo plus dc and switching characteristics advance v0.4 2-5 figure 2-2 ? v2 devices ? i/o state as a function of v cci and v cc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.14 v,1.425 v, 1.7 v, 2.3 v, or 3.0 v v cc v cc = 1.14 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.2 v d eactivation trip point: v d = 0.75 v 0.2 v activation trip point: v a = 0.9 v 0.15 v deactivation trip point: v d = 0.8 v 0.15 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification. v cc = v cci + vt
igloo plus dc and switching characteristics 2-6 advance v0.4 thermal characteristics introduction the temperature variable in the actel designer software refers to the junction temperature, not the ambient temperature. this is an important distinction be cause dynamic and static power consumption cause the chip junction temperatur e to be higher than the ambient temperature. eq 2-1 can be used to calculate junction temperature. t j = junction temperature = t + t a eq 2-1 where: t a = ambient temperature t = temperature gradient between junction (silicon) and ambient t = ja * p ja = junction-to-ambient of the package. ja numbers are located in figure 2-5 . p = power dissipation package thermal characteristics the device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja . the thermal characteristics for ja are shown for two air flow rates. the maximum operating junction te mperature is 100c. eq 2-2 shows a sample calculation of the maximum operating power dissipation allowed for a 484-pi n fbga package at commercial temperature and in still air. eq 2-2 temperature and voltage derating factors maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -------- 100 c70 c ? 20.5c/w ------------------------------------ 1 . 4 6 w = = = table 2-5 ? package thermal resistivities package type pin count jc ja units still air 200 ft./ min. 500 ft./ min. chip scale package (c sp) 201 tbd tbd tbd tbd c/w 281 tbd tbd tbd tbd c/w 289 tbd tbd tbd tbd c/w table 2-6 ? temperature and voltage derating factor s for timing delays (normalized to t j = 70c, v cc =1.425v) for igloo plus v2 or v5 devices, 1.5 v dc core supply voltage array voltage v cc (v) junction temperature (c) ?40c 0c 25c 70c 85c 110c 1.425 0.95 0.97 0.98 1.00 1.01 1.02 1.5 0.870.890.900.920.930.94 1.575 0.81 0.83 0.84 0.86 0.87 0.87
igloo plus dc and switching characteristics advance v0.4 2-7 calculating power dissipation quiescent supply current quiescent supply current (i dd ) calculation depends on multiple factors, including operating voltages (v cc , v cci , and v jtag ), operating temperature, syste m clock frequency, and power mode usage. actel recommends using the power calculat or and smartpower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. table 2-7 ? temperature and voltage derating factor s for timing delays (normalized to t j = 70c, v cc =1.14v) for igloo plus v2, 1.2 v dc core supply voltage array voltage v cc (v) junction temperature (c) ?40c 0c 25c 70c 85c 110c 1.14 0.97 0.98 0.99 1.00 1.01 1.01 1.2 0.860.870.880.890.890.90 1.26 0.79 0.80 0.81 0.81 0.82 0.82 table 2-8 ? quiescent supply current (i dd ) characteristics, igloo plus flash*freeze mode* core voltage aglp030 aglp060 aglp125 units typical (25c) 1.2 v 4 8 13 a 1.5 v 6 10 18 a * i dd includes v cc , v pump , v cci , v jtag , and v ccpll currents. table 2-9 ? quiescent supply current (i dd ) characteristics, igloo plus sleep mode (v cc = 0 v)* core voltage aglp030 aglp060 aglp125 units v cci /v jtag = 1.2 v (per bank) typical (25c) 1.2 v 1.7 1.7 1.7 a v cci /v jtag = 1.5 v (per bank) typical (25c) 1.2 v / 1.5 v 1.8 1.8 1.8 a v cci /v jtag = 1.8 v (per bank) typical (25c) 1.2 v / 1.5 v 1.9 1.9 1.9 a v cci /v jtag = 2.5 v (per bank) typical (25c) 1.2 v / 1.5 v 2.2 2.2 2.2 a v cci /v jtag = 3.3 v (per bank) typical (25c) 1.2 v / 1.5 v 2.5 2.5 2.5 a * i dd includes v cc , v pump , and v ccpll currents. table 2-10 ? quiescent supply current (i dd ) characteristics, igloo plus shutdown mode (v cc , v cci = 0 v)* core voltage aglp030 aglp060 aglp125 units typical (25c) 1.2 v / 1.5 v 0 0 0 a * i dd includes v cc , v pump , v cci , v jtag , and v ccpll currents.
igloo plus dc and switching characteristics 2-8 advance v0.4 power per i/o pin table 2-11 ? quiescent supply current (i dd ), no igloo plus flash*freeze mode 1 core voltage aglp030 aglp060 aglp125 units i cca current 2 typical (25c) 1.2 v 6 10 13 a 1.5 v 16 20 28 a i cci or i jtag current 3 v cci / v jtag = 1.2 v (per bank) typical (25c) 1.2 v 1.7 1.7 1.7 a v cci / v jtag = 1.5 v (per bank) typical (25c) 1.2 v / 1.5 v 1.8 1.8 1.8 a v cci / v jtag = 1.8 v (per bank) typical (25c) 1.2 v / 1.5 v 1.9 1.9 1.9 a v cci / v jtag = 2.5 v (per bank) typical (25c) 1.2 v / 1.5 v 2.2 2.2 2.2 a v cci / v jtag = 3.3 v (per bank) typical (25c) 1.2 v / 1.5 v 2.5 2.5 2.5 a notes: 1. to calculate total device i dd , multiply the number of banks used by i cci and add i cca contribution. 2. includes v cc , v ccpll , and v pump currents. 3. per v cci or v jtag bank table 2-12 ? summary of i/o input buffer power (per pin) ? default i/o software settings v cci (v) dynamic power p ac9 (w/mhz) 1 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 16.88 3.3 v lvttl / 3.3 v lvcmos ? schmitt trigger 3.3 19.54 2.5 v lvcmos 2.5 5.20 2.5 v lvcmos ? schmitt trigger 2.5 6.60 1.8 v lvcmos 1.8 2.22 1.8 v lvcmos ? schmitt trigger 1.8 2.29 1.5 v lvcmos (jesd8-11) 1.5 1.57 1.5 v lvcmos (jesd8-11) ? schmitt trigger 1.5 1.49 1.2 v lvcmos 2 1.2 0.55 1.2 v lvcmos 2 ? schmitt trigger 1.2 0.47 notes: 1. p ac9 is the total dynamic power measured on v cci . 2. applicable to igloo plus v2 devices only.
igloo plus dc and switching characteristics advance v0.4 2-9 power consumption of vari ous internal resources table 2-13 ? summary of i/o output buffer power (p er pin) ? default i/o software settings 1 c load (pf) v cci (v) dynamic power p ac10 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 5 3.3 128.60 2.5 v lvcmos 5 2.5 72.14 1.8 v lvcmos 5 1.8 36.94 1.5 v lvcmos (jesd8-11) 5 1.5 25.65 1.2 v lvcmos 3 51.2 15.22 notes: 1. dynamic power consumption is given for standard lo ad and software default drive strength and output slew. 2. p ac10 is the total dynamic power measured on v cci . 3. applicable for igloo plus v2 devices only. table 2-14 ? different components contributing to dynamic power consumption in igloo plus devices for igloo plus v2 or v5 device s, 1.5 v core supply voltage parameter definition device specific dynamic power (w/mhz) aglp125 aglp060 aglp030 p ac1 clock contribution of a global rib 11.03 9.3 9.3 p ac2 clock contribution of a global spine 0.81 0.81 0.41 p ac3 clock contribution of a versatile row 0.81 p ac4 clock contribution of a versatile used as a sequential module 0.11 p ac5 first contribution of a versatile used as a sequential module 0.057 p ac6 second contribution of a versatile used as a sequential module 0.207 p ac7 contribution of a versatile used as a combinatorial module 0.17 p ac8 average contribution of a routing net 0.7 p ac9 contribution of an i/o inpu t pin (standard-dependent) see table 2-12 on page 2-8 . p ac10 contribution of an i/o output pin (standard-dependent) see table 2-13 . p ac11 average contribution of a ram bl ock during a read operation 25.00 p ac12 average contribution of a ram bl ock during a write operation 30.00 p ac13 dynamic contribution for pll 2.70
igloo plus dc and switching characteristics 2-10 advance v0.4 table 2-15 ? different components contributing to the static power consumption in igloo plus devices for igloo plus v2 or v5 device s, 1.5 v core supply voltage parameter definition device -specific static power (mw) aglp125 aglp060 aglp030 p dc1 array static power in active mode see table 2-11 on page 2-8 p dc2 array static power in static (idle) mode see table 2-11 on page 2-8 p dc3 array static power in flash*freeze mode see table 2-8 on page 2-7 p dc4 2 static pll contribution 1.84 p dc5 bank quiescent power (v cci -dependent) see table 2-11 on page 2-8 notes: 1. for a different output load, drive strength, or slew rate, actel recommends using the actel power spreadsheet calculator or the sm artpower tool in actel libero ? integrated design environment (ide). 2. minimum contribution of the pll when running at lowest frequency. table 2-16 ? different components contributing to dynamic power consumption in igloo plus devices for igloo plus v2 devices, 1.2 v core supply voltage parameter definition device-specific dynamic power (w/mhz) aglp125 aglp060 aglp030 p ac1 clock contribution of a global rib 7.07 5.96 5.96 p ac2 clock contribution of a global spine 0.52 0.52 0.26 p ac3 clock contribution of a versatile row 0.52 p ac4 clock contribution of a versatile used as a sequential module 0.07 p ac5 first contribution of a versatile used as a sequential module 0.045 p ac6 second contribution of a versatil e used as a sequential module 0.186 p ac7 contribution of a versatile used as a combinatorial module 0.11 p ac8 average contribution of a routing net 0.45 p ac9 contribution of an i/o input pin (standard-dependent) see table 2-12 on page 2-8 p ac10 contribution of an i/o output pin (standard-dependent) see table 2-13 on page 2-9 p ac11 average contribution of a ram block during a read operation 25.00 p ac12 average contribution of a ram block during a write operation 30.00 p ac13 dynamic contribution for pll 2.10
igloo plus dc and switching characteristics advance v0.4 2-11 table 2-17 ? different components contributing to the static power consumption in igloo plus devices for igloo plus v2 devices, 1.2 v core supply voltage parameter definition device-specific static power (mw) aglp125 aglp060 aglp030 p dc1 array static power in active mode see table 2-11 on page 2-8 p dc2 array static power in static (idle) mode see table 2-11 on page 2-8 p dc3 array static power in flash*freeze mode see table 2-8 on page 2-7 p dc4 2 static pll co ntribution 0.90 p dc5 bank quiescent power ( v cci -dependent) see table 2-11 on page 2-8 notes: 1. for a different output load, drive strength, or slew rate, actel recommen ds using the actel power spreadsheet calculator or the sm artpower tool in actel libero ide. 2. minimum contribution of the pll when running at lowest frequency.
igloo plus dc and switching characteristics 2-12 advance v0.4 power calculation methodology this section describes a simplified method to estimate power consumptio n of an application. for more accurate and deta iled power estima tions, use the smartpower tool in actel libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number and the frequency of each output clock generated ? the number of combinatorial and se quential cells used in the design ?the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-18 on page 2-14 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-19 on page 2-14 . ? read rate and write rate to the memory?guide lines are provided for typical applications in table 2-19 on page 2-14 . the calculation should be repeat ed for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = (p dc1 or p dc2 or p dc3 ) + n banks * p dc5 n banks is the number of i/o bank s powered in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (p ac1 + n spine *p ac2 + n row *p ac3 + n s-cell * p ac4 ) * f clk n spine is the number of global spines used in the user design?guidelines are provided in table 2-18 on page 2-14 . n row is the number of versatile rows used in the design?guidelines are provided in table 2-18 on page 2-14 . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. p ac1 , p ac2 , p ac3 , and p ac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (p ac5 + 1 / 2 * p ac6 ) * f clk n s-cell is the number of versatiles used as se quential modules in the design. when a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-18 on page 2-14 . f clk is the global clock signal frequency.
igloo plus dc and switching characteristics advance v0.4 2-13 combinatorial cells contribution?p c-cell p c-cell = n c-cell * 1 / 2 * p ac7 * f clk n c-cell is the number of versatiles used as combinatorial modu les in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-18 on page 2-14 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * 1 / 2 * p ac8 * f clk n s-cell is the number of versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modu les in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-18 on page 2-14 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * 2 / 2 * p ac9 * f clk n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-18 on page 2-14 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * 2 / 2 * 1 * p ac10 * f clk n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle rate?guidelines are provided in table 2-18 on page 2-14 . 1 is the i/o buffer enable rate ?guidelines are provided in table 2-19 on page 2-14 . f clk is the global clock signal frequency. ram contribution?p memory p memory = p ac11 * n blocks * f read-clock * 2 + p ac12 * n block * f write-clock * 3 n blocks is the number of ram blocks used in the design. f read-clock is the memory read clock frequency. 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. 3 is the ram enable rate for write op erations?guidelines are provided in table 2-19 on page 2-14 . pll contribution?p pll p pll = p dc4 + p ac13 *f clkout f clkout is the output clock frequency. 1 1. if a pll is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (p ac13 * f clkout product) to the total pll contribution.
igloo plus dc and switching characteristics 2-14 advance v0.4 guidelines toggle rate definition a toggle rate defines the frequency of a net or logi c element relative to a clock. it is a percentage. if the toggle rate of a net is 100 % , this means that this net switch es at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100 % because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25 % : ? bit 0 (lsb) = 100 % ? bit 1 = 50 % ? bit 2 = 25 % ?? ? bit 7 (msb) = 0.78125 % ? average toggle rate = (100 % + 50 % + 25 % + 12.5 % + . . . + 0.78125 % ) / 8 enable rate definition output enable rate is the average percentage of time during which tris tate outputs are enabled. when nontristate output buffers are us ed, the enable rate should be 100 % . table 2-18 ? toggle rate guidelines reco mmended for power calculation component definition guideline 1 toggle rate of versatile outputs 10 % 2 i/o buffer toggle rate 10 % table 2-19 ? enable rate guidelines reco mmended for power calculation component definition guideline 1 i/o output buffer enable rate 100 % 2 ram enable rate for read operations 12.5 % 3 ram enable rate for write operations 12.5 %
igloo plus dc and switching characteristics advance v0.4 2-15 user i/o characteristics timing model figure 2-3 ? timing model operating conditions: std speed, commercial temperature range (t j = 70c), worst-case v cc = 1.425 v, for dc 1.5 v core voltage, applicable to v2 and v5 devices dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvcmos 2.5v output drive strength = 12 ma high slew rate input lvcmos 2.5 v lvcmos 1.5 v lvttl 3.3 v output drive strength = 12 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 4 ma high slew rate lvttl output drive strength = 12 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 1.40 ns t pd = 0.89 ns t dp = 1.62 ns t pd = 1.98 ns t dp = 1.62 ns t pd = 1.24 ns t dp = 1.70 ns t pd = 0.86 ns t dp = 2.07 ns t pd = 0.87 ns t py = 0.85 ns t clkq = 0.80 ns t oclkq = 0.89 ns t sud = 0.84 ns t osud = 0.18 ns t dp = 1.62 ns t py = 0.85 ns t py = 1.15 ns t clkq = 0.80 ns t sud = 0.84 ns t py = 0.85 ns t iclkq = 0.63 ns t isud = 0.18 ns t py = 1.06 ns
igloo plus dc and switching characteristics 2-16 advance v0.4 figure 2-4 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50 % 50 % v ih v cc v il t dout (r) din gnd t dout (f) 50 % 50 % v cc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f))
igloo plus dc and switching characteristics advance v0.4 2-17 figure 2-5 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) v trip v trip v oh v cc d 50 % 50 % v cc 0 v dout 50 % 50 % 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f))
igloo plus dc and switching characteristics 2-18 advance v0.4 figure 2-6 ? tristate output buffer timing model and delays (example) d clk q d clk q 10 % v cci t zl v trip 50 % t hz 90 % v cci t zh v trip 50 % 50 % t lz 50 % eout pad d e 50 % t eout (r) 50 % t eout (f) pad dout eout d i/o interface e t eout t zls v trip 50 % t zhs v trip 50 % eout pad d e 50 % 50 % t eout (r) t eout (f) 50 % v cc v cc v cc v cci v cc v cc v cc v oh v ol v ol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f))
igloo plus dc and switching characteristics advance v0.4 2-19 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-20 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 v lvcmos 8 ma high ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 8 8 1.5 v lvcmos 4 ma high ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 4 4 1.2 v lvcmos 2 2 ma high ?0.3 0.35 * v cci 0.65 * v cci 1.26 0.25 * v cci 0.75 * v cci 22 notes: 1. currents are measured at 85c junction temperature. 2. applicable to igloo plus v2 devices operating at v cci v cc table 2-21 ? summary of maximum and mi nimum dc input levels applicable to commercial and industrial conditions dc i/o standards commercial 1 industrial 2 i il i ih i il i ih a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 1.2 v lvcmos 3 10 10 15 15 notes: 1. commercial range (0c < t a < 70c) 2. industrial range (?40c < t a < 85c) 3. applicable to igloo plus v2 devices operating at v cci v cc
igloo plus dc and switching characteristics 2-20 advance v0.4 summary of i/o timing characteristics ? defaul t i/o software settings table 2-22 ? summary of ac measuring points standard measuring trip point (v trip ) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v 1.2 v lvcmos 0.60 v table 2-23 ? i/o ac paramete r definitions parameter parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer t dout data to output buffer delay through the i/o interface t eout enable to output buffer tristate control delay throug h the i/o interface t din input buffer to data dela y through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delaye d enable?z to low
igloo plus dc and switching characteristics advance v0.4 2-21 table 2-24 ? summary of i/o timing chara cteristics?software default settings, std speed grade, commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 5 pf ? 0.97 1.62 0.1 80.851.140.661.651.272.202.64 ns 2.5 v lvcmos 12 ma high 5 pf ? 0.97 1 .62 0.18 1.06 1.22 0.66 1.65 1.34 2.22 2.56 ns 1.8 v lvcmos 8 ma high 5 pf ? 0.97 1 .82 0.18 0.99 1.43 0.66 1.85 1.53 2.29 2.54 ns 1.5 v lvcmos 4 ma high 5 pf ? 0.97 2 .07 0.18 1.15 1.62 0.66 2.10 1.71 2.37 2.57 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-25 ? summary of i/o timing chara cteristics?software default settings, std speed grade, commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout t dp t din t py ) t pys t eout t zl t zh t lz t hz units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 5 pf ? 0.98 2.16 0.19 0.99 1.37 0.67 2.20 1.74 2.64 3.37 ns 2.5 v lvcmos 12 ma high 5 pf ? 0.98 2.13 0.19 1.20 1.40 0.67 2.17 1.77 2.65 3.25 ns 1.8 v lvcmos 8 ma high 5 pf ? 0.98 2.25 0.19 1.12 1.60 0.67 2.30 1.92 2.70 3.15 ns 1.5 v lvcmos 4 ma high 5 pf ? 0.98 2.48 0.19 1.26 1.79 0.67 2.52 2.10 2.77 3.14 ns 1.2 v lvcmos 2 2 ma high 5 pf ? 0.98 2.68 0.19 1.56 2.34 0.67 2.73 2.24 2.53 2.67 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. applicable to igloo plus v2 devices operating at v cci v cc .
igloo plus dc and switching characteristics 2-22 advance v0.4 detailed i/o dc characteristics table 2-26 ? input capacitance symbol definition conditions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf table 2-27 ? i/o output buffer maximum resistances 1 standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8m a 50 150 12 ma 25 75 16 ma 25 75 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 1.2 v lvcmos 2 ma tbd tbd notes: 1. these maximum values are provided for informatio nal reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, an d process. for board design considerations and detailed output buffer resistances, use the corres ponding ibis models located on the actel website at http://www.actel.co m/download/ibi s/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec
igloo plus dc and switching characteristics advance v0.4 2-23 table 2-28 ? i/o weak pull-up/pull-down resistances minimum and maximum we ak pull-up/pull-down resistance values v cci r (weak pull-up) 1 ( ) r (weak pull-down) 2 ( ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k 1.2 v tbd tbd tbd tbd notes: 1. r (weak pull-up-max) = (v olspec ) / i (weak pull-up-min) 2. r (weak pull-up-max) = (v ccimax ? v ohspec ) / i (weak pull-up-min) table 2-29 ? i/o short currents i osh /i osl drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 25 27 4 ma 25 27 6 ma 51 54 8 ma 51 54 12 ma 103 109 16 ma 103 109 2.5 v lvcmos 2 ma 16 18 4 ma 16 18 6 ma 32 37 8 ma 32 37 12 ma 65 74 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 6 ma 35 44 8 ma 35 44 1.5 v lvcmos 2 ma 13 16 4 ma 25 33 1.2 v lvcmos 2 ma tbd tbd * t j = 100c
igloo plus dc and switching characteristics 2-24 advance v0.4 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 12 ma i/o setting, which is the worst case for this type of analysis. for example, at 110c, the short current condition would have to be sustain ed for more than three months to cause a reliability concern. the i/o desi gn does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-30 ? duration of shor t circuit event before failure temperature time before failure ?40c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months 110c 3 months table 2-31 ? schmitt trigger input hysteresis hysteresis voltage value (typ.) for schmitt mode input buffers input buffer configuration hysteresis value (typ.) 3.3 v lvttl/lvcmos (schmi tt trigger mode) 240 mv 2.5 v lvcmos (schmitt trigger mode) 140 mv 1.8 v lvcmos (schmi tt trigger mode) 80 mv 1.5 v lvcmos (schmi tt trigger mode) 60 mv 1.2 v lvcmos (schmi tt trigger mode) 40 mv table 2-32 ? i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos (schmitt trigger disabled) no requirement 10 ns * 20 years (100c) lvttl/lvcmos (schmitt trigger enabled) no requirement no requirement, but input noise voltage cannot exceed schmitt hysteresis. 20 years (100c) * the maximum input rise/fall time is related to th e noise induced into the input buffer trace. if the noise is low, then the rise ti me and fall time of input buffe rs can be increased beyond the maximum value. the longer the rise/fall times, th e more susceptible the input signal is to the board noise. actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
igloo plus dc and switching characteristics advance v0.4 2-25 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 2-33 ? minimum and maximum dc input and output levels 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 103 109 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 103 109 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-7 ? ac loading table 2-34 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.45 * measuring point = v trip. see table 2-22 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo plus dc and switching characteristics 2-26 advance v0.4 timing characteristics applies to 1.5 v dc core voltage table 2-35 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.97 3.33 0.18 0.85 1.14 0.66 3.39 2.95 1.82 1.87 ns 6 ma std 0.97 2.83 0.18 0.85 1.14 0.66 2.88 2.65 2.04 2.27 ns 8 ma std 0.97 2.83 0.18 0.85 1.14 0.66 2.88 2.65 2.04 2.27 ns 12 ma std 0.97 2.48 0.18 0.85 1.14 0.66 2.52 2.38 2.20 2.53 ns 16 ma std 0.97 2.48 0.18 0.85 1.14 0.66 2.52 2.38 2.20 2.53 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-36 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.97 1.84 0.18 0.85 1.14 0.66 1.88 1.43 1.81 1.98 ns 6 ma std 0.97 1.70 0.18 0.85 1.14 0.66 1.73 1.32 2.04 2.38 ns 8 ma std 0.97 1.70 0.18 0.85 1.14 0.66 1.73 1.32 2.04 2.38 ns 12 ma std 0.97 1.62 0.18 0.85 1.14 0.66 1.65 1.27 2.20 2.64 ns 16 ma std 0.97 1.62 0.18 0.85 1.14 0.66 1.65 1.27 2.20 2.64 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-27 applies to 1.2 v dc core voltage table 2-37 ? 3.3 v lvttl / 3.3 v lvcmos low slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.98 3.92 0.19 0.99 1.37 0.67 3.99 3.47 2.25 2.56 ns 6 ma std 0.98 3.40 0.19 0.99 1.37 0.67 3.47 3.15 2.48 2.97 ns 8 ma std 0.98 3.40 0.19 0.99 1.37 0.67 3.47 3.15 2.48 2.97 ns 12 ma std 0.98 3.04 0.19 0.99 1.37 0.67 3.10 2.88 2.64 3.24 ns 16 ma std 0.98 3.04 0.19 0.99 1.37 0.67 3.10 2.88 2.64 3.24 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-38 ? 3.3 v lvttl / 3.3 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 3.0 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.98 2.39 0.19 0.99 1.37 0.67 2.43 1.91 2.24 2.68 ns 6 ma std 0.98 2.24 0.19 0.99 1.37 0.67 2.28 1.80 2.48 3.10 ns 8 ma std 0.98 2.24 0.19 0.99 1.37 0.67 2.28 1.80 2.48 3.10 ns 12 ma std 0.98 2.16 0.19 0.99 1.37 0.67 2.20 1.74 2.64 3.37 ns 16 ma std 0.98 2.16 0.19 0.99 1.37 0.67 2.20 1.74 2.64 3.37 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-28 advance v0.4 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. it uses a 5 v?tolerant input buffer and push-pull output buffer. table 2-39 ? minimum and maximum dc input and output levels 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 2.7 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 2.7 0.7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 2.7 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 2.7 0.7 1.7 8 8 32 37 10 10 12 ma ?0.3 0.7 1.7 2.7 0.7 1.7 12 12 65 74 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-8 ? ac loading table 2-40 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.25 * measuring point = v trip. see table 2-22 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo plus dc and switching characteristics advance v0.4 2-29 timing characteristics applies to 1.5 v dc core voltage table 2-41 ? 2.5 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.97 3.80 0.18 1.06 1.22 0.66 3.87 3.47 1.80 1.70 ns 6 ma std 0.97 3.21 0.18 1.06 1.22 0.66 3.27 3.11 2.05 2.17 ns 8 ma std 0.97 3.21 0.18 1.06 1.22 0.66 3.27 3.11 2.05 2.17 ns 12 ma std 0.97 2.80 0.18 1.06 1.22 0.66 2.85 2.79 2.22 2.48 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-42 ? 2.5 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.97 1.90 0.18 1.06 1.22 0.66 1.93 1.57 1.79 1.77 ns 6 ma std 0.97 1.73 0.18 1.06 1.22 0.66 1.76 1.42 2.04 2.25 ns 8 ma std 0.97 1.73 0.18 1.06 1.22 0.66 1.76 1.42 2.04 2.25 ns 12 ma std 0.97 1.62 0.18 1.06 1.22 0.66 1.65 1.34 2.22 2.56 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-30 advance v0.4 applies to 1.2 v dc core voltage table 2-43 ? 2.5 lvcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.98 4.37 0.19 1.20 1.40 0.67 4.45 3.95 2.21 2.35 ns 6 ma std 0.98 3.76 0.19 1.20 1.40 0.67 3.83 3.59 2.47 2.83 ns 8 ma std 0.98 3.76 0.19 1.20 1.40 0.67 3.83 3.59 2.47 2.83 ns 12 ma std 0.98 3.34 0.19 1.20 1.40 0.67 3.41 3.26 2.65 3.15 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-44 ? 2.5 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 2.3 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 4 ma std 0.98 2.42 0.19 1.20 1.40 0.67 2.46 2.01 2.21 2.44 ns 6 ma std 0.98 2.24 0.19 1.20 1.40 0.67 2.28 1.85 2.46 2.93 ns 8 ma std 0.98 2.24 0.19 1.20 1.40 0.67 2.28 1.85 2.46 2.93 ns 12 ma std 0.98 2.13 0.19 1.20 1.40 0.67 2.17 1.77 2.65 3.25 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-31 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-45 ? minimum and maximum dc input and output levels 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 4 4 17 22 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 6 6 35 44 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 1.9 0.45 v cci ? 0.45 8 8 35 44 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-9 ? ac loading table 2-46 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.95 * measuring point = v trip. see table 2-22 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo plus dc and switching characteristics 2-32 advance v0.4 timing characteristics applies to 1.5 v dc core voltage table 2-47 ? 1.8 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 5.11 0.18 0.99 1.43 0.66 5.20 4.48 1.78 1.30 ns 4 ma std 0.97 4.31 0.18 0.99 1.43 0.66 4.39 4.04 2.08 2.07 ns 6 ma std 0.97 3.78 0.18 0.99 1.43 0.66 3.85 3.63 2.29 2.46 ns 8 ma std 0.97 3.78 0.18 0.99 1.43 0.66 3.85 3.63 2.29 2.46 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-48 ? 1.8 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 2.21 0.18 0.99 1.43 0.66 2.25 1.86 1.78 1.35 ns 4 ma std 0.97 1.97 0.18 0.99 1.43 0.66 2.01 1.64 2.08 2.15 ns 6 ma std 0.97 1.82 0.18 0.99 1.43 0.66 1.85 1.53 2.29 2.54 ns 8 ma std 0.97 1.82 0.18 0.99 1.43 0.66 1.85 1.53 2.29 2.54 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-33 applies to 1.2 v dc core voltage table 2-49 ? 1.8 v lvcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 5.61 0.19 1.12 1.60 0.67 5.71 4.96 2.18 1.87 ns 4 ma std 0.98 4.80 0.19 1.12 1.60 0.67 4.89 4.50 2.49 2.67 ns 6 ma std 0.98 4.25 0.19 1.12 1.60 0.67 4.33 4.09 2.71 3.06 ns 8 ma std 0.98 4.25 0.19 1.12 1.60 0.67 4.33 4.09 2.71 3.06 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-50 ? 1.8 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.7 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 2.66 0.19 1.12 1.60 0.67 2.71 2.27 2.18 1.92 ns 4 ma std 0.98 2.41 0.19 1.12 1.60 0.67 2.46 2.04 2.49 2.75 ns 6 ma std 0.98 2.25 0.19 1.12 1.60 0.67 2.30 1.92 2.70 3.15 ns 8 ma std 0.98 2.25 0.19 1.12 1.60 0.67 2.30 1.92 2.70 3.15 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-34 advance v0.4 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-51 ? minimum and maximum dc input and output levels 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 2 2 13 16 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 1.575 0.25 * v cci 0.75 * v cci 4 4 25 33 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-10 ? ac loading table 2-52 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.50.755 * measuring point = v trip. see table 2-22 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo plus dc and switching characteristics advance v0.4 2-35 timing characteristics applies to 1.5 v dc core voltage table 2-53 ? 1.5 v lvcmos low slew ? applie s to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 5.47 0.18 1.15 1.62 0.66 5.57 4.89 2.13 2.02 ns 4 ma std 0.97 4.82 0.18 1.15 1.62 0.66 4.91 4.42 2.37 2.47 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-54 ? 1.5 v lvcmos high slew ? applies to 1.5 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.97 2.27 0.18 1.15 1.62 0.66 2.31 1.85 2.13 2.11 ns 4 ma std 0.97 2.07 0.18 1.15 1.62 0.66 2.10 1.71 2.37 2.57 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-36 advance v0.4 applies to 1.2 v dc core voltage table 2-55 ? 1.5 v lvcmos low slew ? applie s to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 5.94 0.19 1.26 1.79 0.67 6.05 5.36 2.53 2.58 ns 4 ma std 0.98 5.28 0.19 1.26 1.79 0.67 5.38 4.88 2.78 3.04 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-56 ? 1.5 v lvcmos high slew ? applies to 1.2 v dc core voltage commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.4 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 2.68 0.19 1.26 1.79 0.67 2.73 2.24 2.53 2.67 ns 4 ma std 0.98 2.48 0.19 1.26 1.79 0.67 2.52 2.10 2.77 3.14 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-37 1.2 v lvcmos (jesd8-12a) low-voltage cmos for 1.2 v comp lies with the lvcmos standard jesd8-12a for general purpose 1.2 v applications. it uses a 1.2 v inpu t buffer and a push-pull output buffer. table 2-57 ? minimum and maximum dc input and output levels 1.2 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 1.26 0.25 * v cci 0.75 * v cci 2 2 tbd tbd 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-11 ? ac loading table 2-58 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.20.65 * measuring point = v trip. see table 2-22 on page 2-20 for a complete table of trip points. test point test point enable path datapath 5 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz
igloo plus dc and switching characteristics 2-38 advance v0.4 timing characteristics applies to 1.2 v dc core voltage table 2-59 ? 1.2 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.14 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 8.28 0.19 1.56 2.34 0.67 3.24 2.76 3.00 3.25 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-60 ? 1.2 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v, worst-case v cci = 1.14 v drive strength speed grade t dout t dp t din t py t pys t eout t zl t zh t lz t hz units 2 ma std 0.98 2.68 0.19 1.56 2.34 0.67 2.73 2.24 2.53 2.67 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-39 i/o register specifications fully registered i/o buffers with asynchronous preset figure 2-12 ? timing model of registered i/o buffers with as ynchronous preset inbuf inbuf tribuf clkbuf inbuf clkbuf data input i/o register with: active high preset positive-edge triggered data output register and enable output register with: active high preset postive-edge triggered pad out clk preset data_out data eout dout clk dq dfn1p1 pre dq dfn1p1 pre dq dfn1p1 pre d_enable a c d e f h i j l y core array
igloo plus dc and switching characteristics 2-40 advance v0.4 table 2-61 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t opre2q asynchronous preset-to-q of th e output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the ou tput enable register j, h t oepre2q asynchronous preset-to-q of th e output enable register i, eout t oerempre asynchronous preset removal time fo r the output enable register i, h t oerecpre asynchronous preset recovery time for the output enab le register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t ipre2q asynchronous preset-to-q of the input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a * see figure 2-12 on page 2-39 for more information.
igloo plus dc and switching characteristics advance v0.4 2-41 fully registered i/o buffer s with asynchronous clear figure 2-13 ? timing model of the registered i/ o buffers with asynchronous clear clk pad out clk clr data_out data y aa eout dout core array dq dfn1c1 clr dq dfn1c1 clr dq dfn1c1 clr d_enable cc dd ee ff ll hh jj clkbuf inbuf trib uf inbuf clkbuf inbuf data input i/o register with active high clear positive-edge triggered data output register and enable output register with active high clear positive-edge triggered
igloo plus dc and switching characteristics 2-42 advance v0.4 table 2-62 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time fo r the output data register ll, hh t orecclr asynchronous clear reco very time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enab le register ii, hh t oerecclr asynchronous clear recove ry time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear reco very time for the inpu t data register dd, aa * see figure 2-13 on page 2-41 for more information.
igloo plus dc and switching characteristics advance v0.4 2-43 input register timing characteristics 1.5 v dc core voltage figure 2-14 ? input register timing diagram 50 % clear out_1 clk data preset 50 % t isud t ihd 50 % 50 % t iclkq 1 0 t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 2-63 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t iclkq clock-to-q of the inpu t data register 0.63 ns t isud data setup time for the input data register 0.18 ns t ihd data hold time for the input data register 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.46 ns t ipre2q asynchronous preset-to-q of th e input data register 0.46 ns t iremclr asynchronous clear removal time for the input data register 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.23 ns t irempre asynchronous preset removal time for the input data register 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.23 ns t iwclr asynchronous clear minimum pulse widt h for the input data register 0.19 ns t iwpre asynchronous preset minimum pulse wi dth for the input data register 0.19 ns t ickmpwh clock minimum pulse width high fo r the input data register 0.28 ns t ickmpwl clock minimum pulse width low fo r the input data register 0.31 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-44 advance v0.4 1.2 v dc core voltage table 2-64 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t iclkq clock-to-q of the inpu t data register 0.99 ns t isud data setup time for the input data register 0.29 ns t ihd data hold time for the input data register 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.68 ns t ipre2q asynchronous preset-to-q of the input data register 0.68 ns t iremclr asynchronous clear removal time for the input data register 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.24 ns t irempre asynchronous preset removal time for the input data register 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.24 ns t iwclr asynchronous clear minimum pulse widt h for the input data register 0.19 ns t iwpre asynchronous preset minimum pulse wi dth for the input data register 0.19 ns t ickmpwh clock minimum pulse width high fo r the input data register 0.28 ns t ickmpwl clock minimum pulse width low fo r the input data register 0.31 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-45 output register timing characteristics 1.5 v dc core voltage figure 2-15 ? output register timing diagram clear dout clk data_out preset 50 % t osud t ohd 50 % 50 % t oclkq 1 0 t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 2-65 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t oclkq clock-to-q of the output data register 0.89 ns t osud data setup time for the output data register 0.18 ns t ohd data hold time for the output data register 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 0.72 ns t opre2q asynchronous preset-to-q of th e output data register 0.78 ns t oremclr asynchronous clear removal time fo r the output data register 0.00 ns t orecclr asynchronous clear reco very time for the output data register 0.23 ns t orempre asynchronous preset removal time for the output data register 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.23 ns t owclr asynchronous clear minimu m pulse width for the output data register 0.19 ns t owpre asynchronous preset mini mum pulse width for the output data register 0.19 ns t ockmpwh clock minimum pulse width high for the output data register 0.28 ns t ockmpwl clock minimum pulse width low for the output data register 0.31 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-46 advance v0.4 1.2 v dc core voltage table 2-66 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t oclkq clock-to-q of the output data register 1.37 ns t osud data setup time for the output data register 0.22 ns t ohd data hold time for the output data register 0.00 ns t oclr2q asynchronous clear-to-q of the output data register 1.05 ns t opre2q asynchronous preset-to-q of th e output data register 1.14 ns t oremclr asynchronous clear removal time fo r the output data register 0.00 ns t orecclr asynchronous clear reco very time for the output data register 0.24 ns t orempre asynchronous preset removal time for the output data register 0.00 ns t orecpre asynchronous preset recovery time for the output data register 0.24 ns t owclr asynchronous clear minimu m pulse width for the output data register 0.19 ns t owpre asynchronous preset mini mum pulse width for the output data register 0.19 ns t ockmpwh clock minimum pulse width high for the output data register 0.28 ns t ockmpwl clock minimum pulse width low for the output data register 0.31 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-47 output enable register timing characteristics 1.5 v dc core voltage figure 2-16 ? output enable regist er timing diagram 50 % preset clear eout clk d_enable 50 % t oesud t oehd 50 % 50 % t oeclkq 1 0 t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 2-67 ? output enable regist er propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t oeclkq clock-to-q of th e output enable register 0.91 ns t oesud data setup time for the output enable register 0.18 ns t oehd data hold time for the ou tput enable register 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 0.74 ns t oepre2q asynchronous preset-to-q of th e output enable register 0.81 ns t oeremclr asynchronous clear removal time fo r the output enable register 0.00 ns t oerecclr asynchronous clear recovery time fo r the output enable register 0.23 ns t oerempre asynchronous preset removal time fo r the output enab le register 0.00 ns t oerecpre asynchronous preset recovery time for the output enab le register 0.23 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 ns t oewpre asynchronous preset minimum pulse widt h for the output enable register 0.19 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.28 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.31 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-48 advance v0.4 1.2 v dc core voltage table 2-68 ? output enable regist er propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t oeclkq clock-to-q of th e output enable register 1.40 ns t oesud data setup time for the output enable register 0.22 ns t oehd data hold time for the ou tput enable register 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 1.08 ns t oepre2q asynchronous preset-to-q of th e output enable register 1.19 ns t oeremclr asynchronous clear removal time for the output enable register 0.00 ns t oerecclr asynchronous clear recovery time fo r the output enable register 0.24 ns t oerempre asynchronous preset removal time fo r the output enab le register 0.00 ns t oerecpre asynchronous preset recovery time for the output enab le register 0.24 ns t oewclr asynchronous clear minimum pulse width for the output enable register 0.19 ns t oewpre asynchronous preset minimum pulse widt h for the output enable register 0.19 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.28 ns t oeckmpwl clock minimum pulse width low for the output enable register 0.31 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-49 versatile characteristics versatile specifications as a combinatorial module the igloo plus library offers all combinations of lut-3 combinatorial functions. in this section, timing characteristics are presented for a sample of the libr ary. for more details, refer to the fusion, igloo/e, and proasi c3/ e macro li brary guide . figure 2-17 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
igloo plus dc and switching characteristics 2-50 advance v0.4 figure 2-18 ? timing model and waveforms net a y b len g th = 1 versatile net a y b len g th = 1 versatile net a y b len g th = 1 versatile net a y b len g th = 1 versatile nand2 or any c om b inatorial lo g i c nand2 or any c om b inatorial lo g i c nand2 or any c om b inatorial lo g i c nand2 or any c om b inatorial lo g i c t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where e dg es are appli c a b le for a parti c ular c om b inatorial c ell fanout = 4 t pd t pd t pd 50% v cc v cc v cc 50% g nd a, b, c 50% 50% 50% (rr) (rf) g nd out out g nd 50% (ff) (fr) t pd t pd
igloo plus dc and switching characteristics advance v0.4 2-51 timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-69 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v combinatorial cell equation parameter std. units inv y = !a t pd 0.72 ns and2 y = a b t pd 0.86 ns nand2 y = !(a b) t pd 0.87 ns or2 y = a + b t pd 0.89 ns nor2 y = !(a + b) t pd 0.90 ns xor2 y = a bt pd 1.35 ns maj3 y = maj(a, b, c) t pd 1.33 ns xor3 y = a b ct pd 1.98 ns mux2 y = a !s + b s t pd 1.24 ns and3 y = a b c t pd 1.40 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-70 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v combinatorial cell equation parameter std. units inv y = !a t pd 1.27 ns and2 y = a b t pd 1.47 ns nand2 y = !(a b) t pd 1.52 ns or2 y = a + b t pd 1.51 ns nor2 y = !(a + b) t pd 1.57 ns xor2 y = a bt pd 2.28 ns maj3 y = maj(a, b, c) t pd 2.39 ns xor3 y = a b ct pd 3.50 ns mux2 y = a !s + b s t pd 2.21 ns and3 y = a b c t pd 2.50 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics 2-52 advance v0.4 versatile specifications as a sequential module the igloo plus library offers a wide variety of se quential cells, including flip-flops and latches. each has a data input and optional en able, clear, or preset. in this se ction, timing ch aracteristics are presented for a representative sample from the library. for more details, refer to the fusion, igloo/e, and proasic3/e macro library guide . figure 2-19 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
igloo plus dc and switching characteristics advance v0.4 2-53 timing characteristics 1.5 v dc core voltage figure 2-20 ? timing model and waveforms pre clr out clk data en t sue 50 % 50 % t sud t hd 50 % 50 % t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % table 2-71 ? register delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t clkq clock-to-q of the core register 0.80 ns t sud data setup time for the core register 0.84 ns t hd data hold time for the core register 0.00 ns t sue enable setup time for the core register 0.73 ns t he enable hold time for the core register 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.62 ns t pre2q asynchronous preset-to-q of the core register 0.60 ns t remclr asynchronous clear removal time for the core register 0.00 ns t recclr asynchronous clear recovery ti me for the core register 0.23 ns t rempre asynchronous preset removal ti me for the core register 0.00 ns t recpre asynchronous preset recovery ti me for the core register 0.24 ns t wclr asynchronous clear mini mum pulse width for the core register 0.30 ns t wpre asynchronous preset minimum pulse width for the core register 0.30 ns t ckmpwh clock minimum pulse width high for the core register 0.56 ns t ckmpwl clock minimum pulse width low for the core register 0.56 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-54 advance v0.4 1.2 v dc core voltage table 2-72 ? register delays commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t clkq clock-to-q of the core register 1.40 ns t sud data setup time for the core register 1.35 ns t hd data hold time for the core register 0.00 ns t sue enable setup time for the core register 1.29 ns t he enable hold time for the core register 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.89 ns t pre2q asynchronous preset-to-q of the core register 0.87 ns t remclr asynchronous clear removal time for the core register 0.00 ns t recclr asynchronous clear recovery ti me for the core register 0.24 ns t rempre asynchronous preset removal ti me for the core register 0.00 ns t recpre asynchronous preset recovery ti me for the core register 0.24 ns t wclr asynchronous clear mini mum pulse width for the core register 0.46 ns t wpre asynchronous preset minimum pulse width for the core register 0.46 ns t ckmpwh clock minimum pulse width high for the core register 0.95 ns t ckmpwl clock minimum pulse width low for the core register 0.95 ns note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-55 global resource characteristics aglp125 clock tree topology clock delays are device-specific. figure 2-21 is an example of a global tree used for clock routing. the global tree presented in figure 2-21 is driven by a ccc located on the west side of the aglp125 device. it is used to drive al l d-flip-flops in the device. figure 2-21 ? example of global tree use in an aglp125 device for clock routing central global rib versatile rows global spine ccc
igloo plus dc and switching characteristics 2-56 advance v0.4 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-59 . table 2-73 to table 2-78 on page 2-58 present minimum and ma ximum global clock dela ys within each device. minimum and maximum delays are measur ed with minimum an d maximum loading. timing characteristics 1.5 v dc core voltage table 2-73 ? aglp030 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.21 1.42 ns t rckh input high delay for global clock 1.23 1.49 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.27 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-74 ? aglp060 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.32 1.52 ns t rckh input high delay for global clock 1.34 1.59 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-57 1.2 v dc core voltage table 2-75 ? aglp125 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.31 1.66 ns t rckh input high delay for global clock 1.29 1.72 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.43 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-76 ? aglp030 global resource commercial-case conditions: t j = 70c, v cc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 1.80 2.09 ns t rckh input high delay for global clock 1.88 2.27 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.39 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics 2-58 advance v0.4 table 2-77 ? aglp060 global resource commercial-case conditions: t j = 70c, v cc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.02 2.30 ns t rckh input high delay for global clock 2.09 2.46 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.37 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values. table 2-78 ? aglp125 global resource commercial-case conditions: t j = 70c, v cc = 1.14 v parameter description std. units min. 1 max. 2 t rckl input low delay for global clock 2.08 2.54 ns t rckh input high delay for global clock 2.15 2.77 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.62 ns f rmax maximum frequency fo r global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-59 clock conditioning circuits ccc electrical specifications timing characteristics table 2-79 ? igloo plus ccc/pll specification for igloo plus v2 or v5 devices, 1.5 v dc core supply voltage parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 250 mhz clock conditioning circuitry output frequency f out_ccc 0.75 250 mhz delay increments in programmable delay blocks 1, 2 360 ps number of programmable values in each programmable delay block 32 input cycle-to-cycle jitte r (peak magnitude) 100 mhz ccc output peak-to-p eak period jitter f ccc_out 1 ns max peak-to-peak period jitter 0.75 mhz to 24 mhz 1 global network used external fb used 3 global networks used 24 mhz to 100 mhz 0.50 % 0.75 % 0.70 % 100 mhz to 250 mhz 1.00 % 1.50 % 1.20 % acquisition time 2.50 % 3.75 % 2.75 % lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter lockcontrol = 0 2.5 lockcontrol = 1 1.5 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2, 3 1.25 15.65 ns delay range in block: programmable delay 2 1, 2, 3 0.025 15.65 ns delay range in block: fixed delay 1, 2 3.5 ns notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-6 and table 2-7 on page 2-7 for deratings. 2. t j = 25c, v cc = 1.5 v 3. for definitions of type 1 and type 2, refer to the pll bl ock diagram in the clock conditioning circuits in igloo and proa sic3 devices chapter of the handbook. 4. the aglp030 device does not support pll. 5. tracking jitter is defined as the variation in clock edge position of pll outputs with reference to the pll input clock edge. tracking jitter do es not measure the variation in pll output period, which is covered by the period jitter parameter.
igloo plus dc and switching characteristics 2-60 advance v0.4 table 2-80 ? igloo plus ccc/pll specification for igloo plus v2 devices, 1.2 v dc core supply voltage parameter min. typ. max. units clock conditioning circuitry input frequency f in_ccc 1.5 160 mhz clock conditioning circuitry output frequency f out_ccc 0.75 160 mhz delay increments in programmable delay blocks 1, 2 580 ps number of programmable values in each programmable delay block 32 input cycle-to-cycle jitte r (peak magnitude) 60 mhz ccc output peak-to-p eak period jitter f ccc_out max peak-to-peak period jitter 1 global network used external fb used 3 global networks used 0.75 mhz to 24 mhz 0.50 % 0.75 % 0.70 % 24 mhz to 100 mhz 1.00 % 1.50 % 1.20 % 100 mhz to 160 mhz 2.50 % 3.75 % 2.75 % acquisition time lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter lockcontrol = 0 4 ns lockcontrol = 1 3 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2, 3 2.3 20.86 ns delay range in block: programmable delay 2 1, 2, 3 0.025 20.86 ns delay range in block: fixed delay 1, 2 5.7 ns notes: 1. this delay is a function of voltage and temperature. see table 2-6 on page 2-6 and table 2-7 on page 2-7 for deratings. 2. t j = 25c, v cc = 1.2 v 3. for definitions of type 1 and type 2, refer to the pll block diagram in the clock conditioning circuits in igloo and proa sic3 devices chapter of the handbook. 4. the aglp030 device does not support pll. 5. tracking jitter is defined as the variation in clock ed ge position of pll outputs with reference to pll input clock edge. tracking jitter does not measure the variat ion in pll output period, which is covered by period jitter parameter. note: peak-to-peak jitter measurements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-22 ? peak-to-peak jitter definition t perio d _max t perio d _min output s i g nal
igloo plus dc and switching characteristics advance v0.4 2-61 embedded sram and fifo characteristics sram figure 2-23 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
igloo plus dc and switching characteristics 2-62 advance v0.4 timing waveforms figure 2-24 ? ram read for pass-through output figure 2-25 ? ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
igloo plus dc and switching characteristics advance v0.4 2-63 figure 2-26 ? ram write, output retained (wmode = 0) figure 2-27 ? ram write, output as write data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (pass-through) di 1 d n di 0 do (pipelined) di 0 di 1 d n di 2
igloo plus dc and switching characteristics 2-64 advance v0.4 figure 2-28 ? write access after write onto same address c lk1 c lk2 wen_b1 wen_b2 add1 add2 di1 di2 do2 (pass-throu g h) do2 (pipeline d ) a 0 t ah t a s t ah t a s t dh t cc kh t d s t c kq1 t c kq2 d 1 a 1 d 2 a 3 d 3 a 0 d 0 d n d 0 d n d 0 a 0 a 4 d 4
igloo plus dc and switching characteristics advance v0.4 2-65 figure 2-29 ? read access after write onto same address c lk1 c lk2 wen_b1 wen_b2 add1 add2 di1 do2 (pass-throu g h) do2 (pipeline d ) a 0 t ah t a s t ah t a s t dh t d s t wro t c kq1 t c kq2 d 0 a 0 a 1 a 4 d n d n d 0 d 0 d 1 a 2 d 2 a 3 d 3
igloo plus dc and switching characteristics 2-66 advance v0.4 figure 2-30 ? write access after read onto same address figure 2-31 ? ram reset a 0 a 1 a 0 a 0 a 1 a 3 d 1 d 2 d 3 t ah t a s t ah t a s t c kq1 t c kq1 t c kq2 t cc kh c lk1 add1 wen_b1 do1 (pass-throu g h) do1 (pipeline d ) c lk2 add2 di2 wen_b2 d n d n d 0 d 1 d 0 clk reset_b do d n t cyc t ckh t ckl t rstbq d m
igloo plus dc and switching characteristics advance v0.4 2-67 timing characteristics 1.5 v dc core voltage table 2-81 ? ram4k9 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t as address setup time 0.83 ns t ah address hold time 0.16 ns t ens ren_b, wen_b setup time 0.81 ns t enh ren_b, wen_b hold time 0.16 ns t bks blk_b setup time 1.65 ns t bkh blk_b hold time 0.16 ns t ds input data (di) setup time 0.71 ns t dh input data (di) hold time 0.36 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 3.53 ns clock high to new data valid on do (flow-through, wmode = 1) 3.06 ns t ckq2 clock high to new data valid on do (pipelined) 1.81 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbd ns t cckh address collision clk-to-clk delay for reli able write access after write/read on same address tbd ns t rstbq reset_b low to data out low on do (flow-through) 2.06 ns reset_b low to data out low on do (pipelined) 2.06 ns t remrstb reset_b removal 0.61 ns t recrstb reset_b recovery 3.21 ns t mpwrstb reset_b minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequency 160 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-68 advance v0.4 table 2-82 ? ram512x18 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t as address setup time 0.83 ns t ah address hold time 0.16 ns t ens ren_b, wen_b setup time 0.73 ns t enh ren_b, wen_b hold time 0.08 ns t ds input data (di) setup time 0.71 ns t dh input data (di) hold time 0.36 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 4.21 ns t ckq2 clock high to new data valid on do (pipelined) 1.71 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbd ns t cckh address collision clk-to-clk delay for reli able write access after write/read on same address tbd ns t rstbq reset_b low to data out low on do (flow-through) 2.06 ns reset_b low to data out low on do (pipelined) 2.06 ns t remrstb reset_b removal 0.61 ns t recrstb reset_b recovery 3.21 ns t mpwrstb reset_b minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequency 160 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-69 1.2 v dc core voltage table 2-83 ? ram4k9 commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t as address setup time 1.53 ns t ah address hold time 0.29 ns t ens ren_b, wen_b setup time 1.50 ns t enh ren_b, wen_b hold time 0.29 ns t bks blk_b setup time 3.05 ns t bkh blk_b hold time 0.29 ns t ds input data (di) setup time 1.33 ns t dh input data (di) hold time 0.66 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 6.61 ns clock high to new data valid on do (flow-through, wmode = 1) 5.72 ns t ckq2 clock high to new data valid on do (pipelined) 3.38 ns t wro address collision clk-to-clk dela y for reliable read access after write on same address tbd ns t cckh address collision clk-to-clk delay for reli able write access after write/read on same address tbd ns t rstbq reset_b low to data out low on do (flow-through) 3.86 ns reset_b low to data out low on do (pipelined) 3.86 ns t remrstb reset_b removal 1.12 ns t recrstb reset_b recovery 5.93 ns t mpwrstb reset_b minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequency 92 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics 2-70 advance v0.4 table 2-84 ? ram512x18 commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t as address setup time 1.53 ns t ah address hold time 0.29 ns t ens ren_b, wen_b setup time 1.36 ns t enh ren_b, wen_b hold time 0.15 ns t ds input data (di) setup time 1.33 ns t dh input data (di) hold time 0.66 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 7.88 ns t ckq2 clock high to new data valid on do (pipelined) 3.20 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbd ns t cckh address collision clk-to-clk delay for reliab le write access after write/read on same address tbd ns t rstbq reset_b low to data out low on do (flow through) 3.86 ns reset_b low to data out low on do (pipelined) 3.86 ns t remrstb reset_b removal 1.12 ns t recrstb reset_b recovery 5.93 ns t mpwrstb reset_b minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequency 92 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-71 fifo figure 2-32 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
igloo plus dc and switching characteristics 2-72 advance v0.4 timing waveforms figure 2-33 ? fifo reset figure 2-34 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter)
igloo plus dc and switching characteristics advance v0.4 2-73 figure 2-35 ? fifo full flag and afull flag assertion figure 2-36 ? fifo empty flag and ae mpty flag deassertion figure 2-37 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull
igloo plus dc and switching characteristics 2-74 advance v0.4 timing characteristics 1.5 v dc core voltage table 2-85 ? fifo worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units t ens ren_b, wen_b setup time 1.99 ns t enh ren_b, wen_b hold time 0.16 ns t bks blk_b setup time 0.30 ns t bkh blk_b hold time 0.00 ns t ds input data (di) setup time 0.76 ns t dh input data (di) hold time 0.25 ns t ckq1 clock high to new data valid on do (flow-through) 3.33 ns t ckq2 clock high to new data valid on do (pipelined) 1.80 ns t rckef rclk high to empty flag valid 3.53 ns t wckff wclk high to full flag valid 3.35 ns t ckaf clock high to almost empt y/full flag valid 12.85 ns t rstfg reset_b low to empty/ full flag valid 3.48 ns t rstaf reset_b low to almost empt y/full flag valid 12.72 ns t rstbq reset_b low to data out low on do (flow-through) 2.02 ns reset_b low to data out lo w on do (pipelined) 2.02 ns t remrstb reset_b removal 0.61 ns t recrstb reset_b recovery 3.21 ns t mpwrstb reset_b minimum pulse width 0.68 ns t cyc clock cycle time 6.24 ns f max maximum frequenc y for fifo 160 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics advance v0.4 2-75 1.2 v dc core voltage table 2-86 ? fifo worst commercial-case conditions: t j = 70c, v cc = 1.14 v parameter description std. units t ens ren_b, wen_b setup time 4.13 ns t enh ren_b, wen_b hold time 0.31 ns t bks blk_b setup time 0.30 ns t bkh blk_b hold time 0.00 ns t ds input data (di) setup time 1.56 ns t dh input data (di) hold time 0.49 ns t ckq1 clock high to new data valid on do (flow-through) 6.80 ns t ckq2 clock high to new data valid on do (pipelined) 3.62 ns t rckef rclk high to empty flag valid 7.23 ns t wckff wclk high to full flag valid 6.85 ns t ckaf clock high to almost empt y/full flag valid 26.61 ns t rstfg reset_b low to empty/ full flag valid 7.12 ns t rstaf reset_b low to almost empt y/full flag valid 26.33 ns t rstbq reset_b low to data out low on do (flow-through) 4.09 ns reset_b low to data out lo w on do (pipelined) 4.09 ns t remrstb reset_b removal 1.23 ns t recrstb reset_b recovery 6.58 ns t mpwrstb reset_b minimum pulse width 1.18 ns t cyc clock cycle time 10.90 ns f max maximum frequenc y for fifo 92 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-7 on page 2-7 for derating values.
igloo plus dc and switching characteristics 2-76 advance v0.4 embedded flashrom characteristics timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage figure 2-38 ? timing diagram a 0 a 1 t s u t hold t s u t hold t s u t hold t c kq2 t c kq2 t c kq2 c lk a dd ress data d 0 d 0 d 1 table 2-87 ? embedded flashrom access time worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description std. units t su address setup time 0.57 ns t hold address hold time 0.00 ns t ck2q clock to out 33.14 ns f max maximum clock frequency 15 mhz table 2-88 ? embedded flashrom access time worst commercial-case conditions: t j = 70c, v cc = 1.14 v parameter description std. units t su address setup time 0.59 ns t hold address hold time 0.00 ns t ck2q clock to out 52.04 ns f max maximum clock frequency 10 mhz
igloo plus dc and switching characteristics advance v0.4 2-77 jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtain complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing ch aracteristics in the "user i/o characteristics" section on page 2-15 for more details. timing characteristics 1.5 v dc core voltage 1.2 v dc core voltage table 2-89 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description std. units t disu test data input setup time 1.00 ns t dihd test data input hold time 2.00 ns t tmssu test mode select setup time 1.00 ns t tmdhd test mode select hold time 2.00 ns t tck2q clock to q (data out) 8.00 ns t rstb2q reset to q (data out) 25.00 ns f tckmax tck maximum frequency 15 mhz t trstrem resetb removal time 0.58 ns t trstrec resetb recovery time 0.00 ns t trstmpw resetb minimum pulse tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-90 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case v cc = 1.14 v parameter description std. units t disu test data input setup time 1.50 ns t dihd test data input hold time 3.00 ns t tmssu test mode select setup time 1.50 ns t tmdhd test mode select hold time 3.00 ns t tck2q clock to q (data out) 11.00 ns t rstb2q reset to q (data out) 30.00 ns f tckmax tck maximum frequency 9.00 mhz t trstrem resetb removal time 1.18 ns t trstrec resetb recovery time 0.00 ns t trstmpw resetb minimum pulse tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values.
igloo plus dc and switching characteristics 2-78 advance v0.4 part number and revision date part number 51700102-002-3 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (advance v0.4) page advance v0.3 (july 2008) data was revised significantl y in the following tables: table 2-24 summary of i/o timing char acteristics?software default settings, std speed grade, commerc ial-case conditions: t j = 70c, worst-case vcc = 1.425 v, worst-case vcci = 3.0 v , table 2-25 summary of i/o timing char acteristics?software default settings, std speed grade, commerc ial-case conditions: t j = 70c, worst-case vcc = 1.14 v, worst-case vcci = 3.0 v table 2-43 2.5 lvcmos low slew ? ap plies to 1.2 v dc core voltage table 2-44 2.5 v lvcmos high slew ? applies to 1.2 v dc core voltage 2-21 , 2-30 advance v0.2 (march 2008) as a result of the libero ide v8.4 re lease, actel now offers a wide range of core voltage support. th e document was updated to change 1.2 v / 1.5 v to 1.2 v to 1.5 v. n/a advance v0.1 (january 2008) tables have been update d to reflect default valu es in the software. the default i/o capacitance is 5 pf. tables have been updated to include the lvcmos 1.2 v i/o set. n/a table note 3 was updated in table 2-2 recommended operating conditions 4 to add the sentence, "v cci should be at the same voltage within a given i/o bank." references to table notes 5, 6, 7, and 8 were added. reference to table note 3 was removed from v pump operation and placed next to v cc . 2-2 table 2-4 overshoot an d undershoot limits 1 was revised to remove "as measured on quiet i/os" from the title. table note 2 was revised to remove "estimated sso density over cycles." table note 3 was deleted. 2-3 the table note for table 2-8 quiescent supply current (i dd ) characteristics, igloo plus flash*freeze mode* to remove the sentence stating that values do not include i/o static contribution. 2-7 the table note for table 2-9 quiescent supply current (i dd ) characteristics, igloo plus sleep mode (vcc = 0 v)* was updated to remove v jtag and v cci and the statement that values do not include i/o static contribution. 2-7 the table note for table 2-10 quiescent supply current (i dd ) characteristics, igloo plus shutdown mode (vcc, vcci = 0 v)* was updated to remove the statement that values do not in clude i/o static contribution. 2-7 note 2 of table 2-11 quiescent supply current (i dd ), no igloo plus flash*freeze mode1 was updated to include v ccpll . table note 4 was deleted. 2-8 table 2-12 summary of i/o input buff er power (per pin) ? default i/o software settings and table 2-13 summary of i/o output buffer power (per pin) ? default i/o software settings1 were updated to remove static power. the table notes were updated to reflect that power was measured on v cci . table note 2 was added to table 2-12 summary of i/o input buffer power (per pin) ? default i/o software settings . 2-8 , 2-9
igloo plus dc and switching characteristics advance v0.4 2-79 actel safety critical, life support, and high-reliability applications policy the actel products described in this advance st atus datasheet may not have completed actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. it is the responsibility of each customer to ensure the fitn ess of any actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. consult actel?s terms and cond itions for specific liability exclusions relating to life-support applications. a reliabilit y report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for addi tional reliability information. advance v0.1 (continued) table 2-15 different components con tributing to the static power consumption in igloo plus devices and table 2-17 different components contributing to the static power consumption in igloo plus devices were updated to change th e definition for p dc5 from bank static power to bank quiescent power. table su btitles were added for table2-15different components contributing to the stat ic power consumption in igloo plus devices , table 2-16 different components contributing to dynamic power consumption in igloo plus devices , and table 2-17 different components contributing to the static power consumption in igloo plus devices . 2-10 , 2-11 the "total static power consumption?p stat " section was revised. 2-12 table 2-31 schmitt trig ger input hysteresis is new. 2-24 previous version changes in current version (advance v0.4) page

v1.4 3-1 igloo ? plus packaging 3 ? package pin assignments 128-pin vqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the bottom view of the package. 1 128-pin vqfp 128
package pin assignments 3-2 v1.4 128-pin vqfp pin number aglp030 function 1 io119rsb3 2 io118rsb3 3 io117rsb3 4 io115rsb3 5 io116rsb3 6 io113rsb3 7 io114rsb3 8 gnd 9v cci b3 10 io112rsb3 11 io111rsb3 12 io110rsb3 13 io109rsb3 14 gec0/io108rsb3 15 gea0/io107rsb3 16 geb0/io106rsb3 17 v cc 18 io104rsb3 19 io103rsb3 20 io102rsb3 21 io101rsb3 22 io100rsb3 23 io99rsb3 24 gnd 25 v cci b3 26 io97rsb3 27 io98rsb3 28 io95rsb3 29 io96rsb3 30 io94rsb3 31 io93rsb3 32 io92rsb3 33 io91rsb2 34 ff/io90rsb2 35 io89rsb2 36 io88rsb2 37 io86rsb2 38 io84rsb2 39 io83rsb2 40 gnd 41 v cci b2 42 io82rsb2 43 io81rsb2 44 io79rsb2 45 io78rsb2 46 io77rsb2 47 io75rsb2 48 io74rsb2 49 v cc 50 io73rsb2 51 io72rsb2 52 io70rsb2 53 io69rsb2 54 io68rsb2 55 io66rsb2 56 io65rsb2 57 gnd 58 v cci b2 59 io63rsb2 60 io61rsb2 61 io59rsb2 62 tck 63 tdi 64 tms 65 v pump 66 tdo 67 trst 68 io58rsb1 69 v jtag 70 io56rsb1 71 io57rsb1 72 v cci b1 128-pin vqfp pin number aglp030 function 73 gnd 74 io55rsb1 75 io54rsb1 76 io53rsb1 77 io52rsb1 78 io51rsb1 79 io50rsb1 80 io49rsb1 81 v cc 82 gdb0/io48rsb1 83 gda0/io47rsb1 84 gdc0/io46rsb1 85 io45rsb1 86 io44rsb1 87 io43rsb1 88 io42rsb1 89 v cci b1 90 gnd 91 io40rsb1 92 io41rsb1 93 io39rsb1 94 io38rsb1 95 io37rsb1 96 io36rsb1 97 io35rsb0 98 io34rsb0 99 io33rsb0 100 io32rsb0 101 io30rsb0 102 io28rsb0 103 io27rsb0 104 v cci b0 105 gnd 106 io26rsb0 107 io25rsb0 108 io23rsb0 128-pin vqfp pin number aglp030 function
igloo plus packaging v1.4 3-3 109 io22rsb0 110 io21rsb0 111 io19rsb0 112 io18rsb0 113 v cc 114 io17rsb0 115 io16rsb0 116 io14rsb0 117 io13rsb0 118 io12rsb0 119 io10rsb0 120 io09rsb0 121 v cci b0 122 gnd 123 io07rsb0 124 io05rsb0 125 io03rsb0 126 io02rsb0 127 io01rsb0 128 io00rsb0 128-pin vqfp pin number aglp030 function
package pin assignments 3-4 v1.4 176-pin vqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the bottom view of the package. 1 176-pin vqfp 176
igloo plus packaging v1.4 3-5 176-pin vqfp pin number agl p060 function 1 gaa2/io156rsb3 2 io155rsb3 3 gab2/io154rsb3 4 io153rsb3 5 gac2/io152rsb3 6 gnd 7v cci b3 8 io149rsb3 9 io147rsb3 10 io145rsb3 11 io144rsb3 12 io143rsb3 13 v cc 14 io141rsb3 15 gfc1/io140rsb3 16 gfb1/io138rsb3 17 gfb0/io137rsb3 18 vcomplf 19 gfa1/io136rsb3 20 v ccplf 21 gfa0/io135rsb3 22 gnd 23 v cci b3 24 gfa2/io134rsb3 25 gfb2/io133rsb3 26 gfc2/io132rsb3 27 io131rsb3 28 io130rsb3 29 io129rsb3 30 io127rsb3 31 io126rsb3 32 io125rsb3 33 io123rsb3 34 io122rsb3 35 io121rsb3 36 io119rsb3 37 gnd 38 v cci b3 39 gec1/io116rsb3 40 geb1/io114rsb3 41 gec0/io115rsb3 42 geb0/io113rsb3 43 gea1/io112rsb3 44 gea0/io111rsb3 45 gea2/io110rsb2 46 nc 47 ff/geb2/io109rsb 2 48 gec2/io108rsb2 49 io106rsb2 50 io107rsb2 51 io104rsb2 52 io105rsb2 53 io102rsb2 54 io103rsb2 55 gnd 56 v cci b2 57 io101rsb2 58 io100rsb2 59 io99rsb2 60 io98rsb2 61 io97rsb2 62 io96rsb2 63 io95rsb2 64 io94rsb2 65 io93rsb2 66 v cc 67 io92rsb2 68 io91rsb2 69 io90rsb2 70 io89rsb2 71 io88rsb2 176-pin vqfp pin number aglp060 function 72 io87rsb2 73 io86rsb2 74 io85rsb2 75 io84rsb2 76 gnd 77 v cci b2 78 io83rsb2 79 io82rsb2 80 gdc2/io80rsb2 81 io81rsb2 82 gda2/io78rsb2 83 gdb2/io79rsb2 84 nc 85 nc 86 tck 87 tdi 88 tms 89 v pump 90 tdo 91 trst 92 v jtag 93 gda1/io76rsb1 94 gdc0/io73rsb1 95 gdb1/io74rsb1 96 gdc1/io72rsb1 97 v cci b1 98 gnd 99 io70rsb1 100 io69rsb1 101 io67rsb1 102 io66rsb1 103 io65rsb1 104 io63rsb1 105 io62rsb1 106 io61rsb1 107 gcc2/io60rsb1 176-pin vqfp pin number aglp060 function
package pin assignments 3-6 v1.4 108 gcb2/io59rsb1 109 gca2/io58rsb1 110 gca0/io57rsb1 111 gca1/io56rsb1 112 v cci b1 113 gnd 114 gcb0/io55rsb1 115 gcb1/io54rsb1 116 gcc0/io53rsb1 117 gcc1/io52rsb1 118 io51rsb1 119 io50rsb1 120 v cc 121 io48rsb1 122 io47rsb1 123 io45rsb1 124 io44rsb1 125 io43rsb1 126 v cci b1 127 gnd 128 gbc2/io40rsb1 129 io39rsb1 130 gbb2/io38rsb1 131 io37rsb1 132 gba2/io36rsb1 133 gba1/io35rsb0 134 nc 135 gba0/io34rsb0 136 nc 137 gbb1/io33rsb0 138 nc 139 gbc1/io31rsb0 140 gbb0/io32rsb0 141 gbc0/io30rsb0 142 io29rsb0 143 io28rsb0 176-pin vqfp pin number agl p060 function 144 io27rsb0 145 v cci b0 146 gnd 147 io26rsb0 148 io25rsb0 149 io24rsb0 150 io23rsb0 151 io22rsb0 152 io21rsb0 153 io20rsb0 154 io19rsb0 155 io18rsb0 156 v cc 157 io17rsb0 158 io16rsb0 159 io15rsb0 160 io14rsb0 161 io13rsb0 162 io12rsb0 163 io11rsb0 164 io10rsb0 165 io09rsb0 166 v cci b0 167 gnd 168 io07rsb0 169 io08rsb0 170 gac1/io05rsb0 171 io06rsb0 172 gab1/io03rsb0 173 gac0/io04rsb0 174 gab0/io02rsb0 175 gaa1/io01rsb0 176 gaa0/io00rsb0 176-pin vqfp pin number aglp060 function
igloo plus packaging v1.4 3-7 201-pin csp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the bottom view of the package. 1 a b c d e f g h j k l m n p r 2 3 4 5 6 7 8 9 15 14 13 12 11 10
package pin assignments 3-8 v1.4 201-pin csp pin number aglp030 function a1 nc a2 io04rsb0 a3 io06rsb0 a4 io09rsb0 a5 io11rsb0 a6 io13rsb0 a7 io17rsb0 a8 io18rsb0 a9 io24rsb0 a10 io26rsb0 a11 io27rsb0 a12 io31rsb0 a13 nc a14 nc a15 nc b1 nc b2 nc b3 io08rsb0 b4 io05rsb0 b5 io07rsb0 b6 io15rsb0 b7 io14rsb0 b8 io16rsb0 b9 io20rsb0 b10 io22rsb0 b11 io34rsb0 b12 io29rsb0 b13 nc b14 nc b15 nc c1 nc c2 nc c3 gnd c4 io00rsb0 c5 io02rsb0 c6 io12rsb0 c7 io23rsb0 c8 io19rsb0 c9 io28rsb0 c10 io32rsb0 c11 io35rsb0 c12 nc c13 gnd c14 io41rsb1 c15 io37rsb1 d1 io117rsb3 d2 io118rsb3 d3 nc d4 gnd d5 io01rsb0 d6 io03rsb0 d7 io10rsb0 d8 io21rsb0 d9 io25rsb0 d10 io30rsb0 d11 io33rsb0 d12 gnd d13 nc d14 io36rsb1 d15 io39rsb1 e1 io115rsb3 e2 io114rsb3 e3 nc e4 nc e12 nc e13 nc e14 gdc0/io46rsb1 e15 gdb0/io48rsb1 f1 io113rsb3 f2 io116rsb3 f3 io119rsb3 f4 io111rsb3 201-pin csp pin number aglp030 function f6 gnd f7 v cc f8 v cci b0 f9 v cci b0 f10 v cci b0 f12 nc f13 nc f14 io40rsb1 f15 io38rsb1 g1 nc g2 io112rsb3 g3 io110rsb3 g4 io109rsb3 g6 v cci b3 g7 gnd g8 v cc g9 gnd g10 gnd g12 nc g13 nc g14 io42rsb1 g15 io44rsb1 h1 nc h2 geb0/io106rsb3 h3 gec0/io108rsb3 h4 nc h6 v cci b3 h7 gnd h8 v cc h9 gnd h10 v cci b1 h12 io54rsb1 h13 gda0/io47rsb1 h14 io45rsb1 h15 io43rsb1 j1 gea0/io107rsb3 201-pin csp pin number aglp030 function
igloo plus packaging v1.4 3-9 j2 io105rsb3 j3 io104rsb3 j4 io102rsb3 j6 v cci b3 j7 gnd j8 v cc j9 gnd j10 v cci b1 j12 nc j13 nc j14 io52rsb1 j15 io50rsb1 k1 io103rsb3 k2 io101rsb3 k3 io99rsb3 k4 io100rsb3 k6 gnd k7 v cci b2 k8 v cci b2 k9 v cci b2 k10 v cci b1 k12 nc k13 io57rsb1 k14 io49rsb1 k15 io53rsb1 l1 io96rsb3 l2 io98rsb3 l3 io95rsb3 l4 io94rsb3 l12 nc l13 nc l14 io51rsb1 l15 io58rsb1 m1 io93rsb3 m2 io92rsb3 m3 io97rsb3 201-pin csp pin number aglp030 function m4 gnd m5 nc m6 io79rsb2 m7 io77rsb2 m8 io72rsb2 m9 io70rsb2 m10 io61rsb2 m11 io59rsb2 m12 gnd m13 nc m14 io55rsb1 m15 io56rsb1 n1 nc n2 nc n3 gnd n4 nc n5 io88rsb2 n6 io81rsb2 n7 io75rsb2 n8 io68rsb2 n9 io66rsb2 n10 io65rsb2 n11 io71rsb2 n12 io63rsb2 n13 gnd n14 tdo n15 v jtag p1 nc p2 nc p3 nc p4 nc p5 io87rsb2 p6 io86rsb2 p7 io84rsb2 p8 io80rsb2 p9 io74rsb2 201-pin csp pin number aglp030 function p10 io73rsb2 p11 io76rsb2 p12 io67rsb2 p13 io64rsb2 p14 v pump p15 trst r1 nc r2 nc r3 io91rsb2 r4 ff/io90rsb2 r5 io89rsb2 r6 io83rsb2 r7 io82rsb2 r8 io85rsb2 r9 io78rsb2 r10 io69rsb2 r11 io62rsb2 r12 io60rsb2 r13 tms r14 tdi r15 tck 201-pin csp pin number aglp030 function
package pin assignments 3-10 v1.4 201-pin csp pin number aglp060 function a1 io150rsb3 a2 gaa0/io00rsb0 a3 gac0/io04rsb0 a4 io08rsb0 a5 io11rsb0 a6 io15rsb0 a7 io17rsb0 a8 io18rsb0 a9 io22rsb0 a10 io26rsb0 a11 io29rsb0 a12 gbc1/io31rsb0 a13 gba2/io36rsb1 a14 io41rsb1 a15 nc b1 io151rsb3 b2 gab2/io154rsb3 b3 io06rsb0 b4 io09rsb0 b5 io13rsb0 b6 io10rsb0 b7 io12rsb0 b8 io20rsb0 b9 io23rsb0 b10 io25rsb0 b11 io24rsb0 b12 io27rsb0 b13 io37rsb1 b14 io46rsb1 b15 io42rsb1 c1 io155rsb3 c2 gaa2/io156rsb3 c3 gnd c4 gaa1/io01rsb0 c5 gab1/io03rsb0 c6 io07rsb0 c7 io16rsb0 c8 io21rsb0 c9 io28rsb0 c10 gbb1/io33rsb0 c11 gba1/io35rsb0 c12 gbb2/io38rsb1 c13 gnd c14 io48rsb1 c15 io39rsb1 d1 io146rsb3 d2 io144rsb3 d3 io148rsb3 d4 gnd d5 gab0/io02rsb0 d6 gac1/io05rsb0 d7 io14rsb0 d8 io19rsb0 d9 gbc0/io30rsb0 d10 gbb0/io32rsb0 d11 gba0/io34rsb0 d12 gnd d13 gbc2/io40rsb1 d14 io51rsb1 d15 io44rsb1 e1 io142rsb3 e2 io149rsb3 e3 io153rsb3 e4 gac2/io152rsb3 e12 io43rsb1 e13 io49rsb1 e14 gcc0/io53rsb1 e15 gcb0/io55rsb1 f1 io141rsb3 f2 gfc1/io140rsb3 f3 io145rsb3 f4 io147rsb3 201-pin csp pin number aglp060 function f6 gnd f7 v cc f8 v cci b0 f9 v cci b0 f10 v cci b0 f12 io47rsb1 f13 io45rsb1 f14 gcc1/io52rsb1 f15 gca1/io56rsb1 g1 vcomplf g2 gfb0/io137rsb3 g3 gfc0/io139rsb3 g4 io143rsb3 g6 v cci b3 g7 gnd g8 v cc g9 gnd g10 gnd g12 io50rsb1 g13 gcb1/io54rsb1 g14 gcc2/io60rsb1 g15 gca2/io58rsb1 h1 vccplf h2 gfa1/io136rsb3 h3 gfb1/io138rsb3 h4 nc h6 v cci b3 h7 gnd h8 v cc h9 gnd h10 v cci b1 h12 gcb2/io59rsb1 h13 gca0/io57rsb1 h14 io64rsb1 h15 io62rsb1 j1 gfa2/io134rsb3 201-pin csp pin number aglp060 function
igloo plus packaging v1.4 3-11 j2 gfa0/io135rsb3 j3 gfb2/io133rsb3 j4 io131rsb3 j6 v cci b3 j7 gnd j8 v cc j9 gnd j10 v cci b1 j12 io61rsb1 j13 io63rsb1 j14 io68rsb1 j15 io66rsb1 k1 io130rsb3 k2 gfc2/io132rsb3 k3 io127rsb3 k4 io129rsb3 k6 gnd k7 v cci b2 k8 v cci b2 k9 v cci b2 k10 v cci b1 k12 io65rsb1 k13 io67rsb1 k14 io69rsb1 k15 io70rsb1 l1 io126rsb3 l2 io128rsb3 l3 io121rsb3 l4 io123rsb3 l12 gdb1/io74rsb1 l13 gdc1/io72rsb1 l14 io71rsb1 l15 gdc0/io73rsb1 m1 io122rsb3 m2 io124rsb3 m3 io119rsb3 201-pin csp pin number aglp060 function m4 gnd m5 io125rsb3 m6 io98rsb2 m7 io96rsb2 m8 io91rsb2 m9 io89rsb2 m10 io82rsb2 m11 gda2/io78rsb2 m12 gnd m13 gda1/io76rsb1 m14 gda0/io77rsb1 m15 gdb0/io75rsb1 n1 io117rsb3 n2 io120rsb3 n3 gnd n4 geb1/io114rsb3 n5 io107rsb2 n6 io100rsb2 n7 io94rsb2 n8 io87rsb2 n9 io85rsb2 n10 gdc2/io80rsb2 n11 io90rsb2 n12 io84rsb2 n13 gnd n14 tdo n15 v jtag p1 gec0/io115rsb3 p2 gec1/io116rsb3 p3 gea0/io111rsb3 p4 gea1/io112rsb3 p5 io106rsb2 p6 io105rsb2 p7 io103rsb2 p8 io99rsb2 p9 io93rsb2 201-pin csp pin number aglp060 function p10 io92rsb2 p11 io95rsb2 p12 io86rsb2 p13 io83rsb2 p14 v pump p15 trst r1 io118rsb3 r2 geb0/io113rsb3 r3 gea2/io110rsb2 r4 ff/geb2/io109rsb 2 r5 gec2/io108rsb2 r6 io102rsb2 r7 io101rsb2 r8 io104rsb2 r9 io97rsb2 r10 io88rsb2 r11 io81rsb2 r12 gdb2/io79rsb2 r13 tms r14 tdi r15 tck 201-pin csp pin number aglp060 function
package pin assignments 3-12 v1.4 281-pin csp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx note: this is the bottom view of the package. 10 9 8 7 6 5432 1 11 12 13 14 15 1 6 17 18 19 m n p r t u v w d e f a b c g h j k l
igloo plus packaging v1.4 3-13 281-pin csp pin number aglp125 function a1 gnd a2 gab0/io02rsb0 a3 gac1/io05rsb0 a4 io09rsb0 a5 io13rsb0 a6 io15rsb0 a7 io18rsb0 a8 io23rsb0 a9 io25rsb0 a10 v cci b0 a11 io33rsb0 a12 io41rsb0 a13 io43rsb0 a14 io46rsb0 a15 io55rsb0 a16 io56rsb0 a17 gbc1/io58rsb0 a18 gba0/io61rsb0 a19 gnd b1 gaa2/io211rsb3 b2 v cci b0 b3 gab1/io03rsb0 b4 gac0/io04rsb0 b5 io11rsb0 b6 gnd b7 io21rsb0 b8 io22rsb0 b9 io28rsb0 b10 io32rsb0 b11 io36rsb0 b12 io39rsb0 b13 io42rsb0 b14 gnd b15 io52rsb0 b16 gbc0/io57rsb0 b17 gba1/io62rsb0 b18 v cci b1 b19 io64rsb1 c1 gab2/io209rsb3 c2 io210rsb3 c6 io12rsb0 c14 io47rsb0 c18 io54rsb0 c19 gbb2/io65rsb1 d1 io206rsb3 d2 io208rsb3 d4 gaa0/io00rsb0 d5 gaa1/io01rsb0 d6 io10rsb0 d7 io17rsb0 d8 io24rsb0 d9 io27rsb0 d10 gnd d11 io31rsb0 d12 io40rsb0 d13 io49rsb0 d14 io45rsb0 d15 gbb0/io59rsb0 d16 gba2/io63rsb1 d18 gbc2/io67rsb1 d19 io66rsb1 e1 io203rsb3 e2 io205rsb3 e4 io07rsb0 e5 io06rsb0 e6 io14rsb0 e7 io20rsb0 e8 io29rsb0 e9 io34rsb0 e10 io30rsb0 e11 io37rsb0 e12 io38rsb0 281-pin csp pin number aglp125 function e13 io48rsb0 e14 gbb1/io60rsb0 e15 io53rsb0 e16 io69rsb1 e18 io68rsb1 e19 io71rsb1 f1 io198rsb3 f2 gnd f3 io201rsb3 f4 io204rsb3 f5 io16rsb0 f15 io50rsb0 f16 io74rsb1 f17 io72rsb1 f18 gnd f19 io73rsb1 g1 io195rsb3 g2 io200rsb3 g4 io202rsb3 g5 io08rsb0 g7 gac2/io207rsb3 g8 v cci b0 g9 io26rsb0 g10 io35rsb0 g11 io44rsb0 g12 v cci b0 g13 io51rsb0 g15 io70rsb1 g16 io75rsb1 g18 gcc0/io80rsb1 g19 gcb1/io81rsb1 h1 gfb0/io191rsb3 h2 io196rsb3 h4 gfc1/io194rsb3 h5 gfb1/io192rsb3 h7 v cci b3 281-pin csp pin number aglp125 function
h8 v cc h9 v cci b0 h10 vcc h11 v cci b0 h12 v cc h13 v cci b1 h15 io77rsb1 h16 gcb0/io82rsb1 h18 gca1/io83rsb1 h19 gca2/io85rsb1 j1 vcomplf j2 gfa0/io189rsb3 j4 v ccplf j5 gfc0/io193rsb3 j7 gfa2/io188rsb3 j8 v cci b3 j9 gnd j10 gnd j11 gnd j12 v cci b1 j13 gcc1/io79rsb1 j15 gca0/io84rsb1 j16 gcb2/io86rsb1 j18 io76rsb1 j19 io78rsb1 k1 v cci b3 k2 gfa1/io190rsb3 k4 gnd k5 io19rsb0 k7 io197rsb3 k8 v cc k9 gnd k10 gnd k11 gnd k12 v cc k13 gcc2/io87rsb1 281-pin csp pin number aglp125 function k15 io89rsb1 k16 gnd k18 io88rsb1 k19 v cci b1 l1 gfb2/io187rsb3 l2 io185rsb3 l4 gfc2/io186rsb3 l5 io184rsb3 l7 io199rsb3 l8 v cci b3 l9 gnd l10 gnd l11 gnd l12 v cci b1 l13 io95rsb1 l15 io91rsb1 l16 nc l18 io90rsb1 l19 nc m1 io180rsb3 m2 io179rsb3 m4 io181rsb3 m5 io183rsb3 m7 v cci b3 m8 v cc m9 v cci b2 m10 v cc m11 v cci b2 m12 v cc m13 v cci b1 m15 io122rsb2 m16 io93rsb1 m18 io92rsb1 m19 nc n1 io178rsb3 n2 io175rsb3 281-pin csp pin number aglp125 function n4 io182rsb3 n5 io161rsb2 n7 gea2/io164rsb2 n8 v cci b2 n9 io137rsb2 n10 io135rsb2 n11 io131rsb2 n12 v cci b2 n13 v pump n15 io117rsb2 n16 io96rsb1 n18 io98rsb1 n19 io94rsb1 p1 io174rsb3 p2 gnd p3 io176rsb3 p4 io177rsb3 p5 gea0/io165rsb3 p15 io111rsb2 p16 io108rsb2 p17 gdc1/io99rsb1 p18 gnd p19 io97rsb1 r1 io173rsb3 r2 io172rsb3 r4 gec1/io170rsb3 r5 geb1/io168rsb3 r6 io154rsb2 r7 io149rsb2 r8 io146rsb2 r9 io138rsb2 r10 io134rsb2 r11 io132rsb2 r12 io130rsb2 r13 io118rsb2 r14 io112rsb2 281-pin csp pin number aglp125 function
igloo plus packaging v1.4 3-15 r15 io109rsb2 r16 gda1/io103rsb1 r18 gdb0/io102rsb1 r19 gdc0/io100rsb1 t1 io171rsb3 t2 gec0/io169rsb3 t4 geb0/io167rsb3 t5 io157rsb2 t6 io158rsb2 t7 io148rsb2 t8 io145rsb2 t9 io143rsb2 t10 gnd t11 io129rsb2 t12 io126rsb2 t13 io125rsb2 t14 io116rsb2 t15 gdc2/io107rsb2 t16 tms t18 v jtag t19 gdb1/io101rsb1 u1 io160rsb2 u2 gea1/io166rsb3 u6 io151rsb2 u14 io121rsb2 u18 trst u19 gda0/io104rsb1 v1 io159rsb2 v2 v cci b3 v3 gec2/io162rsb2 v4 io156rsb2 v5 io153rsb2 v6 gnd v7 io144rsb2 v8 io141rsb2 v9 io140rsb2 281-pin csp pin number aglp125 function v10 io133rsb2 v11 io127rsb2 v12 io123rsb2 v13 io120rsb2 v14 gnd v15 io113rsb2 v16 gda2/io105rsb2 v17 tdi v18 v cci b2 v19 tdo w1 gnd w2 ff/geb2/io163rsb2 w3 io155rsb2 w4 io152rsb2 w5 io150rsb2 w6 io147rsb2 w7 io142rsb2 w8 io139rsb2 w9 io136rsb2 w10 v cci b2 w11 io128rsb2 w12 io124rsb2 w13 io119rsb2 w14 io115rsb2 w15 io114rsb2 w16 io110rsb2 w17 gdb2/io106rsb2 w18 tck w19 gnd 281-pin csp pin number aglp125 function
package pin assignments 3-16 v1.4 289-pin csp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the bottom view of the package. 17 1 6 15 14 13 12 11 10 9 8 7 6 54321 a b c d e f g h j k l m n p r t u a1 ball pa d c orner
igloo plus packaging v1.4 3-17 289-pin csp pin number agl p030 function a1 io03rsb0 a2 nc a3 nc a4 gnd a5 io10rsb0 a6 io14rsb0 a7 io16rsb0 a8 io18rsb0 a9 gnd a10 io23rsb0 a11 io27rsb0 a12 nc a13 nc a14 gnd a15 nc a16 nc a17 io30rsb0 b1 io01rsb0 b2 gnd b3 nc b4 nc b5 io07rsb0 b6 nc b7 v cci b0 b8 io17rsb0 b9 io19rsb0 b10 io24rsb0 b11 io28rsb0 b12 v cci b0 b13 nc b14 nc b15 nc b16 io31rsb0 b17 gnd c1 nc c2 io00rsb0 c3 io04rsb0 c4 nc c5 v cci b0 c6 io09rsb0 c7 io13rsb0 c8 io15rsb0 c9 io21rsb0 c10 gnd c11 io29rsb0 c12 nc c13 nc c14 nc c15 gnd c16 io34rsb0 c17 nc d1 nc d2 io119rsb3 d3 gnd d4 io02rsb0 d5 nc d6 nc d7 nc d8 gnd d9 io20rsb0 d10 io25rsb0 d11 nc d12 nc d13 gnd d14 io32rsb0 d15 io35rsb0 d16 nc d17 nc e1 v cci b3 e2 io114rsb3 e3 io115rsb3 e4 io118rsb3 e5 io05rsb0 e6 nc e7 io06rsb0 e8 io11rsb0 289-pin csp pin number aglp030 function e9 io22rsb0 e10 io26rsb0 e11 v cci b0 e12 nc e13 io33rsb0 e14 io36rsb1 e15 io38rsb1 e16 v cci b1 e17 nc f1 io111rsb3 f2 nc f3 io116rsb3 f4 v cci b3 f5 io117rsb3 f6 nc f7 nc f8 io08rsb0 f9 io12rsb0 f10 nc f11 nc f12 nc f13 nc f14 gnd f15 nc f16 io37rsb1 f17 io41rsb1 g1 io110rsb3 g2 gnd g3 io113rsb3 g4 nc g5 nc g6 nc g7 gnd g8 gnd g9 v cc g10 gnd g11 gnd g12 io40rsb1 289-pin csp pin number aglp030 function
package pin assignments 3-18 v1.4 g13 nc g14 io39rsb1 g15 io44rsb1 g16 nc g17 gnd h1 nc h2 gec0/io108rsb3 h3 nc h4 io112rsb3 h5 nc h6 io109rsb3 h7 gnd h8 gnd h9 gnd h10 gnd h11 gnd h12 nc h13 nc h14 io45rsb1 h15 v cci b1 h16 gdb0/io48rsb1 h17 io42rsb1 j1 nc j2 gea0/io107rsb3 j3 v cci b3 j4 io105rsb3 j5 nc j6 nc j7 v cc j8 gnd j9 gnd j10 gnd j11 v cc j12 io50rsb1 j13 io43rsb1 j14 io51rsb1 j15 io52rsb1 j16 gdc0/io46rsb1 289-pin csp pin number agl p030 function j17 gda0/io47rsb1 k1 gnd k2 geb0/io106rsb3 k3 io102rsb3 k4 io104rsb3 k5 io99rsb3 k6 nc k7 gnd k8 gnd k9 gnd k10 gnd k11 gnd k12 nc k13 nc k14 nc k15 io53rsb1 k16 gnd k17 io49rsb1 l1 io103rsb3 l2 io101rsb3 l3 nc l4 gnd l5 nc l6 nc l7 gnd l8 gnd l9 v cc l10 gnd l11 gnd l12 io58rsb1 l13 io54rsb1 l14 v cci b1 l15 nc l16 nc l17 nc m1 nc m2 v cci b3 m3 io100rsb3 289-pin csp pin number aglp030 function m4 io98rsb3 m5 io93rsb3 m6 io97rsb3 m7 nc m8 nc m9 io71rsb2 m10 nc m11 io63rsb2 m12 nc m13 io57rsb1 m14 nc m15 nc m16 nc m17 v cci b1 n1 nc n2 nc n3 io95rsb3 n4 io96rsb3 n5 gnd n6 nc n7 io85rsb2 n8 io79rsb2 n9 io77rsb2 n10 v cci b2 n11 nc n12 nc n13 io59rsb2 n14 nc n15 gnd n16 io56rsb1 n17 io55rsb1 p1 io94rsb3 p2 nc p3 gnd p4 nc p5 nc p6 io87rsb2 p7 io80rsb2 289-pin csp pin number aglp030 function
igloo plus packaging v1.4 3-19 p8 gnd p9 io72rsb2 p10 io67rsb2 p11 io61rsb2 p12 nc p13 v cci b2 p14 nc p15 io60rsb2 p16 io62rsb2 p17 v jtag r1 gnd r2 io91rsb2 r3 nc r4 nc r5 nc r6 v cci b2 r7 io83rsb2 r8 io78rsb2 r9 io74rsb2 r10 io70rsb2 r11 gnd r12 nc r13 nc r14 nc r15 nc r16 tms r17 trst t1 io92rsb3 t2 io89rsb2 t3 nc t4 gnd t5 nc t6 io84rsb2 t7 io81rsb2 t8 io76rsb2 t9 v cci b2 t10 io69rsb2 t11 io65rsb2 289-pin csp pin number agl p030 function t12 io64rsb2 t13 nc t14 gnd t15 nc t16 tdi t17 tdo u1 ff/io90rsb2 u2 gnd u3 nc u4 io88rsb2 u5 io86rsb2 u6 io82rsb2 u7 gnd u8 io75rsb2 u9 io73rsb2 u10 io68rsb2 u11 io66rsb2 u12 gnd u13 nc u14 nc u15 nc u16 tck u17 v pump 289-pin csp pin number aglp030 function
package pin assignments 3-20 v1.4 289-pin csp pin number aglp060 function a1 gab1/io03rsb0 a2 nc a3 nc a4 gnd a5 io10rsb0 a6 io14rsb0 a7 io16rsb0 a8 io18rsb0 a9 gnd a10 io23rsb0 a11 io27rsb0 a12 nc a13 nc a14 gnd a15 nc a16 nc a17 gbc0/io30rsb0 b1 gaa1/io01rsb0 b2 gnd b3 nc b4 nc b5 io07rsb0 b6 nc b7 v cci b0 b8 io17rsb0 b9 io19rsb0 b10 io24rsb0 b11 io28rsb0 b12 vccib0 b13 nc b14 nc b15 nc b16 gbc1/io31rsb0 b17 gnd c1 io155rsb3 c2 gaa0/io00rsb0 c3 gac0/io04rsb0 c4 nc c5 v cci b0 c6 io09rsb0 c7 io13rsb0 c8 io15rsb0 c9 io21rsb0 c10 gnd c11 io29rsb0 c12 nc c13 nc c14 nc c15 gnd c16 gba0/io34rsb0 c17 io39rsb1 d1 io150rsb3 d2 io151rsb3 d3 gnd d4 gab0/io02rsb0 d5 nc d6 nc d7 nc d8 gnd d9 io20rsb0 d10 io25rsb0 d11 nc d12 nc d13 gnd d14 gbb0/io32rsb0 d15 gba1/io35rsb0 d16 io37rsb1 d17 io42rsb1 e1 v cci b3 e2 io147rsb3 e3 gac2/io152rsb3 e4 gaa2/io156rsb3 e5 gac1/io05rsb0 e6 nc e7 io06rsb0 e8 io11rsb0 289-pin csp pin number aglp060 function e9 io22rsb0 e10 io26rsb0 e11 v cci b0 e12 nc e13 gbb1/io33rsb0 e14 gba2/io36rsb1 e15 gbb2/io38rsb1 e16 v cci b1 e17 io44rsb1 f1 gfc1/io140rsb3 f2 io142rsb3 f3 io149rsb3 f4 v cci b3 f5 gab2/io154rsb3 f6 io153rsb3 f7 nc f8 io08rsb0 f9 io12rsb0 f10 nc f11 nc f12 nc f13 gbc2/io40rsb1 f14 gnd f15 io43rsb1 f16 io46rsb1 f17 io45rsb1 g1 gfc0/io139rsb3 g2 gnd g3 io144rsb3 g4 io145rsb3 g5 io146rsb3 g6 io148rsb3 g7 gnd g8 gnd g9 vcc g10 gnd g11 gnd g12 io48rsb1 289-pin csp pin number aglp060 function
igloo plus packaging v1.4 3-21 g13 io41rsb1 g14 io47rsb1 g15 io49rsb1 g16 io50rsb1 g17 gnd h1 v complf h2 gfb0/io137rsb3 h3 nc h4 io141rsb3 h5 io143rsb3 h6 gfb1/io138rsb3 h7 gnd h8 gnd h9 gnd h10 gnd h11 gnd h12 gcc1/io52rsb1 h13 io51rsb1 h14 gca0/io57rsb1 h15 v cci b1 h16 gca2/io58rsb1 h17 gcc0/io53rsb1 j1 v ccplf j2 gfa1/io136rsb3 j3 v cci b3 j4 io131rsb3 j5 io130rsb3 j6 io129rsb3 j7 v cc j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io59rsb1 j13 gcb1/io54rsb1 j14 io62rsb1 j15 io63rsb1 j16 gcb0/io55rsb1 289-pin csp pin number aglp060 function j17 gca1/io56rsb1 k1 gnd k2 gfa0/io135rsb3 k3 gfb2/io133rsb3 k4 io128rsb3 k5 io123rsb3 k6 io125rsb3 k7 gnd k8 gnd k9 gnd k10 gnd k11 gnd k12 io64rsb1 k13 io61rsb1 k14 io66rsb1 k15 io65rsb1 k16 gnd k17 gcc2/io60rsb1 l1 gfa2/io134rsb3 l2 gfc2/io132rsb3 l3 io127rsb3 l4 gnd l5 io121rsb3 l6 gec1/io116rsb3 l7 gnd l8 gnd l9 v cc l10 gnd l11 gnd l12 gdc1/io72rsb1 l13 gdb1/io74rsb1 l14 v cci b1 l15 io70rsb1 l16 io68rsb1 l17 io67rsb1 m1 io126rsb3 m2 v cci b3 m3 io124rsb3 289-pin csp pin number aglp060 function m4 io122rsb3 m5 geb0/io113rsb3 m6 geb1/io114rsb3 m7 nc m8 nc m9 io90rsb2 m10 nc m11 io83rsb2 m12 nc m13 gda1/io76rsb1 m14 gda0/io77rsb1 m15 io71rsb1 m16 io69rsb1 m17 v cci b1 n1 io119rsb3 n2 io120rsb3 n3 gec0/io115rsb3 n4 gea0/io111rsb3 n5 gnd n6 nc n7 io104rsb2 n8 io98rsb2 n9 io96rsb2 n10 v cci b2 n11 nc n12 nc n13 gdb2/io79rsb2 n14 nc n15 gnd n16 gdb0/io75rsb1 n17 gdc0/io73rsb1 p1 io118rsb3 p2 io117rsb3 p3 gnd p4 nc p5 nc p6 io106rsb2 p7 io99rsb2 289-pin csp pin number aglp060 function
package pin assignments 3-22 v1.4 p8 gnd p9 io91rsb2 p10 io86rsb2 p11 io81rsb2 p12 nc p13 v cci b2 p14 nc p15 gda2/io78rsb2 p16 gdc2/io80rsb2 p17 v jtag r1 gnd r2 gea2/io110rsb2 r3 nc r4 nc r5 nc r6 v cci b2 r7 io102rsb2 r8 io97rsb2 r9 io93rsb2 r10 io89rsb2 r11 gnd r12 nc r13 nc r14 nc r15 nc r16 tms r17 trst t1 gea1/io112rsb3 t2 gec2/io108rsb2 t3 nc t4 gnd t5 nc t6 io103rsb2 t7 io100rsb2 t8 io95rsb2 t9 v cci b2 t10 io88rsb2 t11 io84rsb2 289-pin csp pin number aglp060 function t12 io82rsb2 t13 nc t14 gnd t15 nc t16 tdi t17 tdo u1 ff/geb2/io109rsb2 u2 gnd u3 nc u4 io107rsb2 u5 io105rsb2 u6 io101rsb2 u7 gnd u8 io94rsb2 u9 io92rsb2 u10 io87rsb2 u11 io85rsb2 u12 gnd u13 nc u14 nc u15 nc u16 tck u17 v pump 289-pin csp pin number aglp060 function
igloo plus packaging v1.4 3-23 289-pin csp pin number aglp125 function a1 gab1/io03rsb0 a2 io11rsb0 a3 io08rsb0 a4 gnd a5 io19rsb0 a6 io24rsb0 a7 io26rsb0 a8 io30rsb0 a9 gnd a10 io35rsb0 a11 io38rsb0 a12 io40rsb0 a13 io42rsb0 a14 gnd a15 io48rsb0 a16 io54rsb0 a17 gbc0/io57rsb0 b1 gaa1/io01rsb0 b2 gnd b3 io06rsb0 b4 io13rsb0 b5 io15rsb0 b6 io21rsb0 b7 v cci b0 b8 io28rsb0 b9 io31rsb0 b10 io37rsb0 b11 io39rsb0 b12 v cci b0 b13 io44rsb0 b14 io46rsb0 b15 io49rsb0 b16 gbc1/io58rsb0 b17 gnd c1 io210rsb3 c2 gaa0/io00rsb0 c3 gac0/io04rsb0 c4 io09rsb0 c5 v cci b0 c6 io17rsb0 c7 io23rsb0 c8 io27rsb0 c9 io33rsb0 c10 gnd c11 io43rsb0 c12 io45rsb0 c13 io50rsb0 c14 io52rsb0 c15 gnd c16 gba0/io61rsb0 c17 io68rsb1 d1 io204rsb3 d2 io205rsb3 d3 gnd d4 gab0/io02rsb0 d5 io07rsb0 d6 io10rsb0 d7 io18rsb0 d8 gnd d9 io34rsb0 d10 io41rsb0 d11 io47rsb0 d12 io55rsb0 d13 gnd d14 gbb0/io59rsb0 d15 gba1/io62rsb0 d16 io66rsb1 d17 io70rsb1 e1 v cci b3 e2 io200rsb3 e3 gac2/io207rsb3 e4 gaa2/io211rsb3 e5 gac1/io05rsb0 e6 io12rsb0 e7 io16rsb0 e8 io22rsb0 289-pin csp pin number aglp125 function e9 io32rsb0 e10 io36rsb0 e11 v cci b0 e12 io56rsb0 e13 gbb1/io60rsb0 e14 gba2/io63rsb1 e15 gbb2/io65rsb1 e16 v cci b1 e17 io73rsb1 f1 gfc1/io194rsb3 f2 io196rsb3 f3 io202rsb3 f4 v cci b3 f5 gab2/io209rsb3 f6 io208rsb3 f7 io14rsb0 f8 io20rsb0 f9 io25rsb0 f10 io29rsb0 f11 io51rsb0 f12 io53rsb0 f13 gbc2/io67rsb1 f14 gnd f15 io75rsb1 f16 io71rsb1 f17 io77rsb1 g1 gfc0/io193rsb3 g2 gnd g3 io198rsb3 g4 io203rsb3 g5 io201rsb3 g6 io206rsb3 g7 gnd g8 gnd g9 v cc g10 gnd g11 gnd g12 io72rsb1 289-pin csp pin number aglp125 function
package pin assignments 3-24 v1.4 g13 io64rsb1 g14 io69rsb1 g15 io78rsb1 g16 io76rsb1 g17 gnd h1 v complf h2 gfb0/io191rsb3 h3 io195rsb3 h4 io197rsb3 h5 io199rsb3 h6 gfb1/io192rsb3 h7 gnd h8 gnd h9 gnd h10 gnd h11 gnd h12 gcc1/io79rsb1 h13 io74rsb1 h14 gca0/io84rsb1 h15 v cci b1 h16 gca2/io85rsb1 h17 gcc0/io80rsb1 j1 v ccplf j2 gfa1/io190rsb3 j3 v cci b3 j4 io185rsb3 j5 io183rsb3 j6 io181rsb3 j7 v cc j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io86rsb1 j13 gcb1/io81rsb1 j14 io90rsb1 j15 io89rsb1 j16 gcb0/io82rsb1 289-pin csp pin number aglp125 function j17 gca1/io83rsb1 k1 gnd k2 gfa0/io189rsb3 k3 gfb2/io187rsb3 k4 io179rsb3 k5 io175rsb3 k6 io177rsb3 k7 gnd k8 gnd k9 gnd k10 gnd k11 gnd k12 io88rsb1 k13 io94rsb1 k14 io95rsb1 k15 io93rsb1 k16 gnd k17 gcc2/io87rsb1 l1 gfa2/io188rsb3 l2 gfc2/io186rsb3 l3 io182rsb3 l4 gnd l5 io173rsb3 l6 gec1/io170rsb3 l7 gnd l8 gnd l9 v cc l10 gnd l11 gnd l12 gdc1/io99rsb1 l13 gdb1/io101rsb1 l14 v cci b1 l15 io98rsb1 l16 io92rsb1 l17 io91rsb1 m1 io184rsb3 m2 v cci b3 m3 io176rsb3 289-pin csp pin number aglp125 function m4 io172rsb3 m5 geb0/io167rsb3 m6 geb1/io168rsb3 m7 io159rsb2 m8 io161rsb2 m9 io135rsb2 m10 io128rsb2 m11 io121rsb2 m12 io113rsb2 m13 gda1/io103rsb1 m14 gda0/io104rsb1 m15 io97rsb1 m16 io96rsb1 m17 v cci b1 n1 io180rsb3 n2 io178rsb3 n3 gec0/io169rsb3 n4 gea0/io165rsb3 n5 gnd n6 io156rsb2 n7 io148rsb2 n8 io144rsb2 n9 io137rsb2 n10 v cci b2 n11 io119rsb2 n12 io111rsb2 n13 gdb2/io106rsb2 n14 io109rsb2 n15 gnd n16 gdb0/io102rsb1 n17 gdc0/io100rsb1 p1 io174rsb3 p2 io171rsb3 p3 gnd p4 io160rsb2 p5 io157rsb2 p6 io154rsb2 p7 io152rsb2 289-pin csp pin number aglp125 function
igloo plus packaging v1.4 3-25 p8 gnd p9 io132rsb2 p10 io125rsb2 p11 io126rsb2 p12 io112rsb2 p13 v cci b2 p14 io108rsb2 p15 gda2/io105rsb2 p16 gdc2/io107rsb2 p17 v jtag r1 gnd r2 gea2/io164rsb2 r3 io158rsb2 r4 io155rsb2 r5 io150rsb2 r6 v cci b2 r7 io145rsb2 r8 io141rsb2 r9 io134rsb2 r10 io130rsb2 r11 gnd r12 io118rsb2 r13 io116rsb2 r14 io114rsb2 r15 io110rsb2 r16 tms r17 trst t1 gea1/io166rsb3 t2 gec2/io162rsb2 t3 io153rsb2 t4 gnd t5 io147rsb2 t6 io143rsb2 t7 io140rsb2 t8 io139rsb2 t9 v cci b2 t10 io131rsb2 t11 io127rsb2 289-pin csp pin number aglp125 function t12 io124rsb2 t13 io122rsb2 t14 gnd t15 io115rsb2 t16 tdi t17 tdo u1 ff/geb2/io163rsb2 u2 gnd u3 io151rsb2 u4 io149rsb2 u5 io146rsb2 u6 io142rsb2 u7 gnd u8 io138rsb2 u9 io136rsb2 u10 io133rsb2 u11 io129rsb2 u12 gnd u13 io123rsb2 u14 io120rsb2 u15 io117rsb2 u16 tck u17 v pump 289-pin csp pin number aglp125 function
package pin assignments 3-26 v1.4 part number and revision date part number 51700102-003-4 revised august 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.4) page v1.3 (june 2008) the "128-pin vqfp" package drawing and pin table are new. 3-1 the "176-pin vqfp" package drawing and pin table are new. 3-4 v1.2 (june 2008) the "281-pin csp" package drawing is new. 3-12 the "281-pin csp" table for the aglp125 device is new. 3-13 the "289-pin csp" package drawing was incorrect. the graphic was showing the cs281 mechanical drawing and no t the cs289 mechanical drawing. this has now been corrected. 3-16 v1.1 (june 2008) the "289-pin csp" table for the aglp030 device is new. 3-17 v1.0 (january 2008) the "289-pin csp" table for the aglp060 device is new. 3-20 the "289-pin csp" table for the aglp125 device is new. 3-23
igloo plus packaging v1.4 3-27 datasheet categories categories in order to provide the latest information to desi gners, some datasheets are published before data has been fully characterized. datasheets are designated as "product brief," "advance," "preliminary," and "production." the definiti on of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advance or production) and contains general product information. this document give s an overview of specific device and family information. advance this version contains initial estimated information based on simulation, ot her products, devices, or speed grades. this information can be used as estimates, but not for production. this label only applies to the dc and switching characteristics chapte r of the datasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on si mulation and/or initia l characterization. the information is believed to be co rrect, but changes are possible. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this do cument are subject to the expo rt administration regulations (ear). they could require an ap proved export license prior to export from the united states. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status document may not have completed actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. it is the responsibility of each customer to ensure the fitn ess of any actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. consult actel?s terms and cond itions for specific liability exclusions relating to life-support applications. a reliabilit y report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for addi tional reliability information.

section ii ? core architecture

low-power flash technology and flash*freeze mode

v1.3 1-1 1 ? fpga array architecture in low-power flash devices device architecture advanced flash switch unlike sram fpgas, the low-power flash devices use a live-at-power- up isp flash switch as their programming element. flash cell s are distributed throug hout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate versatile inputs and outputs. in the flash switch, two transistors shar e the floating gate, whic h stores the programming information ( figure 1-1 ). one is the sensing transistor, which is only used for writing and verification of the floating gate voltage. the other is the switchin g transistor. the latter is used to connect or separate routing nets, or to configure versatile logic. it is also used to erase the floating gate. dedicated high-performance li nes are connected as required using the flash switch for fast, low-skew, global signal distribution throughout the device core. maximum core utilization is possible for virtually any design. th e use of the flash switch technolo gy also removes the possibility of firm errors, which are increasingly common in sram-based fpgas. figure 1-1 ? flash-based switch sensing switching switch in switch out word floating gate
fpga array architecture in low-power flash devices 1-2 v1.3 fpga array architecture support the low-power flash fa milies listed in table 1-1 support the architecture features described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 1-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 1-1 . where the informati on applies to only one fa mily or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 1-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proasic ? 3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo ? igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
core architecture of ig loo and proasic3 devices v1.3 1-3 device overview the low-power flash devices cons ist of multiple disti nct programmable architectural features ( figure 1-2 on page 1-3 through figure 1-4 on page 1-4 ): ? fpga fabric/core (versatiles) ? routing and clock resources (versanets) ?flashrom ? dedicated sram and/or fifo ? 15 k and 30 k gate devices do not support sram or fifo. ? automotive devices do not support fifo operation ? i/o structures ? flash*freeze technology and low-power modes note: flash*freeze technology only applies to igloo and proasic3l families. figure 1-2 ? igloo and proasic3/l device architecture overview with four i/o banks (agl600 device is shown) isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2
fpga array architecture in low-power flash devices 1-4 v1.3 figure 1-3 ? igloo plus device architecture overview with four i/o banks note: flash*freeze technology only applies to iglooe devices. figure 1-4 ? iglooe and proasic3e device architectu re overview (agle600 device is shown) ram block 4,608-bit dual-port sram or fifo block * versatile ccc i/os isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps bank 0 bank 1 bank 1 bank 3 bank 3 bank 2 * 4,608-bit dual-port sram or fifo block versatile ram block ccc pro i/os 4,608-bit dual-port sram or fifo block ram block isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps
core architecture of ig loo and proasic3 devices v1.3 1-5 core architecture versatile the proprietary igloo and proasic3 device archit ectures provide granularity comparable to gate arrays. the device core consists of a sea-of-versatiles architecture. as illustrated in figure 1-5 , there are four inputs in a logic versatile cell, and each versatile can be configured using the appropriat e flash switch connections: ? any 3-input logic function ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set (on a 4 th input) versatiles can flexibly map the logic and sequenti al gates of a design. the inputs of the versatile can be inverted (allowing bubble pushing), and th e output of the tile can connect to high-speed, very-long-line routing resources. versatiles and larger fu nctions can be connec ted with any of the four levels of routing hierarchy. when the versatile is used as an enable d-flip-f lop, set/clr is supported by a fourth input. the set/clr signal can only be routed to this fo urth input over the versanet (global) network. however, if, in the user?s design, the set/clr si gnal is not routed over the versanet network, a compile warning message will be given, and the intended logic function will be implemented by two versatiles instead of one. the output of the versatile is f2 wh en the connection is to the ultra-fast loca l lines, or yl when the connection is to the efficient long-l ine or very-long-line resources. * this input can only be connected to the global clock distribution network. figure 1-5 ? low-power flash device core versatile switch (flash connection) ground via (hard connection) legend: y pin 1 0 1 0 1 0 1 0 1 data x3 clk x2 clr/ enable x1 clr xc * f2 yl
fpga array architecture in low-power flash devices 1-6 v1.3 array coordinates during many place-and-route operations in the ac tel designer software tool, it is possible to set constraints that requir e array coordinates. table 1-2 provides array coordinates of core cells and memory blocks for proasi c3 and igloo devices. table 1-3 provides the information for igloo plus devices. the array coordinates are measured from the lower left (0, 0) they can be used in region constraints for spec ific logic groups/b locks, designated by a wi ldcard, and can contain core cells, memories, and i/os. i/o and cell coordinates are used for placement constraints. two coordina te systems are needed because there is not a one-to-one correspondence be tween i/o cells and core cells. in addition, the i/o coordinate system changes depending on the die/package combination. it is not listed in table 1-2 . the designer chipplanner tool provides the ar ray coordinates of all i/o locations. i/o and cell coordinates are used for plac ement constraints. however, i/o placement is easier by package pin assignment. figure 1-6 on page 1-7 illustrates the array coordinates of a 600 k gate device. for more information on how to use a rray coordinates for region/pla cement constraints, see the designer user's guide or online help (available in the software) for software tools. table 1-2 ? igloo and proasic3 array coordinates device versatiles memory rows entire die min. max. bottom top min. max. proasic3/ proasic3l igloo x y x y (x, y) (x, y) (x, y) (x, y) a3p015 agl015 3 2 34 13 none none (0, 0) (37, 15) a3p030 agl030 3 3 66 13 none none (0, 0) (69, 15) a3p060 agl060 3 2 66 25 none (3, 26) (0, 0) (69, 29) a3p125 agl125 3 2 130 25 none (3, 26) (0, 0) (133, 29) a3p250/l agl250 3 2 130 49 none (3, 50) (0, 0) (133, 53) a3p400 3 2 194 49 none (3, 50) (0, 0) (197, 53) a3p600/l agl600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) a3p1000/l agl1000 3 4 258 99 (3, 2) (3, 100) (0, 0) (261, 103) a3pe600 / l , rt3pe600 l agle600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) a3pe1500 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 127) a3pe3000/l, rt3pe3000l agle3000 3 6 450 173 (3, 2) or (3, 4) (3, 174) or (3, 176) (0, 0) (453, 179) table 1-3 ? igloo plus array coordinates device versatiles memory rows entire die min. max. bottom top min. max. igloo plus x y x y (x, y) (x, y) (x, y) (x, y) aglp030 2 3 67 13 none none (0, 0) (69, 15) aglp060 2 2 67 25 none (3, 26) (0, 0) (69, 29) aglp125 2 2 131 25 none (3, 26) (0, 0) (133, 29)
core architecture of ig loo and proasic3 devices v1.3 1-7 note: the vertical i/o tile coordinates are not shown. west-side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east-side coordinates are {(19 5, 2) to (197, 2)} to {(195, 77) to (197, 77)}. figure 1-6 ? array coordinates for agl600, agle600, a3p600, and a3pe600 top row (5, 1) to (168, 1) bottom row (7, 0) to (165, 0) top row (169, 1) to (192, 1) i/o tile memory blocks memory blocks memory blocks ujtag flashrom top row (7, 79) to (189, 79) bottom row (5, 78) to (192, 78) i/o tile (3, 77) (3, 76) memory blocks (3, 3) (3, 2) versatile (core) (3, 75) versatile (core) (3, 4) (0, 0) (197, 0) (194, 2) (194, 3) (194, 4) versatile (core) (194, 75) versatile (core) (197, 79) (194, 77) (194, 76) (0, 79) (197, 1)
fpga array architecture in low-power flash devices 1-8 v1.3 routing architecture the routing structure of low-power flash devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast loca l resources; efficient long-line resources; high-speed, very-long-line resource s; and the high-performa nce versanet networks. the ultra-fast local resources are de dicated lines that allo w the output of each versatile to connect directly to every input of th e eight surrounding versatiles ( figure 1-7 on page 1-8 ). the exception to this is that the set/clr input of a versatile co nfigured as a d-flip-flop is driven only by the versatile global network. the efficient long-line resour ces provide routing for longer distance s and higher-fanout connections. these resour ces vary in length (spanning one, two, or four versatiles), run both vertically and horizontally, an d cover the entire device ( figure 1-8 on page 1-9 ). each versatile can drive signals onto the efficient lo ng-line resources, which can access every input of every versatile. routing software automatically inserts active buffers to limit loading effects. the high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length 1 2 versatiles in the vertical direction and length 16 in the horizontal direction from a given core versatile ( figure 1-9 on page 1-9 ). very long lines in low-power flash devices have been enhanced over those in previous proasic families. this provides a significant performance boost for long-reach signals. the high-performance versanet global networks ar e low-skew, high-fanout nets that are accessible from external pins or internal lo gic. these nets are typically used to distribute clocks, resets, and other high-fanout nets requirin g minimum skew. the versanet netw orks are implemented as clock trees, and signals can be introduced at any junc tion. these can be employ ed hierarchically, with signals accessing every input of every versatil e. for more details on versanets, refer to global resources in actel lo w-power flash devices. note: input to the core cell for the d-flip-flop set a nd reset is only available via the versanet global network connection. figure 1-7 ? ultra-fast local lines connected to the eight nearest neighbors l l l l l l inputs output ultra-fast local lines (connects a versatile to the adjacent versatile, i/o buffer, or memory block) l ll long lines
core architecture of ig loo and proasic3 devices v1.3 1-9 figure 1-8 ? efficient long-line resources figure 1-9 ? very-long-line resources l l llll l lllll l l llll l l llll l l llll spans 1 versatile spans 2 versatiles spans 4 versatiles spans 1 versatile spans 2 versatiles spans 4 versatiles versatile high-speed, very-long-line resources pad ring pad ring i/o ring i/o ring pad ring 1612 block of versatiles sram
fpga array architecture in low-power flash devices 1-10 v1.3 related documents handbook documents global resources in actel low-power flash devices http://www.actel.com/documents/lpd_glorbal_hbs.pdf user?s guides designer user's guide http://www.actel.com/documents/designer_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet. to improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage info rmation. no technical chan ges were made to the content unless explicitly listed. part number 51700094-002-3 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (june 2008) the title of this document was changed from "core architecture of igloo and proasic3 devices" to "fpga array arch itecture in low-power flash devices." 1-1 the "fpga array architecture support" section was revised to include new families and make the in formation more concise. 1-2 table 1-2 igloo and proasic3 array coordinates was updated to include military proasic3/el and rt proasic3 devices. 1-6 v1.1 (march 2008) the following changes were made to the family de scriptions in table 1-1 low- power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 1-2 v1.0 (january 2008) table 1-1 low-power flash families and the accompanying text was updated to include the igloo plus family. the "igloo terminology" section and "device overview" section are new. 1-2 the "device overview" section was updated to note that 15 k devices do not support sram or fifo. 1-3 figure 1-3 igloo plus device architecture overview with four i/o banks is new. 1-4 table 1-2 igloo and proasic3 array coordinates was updated to add a3p015 and agl015. 1-6 table 1-3 igloo plus array coordinates is new. 1-6
v2.1 2-1 2 ? actel?s flash*freeze technology and low- power modes flash*freeze technology and low-power modes actel igloo, ? igloo plus, proasic ? 3l, and radiation-tolerant (rt) proasic3 fpgas with flash*freeze technology are designed to meet the most demanding power and area challenges of today?s portable electronics prod ucts with a reprogrammable, small- footprint, full-featured flash fpga. the igloo, igloo plus, proasic3l, and rt proasic3 families offer lower power consumption in static and dynamic modes, utilizing the unique flash*freeze technology, than any other fpga or cpld. igloo, igloo plus, proasic3l, and rt proasic3 devices offer various power-saving modes that enable every system to utilize modes that achi eve the lowest total system power. low power active capability (static idle) allows for ultra-low power consumption wh ile the device is operational in the system by maintaining sram, regi sters, i/os, and logic functions. flash*freeze technology provides an ultra-low-pow er static mode (flash*freeze mode) that retains all sram and register in formation with rapid reco very to active (operating) mode. igloo plus has an additional feature when operating in flash*freeze mode, allowing it to retain i/o states as well as sram and register states. this mechanism enables the user to qu ickly (within 1 s) enter and exit flash*freeze mode by activating th e flash*freeze (ff) pin while al l power supplies are kept in their original states. in addition, i /os and clocks connected to the fpga can still be toggled without impact on device power consumption. while in flash*freeze mode, the device retains all core register states and sr am information. t his mode can be configured so that no power is consumed by the i/o banks, clocks, jtag pins, or plls; and the igloo and igloo plus devices consume as little as 5 w. actel offers a state management ip core to aid users in gating clocks and managing data before entering flash*freeze mode. this document will guide users in selecting th e best low-power mode for their applications, and introduces actel's flash*fr eeze manageme nt ip core.
actel?s flash*freeze techn ology and low-power modes 2-2 v2.1 actel?s flash families support the flash*freeze feature the low-power flash families listed in table 2-1 support the flash*freeze feature and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 2-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 2-1 . where the informati on applies to only one fa mily or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 2-1 ? low-power flash families product line family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
actel?s flash*freeze technology and low-power modes v2.1 2-3 low-power modes overview table 2-2 summarizes the low-power modes that achi eve power consumption reduction when the fpga or system is idle. static (idle) mode in static (idle) mode, none of the clock inputs is switching, and static power is the only power consumed by the device. this mode can be achieved by switching off the incoming clocks to the fpga, thus benefitting from reduced power consum ption. in addition, i/os draw only minimal leakage current. in this mode, embedded sram, i/os , and registers retain their values so the device can enter and exit this mode just by switching the clocks on or off. if the device-embedded pll is used as the clock so urce, static (idle) mode can easily be entered by pulling the pll powerdown pin low (activ e low), which will turn off the pll. table 2-2 ? power modes summary mode v cci v cc core clocks ulsicc macro to e n t e r mode to r e s u m e operation trigger active on on on on n/a initiate clock none ? static idle on on on off n/a stop clock initiate clock external flash*freeze type 1 on on on on* n/a assert ff pin deassert ff pin external flash*freeze type 2 on on on on* used to enter flash*freeze mode assert ff pin and assert lsicc deassert ff pin external sleep on off off off n/a shut down v cc turn on v cc supply external shutdown off off off off n/a shut down v cc and v cci supplies turn on v cc and v cci supplies external * external clocks can be left toggling while the device is in flash*freeze mode. clocks generated by the embedded pll will be turned off automatically.
actel?s flash*freeze techn ology and low-power modes 2-4 v2.1 flash*freeze mode igloo, igloo plus, proasic3l, an d rt proasic3 fpgas offer an ultra-low static power mode to reduce power consumption while preserving the state of the registers, sram contents, and i/o states (igloo plus only) withou t switching off any power supplie s, inputs, or input clocks. flash*freeze technology enables the user to switch to flash* freeze mode within 1 s, thus simplifying low-power design implementation. the flash*freeze (ff) pin (active low) is a dedicated pin used to enter or exit flash*freeze mode direct ly; or the pin can be routed internally to the fpga core and state management ip to allow the user 's application to decide if and when it is safe to transition to this mode. if the ff pin is not used, it can be used as a regular i/o. the ff pin has a built-in glitch filter and optional schmitt trigger (not available for all devices) to prevent entering or exiting fl ash*freeze mode accidentally. there are two ways to use flash*freeze mode. in flash*freeze type 1, entering and exiting the mode is exclusively con trolled by the assertion and deasserti on of the ff pin. this enables an external processor or human interface device to directly control flash*freeze mode; however, valid data must be preserved using standard procedures (refer to the "flash*freeze mode device behavior" section on page 2-9 ). in flash*freeze mode type 2, entering and exiting the mode is controlled by both the ff pin and user-defined logi c. flash*freeze management ip may be used in type 2 mode for clock and data management while entering and exiting flash*freeze mode. flash*freeze type 1: control by dedicated flash*freeze pin flash*freeze type 1 is intended for systems wher e either the device will be reset upon exiting flash*freeze mode, or da ta and clock are managed externally. the device enters flash*freeze mode 1 s after the dedicated ff pin is asserte d (active low), and returns to normal operation when the ff pin is deasserted (high) ( figure 2-1 on page 2-5 ). in this mode, ff pin assertion or deassertion is the only condition that dete rmines entering or exit ing flash*freeze mode. in actel libero ? integrated design environment (ide) v8.2 and before, this mode is implemented by enabling flash*freeze mode (default setting) in the compile options of the actel designer software. to simplify us age of flash*freeze mode , beginning with libero ide v8 .3, an inbuf_ff i/o macro was introd uced. an inbuf_ff i/o buffer must be used to identify the flash*freeze input. actel recommends switching to the new implementation. in libero ide v8.3 and later, th e user must manually instantiate the inbuf_ff macro in the top level of the design in order implement fl ash*freeze type 1, as shown in figure 2-1 on page 2-5 .
actel?s flash*freeze technology and low-power modes v2.1 2-5 figure 2-1 shows the concept of ff pin contro l in flash*freeze mode type 1. figure 2-2 shows the timing diagram for entering and exiting flash*freeze mode type 1. figure 2-1 ? flash*freeze mode ty pe 1 ? controlled by the flash*freeze pin user design actel igloo, igloo plus, proasic3l, or rt proasic3 device flash*freeze mode enables entering flash*freeze mode flash*freeze signal flash*freeze technology flash*freeze (ff) pin inbuf_ff flash*freeze mode control and to fpga core or floating 1 figure 2-2 ? flash*freeze mode type 1 ? timing diagram normal operation flash*freeze mode normal operation flash*freeze pin t = 1 s t = 1 s
actel?s flash*freeze techn ology and low-power modes 2-6 v2.1 flash*freeze type 2: control by dedicated flash*freeze pin and internal logic the device can be made to enter flash*freeze m ode by activating the ff pin together with actel's flash*freeze management ip core (refer to the "flash*freeze management ip" section on page 2-15 for more information) or user-defined control logic ( figure 2-3 ) within the fpga core. this method enables the design to perform important activities before allowing the device to enter flash*freeze mode, such as transitioning into a safe state, comp leting the processing of a critical event. designers are encouraged to take advantage of actel's flash* freeze management ip to handle clean entry and exit of flash*freeze mode (described later in this document). the device wi ll only enter flash*freeze mode when the flash*freeze pin is asserted (active low) and the user low static i cc (ulsicc) macro input signal, called the lsicc signal, is asserted (h igh). one condition is not sufficient to enter flash*freeze mode type 2; both the ff pin and lsicc signal must be asserted. when flash*freeze type 2 is implemented in the de sign, the ulsicc macro n eeds to be instantiated by the user. there are no func tional differences in the device whether the ulsicc macro is instantiated or not, and whether the lsicc signal is asserted or deasserted. the lsicc signal is used only to control enteri ng flash*freeze mode. figure 2-4 on page 2-7 shows the timing diagram for entering and exiting flas h*freeze mode type 2. after exiting flash*freeze mode type 2 by deasse rting the flash*freeze pin, the lsicc signal must be deasserted by the user design . this will prevent en tering flash*freeze mo de by asserting the flash*freeze pin only. refer to table 2-3 for flash*freeze (ff) pin and lsicc si gnal assertion and deassertion values. table 2-3 ? flash*freeze mode type 1 and type 2 ? signal assertion and deassertion values signal assertion value deassertion value flash*freeze (ff) pin low high lsicc signal high low notes: 1. the flash*freeze (ff) pin is an active-low signal, and lsicc is an active-high signal. 2. the lsicc signal is used only in flash*freeze mode type 2. figure 2-3 ? flash*freeze mode type 2 ? controlled by flash*freeze pin and internal logic (lsicc signal) inbuf_ff auto- c onne c te d to ip ul s i cc ma c ro flash * freeze mana g ement ip user desi g n a c tel i g loo, i g loo plu s , proa s i c 3l, or rt proa s i c 3 devi c e flash * freeze mo d e ena b les enterin g flash * freeze mo d e flash * freeze s i g nal flash * freeze te c hnolo g y flash * freeze (ff) pin and c onne c t to top-level port
actel?s flash*freeze technology and low-power modes v2.1 2-7 table 2-4 summarizes the flash*freeze mode implementations. igloo, proasic3l, and rt proasic3 i/o state in flash*freeze mode in igloo and proasic3l devices, when the devi ce enters flash*freeze mode, i/os will become tristated. if the weak pull-up or pull-down feature is used, the i/os will maintain the configured weak pull-up or pull-d own status. this feature enables the desi gn to set the i/o state to a certain level that is determined by the pull-up/-down configuration. table 2-5 shows the i/o pad state based on the configuration and buffer type. note that configuring weak pull- up or pull-down for the ff pin is not allowed. the ff pin can be configured as a schmitt trigger input in iglooe, proasic3el, and igloo plus devices. figure 2-4 ? flash*freeze mode type 2 ? timing diagram lsicc signal normal operation flash*freeze mode normal operation flash*freeze pin t = 1 s t = 1 s table 2-4 ? flash*freeze mode usage flash*freeze mode type description flash*freeze pin state instantiate ulsicc macro lsicc signal operating mode 1 flash*freeze mode is controlled only by the ff pin. deasserted no n/a normal operation asserted no n/a flash*freeze mode 2 flash*freeze mode is controlled by the ff pin and lsicc signal. "don?t care" yes deasserted normal operation deasserted yes "don?t care" normal operation asserted yes asserted flash*freeze mode note: refer to table 2-3 on page 2-6 for flash*freeze pin and lsicc signa l assertion and deassertion values. table 2-5 ? igloo, proasic3l, and rt proa sic3 flash*freeze mode (type 1 and type 2)?i/o pad state buffer type i/o pad weak pull-up/-down i/o pad state in flash*freeze mode input/global en abled weak pull-up/pull-down* disabled tristate* output enabled weak pull-up/pull-down disabled tristate bidirectional / tristate buffer e = 0 (input/tristate) enabled weak pull -up/pull-down* disabled tristate* e = 1 (output) enabled weak pull-up/pull-down disabled tristate * internal core logic driven by this input/global buffer will be tied high as long as the device is in flash*freeze mode.
actel?s flash*freeze techn ology and low-power modes 2-8 v2.1 igloo plus i/o state in flash*freeze mode in igloo plus devices, users have multiple options in how to configure i/os during flash*freeze mode: 1. hold the previous state 2. set i/o pad to weak pull-up or pull-down 3. tristate i/o pads the i/o configuration must be co nfigured by the user in the i/o attribute editor or in a pdc constraint file, and can be done on a pin-by-pin basis. the output hold feature will hold the output in the last registered state, using the i/o pad weak pull-up or pull-down resistor when the ff pin is asserted. when inputs are configured with the ho ld feature enabled, the fpga core side of the input will hold the last valid state of the input pad before the de vice entered flash*freeze mode. the input pad can be driven to any value, configured as tristate, or configur ed with the weak pull- up or pull-down i/o pad feature during flash*freeze mode without affecting the hold state. if the weak pull-up or pull-down feature is used without the output hold feature, the input and output pads will maintain the configured weak pull-up or pull-down status during flash*freeze mode and normal operation. if a fixed weak pull-up or pull-down is defined on an output buffer or as bidirectional in output mode, and a hold state is also defined for the same pin, the pin will be configured in hold state mode during flash*free ze mode. during normal operation, the pin will be configured with the predefined weak pull-up or pull-down. any i/os that do not use the hold state or i/o pad weak pull-up or pull-down features will be tristated during flash*freeze mode and the fpga core will be driven high by inputs. inputs th at are tristated during flash*freeze mode may be left floating wi thout any reliability concern or impact to power consumption. table 2-6 shows the i/o pad state based on the configuration and buffer type. note that configur ing weak pull-up or pull-down for the ff pin is not allowed. table 2-6 ? igloo plus flash*freeze mode (type 1 and type 2)?i/o pad state buffer type hold state i/o pad weak pull-up/-down i/o pad state in flash*freeze mode input enabled enabled weak pull-up/pull-down 1 disabled enabled weak pull-up/pull-down 2 enabled disabled tristate 1 disabled disabled tristate 2 output enabled "don't care" w eak pull to hold state disabled enabled weak pull-up/pull-down disabled disabled tristate bidirectional / tristate buffer e = 0 (input/tristate) enabled enabled weak pull-up/pull-down 1 disabled enabled weak pull-up/pull-down 2 enabled disabled tristate 1 disabled disabled tristate 2 e = 1 (output) enabled "don't ca re" weak pull to hold state 3 disabled enabled weak pull-up/pull-down disabled disabled tristate notes: 1. internal core logic driv en by this input buffer will be set to the value this i/o had when entering flash*freeze mode. 2. internal core logic driven by this input buffer will be tied high as long as the de vice is in flash*freeze mode. 3. for bidirectional buffers: in ternal core logic driven by the input portion of the bi directional buffer will be set to the hold state.
actel?s flash*freeze technology and low-power modes v2.1 2-9 flash*freeze mode device behavior entering flash*freeze mode ? actel igloo, igloo plus, proasci3l, and rt proasic3 devices are designed and optimized to enter flash*freeze mode onl y when power supplies are stable. if the device is being powered up while the ff pin is asserted (flash *freeze mode type 1), or while both ff pin and lsicc signal are asserted (f lash*freeze mode type 2), the device is expected to enter flash*freeze mode within 5 s after the i/os and fpga core have reached their activation levels. ? if the device is already powered up when th e ff pin is asserted, the device will enter flash*freeze mode within 1 s (type 1). in flash*fr eeze mode type 2 operation, entering flash*freeze mode is completed within 1 s a fter both ff pin and lsicc signal are asserted. exiting flash*freeze mode is completed within 1 s after deasserting the ff pin only. plls ? if an embedded pll is used, entering flash*fr eeze mode will automa tically power down the pll. ? the pll output clocks will stop toggling with in 1 s after the assertion of the ff pin in type 1, or after both ff pin and lsicc signal are a sserted in type 2. at th e same time, i/os will transition into the state specified in table 2-6 on page 2-8 . the user design must ensure it is safe to enter flash*freeze mode. i/os and globals ? while entering flash*freeze mode, inputs, gl obals, and plls will enter their flash*freeze state asynchronously to each other. as a resu lt, clock and data glitches and narrow pulses may be generated while entering flash*freeze mode, as shown in figure 2-5 . ? i/o banks are not all deactivated simultaneously when entering flash* freeze mode. this can cause clocks and inputs to become disabled at different times, resulting in unexpected data being captured. ? upon entering flash*freeze mode, all inputs and globals become tied high internally (except when an input hold stat e is used on igloo plus device s). if any of these signals are driven low or tied low externally, they will experience a low to high transition internally when entering fl ash*freeze mode. ? upon entering type 2 flash*freeze mode, ensu re the lsicc signal (active high) does not de- assert. this can prevent the device from enteri ng flash*freeze mode. ? asynchronous input to output paths may experi ence output glitches. for example, on a direct in-to-out path, if the current state is '0' and the input bank tu rns off first, the input and then the outp ut will transition to '1' before the output enters its flash*freeze state. this can be prevented by using latches in asynchronous in-to-out paths. ? the above situations can cause glitches or invalid data to be clocked into and preserved in the device. refer to the "flash*freeze design guid e" section on page 2-13 for solutions. figure 2-5 ? narrow clock pulses during flash*freeze entrance and exit external c lo c k internal c lo c k enters flash * freeze mo d e exits flash * freeze mo d e flash * freeze pin
actel?s flash*freeze techn ology and low-power modes 2-10 v2.1 during flash*freeze mode ? plls are turned off duri ng flash*freeze mode. ? i/o pads are configured according to table 2-5 on page 2-7 and table 2-6 on page 2-8 . ? inputs and input clocks to the fpga can toggle without any im pact on static power consumption, assuming weak pull-up or pull-down is not selected. ? if weak pull-up or pull-down is selected and the input is driven to the opposite direction, power dissipation will occur. ? any toggling signals will be charging and discharging the package pin capacitance. ? i gloo and proasic3l outputs will be tristate d unless the i/o is configured with weak pull-up or pull-down. the output of the i/o to the fpga core is logic high regardless of whether the i/o pin is configured with a weak pull-up or pull-down. refer to table 2-5 on page 2-7 for more information. ? igloo plus output behavior will be based on the configuration defined by the user. refer to table 2-6 on page 2-8 for a description of output behavior during flash*freeze mode. ? the jtag circuit is active; however, jtag op erations, such as jtag commands, jtag bypass, programming, and authentication, cannot be executed. the device must exit flash*freeze mode before jtag commands can be sent. tc k should be static to avoid extra power consumption from the jtag state machine. ? the ff pin must be external ly asserted for the device to stay in flash*freeze mode. ? the ff pin is still active; i.e., the pin is us ed to exit flash*freeze mode when deasserted. exiting flash*freeze mode i/os and globals ? while exiting flash*freeze mode, inputs and globals will exit their flash*freeze state asynchronously to each other. as a result, clock and data glitches and narrow pulses may be generated while exiting flash*freeze mode, unless clock gating schemes are used. ? i/o banks are not all activated simultaneously when exiting flash*fr eeze mode. this can cause clocks and inputs to become enabled at different times, result ing in unexpected data being captured. ? upon exiting flash*freeze mode, inputs and glob als will no longer be tied high internally (does not apply to input hold state on igloo pl us). if any of these signals are driven low or tied low externally, they will experience a high-to-low trans ition internally when exiting flash*freeze mode. ? applies only to igloo plus: output hold state is asynchronously controlled by the signal driving the output buffer (output signal). this ensures a clean, glit ch-free transition from hold state to output drive. however, any gl itches on the output si gnal during exit from flash*freeze mode may result in glitches on the output pad. ? the above situations can cause glitches or invalid data to be clocked into and preserved in the device. refer to the "flash*freeze design guide" on page 2-13 for solutions. plls ? if the embedded pll is used, the design mu st allow maximum acquisition time (per device datasheet) for the pll to acquire the lock signal. flash*freeze pin locations refer to the pin descriptions chapter of the handbook for info rmation regarding flash*freeze pin location on the available packages. the flash*fr eeze pin location is independent of the device, allowing migration to larger or smaller device s while maintaining the sa me pin location on the board.
actel?s flash*freeze technology and low-power modes v2.1 2-11 sleep and shutdown modes sleep mode actel igloo, igloo plus, proasi c3l, and rt proasic3 fpgas support sleep mode when device functionality is no t required. in sleep mode, th e fpga core voltage supply (v cc ) is turned off (either grounded or floated) while other power supplies are left on, resulting in the fpga core being turned off to reduce power consum ption. while the device is in sl eep mode, the rest of the system can still be operating and driving the input buffer s of the device. the driven inputs do not pull up the internal power pl anes, and the current draw is li mited to minimal leakage current. table 2-7 shows the power supply statu s in sleep mode. when the v cc power supply is powered off, the corresponding power pin ca n be left floating or grounded. refer to the "power-up/-down behavior" section on page 2-12 for more information about i/o states during sleep mode and the timing diagram for entering and exiting sleep mode. shutdown mode shutdown mode is supported for all igloo plus devices, agl015, agl030, agle600, agle3000, and a3pe3000l. shutdown mode can be used by tu rning off all power supp lies when the device function is not needed. cold-sparing and hot-insertion features enable these devices to be powered down without turning of f the entire system. when powe r returns, the live-at-power-up feature enables operation of the device a fter reaching the volt age activation point. using sleep and shutdow n modes in the system depending on the power supply an d the components used in an application, there are many ways to power on or off the power supplies connected to the de vice. for example, figure 2-6 shows how a microprocessor can be used to control a power fet. actel recomme nds that power fets with low resistance be used to perform the switching action. table 2-7 ? sleep mode?power supply requirement fo r igloo, igloo plus, proasic3l, and rt proasic3 devices power supplies power supply state v cc powered off v cci = vmv powered on v jtag powered on v pump powered on figure 2-6 ? controlling power-on/-of f state using microprocessor and power fet microprocessor power-on/off control signal 1.2 / 1.5 v power supply igloo, igloo plus, or proasic3l devices v cc pin p-channel power fet
actel?s flash*freeze techn ology and low-power modes 2-12 v2.1 figure 2-7 shows how a micropro cessor can be used with a volt age regulator?s shutdown pin to turn on or off the power supp lies connected to the device. power-up/-down behavior by design, all igloo, igloo plus, proasic3l, and rt proasic3 i/os are in tristate mode before device power-up. the i/os remain tri stated until the last voltage supply (v cc or v cci ) is powered to its activation level. after the last supply reaches its functional le vel, the outputs exit the tristate mode and drive the logic at the input of the output buffer. the behavior of user i/os is independent of the v cc and v cci sequence or the state of othe r voltage supplies of the fpga (v pump and v jtag ). during power-down, device i/os beco me tristated once the first power supply (v cc or v cci ) drops below its deactivation voltage level. the i/o behavior during power-down is also independent of voltage supply sequencing. figure 2-8 shows a timing diagram when the v cc power supply crosses the activation and deactivation trip points in a typical application when the v cc power supply ramp-rate is 100 s (ramping from 0 v to 1.5 v in th is example). this is the timing di agram for the fpga entering and exiting sleep mode, as this function is dependent on powering v cc down or up. depending on the ramp-rate of the power supply an d board-level configurations, the user can easily calculate how long it will take for the core to become inacti ve or active. for more information, refer to power- up/-down behavior of low-power flash devices . figure 2-7 ? controlling power-on/-off state using microprocessor and voltage regulator igloo, igloo plus, or proasic3l device shutdown control signal for v cc v cc power pin v cci power pin voltage regulator microprocessor power supply shutdown control signal for v cci figure 2-8 ? entering and exiting sleep mode, typical timing diagram activation trip point va = 0.85 0.25 v deactivation trip point vd = 0.75 0.25 v v cc = 1.5 v v cc sleep mode t = 50 s t = 56.6 s
actel?s flash*freeze technology and low-power modes v2.1 2-13 context save and restore in sleep or shutdown mode in sleep mode or shutdown mode , the contents of the sram, state of the i/os, and state of the registers are lost when the device is powered off, if no other measure is taken. a low-cost external serial eeprom can be used to save and restore the contents of the device when entering and exiting sleep mode or shutdown mode. in the embedded sram initialization using external serial eeprom application note, detailed in formation and a reference design are provided for initializing the embedded sram using an exte rnal serial eeprom. the user ca n easily customize the reference design to save and restore the fpga state when entering and exiting sl eep mode or shutdown mode. the microcontroller will need to manage this activity; hence, before powering down v cc , the data will be read from the fpga and stored externally. in a similar way, after the fpga is powered up, the microcon troller will allow the fpga to load the data from external memory and restore its original state. flash*freeze design guide this section describes how designers can crea te reliable designs that use ultra-low power flash*freeze modes optimally. the section below provides guidance on how to select the best flash*freeze mode for any application. the "design solutions" section on page 2-14 gives specific recommendations on how to design and configure cl ocks, set/reset signals, and i/os. this section also gives an overview of the design flow and provides details concerning actel's flash*freeze management ip, which enables clean clock gating and housekeeping. the "additional power conservation techniques" section on page 2-20 describes board-level co nsiderations for entering and exiting flash*freeze mode. selecting the right flash*freeze mode both flash*freeze modes will br ing an fpga into an ultra-low-pow er static mode that retains register and sram content and sets i/os to a predetermined configuration. there are two primary differences that distinguish type 2 mode from type 1, and they must be considered when creating a design using flash* freeze technology. first, with type 2 mode, the de vice has an opportunity to wait for a second signal to enable activation of flash*freeze mode. this allows proces ses to complete prior to deactivating the device, and can be useful to control task completion, data preservation, accidental flash*freeze activation, system shutdown, or any other housekeeping func tion. the second signal may be derived from an external or in-to-out internal source. the second difference between type 1 and type 2 modes is that a design for type 2 mode ha s an opportunity to cl eanly manage clocks an d data activity before entering and exiting flash*freeze mode. this is particularly important when data preservation is needed, as it ensures valid data is stored prior to entering, and upon exit ing, flash*freeze mode. type 1 flash*freeze mode is idea lly suited for applications with the following design criteria: ? entering flash*freeze mode is not dependent on any signal other than the external ff pin. ? internal housekeeping is not requir ed prior to entering flash*freeze. ? the device is reset upon exit ing flash*freeze mode or intern al state saving is not required. ? state saving is required, bu t data and clock management is performed external to the fpga. in other words, incoming data is externally guaranteed an d held valid prior to entering flash*freeze mode. type 2 flash*freeze mode is idea lly suited for applications with the following design criteria: ? entering flash*freeze mode is dependent on an internal or external signal in addition to the external ff pin. ? state saving is required and incoming data is not externally guaranteed valid. ? the designer wants to use his/her own fl ash*freeze management ip for clock and data management. ? the designer wants to use his/her own flas h*freeze management logic for clock and data management.
actel?s flash*freeze techn ology and low-power modes 2-14 v2.1 ? internal housekeeping is required prior to entering flash*freeze mode. housekeeping activities may include loading data to sram, system shutdown, completion of current task, or ensuring valid flash*freeze pin assertion. there is no downside to type 2 mode, and actel's flash*freeze management ip offers a very low tile count clock and data management solution. ac tel's recommendation for most designs is to use type 2 flash*freeze mode with flash*freeze management ip. design solutions clocks ? actel recommends using a comp letely synchronous design in type 2 mode with flash*freeze management ip cleanly gate all internal and external cl ocks. this will prevent narrow pulses upon entrance and exit from flash*freeze mode ( figure 2-5 on page 2-9 ). ? upon entering flash*freeze mo de, external clocks become ti ed off high, internal to the clock pin (unless hold state is used on igloo plus), and plls will be turned off. any clock that is externally low will re alize a low to high transition internal to th e device while entering flash*freeze. if clocks will float during flas h*freeze mode, actel recommends using the weak pull-up feature. if clocks will continue to drive the device during flash*freeze mode, the clock gating (filter) available in flash*freeze management ip can help to filter unwanted narrow clock pulses upon flash*freeze mode entry and exit. ? clocks may continue to drive fpga pins while the device is in fl ash*freeze mode, with virtually no power consumption. the weak pull-up/down configuration will result in unnecessary power consumption if used in this scenario. ? floating clocks can cause totem pole currents on the input i/o circuitry when the device is in active mode. if clocks are externally gated prior to entering flash*freeze mode, actel recommends gating them to a known value (preferably '1', to avoid possible narrow pulse upon flash*freeze mode exit), and not left floating. however, during flash*freeze mode, all inputs and clocks are intern ally tied off to pr event totem pole currents, so they can be left floating. ? upon exiting flash*freeze mode, the design must allow maximum acqu isition time for the pll to acquire the lock signal, and for a pll cloc k to become active. if a pll output clock is used as the primary clock for flash*freeze mana gement ip, it is important to note that the clock gating circuit will only release other clocks after the primary pll output clock becomes available. set/reset ? since all i/os and globals are tied high in flash*freeze mode (unles s igloo plus hold state is used), actel recommends using active low se t/reset at the top-level port. if needed, the signal can be inve rted internally. ? if the intention is to always set/reset in fl ash*freeze mode, a self set/reset circuit may be implemented to accomplis h this, as shown in figure 2-9 . configure an active high set/reset input pin so it uses the internal pull-up du ring flash*freeze mode, and drives low during active mode. when the device exits flash*freeze mode, the in put will transi tion from high to low, releasing the set/reset. note that this circuit may release set/reset before all outputs become active, since outputs are enabled up to 200 ns after inputs when exiting flash*freeze mode. figure 2-9 ? flash*freeze sel f-reset circuit input pull-up s et/reset ' 0 '
actel?s flash*freeze technology and low-power modes v2.1 2-15 i/os ? floating inputs can cause totem po le currents on the input i/o ci rcuitry when th e device is in active mode. if inputs will be released (undriven) during flas h*freeze mode, actel recommends that they are only released after the device ente rs flash*freeze mode. ? as mentioned earlier, asynchronous input to ou tput paths are subject to possible glitching when entering flash*freeze mode. for example, on a direct in-to-out path, if the current state is '0' and the input bank deactivates first, the input and th en the output will transition to '1' before the output enters its flash*freeze state. this can be prev ented by using latches along with flash*freeze management ip to gate asynchronous in-to-out paths prior to entering flash*freeze mode. jtag ? the jtag state machine is powered, bu t not active during flash*freeze mode. ? tck should be held in a static state to prevent dynamic power co nsumption of the jtag circuit during flash*freeze. ? specific jtag pin tie-off recomme ndations suitable for flash* freeze mode can be found in the pin descriptions chapter of the handbook. ulsicc ? the user low static icc (uls icc) macro acts as an access po int to the hard flash*freeze technology block in the device. the ulsicc ma cro represents a hard, fixed location block in the device. when the lsicc input of the ulsicc macro is driven low, the flas h*freeze pin is blocked, and when lsicc is driven high, the flash*freeze pin is enabled. ? if the user decides to build his/her own flash*freeze type 2 clock and data management logic, note that the lsicc signal on the ulsicc macro is anded internally with the flash*freeze signal. in order to reliably en ter flash*freeze, the lsicc signal must remain asserted high while entering and during flash*freeze mode. flash*freeze management ip one of the key benefits of actel's flash*freeze mo de is the ability to preserve the state of all internal registers, sram conten t, and i/os (igloo plus only). this feature enables seamless continuation of data processing before and a fter flash*freeze, without the need to reload or reinitialize the fpga system. actel's flash* freeze management ip, available for type 2 implementation, offers a robust rtl block that ensures clean cloc k gating of all system clocks before entering and upon exiting flash*freeze mode . this ip also gives users the option to perform housekeeping prior to entering fl ash*freeze mode. this section will provide an overview of the flash*freeze management ip. additional information on this ip core can be found in the libero ide online help.
actel?s flash*freeze techn ology and low-power modes 2-16 v2.1 the flash*freeze management ip is comprised of three blocks: the flash*freeze finite state machine (fsm), the clock gating (filter) block, and the ulsicc macro, as shown in figure 2-10 . flash*freeze management fsm the flash*freeze fsm block is a simple, robust, fully encoded 3-bit state ma chine that ensures clean entrance and exit from flash*freeze mode by controlling activities of the clock gating, ulsicc, and optional housekeeping blocks. the state diagram for the fsm is shown in figure 2-12 on page 2-18 , below. in normal operation, the state machine waits for flash*freeze pin assertion, and upon detection of a request, it waits for a short period of time to ensure the assertion persists; then it asserts wait_houseke eping (active high) synchronous to the user?s designated system clock. this flag can be used by user logic to perform any needed shutdown processes prior to entering flash*freeze mode, su ch as storing data into sram, notifying other system components of the reques t, or timing/validating the flas h*freeze reque st. the fsm also asserts flash_freeze _enabled whenever the device enters fl ash*freeze mode. th is occurs after all housekeeping and clock gating functions have completed. the flash_freeze _enabled signal remains asserted, even during flash*freeze mode , until the flash*freeze pin is deasserted. use the flash_freeze_enabled signal to drive any logic in the design th at needs to be in a particular state during flash*freeze mo de. the done_housekeeping (act ive high) signal should be asserted to notify the fsm when all the housekeepin g tasks are completed. if the user chooses not to use housekeeping, the fl ash*freeze management ip core generator in libero ide will connect wait_housekeepi ng to done_housekeeping. figure 2-10 ? flash*freeze management ip block diagram flash * freeze te c hnolo g y flash * freeze pin inbuf _ff user desi g n c onne c t to top-level port ul s i cc ma c ro flash * freeze mana g ement ip flash * freeze f s m inbuf house - keepin g (optional) c lo c k g atin g (filter) from array to array net lo g i c al c onne c tion har d wire d c onne c tion le g end c lkint c lkint a c tel i g loo, i g loo plu s , proa s i c 3l, or rt proa s i c 3 devi c e
actel?s flash*freeze technology and low-power modes v2.1 2-17 clock gating block once done_housekeeping is detected, the fsm will initiate the clock gating circuit by asserting assert_gate (active low). assert_gate is named control_user_clock_net in the ip block. upon assertion of the assert_gate signal, the clock will be gated in less than 2 cycles. the clock gating circuit is comprised of a flip-flop, la tch, and gate, and cl kint, as shown in figure 2-11 . the clock gating block can support gating of up to 17 clocks. after initiating the clock gating circuit, the fsm wi ll assert and hold the lsi cc signal (active high), feeding the ulsicc macro. this will initiate the 1 s entran ce into flash* freeze mode. upon deassertion of the flash*freeze pin, the fsm will set a ssert_gate high. once the i/o banks become active, the clock will enter the device , and register the assert_gate signal, cleanly releasing the clock gate. design flow 1 actel has developed a convenient and intuitive design flow fo r configuring and integrating flash*freeze technology into an fpga design. flash*freeze type 1 is implemented by instantiating the inbuf_ff macro in the top level of a design. fl ash*freeze type 2 with management ip can be generated by the libero ide core generator or smartgen and instantiated as a single block in the user's design. this si ngle block will include an inbuf_ff macro and the optional flash*freeze management ip, which includes th e ulsicc macro. if designers do not wish to use this core generator, the inbuf_ff macro and the optional ulsicc macro may be instantiated in the design, and custom flash*freeze management ip can be developed by the user. the remainder of this section will cover configuratio n details of the inbuf_ff macro, the ulsicc macro, and the flash*freeze management ip. additional information on the tools discussed with in this section may be found in the libero ide online help. inbuf_ff the inbuf_ff macro is a special-purpose input buff er macro that is interp reted downstream in the design flow by actel's de signer software. when this macro is used, the top-level port will be forced to the dedicated ff pin in the fpga, and flash*fr eeze mode will be available for use in the device. the following are the design rules for inbuf_ff: ? if inbuf_ff is not used in the design, the device will not be configured to support flash*freeze mode. ? when the inbuf_ff macro is used , the ff pin will establish a hardwired connec tion to the flash*freeze technology circuit in the device, as shown in figure 2-1 on page 2-5 , figure 2-3 figure 2-11 ? clock gating circuit 1. this section applies to libero ide / designer v8.3 and later. actel recommends that designs created in earlier versions of the software be modified to accommodate this flow by instantiating the inbuf_ff macro or the flash*freeze management ip. refer to the libero ide / designer v8.3 release notes and the libero ide online help for more information on migrating design s from older software versions. f*f fsm assert_gate d q flip-flop latch and d q clk g clkint system clock
actel?s flash*freeze techn ology and low-power modes 2-18 v2.1 on page 2-6 , and figure 2-10 on page 2-16 and described "flash*freeze type 1: control by dedicated flash*freeze pi n" section on page 2-4 . ? the inbuf_ff must be driven by a to p-level input port of the design. ? the inbuf_ff and the ulsicc ma cro must be used to enable type 2 flash*freeze mode. ? for type 2 flash*freeze mo de, the inbuf_ff must drive some logic in the design. ? for type 1 flash*freeze mode, the inbuf_ff may drive some logi c in the design, but it may also be left floating. ? only one inbuf_ff may be in stantiated in a device. ? the ff pin threshold voltages are defined by v cci and the supported single-ended i/o standard in the corresponding i/o bank. ? the ff pin schmitt trigger option may be config ured in the i/o attrib ute editor in actel's designer software. the schmitt trigger option is only available for iglooe, igloo plus, proasic3el, and rt proasic3 devices. figure 2-12 ? fsm state diagram s ystem reset deassert ul s i cc un- g ate user c lo c ks fail s afe dummy s tate 2 fail s afe dummy s tate 1 turn on user c lo c k ul s i cc tri gg er ul s i cc wait on flash * freeze persistent flash * freeze house keepin g re q uest to user lo g i c s top c lo c k to user tri gg er ul s i cc g ate user c lo c ks flash * freeze asserte d flash * freeze asserte d flash * freeze asserte d g ate d c lo c k to user desi g n c lo c k g atin g c ir c uit user c lo c k s afe to turn off c lo c k from user lo g i c house-keepin g re q uest to user lo g i c flash * freeze deasserte d flash * freeze deasserte d flash * freeze deasserte d flash * freeze deasserte d flash * freeze deasserte d flash * freeze deasserte d flash * freeze deasserte d
actel?s flash*freeze technology and low-power modes v2.1 2-19 ? a 2 ns glitch filter resides in the flash*freeze technology block to filter unwanted glitches on the ff pin. ulsicc the user low static icc (ulsicc) macro allows the fpga core to access the flash*freeze technology block so that entering and exiting flash*freeze mode can be controlled by the user's design. the ulsicc macro enables a hard block with an available lsicc input port, as shown in figure 2-3 on page 2-6 and figure 2-10 on page 2-16 . design rules for the ulsi cc macro are as follows: ? the ulsicc macro by itself cannot enable fl ash*freeze mode. the inbuf_ff and the ulsicc macro must both be used to en able type 2 flash*freeze mode. ? the ulsicc controls entering the flash*freeze mode by assert ing the lsicc input (logic '1') of the ulsicc macro. the ff pin must also be as serted (logic '0') to enter flash*freeze mode. ? when the lsicc signal is '0', the device cann ot enter flash*freeze mode; and if already in flash*freeze mode, it will exit. ? when the ulsicc macro is not instantiated in the user's design, the lsicc port will be tied high. flash*freeze management ip the flash*freeze management ip can be config ured with the libero ide (or smartgen) core generator in a simple, intuitive in terface. with the core configur ation tool, users can select the number of clocks to be gated, and select whether or not to implement housekeeping. all port names on the flash*freeze management ip block can be renamed by the user. ? the clock gating (filter) blocks include clkint buffers for each gated clock output (version 8.3). ? when housekeeping is not used, the wait_hou sekeeping signal will be automatically fed back into done_housekeeping inside the core, and the ports will not be available at the ip core interface. ? the inbuf_ff macro is au tomatically inst antiated within the ip core ? the inbuf_ff port (default na me is "flash_freeze_n ") must be connec ted to a top-level input port of the design. ? the ulsicc macro is automatically instantiate d within the ip core, and the lsicc signal is driven by the fsm. ? timing analysis can be performed on the clock do main of the source cloc k (i.e., input to the clock gating filters). for example, if cl kin becomes clkin_gated, the timing can be performed on the clkin do main in smarttime. ? the gated clocks can be added to the clock li st if the user wishes to analyze these clocks specifically. the user can locate the gated cloc ks by looking for instanc e names such as those below: top/ff1/ff_1_wrapper_inst/user_ff_1_wrapper/primary_filter_instance/latch_for_clock_ga ting:q top/ff1/ff_1_wrapper_inst/user_ff_1_wrapper/genblk1.genblk2.secondary_filter[0].second ay_filter_instance/latch_for_clock_gating:q top/ff1/ff_1_wrapper_inst/user_ff_1_wrapper/genblk1.genblk2.secondary_filter[1].second ay_filter_instance/latch_for_clock_gating:q ? there will be added skew and clock insertion de lay due to the clock ga ting circuit. the user should analyze external setu p/hold times carefully. the us er should also ensure the additional skew across the clock gating filter circuit is accounted for in an y paths where the launch register is driven from the filter input clock and captured by a register driven by the gated clock filter output clock.
actel?s flash*freeze techn ology and low-power modes 2-20 v2.1 power analysis smartpower identifies static and dynamic power consumption problems quickly within a design. it provides a hierarchical view, allowing users to drill down and estimate the power consumption of individual components or events. smartpower an alyzes power consumption for nets, gates, i/os, memories, clocks, cores, clock domains, power supply rails, peak power during a clock cycle, and switching transitions. smartpower generates detailed hierarchical repo rts of the dynamic power consumption of a design for easy inspection . these reports include design-level po wer summary, average switching activity, and ambient and junction temperat ure readings. input the target cl ock and data frequencies for a design, and let smartpower perform a detailed and accurate power analysis . smartpower supports importing files in the vc d (value-change dump) format as sp ecified in the ieee 1364 standard. it also supports the synopsys? switch ing activity interchange format (saif) standard. support for these formats lets designers generate switching activity information in a variety of simulators and then import this information directly into smartpower. for portable or battery operated applications, a power profile feature enables you to measure power and battery life, based on a sequence of operational modes of the design. in most portable and battery-operated applications, the system is se ldom fully "on" 100 percent of the time. "on" is a combination of fully active, standby, sleep, or other functional modes. smartpower allows users to create a power profile for a design by specifyi ng operational modes and the percent of time the device will run in each of the modes. power is ca lculated for each of the modes, and total power is calculated based on the weig hted average of all modes. smartpower also provides an estimated batter y life based on the power profile. the current capacity for a given battery is in put and used to estimate the life of the battery. the result is an accurate and realistic indi cation of battery life. more information on smartpower ca n be found on the actel website: http://www.actel.com/products/so ftware/libero/smartpower.aspx . additional power conservation techniques igloo and proasic3l fpgas provide many ways to inherently conser ve power; however, there are also several design techniques that can be used to reduce power on the board. ? actel recommends that the designer use the minimum number of i/o banks possible and tie any unused power supplies (such as v ccpll , v cci , vmv, and v pump ) to ground. ? leave unused i/o ports floating. unused i/os are configured by the software as follows: ? output buffer is disabled (with tristate value of high impedance) ? input buffer is disabled (with tristate value of high impedance) ? use the lowest availabl e voltage i/o standard, the lowest drive strength, and the slowest slew rate to reduce i/o switching contribution to power consumption. ? advanced and pro i/o banks may consume slightly higher static current than standard and standard plus banks?avoid using advanced and pro banks whenever practical. ? the small static power benefit obtained by avoiding advanced or pro i/o banks is usually negligible compared to the benefit of using a low-power i/o standard. ? deselect ram blocks that are not being used. ? only enable read and write ports on ram blocks when they are needed. ? gating clocks low offers improved static power of ram blocks. ? drive the ff port of ram blocks with the fl ash_freeze_enabled signal from the flash*freeze management ip. ? drive inputs to the full voltage level so that all transistors are turned on or off completely. ? avoid using pull-ups and pull-downs on i/os because these resistors draw some current. avoid driving resistive loads or bipolar transi stors, since these draw a continuous current, thereby adding to the static current. ? when partitioning the design across multip le devices, minimize i/o usage among the devices.
actel?s flash*freeze technology and low-power modes v2.1 2-21 prototyping for igloo and proa sic3l devices using proasic3 prototyping in proasic3 does no t apply for the igloo plus family . the igloo, proasic3l, and proasic3 families are architectu rally compatible with the except ion of the flash*freeze technology implementation and the flash*fr eeze pin available on the iglo o and proasic3l devices. for example, the agl125 user can start prototyping wi th the a3p125, since the devices share the same features and pinout, except for the flash*freeze pin. the pin in that location for proasic3 devices is an i/o pin. if flash*freeze mode will be used in the ig loo or proasic3l device , prototyping using the equivalent proasic3 device could implement a flas h*freeze testing pin at the same location in the proasic3 package as the actual flash*freeze pin on the igloo or proasic3l device, as listed in table 2-8 . you can use the flash*freeze testing pin on pr oasic3 devices to activate the ulsicc macro internally. migrating to the igloo device is easy, as the timing of the exte rnally controlled ulsicc macro is similar to that of the flash*freeze pin. keep in mind that the acti vation trigger for the ulsicc macro is active high, whereas the activation trigger for the flash*fr eeze pin is active low. this means that to emulate en tering flash*freeze mode using the ulsicc macro in a proasic3 device, the external signal sh ould be inverted at the input. if flash*freeze mode will not be used, the flash*free ze pin can still be used as a regular user i/o, making it possible to use the same pcb for both the igloo and proasic3l families. table 2-8 provides detailed information on prototyping for igloo and proasic3l families. table 2-8 ? prototyping/migration solutions scenario board-level software/designer prototype with existing proasic3 devices and plan to migrate to igloo or proasic3l devices to take advantage of ultra-low power consumption. flash*freeze feature is not needed. since the flash*fr eeze pin is not used, the board layout is the same for all igloo and proasic3 families. note: use 1.5 v v cc for igloo and proasic3. igloo and proasic3l can support both 1.5 v and 1.2 v core voltage. the 1.2 v core voltage results in lower power consumption. 1. open the proasic3 adb file in designer. 2. export the netlist and pdc files. 3. create a new adb file targeting the igloo or proasic3l device and import the files created in step 2. 4. run compile (disable flash*freeze mode), run layout , and perform post-layout simulation and timing analysis. prototype with existing proasic3 devices and plan to migrate to igloo or proasic3l devices to take advantage of ultra-low power consumption. flash*freeze mode will be used to reduce power consumption when device function is not needed. ulsicc mode is optional. users must ensure the equivalent flash*freeze pin location is not used as a user i/o. note: use 1.5 v v cc for igloo and proasic3. igloo and proasic3l can support both 1.5 v and 1.2 v core voltage. the 1.2 v core voltage results in lower power consumption. 1. open the proasic3 adb file in designer. 2. export the netlist and pdc files. 3. if needed, create a pdc file to define the flash*freeze mode i/o state and port name for the flash*freeze pin. 4. create a new adb file targeting the igloo or proasic3l devices and import the files created in step 2. 5. run compile (enable flash*freeze mode), run layout , and perform post-layout simulation and timing analysis. note: device migration is not supported for igloo plus devices .
actel?s flash*freeze techn ology and low-power modes 2-22 v2.1 export files to export the netlist and constraint files from design er, follow the steps below: 1. export the netlist in designer. file > export > netlist files > *.edn 2. export the pdc file in designer. file > export > constraint files > *.pdc > select complete placement information ( figure 2-13 ). table 2-9 and table 2-10 on page 2-23 show the device-to-device and packages compatibility list. figure 2-13 ? export netlist table 2-9 ? device migration?igloo supported packages in proasic3 devices package a3p030 agl030 a3p060 agl060 a3p125 agl125 a3p250 agl250 a3p600 agl600 a3p1000 agl1000 a3pe600 agle600 a3pe3000 agle3000 qn132 ???? vq100 ???? fg144 ???? ? cs196 igloo and iglooe devices only fg256 proasic3 only ?? ? fg484 ?? ? ? fg896 ? note: igloo plus and rt proasic3 do not support device migration.
actel?s flash*freeze technology and low-power modes v2.1 2-23 conclusion actel igloo, igloo plus, proasic3l, and rt proasic3 family archit ectures are designed to achieve ultra-low power consumption based on enhanced nonvolatile and live-at-power-up flash-based technology. power consumption can be reduced further by using flas h*freeze, static (idle), sleep, and shutdown power modes. all these features resu lt in a low-power, cost -effective, single-chip solution designed specifically for power-sensitive and battery-operated elec tronics applications. related documents application notes embedded sram initialization using external serial eeprom http://www.actel.com/documen ts/embeddedsraminit_an.pdf handbook documents power-up/-down behavior of low-power fl ash devices http://www.actel.com/docum ents/lpd_powerup_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage information to reduce duplicat ion and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-004-5 revised october 2008 table 2-10 ? device migration?proasic3l supporte d packages in proasic3 devices package a3p250 a3p250l a3p600 a3p600l a3p1000 a3p1000l a3pe3000 a3pe3000l vq100 ? pq208 ???? fg144 ??? fg256 ??? fg324 proasic3l only fg484 ??? fg896 ? note: igloo plus and rt proasic3 do not support device migration.
actel?s flash*freeze techn ology and low-power modes 2-24 v2.1 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v2.1) page v2.0 (october 2008) the "flash*freeze management fsm" section was updated with the following information: the fsm also asserts flas h_freeze_enabled wh enever the device enters flash*freeze mode. this occurs after all housekeeping and clock gating functions have completed. 2-16 v1.3 (june 2008) the title changed from "flash*freez e technology and low-power modes in igloo, igloo plus, and proasic3l devices" to actel?s flash*freeze technology and low-power modes." n/a the "actel?s flash families support th e flash*freeze feature" section was updated. 2-2 significant changes were made to this document to support libero ide v8.4 and later functionality. rt proasic3 device support information is new. in addition to the other major changes, the following tables and figures were updated or are new: figure 2-3 flash*freeze mode type 2 ? controlled by flash*freeze pin and internal logic (lsicc signal) ? updated figure 2-5 narrow clock pulses duri ng flash*freeze entrance and exit ? new figure 2-10 flash*freeze management ip block diagram ? new figure 2-12 fsm state diagram ? new table 2-6 igloo plus flash*freeze mode (type 1 and type 2)?i/o pad state ? updated please review the entire document carefully. 2-6 2-9 2-16 2-18 2-8 v1.2 (march 2008) the family description for proasic3l in table 2-1 low-power flash families was updated to include 1.5 v. 2-2 v1.1 (february 2008) the part number for this document was changed from 51700094-003-1 to 51700094-004-2. n/a the title of the document was changed to "flash*freeze te chnology and low- power modes in igloo, igloo plus, and proasic3l devices." n/a the "flash*freeze technology an d low-power modes" section was updated to remove the parenthetical phrase, "from 25 w," in the second paragraph. the following sentence was added to the third paragraph: "igloo plus has an additional feature when operating in fl ash*freeze mode, a llowing it to retain i/o states as well as sram and register states." 2-1 the "power conservation techniques" section was updated to add v jtag to the parenthetical list of power supplies that should be tied to the ground plane if unused. additi onal information was added regarding how the software configures unused i/os. 2-1 table 2-1 low-power flash families and the accompanying text was updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 2-2 the "flash*freeze mode" section was revised to include that i/o states are preserved in flash*freeze mode for igloo plus devices. the last sentence in the second paragraph was changed to, "if the ff pin is not used, it can be used as a regular i/o." the following sent ence was added for flash*freeze mode type 2: "exiting the mode is controlle d by either the ff pin or the user- defined lsicc signal." 2-4
actel?s flash*freeze technology and low-power modes v2.1 2-25 v1.1 (continued) the "flash*freeze type 1: control by de dicated flash*free ze pin" section was revised to change instructions for implementing this mode, including instructions for implementati on with libero ide v8.3. 2-4 figure 2-1 flash*freeze mode type 1 ? controlled by th e flash*freeze pin was updated. 2-5 the "refer to table 2-3 for flash*freeze (ff) pin and lsicc signal assertion and deassertion values." section was renamed from "type 2 software implementation." 2-6 the "type 2 software implementation for libero ide v8.3" section is new. 2-6 figure 2-3 flash*freeze mode type 2 ? controlled by flash*freeze pin and internal logic (lsicc signal) was updated. 2-6 figure 2-4 flash*freeze mode type 2 ? timing diagram was revised to show deasserting lsicc after the device has exited flash*freeze mode. 2-7 the "igloo plus i/o state in flash*freeze mode" section was added to include information for igloo plus devices. table 2-6 igloo plus flash*freeze mode (type 1 an d type 2)?i/o pad state is new. 2-7 , 2-8 the "during flash*freeze mode" section was revised to in clude a new bullet pertaining to output behavior for ig loo plus. the bullet on jtag operation was revised to provide more detail. 2-10 figure 2-6 controlling power-on/-off state using microprocessor and power fet and figure 2-7 controlling power-on/-off state using microprocessor and voltage regulator were updated to include igloo plus. 2-11 , 2-12 the first sentence of the "shutdown mode" section was updated to list the devices for which it is supported. 2-11 the first paragraph of the "power-up/-down behavior" section was revised. the second sentence was changed to, "th e i/os remain tristated until the last voltage supply (v cc or v cci ) is powered to its activation level." the word "activation" replaced the word "functional." the sentence, "during power- down, device i/os become tristated once the first power supply (v cc or v cci ) drops below its deactivation volt age level" was revised. the word "deactivation" replaced the word "brownout." 2-12 the "prototyping for igloo and proasic3 l devices using pr oasic3" section was revised to state that prototyping in proasic3 does not apply for the igloo plus family. 2-21 table 2-8 prototyping/migration solutions , table 2-9 device migration? igloo supported packages in proasic3 devices , and table 2-10 device migration?proasic3l supported pa ckages in proasic3 devices were updated with a table note stating that device migration is not supported for igloo plus devices. 2-21 , 2-23 the text following table2-10device migrat ion?proasic3l supported packages in proasic3 devices was moved to a new section: the "flash*freeze design guide" section . 2-13 v1.0 (january 2008) table 2-1 low-power flash families was updated to remove the proasic3, proasic3e, and automoti ve proasic3 fa milies, which were incorrectly included. 2-2 previous version changes in current version (v2.1) page
actel?s flash*freeze techn ology and low-power modes 2-26 v2.1 51900147-2/5.07 detailed descriptions of low- power modes are described in the advanced datasheets. this application note was updated to describe how to use the features in an igloo/e application. n/a figure 2-1 flash*freeze mode type 1 ? controlled by th e flash*freeze pin was updated. 2-5 figure 2-2 flash*freeze mode type 1 ? timing diagram is new. 2-5 steps 4 and 5 are new in the "refer to table 2-3 for fl ash*freeze (ff) pin and lsicc signal assertion and deassertion values." section . 2-6 51900147-1/3.07 in the following sentence, located in the "flash*freeze mode" section , the bold text was changed from active high to active low. the flash*freeze pin ( active low ) is a dedicated pin used to enter or exit flash*freeze mode directly, or alternativ ely the pin can be routed internally to the fpga core to allow the user's logic to de cide if it is safe to transition to this mode. 2-4 figure 2-2 flash*freeze mode type 1 ? timing diagram was updated. 2-5 information about ulsi cc was added to the "prototyping for igloo and proasic3l devices usin g proasic3" section . 2-21 51900147-0/8.06 in the "flash*freeze mode" section , "active high" was changed to "active low." 2-4 the "prototyping for igloo and proasic3 l devices using pr oasic3" section was updated with information conc erning the flash*freeze pin. 2-21 previous version changes in current version (v2.1) page
global resources and clock conditioning

v1.3 3-1 3 ? global resources in actel low-power flash devices introduction actel igloo, ? fusion, and proasic ? 3 fpga devices offer a powerful, low-delay versanet global network scheme and have extensiv e support for multiple clock doma ins. in addition to the clock conditioning circuits (cccs) and phase-locked lo ops (plls), there is a co mprehensive global clock distribution network called a versanet global netw ork. each logical elemen t (versatile) input and output port has access to these global networks . the versanet global networks can be used to distribute low-skew clock signals or high-fanout ne ts. in addition, these hi ghly segmented versanet global networks offer users the flexibility to create low-skew local netw orks using spines. this document describes versanet global networks and discusses how to assign signals to these global networks and spines in a design flow. details conc erning low-power flash de vice plls are described in clock conditioning circuits in igloo and proasic3 devices . this document describes the low-power flash devices? global architecture and uses of these global networks in designs. global architecture low-power flash devices offer powerful and flexible control of circuit timing through the use of analog circuitry. each chip has up to six cccs, some with plls. ? in iglooe, proasic3el, and proasic3e devices, all cccs have plls?hence, 6 plls per device. ? in igloo, igloo plus, proasic3l, and proasic3 devices, the west ccc contains a pll core (except in 15 k and 30 k devices). ? in fusion devices, the west cc c also contains a pll core. in the two larger devices (afs600 and afs1500), the west and ea st cccs each contain a pll. each pll includes delay lines, a phase shifter (0, 90, 180, 270), and cl ock multipliers/dividers. each ccc has all the circuitry needed for the selection and interconnection of inputs to the versanet global network. the east and west cccs each have access to three versanet global lines on each side of the chip (six global lines total). the cccs at the four corners each have access to three quadrant global lines in each quadrant of the chip (except in 15 k gate and 30 k gate devices). in 15 k and 30 k gate devices, all six versanet gl obal lines are driven fr om three southern i/os, located toward the east and west si des. each of these tiles can be configured to select a central i/o on its respective side or an inte rnal routed sign al as the input signal. 15 k and 30 k gate devices do not support any clock conditioning circuitry, nor do they contain the versanet global network concept of top and bottom spines. the flexible use of the versanet global network allows the desi gner to address several design requirements. user applications th at are clock-resource-intensive can easily route external or gated internal clocks using versanet global routing netw orks. designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the versanet global network. the following sections give an overview of the versanet global network, the structure of the global network, and the clock aggregation feature that enables a design to have very low clock skew using spines.
global resources in actel low-power flash devices 3-2 v1.3 global resource support in low-power devices the low-power flash families listed in table 3-1 support the global reso urces and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 3-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 3-1 . where the informati on applies to only one fa mily or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 3-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
global resources in actel low-power flash devices v1.3 3-3 versanet global network distribution one of the architectural benefits of low-power flash architecture is the set of powerful, low-delay versanet global networks that can access the versatiles, sram, an d i/o tiles of the device. each device offers a chip global networ k with six global lines that are distributed from th e center of the fpga array. in addition, each device, (except th e 15 k and 30 k gate device), has four quadrant global networks, each with three regional global line resources. these quadrant global networks can only drive a signal inside their own quadrant. each core versatile has access to nine global line resources?three quadrant and six chip-wide (main) global networks?and a total of 18 globals are available on the device (3 4 region al from each quadrant and 6 global). figure 3-1 shows simplified devi ce architecture, and figure 3-2 on page 3-4 shows an overview of the versanet global networks. the versanet global networks are segmented and consist of versanet glob al networks, spines, global ribs, and global multiplexers (muxes), as shown in figure 3-1 . the global networks are driven from the global rib at the center of the die or quadrant global networks at the north or south side of the die. the global network uses th e mux trees to access the spine, and the spine uses the clock ribs to ac cess the versatile. access is available to the chip or quadrant global networks and the spines through th e global muxes. access to the spine using the global muxes is explained in the "spine architecture" section on page 3-4 . these versanet global networks offer fast, lo w-skew routing resources for high-fanout nets, including clock signals. in addition, these high ly segmented global networks offer users the flexibility to create low-skew loca l networks using spines for up to 252 internal/external clocks or other high-fanout nets in low-power flash device s. optimal usage of these low-skew networks can result in significant improv ement in design performance. note: not applicable to 15 k and 30 k gate devices figure 3-1 ? overview of versanet global network and device architecture pa d rin g pa d rin g pa d rin g i/o rin g i/orin g c hip (main) g lo b al pa d s g lo b al pa d s hi g h-performan c e g lo b al network g lo b al s pine g lo b al ri b s sc ope of s pine (sha d e d area plus lo c al rams an d i/os) s pine- s ele c tion mux em b e dd e d ram blo c ks lo g i c tiles top s pine bottom s pine t1 b1 t2 b2 t3 b3 qua d rant g lo b al pa d s
global resources in actel low-power flash devices 3-4 v1.3 spine architecture the low-power flash device archit ecture allows the versanet glob al networks to be segmented. each of these networks contains spines (the vertical branches of the global network tree) and ribs that can reach all the versatiles inside its region . the nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global netw ork, which has six spines. note that there are three quadrant spines in each qu adrant of the device (except in 15 k and 30 k gate devices). there are four quadrant global network regions per device. in 15 k and 30 k gate devices, there is no quadrant clock network, so there are only six spin es in each spine tree. th e spines are the vertical branches of the global network tree, shown in figure 3-2 . each spine in a vertical co lumn of a chip (main) global network is further divided into two equal- length spine segments: on e in the top and one in the bottom half of the die (except in 15 k and 30 k gate devices). top and bottom spine segments radiating from the center of a device have the same height. however, just as in the proasic plus ? family, signals assigned only to the top and bottom spine cannot access the middle two rows of the die. the spines for quadrant clock networks do not cross the middle of the die and cannot access the middle two rows of the architecture. each spine and its associated ribs cover a certain area of the device (the "scope" of the spine; see figure 3-2 ). each spine is accessed by the dedicated global networ k mux tree architecture, which defines how a particular spine is driven?either by the signal on the global network from a ccc, for example, or by another net defined by the user. details of the chip (main) global network spine- selection mux are presented in figure 3-4 on page 3-7 . the spine drivers for each spine are located in the middle of the die. quadrant spines can be driven from user i/os on th e north and south sides of the die. the ability to drive spines in the quadrant glob al networks can have a significan t effect on system performance for high-fanout inputs to a design . access to the top quadrant spine regions is from the top of the die, and access to the bottom qu adrant spine regions is from the bottom of the die. the a3pe3000 device has 28 clock trees and each tree has nine spines; this flexible global network architecture enables users to map up to 252 different inte rnal/external clocks in an a3pe3000 device. note: not applicable to 15 k and 30 k gate devices. figure 3-2 ? simplified versanet global network north quadrant global network south quadrant global network chip (main) global network 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc ccc ccc ccc ccc ccc
global resources in actel low-power flash devices v1.3 3-5 spine access the physical location of each sp ine is identified by the letter 't' (top) or 'b' (bottom) and an accompanying number (t n or b n ). the number n indicates the horizontal location of the spine; 1 refers to the first spine on the left side of the die. since there are six chip spines in each spine tree, there are up to six spines available fo r each combination of 't' (or 'b') and n (for example, six t1 spines). similarly, there are three quadrant spines available for each combination of 't' (or 'b') and n (for example, four t1 spines), as shown in figure 3-3 on page 3-6 . table 3-2 ? globals/spines/rows for ig loo and proasic3 devices proasic3/ proasic3l devices igloo devices chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatile s rows in each spine a3p015 agl015 6 0 1 9 9 384 384 12 a3p030 agl030 6 0 2 9 18 384 768 12 a3p060 agl060 6 12 4 9 36 384 1,536 12 a3p125 agl125 6 12 8 9 72 384 3,072 12 a3p250/l agl250 6 12 8 9 72 768 6,144 24 a3p400 6 12 12 9 108 768 9,216 24 a3p600/l agl600 6 12 12 9 108 1,152 13,824 36 a3p1000/l agl1000 6 12 16 9 144 1,536 24,576 48 a3pe600/l agle600 6 12 12 9 108 1,120 13,440 35 a3pe1500 6 12 20 9 180 1,888 37,760 59 a3pe3000/l agle3000 6 12 28 9 252 2,656 74,368 83 table 3-3 ? globals/spines/rows fo r igloo plus devices igloo plus devices chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatiles rows in each spine aglp030 6 0 2 9 18 384* 792 12 aglp060 6 12 4 9 36 384* 1,584 12 aglp125 6 12 8 9 72 384* 3,120 12 note: *clock trees that are located at far left and far right will support more versatiles. table 3-4 ? globals/spines/rows for fusion devices fusion device chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatiles rows in each spine afs090 6 12 6 9 54 384 2,304 12 afs250 6 12 8 9 72 768 6,144 24 afs600 6 12 12 9 108 1,152 13,824 36 afs1500 6 12 20 9 180 1,920 38,400 60
global resources in actel low-power flash devices 3-6 v1.3 spines are also called local clocks, and are ac cessed by the dedicated global mux architecture. these muxes define how a particu lar spine is driven. refer to figure 3-4 on page 3-7 for the global mux architecture. the muxes for each chip global spine are located in the middle of the die. access to the top and bottom chip global spine is available from the middle of the die. there is no control dependency between the top and bottom spines. if a top spine, t1, of a chip global network is assigned to a net, b1 is not wasted and can be used by the global clock network. the signal assigned only to the top or bottom sp ine cannot access the mi ddle two rows of the architecture. however, if a spin e is using the top and bottom at the same time (t1 and b1, for instance), the previous restriction is lifted. the muxes for each quadrant global spine are located in the north and south sides of the die. access to the top and bottom quadrant global sp ines is available from th e north and south sides of the die. since the muxes for quadrant spines are located in the north and south sides of the die, you should not try to drive t1 and b1 quadrant spines from the same signal. figure 3-3 ? chip global aggregation tn tn+1 tn+2 tn+3 tn+4 a b c global network
global resources in actel low-power flash devices v1.3 3-7 using clock aggregation clock aggregation allows for multi-spine cloc k domains to be assigned using hardwired connections, with out adding any extra skew . a mux tree, shown in figure 3-4 , provides the necessary flexibility to allow long lines, local reso urces, or i/os to access domains of one, two, or four global spines. signal acce ss to the clock aggregation system is achieved through long-line resources in the central rib in the center of the die, and also through loca l resources in the north and south ribs, allowing i/os to feed directly into the clock system. as figure 3-5 indicates, this access system is contiguous. there is no break in the middle of the chip fo r the north and south i/o versanet access. this is different from the quadrant clocks located in these ribs, which only reach the middle of the rib. figure 3-4 ? spine selection mu x of global tree figure 3-5 ? clock aggregation tree architecture internal/external signal internal/external signal internal/external signals spine global rib global driver mux tree node mux tree node mux internal/external signals tree node mux global spine global rib global driver and mux i/o access internal signal access i/o tiles global signal access tree node mux
global resources in actel low-power flash devices 3-8 v1.3 clock aggregation architecture this clock aggregation feature allows a balanced clock tree, which improves clock skew. the physical regions for clock aggregation are defined from left to right and shift by one spine. for chip global networks, there are three types of clock aggregation available, as shown in figure 3-6 : ? long lines that can drive up to four adjacent spines ? long lines that can drive up to two adjacent spines ? long lines that can drive one spine there are three types of clock aggregation av ailable for the quadrant spines, as shown in figure 3-6 : ? i/os or local resources that can drive up to four adjacent spines ? i/os or local resources that can drive up to two adjacent spines ? i/os or local resources that can drive one spine ? as an example, a3pe600 and afs600 devices have twelve spine location s: t1, t2, t3, t4, t5, t6, b1, b2, b3, b4, b5, and b6. table 3-5 shows the clock aggreg ation you can have in a3pe600 and afs600. the clock aggregation for the quadrant spines can cross over from the left to right quadrant, but not from top to bottom. the quad rant spine assignment t1:t4 is legal, but the quadrant spine assignment t1:b1 is not legal. no te that this clock aggregation is hardwired. you can always assign signals to spine t1 and b2 by instantiating a buffer, but this may ad d skew in the signal. figure 3-6 ? four spines aggregation tn tn + 1 tn + 2 tn + 4 a b c tn + 3 table 3-5 ? spine aggregation in a3pe600 or afs600 clock aggregation spine 1 spine t1, t2, t3, t4, t5, t6, b1, b2, b3, b4, b5, b6 2 spines t1:t2, t2: t3, t3:t4, t4:t5, t5:t6, b1:b2, b2:b3, b3:b4, b4:b5, b5:b6 4 spines b1:b4, b2:b5, b3:b 6, t1:t4, t2:t5, t3:t6
global resources in actel low-power flash devices v1.3 3-9 i/o banks and global i/os the following sections give an overview of naming conventions and other related i/o information. naming of global i/os in low-power flash devices, the gl obal i/os have access to certain clock conditioning circuitry and have direct access to the global network. additionally, the global i/os can be used as regular i/os, since they have identical capabilities to thos e of regular i/os. due to the comprehensive and flexible nature of the i/os in low-p ower flash devices, a naming sche me is used to show the details of the i/o. the global i/o uses the generic name gmn/iouxwbyvz. refer to the i/o structure section of the handbook for the device that you ar e using for more information on this naming convention. figure 3-7 represents the global input pins connec tion to the northwest ccc or northwest quadrant global networks for a low-power flash device. each global buffer, as well as the pll reference clock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core since each bank can have a differ ent i/o standard, the user should be careful to choose the correct global i/o for the design. there ar e 54 global pins availa ble to access 18 global networks. for the single-ended and voltage-referenc ed i/o standards, you can use any of these three available i/os to access the global network. for di fferential i/o standards such as lvds and lvpecl, the i/o macro needs to be placed on gaa0 and gaa1 or a simi lar location. the unassi gned global i/os can be used as regular i/os. note that pin names starti ng with gf and gc are associated with the chip global networks, and ga, gb, gd, and ge are used for quadrant global networks. figure 3-7 ? global i/o overview + + source for ccc (clka or clkb or clkc) each shaded box represents an inbuf or inbuf_lvds/lvpecl macro, as appropriate. to core routed clock (from fpga core) sample pin names gaa0/io0ndb0v0 1 gaa1/io00pdb0v0 1 gaa2/io13pdb7v1 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source. 2
global resources in actel low-power flash devices 3-10 v1.3 unused global i/o configuration the unused clock inputs behave similarly to the unused pro i/ os. the actel designer software automatically conf igures the unused global pins as inputs with pull-up resistors if they are not used as regular i/o. i/o banks and global i/o standards in low-power flash devices, any i/o or internal logic can be used to drive the global network. however, only the global macro placed at the global pins will use the hardwired connection between the i/o and global network. global signal (signal driving a global macro) assignment to i/o banks is no different from regular i/o assignme nt to i/o banks with the exception that you are limited to the pin placem ent location available. only global signals compatible with both the v cci and v ref standards can be assign ed to the same bank. design recommendations the following sections provide design flow recommendations for using a global network in a design. ? "global macros and i/o standards" ? "using global macros in synplicity" on page 3-12 ? "global promotion and demoti on using pdc" on page 3-13 ? "spine assignment" on page 3-14 ? "designer flow for global assignment" on page 3-15 ? "simple design example" on page 3-17 ? "global management in pll design" on page 3-19 ? "using spines of occupied global networks" on page 3-20 global macros and i/o standards low-power flash devices have six chip global networks and four quadrant clock networks. however, the same clock macros are used for assigning signals to chip globals and quadrant globals. depending on th e clock macro placement or assignment in the physical design constraint (pdc) file or multiview navigator (mvn), the signal will use the chip global network or quadrant network. table 3-6 on page 3-11 lists the clock macros available for low-power flash devices. refer to the igloo, fusion and proasi c3 macro library guide for details.
global resources in actel low-power flash devices v1.3 3-11 use these available macros to assign a signal to the global network. in addition to these global macros, pll and clkdly macros ca n also drive the global networks . use i/o?standard?specific clock macros (clkbuf_x) to instan tiate a specific i/o standar d for the global signals. table 3-7 shows the list of these i/o?standard?specific macros. note that if you use these i/o?standard?specific clock macros, you cannot change the i/ o standard later in the design stage. if you use the regular clkbuf macro, you can use mvn or the pdc file in designer to change the i/o standard. the default i/o standard for clkbuf is lvttl in the current actel libero ? integrated design environment (ide) and designer software. table 3-6 ? clock macros macro name description symbol clkbuf input macro for clock network clkbuf_x input macro for clock network with specific i/o standard clkbuf_lvds/ lvpecl lvds or lvpecl input macro for clock network clkint internal clock interface clkbibuf bidirectional macro with input dedicated to routed clock network y pad clkbuf pad y clkbuf_x padn padp clkbibuf_lvpecl y padn padp clkbibuf_lvds y ay clkint d y e pad clkbibu f table 3-7 ? i/o standards within clkbuf name description clkbuf_lvcmos5 lvcmos clock buffer with 5.0 v cmos voltage level clkbuf_lvcmos33 lvcmos clock buffer with 3.3 v cmos voltage level clkbuf_lvcmos25 lvcmos clock buffer with 2.5 v cmos voltage level 1 clkbuf_lvcmos18 lvcmos clock buffer with 1.8 v cmos voltage level clkbuf_lvcmos15 lvcmos clock buffer with 1.5 v cmos voltage level clkbuf_lvcmos12 lvcmos clock buffer with 1.2 v cmos voltage level clkbuf_pci pci clock buffer clkbuf_pcix pcix clock buffer clkbuf_gtl25 gtl clock buffer wi th 2.5 v cmos voltage level 1 clkbuf_gtl33 gtl clock buffer wi th 3.3 v cmos voltage level 1 notes: 1. supported in only the iglooe, proa sic3e, afs600, an d afs1500 devices 2. by default, the clkbuf macro uses the 3.3 v lvttl i/o technology.
global resources in actel low-power flash devices 3-12 v1.3 the current synthesis tool libraries only infer the clkbuf or clki nt macros in the netlist. all other global macros must be instantiat ed manually into your hdl code . the following is an example of clkbuf_lvcmos25 global macro in stantiations that you can copy and paste into your code: vhdl component clkbuf_lvcmos25 port (pad : in std_logic; y : out std_logic); end component begin -- concurrent statements u2 : clkbuf_lvcmos25 port map (pad => ext_clk, y => int_clk); end verilog module design (______); input _____; output ______; clkbuf_lvcmos25 u2 (.y(int_clk), .pad(ext_clk); endmodule using global macros in synplicity the synplify ? synthesis tool automaticall y inserts global buffers for nets with high fanout during synthesis. by default, synplicity ? puts six global macros (clkbuf or clkint) in the netlist, including any global instantiation or pll ma cro. synplify always honors your global macro instantiation. if you have a pll (only primary output is used) in the design, synplify adds five more global buffers in the netlist. synplify uses the following global counting rule to add global macros in the netlist: 1. clkbuf: 1 global buffer 2. clkint: 1 global buffer 3. clkdly: 1 global buffer 4. pll: 1 to 3 global buffers ? gla, glb, glc, yb, and yc are counted as 1 buffer. ? glb or yb is used or bo th are counted as 1 buffer. ? glc or yc is used or bo th are counted as 1 buffer. clkbuf_gtlp25 gtl+ clock buffer with 2.5 v cmos voltage level 1 clkbuf_gtlp33 gtl+ clock buffer with 3.3 v cmos voltage level 1 clkbuf_ hstl _i hstl class i clock buffer 1 clkbuf_ hstl _ii hstl class ii clock buffer 1 clkbuf_sstl2_i sstl2 class i clock buffer 1 clkbuf_sstl2_ii sstl2 cl ass ii clock buffer 1 clkbuf_sstl3_i sstl3 class i clock buffer 1 clkbuf_sstl3_ii sstl3 cl ass ii clock buffer 1 table 3-7 ? i/o standards within clkbuf (continued) name description notes: 1. supported in only the iglooe, proa sic3e, afs600, an d afs1500 devices 2. by default, the clkbuf macro uses the 3.3 v lvttl i/o technology.
global resources in actel low-power flash devices v1.3 3-13 you can use the syn_global_buffers attribute in synplify to specify a ma ximum number of global macros to be inserted in the netlist. this can also be used to restrict the number of global buffers inserted. in the synplicity 8.1 version, a new attr ibute, syn_global_minfanout, has been added for low-power flash devices. this enables you to promote only the high-fanout signal to global. however, be aware that you can only have six signals assigned to chip global networks, and the rest of the global signals should be assigned to qu adrant global networks. so, if the netlist has 18 global macros, the remaining 12 global macros should have fanout that allows the instances driven by these globals to be placed inside a quadrant. global promotion and demotion using pdc the hdl source file or schematic is the pref erred place for defining which signals should be assigned to a clock network using clock macro instan tiation. this method is preferred because it is guaranteed to be honored by the synthesis tool s and designer software and stop any replication on this net by the synthesis tool. note that a signal with fanout ma y have logic replication if it is not promoted to global during synthesis. in th at case, the user cannot promote that signal to global using pdc. see synplicity help for details on using this attribute. to help you with global management, designer allows you to promote a si gnal to a global network or demote a global macro to a regular macro from th e user netlist using the compile options and/or pdc commands. the following are the pdc constr aints you can use to promote a signal to a global network: 1. pdc syntax to promote a regula r net to a chip global clock: assign_global_clock ?net netname the following will happen during promotion of a regular signal to a global network: ? if the net is external, the net will be dr iven by a clkint in serted automatically by compile. ? the i/o macro will not be changed to clkbuf macros. ? if the net is an internal net, the net will be driven by a clkint inserted automatically by compile. 2. pdc syntax to promote a net to a quadrant clock: assign_local_clock ?net netname ?type quadrant ur|ul|lr|ll this follows the same rule as the chip global clock network. the following pdc comma nd demotes the clock nets to regular nets. unassign_global_clock -net netname note: oavdivrst exis ts only in the fusion pll. figure 3-8 ? plls in low-powe r flash devices c lka g la extfb powerdown oadivr s t lo c k g lb yb g l c y c
global resources in actel low-power flash devices 3-14 v1.3 the following will happen during demotion of a global signal to regular nets: ? clkbuf_x becomes inbuf_x; clkint is removed from the netlist. ? the essential global macro, su ch as the output of the clock conditioning circuit, cannot be demoted. ? no automatic buffering will happen. since no automatic buffering happens when a signal is demoted, this net may have a high delay due to large fanout. this may have a negative effect on the quality of the results. actel recommends that the automatic gl obal demotion only be used on small-fanout nets. use clock networks for high-fanout nets to improve timing and routability. spine assignment the low-power flash device archit ecture allows the global networks to be segmented and used as clock spines. these spines, also ca lled local clocks, enable the use of pdc or mvn to assign a signal to a spine. pdc syntax to promote a net to a spine/local clock: assign_local_clock ?net netname ?type [quadrant|chip] tn|bn|tn:bm if the net is driven by a clock macro, designer automatically demotes the cl ock net to a regular net before it is assigned to a spine. nets driven by a pll or clkdly ma cro cannot be assigned to a local clock. when assigning a signal to a sp ine or quadrant global networ k using pdc (pre-compile), the designer software will legalize the shared in stances. the number of shared instances to be legalized can be controlled by compile options . if these networks are created in mvn (only quadrant globals can be created), no legalization is done (as it is post-compile). designer does not do legalization between non-clock nets. as an example, consider two nets, net_clk and net_reset, driving the same flip-flop. the following pdc constraints are used: assign_local_clock ?net net_clk ?type chip t3 assign_local_clock ?net net_reset ?type chip t1:t2 during compile, designer adds a bu ffer in the reset net and places it in the t1 or t2 region, and places the flip-flop in the t3 spine region ( figure 3-9 ). figure 3-9 ? adding a buffer fo r shared instances d clk clr net_clk net_reset t1 t2 t3 d clk clr net_clk net_reset assign_local_clock -net net_clk -type chip t3 assi g n_local_clock -net net_reset -t yp e chi p t1:t2 before compile after compile added buffer
global resources in actel low-power flash devices v1.3 3-15 you can control the maximum numb er of shared instances allowe d for the legalization to take place using the compile option dialog box shown in figure 3-10 . refer to libero ide / designer online help for details on the co mpile option dialog box. a large number of shared instances most likely indicates a floorplanning problem that you should address. designer flow for global assignment to achieve the desired result, pay special attention to global management during synthesis and place-and-route. the current synplify tool does no t insert more than six global buffers in the netlist by default. thus, the default flow will not assi gn any signal to the qu adrant global network. however, you can use attributes in synplify and in crease the default glob al macro assignment in the netlist. designer v6.2 suppo rts automatic quadrant global a ssignment, which was not available in designer v6.1. layout will ma ke the choice to assign the correct signals to global. however, you can also utilize pdc and perform manual global assignment to overwrite any automatic assignment. the following step-by-step suggestions guide you in the layout of your design and help you improve timing in designer: 1. run compile and check the compile report. th e compile report has global information in the "device utilization" section that describe s the number of chip and quadrant signals in the design. a "net report" section describes chip global nets, quadrant global nets, local clock nets, a list of nets listed by fanout, and net candidates for local clock assignment. review this information. note that yb or yc are counted as global on ly when they are used in isolation; if you use yb only and not glb, this net is not shown in the global/quadrant nets report. instead, it appears in the global utilization report. 2. if some signals have a very high fanout and are candidates for global promotion, promote those signals to global using the compile options or pdc commands. figure 3-11 on page 3-16 shows the globals management section of the compile options. select promote regular nets whose fanout is greater than and enter a reasonable value for fanouts. figure 3-10 ? shared instances in the co mpile option dialog box
global resources in actel low-power flash devices 3-16 v1.3 3. occasionally, the synthesis tool assigns a global macro to cloc k nets, even though the fanout is significantly less than othe r asynchronous signals. select demote global nets whose fanout is less than and enter a reasonable value for fa nouts. this frees up some global networks from the signals that have very lo w fanouts. this can also be done using pdc. 4. use local clocks for the signals that do not need to go to the whole chip but should have low skew. this local clocks assignme nt can only be done using pdc. 5. assign the i/o buffer using mvn if you have fixed i/o assignment. as shown in figure 3-6 on page 3-8 , there are three sets of global pins th at have a hardwired connection to each global network. do not try to put multiple clkbuf macros in these three sets of global pins. for example, do not assign two clkbufs to gaa0x and gaa2x pins. 6. you must click commit at the end of mvn assignment. this runs the pre-layout checker and checks the validity of global assignment. 7. always run co mpile with the keep existing physi cal constraints option on. this uses the quadrant clock network assignment in the mv n assignment and checks if you have the desired signals on the global networks. 8. run layout and check the timing. figure 3-11 ? globals management gui in designer
global resources in actel low-power flash devices v1.3 3-17 simple design example consider a design consisting of six building blocks (shift regi sters) and targeted for an a3pe600- pq208 ( figure 3-9 on page 3-14 ). the example design consists of two plls (pll1 has gla only; pll2 has both gla and glb), a global reset (aclr), an enable (en_all), an d three external clock domains (qclk1, qclk2, and qclk3) driving the di fferent blocks of the design. note that the pq208 package only has two plls (which access the chip global network). because of fanout, the global reset and enable signals need to be assigned to the chip global resources. there is only one free chip global for the remaining global (qclk1, qclk2, qclk3). pl ace two of these signals on the quadrant global resource. the design example de monstrates manually a ssignment of qclk1 and qclk2 to the quadrant glob al using the pdc command. figure 3-12 ? block diagram of the global management example design reg256_behave reg_pllclk2gla_out reg_qclk1_out reg_qclk2_out reg_pllclk2glb_out reg_qclk3_out reg_pllclk1_out reg_pllclk2gla pdown pllz_clka data_qclk1 data_pllcqclk2 en_all qclk1 data_qclk2 qclk2 aclr data_qclk3 data_pllclk1 pll1_clka qclk3 shhl_in shhl_in adr clock shhl_out reg_qclk1 reg_qclk2 reg_pllclk2glb reg_qclk3 reg_pllclk1 pll1 \$115 power-down clka lock gla power-down clka lock gla glb pll2 \$116 reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out
global resources in actel low-power flash devices 3-18 v1.3 step 1 run synthesis with default options. the synplicity log shows the following device utilization: step 2 run compile with the promote regular nets whose fanout is greater than option selected in designer; you will see the following in the compile report: device utilization report: ========================== core used: 1536 total: 13824 (11.11%) io (w/ clocks) used: 19 total: 147 (12.93%) differential io used: 0 total: 65 (0.00%) global used: 8 total: 18 (44.44%) pll used: 2 total: 2 (100.00%) ram/fifo used: 0 total: 24 (0.00%) flashrom used: 0 total: 1 (0.00%) ???????? the following nets have been assigned to a global resource: fanout type name -------------------------- 1536 int_net net : en_all_c driver: en_all_pad_clkint source: auto promoted 1536 set/reset_net net : aclr_c driver: aclr_pad_clkint source: auto promoted 256 clk_net net : qclk1_c driver: qclk1_pad_clkint source: auto promoted 256 clk_net net : qclk2_c driver: qclk2_pad_clkint source: auto promoted 256 clk_net net : qclk3_c driver: qclk3_pad_clkint source: auto promoted 256 clk_net net : $1n14 driver: $1i5/core source: essential 256 clk_net net : $1n12 driver: $1i6/core source: essential 256 clk_net net : $1n10 driver: $1i6/core source: essential designer will promote five more signals to global due to high fanout. there are eight signals assigned to global networks. cell usage: cell count area count*area dfn1e1c1 buff inbuf vcc gnd outbuf clkbuf pll total 1536 278 10 9 9 6 3 2 1853 2.0 1.0 0.0 0.0 0.0 0.0 0.0 0.0 3072.0 278.0 0.0 0.0 0.0 0.0 0.0 0.0 3350.0
global resources in actel low-power flash devices v1.3 3-19 during layout, designer will assign two of the signals to quadrant global locations. step 3 (optional) you can also assign the qclk1_c and qclk2_c ne ts to quadrant regions using the following pdc commands: assign_local_clock ?net qclk1_c ?type quadrant ul assign_local_clock ?net qclk2_c ?type quadrant ll step 4 import this pdc with the netlist and run compile again. you will see the following in the compile report: the following nets have been assigned to a global resource: fanout type name -------------------------- 1536 int_net net : en_all_c driver: en_all_pad_clkint source: auto promoted 1536 set/reset_net net : aclr_c driver: aclr_pad_clkint source: auto promoted 256 clk_net net : qclk3_c driver: qclk3_pad_clkint source: auto promoted 256 clk_net net : $1n14 driver: $1i5/core source: essential 256 clk_net net : $1n12 driver: $1i6/core source: essential 256 clk_net net : $1n10 driver: $1i6/core source: essential the following nets have been assigned to a quadrant clock resource using pdc: fanout type name -------------------------- 256 clk_net net : qclk1_c driver: qclk1_pad_clkint region: quadrant_ul 256 clk_net net : qclk2_c driver: qclk2_pad_clkint region: quadrant_ll step 5 run layout. global management in pll design this section describes the legal global network co nnections to plls in th e low-power flash devices. for detailed information on using plls, refer to clock conditioning circuits in igloo and proasic3 devices . actel recommends that you use the dedicated gl obal pins to directly drive the reference clock input of the associated pll for reduced propagation delays and clock distortion. however, low-power flash devices offer the fl exibility to connect other signal s to reference clock inputs. each pll is associated with three global networks ( figure 3-7 on page 3-9 ). there are some limitations, such as when trying to use the global and pll at the same time: ? if you use a pll with only primary output, you can still use the remaining two free global networks. ? if you use three globals associ ated with a pll location, yo u cannot use the pll on that location. ? if the yb or yc output is used standalone, it will occupy one global, even though this signal does not go to the global network.
global resources in actel low-power flash devices 3-20 v1.3 using spines of occ upied global networks when a signal is assigned to a global network, the flash switches are programmed to set the mux select lines (explained in the "clock aggregation architecture" section on page 3-8 ) to drive the spines of that network wi th the global net. however, if the global net is restricted from reaching into the scope of a spine, the mux drivers of that spine are available for other high-fanout or critical signals ( figure 3-13 ). for example, if you want to limit the clk1_c signal to the left half of th e chip and want use the right side of the same global network for clk2_c, you can add the following pdc commands: define_region -name region1 -type inclusive 0 0 34 29 assign_net_macros region1 clk1_c assign_local_clock ?net clk2_c ?type chip b2 conclusion igloo, fusion, an d proasic3 devices contain 18 global ne tworks: 6 chip glob al networks and 12 quadrant global networks . these global networks can be se gmented into loca l low-skew networks called spines. the sp ines provide low-skew networks for the high-fanout signals of a design. these allow you up to 252 different internal/externa l clocks in an a3pe3000 device. this document describes the architecture for the global network, plus guidelines and methodologies in assigning signals to globals and spines. figure 3-13 ? design example using spines of occupied global networks
global resources in actel low-power flash devices v1.3 3-21 related documents handbook documents clock conditioning circuits in igloo and proasic3 devices http://www.actel.com /lpd_ccc_hbs.pdf i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in iglo oe and proasic3e device s http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf user?s guides igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-005-3 revised october 2008
global resources in actel low-power flash devices 3-22 v1.3 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (june 2008) a third bullet was added to the beginning of the "global architecture" section : in fusion devices, the west ccc al so contains a pll core. in the two larger devices (afs600 and afs1500), the west and east cccs each contain a pll. 3-1 the "global resource support in low-power devices" section was revised to include new families and make the information more concise. 3-2 table 3-2 globals/spines/rows fo r igloo and proasic3 devices was updated to include a3pe600/ l in the device column. 3-5 table note 1 was revised in table 3-7 i/o standards within clkbuf to include afs600 and afs1500. 3-11 v1.1 (march 2008) the following changes were made to the family descriptions in table 3-1 low-power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 3-2 v1.0 (january 2008) the "global architecture" section was updated to include the igloo plus family. the bullet was revised to incl ude that the west ccc does not contain a pll core in 15 k and 30 k devices. instances of "a3p030 and agl030 devices" were replaced with "15 k and 30 k gate devices." 3-1 table 3-1 low-power flash families and the accompanying text was updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 3-2 the "versanet global networ k distribution" section , "spine architecture" section , the note in figure 3-1 overview of ve rsanet global network and device architecture , and the note in figure 3-2 simplified versanet global network were updated to include mention of 15 k gate devices. 3-3 , 3-4 table 3-2 globals/spines/rows fo r igloo and proasic3 devices was updated to add the a3p015 device, and to revise the values for clock trees, globals/spines per tree, and globals/spines per device for the a3p030 and agl030 devices. 3-5 table 3-3 globals/spines/rows for igloo plus devices is new. 3-5 clkbuf_lvcmos12 was added to table 3-7 i/o standards within clkbuf . 3-11 the "handbook documents" section was updated to include the three different i/o structures chapters for proasic3 and igloo device families. 3-21 51900087-1/3.05 figure 3-2 simplified versanet global network was updated. 3-4 the "naming of global i/os" section was updated. 3-9 the "using global macros in synplicity" section was updated. 3-12 the "global promotion and demotion using pdc" section was updated. 3-13 the "designer flow for glob al assignment" section was updated. 3-15 the "simple design example" section was updated. 3-17 51900087-0/1.05 table 3-2 globals/spines/rows fo r igloo and proasic3 devices was updated. 3-5
v1.3 4-1 4 ? clock conditioning circuits in low-power flash devices and mixed-signal fpgas introduction this document outlines the following device information: clock conditioning circuits (ccc) features, pll core specifications, functional de scriptions, software co nfiguration information, detailed usage information, recommended board- level considerations, an d other considerations concerning clock conditioning circuits and global networks in low-power flash devices or mixed- signal fpgas. overview of clock conditioning circuitry in fusion, igloo ? , and proasic ? 3 devices, the cccs are used to implement freq uency division, frequency multiplication, phase shifting, and dela y operations. the cccs ar e available in six chip locations?each of the four chip corners and th e middle of the east and west chip sides. for device- specific variations, refer to the "device-specific layout" section on page 4-16 . the ccc is composed of the following: ? pll core ? 3 phase selectors ? 6 programmable delays and 1 fixe d delay that advances/delays phase ? 5 programmable frequency dividers that provide frequency multiplication/division (not shown in figure 4-5 on page 4-10 because they are automatically configured based on the user's required frequencies) ? 1 dynamic shift register that provides ccc dynamic reconfiguration capability figure 4-1 provides a simplified block diagram of th e physical implementation of the building blocks in each of the cccs. figure 4-1 ? overview of the cccs offered in fusion, igloo, and proasic3 3 global i/os clka clkb clkc to global network a to global network b to global network c from core to core ccc function block (with or without pll) multiplexer tree 3 global i/os 3 global i/os to core to core from core from core multiple signals single signals
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-2 v1.3 each ccc can implement up to three independent global buffers (with or without programmable delay) or a pll function (programmable frequency division/multiplication, phase shift, and delays) with up to three global outputs. unused global outputs of a pll can be used to implement independent global buffers, up to a maximu m of three global ou tputs for a given ccc. ccc programming the ccc block is fully configurab le, either via flash configurat ion bits set in the programming bitstream or through an asynch ronous interface. this asynchro nous dedicated shift register interface is dynamically accessible from inside the low-power flash devices to permit parameter changes, such as pll divide ratios and delays, during device operation. to increase the versatility and flexibility of the clock conditioning system, the ccc configuration is determined either by th e user during the design process, with configuration data being stored in flash memory as part of the devi ce programming procedure, or by writing data into a dedicated shift register during normal device operation. this latter mode allows the user to dynamically reconfigur e the ccc without the need for core programming. the shift register is accessed th rough a simple serial interface. refer to ujtag applications in actel?s low-power flash devices or the application note using global resources in actel fusion devices . global resources low-power flash and mixed signal devices provide three global routing networks (gla, glb, and glc) for each of the ccc locations. there are potentially many i/o locations; each global i/o location can be chosen from only one of three possi bilities. this is controlled by the multiplexer tree circuitry in each global network. once the i/o location is selected, th e user has the option to utilize the cccs before the signals are connected to the global networks. the ccc in each location (up to six) has the same structure, so generating the ccc macros is always done with an identical software gui. the cccs in the corner locations drive the quadra nt global networks, and the cccs in the middle of the east and west chip sides drive the chip global networks. the quadrant global networks span only a quarter of the device, while the ch ip global networks sp an the entire device. for more details on global resources offe red in low-power flash devices, refer to global resources in actel low-powe r flash devices . a global buffer can be placed in any of the three global locations (clka-gla, clkb-glb, or clkc-glc) of a given ccc. a pll macro uses the clka ccc input to drive its reference clock. it uses the gla and, optionally, the glb and glc global outputs to drive the global networks. a pll macro can also drive the yb and yc regular core outputs. the glb (or glc) global output cannot be reused if the yb (or yc) ou tput is used. refer to the "pll macro signal descriptions" section on page 4-8 for more information. each global buffer, as well as the pll reference cl ock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-3 ccc support in actel?s low-power flash devices the low-power flash families listed in table 4-1 support the ccc feature and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 4-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 4-1 . where the informati on applies to only one fa mily or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 4-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-4 v1.3 global buffers with no programmable delays access to the global / quadrant global networks can be configured directly from the global i/o buffer, bypassing the ccc functional block (as indicated by the dotted lines in figure 4-1 on page 4-1 ). internal signals driven by the fpga core can use the global / quadrant global networks by connecting via the routed clock input of the multiplexer tree. there are many specific clkbuf macros supporting the wide variety of single-ended i/o inputs (clkbuf) and differential i/o standards (clkbuf_ lvds/lvpecl) in the lo w-power flash families. they are used when connecti ng global i/os directly to the global/quadrant networks. when an internal signal needs to be connected to the global/quadrant network, the clkint macro is used to connect the sign al to the routed clock inpu t of the network's mux tree. to utilize direct connection from global i/os or from internal signals to the global/quadrant networks, clkbuf, clkbuf_lvpecl/lvds, and clkint macros are used ( figure 4-2 ). ? the clkbuf and clkbuf_lvpecl/lvds/b-lvds/ m-lvds macros are composite macros that include an i/o macro driving a global bu ffer, which uses a hardwired connection. ? the clkbuf, clkbuf_lvpecl/ lvds/b-lvds/m-lvds, and clki nt macros are pass-through clock sources and do not use the pll or pr ovide any programmable delay functionality. ? the clkint macro provides a global buffer function driven internally by the fpga core. the available clkbuf macros are described in the igloo, fusion, and proa sic3 macro library guide . global buffer with programmable delay clocks requiring clock adjustments can utilize th e programmable delay cores before connecting to the global / quadrant global netw orks. a maximum of 18 ccc global buffers can be instantiated in a device?three per ccc and up to six cccs per device. each ccc functional block contains a programmable delay element for each of the global networks (up to three), and users can utilize these features by using the corresponding macro ( figure 4-3 on page 4-5 ). note: the clkdly macro uses programmable delay element type 2 (refer to "clkdly macro usage" section on page 4-5 ). figure 4-2 ? ccc options: global buffers with no programmable delay none clkbuf_lvds/lvpecl macro padn padp yy a pad y clkint macro clkbuf macro gla or glb or glc clock source clock conditioning output
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-5 the clkdly macro is a pass-through clock source th at does not use the pll, but provides the ability to delay the clock input using a programmable delay. the clkdly macro takes the selected clock input and adds a user-defined de lay element. this macro generate s an output clock phase shift from the in put clock. the clkdly macro can be driven by an inbuf* macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the software will automatically place the de dicated global i/o in the appropriate locations. many specific inbuf macros support the wide vari ety of single-ended and differential i/o standards supported by the low-power flash family. the available inbuf macros are described in the igloo, fusion, and proasic3 macro library guide . the clkdly macro can be driven directly from th e fpga core. the clkdly macro can also be driven from an i/o that is routed through the fpga re gular routing fabric. in this case, users must instantiate a special macro, pllint, to differen tiate the clock input driven by the hardwired i/o connection. the visual clkdly configuration in th e smartgen area of the actel libero ? integrated design environment (ide) and designer to ols allows the user to select the desired amount of delay and configures the delay elem ents appropriately. smartgen also a llows the user to select the input clock source. smartgen will automatically instan tiate the special macro, pllint, when needed. clkdly macro signal descriptions the clkdly macro supports one input and on e output. each signal is described in table 4-2 . clkdly macro usage when a clkdly macro is used in a ccc location, the programmable delay element is used to allow the clock delays to go to the gl obal network. in addition, the user can bypass the pll in a ccc location integrated with a pll, but use the prog rammable delay that is as sociated with the global network by instantiating the clkdly macro. the same is true when using programmable delay elements in a ccc location with no plls (the us er needs to instantiate the clkdly macro). there is no difference between the programmable delay el ements used for the pll and the clkdly macro. note: for inbuf* driving a pll macro or clkd ly macro, the i/o will be hard-routed to the ccc; i.e., will be placed by software to a dedicated global i/o. figure 4-3 ? ccc options: global buffers with programmable delay padn padp y pad y input lvds/lvpecl macro inbuf* macro gla or glb or glc clock source clock conditioning output clk dlygl[4:0] gl table 4-2 ? input and output description of the clkdly macro signal name i/o description clk reference clock input reference clock input for pll core input clock for primary output clock, gla gl global output output primary output clock to respective global/quadrant clock networks
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-6 v1.3 the ccc will be configured to use the programma ble delay elements in accordance with the macro instantiated by the user. as an example, if the pll is not used in a partic ular ccc location, the desi gner is free to specify up to three clkdly macros in the ccc, each of wh ich can have its own input frequency and delay adjustment options. if the pll core is used, assuming output to only one global clock network, the other two global clock networks are free to be us ed by either connecting directly from the global inputs or connecting from one or two clkdly macros for programmable delay. the programmable delay elements are shown in the block diagram of the pll block shown in figure 4-5 on page 4-10 . note that any ccc locations with no pll present contain only the programmable delay blocks going to the global networks (labeled "prog rammable delay type 2"). refer to the "clock delay adjustment" section on page 4-24 for a description of the programmable delay types used for the pll. also refer to table 4-13 on page 4-30 for programmable delay type 1 step delay values, and table 4-14 on page 4-31 for programmable delay type 2 step delay values. ccc locations with a pll present can be configured to utilize only the programmable delay blocks (programmable delay type 2) going to the global networks a, b, and c. global network a can be configured to use only th e programmable delay element (bypassing the pll) if the pll is not used in the design. figure 4-5 on page 4-10 shows a block diagram of the pll, where the programmable delay elements are used for the global networks (programmable delay type 2). global buffers with pll function clocks requiring frequency sy nthesis or clock adjustments ca n utilize the pll core before connecting to the global / quadrant global networks. a maximum of 18 ccc global buffers can be instantiated in a device?three per ccc and up to six cccs per device. eac h pll core can generate up to three global/quadrant clocks, while a clock delay element provides one.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-7 the pll functionality of the clock conditio ning block is supported by the pll macro . the pll macro provides five deri ved clocks (three independent) from a single reference clock. the pll macro also provides power-down input and lo ck output signals. the additional inputs shown on the macro are configuration settings, which are configured through the use of smartgen. for manual setting of these bits refer to the igloo, fusion, and proasi c3 macro library guide for details. figure 4-5 on page 4-10 illustrates the various clock ou tput options and delay elements. notes: 1. for fusion only. 2. refer to the igloo, fusion, and proasi c3 macro library guide for more information. 3. for inbuf* driving a pll macro or cl kdly macro, the i/o will be hard-route d to the ccc; i.e., will be placed by software to a dedicated global i/o. figure 4-4 ? ccc options: global buffers with pll padn padp y pad y input lvds/lvpecl macro pll macro inbuf* macro gla or gla and (glb or yb) or gla and (glc or yc) or gla and (glb or yb) and (glc or yc) clock source clock conditioning output oadivhalf oadiv[4:0] oamux[2:0] dlygla[4:0] obdiv[4:0] obmux[2:0] dlyyb[4:0] dlyglb[4:0] ocdiv[4:0] ocmux[2:0] dlyyc[4:0] dlyglc[4:0] findiv[6:0] fbdiv[6:0] fbdly[4:0] fbsel[1:0] xdlysel vcosel[2:0] clka extfb gla lock glb yb glc yc powerdown oadivrst 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-8 v1.3 pll macro signal descriptions the pll macro supports two in puts and up to six outputs. table 4-3 gives a description of each signal. input clock the inputs to the input re ference clock (clka) of the pll can co me from global input pins, regular i/o pins, or internally from the core. for fusion families, the inpu t reference clock can also be from the embedded rc oscillat or or crystal oscillator. global output clocks gla (primary), glb (secondary 1) , and glc (secondary 2) are the outputs of global multiplexer 1, global multiplexer 2, and global multiplexer 3, respectively. these signal s (glx) can be used to drive the high-speed global and quadrant networks of the low-power flash devices. a global multiplexer block consists of the input ro uting for selecting the in put signal for the glx clock and the output mu ltiplexer, as well as delay elements associated with that clock. core output clocks yb and yc are known as core outputs and can be used to drive internal logic without using global network resources. this is especially helpful when global network resources must be conserved and utilized for other timing-critical paths. table 4-3 ? input and output signals of the pll block signal name i/o description clka reference clock input reference clock in put for pll core; input clock for primary output clock, gla oadivrst reset signal for the output divider a input for fusion only. oadivrst can be used when you bypass the pll core (i.e., oamux = 001). the pu rpose of the o adivrst signals is to reset the output of the final clock divider in order to synchronize it with the input to that divider when the pll is bypassed. the signal is active on a low to high transition. the signal must be low for at least on e divider input. if pll core is used, this signal is "don't care " and the internal circuitry will generate the reset signal fo r the synchronization purpose. oadivhalf output a division by half input for fusion only. active high . division by half feature. this feature can only be used when users bypass the pll core (i.e., oamux = 001) and the rc oscillator (rcosc) drives the clka input. this can be used to divide the 100 mhz rc oscillator by a factor of 1.5, 2.5, 3.5, 4.5 ... 14.5). refer to table 4-17 on page 4-32 for more information. extfb external feedback input allows an external signal to be co mpared to a reference clock in the pll core's phase detector. powerdown power down input active low input that selects power-down mode and disables the pll. with the powerdown signal asserted, the pll core sends 0 v signals on all of the outputs. gla primary output output prim ary output clock to respective global/quadrant clock networks glb secondary 1 output output secondary 1 output clock to respective global/quadrant clock networks yb core 1 output output core 1 output clock to local routing network glc secondary 2 output output secondary 2 output clock to respective global/quadrant clock networks yc core 2 output output core 2 output clock to local routing network lock pll lock indicator output active-high signa l indicating that steady-state lock has been achieved between clka and the pll feedback signal
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-9 yb and yc are identical to glb and glc, respectively , with the exception of a higher selectable final output delay. the smartgen pll wizard will configure these outputs according to user specifications and can enable thes e signals with or without the enab ling of global output clocks. the above signals can be enabled in the following output groupings in both internal and external feedback configurati ons of the static pll: ? one output ? gla only ? two outputs ? gla + (glb and/or yb) ? three outputs ? gla + (glb an d/or yb) + (glc and/or yc) pll macro block diagram as illustrated, the pll supports three distinct output frequencies from a given input clock. two of these (glb and glc) can be routed to the b an d c global network acce ss, respectively, and/or routed to the device core (yb and yc). there are five delay elements to support phase con trol on all five outputs (gla, glb, glc, yb, and yc). there are delay elements in the feed back loop that can be used to advance the clock relative to the reference clock. the pll macro reference clock can be driven in the following ways: 1. by an inbuf* macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hard wired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. 2. driven directly from the fpga core. 3. from an i/o that is routed through the fpga regula r routing fabric. in this case, users must instantiate a special macro, pllint, to diff erentiate from the hardwired i/o connection described earlier. during power-up, the pll output s will toggle around the maxi mum frequency of the voltage- controlled oscillator (vco) gear selected. toggl e frequencies can range from 40 mhz to 250 mhz. this will continue as long as the clock input (clka) is constant (high or low). this can be prevented by low assertion of the powerdown signal. the visual pll configuration in smartgen, a component of the libe ro ide and design er tools, will derive the necessary internal divider ratios based on the input frequ ency and desired output frequencies selected by the user. smartgen also allows the user to select the variou s delays and phase shift values necessary to adjust the phases between the reference cl ock (clka) and the derived clocks (gla, glb, glc, yb, and yc).
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-10 v1.3 smartgen allows the user to sele ct the input clock source. smartgen automatically instantiates the special macro, pllint, when needed. global input selections low-power flash devices provide the flexibility of choosing one of the three global input pad locations available to conn ect to a ccc functional block or to a global / quadrant global network. figure 4-6 on page 4-11 shows the detailed architecture of each global input structure. if the single-ended i/o standard is chosen, there is flexibility to choose one of the global input pads (the first, second, and fourth in put). once chosen, the other i/o locati ons are used as regular i/os. if the differential i/o standard is chosen, the first and second inputs are consider ed as paired, and the third input is paired with a regular i/o. the user then has the choice of selecting one of th e two sets to be used as the clock input source to the ccc functional block. there is also the option to allow an internal clock signal to feed the global network or the ccc functional block. a multiplexer tree selects the appropriate global input for routing to the desired location . note that the global i/o pads do not need to feed the global network; they can also be used as regular i/o pads. note: clock divider and clock multiplier blocks are not shown in this figure or in smartgen. they are automatically configured based on the user's required frequencies. figure 4-5 ? ccc with pll block pll core phase select phase select phase select gla clka glb yb glc yc programmable delay programmable delay type 1 programmable delay type 2 programmable delay type 2 programmable delay type 1 programmable delay type 2 programmable delay type 1 four-phase output extfb
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-11 each global buffer, as well as the pll reference cl ock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core since the architecture of the devi ces varies as size increases, th e following list details i/o types supported for globals: igloo and proasic3 ? lvds-, b-lvds-, and m-lvds?based clock source s are only available on 250 k gate devices and above. ? 65 k and 125 k gate devices suppo rt single-ended clock sources only. ? 15 k and 30 k gate devices support these in puts for ccc only and do not contain a pll. fusion ? afs600 and afs1500: all sing le-ended, differenti al, and voltage-referenced i/o standards (pro i/o). ? afs090 and afs250: all single-ended and differential i/o standards. notes: 1. represents the global input pins. globals have direct access to the clock conditioning block and are not routed via the fpga fabric. refer to user i/o naming conventions in i/o structures in igloo and proasic3 devices . 2. instantiate the routed cloc k source input as follows: a) connect the output of a logic element to the clock input of a pll, clkdly, or clkint macro. b) do not place a clock source i/ o (inbuf or inbuf_lvpecl/lvds/b-lvds /m-lvds/ddr) in a relevant global pin location. figure 4-6 ? clock input sources including clkbuf, clkbuf_lvds/lvpecl, and clkint + + source for ccc (clka or clkb or clkc) each shaded box represents an inbuf or inbuf_lvds/lvpecl macro, as appropriate. to core routed clock (from fpga core) sample pin names gaa0/io0ndb0v0 1 gaa1/io00pdb0v0 1 gaa2/io13pdb7v1 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source. 2
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-12 v1.3 clock sources for p ll and clkdly macros the input reference clock (clka for a pll macro, clk for a clkdly macro) can be accessed from different sources via the associated clock multiple xer tree. each ccc has the option of choosing the source of the input clock from one of the following: ? hardwired i/o ? external i/o ? core logic ? rc oscillator (fusion only) ? crystal oscillator (fusion only) the smartgen macro builder tool al lows users to easily create the pll and clkdly macros with the desired settings. actel strongly re commends using smartgen be used to generate the ccc macros. hardwired i/o clock source hardwired i/o refers to global inpu t pins that are hardwired to th e multiplexer tree, which directly accesses the ccc global buffers. these global input pins have designated pin locations and are indicated with the i/o naming convention gmn ( m refers to any one of the positions where the pll core is available, and n refers to any one of the three glob al input muxes and the pin number of the associated global location, m ). choosing this option provides the benefit of directly connecting to the ccc reference clock input, which provides less delay. see figure 4-7 for an example illustration of the connections, shown in red. if a clkdly macro is initiated to utilize the programmable delay element of the ccc, the clock input can be placed at one of nine dedicated global input pin locations. in other words, if ha rdwired i/o is chosen as the input source, the user can decide to place the input pin in one of the gma0, gma1, gma2, gmb0, gmb1, gmb2, gmc0, gmc1, or gmc2 locations of the low-power flash de vices. when a pll macro is used to utilize the pll core in a ccc location, the clock input of th e pll can only be connected to one of three gma* global pin locations: gma0, gma1, or gma2. figure 4-7 ? illustration of hardwired i/o (global input pins) usage + _ pll or clkdly macro routed clock (from fpga core) gmn0 gmn1 gmn2 to core to global (or local) routing network clka pllint multiplexer tree + _ iouxwbyvz gmn* = global input pin iouxwbyvz = regular i/o pin
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-13 external i/o clock source external i/o refers to regular i/o pins. the clock source is instantiated with one of the various inbuf options and accesses th e cccs via internal routing. the user has the option of assigning this input to any of the i/os labeled with the i/o convention iouxwbyvz . refer to user i/o naming conventions in i/o structures in igloo and proasic3 devices and for fusion, refer to the fusion mixed-signal programmable system chip datasheet for more information. figure 4-8 gives a brief explanation of external i/o usage. choosing this option provides the freedom of selecting any user i/o location but introduces additi onal delay because the signal conn ects to the rout ed clock input through internal routing before connecting to the ccc reference clock input. for the external i/o opti on, the routed signal would be instan tiated with a pllint macro before connecting to the ccc reference cl ock input. this instantiation is conveniently done automatically by smartgen when this option is selected. acte l recommends using the smar tgen tool to generate the ccc macro. the instantiation of the pllint macr o results in the use of the routed clock input of the i/o to connect to the pll cl ock input. if not using smartgen , manually instantiate a pllint macro before the pll reference clock to indicate th at the regular i/o driving the pll reference clock should be used (see figure 4-8 for an example illustration of the connections, shown in red). in the above two op tions, the clock s ource must be instantiated with one of the various inbuf macros. the reference clock pins of the ccc functional block core macros must be driven by regular input macros (inbufs), not clock input macros. for fusion devices, the input re ference clock can also be from th e embedded rc oscillator and crystal oscillator. in this case, the ccc configurat ion is the same as the ha rdwired i/o clock source, and users are required to instanti ate the rc oscillator or crystal oscillator macro and connect its output to the input reference clock of the ccc block. figure 4-8 ? illustration of external i/o usage pll or clkdly macro routed clock (from fpga core) gmn* gmn* gmn* to core iouxwbyvz* to global (or local) routing network iouxwbyvz* clka pllint multiplexer tree + _ + _ gmn* = global input pin iouxwbyvz = regular i/o pin
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-14 v1.3 core logic clock source core logic refers to internal routed ne ts. internal routed signals ac cess the ccc via the fpga core fabric. similar to the external i/o option, whenever the clock source comes internally from the core itself, the routed signal is instantiated with a pllint macro before conn ecting to the ccc clock input (see figure 4-9 for an example illustration of the connections, shown in red). for fusion devices, the input re ference clock can also be from th e embedded rc oscillator and crystal oscillator. in this case, the ccc configurat ion is the same as the ha rdwired i/o clock source, and users are required to instanti ate the rc oscillator or crystal oscillator macro and connect its output to the input reference clock of the ccc block. figure 4-9 ? illustration of core logic usage pll or clkdly macro routed clock (from fpga core) gmn* gmn* gmn* to core iouxwbyvz* to global (or local) routing network from internal signals clka pllint multiplexer tree _ + _ + gmn* = global input pin iouxwbyvz = regular i/o pin
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-15 available i/o standards global synthesis constraints the synplify ? synthesis tool, by default, allows six clocks in a de sign for fusion, igloo, and proasic3. when more than six clocks are needed in the design, a user synthe sis constraint attribute, syn_global_buffers, can be used to control the maximum number of clocks (up to 18) that can be inferred by the synthesis engine. high-fanout nets will be inferred with clock buff ers and/or internal cloc k buffers. if the design consists of ccc global buffers, they are incl uded in the count of clocks in the design. the subsections below discuss the clock input source (global buffer s with no programmable delays) and the clock conditioning functional block (global buffers with programmable delays and/or pll function) in detail. table 4-4 ? available i/o stan dards within clkbuf and clkbuf_lvds/lvpecl macros clkbuf_lvcmos5 clkbuf_lvcmos33 1 clkbuf_lvcmos25 2 clkbuf_lvcmos18 clkbuf_lvcmos15 clkbuf_pci clkbuf_pcix 3 clkbuf_gtl25 2,3 clkbuf_gtl33 2,3 clkbuf_gtlp25 2,3 clkbuf_gtlp33 2,3 clkbuf_hstl_i 2,3 clkbuf_hstl_ii 2,3 clkbuf_sstl3_i 2,3 clkbuf_sstl3_ii 2,3 clkbuf_sstl2_i 2,3 clkbuf_sstl2_ii 2,3 clkbuf_lvds 4 clkbuf_lvpecl notes: 1. by default, the clkbuf macro uses 3.3 v lvttl i/o technology. for more details, refer to the igloo, fusion, and proasic3 macro library guide . 2. i/o standards only supported in proasic3e and iglooe families. 3. i/o standards only supported in the following fusion devices: afs600 and afs1500. 4. b-lvds and m-lvds standards are supported by clkbuf_lvds.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-16 v1.3 device-specific layout two kinds of cccs are offered in low-power flas h devices: cccs with in tegrated plls, and cccs without integrated plls (simplified cccs). table 4-5 lists the number of cc cs in various devices. this document outlines the following device in formation: ccc features, pll core specifications, functional descri ptions, software configuration info rmation, detailed usage information, recommended board-level considerations, and other considerations concerning global networks in low-power flash devices. clock conditioning circuits with integrated plls each of the cccs with integrated plls includes the following: ? 1 pll core, which consists of a phase detector , a low-pass filter, and a four-phase voltage- controlled oscillator ? 3 global multiplexer blocks that steer signals fr om the global pads and the pll core onto the global networks ? 6 programmable delays and 1 fixed de lay for time advanc e/delay adjustments ? 5 programmable frequency divider blocks to provide frequency synthesis (automatically configured by the smartgen macro builder tool) table 4-5 ? number of cccs by device size and package device package cccs with integrated plls cccs without integrated plls (simplified ccc) proasic3/proasic3l igloo/igloo plus a3p015 agl015 all 0 2 a3p030 agl030/aglp030 all 0 2 a3p060 agl060/aglp060 all 1 5 a3p125 agl125/aglp125 all 1 5 a3p250/l agl250 all 1 5 a3p400 all 1 5 a3p600/l agl600 all 1 5 a3p1000/l agl1000 all 1 5 a3pe600 agle600 pq208 2 4 a3pe600/l all other packages 60 a3pe1500 pq208 2 4 a3pe1500 all other packages 60 a3pe3000/l pq208 2 4 a3pe3000/l agle3000 all other packages 60 fusion devices afs090 all 1 5 afs250, m1afs250 all 1 5 afs600, m7afs600, m1afs600 all 2 4 afs1500, m1afs1500 all 2 4
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-17 clock conditioning circuits without integrated plls each of the simplified cccs without integrated plls in the low-power flash families is composed of the following: ? 3 global multiplexer blocks that steer sign als from the global pads and the programmable delay elements onto the global networks ? 3 programmable delay elements to provide time delay adjustments ccc locations cccs located in the middle of the east and west sides of the device access the three versanet global networks on each side (six total networks), while the four cccs located in the four corners access three quadrant global networks (twelve total networks). see figure 4-10 . the following explains the locations of the cccs in igloo and proasic3 devices: in figure 4-13 on page 4-20 through figure 4-14 on page 4-20 , cccs with integrated plls are indicated in red, and simplified cccs are indicated in yellow. there is a letter associated with each location of the ccc, in clockwise order. the uppe r left corner ccc is name d "a," the upper right is named "b," and so on. these names finish up at the middle left with letter "f." figure 4-10 ? global network architecture northwest quadrant global networks southeast quadrant global networks chip-wide (main) global networks 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc location a ccc location f ccc location e ccc location d ccc location c ccc location b
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-18 v1.3 igloo and proasi c3 ccc locations in all igloo and proasic3 devices (except 15 k an d 30 k gate devices, which do not contain plls), six cccs are located in the same positions as the iglooe and proasic3e cccs. only one of the cccs has an integrated pll and is locate d in the middle of the west (mid dle left) side of the device. the other five cccs are simplified cc cs and are located in the four co rners and the middle of the east side of the device ( figure 4-11 ). figure 4-11 ? ccc locations in igloo and proasic3 family devices (except 15 k and 30 k gate devices) ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 a b c d e f = ccc with integrated pll = simplified ccc with programmable delay elements (no pll)
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-19 note that the 15 k and 30 k gate de vices do not support pll features. this device has only six global i/o buffers: three on the east and three on the west, lo cated in the middle of the side of the device. a ccc functional block is available in each of the two locations, for a total of two cccs. no quadrant global networks are present in the four corners of this device ( figure 4-12 ). figure 4-12 ? ccc locations in the 15 k and 30 k gate devices ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 = simplified ccc with programmable delay elements (no pll) a b c d e f
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-20 v1.3 iglooe and proasic3e ccc locations iglooe and proasic3e devices have six cccs ? one in each of the four corners and one each in the middle of the east and we st sides of the device ( figure 4-13 ). all six cccs are integrated with plls, except in pqfp-208 package devi ces. pqfp-208 package devices also have six cccs, of which two include plls and four are simpli fied cccs. the cccs with plls are implemented in the middle of the east and west sides of the de vice (middle right and middle left). the simplified cccs without plls are located in the four corners of the device ( figure 4-14 ). figure 4-13 ? ccc locations in iglooe an d proasic3e family device s (except pqfp-208 package) figure 4-14 ? ccc locations in proasic3e fami ly devices (pqfp-208 package) versatile ram block 4,608-bit dual-port sram or fifo block pro i/os ram block 4,608-bit dual-port sram or fifo block isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps = ccc with integrated pll ccc a b c d e f ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 = ccc with integrated pll = simplified ccc with programmable delay elements (no pll) b c d ccc a e f isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-21 fusion ccc locations fusion devices have six cccs: one in each of the four corners and one each in the middle of the east and west sides of the device ( figure 4-15 and figure 4-16 ). the device can have one integrated pll in the middle of the west side of the device or two integrated plls in th e middle of the east and west sides of the device (mid dle right and middle left). figure 4-15 ? ccc locations in fusi on family devices (afs090, afs250, m1afs250) figure 4-16 ? ccc locations in fusion family devi ces (except afs090, afs250, m1afs250) ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 a b c d e f = ccc with integrated pll = simplified ccc with programmable delay elements (no pll) ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 = ccc with integrated pll = simplified ccc with programmable delay elements (no pll) b c d ccc a e f isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-22 v1.3 pll core specifications pll core specifications can be found in the dc and switching characte ristics chapter of the appropriate family datasheet. loop bandwidth common design practice fo r systems with a low-noise input clock is to have plls with small loop bandwidths to reduce the effects of noise sources at the output. table 4-6 shows the pll loop bandwidth, providing a measure of the pll's ab ility to track the input clock and jitter. pll core operating principles this section briefly describes the basic principles of pll operation. the pll core is composed of a phase detector (pd), a low-pass filter (lpf), an d a four-phase voltage-co ntrolled oscillator (vco). figure 4-17 illustrates a basic single-phase pll core wi th a divider and delay in the feedback path. the pll is an electronic servo loop that phase-aligns the pd fee dback signal with the reference input. to achieve this, the pll dynamically adjusts the vco output signal according to the average phase difference between the input and feedback signals. the first element is the pd, wh ich produces a voltage proporti onal to the phase difference between its inputs. a simple exam ple of a digital phase detector is an exclusive-or gate. the second element, the lpf, extracts the average voltage from the phas e detector and applies it to the vco. this applied voltage alters the resonant fr equency of the vco, th us adjusting its output frequency. consider figure 4-17 with the feedback path bypassing the divider and delay elements. if the lpf steadily applies a voltage to the vco such that the output freque ncy is identical to the input frequency, this steady-state condition is known as lock. note that the inpu t and output phases are also identical. the pll core sets a lock outp ut signal high to in dicate this condition. should the input frequency increase slightly, the pd detects the frequency/phase difference between its reference and feedback input signals. since the pd output is proportional to the phase difference, the change causes the output from th e lpf to increase. this voltage change increases the resonant frequency of the vco and increase s the feedback frequency as a result. the pll dynamically adjusts in this manner until the pd senses two phase- identical signals and steady-state lock is achieved. the opposite (decreasing pd output signal) occurs wh en the input frequency decreases. table 4-6 ? ?3db frequency of the pll minimum (t a = +125c, v cca = 1.4 v) ty p i c a l (t a = +25c, v cca = 1.5 v) maximum (t a = ? 55c, v cca = 1.6 v) ? 3 db frequency 15 khz 25 khz 45 khz figure 4-17 ? simplified pll core with fe edback divider and delay frequency reference input f in phase detector low-pass filter voltage controlled oscillator divide by m counter delay frequency output m f in
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-23 now suppose the feedback divider is inserted in the feedback path. as the division factor m (shown in figure 4-18 ) is increased, the average phase differen ce increases. the average phase difference will cause the vco to increase its frequency until th e output signal is phas e-identical to the input after undergoing division. in other words, lock in both frequency and phase is achieved when the output frequency is m times the input. thus, clock division in the feedback path results in multiplication at the output. a similar argument can be made when the delay element is inserted into the feedback path. to achieve steady-state lock, the vco output signal will be delayed by the input period less the feedback delay. for periodic signals, this is equi valent to time-advancing the output clock by the feedback delay. another key parameter of a pll system is the acqu isition time. acquisition time is the amount of time it takes for the pll to ac hieve lock (i.e., phase- align the feedback si gnal with the input reference clock). for example, su ppose there is no voltage applie d to the vco, allowing it to operate at its free-running frequency. should an input reference clock suddenly appear, a lock would be established within the maximum acquisition time. functional description this section provides detailed descriptions of p ll block functionality: clock dividers and multipliers, clock delay adjustment, phase adjustm ent, and dynamic pll configuration. clock dividers and multipliers the pll block contains five programmable dividers. figure 4-18 shows a simplifi ed pll block. figure 4-18 ? pll block diagram pll core clka fixed delay d1 d2 d2 d1 d2 d1 n m u v w gla glb glc primary secondary 1 secondary 2 yb yc system delay output delay feedback delay output delay output delay output delay output delay 270 180 90 0 d1 = programmable delay type 1 d2 = programmable delay type 2
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-24 v1.3 dividers n and m (the input divider and feedback divider, respectively) provide integer frequency division factors from 1 to 128. the output dividers u , v , and w provide integer di vision factors from 1 to 32. frequency scaling of the reference cloc k clka is performed acco rding to the following formulas: f gla = f clka m / (n u) ? gla primary pll output clock eq 4-1 f glb = f yb = f clka m / (n v) ? glb secondary 1 pll output clock(s) eq 4-2 f glc = f yc = f clka m / (n w) ? glc secondary 2 pll output clock(s) eq 4-3 smartgen provides a user-friendl y method of generating the configured pll netlist, which includes automatically setting the division factors to achi eve the closest possible match to the requested frequencies. since the five output clocks share the n and m dividers, the achievable output frequencies are inte rdependent and related accord ing to the foll owing formula: f gla = f glb (v / u) = f glc (w / u) eq 4-4 clock delay adjustment there are a total of seven configurable delay elements implemented in the pll architecture. two of the delays are located in the feedback path, entitled system delay and feedback delay. system delay provides a fixed delay of 2 ns (typical), and feedback delay provides se lectable delay values from 0.6 ns to 5.56 ns in 160 ps increments (typical). for plls, dela ys in the feedback path will effectively advance the output signal from the pll core with respect to the reference clock. thus, the system and feedback delays generate nega tive delay on the output clock. additionally, each of these delays can be independently bypassed if necessary. the remaining five delays perform traditional time delay and are located at each of the outputs of the pll. besides the fixed global driver delay of 0.755 ns for each of the global networks, the global multiplexer outputs (gla, glb, an d glc) each feature an addition al selectable delay value from 0.025 ns to 0.76 ns in the first st ep, and then to 5.56 ns in 160 ps increments. the additional yb and yc signals have access to a selectable delay from 0. 6 ns to 5.56 ns in 160 ps increments (typical). this is the same delay value as the clkdly macro. it is similar to clkdly, which bypasses the pll core just to take advantage of the phase adjustment option wi th the delay value. the following parameters must be taken into consideration to achieve minimum delay at the outputs (gla, glb, glc, yb, and yc) relative to the reference clock: routing delays from the pll core to ccc outputs, core output s and global network output delays, and the feedback path delay. the feedback path delay acts as a time advance of the input clock and will offset any delays introduced beyond the pll core output. the routing delays are determined from back-annotated simulation and are configuration-dependent. phase adjustment the output from the pll core can be phase-adju sted with respect to the reference input clock, clka. the user can select a 0, 90, 180, or 270 phase shift independently for each of the outputs ya, glb/yb, and glc/yc. note that each of thes e phase-adjusted signals might also undergo further frequency division and/or time adjustment via the remaining dividers and delays located at the outputs of the pll. dynamic pll configuration the cccs can be configured both statically and dynamically. in addition to the ports available in the static ccc, th e dynamic ccc has the dynamic shift register signals that enab le dynamic reconfiguration of the ccc. with the dynamic ccc, the ports clkb and clkc are also exposed. all three clocks (clka, clkb, and cl kc) can be configured independently.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-25 the ccc block is fully configurable. the followin g two sources can act as the ccc configuration bits. flash configuration bits the flash configuration bits are the configuratio n bits associated with pr ogrammed flash switches. these bits are used when the ccc is in static co nfiguration mode. once the device is programmed, these bits cannot be modifi ed. they provide the default operating state of the ccc. dynamic shift register outputs this source does not require core reprog ramming and allows core-driven dynamic ccc reconfiguration. when the dynamic register drives the configuration bits, the user-defined core circuit takes full control over sdin, sdout, sclk , sshift, and supdate. the configuration bits can consequently be dynamically changed through shift and update operations in the serial register interface. access to the logic core is accomplished via the dynamic bi ts in the specific tiles assigned to the plls. figure 4-19 illustrates a simplified block diagram of the mux ar chitecture in the cccs. the selection between the flash configuration bits and the bits from the co nfiguration register is made using the mode signal shown in figure 4-19 . if the mode signal is logic high, the dynamic shift register configuration bits are selected. there are 81 control bits to configure the different functions of the ccc. each group of control bits is assigned a specific lo cation in the configuration shift register. for a list of the 81 configuration bits (c[80:0]) in the ccc and a description of each, refer to "pll configuration bits description" on page 4-27 . the configuration registe r can be serially loaded with the new configuration data and progra mmed into the ccc usin g the following ports: ? sdin: the configuration bits are serially loaded into a shift register thro ugh this port. the lsb of the configuration data bits should be loaded first. ? sdout: the shift register contents can be shi fted out (lsb first) thro ugh this po rt using the shift operation. ? sclk: this port should be driven by the shift clock. ? sshift: the active-high shift enable signal shou ld drive this port. the configuration data will be shifted into the shift register if this si gnal is high. once sshift goes low, the data shifting will be halted. ? supdate: the supdate signal is used to conf igure the ccc with the new configuration bits when shifting is complete. to access the configuration ports of the shift regi ster (sdin, sdout, sshift, etc.), the user should instantiate the ccc macro in his design with appropriate ports. actel recommends that users choose smartgen to generate the ccc macros with the required po rts for dynamic reconfiguration. * for fusion, bit <88:81> is also needed. figure 4-19 ? the ccc configuration mux architecture sdin sclk reset_enable sdout sshift mode supdate configuration bits dynamic shift register flash programming configuration bits <80:0>* <80> <79:0> <79:0>*
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-26 v1.3 users must familiarize themselves with the architec ture of the ccc core and its input, output, and configuration ports to implement the desired de lay and output frequency in the ccc structure. figure 4-20 shows a model of the ccc with configurable blocks and switches. loading the confi guration register the most important part of ccc dynamic configuratio n is to load the shift register properly with the configuration bits. there are different ways to access and load the co nfiguration shift register: ? jtag interface ?logic core ? specific i/o tiles figure 4-20 ? ccc block control bits ? graphical representation of assignments /w d c<37:35> c<28:24> internal c<60:56> glc d c<70:66> yc clkc clkb internal c<55:51> c<23:19> c<34:32> glb d dyb /v c<44:40> c<45> c<39:38> d d (0) (1) (1) (2) c<13:7> c<6:0> /m /n clka pll core (4) (2) (7) (6) (5) c<18:14> c<31:29> c<50:46> internal gla d /u m u x a 0 270 90 180 m u x b m u x c
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-27 jtag interface the jtag interface requires no ad ditional i/o pins. the jtag tap co ntroller is used to control the loading of the ccc configuration shift register. low-power flash devices provide a user interface macro between the jtag pins and the device core logic. this macro is called ujtag. a user should instantiate the uj tag macro in his design to access the configuration register ports via the jtag pins. for more information on ccc dynamic reconfiguration using ujtag, refer to ujtag applications in actel?s low-power flash devices. logic core if the logic core is employed, the user must design a module to provide th e configuration data and control the shifting and updating of the ccc configur ation shift register. in effect, this is a user- designed tap controller, which requ ires additional chip resources. specific i/o tiles if specific i/o tiles are used fo r configuration, the user must prov ide the external equivalent of a tap controller. this does no t require additional core re sources but does use pins. shifting the conf iguration data to enter a new configuration, all 81 bits must shift in via sdin. after all bits are shi fted, sshift must go low and supdate high to enable the new configuration. for simulation purposes, bits <71:73> and <77:80> are "don?t cares." the supdate signal must be low during any clock cycle where sshift is active. after supdate is asserted, it must go back to the low state until a new update is required. pll configuration bits description table 4-7 ? configuration bit descriptions for the ccc blocks config. bits signal name description <88:87> glmuxcfg [1:0] 1 ngmux configuration the configuratio n bits specify the input clocks to the ngmux (refer to table 4-16 on page 4-31 ). 2 86 ocdivhalf 1 division by half when the p ll is bypassed, the 100 mhz rc oscillator can be divided by the divider factor in table 4-17 on page 4-32 ). 85 obdivhalf 1 division by half when the p ll is bypassed, the 100 mhz rc oscillator can be divide d by certain 0.5 factor (refer to table 4-17 on page 4-32 ). 84 oadivhalf 1 division by half when the p ll is bypassed, the 100 mhz rc oscillator can be divide d by certain 0.5 factor (refer to table 4-15 on page 4-31 ). 83 rxcsel 1 clkc input selection select the clkc input clock source between rc oscillator and crystal oscillator (refer to table 4-15 on page 4-31 ). 2 82 rxbsel 1 clkb input selection select the clkb input clock source between rc oscillator and crystal oscillator (refer to table 4-15 on page 4-31 ). 2 notes: 1. the <88:81> conf iguration bits are only for the fusion dynamic ccc. 2. this value depends on the input clock source, so layo ut must complete before these bits can be set. after completing layout in designer, generate the "ccc_configuration " report by choosing tools > report > ccc_configuration . the report contains the appr opriate settings for these bits.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-28 v1.3 81 rxasel 1 clka input selection select the cl ka input clock source between rc oscillator and crystal oscillator (refer to table 4-15 on page 4-31 ). 2 80 reseten reset enable enables (activ e high) the synchronization of pll output dividers after dynamic reconfiguration (supdate). the reset enable signal is read- only and should not be modified via dynamic reconfiguration. 79 dyncsel clock input c dynamic select configures clock input c to be sent to glc for dynamic control. 2 78 dynbsel clock input b dynamic select configures clock input b to be sent to glb for dynamic control. 2 77 dynasel clock input a dynamic select co nfigures clock input a for dynamic pll configuration. 2 <76:74> vcosel[2:0] vco gear control three- bit vco gear control for four frequency ranges (refer to table 4-18 on page 4-32 and table 4-19 on page 4-32 ). 73 statcsel mux select on input c mux selection for clock input c 2 72 statbsel mux select on input b mux selection for clock input b 2 71 statasel mux select on input a mux selection for clock input a 2 <70:66> dlyc[4:0] yc output delay sets the output delay value for yc. <65:61> dlyb[4:0] yb output delay sets the output delay value for yb. <60:56> dlyglc[4:0] glc output delay sets the output delay value for glc. <55:51> dlyglb[4:0] glb output delay sets the output delay value for glb. <50:46> dlygla[4:0] primary output delay primary, gla output delay 45 xdlysel system delay select when se lected, inserts system delay in the feedback path in figure 4-18 on page 4-23 . <44:40> fbdly[4:0] feedback delay sets the feedback delay value for the feedback element in figure 4-18 on page 4-23 . <39:38> fbsel[1:0] primary feedback delay select co ntrols the feedback mux: no delay, include programmable delay element, or use external feedback. <37:35> ocmux[2:0] secondary 2 ou tput select selects from the vc o?s four phase outputs for glc/yc. <34:32> obmux[2:0] secondary 1 ou tput select selects from the vc o?s four phase outputs for glb/yb. <31:29> oamux[2:0] gla output select selec ts from the vco?s four phase outputs for gla. table 4-7 ? configuration bit descriptions for the ccc blocks (continued) config. bits signal name description notes: 1. the <88:81> conf iguration bits are only for the fusion dynamic ccc. 2. this value depends on the input clock source, so layo ut must complete before these bits can be set. after completing layout in designer, generate the "ccc_configuration " report by choosing tools > report > ccc_configuration . the report contains the appr opriate settings for these bits.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-29 table 4-8 to table 4-14 on page 4-31 provide descriptions of th e configuration data for the configuration bits. <28:24> ocdiv[4:0] secondar y 2 output divider sets the divide r value for the glc/yc outputs. also known as divider w in figure 4-18 on page 4-23 . the divider value will be ocdiv[4:0] + 1. <23:19> obdiv[4:0] secondar y 1 output divider sets the divide r value for the glb/yb outputs. also known as divider v in figure 4-18 on page 4-23 . the divider value will be obdiv[4:0] + 1. <18:14> oadiv[4:0] primary output divider sets the divider va lue for the gla output. also known as divider u in figure 4-18 on page 4-23 . the divider value will be oadiv[4:0] + 1. <13:7> fbdiv[6:0] feedback divider sets the divider value for the pll core feedback. also known as divider m in figure 4-18 on page 4-23 . the divider value will be fbdiv[6:0] + 1. <6:0> findiv[6:0] input divider input clock divider (/n). sets the divider value for the input delay on clka. the divider value will be findiv[6:0] + 1. table 4-7 ? configuration bit descriptions for the ccc blocks (continued) config. bits signal name description notes: 1. the <88:81> conf iguration bits are only for the fusion dynamic ccc. 2. this value depends on the input clock source, so layo ut must complete before these bits can be set. after completing layout in designer, generate the "ccc_configuration " report by choosing tools > report > ccc_configuration . the report contains the appr opriate settings for these bits. table 4-8 ? input clock divider, findiv[6:0] (/n) findiv<6:0> state divis or new frequency factor 0 1 1.00000 1 2 0.50000 ? ? ? 127 128 0.0078125 table 4-9 ? feedback clock divider, fbdiv[6:0] (/m) fbdiv<6:0> state divisor new frequency factor 011 122 ? ? ? 127 128 128
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-30 v1.3 table 4-10 ? output frequency dividers a output divider, oadiv <4:0> (/u); b output divider, obdiv <4:0> (/v); c output divider, ocdiv <4:0> (/w) oadiv<4:0>; obdiv<4:0>; cdiv<4:0> state divisor new frequency factor 0 1 1.00000 1 2 0.50000 ? ? ? 31 32 0.03125 table 4-11 ? muxa, muxb, muxc oamux<2:0>; obmux<2:0>; ocmux<2:0> state mux input selected 0 none. six-input mux and pll are bypassed. clock passes only through global mux and goes directly into hc ribs. 1 not available 2 pll feedback delay line output 3not used 4 pll vco 0 phase shift 5 pll vco 90 phase shift 6 pll vco 180 phase shift 7 pll vco 270 phase shift table 4-12 ? 2-bit feedback mux fbsel<1:0> state mux input selected 0 ground. used for power-down mode in power-down logic block. 1 pll vco 0 phase shift 2 pll delayed vco 0 phase shift 3n/a table 4-13 ? programmable delay selection for feedback delay and secondary core output delays fbdly<4:0>; dlyyb<4:0>; dlyyc<4:0> state delay value 0 typical delay = 600 ps 1 typical delay = 760 ps 2 typical delay = 920 ps ? ? 31 typical delay = 5.56 ns
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-31 table 4-14 ? programmable delay selection fo r global clock output delays dlygla<4:0>; dlyglb<4:0>; dlyglc<4:0> state delay value 0 typical delay = 225 ps 1 typical delay = 760 ps 2 typical delay = 920 ps ? ? 31 typical delay = 5.56 ns table 4-15 ? fusion dynamic ccc clock source selection rxasel dynasel source of clka 1 0 rc oscillator 1 1 crystal oscillator rxbsel dynbsel source of clkb 1 0 rc oscillator 1 1 crystal oscillator rxbsel dyncsel source of clkc 1 0 rc oscillator 1 1 crystal oscillator table 4-16 ? fusion dynamic ccc ngmux configuration glmuxcfg<1:0> ngmux select signal supported input clocks to ngmux 00 0 gla 1glc 01 0 gla 1glint 10 0 glc 1glint
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-32 v1.3 table 4-17 ? fusion dynamic ccc division by half configuration oadivhalf / obdivhalf / ocdivhalf oadiv<4:0> / obdiv<4:0> / ocdiv<4:0> (in decimal) divider factor input clock frequency output clock frequency (mhz) 1 2 1.5 100 mhz rc oscillator 66.7 4 2.5 40.0 6 3.5 28.6 8 4.5 22.2 10 5.5 18.2 12 6.5 15.4 14 7.5 13.3 16 8.5 11.8 18 9.5 10.5 20 10.5 9.5 22 11.5 8.7 24 12.5 8.0 26 13.5 7.4 28 14.5 6.9 0 0-31 1-32 other clock sources depends on other dividers setting table 4-18 ? configuration bit <76: 75> / vcosel<2:1> selection for all families voltage vcosel[2:1] 00 01 10 11 min. (mhz) max. (mhz) min. (mhz) max. (mhz) min. (mhz) max. (mhz) min. (mhz) max. (mhz) igloo and igloo plus 1.2 v 5 % 24 35 30 70 60 140 135 160 1.5 v 5 % 24 43.75 30 87.5 60 175 135 250 proasic3l, rt proasic3, and military proasic3/l 1.2 v 5 % 24 35 30 70 60 140 135 250 1.5 v 5 % 24 43.75 30 70 60 175 135 350 proasic3 and fusion 1.5 v 5 % 24 43.75 33.75 87.5 67.5 175 135 350 table 4-19 ? configuration bit <74> / vcose l<0> selection for all families vcosel[0] description 0 fast pll lock acquisition time with high tracking jitter. refer to the co rresponding datasheet for specific value and definition. 1 slow pll lock acquisition time with low tracking jitter. refer to the co rresponding datasheet for specific value and definition.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-33 software configuration smartgen automatically generates the desired ccc functional block by configuring the control bits, and allows the user to select two ccc modes: static pll and delayed clock (clkdly). static pll configuration the newly implemented visual p ll configuration wizard feature provides the user a quick and easy way to configure the pll with the desired settings ( figure 4-21 ). the user can invoke smartgen to set the parameters and generate the netlist file with the appropriate flash configuration bits set for the cccs. as mentioned in "pll macro block diagram" on page 4-9 , the input reference clock clka can be configured to be driven by hardwired i/o, external i/o, or core logic. the user enters the desired settings fo r all the parameters (output frequency, output selection, output phase adjustment, clock delay, feed back delay, and system delay). notice that the actual values (divider values, ou tput frequency, delay values, and phase) are shown to aid the user in reaching the desired design fre quency in real time. these values are typical-case data. best- and worst-case data can be observed through static timing analysis in smar ttime within designer. for dynamic configuration, the ccc parameters ar e defined using either the external jtag port or an internally defined serial interface via the bu ilt-in dynamic shift regist er. this feature provides the ability to compensate for chan ges in the external environment. figure 4-21 ? visual pll conf iguration wizard input selection fixed system delay feedback selection (feedback mux) vco clock frequency programmable output delay elements output selection
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-34 v1.3 feedback configuration the pll provides both internal and external feedback delays. depending on the configuration, various combinations of feedback delays can be achieved. internal feedback configuration this configuration essentially sets the feedback multiplexer to route the vco output of the pll core as the input to the feedback of the pll. the feedback signal can be processed with the fixed system and the adju stable feedback delay, as shown in figure 4-22 . the dividers are automatically configured by smartgen based on the user input. indicated below is the system delay pull-down me nu. the system delay can be bypassed by setting it to 0. when set, it adds a 2 ns delay to the feedback path (wh ich results in delay advancement of the output clock by 2 ns). figure 4-23 shows the controllable feedback delay. if set properly in conjunction with the fixed system delay, the total output dela y can be advanced significantly. figure 4-22 ? internal feedback with selectable system delay figure 4-23 ? internal feedback with se lectable feedback delay
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-35 external feedback configuration for certain applications, such as those requiring generation of pcb clocks that must be matched with existing board delays, it is useful to im plement an external feedback, extfb. the phase detector of the pll core will receive clka and extfb as inputs. extfb may be processed by the fixed system delay element as well as the m divider element. the extf b option is currently not supported. after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen gives the option of saving session results and messages in a log file: **************** macro parameters **************** name : test_pll family : proasic3e output format : vhdl type : static pll input freq(mhz) : 10.000 clka source : hardwired i/o feedback delay value index : 1 feedback mux select : 2 xdly mux select : no primary freq(mhz) : 33.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 66.000 use glb : yes use yb : yes glb delay value index : 1 yb delay value index : 1 secondary1 phaseshift : 0 secondary1 mux select : 4 secondary2 freq(mhz) : 101.000 use glc : yes use yc : no glc delay value index : 1 yc delay value index : 1 secondary2 phaseshift : 0 secondary2 mux select : 4 ? ? ? primary clock frequency 33.333 primary clock phase shift 0.000 primary clock output delay from clka 0.180 secondary1 clock frequency 66.667 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clka 0.180 secondary1 clock core output delay from clka 0.625 secondary2 clock frequency 100.000 secondary2 clock phase shift 0.000 secondary2 clock global output delay from clka 0.180 below is an example verilog hdl description of a legal pll core configuration generated by smartgen: module test_pll(powerdown,clka,lock,gla);
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-36 v1.3 input powerdown, clka; output lock, gla; wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); pll core(.clka(clka), .extfb(gnd), .powerdown(powerdown), .gla(gla), .lock(lock), .glb(), .yb(), .glc(), .yc(), .oadiv0(gnd), .oadiv1(gnd), .oadiv2(gnd), .oadiv3(gnd), .oadiv4(gnd), .oamux0(gnd), .oamux1(gnd), .oamux2(vcc), .dlygla0(gnd), .dlygla1(gnd), .dlygla2(gnd), .dlygla3(gnd) , .dlygla4(gnd), .obdiv0(gnd), .obdiv1(gnd), .obdiv2(gnd), .obdiv3(gnd), .obdiv4(gnd), .obmux0(gnd), .obmux1(gnd), .obmux2(gnd), .dlyyb0(gnd), .dlyyb1(gnd), .dlyyb2(gnd), .dlyyb3(gnd), .dlyyb4(gnd), .dlyglb0(gnd), .dlyglb1(gnd), .dlyglb2(gnd), .dlyglb3(gnd), .dlyglb4(gnd), .ocdiv0(gnd), .ocdiv1(gnd), .ocdiv2(gnd), .ocdiv3(gnd), .ocdiv4(gnd), .ocmux0(gnd), .ocmux1(gnd), .ocmux2(gnd), .dlyyc0(gnd), .dlyyc1(gnd), .dlyyc2(gnd), .dlyyc3(gnd), .dlyyc4(gnd), .dlyglc0(gnd), .dlyglc1(gnd), .dlyglc2(gnd), .dlyglc3(gnd) , .dlyglc4(gnd), .findiv0(vcc), .findiv1(gnd), .findiv2( vcc), .findiv3(gnd), .findiv4(gnd), .findiv5(gnd), .findiv6(gnd), .fbdiv0(vcc), .fbdiv1(gnd), .fbdiv2(vcc), .fbdiv3(gnd), .fbdiv4(gnd), .fbdiv5(gnd), .fbdiv6(gnd), .fbdly0(gnd), .fbdly1(gnd), .fbdly2(gnd), .fbdly3(gnd), .fbdly4(gnd), .fbsel0(vcc), .fbsel1(gnd), .xdlysel(gnd), .vcosel0(gnd), .vcosel1(gnd), .vcosel2(gnd)); defparam core.vcofrequency = 33.000; endmodule the "pll configuration bits descri ption" section on page 4-27 provides descriptions of the pll configuration bits for completeness. the configuration bits are shown as busses only for purposes of illustration. they wi ll actually be broken up into individu al pins in compilati on libraries and all simulation models. for example, the fbsel[1:0] bus will actually appear as pins fbsel1 and fbsel0. the setting of these select lines for the static pll configuration is performed by the software and is completely transpar ent to the user.
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-37 dynamic pll configuration to generate a dynamically reconfigur able ccc, the user should select dynamic ccc in the configuration section of the smartgen gui ( figure 4-24 ). this will ge nerate both the ccc core and the configuration shift re gister / control bit mux. even if dynamic configuration is selected in smartgen, the user must still specify the static configuration data for the ccc ( figure 4-25 ). the specified static conf iguration is used whenever the mode signal is set to low and the ccc is requ ired to function in th e static mode. the static configuration data can be used as the default behavior of the ccc where required. figure 4-24 ? smartgen gui figure 4-25 ? dynamic ccc configuration in smartgen
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-38 v1.3 when smartgen is used to define the configuration that will be sh ifted in via the serial interface, smartgen prints out the values of the 81 configurat ion bits. for ease of use, several configuration bits are automatically inferred by smartgen when the dynamic pll core is generated; however, <71:73> (statasel, statbsel, statcsel) and <7 7:79> (dynasel, dynbsel, dyncsel) depend on the input clock source of the corresponding cc c. users must first run layout in designer to determine the exact setting for these ports. after layout is complete, generate the "ccc_configuration" re port by choosing to o l s > reports > ccc_configuration in the designer software. refer to "pll configuration bits description" on page 4-27 for descriptions of the pll configuration bits. for si mulation purposes, bits <71:73> and <78:80> are "don?t cares." therefore, it is strongly suggested that smartgen be used to generate the correct configuration bit settings for the dynamic pll core. after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen gives the option of saving session results and messages in a log file: **************** macro parameters **************** name : dyn_pll_hardio family : proasic3e output format : verilog type : dynamic ccc input freq(mhz) : 30.000 clka source : hardwired i/o feedback delay value index : 1 feedback mux select : 1 xdly mux select : no primary freq(mhz) : 33.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 40.000 use glb : yes use yb : no glb delay value index : 1 yb delay value index : 1 secondary1 phaseshift : 0 secondary1 mux select : 0 secondary1 input freq(mhz) : 40.000 clkb source : hardwired i/o secondary2 freq(mhz) : 50.000 use glc : yes use yc : no glc delay value index : 1 yc delay value index : 1 secondary2 phaseshift : 0 secondary2 mux select : 0 secondary2 input freq(mhz) : 50.000 clkc source : hardwired i/o configuration bits: findiv[6:0] 0000101 fbdiv[6:0] 0100000 oadiv[4:0] 00100 obdiv[4:0] 00000 ocdiv[4:0] 00000 oamux[2:0] 100 obmux[2:0] 000 ocmux[2:0] 000 fbsel[1:0] 01 fbdly[4:0] 00000 xdlysel 0 dlygla[4:0] 00000
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-39 dlyglb[4:0] 00000 dlyglc[4:0] 00000 dlyyb[4:0] 00000 dlyyc[4:0] 00000 vcosel[2:0] 100 primary clock frequency 33.000 primary clock phase shift 0.000 primary clock output delay from clka 1.695 secondary1 clock frequency 40.000 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clkb 0.200 secondary2 clock frequency 50.000 secondary2 clock phase shift 0.000 secondary2 clock global output delay from clkc 0.200 ###################################### # dynamic stream data ###################################### -------------------------------------- |name |sdin |value |type | -------------------------------------- |findiv |[6:0] |0000101 |edit | |fbdiv |[13:7] |0100000 |edit | |oadiv |[18:14] |00100 |edit | |obdiv |[23:19] |00000 |edit | |ocdiv |[28:24] |00000 |edit | |oamux |[31:29] |100 |edit | |obmux |[34:32] |000 |edit | |ocmux |[37:35] |000 |edit | |fbsel |[39:38] |01 |edit | |fbdly |[44:40] |00000 |edit | |xdlysel |[45] |0 |edit | |dlygla |[50:46] |00000 |edit | |dlyglb |[55:51] |00000 |edit | |dlyglc |[60:56] |00000 |edit | |dlyyb |[65:61] |00000 |edit | |dlyyc |[70:66] |00000 |edit | |statasel|[71] |x |masked | |statbsel|[72] |x |masked | |statcsel|[73] |x |masked | |vcosel |[76:74] |100 |edit | |dynasel |[77] |x |masked | |dynbsel |[78] |x |masked | |dyncsel |[79] |x |masked | |reseten |[80] |1 |readonly | below is the resultant verilog hdl description of a legal dynamic pll core configuration generated by smartgen: module dyn_pll_macro(powerdown, clka, lock, gla, glb, glc, sdin, sclk, sshift, supdate, mode, sdout, clkb, clkc); input powerdown, clka; output lock, gla, glb, glc; input sdin, sclk, sshift, supdate, mode; output sdout; input clkb, clkc; wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd));
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-40 v1.3 dynccc core(.clka(clka), .extfb(gnd), .powerdown(powerdown), .gla(gla), .lock(lock), .clkb(clkb), .glb(glb), .yb(), .clkc(clkc), .glc(glc), .yc(), .sdin(sdin), .sclk(sclk), .sshift(sshift), .supdate(supdate), .mode(mode), .sdout(sdout), .oadiv0(gnd), .oadiv1(gnd), .oadiv2(vcc), .oadiv3(gnd), .oadiv4(gnd), .oamux0(gnd), .oamux1(gnd), .oamux2(vcc), .dlygla0(gnd), .dlygla1(gnd), .dlygla2(gnd), .dlygla3(gnd), .dlygla4(gnd), .obdiv0(gnd), .obdiv1(gnd), .obdiv2(gnd), .obdiv3(gnd), .obdiv4(gnd), .obmux0(gnd), .obmux1(gnd), .obmux2(gnd), .dlyyb0(gnd), .dlyyb1(gnd), .dlyyb2(gnd), .dlyyb3(gnd), .dlyyb4(gnd), .dlyglb0(gnd), .dlyglb1(gnd), .dlyglb2(gnd), .dlyglb3(gnd), .dlyglb4(gnd), .ocdiv0(gnd), .ocdiv1(gnd), .ocdiv2(gnd), .ocdiv3(gnd), .ocdiv4(gnd), .ocmux0(gnd), .ocmux1(gnd), .ocmux2(gnd), .dlyyc0(gnd), .dlyyc1(gnd), .dlyyc2(gnd), .dlyyc3(gnd), .dlyyc4(gnd), .dlyglc0(gnd), .dlyglc1(gnd), .dlyglc2(gnd), .dlyglc3(gnd), .dlyglc4(gnd), .findiv0(vcc), .findiv1(gnd), .findiv2(vcc), .findiv3(gnd), .findiv4(gnd), .findiv5(gnd), .findiv6(gnd), .fbdiv0(gnd), .fbdiv1(gnd), .fbdiv2(gnd), .fbdiv3(gnd), .fbdiv4(gnd), .fbdiv5(vcc), .fbdiv6(gnd), .fbdly0(gnd), .fbdly1(gnd), .fbdly2(gnd), .fbdly3(gnd), .fbdly4(gnd), .fbsel0(vcc), .fbsel1(gnd), .xdlysel(gnd), .vcosel0(gnd), .vcosel1(gnd), .vcosel2(vcc)); defparam core.vcofrequency = 165.000; endmodule delayed clock configuration the clkdly macro can be generated with the desi red delay and input clock source (hardwired i/o, external i/o, or core logic), as in figure 4-26 . after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen gives the option of saving session results and messages in a log file: **************** macro parameters **************** name : delay_macro family : proasic3 output format : verilog type : delayed clock delay index : 2 clka source : hardwired i/o total clock delay = 0.935 ns. the resultant clkdly macro verilog netlist is as follows: module delay_macro(gl,clk); output gl; input clk; figure 4-26 ? delayed clock configuration dialog box
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-41 wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); clkdly inst1(.clk(clk), .gl(gl), .dlygl0(vcc), .dlygl1(gnd), .dlygl2(vcc), .dlygl3(gnd), .dlygl4(gnd)); endmodule detailed usage information clock frequency synthesis deriving clocks of various fre quencies from a single reference clock is known as frequency synthesis. the pll has an input frequency range from 1.5 to 350 mh z. this frequency is automatically divided down to a range between 1.5 mhz and 5.5 mhz by input dividers (not shown figure 4-17 on page 4-22 ) between pll macro inputs and p ll phase detector inputs. the vco output is capable of an output range from 24 to 350 mhz. with dividers befo re the input to the pll core and following the vc o outputs, the vco output frequency can be divided to provide the final frequency range from 0.75 to 350 mhz. using smar tgen, the dividers are automatically set to achieve the closest possib le matches to the specified output frequencies. users should be cautious when selecting the de sired pll input and output frequencies and the i/o buffer standard used to connect to the pll input and output clocks. depending on the i/o standards used for the pll input and output cloc ks, the i/o frequencies have different maximum limits. refer to the fami ly datasheets for specifications of maximum i/o frequencies for supported i/o standards. desired p ll input or output frequencies will not be achieved if the selected frequencies are higher than the maximum i/o frequencies allowed by the selected i/o standards. users should be careful when selecting the i/o standards used for pll in put and output clocks. performing post-layout simulation ca n help detect this type of error, which will be identified with pulse width violation errors. use rs are strongly encouraged to pe rform post-layout simulation to ensure the i/o standard used can provide the desi red pll input or output frequencies. users can also choose to cascade p lls together to achieve the high frequ encies needed for their applications. details of cascading plls are discussed in the "cascading cccs" section on page 4-46 . in smartgen, the actual generated frequency (under typical operating conditions) will be displayed beside the requested output frequency value. th is provides the ability to determine the exact frequency that can be generated by smartgen, in real time. the log file generated by smartgen is a useful tool in determining how closely th e requested clock frequencies match the user specifications. for example, assume a user sp ecifies 101 mhz as one of the secondary output frequencies. if the best output frequency that could be achi eved were 100 mhz, the log file generated by smartgen would indicate the actual generated frequency. simulation verification the integration of the generated pll and clkdly modules is similar to any vhdl component or verilog module instantiation in a larger design; i. e., there is no special re quirement that users need to take into account to successf ully synthesize their designs. for simulation purposes, users need to refer to the vital or verilog library that includes the functional descript ion and associated timing parameters. refer to the software tools section of the actel website to obtain the family simulation libraries. if actel desi gner is installed, these libraries are stored in the following locations: \lib\vtl\95\proasic3.vhd \lib\vtl\95\proasic3e.vhd \lib\vlog\ proasic3.v \lib\vlog\ proasic3e.v
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-42 v1.3 for libero ide users, there is no need to compil e the simulation libraries, as they are conveniently pre-compiled in the model sim ? actel simulation tool. the following is an example of a pll configuratio n utilizing the clock frequency synthesis and clock delay adjustment features. the ste ps include generating the pll core with smartgen, performing simulation for verifi cation with model sim , and performing stat ic timing analysis with smarttime in designer. parameters of the example pll configuration: input frequency ? 20 mhz primary output requirement ? 20 mhz with clock advancement of 3.02 ns secondary 1 output requirement ? 40 mhz with clock delay of 2.515 ns figure 4-27 shows the smartgen settings. notice that the overall delays are calculated automatically, allowing the user to adjust the delay elements appropriately to obtain the desired delays. after confirming the correct settings, generate a structural netlist of th e pll and verify pll core settings by checking the log file: name : test_pll_delays family : proasic3e output format : vhdl type : static pll input freq(mhz) : 20.000 clka source : hardwired i/o feedback delay value index : 21 feedback mux select : 2 xdly mux select : no primary freq(mhz) : 20.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 40.000 use glb : yes use yb : no figure 4-27 ? smartgen settings
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-43 ? ? ? primary clock frequency 20.000 primary clock phase shift 0.000 primary clock output delay from clka -3.020 secondary1 clock frequency 40.000 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clka 2.515 next, perform simulation in model sim to verify the correct delays. figure 4-28 shows the simulation results. the delay values match those reported in the smartgen pll wizard. the timing can also be analyzed using smarttim e in designer. the user should import the synthesized netlist to designer, perform compile and layout, and then invoke smarttime. go to tools > options and change the maximum delay operating conditions to typical case . then expand the clock-to-out paths of gla and glb and the in dividual components of the path delays are shown. the path of gla is shown in figure 4-29 on page 4-44 displaying the sa me delay value. figure 4-28 ? model sim simulation results primary clock output time advancement from clka secondary1 clock global output delay from clka
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-44 v1.3 place-and-route stage considerations several considerations must be noted to properly place the ccc macros for layout. for cccs with clock inputs configured with the hardwired i/o?driven option: ? pll macros must have the cl ock input pad coming from one of the gma* locations. ? clkdly macros must have the clock input pad coming from one of the global i/os. if a pll with a hardwired i/o in put is used at a ccc location and a hardwired i/o?driven clkdly macro is used at the same ccc location, the clock input of the clkdly macro must be chosen from one of the gmb* or gmc* pin locations. if the pll is not used or is an external i/o?driven or core logic?driven pll, the clock input of the clkd ly macro can be sourced from the gma*, gmb*, or gmc* pin locations. for cccs with clock inputs configured with the ex ternal i/o?driven option, the clock input pad can be assigned to any regular i/o location (io*** ***** pins). note that sinc e global i/o pins can also be used as regular i/os, regardle ss of ccc function (clkdly or pll), clock inputs can also be placed in any of these i/o locations. by default, the designer layout engine will place global nets in the design at one of the six chip globals. when the number of glob als in the design is greater than six, the designer layout engine will automatically assign addition al globals to the quadrant global networks of the low-power flash devices. if the user wishes to decide which global signals should be assigned to chip globals (six available) and which to the quadrant globals (three per quadrant for a total of 12 available), the assignment can be achieved with pineditor, chipplanner, or by importing a placement figure 4-29 ? static timing analysis using smarttime
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-45 constraint file. layout will fail if the global assignments are not allocated properly. see the "physical constraints for quadrant clocks" section for information on assi gning global signals to the quadrant clock networks. promoted global signals will be instantiated with clkint macros to drive these signals onto the global network. this is automatically done by designer when the au to-promotion option is selected. if the user wishes to as sign the signals to th e quadrant globals inst ead of the default chip globals, this can done by using chipplanner, by de claring a physical design constraint (pdc), or by importing a pdc file. physical constraints for quadrant clocks if it is necessary to promote global clocks (clkbuf, clkint, pll, clkdly) to quadrant clocks, the user can define pdcs to execute the promotion. pdcs can be created using pdc commands (pre- compile) or the multiview naviga tor (mvn) interface (post-compil e). the advantag e of using the pdc flow over the mvn flow is that the compile st age is able to automati cally promote any regular net to a global net befo re assigning it to a quadrant. there are three options to place a quadrant clock using pdc commands: ? place a clock core (not hardwired to an i/o) into a quadrant clock location. ? place a clock core (hardwired to an i/o) in to an i/o location (set_io) or an i/o module location (set_location) that dr ives a quadrant clock location. ? assign a net driven by a regular net or a cloc k net to a quadrant clock using the following command: assign_local_clock -net -type quadrant where is the name of the net assigned to the local user clock region. defines which quadrant the net should be assigned to. quadrant clock regions are defined as ul (upper left), ur (upper right), ll (low er left), and lr (lower right). note: if the net is a regular net, the software inserts a clkint buffer on the net. for example: assign_local_clock -net localreset -type quadrant ur keep in mind the following when placing quadrant clocks using multiview navigator: hardwired i/o?driven cccs ? find the associated cl ock input port under th e ports tab, and place the input port at one of the gmn* locations using pineditor or i/o attribute editor, as shown in figure 4-30 . figure 4-30 ? port assignment for a ccc with hardwired i/o clock input
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-46 v1.3 ? use quadrant global region assignments by finding the clock net as sociated with the ccc macro under the nets tab and creating a quadra nt global region for the net, as shown in figure 4-31 . external i/o?driven cccs the above-mentioned recommendation for proper layout techniques wi ll ensure the correct assignment. it is possible that, es pecially with external i/o?driv en ccc macros, placement of the ccc macro in a desired location may not be achieved. for example, assigning an input port of an external i/o?driven ccc near a particular ccc lo cation does not guarante e global assignments to the desired location. this is because the clock inputs of external i/o?driven cccs can be assigned to any i/o location; therefore, it is possible that th e ccc connected to the clock input will be routed to a location other than the one cl osest to the i/o location, depend ing on resource availability and placement constraints. clock placer the clock placer is a placement en gine for low-power flash devices that places global signals on the chip global and quadrant global networks. based on the clock assignment constraints for the chip global and quadrant global clocks, it will try to satisfy all constraints, as well as creating quadrant clock regions when necessary. if th e clock placer fails to create th e quadrant clock regions for the global signals, it will repo rt an error and stop layout. the user must ensure that the co nstraints set to promote clock sign als to quadrant global networks are valid. cascading cccs the cccs in low-power flash devices can be cascaded. cascading cccs can help achieve more accurate pll output frequency resu lts than those achievable with a single ccc. in addition, this technique is useful when the user application requires the output clock of the pll to be a multiple of the reference clock by an integer greater than the maximum feedback divider value of the pll (divide by 128) to achieve the desired frequency. for example, the user application may requir e a 280 mhz output clock using a 2 mhz input reference clock, as shown in figure 4-32 on page 4-47 . figure 4-31 ? quadrant clock assignment for a global net
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-47 using internal feedback, we know from eq 4-1 on page 4-24 that the maximum achievable output frequency from the primary output is f gla = f clka m / (n u) = 2 mhz 128 / (1 1) = 256 mhz eq 4-5 figure 4-33 shows the settings of the initial pll. when configuring the initial pll, specify the input to be either hardwired i/o?driven or external i/o?driven. this generates a netlist with the initial pll routed from an i/o. do not sp ecify the input to be core logi c?driven, as this prohibits the connection from the i/o pin to the input of the pll. a second pll can be connected serially to achieve the required frequency. eq 4-1 on page 4-24 to eq 4-3 on page 4-24 are extended as follows: f gla2 = f gla m 2 / (n 2 u 2 ) = f clka1 m 1 m 2 / (n 1 u 1 n 2 u 2 ) ? primary pll output clock eq 4-6 f glb2 = f yb2 = f clka1 m 1 m 2 / (n 1 n 2 v 1 v 2 ) ? secondary 1 pll output clock(s) eq 4-7 f glc2 = f yc2 = f clka1 m 1 m 2 / (n 1 n 2 w 1 w 2 ) ? secondary 2 pll output clock(s) eq 4-8 in the example, the final output frequency (f output ) from the primary output of the second pll will be as follows ( eq 4-9 ): f output = f gla2 = f gla m 2 / (n 2 u 2 ) = 256 mhz 70 / (64 1) = 280 mhz eq 4-9 figure 4-34 on page 4-48 shows the settings of the second p ll. when configuring the second pll (or any subsequent-stage plls), sp ecify the input to be core logic? driven. this gene rates a netlist with the second pll routed internally from the co re. do not specify the in put to be hardwired i/o? driven or external i/o?driven, as these options prohibit the connection from the output of the first pll to the input of the second pll. figure 4-32 ? cascade pll configuration figure 4-33 ? first-stage pll showing input of 2 mhz and output of 256 mhz
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-48 v1.3 figure 4-35 shows the simulation results, where the first pll?s outp ut period is 3.9 ns (~256 mhz), and the stage 2 (final) output period is 3.56 ns (~280 mhz). figure 4-34 ? second-stage pll showing input of 256 mhz from first stage and final output of 280 mhz figure 4-35 ? model sim simulation results stage 1 output clock period stage 2 output clock period
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-49 recommended board-level considerations the power to the pll core is supplied by v ccpla/b/c/d/e/f (v ccplx) , and the associated ground connections are supplied by v compla/b/c/d/e/f (v complx ). when the plls are not used, the actel designer place-and-route tool automatically disables the unused plls to lower power consumption. the user should tie unused v ccplx and v complx pins to ground. optionally, the pll can be turned on/off during normal devi ce operation via the powerdown port (see table 4-3 on page 4-8 ). pll power supply decoupling scheme the pll core is designed to tole rate noise levels on the pll po wer supply as specified in the datasheets. when operated within the noise limits, the pll will meet the ou tput peak-to-peak jitter specifications specified in the datasheets. user applications should al ways ensure the pll power supply is powered from a no ise-free or low-no ise power source. however, in situations where the pll power supply noise level is higher th an the tolerable limits, various decoupling schemes can be designed to suppress noise to th e pll power supply. an example is provided in figure 4-36 . the v ccplx and v complx pins correspond to the pll analog power supply and ground. actel strongly recommends that tw o ceramic capacitors (10 nf in parallel with 100 nf) be placed close to the power pins (less than 1 inch away ). a third generic 10 f electrolytic capacitor is recommended for low-frequency noise and should be placed farther away due to its large physical size. actel recommends that a 6.8 h inductor be placed between the supply source and the capacitors to filter out any low-/medium- and hi gh-frequency noise. in addition, the pcb layers should be controlled so the v ccplx and v complx planes have the minimum separation possible, thus generating a good-quality rf capacitor. for more recommendations, refer to the board-level considerations application note. recommended 100 nf capacitor: ? producer bc components, type x7r, 100 nf, 16 v ? bc components part number: 0603b104k160bt ? digi-key part number: bc1254ct-nd ? digi-key part number: bc1254tr-nd recommended 10 nf capacitor: ? surface-mount ceramic capacitor ? producer bc components, type x7r, 10 nf, 50 v ? bc components part number: 0603b103k500bt ? digi-key part number: bc1252ct-nd ? digi-key part number: bc1252tr-nd figure 4-36 ? decoupling scheme for one pll (should be replicated for each pll used) igloo/e or proasic3/e device power supply v ccplx v complx 10 nf 100 nf 10 f
clock conditioning circuits in low-power flash devices and mixed-signal fpgas 4-50 v1.3 conclusion the advanced cccs of th e igloo and proasic3 families are idea l for applications requiring precise clock management. they integrat e easily with the inte rnal low-skew clock networks and provide flexible frequency synthesis, clock de-skewing, and/or time shifting operations. related documents application notes board-level considerations http://www.actel.com/documents/boardlevelcons_an.pdf handbook documents ujtag applications in acte l?s low-power flash devices http://www.actel.com/documents/lpd_ujtag_hbs.pdf global resources in actel low-power flash devices http://www.actel.com/documents/lpd_global_hbs.pdf user i/o naming conventions in i/o stru ctures in igloo an d proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf user?s guides igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-006-3 revised october 2008
clock conditioning circuits in low-power flash devices and mixed-signal fpgas v1.3 4-51 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.3) page v1.3 (june 2008) this document was updated to incl ude fusion and rt proasic3 device information. please review th e document very carefully. n/a the "ccc support in actel?s low-p ower flash devi ces" section was updated. 4-3 in the "global buffer with programmable delay" section , the following sentence was changed from: "in this case, the i/o must be placed in one of the dedicated global i/o locations." to "in this case, the software will automatica lly place the dedicated global i/o in the appropriate locations." 4-4 figure 4-4 ccc options: gl obal buffers with pll was updated to include oadivrst and oadivhalf. 4-7 in figure 4-5 ccc with pll block "fixed delay" was changed to "programmable delay". 4-7 table 4-3 input and output signals of the pll block was updated to include oadivrst and oadivhalf descriptions. 4-8 table 4-7 configuration bit de scriptions for the ccc blocks was updated to include configuration bits 88 to 81. note 2 is new. in addition, the description for bit <76:74> was updated. 4-27 table 4-15 fusion dynamic ccc clock source selection and table4-16fusion dynamic ccc ngmux configuration are new. 4-31 table 4-17 fusion dynamic ccc division by half configuration and table 4-18 configuration bit <76:75> / vcosel<2:1> selectio n for all families are new. 4-32 v1.1 (march 2008) the following changes were made to the family descriptions in table 4-1 overview of the cccs offe red in fusion, igloo, and proasic3 : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 4-1 v1.0 (january 2008) table 4-1 low-power flash families and the associated text were updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 4-3 the "global input selections" section was updated to include 15 k gate devices as supported i/o types for globals, for ccc only. 4-10 table 4-5 number of cccs by device size and package was revised to include proasic3l, igloo plus, a3p015, ag l015, aglp030, aglp060, and aglp125. 4-16 the "igloo and proasic3 ccc locations" section was revised to include 15 k gate devices in the exception statements, as they do not contain plls. 4-18 51900133-0/5.06 information about unlocking the pll was removed from the "dynamic pll configuration" section . 4-24 in the "dynamic pll configuration" section , information was added about running layout and determining the exact setting of the ports. 4-37 in table 4-7 configuration bit descriptions for the ccc blocks , the following bits were updated to delete "transport to the user" and reference the footnote at the bottom of the table: 79 to 71. 4-27

embedded memories

v1.3 5-1 5 ? flashrom in actel?s low-power flash devices introduction the fusion, igloo, ? and proasic ? 3 families of low-power flash-based devices have a dedicated nonvolatile flashrom memory of 1,024 bits, which provides a unique feature in the fpga market. the flashrom can be read, modified, and written using the jtag (or ujtag) interface. it can be read but not modified from the fpga core. only low-power flash devices contain on-chip user nonvolatile memory (nvm). architecture of user nonvolatile flashrom low-power flash devices have 1 kbit of user-acce ssible nonvolatile flash me mory on-chip that can be read from the fpga core fabr ic. the flashrom is arranged in eight banks of 128 bits (16 bytes) during programming. the 128 bits in each bank are addressable as 16 bytes during the read-back of the flashrom from the fpga core. figure 5-1 shows the flashrom logical structure. the flashrom can only be programmed via the ieee 1532 jtag port. it cannot be programmed directly from the fpga core. when programming, each of the eight 128-bit banks can be selectively reprogrammed. the flashrom ca n only be reprogrammed on a bank boundary. programming involves an automatic, on-chi p bank erase prior to reprogramming the bank. the flashrom supports synchronous read. the ad dress is latched on the rising ed ge of the clock, and the new output data is stable after the fa lling edge of the same clock cycl e. for more information, refer to the timing diagrams in the appropriate family data sheet dc and switching characteristics chapter. the flashrom can be read on by te boundaries. the upper three bi ts of the flashrom address from the fpga core define the bank being accessed. th e lower four bits of th e flashrom address from the fpga core define which of the 16 by tes in the bank is being accessed. figure 5-1 ? flashrom architecture bank number 3 msb of addr (read) byte number in bank 4 lsb of addr (read) 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
flashrom in actel?s lo w-power flash devices 5-2 v1.3 flashrom support in low-power devices the low-power flash families listed in table 5-1 support the flashrom fe ature and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 5-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 5-1 . where the informati on applies to only one fa mily or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 5-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
flashrom in actel?s lo w-power flash devices v1.3 5-3 figure 5-2 ? fusion device architecture overview (afs600) figure 5-3 ? proasic3 and igloo de vice architecture versatile ccc ccc i/os osc ccc/pll bank 0 bank 4 bank 2 bank 1 bank 3 sram block 4,608-bit dual-port sram or fifo block sram block 4,608-bit dual-port sram or fifo block flash memory blocks flash memory blocks adc analog quad isp aes decryption user nonvolatile flashrom charge pumps analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad 4,608-bit dual-port sram or fifo block versatile ram block ccc pro i/os isp aes decryption nonvolatile memory flashrom charge pumps 4,608-bit dual-port sram or fifo block ram block
flashrom in actel?s lo w-power flash devices 5-4 v1.3 flashrom applications the smartgen core generator is used to configure flashrom content. you can configure each page independently. smartgen enables you to create and modify regions within a page; these regions can be 1 to 16 bytes long ( figure 5-4 ). the flashrom content can be changed independentl y of the fpga core content. it can be easily accessed and programmed via jtag, depending on the security settings of the device. the smartgen core generator enables each region to be independently updated (described in the "programming and accessing flashrom" section on page 5-6 ). this enables you to change the flashrom content on a per-part ba sis while keeping some regions "constant" for all parts. these features allow the flashrom to be used in dive rse system applications. consider the following possible uses of flashrom: ? internet protocol (ip) addressing (wireless or fixed) ? system calibration settings ? restoring configuration after unpredictable system power-down ? device serialization and/or inventory control ? subscription-based business mo dels (e.g., set-top boxes) ? secure key storage ? asset management tracking ? date stamping ? version management figure 5-4 ? flashrom configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 byte number in page page number
flashrom in actel?s lo w-power flash devices v1.3 5-5 flashrom security low-power flash devices have an on-chip advanc ed encryption standard (aes) decryption core, combined with an enhanced version of the actel flash-based lock technology (flashlock ? ). together, they provide unmatched levels of securi ty in a programmable logi c device. this security applies to both the fpga core and flashrom content. these de vices use the 128-b it aes (rijndael) algorithm to encr ypt programming files for se cure transmission to the on-chip aes decryption core. the same algorithm is then used to decrypt the programming file. this key size provides approximately 3.4 10 38 possible 128-bit keys. a computing sy stem that could find a des key in a second would take approximately 149 trillion years to crack a 128-bit aes key. the 128-bit flashlock feature in low-power flash devices wo rks via a flashlock secu rity pass key mechanism, where the user locks or un locks the device with a us er-defined key. refer to security in low-power flash devices . if the device is locked with cert ain security settings, fu nctions such as device read, write, and erase are disabled. this unique feature helps to pr otect against invasive and noninvasive attacks. without the correct pass key, access to the fpga is denied. to gain access to the fpga, the device first must be unlocked us ing the correct pass key. during pr ogramming of the flashrom or the fpga core, you can generate the security header programming file, which is used to program the aes key and/or flashlock pass key. the security header programming file can also be generated independently of the flashrom and fpga core conten t. the flashlock pass key is not stored in the flashrom. low-power flash devices with aes-based security al low for secure remote field updates over public networks such as the internet, and ensure that va luable intellectual prop erty (ip) remains out of the hands of ip thieves. figure 5-5 shows this flow diagram. figure 5-5 ? programming flashrom using aes flash device aes encryption encrypted data aes-128 decryption core encrypted data flashrom fpga core programming data untrusted medium same aes key
flashrom in actel?s lo w-power flash devices 5-6 v1.3 programming and accessing flashrom the flashrom content can only be programmed via jtag, but it can be read back selectively through the jtag programming interface, the ujtag interface, or via direct fpga core addressing. the pages of the flashrom can be made secure to prevent read-back via jtag. in that case, read- back on these secured pages is only possibl e by the fpga core fabric or via ujtag. a 7-bit address from the fpga core defines which of the eight pages (three msbs) is being read, and which of the 16 bytes with in the selected page (four lsbs) are being read. the flashrom content can be read on a random basis; the access time is 10 ns for a device supporting commercial specifications. the fpga core will be powered down during writing of the flashrom content. fpga power-down during flashrom programming is ma naged on-chip, and fpga core functionality is not available during programming of the flashrom. table 5-2 summarizes various flashrom access scenarios. figure 5-6 shows the accessing of the flashrom using th e ujtag macro. this is similar to fpga core access, where the 7-bit address defines which of the eight pages (three msbs) is being read and which of the 16 bytes within the selected page (four lsbs) are being read. refer to ujtag applications in actel?s low-power flash devices for details on using the ujtag macro to read the flashrom. figure 5-7 on page 5-7 and figure 5-8 on page 5-7 show the flashrom access from the jtag port. the flashrom content can be read on a random ba sis. the three-bit addres s defines which page is being read or updated. table 5-2 ? flashrom read/write capa bilities by access mode access mode flashrom read flashrom write jtag yes yes ujtag yes no fpga core yes no figure 5-6 ? block diagram of using ujtag to read flashrom contents flashrom addr [6:0] data[7:0] clk enable sdo sdi reset addr [6:0] data [7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg [7:0] control ujtag address generation and data serialization
flashrom in actel?s lo w-power flash devices v1.3 5-7 figure 5-7 ? accessing flashrom using fpga core figure 5-8 ? accessing flashrom using jtag port 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 word number in page 4 lsb of addr (read) page number 3 msb of addr (read) 3-bit page address 111 1110000 7-bit address from core 0000 4-bit word address 8-bit data 8-bit data to fpga core 8-bit data from page 7 word 0 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 word number in page 4 lsb of addr (read) page number 3 msb of addr (read) 4-bit page address from jtag interface to/from jtag interface ...........................00001:128 bit data
flashrom in actel?s lo w-power flash devices 5-8 v1.3 flashrom design flow the actel libero ? integrated design environment (ide) software has extensive flashrom support, including flashrom generation, instanti ation, simulation, and programming. figure 5-9 shows the user flow diagram. in the design flow, ther e are three main steps: 1. flashrom generation and instantiation in the design 2. simulation of flashrom design 3. programming file genera tion for flashrom design figure 5-9 ? flashrom design flow simulator flashpoint smartgen programmer synthesis designer security header options programming files ufc file flashrom netlist user design user netlist core map mem file back- annotated netlist
flashrom in actel?s lo w-power flash devices v1.3 5-9 flashrom generation and in stantiation in the design the smartgen core genera tor, available in libero ide and designer, is the only tool that can be used to generate the flashrom content. smartgen has several user-friendly features to help generate the flashrom contents. instead of selecting each byte and assigning values, you can create a region within a page, mo dify the region, and assign properties to that region. the flashrom user interface, shown in figure 5-10 on page 5-9 , includes the configuration grid, existing regions list, and properties field. the properti es field specifies the region-spe cific information and defines the data used for that region. you can assi gn values to the following properties: 1. static fixed data?enables yo u to fix the data so it canno t be changed during programming time. this option is useful when you have fixe d data stored in this region, which is required for the operation of the design in the fpga. key storage is one example. 2. static modifiable data?select this option when th e data in a particular region is expected to be static data (such as a version number, wh ich remains the same for a long duration but could conceivably change in th e future). this op tion enables you to avoid changing the value every time you enter new data. 3. read from file?this provides the full flexibil ity of flashrom usage to the customer. if you have a customized algorithm fo r generating the flashrom data, you can specify this setting. you can then generate a text file with data fo r as many devices as you wish to program, and load that into the flashpoint programming file generation softw are to get programming files that include all the data. smartgen will optionally pass the location of the file where the data is stored if the file is specified in smartgen. each text file has only one type of data format (binary, decimal, hex, or ascii text). the length of each data file must be shorter than or equal to the selected region length. if the data is shorter th an the selected region length, the most signific ant bits will be padded with 0s. fo r multiple text files for multiple regions, the first li nes are for the first device. in smartgen, load sim. value from file allows you to load the first device data in the mem file for simulation. 4. auto increment/decrement?this scenario is useful when you specify the contents of flashrom for a large number of devices in a series. you can specify the step value for the serial number and a maximum value for in ventory control. during programming file generation, the actual number of devices to be programmed is specified and a start value is fed to the software. figure 5-10 ? smartgen gui of the flashrom
flashrom in actel?s lo w-power flash devices 5-10 v1.3 smartgen allows you to generate the flashrom netl ist in vhdl, verilog, or edif format. after the flashrom netlist is generated, the core can be instantiated in the main design like other smartgen cores. note that the macro library name for flashrom is ufrom. the following is a sample flashrom vhdl netlist that can be instantiated in the main design: library ieee; use ieee.std_logic_1164.all; library fusion; entity from_a is port( addr : in std_logic_vector(6 downto 0); dout : out std_logic_vector(7 downto 0)); end from_a; architecture def_arch of from_a is component ufrom generic (memoryfile:string); port(do0, do1, do2, do3, do4, do5, do6, do7 : out std_logic; addr0, addr1, addr2, addr3, addr4, addr5, addr6 : in std_logic := 'u') ; end component; component gnd port( y : out std_logic); end component; signal u_7_pin2 : std_logic ; begin gnd_1_net : gnd port map(y => u_7_pin2); ufrom0 : ufrom generic map(memoryfile => "from_a.mem") port map(do0 => dout(0), do1 => dout(1), do2 => dout(2), do3 => dout(3), do4 => dout(4), do5 => dout(5), do6 => dout(6), do7 => dout(7), addr0 => addr(0), addr1 => addr(1), addr2 => addr(2), addr3 => addr(3), addr4 => addr(4), addr5 => addr(5), addr6 => addr(6)); end def_arch; smartgen generates the following files along with the netlist. th ese are located in the smartgen folder for the li bero ide project. 1. mem (memory initialization) file 2. ufc (user flash configuration) file 3. log file the mem file is used for simulation, as explained in the "simulation of flashrom design" section . the ufc file, generated by smar tgen, has the flashrom configur ation for single or multiple devices and is used during stapl generation. it contains the region properties and simulation values. note that any changes in the mem file will not be reflected in th e ufc file. do not modify the ufc to change flashrom content. instead, use the smartgen gui to modify the flashrom content. see the "programming file generation for fl ashrom design" section on page 5-11 for a description of how the ufc file is used during the programming file gene ration. the log file has information regarding the file type and file location.
flashrom in actel?s lo w-power flash devices v1.3 5-11 simulation of flashrom design the mem file has 128 rows of 8 bits, each repres enting the contents of the flashrom used for simulation. for example, the first row represents page 0, byte 0; the next row is page 0, byte 1; and so the pattern continues. note that the three msbs of the addr ess define the page number, and the four lsbs define the byte number . so, if you send address 0000100 to flashrom, this corresponds to the page 0 and byte 4 location, which is the fifth row in the mem file. smartgen defaults to 0s for any unspecified location of the flashrom. besides using the mem file generated by smartgen, you can create a binary file with 128 rows of 8 bits each and use this as a mem file. actel recommends that you use different file names if you plan to genera te multiple mem files. during simulation, libero ide passes the mem file used as the generic fi le in the netlist, along with the design files and testbench. if you want to use different mem f iles during simulation, you need to modify the generic file reference in the netlist. ??????? ufrom0: ufrom --generic map(memoryfile => "f:\appsnotes\from\test_designs\testa\smartgen\from_a.mem") --generic map(memoryfile => "f:\appsnotes\from\test_designs\testa\smartgen\from_b.mem") ????????. the vital and verilog simulation mo dels accept the generics passed by the netlist, read the mem file, and perform simulation wi th the data in the file. programming file generation for flashrom design flashpoint is the programming software used to generate the programming files for flash devices. depending on the applications, you can use the fl ashpoint software to generate a stapl file with different flashrom contents. in each case, optional aes decryption is available. to generate a stapl file that contains the same fpga core content and different flashrom contents, the flashpoint software needs an array map file fo r the core and ufc file(s ) for the flashrom. this final stapl file represents the combination of the logic of the fpga core and flashrom content. flashpoint generates the stapl files you can use to program the desired flashrom page and/or fpga core of the fpga device contents. flashp oint supports the encryp tion of the flashrom content and/or fpga array configuration data. in the case of using the flashrom for device serialization, a sequence of un ique flashrom contents will be generated. when generating a programming file with mu ltiple unique flashrom contents, yo u can specify in flashpoint whether to include all flashrom content in a single stapl file or generate a different stapl file for each flashrom ( figure 5-11 ). the programming software (flashpro) handles the single stapl file that contains the flashr om content from multiple devices. it enables you to program the flashrom content into a series of devices sequentially ( figure 5-11 ). see the flashpro user?s guide for information on serial programming. figure 5-11 ? single or multiple programming file generation flashpoint fpga arrary map file fpga arrary map file security settings security settings ufc file for multiple flashrom content ufc file for single flashrom content flashpoint single stapl file single stapl file single stapl file
flashrom in actel?s lo w-power flash devices 5-12 v1.3 figure 5-12 on page 5-12 shows the programming file generato r, which enables different stapl file generation methods. when you select program flashrom and choose the ufc file, the flashrom settings window appears, as shown in figure 5-13 on page 5-12 . in this window, you can select the flashrom page you want to program and the data value for the configured regions. this enables you to use a different page for different programming files. the programming hardware and software can load the flashrom with the appropriate stapl file. programming software handles the single stapl file that contains multiple flashrom contents for multiple devices, and programs th e flashrom in sequential order (e .g., for device serialization). figure 5-12 ? programming file generator figure 5-13 ? setting flashrom during pr ogramming file generation
flashrom in actel?s lo w-power flash devices v1.3 5-13 this feature is supported in the programming so ftware. after programming with the stapl file, you can run device_info to check the flashrom content. device_info displays the flashrom content, serial number, de sign name, and checksum as shown below: export idcode[32] = 123261cf export silsig[32] = 00000000 user information : checksum: 61a0 design name: top programming method: stapl algorithm version: 1 programmer: unknown ========================================= flashrom information : export region_7_0[128] = ffffffffffffffffffffffffffffffff ========================================= security setting : encrypted flashrom programming enabled. encrypted fpga array programming enabled. ========================================= the libero ide file manager re cognizes the ufc and mem files and displays them in the appropriate view. libero ide also recognizes the multiple progra mming files, if you choose the option to generate multiple files for multiple fl ashrom content in design er. these features enable a user-friendly flow for the flashrom ge neration and programming in libero ide. custom serialization using flashrom you can use flashrom for device serialization or inventory control by using the auto inc region or read from file region. flashpoint will automatica lly generate the serial number sequen ce for the auto inc region with the start value , max value , and step value provided. if you have a unique serial number generation scheme that you prefer, the read from file region allows you to import the file with your serial number scheme programmed into the region. see the flashpro user's guide for custom serialization file format information. the following steps describe ho w to perform device serializatio n or inventory control using flashrom: 1. generate flashrom using smartgen. from the properties section in the flashrom settings dialog box, select auto inc or read from file region. for auto inc region, specify the desired step value. you will not be able to modify this value in the flashpoint software. 2. go through the regula r design flow and finish place-and-route. 3. select programming file in designer and open generate programming file ( figure 5-12 on page 5-12 ). 4. click program flashrom , browse to the ufc file, and click next . the flashrom settings window appears, as shown in figure 5-13 on page 5-12 . 5. select the flashrom page you want to pr ogram and the data value for the configured regions. the stapl file generated will contai n only the data that targets the selected flashrom page. 6. modify properties fo r the serialization. ? for auto inc region, specify the start and max values. ? for read from file region, select the file name of the custom serialization file. 7. select the flashrom programming file type you want to generate from the two options below: ? single programming file for all devices: generates one programming file with all flashrom values. ? one programming file per device: genera tes a separate programming file for each flashrom value.
flashrom in actel?s lo w-power flash devices 5-14 v1.3 8. enter the number of devices you want to program and generate the required programming file. 9. open the programm ing software and load the pr ogramming file. the programming software, flashpro3 and silicon sc ulptor ii, supports the device serialization feature. if, for some reason, the device fails to program a part during serialization, th e software allows you to reuse the serial data or skip the serial data. refer to the flashpro user?s guide for details. conclusion the fusion, igloo, and proasic3 families are the only fp gas that offer on-chi p flashrom support. this document presents informa tion on the flashrom archit ecture, possible applications, programming, access through the jtag and ujtag in terface, and integration into your design. in addition, the libero ide tool set enables easy creation and mo dification of the flashrom content. the nonvolatile flashrom block in the fpga can be customized, enabling multiple applications. additionally, the security offered by the low-p ower flash devices keep s both the contents of flashrom and the fpga design sa fe from system over-builders, sy stem cloners, and ip thieves. related documents handbook documents security in low-pow er flash devices www.actel.com/documents/lpd_security_hbs.pdf ujtag applications in acte l?s low-power flash devices http://www.actel.com/documents/lpd_ujtag_hbs.pdf user?s guides flashpro user?s guide http://www.actel.com/documents/flashpro_ug.pdf
flashrom in actel?s lo w-power flash devices v1.3 5-15 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-007-3 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (june 2008) the "flashrom support in low-power devices" section was revised to include new families and make the information more concise. 5-2 figure 5-2 fusion device ar chitecture overview (afs600) was replaced. figure 5-5 programming flashrom using aes was revised to change "fusion" to "flash device." 5-3 , 5-5 the flashpoint user?s guide was removed from the "user?s guides" section , as its content is now part of the flashpro user?s guide . v1.1 (march 2008) the following changes were made to the family de scriptions in table 5-1 low- power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 5-2 v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. the "igloo terminology" section and "proasic3 terminology" section are new. n/a

v1.4 6-1 6 ? sram and fifo memories in actel's low- power flash devices introduction as design complexity grows, gr eater demands are placed upon an fpga's embedded memory. actel fusion, ? igloo, ? and proasic ? 3 devices provide the flexibility of true dual-port and two-port sram blocks. the embedded memory, along with built-in, dedicated fifo control logic, can be used to create cascading ram blocks and fifos without using additional logic gates. igloo, igloo plus, and proasic3l fpgas contain an additional feature that allows the device to be put in a low-power mode called flash*freeze. in this mode, the core draws minimal power (on the order of 4 to 127 w) and still retains va lues on the embedded sram/fifo and registers. flash*freeze technology allows th e user to switch to active mo de on demand, thus simplifying power management and the use of sram/fifos. device architecture the low-power flash devices feature up to 504 kbits of ram in 4,608-bit blocks ( figure 6-1 on page 6-2 and figure 6-2 on page 6-3 ). the total embedded sram for each device can be found in the datasheets. these memory blocks are arrang ed along the top and bo ttom of the device to allow better access from the core and i/o (in some devices, they are only available on the north side of the device). every ram block has a flexible, hardwired, embedded fifo controller, enabling the user to implement efficient fifo s without sacrificing user gates. in the igloo and proasic3 families of devi ces, the following memories are supported: ? 15 k and 30 k gate devices do not support sram and fifo. ? 60 k and 125 k gate devices support memories on the north side of the device only. ? 250 k devices and larger support memories on the north and south sides of the device. in fusion devices, the foll owing memories are supported: ? afs090 and afs250 support memories on the north side of the device only. ? afs600 and afs1500 support memories on th e north and south si des of the device.
sram and fifo memori es in actel's low-p ower flash devices 6-2 v1.4 notes: 1. aes decryption not supported in 15 k and 30 k gate devices 2. flash*freeze is supported only in igloo, igloo plus, and iglooe and proasic3l devices. figure 6-1 ? igloo and proasic3 device architecture overview isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps 2 ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 1
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-3 figure 6-2 ? fusion device architecture overview (afs600) flash array flash array adc analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad versatile ccc/pll i/os osc ccc isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 4 bank 2 bank 1 bank 3 ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block
sram and fifo memori es in actel's low-p ower flash devices 6-4 v1.4 sram/fifo support in low-power devices the low-power flash families listed in table 6-1 support sram and fifo blocks and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 6-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 6-1 . where the informati on applies to only one fa mily or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 6-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-5 sram and fifo architecture to meet the needs of high-perfo rmance designs, the memo ry blocks operate strictly in synchronous mode for both read and write operations. the r ead and write clocks are completely independent, and each can operate at any desired frequency up to 250 mhz. ? 4k1, 2k2, 1k4, 5129 (dual-port ram?2 read / 2 write or 1 read / 1 write) ? 5129, 25618 (2-port ram?1 read / 1 write) ? sync write, sync pipelined / nonpipelined read automotive proasic3 devices supp ort single-port sram capabilities or dual-port sram only under specific conditions. dual-port mode is supported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the port a clock is the inverse of the port b clock). the actel libero ? integrated design environment (i de) software macro libraries supp ort a dual-port macro only. for use of this macro as a single-port sram, the inputs and clock of one port should be tied off (grounded) to prevent errors du ring design compile. for use in dual-port mode, the same clock with an inversion between the two clock pins of th e macro should be used in the design to prevent errors during compile. the memory block includes dedicated fifo cont rol logic to generate internal addresses and external flag logic (full, empty, afull, aempty). simultaneous dual-port read/write and write/writ e operations at the same address are allowed when certain timing requirements are met. during ram operation, addresses are sourced by the user logic, and the fifo controller is ignored. in fifo mode, the internal addresses are generate d by the fifo controller and routed to the ram array by internal muxes. the low-power flash device architec ture enables the read and write sizes of rams to be organized independently, allowing for bus conversion. for ex ample, the write size can be set to 25618 and the read size to 5129. both the write width and read width for the ram blocks can be specified independently with the ww (write width) and rw (read width) pins. th e different dw configurations are 25618, 5129, 1k4, 2k2, and 4k1. when widths of one, two, or four are select ed, the ninth bit is unused. for example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addres sable for read operations. the ninth bit is not accessible. conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. the ram blocks empl oy little-endian byte or der for read and write operations. memory blocks and macros memory blocks can be configured with many diff erent aspect ratios, but are generically supported in the macro libraries as one of two memory elements: ram4k9 or ram512x18. the ram4k9 is configured as a true dual-port memory block, and the ram512x18 is configured as a two-port memory block. dual-port memory allows the ra m to both read from an d write to either port independently. two-port memory allows the ram to read from one port and write to the other using a common clock or independent read and write clocks. if needed, the ram4k9 blocks can be configured as two-port memory blocks. the memory block can be configured as a fifo by combining the basi c memory block with dedicated fifo controller logic. the fifo macro is named fifo4kx18 ( figure 6-3 on page 6-6 ). clocks for the ram blocks can be driven by the versanet (global resource s) or by regular nets. when using local clock segments, the clock segm ent region that encompasses the ram blocks can drive the rams. in the dual-port configuration (ram4k9), each memory block port can be driven by either rising-edge or falling-edge clocks. each po rt can be driven by clocks with different edges. though only a rising-edge clock can drive the physica l block itself, the actel designer software will automatically bubble-push the inve rsion to properly implement th e falling-edge trigger for the ram block.
sram and fifo memori es in actel's low-p ower flash devices 6-6 v1.4 note: automotive proasic3 devices restrict ram4k9 to a single port or to dual ports with the same clock 180 out of phase (inverted) between clock pins. in singl e-port mode, inputs to port b should be tied to ground to prevent errors during compile. for fifo4k18, the sa me clock 180 out of phase (inverted) between clock pins should be used. figure 6-3 ? supported basic ram macros fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-7 sram features ram4k9 macro ram4k9 is the dual-port configuration of the ram block ( figure 6-4 ). the ram4k9 nomenclature refers to both the deepest possibl e configuration and the widest possible configuration the dual- port ram block can assume, and does not denote a possible memory aspect ratio. the ram block can be configured to the followin g aspect ratios: 4,096x1, 2,048x2, 1,024x4, and 512x9. ram4k9 is fully synchronous and has the following features: ? two ports that allow fully independent r eads and writes at different frequencies ? selectable pipelined or nonpipelined read ? active-low block enables for each port ? toggle control between read and write mode for each port ? active-low asynchronous reset ? pass-through write data or hold existing da ta on output. in pass-through mode, the data written to the write port will imme diately appear on the read port. ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. signal descriptions for ram4k9 note: automotive proasic3 devices support single-port sram capabilities, or dual-port sram only under specific conditions. dual-port mode is s upported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the por t a clock is the inverse of the port b clock). since actel libero ide macro libraries suppo rt a dual-port macro only, certain modifications must be made. these are detailed below. the following signals are used to co nfigure the ram4k9 memory element: widtha and widthb these signals enable the ram to be configured in one of four allowable aspect ratios ( table 6-2 on page 6-8 ). note: when using the sram in single-port mode for automotive proasic3 devices, widthb should be tied to ground. note: for timing diagrams of the ram signals, refer to the appropriate family datasheet. figure 6-4 ? ram4k9 simplified configuration dina douta doutb write data ram4k9 reset write data read data read data dinb addra address address addrb blka blk blk blkb wena wen wen wenb clka clk clk clkb
sram and fifo memori es in actel's low-p ower flash devices 6-8 v1.4 blka and blkb these signals are active-low and will enable the resp ective ports when a sserted. when a blkx signal is deasserted, that port?s outputs hold the previous value. note: when using the sram in single-port mode for automotive proasic3 devices, blkb should be tied to ground. wena and wenb these signals switch the ram between read and write mode s for the respective ports. a low on these signals indicates a write operat ion, and a high indicates a read. note: when using the sram in single-port mode for automotive proasic3 devices, wenb should be tied to ground. clka and clkb these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. note: for automotive proasic3 devices, dual-port mode is supported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the port a clock is the inverse of the port b clock). for use of this macro as a single-port sram, the inputs and clock of one port should be tied off (grounded) to preven t errors during design compile. pipea and pipeb these signals are used to specify pipelined read on the output. a low on pipea or pipeb indicates a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. a high indicates a pipelined read, and data appears on the corresponding output in the next clock cycle. note: when using the sram in single-port mode for automotive proasic3 devices, pipeb should be tied to ground. for use in dual-port mode, the same clock with an inversion between the two clock pins of the macro should be used in the design to prevent errors during compile. wmodea and wmodeb these signals are used to config ure the behavior of the output when the ram is in write mode. a low on these signals makes the output retain data from the previous read. a high indicates pass- through behavior, wherein the data being writte n will appear immediately on the output. this signal is overridden when the ram is being read. note: when using the sram in single-port mode for automotive proasic3 devices, wmodeb should be tied to ground. reset this active-low signal re sets the control logic, fo rces the output hold state registers to zero, disables reads and writes from the sram block, and clears th e data hold registers when asserted. it does not reset the contents of the memory array. while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. addra and addrb these are used as read or write addresses, and th ey are 12 bits wide. when a depth of less than 4 k is specified, the unused high-order bits must be grounded ( table 6-3 on page 6-9 ). table 6-2 ? allowable aspect ratio settings for widtha[1:0] widtha[1:0] widthb[1:0] dw 00 00 4k1 01 01 2k2 10 10 1k4 11 11 5129 note: the aspect ratio settings are consta nt and cannot be changed on the fly.
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-9 note: when using the sram in single-port mode for automotive proasic3 devices, addrb should be tied to ground. dina and dinb these are the input data signals, and they are ni ne bits wide. not all nine bits are valid in all configurations. when a data width less than nine is specified, unused hi gh-order signals must be grounded ( table 6-4 ). note: when using the sram in single-port mode for automotive proasic3 devices, dinb should be tied to ground. douta and doutb these are the nine-bit output data signals. not all nine bits are valid in all configurations. as with dina and dinb, high -order bits may not be used ( table 6-4 ). the output data on unused pins is undefined. ram512x18 macro ram512x18 is the two-port configuration of the same ram block ( figure 6-5 on page 6-10 ). like the ram4k9 nomenclature, the ram512x18 nomenc lature refers to both the deepest possible configuration and the widest possible configuration the two-port ram block can assume. in two- port mode, the ram block can be configured to ei ther the 512x9 aspect ratio or the 256x18 aspect ratio. ram512x18 is also fully synchr onous and has the following features: ? dedicated read and write ports ? active-low read and write enables ? selectable pipelined or nonpipelined read ? active-low asynchronous reset ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. table 6-3 ? address pins unused/used for various supported bus widths dw addrx unused used 4k1 none [11:0] 2k2 [11] [10:0] 1k4 [11:10] [9:0] 5129 [11:9] [8:0] note: the "x" in addrx implies a or b. table 6-4 ? unused/used input and output data pins for various supported bus widths dw dinx/doutx unused used 4k1 [8:1] [0] 2k2 [8:2] [1:0] 1k4 [8:4] [3:0] 5129 none [8:0] note: the "x" in dinx or doutx implies a or b.
sram and fifo memori es in actel's low-p ower flash devices 6-10 v1.4 signal descripti ons for ram512x18 ram512x18 has slightly different behavior from ram4k9, as it has dedicated read and write ports. ww and rw these signals en able the ram to be configured in one of the two allowable aspect ratios ( table 6-5 ). wd and rd these are the input an d output data signals, and they are 18 bits wide. when a 5129 aspect ratio is used for write, wd[17:9] are unused and must be grounded. if this aspect ratio is used for read, rd[17:9] are undefined. waddr and raddr these are read and write addresse s, and they are nine bits wide . when the 25618 aspect ratio is used for write or read, waddr[8] and radd r[8] are unused and must be grounded. wclk and rclk these signals are the write and read clocks, respecti vely. they can be clocked on the rising or falling edge of wclk and rclk. wen and ren these signals are the writ e and read enables, respectively. th ey are both active-low by default. these signals can be configured as active-high. reset this active-low signal re sets the control logic, fo rces the output hold state registers to zero, disables reads and writes from the sram block, and clears th e data hold registers when asserted. it does not reset the contents of the memory array. while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. note: for timing diagrams of the ram signals, refer to the appropriate family datasheet. figure 6-5 ? 512x18 two-port ram block diagram table 6-5 ? aspect ratio settings for ww[1:0] ww[1:0] rw[1:0] dw 01 01 5129 10 10 25618 00, 11 00, 11 reserved wd waddr radd r write data read data read address write address rd wen write enable read enable ren wclk write clk read clk rclk ram512x18 reset
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-11 pipe this signal is used to specify pipelined read on the output. a low on pi pe indicates a nonpipelined read, and the data appears on the output in th e same clock cycle. a high indicates a pipelined read, and data appears on the ou tput in the next clock cycle. sram usage the following descri ptions refer to the usage of both ram4k9 and ram512x18. clocking the dual-port sram blocks are only clocked on the rising edge. smartgen allows falling-edge- triggered clocks by adding inverters to the netlist, hence achieving dual-port sram blocks that are clocked on either edge (rising or falling). for dual-port sram, each port can be clocked on either edge and by separate clocks by port. note that for automotive proasic3, the same clock, with an inversion between the two clock pins of the macro, should be used in design to prevent errors during compile. low-power flash devices support inversion (bubbl e-pushing) throughout the fpga architecture, including the clock input to the sram modules. inversions added to the sram clock pin on the design schematic or in the hdl code will be au tomatically accounted for during design compile without incurring additional delay in the clock path. the two-port sram can be clocked on the rising or falling edge of wclk and rclk. if negative-edge ram and fifo clocking is se lected for memory macros, clock edge inversion management (bubble-pushing) is automatically used within th e development tools, without performance penalty. modes of operation there are two read modes and one write mode: ? read nonpipelined (synchronous?1 clock edge ): in the standard read mode, new data is driven onto the rd bus in the same clock cycle following ra and ren valid. the read address is registered on the read port clock active edge, and data appears at rd after the ram access time. setting pipe to off enables this mode. ? read pipelined (synchronous?2 clock edges): the pipelined mode incurs an additional clock delay from address to data but enables oper ation at a much higher frequency. the read address is registered on the read port active cl ock edge, and the read da ta is registered and appears at rd after the second read clock edge. setting pi pe to on enables this mode. ? write (synchronous?1 clock edge ): on the write clock active ed ge, the write data is written into the sram at the write ad dress when wen is hi gh. the setup times of the write address, write enables, and write data are mini mal with respect to the write clock. ram initialization each sram block can be individually initialized on power-up by means of the jtag port using the ujtag mechanism. the shift register for a target block can be selected a nd loaded with the proper bit configuration to enable seri al loading. the 4,608 bits of da ta can be loaded in a single operation. fifo features the fifo4kx18 macro is created by merging the ram block with dedicated fifo logic ( figure 6-6 on page 6-12 ). since the fifo logic can only be used in conjunction with the memory block, there is no separate fifo controller macro. as with th e ram blocks, the fifo4kx18 nomenclature does not refer to a possible aspect rati o, but rather to th e deepest possible data depth and the widest possible data width. fifo4kx18 can be configured into the following aspect ratios: 4,096x1, 2,048x2, 1,024x4, 512x9, and 256x 18. in addition to being fully synchronous, the fifo4kx18 also has the following features: ? four fifo flags: empty, full, almost-empty, and almost-full ? empty flag is synchronized to the read clock ? full flag is synchronized to the write clock ? both almost-empty and almost-full fl ags have programmable thresholds
sram and fifo memori es in actel's low-p ower flash devices 6-12 v1.4 ? active-low asynchronous reset ? active-low block enable ? active-low write enable ? active-high read enable ? ability to configure the fifo to either stop counting after the empty or full states are reached or to allow the fifo counters to continue ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. the fifos maintain a separate read and write addr ess. whenever the difference between the write address and the read address is greater than or equal to the almost-full value (afval), the almost- full flag is asserted. similarly, the almost-empty flag is asserted whenever the difference between the write address and read address is less th an or equal to the al most-empty value (aeval). figure 6-6 ? fifo4kx18 bl ock diagram figure 6-7 ? ram block with embedded fifo controller wd full empty write data fifo4kx18 reset read data empty flag full flag rd afull almost-full flag almost-empty flag aempty wen write enable write clock read enable ren wclk read clock rclk c nt 12 e = e = c nt 12 afval aeval s ub 12 r c lk wd w c lk reset rblk ren e s top wblk wen f s top rd[17:0] wd[17:0] r c lk w c lk radd[ j :0] wadd[ j :0] ren fren fwen wen full aempty afull empty rd rpipe rw[2:0] ww[2:0] ram
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-13 due to synchronization between the read and write clocks, the empty flag wi ll deassert after the second read clock edge from the po int that the write enable asser ts. however, since the empty flag is synchronized to the read clock, it will assert after the read clock reads the last data in the fifo. also, since the full flag is dependent on the actual hardware configuration, it will assert when the actual physical implementation of the fifo is full. for example, when a user config ures a 12818 fifo, the actual ph ysical implementation will be a 25618 fifo element. since the actu al implementation is 25618, the full flag will not trigger until the 25618 fifo is full, even th ough a 12818 fifo was requested. for this example, the almost- full flag can be used instead of the full flag to signal when the 128th data word is reached. to accommodate different aspect ratios, the almost-full and almo st-empty values are expressed in terms of data bits instead of data words. smartg en translates the user?s input, expressed in data words, into data bits inte rnally. smartgen allows the user to select the threshol ds for the almost- empty and almost-full flags in terms of either the read data words or the write data words, and makes the appropriate conv ersions for each flag. after the empty or full states are reached, the fi fo can be configured so the fifo counters either stop or continue counting. for timing numbers, refer to the appropriate fami ly datasheet. signal descriptions for fifo4k18 the following signals are used to co nfigure the fifo4k18 memory element: ww and rw these signals enable the fifo to be configured in one of the five allowable aspect ratios ( table 6-6 ). wblk and rblk these signals are acti ve-low and will enable th e respective ports when lo w. when the rblk signal is high, that port?s output s hold the previous value. wen and ren read and write enables. wen is active-low and re n is active-high by defa ult. these signals can be configured as active-high or -low. wclk and rclk these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. note: for the automotive proasic3 fifo4k18, for the same clock, 180 out of phase (inverted) between clock pins should be used. rpipe this signal is used to specify pipelined r ead on the output. a lo w on rpipe indicates a nonpipelined read, and the data ap pears on the output in the same clock cycle. a high indicates a pipelined read, and data appears on the output in the next clock cycle. reset this active-low signal resets the control logic and forces the output hold state registers to zero when asserted. it does not reset the contents of the memory array ( table 6-7 on page 6-14 ). table 6-6 ? aspect ratio settings for ww[2:0] ww[2:0] rw[2:0] dw 000 000 4k1 001 001 2k2 010 010 1k4 011 011 5129 100 100 25618 101, 110, 111 101, 110, 111 reserved
sram and fifo memori es in actel's low-p ower flash devices 6-14 v1.4 while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care mu st be taken not to assert it too close to the edges of active read and write clocks. wd this is the input data bus and is 18 bits wide. not all 18 bits are valid in al l configurations. when a data width less than 18 is specified, unus ed higher-order signals must be grounded ( table 6-7 ). rd this is the output data bus and is 18 bits wide. not all 18 bits are va lid in all configurations. like the wd bus, high-order bits become unusable if the data width is less than 18. the output data on unused pins is undefined ( table 6-7 ). estop, fstop estop is used to stop the fifo re ad counter from further counting on ce the fifo is empty (i.e., the empty flag goes high). a high on this signal inhibits the counting. fstop is used to stop th e fifo write counter from further coun ting once the fifo is full (i.e., the full flag goes high). a high on this signal inhibits the counting. for more information on th ese signals, refer to the "estop and fstop usage" section on page 6-15 . full, empty when the fifo is full and no more data can be written, the full flag asse rts high. the full flag is synchronous to wclk to inhibit writing immediately upon detection of a full condition and to prevent overflows. since the write address is co mpared to a resynchron ized (and thus time- delayed) version of the read addr ess, the full flag will remain asserted until two wclk active edges after a read operation el iminates the full condition. when the fifo is empty and no more data can be read, the empty flag asserts high. the empty flag is synchronous to rclk to inhibit reading immediately upon detection of an empty condition and to prevent underflows. since th e read address is compared to a resynchronized (and thus time- delayed) version of the write address, the empt y flag will remain asserted until two rclk active edges after a write operation removes the empty condition. for more information on these signals, refer to the "fifo flag usage cons iderations" section on page 6-15 . afull, aempty these are programmable flags and will be asse rted on the threshold specified by afval and aeval, respectively. when the number of words store d in the fifo reaches the am ount specified by aeval while reading, the aempty output will go high. likewis e, when the number of words stored in the fifo reaches the amount specified by afval while writing, the afull output will go high. afval, aeval the aeval and afval pins are used to specify th e almost-empty and almost -full threshold values. they are 12-bit signals. for more information on thes e signals, refer to the "fifo flag usage considerations" section on page 6-15 . table 6-7 ? input data signal usage fo r different aspect ratios dw wd/rd unused 4k1 wd[17:1], rd[17:1] 2k2 wd[17:2], rd[17:2] 1k4 wd[17:4], rd[17:4] 5129 wd[17:9], rd[17:9] 25618 ?
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-15 fifo usage estop and fstop usage the estop pin is used to stop th e read counter from co unting any further once the fifo is empty (i.e., the empty flag goes high). likewise, the fstop pin is used to stop the wr ite counter from counting any further once the fifo is full (i.e., the full flag goes high). the fifo counters in the device start the co unt at zero, reach the maximum depth for the configuration (e.g., 511 for a 5129 configurat ion), and then restart at zero. an example application for esto p, where the read counter keeps counti ng, would be writing to the fifo once and reading the same content over an d over without doing another write. fifo flag usage considerations the aeval and afval pins are used to specify th e 12-bit aempty and afull threshold values. the fifo contains separate 12-bit write address (waddr) and read address (raddr) counters. waddr is incremented every time a write operation is pe rformed, and raddr is in cremented every time a read operation is performed. whenever the di fference between waddr and raddr is greater than or equal to afval, the afull output is a sserted. likewise, whenever the difference between waddr and raddr is less than or equal to aeva l, the aempty output is asserted. to handle different read and write aspect ratios, afval and aeval are expressed in terms of total data bits instead of total data words. when users specify afval and aeval in terms of read or write words, the smartgen tool translates them into bit addr esses and configures these signals automatically. smartgen configures the afull flag to assert wh en the write address exceeds the read address by at least a predefined value. in a 2k8 fifo, for example, a value of 1,500 for afval means that the afull flag will be asserted after a write when th e difference between the write address and the read address reaches 1,500 (there have been at least 1,500 more writes than reads). it will stay asserted until the difference between the writ e and read addresses drops below 1,500. the aempty flag is asserted when the difference between the write address and the read address is less than a predefined value. in the exampl e above, a value of 200 for aeval means that the aempty flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. it will stay asserted un til that difference rises above 200. note that the fifo can be configured with different read and write widths; in this case, the afval setting is based on the number of write data entries, and th e aeval setting is based on the number of read data entries. for aspect ratios of 5129 and 25618, only 4,096 bits can be addressed by the 12 bits of afval and aeval. the number of words must be multiplied by 8 an d 16 instead of 9 and 18. the smartgen tool automatically uses the proper values. to avoid halfwords being written or read, which could happen if different read and write as pect ratios were specified, the fifo will assert full or empty as soon as at least one word canno t be written or read. for example, if a two-bit word is written and a four-bit word is being read, the fifo will re main in the empty state when the first word is written. this occurs even if the fifo is not completely empty, because in this case, a complete word cannot be read. the sa me is applicable in the full stat e. if a four-bit word is written and a two-bit word is read, the fi fo is full and one word is read . the full flag will remain asserted because a complete word cannot be written at this point. variable aspect ra tio and cascading variable aspect ratio and cascading allow users to configure the memory in the width and depth required. the memory block can be configured as a fifo by combining the basic memory block with dedicated fifo controller logic. the fifo macro is named fifo4kx18. low-power flash device ram can be configured as 1, 2, 4, 9, or 18 bits wide. by cascading the memory blocks, any multiple of those widths can be created. the ram blocks can be from 256 to 4,096 bits deep, depending on the aspect ratio, and the blocks can also be casc aded to create deeper areas. refer to the aspect ratios available for ea ch macro cell in the "sram features" se ction on page 6-7 . the largest continuous configurable memory area is equal to half the total memory available on the device, because the ram is separated into two groups, one on each side of the device. the actel smartgen core generator will automati cally configure and cascade both ram and fifo blocks. cascading is accomplished using dedicated memory logic and does not consume user gates for depths up to 4,096 bits deep and widths up to 18, depending on the configuration. deeper memory will utilize some user gates to multiplex the outputs.
sram and fifo memori es in actel's low-p ower flash devices 6-16 v1.4 generated ram and fifo macros ca n be created as either structural vhdl or verilog for easy instantiation into the design. us ers of actel libero ide can crea te a symbol for the macro and incorporate it into a design schematic. table 6-10 on page 6-17 shows the number of memory blocks required for each of the supported depth and width memory configurations, and for each depth and width combination. for example, a 256-bit deep by 32-bit wide two-port ram woul d consist of two 25618 ram blocks. the first 18 bits would be stored in the first ram block, and the remaining 14 bits would be implemented in the other 25618 ram block. this second ram block would have four bits of unused storage. similarly, a dual-port memory bloc k that is 8,192 bits d eep and 8 bits wide would be implemented using 16 memory blocks. the dual -port memory would be configur ed in a 4,0961 aspect ratio. these blocks would then be casc aded two deep to achi eve 8,192 bits of depth, and eight wide to achieve the eight bits of width. table 6-8 and table 6-9 show the maximum potential widt h and depth configuration for each device. note that 15 k and 30 k gate devices do not support ram or fifo. table 6-8 ? memory availability per igloo and proasic3 devices device ram blocks maximum potential width 1 maximum potential depth 2 igloo/ igloo plus proasic3/ proasic3l depth width depth width agl060 / aglp060 a3p060 4 256 72 (418) 16,384 (4,0964) 1 agl125 aglp125 a3p125 8 256 144 (818) 32,768 (4,0948) 1 agl250 a3p250/l 8 256 144 (818) 32,768 (4,0968) 1 a3p400 12 256 216 (1218) 49,152 (4,09612) 1 agl600 a3p600/l 24 256 432 (2418) 98,304 (4,09624) 1 agl1000 a3p1000/l 32 256 576 (3218) 131,072 (4,09632) 1 agle600 a3pe600 24 256 432 (2418) 98,304 (4,09624) 1 a3pe1500 60 256 1,080 (6018) 245,760 (4,09660) 1 agle3000 a3pe3000/l 112 256 2,016 (11218) 458,752 (4,096112) 1 notes: 1. maximum potential width uses the two-port configuration. 2. maximum potential depth uses the dual-port configuration. table 6-9 ? memory availability per fusion device device ram blocks maximum potential width 1 maximum potential depth 2 depth width depth width afs090 6 256 108 (618) 24,576 (4,0946) 1 afs250 8 256 144 (818) 32,768 (4,0948) 1 afs600 24 256 432 (2418) 98,304 (4,09624) 1 afs1500 60 256 1,080 (6018) 245,760 (4,09660) 1 notes: 1. maximum potential width uses the two-port configuration. 2. maximum potential depth uses the dual-port configuration.
v1.4 6-17 sram and fifo memories in ac tel?s low-power flash devices table 6-10 ? ram and fifo memory block consumption depth 256 512 1,024 2,048 4,096 8,192 16,384 32,768 65,536 two-port dual-port dual-port dual-port dual-port du al-port dual-port dual-port dual-port dual-port width 1 number block 1 1 1 1 1 1 2 4 8 16 1 configuration any any any 1,024 4 2,048 2 4,096 1 2 (4,096 1) cascade deep 4 (4,096 1) cascade deep 8 (4,096 1) cascade deep 16 (4,096 1) cascade deep 2 number block 1 1 1 1 1 2 4 8 16 32 configuration any any any 1,0244 2,048 2 2 (4,096 1) cascaded wide 4 (4,096 1) cascaded 2 deep and 2 wide 8 (4,096 1) cascaded 4 deep and 2 wide 16 (4,096 1) cascaded 8 deep and 2 wide 32 (4,096 1) cascaded 16 deep and 2 wide 4 number block 1 1 1 1 2 4 8 16 32 64 configuration any any any 1,024 4 2 (2,048 2) cascaded wide 4 (4,096 1) cascaded wide 4 (4,096 1) cascaded 2 deep and 4 wide 16 (4,096 1) cascaded 4 deep and 4 wide 32 (4,096 1) cascaded 8 deep and 4 wide 64 (4,096 1) cascaded 16 deep and 4 wide 8 number block 1 1 1 2 4 8 16 32 64 configuration any any any 2 (1,024 4) cascaded wide 4 (2,048 2) cascaded wide 8 (4,096 1) cascaded wide 16 (4,096 1) cascaded 2 deep and 8 wide 32 (4,096 1) cascaded 4 deep and 8 wide 64 (4,096 1) cascaded 8 deep and 8 wide 9 number block 1 1 1 2 4 8 16 32 configuration any any any 2 (512 9) cascaded deep 4 (512 9) cascaded deep 8 (512 9) cascaded deep 16 (512 9) cascaded deep 32 (512 9) cascaded deep 16 number block 1 1 1 4 8 16 32 64 configuration 256 18 256 18 256 18 4 (1,024 4) cascaded wide 8 (2,048 2) cascaded wide 16 (4,096 1) cascaded wide 32 (4,096 1) cascaded 2 deep and 16 wide 32 (4,096 1) cascaded 4 deep and 16 wide 18 number block 1 2 2 4 8 18 32 configuration 256 8 2 (512 9) cascaded wide 2 (512 9) cascaded wide 4 (512 9) cascaded 2 deep and 2 wide 8 (512 9) cascaded 4 deep and 2 wide 16 (512 9) cascaded 8 deep and 2 wide 16 (512 9) cascaded 16 deep and 2 wide 32 number block 2 4 4 8 16 32 64 configuration 2 (256 18) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded wide 8 (1,024 4) cascaded wide 16 (2,048 2) cascaded wide 32 (4,096 1) cascaded wide 64 (4,096 1) cascaded 2 deep and 32 wide 36 number block 2 4 4 8 16 32 configuration 2 (256 18) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded 2 deep and 4 wide 16 (512 9) cascaded 4 deep and 4 wide 16 (512 9) cascaded 8 deep and 4 wide 64 number block 4 8 8 16 32 64 configuration 4 (256 18) cascaded wide 8 (512 9) cascaded wide 8 (512 9) cascaded wide 16 (1,024 4) cascaded wide 32 (2,048 2) cascaded wide 64 (4,096 1) cascaded wide 72 number block 4 8 8 16 32 configuration 4 (256 18) cascaded wide 8 (512 9) cascaded wide 8 (512 9) cascaded wide 16 (512 9) cascaded wide 16 (512 9) cascaded 4 deep and 8 wide note: memory configurations represented by grayed cells are not supported.
sram and fifo memori es in actel's low-p ower flash devices 6-18 v1.4 initializing the ram/fifo the sram blocks can be initialized with data to us e as a lookup table (lut). data initialization can be accomplished either by loading the data th rough the design logic or through the ujtag interface. the ujtag macro is used to allow access from the jtag port to the internal logic in the device. by sending the appropriate initializati on string to the jtag test access port (tap) controller, the designer can put th e jtag circuitry into a mode that allows the user to shift data into the array logic through the jtag port using the ujtag macro. for a mo re detailed explanation of the ujtag macro, refer to ujtag applications in acte l?s low-power flash devices . a user interface is required to receive the user command, initiali zation data, and clock from the ujtag macro. the interface must synchronize and lo ad the data into the correct ram block of the design. the main outputs of the user interface block are the following: ? memory block chip select: selec ts a memory block for initializa tion. the chip selects signals for each memory bloc k that can be generated from different user-defined pockets or simple logic, such as a ring counter (see below). ? memory block write address: identifies the ad dress of the memory cell that needs to be initialized. ? memory block write data: the interface block re ceives the data serially from the utdi port of the ujtag macro and loads it in parallel in to the write data ports of the memory blocks. ? memory block write clock: drives the wclk of the memory block and synchronizes the write data, write address, and chip select signals. figure 6-8 shows the user interface between ujtag and the memory blocks. an important component of the interface between the ujt ag macro and the ram blocks is a serial-in/parallel-out shift register. the width of the shift register should equal the data width of the ram blocks. the ram data arrives serially fro m the utdi output of the ujtag macro. the data must be shifted into a shift regi ster clocked by the jtag clock (provided at the udrck output of the ujtag macro). then, after the shift register is fu lly loaded, the data must be tran sferred to the write data port of the ram block. to synchronize the loading of th e write data with the write address and write clock, the output of the shift register can be pipelined before driving the ram block. the write address can be generated in different ways. it can be imported through the tap using a different instruction opcode and another shift re gister, or generated internally using a simple figure 6-8 ? interfacing tap ports and sram blocks trst ujtag tdo tdi tms tck trst tdo tdi tms tck urstb udrupd udrsh udrcap udrck utdi utdo uireg[7:0] ir[7:0] user interface wdata waddr wclk wen1 wen2 wen3 reset dr_update dr_shift dr_capture dr_clk din dout wd waddr wclk wen ram1 wd waddr wclk wen ram2 wd waddr wclk wen ram3
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-19 counter. using a counter to gene rate the address bits and sweep through the address range of the ram blocks is recommended, since it reduces the complexity of the user interface block and the board-level jtag driver. moreover, using an intern al counter for address ge neration speeds up the initialization procedure, since the user only needs to import the data through the jtag port. the designer may use different me thods to select among the multiple ram blocks. using counters along with demultiplexers is one approach to set the write enable signals. basicall y, the number of ram blocks needing initialization determines the mo st efficient approach. for example, if all the blocks are initialized with the same data, one enable signal is enough to activate the write procedure for all of them at the same time. an other alternative is to use different opcodes to initialize each memory block. for a small number of ram blocks, using counters is an optimal choice. for example, a ring counter can be used to select from multiple ram blocks. the clock driver of this counter needs to be con trolled by the address generation process. once the addressing of one block is finished, a clock pulse is sent to the (ring) counter to select the next memory block. figure 6-9 illustrates a simple block diagram of an interface block between ujtag and ram blocks. in the circuit shown in figure 6-9 , the shift register is enabled by the udrsh output of the ujtag macro. the counters and chip sele ct outputs are contro lled by the value of the tap instruction register. the comparison block compares the uire g value with the "start initialization" opcode value (defined by the user). if the result is true, the counters start to generate addresses and activate the wen inputs of appropriate ram blocks. the udrupd output of the ujtag macro, also shown in figure 6-9 , is used for generating the write clock (wclk) and synchronizing the data register and address counter with wclk. udrupd is high when the tap controller is in th e data register update state, which is an indication of completing the loading of one data word. once the tap controller goes into the data register update state, the udrupd output of the ujtag macro goes hi gh. therefore, the pipe line register and the address counter place the proper data and ad dress on the outputs of the interface block. meanwhile, wclk is defined as th e inverted udrupd. this will prov ide enough time (equal to the udrupd high time) for the data and address to be placed at the proper ports of the ram block before the rising ed ge of wclk. the inverter is not required if the ram blocks are clocked at the falling edge of the write clock. an example of this is described in the "example of ram initialization" section on page 6-20 . figure 6-9 ? block diagram of a sample user interface n n m m utdi udrsh udrck utdo udrupdi uireg urstb clk enable sin serial-to-port shift register pout sout d en reset clk en reset clk q q clk wdata wclk wen1 wen2 weni waddr chip select data reg. addr counter ring counter binary counter compare with defined opcode in result
sram and fifo memori es in actel's low-p ower flash devices 6-20 v1.4 example of ram initialization this section of the document presents a sample design in which a 44 ram block is being initialized through the jtag port. a test feature ha s been implemented in the design to read back the contents of the ram after init ialization to verify the procedure. the interface block of th is example performs two major functions: initialization of the ram block and running a test procedure to read back the cont ents. the clock output of the interface is either the write clock (for initialization) or the read cl ock (for reading back the contents). the verilog code for the interface bl ock is included in the "sample verilog code" section on page 6-21 . for simulation purposes, users can declare the input ports of the ujtag macro for easier assignment in the testbench. however, the ujtag input ports should not be declared on the top level during synthesis. if the input ports of the uj tag are declared during synthesis, the synthesis tool will instantiate input buffer s on these ports. the input buffers on the ports will cause compile to fail in designer. figure 6-10 shows the simulation resu lts for the initiali zation step of the example design. the clk_out signal, which is the clock output of the interface bl ock, is the inverted dr_update output of the ujtag macro. it is clear that it give s sufficient time (while the tap controller is in the data register update state) for the write address and data to become stab le before loading them into the ram block. figure 6-11 presents the test procedure of the example. the data read back from the memory block matches the written data, thus ve rifying the design functionality. figure 6-10 ? simulation of initialization step figure 6-11 ? simulation of the test procedure of the example
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-21 the rom emulation application is based on ram bloc k initialization. if the user's main design has access only to the read ports of the ram bloc k (raddr, rd, rclk, and ren), and the contents of the ram are already initialized through the tap, then the memory bloc ks will emulate rom functionality for the core design. in this case, the write ports of the ram blocks are accessed only by the user interface block, and the interface is activated only by the tap instruction register contents. users should note that the contents of the ram blocks are lost in the absence of applied power. however, the 1 kbit of flash memory, flashrom, in low-power flash devices can be used to retain data after power is removed from the device. refer to flashrom in actel?s lo w-power flash devices for more information. sample verilog code interface block `define initialize_start 8'h22 //initialization start command value `define initialize_stop 8'h23 //initialization start command value module interface(ir, rst_n, data_shift, clk_in, data_update, din_ser, dout_ser, test, test_out,test_clk,clk_out,wr_en,rd_en,write_word,read_word,rd_addr, wr_addr); input [7:0] ir; input [3:0] read_word; //ram data read back input rst_n, data_shift, clk_in, data_update, din_ser; //initialization signals input test, test_clk; //test procedure clock and command input output [3:0] test_out; //read data output [3:0] write_word; //write data output [1:0] rd_addr; //read address output [1:0] wr_addr; //write address output dout_ser; //tdo driver output clk_out, wr_en, rd_en; wire [3:0] write_word; wire [1:0] rd_addr; wire [1:0] wr_addr; wire [3:0] q_out; wire enable, test_active; reg clk_out; //select clock for initialization or readback test always @(enable or test_clk or data_update) begin case ({test_active}) 1 : clk_out = test_clk ; 0 : clk_out = !data_update; default : clk_out = 1'b1; endcase end assign test_active = test && (ir == 8'h23); assign enable = (ir == 8'h22); assign wr_en = !enable; assign rd_en = !test_active; assign test_out = read_word; assign dout_ser = q_out[3]; //4-bit sin/pout shift register shift_reg data_shift_reg (.shiften(data_shift), .shiftin(din_ser), .clock(clk_in), .q(q_out)); //4-bit pipeline register d_pipeline pipeline_reg (.data(q_out), .clock(data_update), .q(write_word));
sram and fifo memori es in actel's low-p ower flash devices 6-22 v1.4 // addr_counter counter_1 (.clock(data_update), .q(wr_addr), .aset(rst_n), .enable(enable)); addr_counter counter_2 (.clock(test_clk), .q(rd_addr), .aset(rst_n), .enable( test_active)); endmodule interface block / ujtag wrapper this example is a sample wrap per, which connects the interface block to the ujtag and the memory blocks. // wrapper module top_init (tdi, trstb, tms, tck, tdo, test, test_clk, test_ out); input tdi, trstb, tms, tck; output tdo; input test, test_clk; output [3:0] test_out; wire [7:0] ir; wire reset, dr_shift, dr_cap, init_clk, dr_update, data_in, data_out; wire clk_out, wen, ren; wire [3:0] word_in, word_out; wire [1:0] write_addr, read_addr; ujtag ujtag_u1 (.uireg0(ir[0]), .uireg1(ir[1]), .uireg2(ir[2]), .uireg3(ir[3]), .uireg4(ir[4]), .uireg5(ir[5]), .uireg6(ir[6]), .uireg7(ir[7]), .urstb(reset), .udrsh(dr_shift), .udrcap(dr_cap), .udrck(init_clk), .udrupd(dr_update), .ut-di(data_in), .tdi(tdi), .tms(tms), .tck(tck), .trstb(trstb), .tdo(tdo), .ut-do(data_out)); mem_block ram_block (.do(word_out), .rclock(clk_out), .wclock(clk_out), .di(word_in), .wrb(wen), .rdb(ren), .wad-dr(write_addr), .raddr(read_addr)); interface init_block (.ir(ir), .rst_n(reset), .data_shift(dr_shift), .clk_in(init_clk), .data_update(dr_update), .din_ser(data_in), .dout_ser(data_out), .test(test), .test_out(test_out), .test_clk(test_clk), .clk_out(clk_out), .wr_en(wen), .rd_en(ren), .write_word(word_in), .read_word(word_out), .rd_addr(read_addr), .wr_addr(write_addr)); endmodule address counter module addr_counter (clock, q, aset, enable); input clock; output [1:0] q; input aset; input enable; reg [1:0] qaux; always @(posedge clock or negedge aset) begin if (!aset) qaux <= 2'b11; else if (enable) qaux <= qaux + 1; end assign q = qaux; endmodule
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-23 pipeline register module d_pipeline (data, clock, q); input [3:0] data; input clock; output [3:0] q; reg [3:0] q; always @ (posedge clock) q <= data; endmodule 4x4 ram block (created by sm artgen core generator) module mem_block(di,do,waddr,raddr,wrb,rdb,wclock,rclock); input [3:0] di; output [3:0] do; input [1:0] waddr, raddr; input wrb, rdb, wclock, rclock; wire webp, weap, vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); inv webubbleb(.a(wrb), .y(webp)); ram4k9 ramblock0(.addra11(gnd), .addra10(gnd), .addra9(gnd), .addra8(gnd), .addra7(gnd), .addra6(gnd), .addra5(gnd), .addra4(gnd), .addra3(gnd), .addra2(gnd), .addra1(raddr[1]), .addra0(raddr[0]), .addrb11(gnd), .addrb10(gnd), .addrb9(gnd), .addrb8(gnd), .addrb7(gnd), .addrb6(gnd), .addrb5(gnd), .addrb4(gnd), .addrb3(gnd), .addrb2(gnd), .addrb1(waddr[1]), .addrb0(waddr[0]), .dina8(gnd), .dina7(gnd), .dina6(gnd), .dina5(gnd), .dina4(gnd), .dina3(gnd), .dina2(gnd), .dina1(gnd), .dina0(gnd), .dinb8(gnd), .dinb7(gnd), .dinb6(gnd), .dinb5(gnd), .dinb4(gnd), .dinb3(di[3]), .dinb2(di[2]), .dinb1(di[1]), .dinb0(di[0]), .widtha0(gnd), .widtha1(vcc), .widthb0(gnd), .widthb1(vcc), .pipea(gnd), .pipeb(gnd), .wmodea(gnd), .wmodeb(gnd), .blka(weap), .blkb(webp), .wena(vcc), .wenb(gnd), .clka(rclock), .clkb(wclock), .reset(vcc), .douta8(), .douta7(), .douta6(), .douta5(), .douta4(), .douta3(do[3]), .douta2(do[2]), .douta1(do[1]), .douta0(do[0]), .doutb8(), .doutb7(), .doutb6(), .doutb5(), .doutb4(), .doutb3(), .doutb2(), .doutb1(), .doutb0()); inv webubblea(.a(rdb), .y(weap)); endmodule
sram and fifo memori es in actel's low-p ower flash devices 6-24 v1.4 software support the smartgen core generator is the easiest wa y to select and config ure the memory blocks ( figure 6-12 ). smartgen automatically selects the proper memory block type an d aspect ratio, and cascades the memory blocks based on the user's se lection. smartgen also configures any additional signals that may require tie-off. smartgen will attempt to use the minimum number of blocks required to implement the desired memory. when cascading, smartgen will configure the memory fo r width before configuring for depth. for example, if the user requests a 2568 fifo, smartgen will use a 5129 fifo configuration, not 25618. figure 6-12 ? smartgen core generator interface
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-25 smartgen enables the user to co nfigure the desired ram element to use either a single clock for read and write, or two independent clocks for read and write. the user can select the type of ram as well as the width/depth and several other parameters ( figure 6-13 ). smartgen also has a port mapping option that allows the user to specify the names of the ports generated in the memory block ( figure 6-14 ). figure 6-13 ? smartgen memory configuration interface figure 6-14 ? port mapping interface for smartgen-generated memory
sram and fifo memori es in actel's low-p ower flash devices 6-26 v1.4 smartgen also configures the fifo according to user specifications. users can select no flags, static flags, or dynamic flags. static flag settings are configured using configuration flash and cannot be altered without reprogramming th e device. dynamic flag settings are determined by register values and can be altered without reprogramming the device by reloading the register values either from the design or through the ujtag inte rface described in the "initializing the ram/fifo" section on page 6-18 . smartgen can also configure the fifo to contin ue counting after the fifo is full. in this configuration, the fifo write coun ter will wrap after the counter is full and continue to write data. with the fifo configured to continue to read a fter the fifo is empty, the read counter will also wrap and re-read data that was previously read. this mode can be used to continually read back repeating data patterns stored in the fifo ( figure 6-15 ). fifos configured using smartgen can also make use of the port mapping feature to configure the names of the ports. limitations users should be aware of the following limitatio ns when configuring sram blocks for low-power flash devices: ? smartgen does not track the target device in a family, so it cannot determine if a configured memory block will fit in the target device. ? dual-port rams with different read an d write aspect ratios are not supported. ? cascaded memory blocks can only use a maximum of 64 blocks of ram. ? the full flag of the fifo is sensitive to the maximum depth of the actual physic al fifo block, not the depth requested in the smartgen interface. figure 6-15 ? smartgen fifo configuration interface
sram and fifo memories in ac tel?s low-power flash devices v1.4 6-27 conclusion fusion, igloo, and proasic3 devices provide user s with extremely flexible sram blocks for most design needs, wi th the ability to choose between an ea sy-to-use dual-port memory or a wide-word two-port memory. used with the bu ilt-in fifo controllers, these memory blocks also serve as highly efficient fifos that do not consume user gates when impl emented. the actel smartgen core generator provides a fast and easy way to conf igure these memory elem ents for use in designs. related documents handbook documents ujtag applications in acte l?s low-power flash devices www.actel.com/document s/lpd_ujtag_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-008-4 revised october 2008
sram and fifo memori es in actel's low-p ower flash devices 6-28 v1.4 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.4) page v1.3 (august 2008) the "sram/fifo support in lo w-power device s" section was revised to include new families and make the information more concise. 6-4 the "sram and fifo architecture" section was modified to remove "igloo and proasic3e" from the de scription of what the me mory block includes, as this statement applies to all memory blocks. 6-5 the "clocking" section was revised to change "i gloo and proasic3 devices support inversion ..." to "low-power flash devices support inversion ..."the reference to igloo and proasic3 deve lopment tools in the last paragraph of the section was changed to refer to development tools in general. 6-11 the "estop and fstop usage" section was updated to refe r to fifo counters in devices in general rather than only igloo and proasic3e devices. 6-15 v1.2 (june 2008) the note was removed from figure 6-7 ram block with embedded fifo controller and placed in the wclk and rclk description. 6-12 the "wclk and rclk" description was revised. 6-13 v1.1 (march 2008) the following changes were made to the family descriptions in table 6-1 low-power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 6-4 v1.0 (january 2008) the "introduction" section was updated to include the igloo plus family. 6-1 the "device architecture" section was updated to state that 15 k gate devices do not supp ort sram and fifo. 6-1 the first note in figure 6-1 igloo and proasi c3 device architecture overview was updated to include mention of 15 k gate devices, and igloo plus was added to the second note. 6-3 the table 6-1 low-power flash families table and associated text were updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 6-4 the text introducing table 6-8 memory availability per igloo and proasic3 devices was updated to replace "a3p030 and agl030" with "15 k and 30 k gate devices. table 6-8 memory availability per igloo and proasic3 devices was updated to remove agl400 and agle1500 and include igloo plus and proasic3l devices. 6-16
i/o descriptions and usage

v1.2 7-1 7 ? i/o structures in igloo plus devices introduction low-power flash devices feature a flexible i/o structure, supporting a range of mixed voltages (1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v) through bank-selectable voltages. the igloo ? plus family supports igloo plus i/os. users designing i/o solutions are faced with a number of implementation decisions and configuration choices that can dire ctly impact the efficiency and effectiveness of their final design. the flexible i/o structure, supporting a wide variety of voltages and i/o standards, enables users to meet the growing challenges of their ma ny diverse applications. the actel libero ? integrated design environment (ide) provides an easy way to implement i/o that will result in robust i/o design. this document describes igloo plus i/o types in terms of the suppo rted standards. it then explains the individual features and how to im plement them in actel's libero ide. figure 7-1 ? igloo plus i/o block logical representation 2 output re g ister 1 input re g ister 3 output re g ister i/o / d0 i/o / oe i/o / c lr i/o / c lk i/o / q0 c lr c lr c lr s c an y pad sc an sc an
i/o structures in igloo plus devices 7-2 v1.2 low-power flash device i/o support the low-power flash families listed in table 7-1 support i/os and the fu nctions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 7-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 7-1 ? low-power flash families product line family * description igloo igloo plus igloo fpgas with enhanced i/o capabilities note: *the family name links to the appropriate data sheet, including product brief, dc and switching characteristics, and packaging information.
i/o structures in igloo plus devices v1.2 7-3 igloo plus i/os table 7-2 and table 7-3 show the voltages and compatible i/o standards for igloo plus family. i/os provide programmable slew rates, drive strengths, and weak pull-up and pull-down circuits. selectable schmitt trigger and 5 v tole rant receivers are offered. see the "5 v input tolerance" section on page 7-11 for possible implementa tions of 5 v tolerance. all i/os are in a known state during power-up, and any power-up sequence is allowed without current impact. refer to the "i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial)" sect ion in the datasheet for more information. during power-up, before reaching activation levels, the i/o inpu t and output buffers are disabled while the weak pull-up is enabled. activation leve ls are described in the datasheet. i/o banks and i/o standards compatibility i/os are grouped into i/o voltage banks. a ll igloo plus devices have four i/o banks. each i/o voltage bank has dedicated i/o supply and ground voltages. this is olation is necessary to minimize simultaneous switchin g noise from the input and output (ssi and sso). the switching noise (ground bounce and power bounce) is generated by the output buffers and transferred into input buffer circuits, and vice versa. because of these dedicated supplies, only i/os with compatible standards can be assigned to the same i/o voltage bank. table 7-3 shows the required voltage compatibility values for each of these voltages. i/o standards are compatible if their v cci values are identical. for mo re information about i/o and global assignments to i/o banks in a device, refer to the specific pin table for the device in the packaging section of the datasheet and the "user i/o naming convention" section on page 7-18 . table 7-2 ? supported i/o standards igloo plus aglp030 aglp060 aglp125 single-ended lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v / 1.2 v ??? table 7-3 ? v cci voltages and compatible igloo plus standards v cci (typical) compatible standards 3.3 v lvttl/lvcmos 3.3 2.5 v lvcmos 2.5 1.8 v lvcmos 1.8 1.5 v lvcmos 1.5 1.2 v lvcmos 1.2
i/o structures in igloo plus devices 7-4 v1.2 features supported on every i/o table 7-4 lists all features supported by trans mitter/receiver for single-ended i/os. table 7-5 lists the performance of each io technology. table 7-4 ? i/o features feature description all i/o ? high performance ( table 7-5 ) ? electrostatic discharge (esd) protection ? i/o register combining option single-ended transmitter features ? hot-swap ? i/os can be configured to behave in flash*freeze mode as tristate, high, low, or to hold the previous state. ? programmable output sl ew rate: high and low ? optional weak pull-up and pull-down resistors ? output drive: 3 drive str engths (except for lvcmos 1.2 v) ? lvttl/lvcmos 3.3 v output s compatible with 5 v ttl inputs single-ended receiver features ? selectable schmitt trigger ? 5 v?input?tolerant receiver ( table 7-11 on page 7-11 ) ? separate ground plane fo r gndq pin and power plane for v cci pin are used for input buffer to reduce output- induced noise. table 7-5 ? maximum i/o frequency specification maximum performance igloo plus v2 or v5 devices, 1.5 v dc core supply voltage igloo plus v2, 1.2 v dc core supply voltage lvttl/lvcmos 3.3 v 180 mhz tbd lvcmos 2.5 v 230 mhz tbd lvcmos 1.8 v 180 mhz tbd lvcmos 1.5 v 120 mhz tbd lvcmos 1.2 v n/a tbd
i/o structures in igloo plus devices v1.2 7-5 i/o architecture i/o tile the i/o tile provides a flexible, programmable s tructure for implementing a large number of i/o standards. in addition, the regi sters available in the i/o tile can be used to support high- performance register inputs and outputs, with register enable if desired ( figure 7-1 on page 7-1 ). as depicted in figure 7-1 on page 7-1 , all i/o registers share one clr port. i/o bank structure low-power flash device i/os are divided into multiple technology banks. the igloo plus devices have four banks. each bank has its own v cci power supply pin. refer to figure 7-2 for more information. notes: 1. all nmos transistors connected to th e i/o pad serve as esd protection. 2. see table 7-2 on page 7-3 for available i/o standards. 3. 5 v tolerance requires external resistor. figure 7-2 ? simplified i/o buffer circuitry input buffer standard 2 and schmitt trigger control input signal to core logic input buffer oe (from core logic) output signal (from core logic) output buffer logic drive strength and output slew rate control clamp diode esd protection 1 weak pull- down control (from core) clamp diode esd protection 1 v cci i/o pad weak pull-up control (from core) hot-swap, 5 v tolerance, and clamp diode control output buffer v cci 3
i/o structures in igloo plus devices 7-6 v1.2 i/o registers each i/o module contains several inpu t and output regi sters. refer to figure 7-2 on page 7-5 for a simplified representation of the i/o block. the number of input re gisters is selected by a set of switches (not shown in figure 7-1 on page 7-1 ) between registers to im plement single-ended data transmission to and from the fpga core. the designer software sets these switches for the user. a common clr/pre signal is employed by all i/o registers when i /o register combining is used. the i/o register combining requires that no combinatorial logic be presen t between the register and the i/o. i/o standards single-ended standards these i/o standards use a push-pull cmos output sta ge with a voltage referenced to system ground to designate logical states. the input buffer conf iguration, output drive, and i/o supply voltage (v cci ) vary among the i/o standards ( figure 7-3 ). the advantage of these standards is that a comm on ground can be used for multiple i/os. this simplifies board layout and reduces system cost. their low-edge-rate ( dv / dt ) data transmission causes less electromagnetic interference (emi) on th e board. however, they are not suitable for high-frequency (>200 mhz) switching due to noise impact and higher power consumption. lvttl (low-voltage ttl) this is a general-purpose standard (eia/jesd8-b) for 3.3 v applications . it uses an lvttl input buffer and a push-pull output buffer. the lvttl output bu ffer can have up to six different programmable drive strengths. refer to "i/o programmable features" on page 7-7 for details. refer to table 7-13 on page 7-16 for details. lvcmos (low-voltage cmos) the low-power flash devices provid e five voltage levels for lvcmos: lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 1.8 v, lvcmos 1.5 v, and lvcmos 1.2 v. lvcmos 3.3 v is an extension of the lvcmos standard (jesd8-b?compliant) used for general-purpose 3.3 v applications. lvcmos 2.5 v is an extension of the lvcmos standard (jesd8-5?compliant) used for general-purpose 2.5 v applications. lvcmos 1.8 v is an extension of the lvcmos standard (jesd8-7?comp liant) used for general- purpose 1.8 v applications. lvcmos 1.5 v is an extension of the lvcmos standard (jesd8-11? compliant) used for gene ral-purpose 1.5 v applications. lvcm os 1.2v is an extension of the lvcmos standard (jesd8-12a-compliant) used for general-purpose 1.2 v applications. the v cci values for these standards are 3.3 v, 2.5 v, 1.8 v, 1.5 v, and 1.2 v, respective ly. all these versions use a 3.3 v?tolerant cmos input buffer and a push-pull output buffer . like lvttl, the output buffer has up to six different programmable drive stre ngths (2, 4, 6, 8, 12, and 16 ma). refer to "igloo plus output drive and slew" on page 7-16 for details. figure 7-3 ? single-ended i/o standard topology out gnd in gnd device 1 device 2 v cci v cci
i/o structures in igloo plus devices v1.2 7-7 i/o features igloo plus devices support multip le i/o features that make boar d design easier. for example, an i/o feature like schmitt trigger in the input buffer saves the board space that would be used by an external schmitt trigger for a slow or noisy input signal. thes e features are also programmable for each i/o, which in turn gives flexibility in inte rfacing with other components. the following is a detailed description of all availabl e features in igloo plus devices. i/o programmable features low-power flash devices offer many flexible i/o features to support a wide variety of board designs. some of the features are prog rammable, with a range for selection. table 7-6 lists programmable i/o features and their ranges. hot-swap support all devices in the igloo plus family are hot-swappable. the hot-swap feature appears as a read-only check box in the i/ o attribute editor that shows whether an i/o is hot-swappable or not. refer to power-up/-down behavior of low-power flash devices for details on hot-swapping. hot-swapping is the operation of hot insertion or hot removal of a card in a powered-up system. the levels of hot-swap support and examples of related applications are described in table 7-7 on page 7-8 to table 7-10 on page 7-9 . the i/os also need to be configured in hot-insertion mode if hot-plugging compliance is required. igloo plus devices have an i/o stru cture that allows the support of level 3 and level 4 hot-swap with only two levels of staging. table 7-6 ? programmable i/o features (user c ontrol via i/o attribute editor) feature description range slew control output slew rate high, low output drive (ma) output drive strength depends on i/o type resistor pull weak resistor pull circuit up, down, none schmitt trigger schmitt trigger for input only on, off
i/o structures in igloo plus devices 7-8 v1.2 table 7-7 ? hot-swap level 1 description cold-swap power applied to device no bus state ? card ground connection ? device circuitry connected to bus pins ? example application system and card with actel fpga chip are powered down, and the card is plugged into the system. then the po wer supplies are turned on for the system but not for the fpga on the card. compliance of igloo plus devices compliant table 7-8 ? hot-swap level 2 description hot-swap while reset power applied to device yes bus state held in reset state card ground connection reset must be maintained for 1 ms before, during, and after insertion/removal. device circuitry connected to bus pins ? example application in the pci hot-plug specification, reset control circuitry isolates the ca rd busses until the card supplies are at their nominal operating levels and stable. compliance of igloo plus devices compliant
i/o structures in igloo plus devices v1.2 7-9 for level 3 and level 4 co mpliance with the igloo plus devices, cards with two levels of staging should have the fo llowing sequence: ? grounds ? powers, i/os, and other pins table 7-9 ? hot-swap level 3 description hot-swap wh ile bus idle power applied to device yes bus state held idle (no ongoing i/o processes during insertion/removal) card ground connection reset must be maintained for 1 ms before, during, and after insertion/removal. device circuitry connected to bus pins must remain glitch-fre e during power-up or power-down example application board bus shared with ca rd bus is "frozen," and there is no toggling activity on the bus. it is critical that the logic sta tes set on the bus signal not be disturbed during card insertion/removal. compliance of igloo plus devices compliant table 7-10 ? hot-swap level 4 description hot-swap on an active bus power applied to device yes bus state bus may have active i/o processes ongoing, but device being inserted or removed must be idle. card ground connection reset must be maintained for 1 ms before, during, and after insertion/removal. device circuitry connected to bus pins must remain glitch-fre e during power-up or power-down example application there is activity on th e system bus, and it is critical that the logic sta tes set on the bus signal not be disturbed during card insertion/removal. compliance of igloo plus devices compliant
i/o structures in igloo plus devices 7-10 v1.2 cold-sparing support cold-sparing refers to the ability of a device to leav e system data undisturb ed when the system is powered up, while the component itself is powere d down, or when power supplies are floating. cold-sparing is supported on igloo plus devices only when the user provides resistors from each power supply to ground. the resi stor value is calculated based on the decoupling capacitance on a given power supply. the rc constant should be greater than 3 s. to remove resistor current during operation, it is suggested that the resistor be disconnected (e.g., with an nmos switch) from the po wer supply after the supply has reached its final value. refer to the power-up/-down behavior of low-power flash devices chapter of the proasic3 and proasic3e handbooks for details on cold-sparing. cold-sparing means that a subsyste m with no power applied (usually a circuit board) is electrically connected to the system that is in operation. th is means that all input buffers of the subsystem must present very high input impedance with no po wer applied so as not to disturb the operating portion of the system. when targeting low-power applications, i/o cold-sparing may add additional current if a pin is configured with either a pull-up or pull-down resi stor and driven in the oppo site direction. a small static current is induced on each i/o pin when the pin is driven to a voltage opposite to the weak pull resistor. the current is eq ual to the voltage drop across the input pin divided by the pull resistor. refer to the "detailed i/o dc characterist ics" section of the appr opriate family datasheet for the specific pull resistor valu e for the corresponding i/o standard. for example, assuming an lvttl 3.3 v input pin is configured with a weak pull-up resistor, a current will flow through the pull-up resistor if the input pin is driven low. for lvttl 3.3 v, the pull-up resistor is ~45 k , and the resulting current is equal to 3.3 v / 45 k = 73 a when the io pin is driven low. this is true also when a weak pull-down is chosen and the input pin is driven high. this current can be avoided by driving the input low when a weak pull-down resistor is used and driving it high when a weak pull-up resistor is used. this current draw can occur in the following cases: ? in active and static modes: ? input buffers with pull-up, driven low ? input buffers with pull-down, driven high ? bidirectional buffers with pull-up, driven low ? bidirectional buffers with pull-down, driven high ? output buffers with pull-up, driven low ? output buffers with pull-down, driven high ? tristate buffers with pull-up, driven low ? tristate buffers with pull-down, driven high ? in flash*freeze mode: ? input buffers with pull-up, driven low ? input buffers with pull-down, driven high ? bidirectional buffers with pull-up, driven low ? bidirectional buffers with pull-down, driven high
i/o structures in igloo plus devices v1.2 7-11 electrostatic discharge protection low-power flash devices are tested per jedec standard jesd22-a114-b. these devices contain clamp diodes at every i/o, global, and power pad. clamp diodes protect all device pads against damage from esd as we ll as from excessive voltage transients. all igloo plus devices are qualified to the human body model (hbm) and the charged device model (cdm). 5 v input and output tolerance igloo plus devices can be made 5 v?input?tolerant for certain i/o standards by using external level shifting techniques. 5 v ou tput compliance can be achieved using certain i/o standards. table 7-4 on page 7-4 shows the i/o standards that support 5 v input tolerance. only 3.3 v lvttl/lvcmos standards support 5 v output tolerance. 5 v input tolerance i/os can support 5 v input tolera nce when lvttl 3.3 v, lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 1.8 v, lvcmos 1.5 v, and lvcmos 1.2 v configurations are used (see table 7-11 ). there are three recommended solutions for achievin g 5 v receiver tolerance (see figure 7-4 on page 7-12 to figure 7-6 on page 7-13 for details of board an d macro setups). all the solutions me et a common requirement of limiting th e voltage at the input to 3.6 v or le ss. in fact, the i/o absolute maximum voltage rating is 3.6 v, and any voltage above 3.6 v may cause long-term gate oxide failures. solution 1 the board-level design mu st ensure that the reflected waveform at the pad does not exceed the limits provided in th e recommended operating conditions in the datasheet. this is a requirement to ensure long-term reliability. this solution requires two board resistors, as demonstrated in figure 7-4 on page 7-12 . here are some examples of possible resistor values (based on a simplified simula tion model with no line effects and 10 transmitter output resist ance, where rtx_out_high = (v cci ?v oh )/i oh and rtx_out_low = v ol /i ol ). example 1 (high spee d, high current): rtx_out_high = rtx_out_low = 10 r1 = 36 (5%), p(r1)min = 0.069 r2 = 82 (5%), p(r2)min = 0.158 imax_tx = 5.5 v / (82 0.95 + 36 0.95 + 10) = 45.04 ma t rise = t fall = 0.85 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise = t fall = 4 ns at c_pad_load = 50 pf (i ncludes up to 25% safety margin) table 7-11 ? i/o hot-swap and 5 v input tolerance capabilities in igloo plus devices i/o assignment clamp diode hot insertion 5 v input tolerance input buffer output buffer 3.3 v lvttl/lvcmos no yes yes * enabled/disabled lvcmos 2.5 v no yes no enabled/disabled lvcmos 1.8 v no yes no enabled/disabled lvcmos 1.5 v no yes no enabled/disabled lvcmos 1.2 v no yes no enabled/disabled * can be implemented with an external idt bus sw itch, resistor divider, or zener with resistor.
i/o structures in igloo plus devices 7-12 v1.2 example 2 (low?medium sp eed, medium current): rtx_out_high = rtx_out_low = 10 r1 = 220 (5%), p(r1)min = 0.018 r2 = 390 (5%), p(r2)min = 0.032 imax_tx = 5.5 v / (220 0.95 + 390 0.95 + 10) = 9.17 ma t rise = t fall = 4 ns at c_pad_load = 10 pf (i ncludes up to 25% safety margin) t rise = t fall = 20 ns at c_pad_load = 50 pf (includes up to 25% safety margin) other values of resistors are also allowed as long as the resistors ar e sized appropriat ely to limit the voltage at the receiving end to 2.5 v < vin (rx) < 3.6 v when the transmitt er sends a logic 1. this range of vin_dc(rx) must be assured for an y combination of transmitter supply (5 v 0.5 v), transmitter output resistance, and board resistor tolerances. temporary overshoots are allowe d according to the overshoot and undersh oot table in the datasheet. figure 7-4 ? solution 1 solution 1 5.5 v 3.3 v requires two board resistors, lvcmos 3.3 v i/os i/o input rext1 rext2
i/o structures in igloo plus devices v1.2 7-13 solution 2 this solution requires one board resistor an d one zener 3.3 v diode, as demonstrated in figure 7-5 . solution 3 this solution requires a bus switch on the board, as demonstrated in figure 7-6 . figure 7-5 ? solution 2 figure 7-6 ? solution 3 solution 2 5.5 v 3.3 v requires one board resistor, one zener 3.3 v diode, lvcmos 3.3 v i/os i/o input rext1 zener 3.3 v solution 3 requires a bus switch on the board, lvttl/lvcmos 3.3 v i/os. i/o input 3.3 v 5.5 v 5.5 v bus switch idtqs32x23
i/o structures in igloo plus devices 7-14 v1.2 5 v output tolerance igloo plus i/os must be set to 3.3 v lvttl or 3.3 v lvcmos mode to reliably drive 5 v ttl receivers. it is also critical that there be no ex ternal i/o pull-up resistor to 5 v, since this resistor would pull the i/o pad voltage beyond the 3.6 v absolute maximum value and consequently cause damage to the i/o. when set to 3.3 v lvttl or 3.3 v lvcmos mode, the i/os can directly drive signals into 5 v ttl receivers. in fact, v ol =0.4v and v oh = 2.4 v in both 3.3 v lvttl and 3.3 v lvcmos modes exceeds the v il =0.8v and v ih = 2 v level requirements of 5 v ttl receivers. therefore, level 1 and level 0 will be recognized correc tly by 5 v ttl receivers. schmitt trigger a schmitt trigger is a buffer used to convert a sl ow or noisy input signal into a clean one before passing it to the fpga. using schmitt trigger buff ers guarantees a fast, noise-free input signal to the fpga. igloo plus devices have schmitt triggers built into their i/o circuitry. schmitt trigger is available on all i/o configurations. this feature can be implemented by using a physical design constr aints (pdc) command ( table 7-4 on page 7-4 ) or by selecting a check box in the i/o a ttribute editor in desi gner. the check box is cleared by default. i/o register combining every i/o has several embedded registers in the i/o tile that are close to the i/o pads. rather than using the internal regist er from the core, the user has the opti on of using these registers for faster clock-to-out timing, and external hold and setup. when combining th ese registers at the i/o buffer, some architectural rules must be met. provided th ese rules are met, the user can enable register combining globally during compile (as shown in the "compiling the design" section in the i/o software control in lo w-power flash devices section of the handbook). this feature is supporte d by all i/o standards. rules for registered i/o function: 1. the fanout between an i/o pin (d, y, or e) an d a register must be equa l to one for combining to be considered on that pin. 2. all registers (input, ou tput, and output enable) connected to an i/o must share the same clear or preset function: ? if one of the registers has a clr pin, all th e other registers that are candidates for combining in the i/o must have a clr pin. table 7-12 ? comparison table for 5 v?compliant receiver solutions solution board components speed current limitations 1 two resistors low to high 1 limited by transmitter's drive strength 2 resistor and zener 3.3 v medium limit ed by transmitter's drive strength 3 bus switch high n/a notes: 1. speed and current consumption increase as the board resistance values decrease. 2. resistor values ensure i/o diode long-term reliability. 3. at 70c, customers could still use 420 on every i/o. 4. at 85c, a 5 v solution on every other i/o is permitted, since the resistance is lower (150 ) and the current is higher. also, the designer can still use 420 and use the solution on every i/o. 5. at 100c, the 5 v solution on every i/o is permitted, since 420 are used to limit the current to 5.9 ma.
i/o structures in igloo plus devices v1.2 7-15 ? if one of the registers has a pre pin, all th e other registers that are candidates for combining in the i/o must have a pre pin. ? if one of the registers has neither a clr nor a pre pin, all the other registers that are candidates for combining must have neither a clr nor a pre pin. ? if the clear or preset pins are present, they must have the same polarity. ? if the clear or preset pins are present, th ey must be driven by the same signal (net). 3. registers connected to an i/o on the output and output enable pins must have the same clock function: ? both the output and output enable registers must not have an e pin (clock enable). weak pull-up and weak pull-down resistors igloo plus devices support optional weak pull-u p and pull-down resistors on each i/o pin. when the i/o is pulled up, it is connected to the v cci of its corresponding i/o bank. when it is pulled down, it is connected to gnd. refer to the datasheet for more information. for low-power applications, configuration of the pull-up or pull-down of the i/o can be used to set the i/o to a known state while the devi ce is in flash*freeze mode. refer to flash*freeze technology and low-power modes in igloo and pr oasic3l devices for more information. the flash*freeze (ff) pin cannot be configured with a weak pull -down or pull-up i/o attribute, as the signal needs to be driven at all times. output slew rate control the slew rate is the amount of time an input signal takes to get from logic low to logic high or vice versa. it is commonly defined as the propagation delay between 10 % and 90 % of the signal's voltage swing. slew rate control is ava ilable for the output buffers of low-power flash devices. the output buffer has a programmable slew rate for bo th high-to-low and low-to-high transitions. the slew rate can be implemen ted by using a pdc command ( table 7-4 on page 7-4 ), setting "high" or "low" in the i/o attribute editor in designer, or instantiating a special i/o macro. the default slew rate value is "high." actel recommends the high slew ra te option to minimize the prop agation delay. this high-speed option may introduce noise into the system if appropriate signal integrity measures are not adopted. selecting a low sl ew rate reduces this kind of noise but adds some delays in the system. low slew rate is recommended wh en bus transients are expected. output drive the output buffers of igloo plus devices can pr ovide multiple drive st rengths to meet signal integrity requirements. the lvttl and lvcmos (e xcept 1.2 v lvcmos) standards have selectable drive strengths. drive strength should also be se lected according to the design requirements and noise immunity of the system.
i/o structures in igloo plus devices 7-16 v1.2 refer to table 7-9 on page 7-9 for more information about th e slew rate and drive strength specification for lvttl/lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 1.8 v, lvcmos 1.5 v, and lvcmos 1.2 v output buffers. simultaneously switching output s (ssos) and printed circuit board layout each i/o voltage bank has a separate ground and power plane for input and output circuits. this isolation is necessary to minimize simultaneous sw itching noise from the input and output (ssi and sso). the switching noise (ground bounce and power bounce) is generated by the output buffers and transferred into input buff er circuits, and vice versa. ssos can cause signal integrity problems on adjacent signals that are not part of the sso bus. both inductive and capacitive coupling parasitics of bo nd wires inside packages and of traces on pcbs will transfer noise from sso busses onto signals adjace nt to those busses. additionally, ssos can produce ground bounce noise and v cci dip noise. these two noise types are caused by rapidly changing currents through gnd and v cci package pin inductances during switching activities ( eq 7-1 and eq 7-2 ). ground bounce noise voltage = l(gnd) di/dt eq 7-1 v cci dip noise voltage = l(v cci ) di/dt eq 7-2 any group of four or more input pins switching on the same clock edge is considered an sso bus. the shielding should be done both on the board and inside the package unless otherwise described. in-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to the sso bus are lvttl/lvcmos inputs, lvttl/lvcmos outputs, or gtl/sstl/hstl/lvds/lvpecl inputs and outputs. board traces in the vicinity of the sso bus have to be adequately shielded from mutu al coupling and inductive noise that can be generated by the sso bus. also, noise generated by the sso bus needs to be reduced inside the package. pcbs perform an important function in feeding sta ble supply voltages to the ic and, at the same time, maintaining signal integrity between devices. key issues that need to be considered are as follows: ? power and ground plane design and decoupling network design ? transmission line reflections and terminations for extensive data per package on the sso and pcb issues, refer to proasic3/e sso and pin placement an d guidelines chapter of the handbook. table 7-13 ? igloo plus output drive and slew i/o standards 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma slew lvttl / lvcmos 3.3 v ??? ??? high low lvcmos 2.5 v ? ? ? ? ? ?highlow lvcmos 1.8 v ?? ? ? ? ? high low lvcmos 1.5 v ?? ? ???high low lvcmos 1.2 v ? ?? ???high low
i/o structures in igloo plus devices v1.2 7-17 i/o software support in actel's libero ide software, default settings have been defi ned for the various i/o standards supported. changes can be made to the default settings via the use of attributes; however, not all i/o attributes are applicable for all i/o standards. table 7-14 ? igloo plus i/o attributes vs. i/o standard applications i/o standard slew (output only) out_drive (output only) res_pull out_load (output only) schmitt trigger hold state combine register lvttl/ lvcmos3.3 ? ? (12) ????? lvcmos2.5 ? ? (12) ????? lvcmos1.8 ? ? (8) ????? lvcmos1.5 ? ? (4) ????? lvcmos1.2 ? ? (2) ????? software defaults high refer to the numbers in parentheses in the above cells. none 5 pf off off no
i/o structures in igloo plus devices 7-18 v1.2 user i/o naming convention due to the comprehensive and flexible nature of igloo plus i/os, a naming scheme is used to show the details of each i/o ( figure 7-7 ). the name identifies to which i/o bank it belongs. i/o nomenclature = ff/gmn/iouxwby gmn is only used for i/os that also have ccc access?i.e., global pins. ff = indicates the i/o dedicated for th e flash*freeze mode activation pin g=global m = global pin location associat ed with each ccc on the devi ce: a (northwest corner), b (northeast corner), c (east midd le), d (southeast corner), e (s outhwest corner), and f (west middle) n = global input mux and pin number of the asso ciated global location m?either a0, a1, a2, b0, b1, b2, c0, c1, or c2. refer to global resources in acte l low-power flash devices for information about the three input pins per clock source mux at ccc location m. u = i/o pair number in the bank, starting at 00 from the northwest i/o bank and proceeding in a clockwise direction x = r (regular?single-ended) for the i/os that support single-ended standards. w = s (single-ended) b = bank y = bank number (0?3). the bank number st arts at 0 from the no rthwest i/o bank and proceeds in a clockwise direction. figure 7-7 ? naming conventions of igloo plus devices ? top view aglp030 aglp060 aglp125 gnd vcc gnd v cci b3 bank 3 bank 3 bank 1 bank 1 bank 2 bank 0 v complf v ccplf gnd v cc v cci b3 gnd v cci b3 gndq gnd gnd v cci b2 v cci b2 v cc v cci b2 v cc gnd v cci b2 gndq gnd tck tdi tms v jtag trst tdo v pump gnd gnd v cc v cci b1 gnd v cc gnd v cci b1 gnd gndq v cci b1 v cc v cci b0 gnd v cc v cci b0 gnd v cci b0 gnd v cci b0 gndq ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c"
i/o structures in igloo plus devices v1.2 7-19 board-level considerations low-power flash devices have robust i/o featur es that can help in reducing board-level components. the devices offer si ngle-chip solutions, which makes the board layout simpler and more immune to signal integrity issues. although, in ma ny cases, these devices resolve board-level issues, special attention should always be given to overall signal integrity. this section covers important board-level considerations to facilitate optimum device performance. termination proper termination of all signal s is essential for good signal quality. nonterminated signals, especially clock signals, can cause malfunctioning of the device. for general termination gu idelines, refer to the board-level considerations application note for actel fpgas. also refer to pin descriptions for termination requirem ents for specific pins. low-power flash i/os are equipped with on-chip pu ll-up/-down resistors. the user can enable these resistors by instantiating them either in the top level of the design (refer to the igloo, fusion, and proasic3 macro library guide for the available i/o macros wi th pull-up/-down) or in the i/o attribute editor in designer if generic input or output buffers are instantiated in the top level. unused i/o pins are configured as inputs with pull-up resistors. as mentioned earlier, low-power flash devices ha ve multiple programmable drive strengths, and the user can eliminate unwanted overshoot an d undershoot by adjustin g the drive strengths. power-up behavior low-power flash devices are power-up/-down friendly; i.e., no particular sequ encing is required for power-up and power-down. this eliminates extra board componen ts for power-up sequencing, such as a power-up sequencer. during power-up, all i/os are tri stated, irrespective of i/o macro type (input buffers, output buffers, i/o buffers with weak pull-ups or weak pull-downs, etc.). once i/os become activated, they are set to the user-selected i/o macros. refer to the power-up/-down behavior of low-power flash devices chapter of the proasic3 and proasic3e handbooks for details. drive strength low-power flash devices have up to seven prog rammable output drive strengths. the user can select the drive strength of a particular output in the i/o attribute editor or can instantiate a specialized i/o macro, su ch as outbuf_s_12 (slew = low, out_drive = 12 ma). the maximum available drive strength is 16 ma pe r i/o. though no i/o should be forced to source or sink more than 16 ma indefinitely, i/os may handle a higher amount of current (refer to the device ibis model for maximum so urce/sink current) during signal transition (ac current). every device package has its own power dissipation lim it; hence, power calculation must be performed accurately to determine how much current can be tolerate d per i/o within that limit. i/o interfacing low-power flash devices are 5 v?input? and 5 v?output?tolerant without adding any extra circuitry. along with other low-vol tage i/o macros, this 5 v tolera nce makes these devices suitable for many types of boar d component interfacing.
i/o structures in igloo plus devices 7-20 v1.2 table 7-15 shows some high-level interfacing examples usin g low-power flash devices. conclusion igloo plus support for multiple i/o standards minimizes board-level components and makes possible a wide variety of applications. the actel designer software, integr ated with actel libero ide, presents a clear visual displa y of i/o assignments, allowing us ers to verify i/o and board-level design requirements before programming the device. the igloo plus device i/o features and functionalities en sure board designers can produce low-cost and low-power fpga applications fulfilling the comple xities of contempora ry design needs. related documents handbook documents board-level considerations http://www.actel.com/documents/boardlevelcons_an.pdf ddr for actel?s low- power flash devices http://www.actel.com/documents/lpd_ddr_hbs.pdf flash*freeze technology an d low-power modes in iglo o and proasic3l devices http://www.actel.com/documen ts/lpd_flashfreeze_hbs.pdf global resources in actel low-power flash devices http://www.actel.com/documents/lpd_global_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf power-up/-down behavior of low-power fl ash devices http://www.actel.com/docum ents/lpd_powerup_hbs.pdf proasic3/e sso and pin placement an d guidelines http://www.actel.c om/documents/pa 3_e_sso_hbs.pdf user?s guides actel libero ide user?s guide http://www.actel.com/documents/libero_ug.pdf igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf smartgen core reference guide http://www.actel.com/documents/genguide_ug.pdf table 7-15 ? igloo plus high-level interface interface clock i/o type frequency type signals in signals out data i/o gm src sync 125 mhz lvttl 8 8 125 mbps tbi src sync 125 mhz lvttl 10 10 125 mbps
i/o structures in igloo plus devices v1.2 7-21 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-025-2 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.2) page v1.1 (june 2008) the "low-power flash device i/o support" section was revised. 7-2 v1.0 (march 2008) the following changes were made to the family de scriptions in table 7-1 low- power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed fro m five to six. 7-2

v1.3 8-1 8 ? i/o software control in low-power flash devices actel fusion, ? igloo, ? and proasic ? 3 i/os provide more design flexibility, allowing the user to control specific features by enabling certain i/o standards. some features are selectable only for certain i/o standards, whereas others are available fo r all i/o standards. for example, slew control is not supported by differential i/o standards. conve rsely, i/o register combinin g is supported by all i/o standards. for detailed information about whic h i/o standards and features are available on each device and each i/o type, refer to the i/o structures sectio n of the handbook for the device you are using. figure 8-1 shows the various points in the software de sign flow where a user can provide input or control of the i/o selection and parameters. a de tailed description is provided throughout this document. figure 8-1 ? user i/o assignment flow chart design entry 1. i/o macro using smartgen 2. i/o buffer cell schematic entry 3. instantiating i/o library macro in hdl code 4. generic buffer using 1, 2, 3 method 5. synthesis 6. compile 6.1 i/o assignments by pdc import 7. i/o assignments by multi-view navigator (mvn) i/o standard selection for generic i/o macro i/o standards and v ref assignment by i/o bank assigner i/o attribute selection for i/o standards 8. layout and other steps
i/o software control in low-power flash devices 8-2 v1.3 low-power flash families i/o support the low-power flash families listed in table 8-1 support i/os and the fu nctions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 8-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 8-1 . where the informati on applies to only one fa mily or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 8-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
i/o software control in low-power flash devices v1.3 8-3 software-controlled i/o attributes users may modify these programmable i/o attribut es using the i/o attribute editor. modifying an i/o attribute may result in a change of state in designer. table 8-2 details which steps have to be re- run as a function of mo dified i/o attribute. table 8-2 ? designer state (resulting from i/o attribute modification) i/o attribute designer states compile layout fuse timing power slew control no no yes yes yes output drive (ma) no no yes yes yes skew control no no yes yes yes resistor pull no no yes yes yes input delay no no yes yes yes schmitt trigger no no yes yes yes out_load no no no yes yes combine_register yes yes n/a n/a n/a notes: 1. no = remains the same, yes = re-r un the step, n/a = not applicable 2. skew control and input delay do not apply to igloo plus.
i/o software control in low-power flash devices 8-4 v1.3 implementing i/os in actel software actel libero ? integrated design environmen t (ide) is integrated with de sign entry tools such as the smartgen macro builder, the viewdraw schemati c entry tool, and an hdl editor. it is also integrated with the synthesis and designer tools. in this section, all necessary steps to implement the i/os are discussed. design entry there are three ways to implement i/os in a design: 1. use the smartgen macro builder to configure i/os by generating specific i/o library macros and then instantiating th em in top-level code. this is especially useful when creating i/o bus structures. 2. use an i/o buffer cell in a schematic design. 3. manually instantiate specific i/o macros in the top-level code. if technology-specific macros, su ch as inbuf_lvcmos33 and outbu f_pci, are used in the hdl code or schematic, the user will not be able to change the i/ o standard later on in designer. if generic i/o macros are used, such as inbuf, outbuf, tribuf, clkbuf, and bibu f, the user can change the i/o standard using the designer i/o attribute editor tool. using smartgen for i/o configuration the smartgen tool in libero id e provides a gui-based method of configuring the i/o attributes. the user can select certain i/o attributes while co nfiguring the i/o macro in smartgen. the steps to configure an i/o macro with specif ic i/o attributes are as follows: 1. open libero ide. 2. on the left hand side of the catalog view, select i/o , as shown in figure 8-2 . figure 8-2 ? smartgen catalog
i/o software control in low-power flash devices v1.3 8-5 3. expand the i/o section and do uble-click one of the options ( figure 8-3 ). 4. double-click any of the varieties. the i/o create core window opens ( figure 8-4 ). as seen in figure 8-4 , there are five tabs to configure the i/ o macro: input buffers, output buffers, bidirectional buffers, tristate buffers, and ddr. input buffers there are two variations : regular and special. if the regular variation is selected, only the width (1 to 128) needs to be entered. the default value for width is 1. the special variation has width, technology, voltage level, and resistor pull-up/-down options (see figure 8-4 ). all the i/o standards and supply voltages (v cci ) supported for the device family are available for selection. figure 8-3 ? expanded i/o section figure 8-4 ? i/o create core window
i/o software control in low-power flash devices 8-6 v1.3 output buffers there are two variations : regular and special. if the regular variation is selected, only the width (1 to 128) needs to be entered. the default value for width is 1. the special variation has width, technology, output drive, and slew rate options. bidirectional buffers there are two variations : regular and special. the regular variation has enable polarity (active hi gh, active low) in addition to the width option. the special variation has width, technology, output dr ive, slew rate, and resistor pull-up/-down options. tristate buffers same as bidirectional buffers. ddr there are eight variations: ddr wi th regular input buffers, specia l input buffers, regular output buffers, special output buffers, regular trista te buffers, special tristate buffers, regular bidirectional buffers, and special bidirectional buffers. these variations resemble the options of the previous i/o ma cro. for example, the special input buffers variation has width, technology, voltage level, and resistor pull-up/-down options. ddr is not available on igloo plus devices. 5. once the desired configuration is selected, click the generate button. the generate core window opens ( figure 8-5 ). 6. enter a name for the macro. click ok . the core will be generated and saved to the appropriate location with in the project files ( figure 8-6 on page 8-7 ). 7. instantiate the i/o macr o in the top-level code. the user must instantiate the ddr_reg or dd r_out macro in the design. use smartgen to generate both these macros and then instantia te them in your top level. to combine the ddr macros with the i/o, th e following rules must be met: figure 8-5 ? generate core window
i/o software control in low-power flash devices v1.3 8-7 rules for the ddr i/o function ? the fanout between an i/o pin (d or y) and a ddr (ddr_reg or ddr_out) macro must be equal to one for th e combining to happen on that pin. ? if a ddr_reg macro and a ddr_out macro are combined on the same bidirectional i/o, they must share the same clear signal. ? registers will not be combined in an i/o in the presence of ddr combining on the same i/o. using the i/o buffe r schematic cell libero ide includes the viewdraw schematic entry too l. using viewdraw, the user can insert any supported i/o buffer cell in the top-level schematic. figure 8-6 shows a top-level schematic with different i/o buffer cells. when synthesized, the netlist will contain the same i/o macro. figure 8-6 ? i/o buffer schematic cell usage
i/o software control in low-power flash devices 8-8 v1.3 instantiating in hdl code all the supported i/o macros can be instantiat ed in the top-level hdl code (refer to the igloo, fusion, and proasic3 macro library guide for a detailed list of all i/o macros). the following is an example: library ieee; use ieee.std_logic_1164.all; library proasic3e; entity top is port(in2, in1 : in std_logic; out1 : out std_logic); end top; architecture def_arch of top is component inbuf_lvcmos5u port(pad : in std_logic := 'u'; y : out std_logic); end component; component inbuf_lvcmos5 port(pad : in std_logic := 'u'; y : out std_logic); end component; component outbuf_sstl3_ii port(d : in std_logic := 'u'; pad : out std_logic); end component; other component ?.. signal x, y, z??.other signals : std_logic; begin i1 : inbuf_lvcmos5u port map(pad => in1, y =>x); i2 : inbuf_lvcmos5 port map(pad => in2, y => y); i3 : outbuf_sstl3_ii port map(d => z, pad => out1); other port mapping? end def_arch; synthesizing the design libero ide integrates with the synplify ? synthesis tool. other synthesis tools can also be used with libero ide. refer to the actel libero ide user?s guide or libero ide online help for details on how to set up the libero ide tool profile with synthesis tools from other vendors. during synthesis, the following rules apply: ? generic macros: ? users can instantiate generic inbuf, outbuf, tribuf, and bibuf macros. ? synthesis will automatically infer generic i/o macros. ? the default i/o technology for these macros is lvttl. ? users will need to use the i/ o attribute editor in design er to change the default i/o standard if needed (see figure 8-7 on page 8-9 ). ? technology-specific i/o macros: ? technology-specific i/o macros, such as inbuf_lvcmo25 and outbuf_gtl25, can be instantiated in the design. synthesis will infer these i/o macros in the netlist.
i/o software control in low-power flash devices v1.3 8-9 ? the i/o standard of technology-specific i/o macros cannot be changed in the i/o attribute editor (see figure 8-7 ). ? the user must instantiate differential i/o ma cros (lvds/lvpecl) in the design. this is the only way to use these standards in the design. ? to implement the ddr i/o function, the us er must instantiate a ddr_reg or ddr_out macro. this is the only way to use a ddr macro in the design. performing place-and- route on the design the netlist created by the synthe sis tool should now be import ed into designer and compiled. during compile, the user can specify the i/o plac ement and attributes by importing the pdc file. the user can also specify the i/o placement and at tributes using chipplanner and the i/o attribute editor, under mvn. defining i/o assignments in the pdc file a pdc file is a tcl script file specifying physic al constraints. this file can be imported to and exported from designer. table 8-3 shows i/o assignment constraint s supported in the pdc file. figure 8-7 ? assigning a different i/o standa rd to the generic i/o macro table 8-3 ? pdc i/o constraints command action example comment i/o banks setting constraints set_iobank sets the i/o supply voltage, v cci , and the input reference voltage, v ref , for the specified i/o bank. set_iobank bankname [-vcci vcci_voltage] [-vref vref_voltage] set_iobank bank7 -vcci 1.50 -vref 0.75 must use in case of mixed i/o voltage (v cci ) design set_vref assigns a v ref pin to a bank. set_vref -bank [bankname] [pinnum] set_vref -bank bank0 685 704 723 742 761 must use if voltage- referenced i/os are used note: refer to the actel libero ide user?s guide for detailed rules on pdc naming and syntax conventions.
i/o software control in low-power flash devices 8-10 v1.3 set_vref_defaults sets the default v ref pins for the specified bank. this command is ignored if the bank does not need a v ref pin. set_vref_defaults bankname set_vref_defaults bank2 i/o attribute constraint set_io sets the attributes of an i/o set_io portname [-pinname value] [-fixed value] [-iostd value] [-out_drive value] [-slew value] [-res_pull value] [-schmitt_trigger value] [-in_delay value] [-skew value] [-out_load value] [-register value] set_io in2 -pinname 28 -fixed yes -iostd lvcmos15 -out_drive 12 -slew high -res_pull none -schmitt_trigger off -in_delay off ?skew off -register no if the i/o macro is generic (e.g., inbuf) or technology- specific (inbuf_lvcmos25), then all i/o attributes can be assigned using this constraint. if netlist has an i/o macro that specifies one of its attributes, that attribute cannot be changed using this constraint, though other attributes can be changed. example: outbuf_s_24 (low slew, output drive 24 ma) slew and output drive cannot be changed. i/o region plac ement constraints define_region defines either a rectangular region or a rectilinear region define_region -name [region_name] -type [region_type] x1 y1 x2 y2 define_region -name test -type inclusive 0 15 2 29 if any number of i/os must be assigned to a particular i/o region, such a region can be created with this constraint. assign_region assigns a set of macros to a specified region assign_region [region name] [macro_name...] assign_region test u12 this constraint assigns i/o macros to the i/o regions. when assigning an i/o macro, pdc naming conventions must be followed if the macro name contains special characters; e.g., if the macro name is \\$1i19\\, the correct use of escape characters is \\\\\$1i19\\\\. table 8-3 ? pdc i/o constraints (continued) command action example comment note: refer to the actel libero ide user?s guide for detailed rules on pdc naming and syntax conventions.
i/o software control in low-power flash devices v1.3 8-11 compiling the design during compile, a pdc i/o constraint file can be imported along with the netlist file. if only the netlist file is compiled, certain i/o assignments n eed to be completed before proceeding to layout. all constraints that can be entered in pdc can al so be entered using chipplanner, i/o attribute editor, and pineditor. there are certain rules that must be followed in implementing i/o register combining and the i/o ddr macro (refer to the i/o registers section of the handbook for the device that you are using and the "ddr" section on page 8-6 for details). provided these rules are met, the user can enable or disable i/o register combin ing by using the pdc command set_io portname ?register yes|no in the i/o attribute editor or selecting a ch eck box in the compile options dialog box (see figure 8-8 ). the compile options dialog box appears when the design is compiled for the first time. it can also be accessed by choosing options > compile during successive runs. i/o register combining is off by default. the pdc command ov errides the setting in th e compile options dialog box. understanding the compile report the i/o bank report is generated during compile and displayed in the log window. this report lists the i/o assignments necessary before layout can proceed. when designer is started, the i/o bank assigner to ol is run automatically if the layout command is executed. the i/o bank assigner takes care of the necessary i/o assignments. however, these assignments can also be made manually with mv n or by importing the pdc file. refer to the "assigning technologies and v ref to i/o banks" section on page 8-14 for further description. the i/o bank report can also be extra cted from designer by choosing to o l s > report and setting the report type to iobank . this report has the following tables: i/o function , i/o technology, i/o bank resource usage, and i/o voltage usage. this report is useful if th e user wants to do i/o assignments manually. figure 8-8 ? setting register combining during compile
i/o software control in low-power flash devices 8-12 v1.3 i/o function figure 8-9 shows an example of the i/o function table included in the i/o bank report: this table lists the number of input i/os, output i/os, bidirectional i/os, and differential input and output i/o pairs that us e i/o and ddr registers. certain rules must be met to implement registe red and ddr i/o functions (refer to the i/o structures section of the handbook for the device you are using and the "ddr" section on page 8-6 ). i/o technology the i/o technology table (shown in figure 8-10 ) gives the values of v cci and v ref (reference voltage) for all the i/o standards used in the design. the user should assign these voltages appropriately. figure 8-9 ? i/o function table figure 8-10 ? i/o technology table
i/o software control in low-power flash devices v1.3 8-13 i/o bank res ource usage this is an important portion of the report. th e user must meet the requirements stated in this table. figure 8-11 shows the i/o bank resource usage ta ble included in the i/o bank report: the example in figure 8-11 shows that none of the i/o macros is assigned to the bank because more than one v cci is detected. i/o voltage usage the i/o voltage usage table provides the number of v ref (e devices only) and v cci assignments required in the design. if the us er decides to make i/o assignme nts manually (pdc or mvn), the issues listed in this ta ble must be resolved be fore proceeding to layout. as stated earlier, v ref assignments must be made if there are any voltage-referenced i/os. figure 8-12 shows the i/o voltage usage table included in the i/o bank report. the table in figure 8-12 indicates that there are two voltage- referenced i/os used in the design. even though both of the voltage-referenc ed i/o technologies have the same v cci voltage, their v ref voltages are different. as a result, tw o i/o banks are needed to assign the v cci and v ref voltages. figure 8-11 ? i/o bank resource usage table figure 8-12 ? i/o voltage usage table
i/o software control in low-power flash devices 8-14 v1.3 in addition, there are six single-end ed i/os used that have the same v cci voltage. since two banks are already assigned with the same v cci voltage and there are enough unused bonded i/os in those banks, the user does not ne ed to assign the same v cci voltage to another ba nk. the user needs to assign the other three v cci voltages to three more banks. assigning technologies and v ref to i/o banks low-power flash devices offer a wide variety of i/o standards, includ ing voltage-referenced standards. before proceeding to layout, each bank must have the required v cci voltage assigned for the correspondin g i/o technologies used for that ba nk. the voltage-referenced standards require the use of a reference voltage (v ref ). this assignment can be done manually or automatically. the following sections describe this in detail. manually assigning technologies to i/o banks the user can import the pdc at this point an d resolve this requirem ent. the pdc command is set_iobank [bank name] ?vcci [vcci value] another method is to use the i/o bank settings dialog box ( mvn > edit > i/o bank settings ) to set up the v cci voltage for the bank ( figure 8-13 ). figure 8-13 ? setting v cci for a bank
i/o software control in low-power flash devices v1.3 8-15 the procedure is as follows: 1. select the bank to which you want v cci to be assigned from the choose bank list. 2. select the i/o standards for that bank. if you select any standard, the tool will automatically show all compatible standar ds that have a common v cci voltage requirement. 3. click apply . 4. repeat steps 1?3 to assign v cci voltages to other banks. refer to figure 8-12 on page 8-13 to find out how many i/o banks are needed for v cci bank assignment. manually assigning v ref pins voltage-referenced inputs require an input reference voltage (v ref ). the user must assign v ref pins before running layout. before assigning a v ref pin, the user must set a v ref technology for the bank to which the pin belongs. v ref rules for the implementation of voltage-referenced i/o standards the v ref rules are as follows: 1. any i/o (except jtag i/os) can be used as a v ref pin. 2. one v ref pin can support up to 15 i/os. it is re commended, but not required, that eight of them be on one side and seven on the other side (in other words, all 15 can still be on one side of v ref ). 3. sstl3 (i) and (ii): up to 40 i/os per north or south bank in any position 4. lvpecl / gtl+ 3.3 v / gtl 3.3 v: up to 48 i/os per north or south bank in any position 5. sstl2 (i) and (ii) / gtl+ 2.5 v / gtl 2.5 v: up to 72 i/os per north or south bank in any position. 6. v ref minibanks partition rule: each i/o bank is physically partitioned into v ref minibanks. the v ref pins within a v ref minibank are interconnected internally, and consequently, only one v ref voltage can be used within each v ref minibank. if a bank does not require a v ref signal, the v ref pins of that bank are available as user i/os. 7. the first v ref minibank includes all i/os starting from one end of the bank to the first power triple and eight more i/os after the power triple . therefore, the first v ref minibank may contain (0 + 8), (2 + 8), (4 + 8 ), (6 + 8), or (8 + 8) i/os. the second v ref minibank is adjacent to the first v ref minibank and contains eight i/os, a power triple, and eight mo re i/os after the triple. an analogous rule applies to all other v ref minibanks but the last. the last v ref minibank is adjacent to the previous one but contains eight i/os, a power triple, and all i/os left at th e end of the bank. this bank may also contain (8 + 0), (8 + 2), (8 + 4), (8 + 6), or (8 + 8) available i/os. example: 4 i/os triple 8 i/os, 8 i/os triple 8 i/os, 8 i/os triple 2 i/os i.e., minibank a = (4 + 8) i/ os, minibank b = (8 + 8) i/os, minibank c = (8 + 2) i/os assigning the v ref voltage to a bank when importing th e pdc file, the v ref voltage can be assigned to the i/o bank. the pdc command is as follows: set_iobank ?vref [value] another method for assigning v ref is by using mvn > edit > i/o bank settings ( figure 8-14 on page 8-16 ).
i/o software control in low-power flash devices 8-16 v1.3 assigning v ref pins for a bank the user can use default pins for v ref . in this case, select the use default pins for v ref s check box ( figure 8-14 ). this option guarantees full v ref coverage of the bank. th e equivalent pdc command is as follows: set_vref_default [bank name] to be able to choose v ref pins, adequate v ref pins must be created to a llow legal placement of the compatible voltage-referenced i/os. to assign v ref pins manually, the pdc command is as follows: set_vref ?bank [bank name] [package pin numbers] for chipplanner/pineditor to show the range of a v ref pin, perform the following steps: 1. assign v cci to a bank using mvn > edit > i/o bank settings . 2. open chipplanner . zoom in on an i/o package pin in that bank. 3. highlight the pin and th en right-click. choose use pin for v ref . figure 8-14 ? selecting v ref voltage for the i/o bank v ref for gtl+ 3.3 v
i/o software control in low-power flash devices v1.3 8-17 4. right-click and then choose show v ref range . all the pins covered by that v ref pin will be highlighted ( figure 8-15 ). using pineditor or chipplanner, v ref pins can also be assigned ( figure 8-16 ). to unassign a v ref pin: 1. select the pin to unassign. 2. right-click and choose use pin for v ref . the check mark next to the command disappears. the v ref pin is now a regular pin. resetting the pin may result in una ssigning i/o cores, even if they are locked. in this case, a warning message appears so you can cancel the operation. after you assign the v ref pins, right-click a v ref pin and choose highlight vref range to see how many i/os are covered by this pin. to unhighlight the range, choose unhighlight all from the edit menu. figure 8-15 ? v ref range figure 8-16 ? assigning v ref from pineditor
i/o software control in low-power flash devices 8-18 v1.3 automatically assigning technologies to i/o banks the i/o bank assigner (ioba) to ol runs automatically when you run layout. you can also use this tool from with in the multiview navigator ( figure 8-18 ). the ioba tool au tomatically assigns technologies and v ref pins (if required) to every i/o bank that does not currently have any technologies assigned to it. this tool is avai lable when at least one i/o bank is unassigned. to automatically assign techno logies to i/o banks, choose i/o bank assigner from the to o l s menu (or click the i/o bank assigner's toolbar button, shown in figure 8-17 ). messages will appear in the output window informing you when the automatic i/o bank assignment begins and ends. if the assignment is successful, the message "i/o bank assigner completed successfully" appears in the output window, as shown in figure 8-18 . figure 8-17 ? i/o bank assigner?s toolbar button figure 8-18 ? i/o bank assigner displays messages in output window
i/o software control in low-power flash devices v1.3 8-19 if the assignment is not successful, an er ror message appears in the output window. to undo the i/o bank assignments, choose undo from the edit menu. undo removes the i/o technologies assigned by the ioba . it does not remove the i/o te chnologies previously assigned. to redo the changes undone by the undo command, choose redo from the edit menu. to clear i/o bank assignments made before using the undo command, manually unassign or reassign i/o technologies to banks. to do so, choose i/o bank settings from the edit menu to display the i/o bank settings dialog box. conclusion actel fusion, igloo, and proasic3 support for multiple i/o standards minimizes board-level components and makes po ssible a wide variety of applicatio ns. the actel designer software, integrated with actel libe ro ide, presents a clear visual displa y of i/o assignmen ts, allowing users to verify i/o and board-level design requiremen ts before programming the device. the device i/o features and functionalities en sure board designers can produce low-cost and low-power fpga applications fulfilling the complexiti es of contemporary design needs. related documents handbook documents ddr for actel?s low- power flash devices http://www.actel.com/documents/lpd_ddr_hbs.pdf flash*freeze technology an d low-power modes in iglo o and proasic3l devices http://www.actel.com/documen ts/lpd_flashfreeze_hbs.pdf global resources in actel low-power flash devices http://www.actel.com/documents/lpd_global_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglooe and proasic3e devices http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf power-up/-down behavior of low-power fl ash devices http://www.actel.com/docum ents/lpd_powerup_hbs.pdf proasic3/e sso and pin placement an d guidelines http://www.actel.c om/documents/pa 3_e_sso_hbs.pdf user?s guides actel libero ide user?s guide http://www.actel.com/documents/libero_ug.pdf igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf smartgen core reference guide http://www.actel.com/documents/genguide_ug.pdf
i/o software control in low-power flash devices 8-20 v1.3 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-026-2 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current version (v1.3) page v1.2 (june 2008) the "low-power flash families i/o support" section was revised to include new families and make the information more concise. 8-2 v1.1 (march 2008) the following changes were made to the family descriptions in table 8-1 low-power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasic3 e was changed from five to six. 8-2 v1.0 (january 2008) this document was previously part of the i/o structures in igloo and proasic3 devices document. the conten t was separated and made into a new document. n/a table 8-2 designer state (resulting from i/o attribute modification) was updated to include note 2 for igloo plus. 8-3
packaging and pin descriptions

v1.2 9-1 9 ? pin descriptions supply pins gnd ground ground supply voltage to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. with in the package, the gndq plane is decoupled from the simultaneous switching noi se originated from the output buffer ground domain. this minimizes the noise transfer within the pa ckage and improves in put signal integrity. gndq must always be connected to gnd on the board. v cc core supply voltage supply voltage to the fpga co re, nominally 1.5 v for proasic ? 3/e devices, 1.5 v for igloo ? /e v5 devices, and 1.2 v or 1.5 v for ig loo/e v2 and proa sic3l devices. v cc is required fo r powering the jtag state machine in addition to v jtag . even when a device is in bypass mode in a jtag chain of interconnected devices, both v cc and v jtag must remain powered to al low jtag signals to pass through the device. for igloo/e v2 and pr oasic3l devices, v cc can be switched dynamically from 1.2 v to 1.5 v or vice versa. this allows in-system programming (isp) when v cc is at 1.5 v and the benefit of low-power operation when v cc is at 1.2 v. v cci bx i/o supply voltage supply voltage to the bank's i/o output buffers an d i/o logic. bx is the i/ o bank number. there are up to eight i/o banks on low-power flash devices plus a dedicated v jtag bank. each bank can have a separate v cci connection. all i/os in a bank will run off the same v cci bx supply. v cci can be 1.2 v (not supported on proasic3/e devices), 1.5 v, 1. 8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding v cci pins tied to gnd. vmvx i/o supply voltage (quiet) quiet supply voltage to the input buffers of each i/o bank. x is the bank number. within the package, the vmv plane is decoupled from the simu ltaneous switching nois e originated from the output buffer v cci domain. this minimizes the noise transfer within the package and improves input signal integrity. each bank must have at least one vmv connection, and no vmv should be left unconnected. all i/os in a bank run off the same vmvx supply. vmv is used to provide a quiet supply voltage to th e input buffers of each i/o bank. vmvx can be 1.2 v (proasic3l and igloo/e devices only), 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vmv pins tied to gnd. vmv and v cci should be at the same voltage within a given i/o bank. used vmv pins must be connected to the corresponding v cci pins of the same bank (i.e., vmv0 to v cci b0, vmv1 to v cci b1, etc.). v ccpla/b/c/d/e/f pll supply voltage supply voltage to analog pll, nominally 1.5 v or 1.2 v, depending on the device family. ? 1.5 v for igloo v5, iglooe v5, proasic3, and proasic3e devices ? 1.2 v or 1.5 v for igloo v2, iglooe v2, proasic3l, and proasic3el devices when the plls are not used, the actel designer place-and-route t ool automaticall y disables the unused plls to lower power consumption. the user should tie unused v ccplx and v complx pins to ground. actel recommends tying v ccplx to v cc and using proper filtering circuits to decouple v cc noise from pll. refer to the pll power supply decoupling section of clock conditioning circuits in igloo and proasic3 devices for a complete board so lution for the pll analog power supply and ground. ? there is one v ccplf pin on igloo, igloo plus, proasic3l, and proasic3 devices. ? there are six v ccplx pins on iglooe, proasic3el, and proasic3e devices.
pin descriptions 9-2 v1.2 v compla/b/c/d/e/f pll ground ground to analog pll power supp lies. when the plls are not used , the actel designer place-and- route tool automatically disables the unused plls to lower power co nsumption. the user should tie unused v ccplx and v complx pins to ground. ? there is one v complf pin on igloo, proasic3l, and proasic3 devices. ? there are six v compl pins (pll ground) on iglooe, proasic3el, and proasic3e devices. v jtag jtag supply voltage low-power flash devices have a separate bank for the dedi cated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). isolating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned for use, the v jtag pin together with the trst pin could be tied to gnd. it should be noted that v cc is required to be powered for jtag operation; v jtag alone is insufficient. if a device is in a jtag ch ain of interconnected boards, the board containing the device can be powered down, provided both v jtag and v cc to the part remain powered; otherwise, jtag signals will not be able to transition the device, even in bypass mode. actel recommends that v pump and v jtag power supplies be kept se parate with independent filtering capacitors rather than supplying them fro m a common rail. v pump programming supply voltage igloo, proasic3l, and proasic3 devices support si ngle-voltage isp of the configuration flash and flashrom. for programming, v pump should be 3.3 v nominal. during normal device operation, v pump can be left floating or can be tied (pul led up) to any voltage between 0 v and the v pump maximum. programming po wer supply voltage (v pump ) range is listed in the datasheet. when the v pump pin is tied to ground, it will shut of f the charge pump circ uitry, resulting in no sources of oscillation from the charge pump circuitry. for proper programming, 0.01 f and 0.33 f capacito rs (both rated at 16 v) are to be connected in parallel across v pump and gnd, and positioned as close to the fpga pins as possible. actel recommends that v pump and v jtag power supplies be kept se parate with independent filtering capacitors rather than supplying them fro m a common rail. user-defined supply pins v ref i/o voltage reference reference voltage for i/o minibanks in iglooe, proasic3el, and proasic3e devices. v ref pins are configured by the user from regular i/os, an d any i/o in a bank, except jtag i/os, can be designated the voltage re ference i/o. only certain i/o standa rds require a voltage reference?hstl (i) and (ii), sstl2 (i) and (ii), sstl3 (i) and (ii), and gtl/gtl+. one v ref pin can support the number of i/os available in its minibank.
pin descriptions v1.2 9-3 user pins i/o user input/output the i/o pin functions as an input, output, tristate , or bidirectional buffer. input and output signal levels are compatible with the i/o standard selected. during programming, i/os become tristated and weakly pulled up to v cci . with v cci , vmv, and v cc supplies continuously powered up, when the devi ce transitions from programming to operating mode, the i/os are instantly configured to the desired us er configuration. unused i/os are configured as follows: ? output buffer is disabled (with tristate value of high impedance) ? input buffer is disabled (with tristate value of high impedance) ? weak pull-up is programmed gl globals gl i/os have access to certain clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the glob al i/os can be used as regular i/os, since they have identical capabilities. unused gl pins ar e configured as inputs wi th pull-up resistors. see more detailed descriptions of global i/o connectivity in clock conditioning circuits in igloo and proasic3 devices . all inputs labeled gc/gf are direct inputs into the quadrant clocks. for example, if gaa0 is used for an input, gaa1 an d gaa2 are no longer avai lable for input to the quadrant globals. all inputs labe led gc/gf are direct inputs into th e chip-level globals, and the rest are connected to the quadrant gl obals. the inputs to th e global network are multiplexed, and only one input can be used as a global input. refer to the i/o structure section of the handbook for the device you are using for an explanation of the naming of global pins. ff flash*freeze mode activation pin flash*freeze is available on iglo o, proasic3l, and rt proasic3 devices. it is not supported on proasic3/e devices. the ff pin is a dedicated input pin used to enter and exit flash*freeze mode. the ff pin is active-low, has the same characteristi cs as a single-ended i/o, and must meet the maximum rise and fall times. wh en flash*freeze mode is not us ed in the design , the ff pin is available as a regular i/o. for iglooe, proasi c3el and rt proasic3 only, the ff pin can be configured as a schmitt trigger input. when flash*freeze mode is used, the ff pin must no t be left floating to avoid accidentally entering flash*freeze mode. wh ile in flash*freeze mo de, the flash*freeze pin should be constantly asserted. the flash*freeze pin can be used with any single-e nded i/o standard supported by the i/o bank in which the pin is located, and input signal levels compatible with the i/o standard selected. the ff pin should be treated as a sensitive asynchrono us signal. when defining pin placement and board layout, simultaneously switching outputs (ssos) and th eir effects on sensit ive asynchronous pins must be considered. unused ff or i/o pins are tristated with weak pull-up. this default configuration applies to both flash*freeze mode and normal operation mode . no user intervention is required.
pin descriptions 9-4 v1.2 table 9-1 shows the flash*freeze pin location on th e available packages for igloo and proasic3l devices. the flash*freeze pin location is indepe ndent of device (except for a pq208 package), allowing migration to larger or smaller igloo de vices while maintaining th e same pin location on the board. refer to flash*freeze technology and low-po wer modes in igloo and proasic3l devices for more information on i/o states during fl ash*freeze mode. jtag pins low-power flash devices have a separate bank for the dedi cated jtag pins. the jtag pins can be run at any voltage from 1. 5v to 3.3v (nominal). v cc must also be powered for the jtag state machine to operate, even if the device is in bypass mode; v jtag alone is insufficient. both v jtag and v cc to the part must be supplied to allow jtag sign als to transition the device. isolating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither us ed nor planned for use, the v jtag pin together with the trst pin could be tied to gnd. tck test clock test clock input for jtag boundary scan, isp, and ujtag. the tck pin does not have an internal pull-up/-down resistor. if jtag is not used, actel recommends tying of f tck to gnd through a resistor placed close to the fpga pin. this prevents jtag operatio n in case tms enters an undesired state. table 9-1 ? flash*freeze pin location in igloo and proasic3l family packages (device- independent) igloo and proasic3l packages flash*freeze pin cs81/uc81 h2 cs121 j5 cs196 p3 qn68 18 qn132 b12 cs281 w2 cs201 (package available only for igloo plus devices) r4 cs289 (package available only for igloo plus devices) tbd vq100 27 fg144 l3 fg256 t3 fg484 w6 cg/lg484 (package available only for rt proasic3 devices) w6 fg896 ah4 cg/lg896 (package available only for rt proasic3 devices) tbd pq208 (package available on ly for proasic3l devices) pq208-a3p250 pq208-a3p600l pq2097-a3p1000l pq208-a3pe3000l 56 55 55 58
pin descriptions v1.2 9-5 note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. refer to table 9-2 for more information. tdi test data input serial input for jtag boundary sc an, isp, and ujtag usage. ther e is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jt ag boundary scan, isp, and ujtag usage. tms test mode select the tms pin controls the use of the ieee 1532 bounda ry scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trst boundary scan reset pin the trst pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the tr st pin. if jtag is not used, an external pull-down resistor could be included to ensure the test access port (tap) is held in reset mode. the resistor values must be chosen from table 9-2 and must satisfy the parallel resistance value requirement. the values in table 9-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resist or when multiple devices are connected via a jtag chain. in critical applications, an upset in the jtag circuit could allow entranc e to an undesired jtag state. in such cases, actel recommends tying off tr st to gnd through a resi stor placed close to the fpga pin. note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. special function pins nc no connect this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effe ct on the operation of the device. dc do not connect this pin should not be connected to any signals on the pcb. these pins should be left unconnected. table 9-2 ? recommended tie-off values for the tck and trst pins v jtag tie-off resistance v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k notes: 1. equivalent parallel resistance if more than one device is on the jtag chain 2. the tck pin can be pulled up/down. 3. the trst pin is pulled down.
pin descriptions 9-6 v1.2 related documents handbook documents clock conditioning circuits in igloo and proasic3 devices http://www.actel.com/documents/lpd_ccc_hbs.pdf i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in iglooe and proasic3e devices http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf flash*freeze technology an d low-power modes in iglo o and proasic3l devices http://www.actel.com/documen ts/lpd_flashfreeze_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet. to improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage info rmation. no technical chan ges were made to the content unless explicitly listed. part number 51700094-011-2 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.2) page v1.1 (march 2008) the "ff flash*freeze mode ac tivation pin" section was updated to include rt proasic3 devices. 9-3 cg/lg484 and cg/lg896 were added to table 9-1 flash*freeze pin location in igloo and proasic3l family pa ckages (device-independent) . 9-4 v1.0 (january 2008) the "vccibx i/o supply voltage" section was revised to note that 1.2 v is not supported for proasic3/e devices. the "vmvx i/o supply voltage (quiet)" section was updated to state that vmvx ca n also be 1.2 v nominal voltage on proasic3l and igloo/e devices. 9-1 the "handbook documents" section was revised to include the three different i/o structures chapters for iglo o and proasic3 device families. 9-6 the "v ccpla/b/c/d/e/f pll supply voltage" section and "v compla/b/c/d/e/f pll ground" section were revised. the "v ccplf pll supply voltage" section and "v complf pll ground" section were removed. 9-1 to 9-2 the following packages were added to table 9-1 flash*freeze pin location in igloo and proasic3l family packages (device-independent) : uc81, qn68, cs201, and cs289. flash*freeze pin w2 was specified for the cs281 package. the pg208 package was changed to the correct designation of pq208. 9-4
v1.0 10-1 10 ? packaging semiconductor technology is consta ntly shrinking in size while growing in capability and functional integration. to enable next-generation silicon technologies, semiconduc tor packages have also evolved to provide improved performance and flexibility. actel consistently delivers packages that prov ide the necessary mechan ical and environmental protection to ensure consistent reliability and performance. actel ic packaging technology efficiently supports hi gh-density fpgas with large-pin-count ball grid arrays (bgas), but is also flexible enough to acco mmodate stringent form factor requirements for chip scale packaging (csp). in addition, actel offers a variety of packages designed to meet your most demanding application and economic requirements fo r today's embedded and mobile systems. the following documents provide packaging inform ation and device selection for low-power flash devices. package selector guide http://www.actel.com/documents/selguide.pdf lists devices currently recommended for new desi gns and the packages av ailable for each member of the family. use this document or the datash eet tables to determine the best package for your design, and which package drawing to use. package mechanical drawings http://www.actel.com/documents/pckgmechdrwngs.pdf this document contains the pac kage mechanical drawings for all packages currently or previously supplied by actel. use the bo okmarks to navigate to the package mechanical drawings. related documents additional packaging materials are available at http://www.actel.com/products/ solutions/pac kage/docs.aspx . part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 5170009-012-0 revised january 2008

programming and security

v1.2 11-1 11 ? programming flash devices introduction this document provides an over view of the various programming options available for the actel flash families. the electr onic version of this document includes active links to all programming resources, which are available at http://www.actel.com/produc ts/hardware/default.aspx . for actel antifuse devices, refer to the programming anti fuse devices document. summary of programming support flashpro3 is a high-performance in-system prog ramming (isp) tool ta rgeted at the latest generation of low-power flash devices offered by actel: fusion, igloo, ? and proasic ? 3, including arm ? -enabled devices. flashpro3 offers extremely high performance through the use of usb 2.0, is high-speed compliant for full use of the 480 mbps bandwidth, and can program proasic3 devices in under 30 seconds. powered exclusiv ely via usb, flashpro3 provides a v pump voltage of 3.3 v for programming these devices. silicon sculptor 3 is an easy-to-u se, single-site programming tool for actel fpgas that delivers high data throughput and promotes ease of use whil e lowering the overall cost of ownership. silicon sculptor 3 includes a high-speed usb 2.0 interface that allows a customer to connect as many as 12 programmers to a single pc. furthe rmore, silicon sculptor 3 is co mpatible with adapter modules from silicon sculptor ii , thereby preserving a customer's investment and enabling a seamless upgrade to this latest ge neration of the tool. for details of programmer suppo rt for each device, refer to table 11-6 on page 11-10 . figure 11-1 ? flashpro programming setup flashpro software flashpro3 jtag proasic3/e pdb file with security settings
programming flash devices 11-2 v1.2 programming support in flash devices the flash families listed in table 11-1 support flash in-system pr ogramming and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 11-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 11-1 . where the information applies to on ly one family or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 11-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l proasic proasic first generation proasic devices proasic plus second generation proasic devices note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
programming flash devices v1.2 11-3 general flash programming information programming basics when choosing a programming solu tion, there are a number of op tions available. this section provides a brief overview of those options. the next sections provide more detail on those options as they apply to actel fpgas. reprogrammable or one-time-programmable (otp) depending on the technology chosen, devi ces may be reprogrammable or one-time- programmable. as the name impl ies, a reprogrammable device can be programmed many times. generally, the contents of such a device will be completely overwritten wh en it is reprogrammed. all actel flash devices are reprogrammable. an otp device is programmable one time only. once programmed, no more changes can be made to the contents. actel flash devi ces provide the option of disa bling the reprogrammability for security purposes. this combines the convenience of reprogrammabi lity during design verification with the security of an otp techno logy for highly sensitive designs. device programmer or in-system programming there are two fundamental ways to program an fpga: using a device programmer or, if the technology permits, using in-system programming. a device programmer is a piece of equipment in a lab or on the production floor that is used fo r programming devices. th e devices are placed into a socket mounted in a programming adapter modu le, and the appropriate electrical interface is applied. the device can then be placed on the board. a typical programmer, used during development, programs a single device at a time and is referred to as a single-site engineering programmer. with isp, the device is alread y mounted onto the board when pr ogramming occurs, most typically via the jtag pins. the jtag pins can be controlled either by an on-board resource, such as a microprocessor, or by an off-board programmer through a header connection. once mounted, it can be programmed repeatedly. if the applicatio n requires it, the syst em can be designed to reprogram itself using a microprocessor, wi thout the use of any external programmer. for production, high-volume multi-site production programmers handle designs that require device programmers. in addition, actel can preprogram devices for production, negating the need for further programming. this service is re ferred to as in-hou se programming (ihp). live at power-up (l apu) or boot prom utilizing the technology of the fpga significan tly impacts board-level po wer-up considerations. some technologies are nonvolatile and are consid ered functional, or "live," as soon as power reaches the operational level. all actel fpga tech nologies are live at power-up. by contrast, sram technology is volatile, and devices built using sr am cells lose their cont ents when power cycling occurs. these devices must be reprogrammed ever y time power is applied. such a design must include nonvolatile storage for the contents as we ll as the means to reprogram. there is a delay before sram devices are functional; other parts of the board mu st come alive first to reprogram these types of fpgas. therefore, such devices ca n never be part of critical boot circuits. design security design security is a growin g concern for systems designer s. the choice of programming methodology and technology affects system security . use of actel programmi ng technology is the most secure option available, pr oviding much better protection than sram-based devices and asics. actel provides a number of ways to ensu re designs are protected. general information on design security can be fo und on the actel website: http://www.actel.com/products/so lutions/security /default.aspx
programming flash devices 11-4 v1.2 programming features for actel devices actel provides two types of fpgas: flash and antifuse ( table 11-2 ). some progra mming methods are common to both and some are exclusive to flash. this document describes only the programming soluti ons supported for flash devices. flash devices the flash devices su pplied by actel are reprog rammable by either a generic device programmer or isp. actel supports isp using jtag, which is supporte d by the flashpro3, flas hpro, flashpro lite, and sculptor programmers. levels of isp support vary de pending on the device chosen: ? all fusion, igloo, and proasic3 devices support isp. ? proasic3l devices operate using a 1.2 v core voltage and support isp at 1.5 v only. voltage switching is required in-system to switch from a 1.2 v core to 1.5 v core for programming. ? igloo, iglooe, and igloo plus v5 devices can be programmed in-system when the device is using a 1.5 v supply voltage to the fpga core. ? igloo, iglooe, and igloo plus v2 devices ca n operate using either 1.2 v core voltage or 1.5 v core voltage. alth ough the device can operate at 1. 2 v core voltage, the device can only be reprogrammed when the core voltage is 1.5 v. voltage switching is required in- system to switch from a 1.2 v supply (v cc , v cci , and v jtag ) to 1.5 v for programming. since flash devices are nonvolatile, they are live at power-up. this is different from an sram-based device, which loads its programming information wh en it is powered up. sram devices require a time on the order of hundreds of mil liseconds before the system is active. there are multiple levels of securi ty available in flash devices. us e of a security key will lock the device. the device can then only be reprogra mmed by first unlocking the device with the appropriate security key. it can also be locked permanently, whic h means there is no key that can access the device. the command to secure the device is embedded within the programming file, optionally enabled by the programming software. this is also referred to as the otp version of flash, allowing for only a single programming insta nce. this is discussed in more detail in the implementation of security in actel's proasic and proasic plus flash-based fpgas application note, and in the security in low-power flash devices handbook section. flash devices can also be progra mmed using single-sit e or multi-site programmers as well as volume-programming services from actel or other vendors. table 11-2 ? programming features for actel devices feature flash antifuse reprogrammable yes no in-system programmable yes no one-time programmable yes (option) yes live at power-up yes yes secure yes yes single-site programmer support yes yes multi-site programmer support yes yes in-house programming support yes yes
programming flash devices v1.2 11-5 types of programming for flash devices the number of devices to be programmed will influence the optimal programming methodology. those available are listed below: ? in-system programming ? using a programmer ? using a microprocesso r or microcontroller ? device programmers ? single-site programmers ? multi-site programmers, batch prog rammers, or gang programmers ? automated production (robotic) programmers ? volume programming services ? actel in-house programming ? programming centers in-system programming device type supported: flash isp refers to programming the fpga after it has been mounted on the syste m board. the fpga may be preprogrammed and later reprogrammed using isp. the advantage of using isp is the ability to update the fpga design many times without any changes to the board. th is eliminates the require ment of using a socket for the fpga, saving cost and improving reliability. it also reduces progra mming hardware expenses, as the isp methodology is die-/packag e-independent. there are two methods of in-system programming: external and internal. ? programmer isp?refer to in-system programming (isp) of actel?s low-power flash devices using flashpro3 for more information. using an external programmer and a cable, the device can be programmed through a header on the system boar d. in actel documentation, this is referred to as external isp. actel provides flashpro3, flashpro lite, flashpro, or silicon sculptor 3 to perform external isp. note that silicon sculptor ii and silicon sculptor 3 can only provide isp for proasic and proasic plus ? families, not for fusion , igloo, or proasic3. ? advantages: allows local control of progra mming and data files for maximum security. the programming algorithms and hardware ar e available from actel. the only hardware required on the board is a programming header. ? limitations: a negligible board space re quirement for the prog ramming header and jtag signal routing ? microprocessor isp?refer to microprocessor programming of actel?s low-power flash devices for more information. using a microprocessor and an external or internal memory, you can store the program in memory and use the microprocessor to perfo rm the programming. in actel documentation, this is referred to as internal isp. both the code for the progra mming algorithm and the fpga programming file must be stored in me mory on the board. programming voltages must also be generated on the board. ? advantages: the programming code is st ored in the system memory. an external programmer is not required during programming. ? limitations: this is the approach that requ ires the most design work, since some way of getting and/or storing the data is needed; a system interface to the device must be designed; and the low-level api to the pr ogramming firmware must be written and linked into the code provided by actel. wh ile there are benefits to this methodology, serious thought and planning should go into the decision.
programming flash devices 11-6 v1.2 device programmers device type supported: flash and antifuse device programmers are used to program a device before it is mounted on the system board. the advantage of using device pr ogrammers is that no programming hardware is required on the system board. therefore, no additional components or board space are required. if devices are to be reprogrammed multiple times, or if the quantity of devices to be programmed is relatively low, a single-site device programmer is the simplest so lution. for applications in which design security is paramount (often the case in military or space desi gns), the use of on-site programing maintains design security at all times. adapter modules are purc hased with the programmers to supp ort the fpga packages used. the fpga is placed in the adapter module and the programming software is run from a pc. actel supplies the programm ing software for all of the actel prog rammers. the softwa re allows for the selection of the correct die/pack age and programming files. it wi ll then program and verify the device. ? single-site programmers a single-site programmer programs one device at a time. actel offers silicon sculptor 3 as a single-site programmer. ? advantages: lower cost than multi-site programmers. no additional overhead for programming on the system board. allows lo cal control of programming and data files for maximum security. allows on-demand programming on-site. ? limitations: only programs one device at a time. ? multi-site programmers often referred to as batch or gang prog rammers, multi-site programmers can program multiple devices at the same time using the sa me programming file. this is often used for large volume programming and by programming houses. the sites of ten have independent processors and memory enabling the sites to operat e concurrently, meaning each site may start programming the same file independently. this enables the operator to change one device while the other sites continue programming, which increases throughput. multiple adapter modules for the same package are required when us ing a multi-site programmer. silicon sculptor i, ii, and 3 pr ogrammers can be cascaded to program multiple devices in a chain. multi-site programmers can also be purchased from bp microsystems. ? advantages: provides the capability of prog ramming multiple devices at the same time. no additional overhead for programming on the system board. allows local control of programming and data files for maximum security. ? limitations: more expensive than a single-site programmer ? automated production (robotic) programmers automated production programmers are based on multi-site programmers. they consist of a large input tray holding multiple parts and a robotic arm to select and place parts into appropriate programming socke ts automatically. when the programming of the parts is complete, the parts are remove d and placed in a finished tray. the automated programmers are often used in volume programming houses to program parts for which the programming time is small.
programming flash devices v1.2 11-7 volume programming services device type supported: flash and antifuse once the design is stable for ap plications with large production volumes, preprogrammed devices can be purchased. table 11-3 describes the volume programming services. advantages: as programming is outs ourced, this solution is easier to implement th an creating a substantial in-house programming capability. as programming hous es specialize in large-volume programming, this is often th e most cost-effective solution. limitations: there are some logistical issues with the use of a programming service provider, such as the transfer of programming files and the approval of first articl es. by definition, the programming file must be released to a third-party progra mming house. nondisclos ure agreements (ndas) can be signed to help ensure data protection; however, for extremel y security-conscious designs, this may not be an option. ? actel in-house programming when purchasing actel devices in volume, ihp can be requested as part of the purchase. if this option is chosen, there is a small cost adder for each device programmed. each device is marked with a special mark to distinguish it from blank parts. prog ramming files for the design will be sent to actel. sample parts wi th the design programmed , first articles, will be returned for customer approval. once approval of first articles has been received, actel will proceed with programming the remainder of th e order. to request actel ihp, contact your local actel representative. ? distributor programming centers if purchases are made through a distributor, many distributors will provide programming for their customers. cons ult with your preferred dis tributor about this option. ? independent programming centers there are many programming centers that sp ecialize only in programming but are not directly affiliated with actel or our distributo rs. these programming centers must follow the guidelines for programming ac tel devices and use certified programmers to program actel devices. actel does not have recommendat ions for external programming centers. table 11-3 ? volume programming services programmer vendor availability in-house programming actel contact actel sales distributor programming centers me mec unique contact distribution independent programming centers various contact vendor
programming flash devices 11-8 v1.2 programming solutions details for the available programmers can be found in the programmer user's guides listed in the "related documents" section on page 11-14 . refer to table 11-6 on page 11-10 for more information concerning programming solutions. all of the programmers except the flashpro3, flas hpro lite, and flashpro require adapter modules, which are designed to support device packages. the modules are all listed on the actel website at http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . they are not listed in this document, sinc e this list is updated frequently with new package options and any upgrades required to improve programming yield or support new families. programmer ordering codes the products shown in table 11-5 can be ordered through actel sales and will be shipped directly from actel. products can also be or dered from actel distributors, bu t will still be shipped directly from actel. table 11-5 includes ordering codes for the full kit, as well as codes for replacement items and any related hardware. some additi onal products can be purchased from external suppliers for use with the prog rammers. ordering codes for ad apter modules used with silicon sculptor are available on the actel website at http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . table 11-4 ? programming solutions programmer vendor isp single device multi-device availability flashpro3 actel only yes yes 1 available flashpro lite actel only yes yes 1 available flashpro actel only yes yes 1 available silicon sculptor 3 actel yes 2 yes cascade option (up to two) available silicon sculptor ii actel yes 2 yes cascade option (up to two) available silicon sculptor actel yes yes cascade option (up to four) discontinued sculptor 6x actel no yes yes discontinued bp microprogrammers bp microsystems no yes yes contact bp microsystems at www.bpmicro.com notes: 1. multiple devices can be connected in the same jtag chain for programming. 2. silicon sculptor ii and silicon sculptor 3 can only provide isp for proasic and proasic plus families, not for fusion, igloo, or proasic3 devices. table 11-5 ? programming ordering codes description vendor ordering code comment flashpro3 isp programmer actel flashpro 3 uses a 2x5, ra male header connector flashpro lite isp programmer actel flashpro lite supports small pr ogramming header or large header through header converter (not included) flashpro isp programmer actel flash pro supports small prog ramming header or large header through header converter (not included) silicon sculptor 3 actel silicon-sculptor 3 usb 2.0 high-speed production programmer silicon sculptor ii actel silicon-sculptor ii requires add-on adapter modules to support devices silicon sculptor isp module actel smpa-isp-actel-3-kit ships with both large and small header support * a maximum of two silicon sculptor ii programmers can be chained together using a standard ieee 1284 parallel port cable.
programming flash devices v1.2 11-9 concurrent programming cable actel ss-expander used to cascad e silicon sculptor i programmers together* software for silicon sculptor actel sculptor-software-cd http://www.actel.com/download/program_debug/ss/ isp cable for small header actel isp-cable-s supplied with smpa-isp-actel-3-kit isp cable for large header actel pa-isp-cable supplied with smpa-isp-actel-3-kit header converter actel header-converter converts from small to large header small programming header samtec ftsh-113-01-l-d-k supported by flashpro, flashpro lite, and silicon sculptor in migrating to proasic3 /e devices, an fp3-26pin- adapter is required. 10-pin 0.1" pitch cable header (right- angle pcb mount angle) amp 103310-1 supported by flashpro3 10-pin 0.1" pitch cable header (straight pcb mount angle) 3m 2510-6002ub supported by flashpro3 compact programming header (10-pin 0.05" pitch, 2 rows of 5 pins) samtec ftsh-105-01-l-d-k supported by flashpro3, fp3-26pin-adapter required. used for boards where space is at a premium. migration and compact header adapter actel fp3-26pin-adapter required with the use of ftsh-105-01-l-d-k large programming header 0.062" board thickness 3m 3429-6502 supported by silicon sc ulptor by default, flashpro, and flashpro lite, with header converter large programming header 0.094" to 0.125" board thickness 3m 3429-6503 supported by silicon sc ulptor by default, flashpro, and flashpro lite, with header converter plug-in header small actel smpa-isp-header-s requi red for small header fo r proasic only; not used for proasic plus plug-in header actel smpa-isp-header required for large header for proasic only; not used for proasic plus vacuum pens for pq, tq, vq; <208 pins actel penvac vacuum pens for pq, tq, vq; 208 pins actel penvac-hd heavy-duty, provides stronger vacuum table 11-5 ? programming ordering codes (continued) description vendor ordering code comment * a maximum of two silicon sculptor ii programmers can be chained together using a standard ieee 1284 parallel port cable.
programming flash devices 11-10 v1.2 programmer device support refer to table 11-6 to determine which general-purpose flash devices have programmer device support. to learn more about the different actel families, refer to the actel website: http://www.actel.com/products/devices.aspx. data in table 11-6 also applies to arm-enabled m7 device versions of fusion, igloo, and proasic3 devices. refer to the appropriate family data sheets for information on die/package combinations available as arm- enabled versions. table 11-6 ? programmer device support actel family device arm- enabled silicon sculptor silicon sculptor 6x silicon sculptor ii silicon sculptor 3flashpro flashpro lite flashpro3 fusion afs090 no no yes. no isp support. yes. no isp support. no no yes. isp support afs250 afs600 ? afs1500 ? igloo agl015 no no yes. no isp support. yes. no isp support. no no yes. isp support. agl030 agl060 agl125 agl250 ? agl600 ? agl1000 ? iglooe agle600 agle3000 ? no no yes. no isp support yes. no isp support. no no yes. isp support ? igloo plus aglp030 no no yes. no isp support yes. no isp support. no no yes. isp support aglp060 aglp125 proasic3l a3p250l ? no no yes. no isp support. yes. no isp support. no no yes. isp support. a3p600l ? a3p1000l ? a3pe3000l ? proasic3 a3p015 no no yes. no isp support. yes. no isp support. no no yes. isp support. a3p030 a3p060 a3p125 a3p250 ? a3p400 ? a3p600 ? a3p1000 ? proasic3e a3pe600 ? no no yes. no isp support. yes. no isp support. no no yes. isp support. a3pe1500 ? a3pe3000 ? * refer to the "certified programming solutions" section on page 11-11 for more information on programmer support.
programming flash devices v1.2 11-11 certified programming solutions the actel-certified programmers fo r flash devices are flashpro3, flashpro lite, flashpro, silicon sculptor i and ii, and any programmer that is buil t by bp microsystems. all other programmers are considered noncertified programmers. ? flashpro3, flashpro lite, flashpro the actel family of flashpro device progra mmers provides in-system programming in an easy-to-use, compact system that supports all flash families. whether programming a board containing a single device or multiple devices connected in a chain, the actel line of flashpro programmers enables fast programming an d reprogramming. programming with the flashpro series of programmers saves board sp ace and money as it eliminates the need for sockets on the board. there are no built-in al gorithms, so there is no delay between product release and programming support. ? silicon sculptor ii silicon sculptor ii is a robu st, compact, single-d evice programmer with standalone software for the pc. it is designed to enable concurrent programming of multiple units from the same pc with speeds equivalent to or faster than previous actel programmer s. it replaces silicon sculptor i as the actel programmer of choice. ? silicon sculptor i and silicon sculptor 6x actel no longer offers silicon sculptor i or silicon sculptor 6x for sale. both items have been discontinued. actel does support silicon sculptor i and silicon sculptor 6x by continuing to release new software that enables improved programming of previously covered actel devices; new actel devices are only supported on silicon sculptor ii. all software support for silicon sculptor i and silicon sculptor 6x pr ogrammers will be disconnected by the end of 2005; no support for these older programmers will be offered in 2006. actel recommends that all customers upgrade to silicon scul ptor ii or a bp multi-site programmer. ? noncertified programmers actel does not test programmi ng solutions from other vendors, and cannot guarantee programming yield. also, actel will not perform any failure analysis on devices programmed by hardware from other vendors. ? programming centers actel programming hardware policy also applie s to programming centers. actel expects all programming centers to use certified prog rammers to program actel devices. if a programming center uses noncertified pr ogrammers to program actel devices, the " noncertified programmers " policy applies. proasic plus apa075 yes. isp support. yes. isp support. yes. isp support. yes. isp support. yes. isp support. yes. isp support. no apa150 apa300 apa450 apa600 apa750 apa1000 proasic a500k50 yes yes yes yes yes no no a500k130 a500k180 a500k270 table 11-6 ? programmer device su pport (continued) actel family device arm- enabled silicon sculptor silicon sculptor 6x silicon sculptor ii silicon sculptor 3flashpro flashpro lite flashpro3 * refer to the "certified programming solutions" section on page 11-11 for more information on programmer support.
programming flash devices 11-12 v1.2 flash programming guidelines preprogramming setup before programming, several steps are requir ed to ensure an optimal programming yield. use proper handling and electrosta tic discharge (esd) precautions actel fpgas are sensitive electronic devices that are susceptible to damage from esd and other types of mishandling. for more in formation about esd, refer to the actel quality and reliability guide, beginning with page 41. use the latest version of the de signer software to generate your programming file (recommended) the files used to program actel fl ash devices (*.bit, *.stp) contai n important information about the switches that will be programme d in the fpga. find the latest ve rsion and corresponding release notes at http://www.actel.com/download/software/designer/ . also, programming files must always be zipped during file transfer to av oid the possibility of file corruption. use the latest version of the programming software the programming software is frequently updated to accommodate yield enhancements in fpga manufacturing. these updates ensure maximu m programming yield and minimum programming times. before progra mming, always check the ve rsion of software being used to ensure it is the most recent. depending on the programming software, refer to one of the following: ?flashpro: http://www.actel.com/download/program_debug/flashpro/ ? silicon sculptor: http://www.actel.com/download/program_debug/ss/ use the most recent adapter m odule with silicon sculptor occasionally, actel make s modifications to the adapter modules to impr ove programming yields and programming times. to identi fy the latest version of each mo dule before programming, visit http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . perform routine hardware self-diagnostic test ?flashpro the self-test is only appl icable when programming wi th flashpro and flashpro3 programmers. it is not supported with flashpro lite. to run the self-diagn ostic test, follow the instructions given in the "performing a self-test" section of http://www.actel.com/documents/flashpro_ug.pdf . ? silicon sculptor the self-diagnostic test verifi es correct operation of the pin drivers, power supply, cpu, memory, and adapter module. this test shou ld be performed before every programming session. at minimum, the te st must be executed every week . to perform self-diagnostic testing using the silicon sculptor software, perform the following steps, depending on the operating system: ? dos: from anywhere in the software, type alt + d . ? windows: click device > choose actel diagnostic > select the te s t tab > click ok . programming flash fpgas programming a flash device is a one-step proces s, whether programming is conducted with a socket adapter module or via isp. the execute func tion will automatically erase the device, program the flash cells, and verify that it is programmed correctly. actel recommend s confirming the security status is correct before programming. the following steps ar e required to program actel flash fpgas.
programming flash devices v1.2 11-13 programming with flashpro setup properly connect the flashpro ribbon cable with the programming header an d turn on the switch. actel recommends running the self-test be fore programming any devices; see the "perform routine hardware self-diagno stic test" section on page 11-12 . in the programming software, from the file menu, choose connect . in the flashpro connect to programmer dialog box that appears, select the port to which the fl ashpro programmer is connected, and select the device family. disable voltages from the programmer if they are available on the board. click connect . a successful connect or any erro rs appear in the log window. analyze chain and device selection from the file menu, choose analyze chain . chain details appear in the log window. if any failures appear, refer to the error and troubleshooting section of the flashpro user's guide . select the device to be programmed from the device list. if only one device is present in the chain, performing analyze chain sele cts that device automati cally from the device list. loading the stapl file flashpro3, flashpro lite , and flashpro programmers use a stapl (*.stp) file to program the device. to load the stapl file, fro m the file menu, choose open stapl file , or click the open file button in the toolbar. selecting an action after loading the stapl file, sele ct an action from the action list. see the "programming file actions" section in the flashpro user's guide for a definition of each action. programming the device to program the device, in the action li st, select program . make the required selections and click execute to start programming. the progress of th e programming action displays in the log window. the message "exit 0" indicates that the device has successfully been programmed. note: do not interrupt the programming sequence; it may damage the device or programmer. verify correct programming to verify the device is programmed with the corre ct stapl file, load the stapl file and in the action list and click verify . click execute to start the verification proc ess. a successful verification results in "exit 0." note: verification is also performed in the previous "programming the device" step; clicking verify is an additional standalone option. programming failure allowances flash fpgas are reprogrammable, so ac tel tests the programmability for 100 % of the devices shipped. return material authorization (rma) policies actel consistently strives to exceed customer expe ctations by continuing to improve the quality of our products and our quality management system. actel has rma procedures in place to address programming fallout. customers should be mindful of the following rma policies. all devices submitted for an rma, must be within the actel warranty period of one year from date of shipment. actel will reject rmas for devices that are no longer under warranty. rmas will only be authorized fo r current actel devices. devices th at have been discontinued will not receive rmas. all functional failure analysis requests must be initiated by opening a case with actel technical support. devices returned for fail ure analysis against an rma should be in their original packaging and must have an rma number issued by actel.
programming flash devices 11-14 v1.2 contacting the cust omer support group highly skilled engineers staff the cu stomer applications center from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. you can contact the center by one of the following methods: electronic mail you can communicate your technical questions to our email address and receive answers back by email, fax, or phone. also, if you have design pr oblems, you can email your design files to receive assistance. actel monitors the emai l account throughout the day. when sending your request to us, please be sure to incl ude your full name, company name, an d contact information for efficient processing of your request. the technical support email address is tech@actel.com . telephone our technical support hotline answ ers all calls. the center retriev es information, such as your name, company name, telephone nu mber, and question. once this is done, a case number is assigned. then the center forwards the info rmation to a queue wh ere the first available applications engineer receives the data and returns your call. the phone hours are from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. the customer applications cent er number is (800) 262-1060. european customers can call +44 (0) 1256 305 600. related documents below is a list of related documents, their loca tion on the actel website, and a brief summary of each document. application notes programming antifuse devices http://www.actel.com/documen ts/antifuseprogram_an.pdf implementation of security in actel's proasic and proasic plus flash-based fpgas http://www.actel.com/documents/flash_security_an.pdf handbook documents security in low-pow er flash devices http://www.actel.com/docum ents/lpd_secu rity_hbs.pdf in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 http://www.actel.com/documents/lpd_isp_hbs.pdf microprocessor programming of actel?s low-power flash devices http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf user?s guides flashpro programmers flashpro3, flashpro lite, and flashpro http://www.actel.com/products/hardware /program_debug/flashpro/default.aspx flashpro user's guide http://www.actel.com/documents/flashpro_ug.pdf the flashpro user?s guide incl udes hardware and software setup, self-test instructions, use instructions, and a troubleshooting / error message guide.
programming flash devices v1.2 11-15 silicon sculptor 3 and silicon sculptor ii http://www.actel.com/products/hardwa re/program_debug/ss/default.aspx other documents http://www.actel.com/products/solution s/security/default.aspx#flashlock the security resource center descri bes security in actel flash fpgas. actel quality and reliability guide http://www.actel.com/documents/relguide.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-013-2 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.2) page v1.1 (march 2008) the "programming support in flash devices" section was revised to include new families and make the information more concise. 11-2 figure 11-1 flashpro programming setup and the "programming support in flash devices" section are new. 11-1 , 11-2 table 11-6 programmer device support was updated to include a3pe600l with the other pro asic3l devices, an d the rt proasic3 family was added. 11-10 v1.0 (january 2008) the "flash devices" section was updated to include the igloo plus family. the text, "voltage switching is required in-system to switch from a 1.2 v core to 1.5 v core for programming" was revised to state, "although the device can operate at 1.2 v core voltage, the devi ce can only be reprogrammed when the core voltage is 1.5 v. voltage switching is required in-system to switch from a 1.2 v supply (v cc , v cci , and v jtag ) to 1.5 v for programming." 11-4 the proasic3l family was added to table 11-6 programmer device support as a separate set of rows rather than combined with proasic3 and proasic3e devices. the igloo plus family wa s included, and agl015 and a3p015 were added. 11-10

v1.3 12-1 12 ? security in low-power flash devices security in programmable logic the need for security on fpga programmable lo gic devices (plds) has never been greater than today. if the contents of the fpga can be read by an external source, the in tellectual property (ip) of the system is vulnerable to un authorized copying. actel fusion, ? igloo, ? and proasic ? 3 devices contain state-of-the-art ci rcuitry to make the flash-based devices secure during and after programming. low-power flash devices have a built-in 128-bit advanced encryption standard (aes) decryption core (except for 15 k and 30 k gate devi ces). the decryption core facilitates secure in- system programming (isp) of the fpga core ar ray fabric, the flashrom , and the flash memory blocks (fbs) in fusion devices. the flashr om, flash blocks, and fp ga core fabric can be programmed independently of each other, allowi ng the flashrom or flash blocks to be updated without the need for change to the fpga core fabric. actel has incorporated the aes decryption core into the low- power flash devices and has also included the actel flash-based lock technology, flashlock. ? together, they provide leading-edge security in a programmable logic device. configurat ion data loaded into a device can be decrypted prior to being written to the fpga core using the aes 128-bit block cipher standard. the aes encryption key is stored in on-chip, nonvolatile flash memory. this document outlines th e security features offered in low-pow er flash devices, some applications and uses, as well as the different so ftware settings for each application. figure 12-1 ? overview on security
security in low-pow er flash devices 12-2 v1.3 security support in low-power devices the low-power flash families listed in table 12-1 support the security f eature and th e functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 12-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 12-1 . where the information applies to on ly one family or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 12-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
security in low-pow er flash devices v1.3 12-3 security architecture fusion, igloo, and proasic3 devices have b een designed with the most comprehensive programming logic design se curity in the industry. in the architec ture of these devices, security has been designed into the very fabric. the flash cells are located beneath seven metal layers, and the use of many device design and layout techniques makes invasive attacks difficult. since device layers cannot be removed withou t disturbing the char ge on the programmed (or erased) flash gates, devices cannot be easily deconstructed to decode the design. low-power flash devices are unique in being reprogrammable and having inhere nt resistance to both in vasive and noninvasive attacks on valuable ip. secure, remote isp is now possible with aes encryp tion capability for the programming file during electronic transfer. figure 12-2 shows a view of th e aes decryption core inside an igloo device; figure 12-3 on page 12-4 shows the aes decryption core inside a fusion device. the aes core is used to decrypt the encrypted programming f ile when programming. note: isp aes decryption is not supported by 15 k and 30 k gate devices. for details of other architecture features by device, refer to the appropriate family datasheet. figure 12-2 ? block representation of th e aes decryption core in igloo and proasic3 devices flash*freeze technology charge pumps user nonvolatile flashrom isp aes decryption* ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2
security in low-pow er flash devices 12-4 v1.3 security features igloo and proasic3 devices have two entities in side: flashrom and the fpga core fabric. fusion devices contain three entities: flashrom, fb s, and the fpga core fabric. the parts can be programmed or updated independently with a stapl programming file. the programming files can be aes-encrypted or plaintext. this allows maximum flexibilit y in providing security to the entire device. refer to flashrom in actel?s lo w-power flash devices for information on the flashrom structure. unlike sram-based fpga devices, which require a separate bo ot prom to store programming data, low-power flash devices are nonvolatile, and the secured configuration data is stored in on- chip flash cells that are part of the fpga fabric. once programmed, th is data is an inherent part of the fpga array and does not need to be loaded at system power- up. sram-based fpgas load the configuration bitstream upon power-up; therefore, the configuration is exposed and can be read easily. the built-in fpga core, fb, and flashrom support programming f iles encrypted with the 128-bit aes (fips-192) block ciphers. the aes key is stored in dedicated, on-chip flash memory and can be programmed before the device is shipped to other parties (allowin g secure remote field updates). security in arm-enabled low-power flash devices there are slight differences between the regular flash devices and the arm ? -enabled flash devices, which have the m1 and m7 prefix. the aes key is used by actel and preprogrammed into the device to protect the arm ip. as a result, the design is encrypted along with the arm ip, according to the details below. figure 12-3 ? block representation of the aes decr yption core in a fusion afs600 fpga versatile ccc ccc i/os osc ccc/pll bank 0 bank 4 bank 2 bank 1 bank 3 sram block 4,608-bit dual-port sram or fifo block sram block 4,608-bit dual-port sram or fifo block flash memory blocks flash memory blocks adc analog quad isp aes decryption user nonvolatile flashrom charge pumps analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad
security in low-pow er flash devices v1.3 12-5 coremp7 device security arm7 (m7-enabled) devices are shipped with the following security features: ? fpga array enabled for aes-encryp ted programming and verification ? flashrom enabled for plaintext read and write cortex-m1 device security cortex-m1?enabled devices are shipped wi th the following security features: ? fpga array enabled for aes-encryp ted programming and verification ? flashrom enabled for aes-encrypted write and verify ? fusion embedded flash memory enabled for aes- encrypted write aes encryption of programming files low-power flash devices employ aes as part of th e security mechanism that prevents invasive and noninvasive attacks. the mechanism entails encrypting the pr ogramming file with aes encryption and then passing the programming file through the aes de cryption core, which is embedded in the device. the file is decrypted there, and the devi ce is successfully programmed. the aes master key is stored in on-chip nonvolatile memory (flash). the aes master key can be preloaded into parts in a secure programming environment (such as the actel in-house programming center), and then "blank" parts can be shipped to an untrusted pr ogramming or manufactur ing center for final personalization with an aes-encrypted bitstream. late-stage product changes or personalization can be implemented easily and securely by simply sending a stapl file wi th aes-encrypted data. secure remote field updates over public networks (such as the inte rnet) are possible by sending and programming a stapl file with aes-encrypted data. the aes key protects the programming data for f ile transfer into the device, with 128-bit aes encryption. if aes encryption is used, the aes key is stored or preprogrammed into the device. to program, you must use an aes-en crypted file, and the encryption used on the file must match the encryption key alr eady in the device. the aes key is protected by a flashlock security pas s key that is also impl emented in each device. the aes key is always protected by the flashlock key, and the aes-encrypted file does not contain the flashlock key. this flashlock pass key techno logy is exclusive to the actel flash-based device families. flashlock pass key technology can al so be implemented with out the aes encryption option, providing a choice of different security levels. in essence, security featur es can be categorized into the following three options: ? aes encryption with fl ashlock pass key protection ? flashlock protection only (no aes encryption) ? no protection each of the above options is explained in more detail in the following sections with application examples and software im plementation options. advanced encr yption standard the 128-bit aes standard (fips-192) block cipher is the nist (national insti tute of standards and technology) replacement for des (data encryption standard fips46-2). aes has been designed to protect sensitive government info rmation well into the 21st centur y. it replaces the aging des, which nist adopted in 1977 as a federal information processing standard used by federal agencies to protect sensitive, unclassified inform ation. the 128-bit ae s standard has 3.4 10 38 possible 128-bit key variants, and it has been estimated th at it would take 1,000 trillion years to crack 128-bit aes cipher text using exha ustive techniques. keys are store d (securely) in low-power flash devices in nonvolatile flash memory . all programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. all programming verifi cation is performed on-chi p, ensuring that the contents of low-power flash devices remain secure. actel has implemented the 128-bit aes (rijndael) algorithm in low-p ower flash devices. with this key size, there are approximately 3.4 10 38 possible 128-bit keys. des has a 56-bit key size, which provides approximately 7.2 10 16 possible keys. in their aes fact sheet, the nati onal institute of
security in low-pow er flash devices 12-6 v1.3 standards and technology uses the following hypo thetical example to illustrate the theoretical security provided by aes. if one were to assume that a computing system ex isted that could recover a des key in a second, it would take that same ma chine approximately 149 trillion years to crack a 128-bit aes key. nist continues to make their point by stating the universe is believed to be less than 20 billion years old. 1 the aes key is securely stored on-chip in dedi cated low-power flash device flash memory and cannot be read out. in the first step, the aes key is generated and programmed into the device (for example, at a secure or trusted programming site). the actel designer soft ware tool provides aes key generation capability. after the key has been programmed into the device, the device will only correctly decrypt programming files that have been encrypted with the same key. if the individual programming file content is incorrect, a messag e authentication contro l (mac) mechanism inside the device will fail in authenti cating the programming file. in other words, when an encrypted programming file is being loaded into a device that has a different programmed aes key, the mac will prevent this incorrect data from being lo aded, preventing possible device damage. see figure 12-3 on page 12-4 and figure 12-4 on page 12-7 for graphical repr esentations of this process. it is important to note that the user decides what level of protec tion will be implemented for the device. when aes protection is desired, the fl ashlock pass key must be set. the aes key is a content protection mechanism, whereas the flashl ock pass key is a device protection mechanism. when the aes key is programmed into the device, th e device still needs the pass key to protect the fpga and flashrom contents and the security setti ngs, including the aes key. using the flashlock pass key prevents modification of the design contents by means of simply programming the device with a different aes key. aes decryption and mac authentication low-power flash devices have a built-in 128-bit aes decryption core, whic h decrypts the encrypted programming file and performs a mac check that authenticates the file prior to programming. mac authenticates the entire pr ogramming data stream. after aes decryption, the mac checks the data to make sure it is valid programming data for the device. this can be done while the device is still operating. if th e mac validates the file, the device will be erased and programmed. if the mac fails to validate, th en the device will continue to operate uninterrupted. this will ensure the following: ? correct decryption of th e encrypted programming file ? prevention of erroneous or corrupted data being programmed during the programming file transfer ? correct bitstream passed to the device for decryption 1. national institute of standards and technology, ?advanced encryption standard (aes) questions and answers,? 28 january 2002, (10 january 2005).see http://csrc.nist.gov/archive/aes/index1.html for more information.
security in low-pow er flash devices v1.3 12-7 flashlock additional options for iglo o and proasic3 devices the user also has the option of prohibiting write operations to the fpga array but allowing verify operations on the fpga array and/or read oper ations on the flashrom without the use of the flashlock pass key. this option provides the user the freedom of verifying the fpga array and/or reading the flashrom contents after the device is programmed, without having to provide the flashlock pass key. the user can incorporate aes encryption on the prog ramming files to better enhance the level of security used. figure 12-4 ? example application scen ario using aes in igloo and proasic3 devices figure 12-5 ? example application scenario using aes in fusion devices actel designer software programming file generation with aes encryption igloo and proasic3 decrypted bitstream mac validation aes decryptioncore transmit medium / public network encrypted bistream flashrom aes key fpga core actel designer software programming file generation with aes encryption fusion decrypted bitstream mac validation aes decryptioncore transmit medium / public network encrypted bistream flashrom aes key fpga core fbs
security in low-pow er flash devices 12-8 v1.3 permanent security setting options in applications where a permanent lock is not desired, yet the security settings should not be modifiable, igloo and proasic3 device s can accommodate th is requirement. this application is partic ularly useful in cases where a device is located at a remote location and must be reprogrammed with a design or data update. refer to the "application 3: nontrusted environment?field updates/upgrades" section on page 12-10 for further discus sion and examples of how this can be achieved. the user must be careful when considering the permanent flashlock or permanent security settings option. once the design is programmed wi th the permanent settings, it is not possible to reconfigure the security settings already employed on the device . therefore, exercise careful consideration before prog ramming permanent settings. permanent flashlock the purpose of the permanent lock feature is to provide the benefits of the highest level of security to igloo and proasic3 devices. if sele cted, the permanent flashlock feature will create a permanent barrier, preventing an y access to the contents of th e device. this is achieved by permanently disabling write and ve rify access to the array, and write and read access to the flashrom. after permanently lock ing the device, it has been ef fectively rendered one-time- programmable. this feature is usef ul if the intended applications do not require design or system updates to the device.
security in low-pow er flash devices v1.3 12-9 security in action this section illustrates some applications of the security advantages of actel?s devices ( figure 12-6 ). application 1: trusted environment as illustrated in figure 12-7 on page 12-10 , this application allows th e programming of devices at design locations where research and developmen t take place. therefore, encryption is not necessary and is optional to the user. this is of ten a secure way to prot ect the design, since the design program files are not sent elsewhere. in situations where production programming is not available at the design location, programming centers (suc h as actel in-house programming) provide a way of programming designs at an al ternative, secure, and trusted location. in this scenario, the user generates a st apl programming file from the de signer software in plaintext format, containing information on the entire design or the portion of the design to be programmed. the user can choose to employ the flashlock pass key feature with the design. once the design is programmed to unprogrammed devices, the design is protected by this flashlock pass key. if no future programming is needed, the us er can consider permanen tly securing the igloo and proasic3 device, as discussed in the "permanent flashlock" section on page 12-8 . application 2: nontrusted en vironment?unsecured location often, programming of devices is not performe d in the same location as actual design implementation, to redu ce manufacturing cost. overseas programming centers and contract manufacturers are examples of this scenario. to achieve security in this case, the aes key and the flashlock pass key can be initially programmed in-house (trusted environment). this is done by generating a programming file with only the security settings and no design contents. the de sign fpga core, flashrom, and (for fusion) fb contents are generated in a separate programming file. this programming fi le must be set with the same aes key that was used to prog ram to the device previously so the device will correctly decrypt this encrypted programming file. as a result, th e encrypted design content programming file can note: flash blocks are only used in fusion devices. figure 12-6 ? security options plaintext source file aes encryption cipher text source file public domain aes decryption core flashrom flash blocks flash device application 3 application 2 application 1 fpga core
security in low-pow er flash devices 12-10 v1.3 be safely sent off-site to nontrusted pr ogramming locations for design programming. figure 12-7 shows a more detailed fl ow for this application. application 3: nontrusted environment?field updates/upgrades programming or reprogramming of devices may occur at remote locations. reconfiguration of devices in consumer products/equipment through public networks is one example. typically, the remote system is already programmed with particul ar design contents. when design update (fpga array contents update) and/or data upgrade (fla shrom and/or fb contents upgrade) is necessary, an updated programming file with aes encryption can be generated, sent across public networks, and transmitted to the remote system. reprogramm ing can then be done using this aes-encrypted programming file, providing easy and secure field upgrades. low-power flash devices support this secure isp using aes. the detailed flow for this application is shown in figure 12-8 on page 12-11 . refer to microprocessor programming of actel?s low-power flash devices for more information. to prepare devices for this scenar io, the user can initially genera te a programming file with the available security setting options. this programming file is programmed into the devices before shipment. during the prog ramming file generation step, the user has the option of making the security settings permanent or not. in situatio ns where no changes to the security settings are necessary, the user can select this feature in the software to generate the programming file with permanent security settings. actel recommends th at the programming file use encryption with an aes key, especially when isp is done via public domain. for example, if the designer wants to use an aes key for the fpga array and the flashrom, permanent needs to be chosen for this setting. at fi rst, the user would do this by choosing the options to use an aes key for the fpga array and the fl ashrom, and then choosing permanently lock the security settings . a unique aes key would be chosen. once this programming file is notes: 1. programmed portion indi cated with dark gray. 2. programming of fbs applies to fusion only figure 12-7 ? application 2: device programmin g in a nontrusted environment trusted environment nontrusted manufacturing environment flash device aes and/or pass key protected programming file fpga/flashrom/fbs contents security settings generates design contents encrypted with aes generates and programs security settings only (programming of the security keys) programs design contents to devices ships devices to manufacturer sends file(s) to manufacturer oem customers returns programmed devices to vendor ships programmed devices to end customer flash device flash device oem fpga/flashrom/fbs security settings* fpga/flashrom/fbs security settings
security in low-pow er flash devices v1.3 12-11 generated and programmed to the devices, the aes key is permanently stored in the on-chip memory, where it is secured safely. the devices wo uld be sent to distant locations for the intended application. wh en an update is needed, a new progra mming file must be generated. the programming file must use the same aes key for encryption; othe rwise, the authenti cation will fail and the file will not get programmed in the device. flashrom security use models each of the subsequent sections describes in detail the available selections in actel designer as an aid to understanding security ap plications and generating appropriate programming files for those applications. before proceeding, it is helpful to review figure 12-7 on page 12-10 , which gives a general overview of the programming file generati on flow within the desi gner software as well as what occurs during the device programming stage. specific settings are discussed in the following sections. in figure 12-7 on page 12-10 , the flow consists of two sub- flows. sub-flow 1 describes programming security settings to the device only, and sub-flow 2 describes programming the design contents only. in application 1, described in the "application 1: trusted environment" section on page 12-9 , the user does not need to generate separate files but can generate one programming file containing both security settings and design contents. then programming of the secu rity settings and design contents is done in one step. both sub-flow 1 and sub-flow 2 are used. in application 2, described in the "application 2: nontrusted envi ronment?unsecured location" section on page 12-9 , the trusted site should follow sub-fl ows 1 and 2 separately to generate two separate programming files. the programming file from sub-flow 1 will be used at the trusted site to program the device(s) first. the programming fi le from sub-flow 2 will be sent off-site for production programming. figure 12-8 ? application 3: nontrust ed environment?field updates/upgrades remote environment / system trusted environment generates updated design contents encrypted with aes original design contents aes encrypted and flashlock pass key protected oem aes encrypted programming file transmits to remote system update/upgrade flash device
security in low-pow er flash devices 12-12 v1.3 in application 3, described in the "application 3: nontrusted environment?field updates/upgrades" section on page 12-10 , typically only sub-flow 2 will be used because only updates to the design content portion are needed and no security settings need to be changed. in the event that update of the se curity settings is necessary, see the "reprogramming devices" section on page 12-21 for details. for more information on programming low-power flash devices, refer to in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 . note: if programming the security header only, just perform sub-flow 1. if programming design content on ly, just perform sub-flow 2. figure 12-9 ? security programming flows software generates programming file with desired security settings: ? encrypted with aes and protected with flashlock pass key ? protected with flashlock pass key only program design contents program security settings user 1 2 designer software programming software programming previously secured device(s)? yes no no software generates programming file with desired design contents (fpga array, flashrom, fb, or all) yes no device previously programmed? software performs comparison of flashlock pass key between programming file and device software performs comparison of flashlock pass key between programming file and device encrypted design content passes through mac for authentication software programs selected security settings into device no does flashlock pass key match? does flashlock pass key match? yes no returns error returns error yes correct? yes no aes key used previously? yes user assigns desired security settings to fpga/flashrom/fb/all: ? aes key and flashlock pass key ? flashlock pass key only user must reassign exact flashlock pass key previously programmed into the device user must reassign exact aes key previously programmed into the device software generates programming file with flashlock pass key and design contents design content programmed into device software generates programming file with encrypted design contents design content decrypted and programmed into device
security in low-pow er flash devices v1.3 12-13 generating programming files generation of the programming file in a trusted environment? application 1 as discussed in the "application 1: trusted environment" section on page 12-9 , in a trusted environment, the user can choose to program the device with pl aintext bitstream content. it is possible to use plaintext for programming even when the flashlock pass key option has been selected. in this application, it is not necessary to employ ae s encryption prot ection. for aes encryption settin gs, refer to the next sections. the generated programming file w ill include the security setting (if selected) and the plaintext programming file content for the fpga array, flas hrom, and/or fb. these options are indicated in table 12-2 and table 12-3 . for this scenario, generate th e programming file as follows: 1. select the silicon features to be programmed (security settings, fpga array, flashrom, flash memory block), as shown in figure 12-10 on page 12-14 and figure 12-11 on page 12-14 . click next . if security settings is selected (i.e., the flashlock secu rity pass key feature), an additional dialog will be displayed to prompt you to se lect the security level setting. if no security setting is selected, you wi ll be directed to step 3. table 12-2 ? igloo and proasic3 plaintext security options, no aes security protection flashrom only fpga core only both flashrom and fpga no aes / no flashlock ??? flashlock only ??? aes and flashlock ? ? ? table 12-3 ? fusion plaintext security options security protection flashrom only fpga core only fb core only all no aes / no flashlock ???? flashlock ???? aes and flashlock ? ? ? ? note: for all instructions, the programming of flash blocks refers to fusion only.
security in low-pow er flash devices 12-14 v1.3 figure 12-10 ? all silicon features checked fo r igloo and proasic3 devices figure 12-11 ? all silicon features checked for fusion
security in low-pow er flash devices v1.3 12-15 2. choose the appropriate security level setting and enter a flas hlock pass key. the default is the medium security level ( figure 12-12 ). click next . if you want to select different options for the fpga and/or flashrom, this can be set by clicking custom level . refer to the "advanced options" section on page 12-22 for different custom security level options and descriptions of each. figure 12-12 ? medium security level selected for low-power flash devices
security in low-pow er flash devices 12-16 v1.3 3. choose the desired settings for the flashrom configurations to be programmed ( figure 12-13 ). click finish to generate the stapl prog ramming file fo r the design. generation of security head er programming file only? application 2 as mentioned in the "application 2: nontrusted environm ent?unsecured location" section on page 12-9 , the designer may employ flashlock pass key protection or flashl ock pass key with aes encryption on the device before sending it to a nontrusted or unsecured location for device programming. to achieve this, th e user needs to generate a programming file containing only the security settings desired (secur ity header programming file). note: if aes encryption is configured, flashlock pa ss key protection must also be configured. the available security op tions are indicated in table 12-4 and table 12-5 on page 12-17 . figure 12-13 ? flashrom configuration setting s for low-power flash devices table 12-4 ? flashlock security option s for igloo and proasic3 security option flashrom only fpga core only both flashrom and fpga no aes / no flashlock ? ? ? flashlock only ??? aes and flashlock ???
security in low-pow er flash devices v1.3 12-17 for this scenario, generate th e programming file as follows: 1. select only the security settings option, as indicated in figure 12-14 and figure 12-15 on page 12-18 . click next . table 12-5 ? flashlock security options for fusion security option flashrom only fpga core only fb core only all no aes / no flashlock ? ? ? ? flashlock ???? aes and flashlock ???? figure 12-14 ? programming igloo and proasi c3 security settings only
security in low-pow er flash devices 12-18 v1.3 2. choose the desired se curity level se tting and enter the key(s). ?the high security level employs flashlock pass key with aes key protection. ?the medium security level employs flashl ock pass key protection only. figure 12-15 ? programming fusion se curity settings only figure 12-16 ? high security level to implement flas hlock pass key and aes key protection
security in low-pow er flash devices v1.3 12-19 table 12-6 and table 12-7 show all available options. if you want to implement custom levels, refer to the "advanced options" section on page 12-22 for information on each option and how to set it. 3. when done, click finish to generate the security header programming file. generation of programming f iles with aes encryption? application 3 this section discusses how to ge nerate design content programming files needed specifically at unsecured or remote locations to program devices with a security header (flashlock pass key and aes key) already programmed ( "application 2: nontrusted en vironment?unsecured location" section on page 12-9 and "application 3: nontrusted envi ronment?field updates/upgrades" section on page 12-10 ). in this case, the encrypted programm ing file must correspond to the aes key already programmed into the device. if aes encr yption was previously se lected to encrypt the flashrom, fb, and fpga array, aes encryption mu st be set when generati ng the programming file for them. aes encryption can be applied to the flashrom only, the fb only, the fpga array only, or all. the user must ensure both the flashloc k pass key and the aes key match those already programmed to the device(s), and all securi ty settings must matc h what was previously programmed. otherwise, the encryption and/or device unlocking will not be recognized when attempting to program the devi ce with the programming file. the generated programming fi le will be aes-encrypted. in this scenario, generate th e programming file as follows: 1. deselect the security settings and select the portion of the device to be programmed ( figure 12-17 on page 12-20 ). select programming previously secured device(s ). click next . table 12-6 ? all igloo and proasic3 head er file security options security option flashrom only fpga core only both flashrom and fpga no aes / no flashlock ??? flashlock only ??? aes and flashlock ??? note: ? = options that may be used table 12-7 ? all fusion header fi le security options security option flashrom only fpga core only fb core only all no aes / no flashlock ???? flashlock ???? aes and flashlock ????
security in low-pow er flash devices 12-20 v1.3 choose the high security level to reprogram devices usin g both the flashlock pass key and aes key protection ( figure 12-18 on page 12-21 ). enter the aes key and click next . a device that has already been secured with fl ashlock and has an aes key loaded must recognize the aes key to program the device and generate a valid bitstream in authen tication. the flashlock key is only required to unlock the device and change the security settings. this is what makes it possible to program in an untrusted environm ent. the aes key is protected inside the device by the flashlock key, so you ca n only program if you have the correct aes key. in fact, the aes key is not in the programming file eith er. it is the key used to encrypt the data in the file. the same key previously programmed with the flashlock key matche s to decrypt the file. if you had an aes-encrypted file programmed to a device without flashlock, this would not be secure, since without flashlock to protect the aes key, you could simply reprogram the aes key first, then program with any aes key you wanted or no aes key at all. this option is therefore not available in the software. note: the settings in this figure are used to show the ge neration of an aes-encrypted programming file for the fpga array, flashrom, and fb contents. one or all locations may be selected for encryption. figure 12-17 ? settings to program a device secured wi th flashlock and using aes encryption
security in low-pow er flash devices v1.3 12-21 programming with this file is intended for an unsecured enviro nment. the aes key encrypts the programming file with the same aes key already us ed in the device and utilizes it to program the device. reprogramming devices previously programmed devices can be reprogrammed using the steps in the "generation of the programming file in a trusted environm ent?application 1" section on page 12-13 and "generation of security header programming file only?application 2" section on page 12-16 . in the case where a flashlock pass key has been pr ogrammed previously, the user must generate the new programming file with a flashlock pass key that matches the one previously programmed into the device. the software will ch eck the flashlock pass key in th e programming file against the flashlock pass key in the device. the keys must match before the device can be unlocked to perform further progra mming with the new programming file. figure 12-10 on page 12-14 and figure 12-11 on page 12-14 show the option programming previously secured device(s) , which the user should select befo re proceeding. upon going to the next step, the user will be notifi ed that the same flashlock pass key needs to be entered, as shown in figure 12-19 on page 12-22 . figure 12-18 ? security level set high to re program device with aes key
security in low-pow er flash devices 12-22 v1.3 it is important to note that when the security se ttings need to be update d, the user also needs to select the security settings check box in step 1, as shown in figure 12-10 on page 12-14 and figure 12-11 on page 12-14 , to modify the security settings. the user must consid er the following: ? if only a new aes key is necessary, the user must re-enter the same pass key previously programmed into the device in designer and then generate a programming file with the same pass key and a different aes key. this en sures the programming file can be used to access and program the device and the new aes key. ? if a new pass key is necessary, the user can generate a new programming file with a new pass key (with the same or a new aes key if desired). however, for programming, the user must first load the orig inal programming file with the pass key that was previously used to unlock the device. then the ne w programming file can be used to program the new security settings. advanced options as mentioned, there may be app lications where more complicated security setting s are required. the ?custom security levels? section in the flashpro user's guide describes different advanced options available to aid the user in obta ining the best availabl e security settings. figure 12-19 ? flashlock pass key, previously programmed devices
security in low-pow er flash devices v1.3 12-23 programming file header definition in each stapl programming file generated, ther e will be information ab out how the aes key and flashlock pass key are configured. table 12-8 shows the header definitions in stapl programming files for different security levels. example file headers stapl files generated with flashlock key and aes key contain key information ? flashlock key / aes ke y indicated in stapl file header definition ? intended only for secu red/trusted environment programming applications ============================================= note "creator" "designer version: 6.1.1.108"; note "device" "a3pe600"; note "package" "208 pqfp"; note "date" "2005/04/08"; note "stapl_version" "jesd71"; note "idcode" "$123261cf"; note "design" "counter32"; note "checksum" "$edb9"; note "save_data" "fromstream"; note "security" "keyed encrypt "; note "alg_version" "1"; note "max_freq" "20000000"; note "silsig" "$00000000"; note "pass_key" "$00123456789012345678901234567890"; note "aes_key" "$abcdefabcdefabcdefabcdefabcdefab"; ============================================== table 12-8 ? stapl programming fi le header definitions by security level security level stapl f ile header definition no security (no flashlock pass key or aes key) note "security" "disable"; flashlock pass key with no aes key note "security" "keyed "; flashlock pass ke y with aes key note "security" "keyed encrypt "; permanent security settings option enabled note "security" "permlock encrypt "; aes-encrypted fpga array (f or programming updates) note "security" "encrypt core "; aes-encrypted flashrom (for programming updates) note "security" "encrypt from "; aes-encrypted fpga array and flashrom (for programming updates) note "security" "encrypt from core ";
security in low-pow er flash devices 12-24 v1.3 stapl file with aes encryption ? does not contain aes key / flashlock key information ? intended for transmission through web or serv ice to unsecured locations for programming ============================================= note "creator" "designer version: 6.1.1.108"; note "device" "a3pe600"; note "package" "208 pqfp"; note "date" "2005/04/08"; note "stapl_version" "jesd71"; note "idcode" "$123261cf"; note "design" "counter32"; note "checksum" "$ef57"; note "save_data" "fromstream"; note "security" "encrypt from core "; note "alg_version" "1"; note "max_freq" "20000000"; note "silsig" "$00000000"; conclusion the new and enhanced security features offered in actel fusion, igloo, and proasic3 devices provide state-of-the-art security to designs programmed into thes e flash-based devices. actel low- power flash devices employ the encryption standard used by nist and the u.s. government?aes using the 128-bit rijndael algorithm. the combination of an on-chip ae s decryption engine and actel fl ashlock technology provides the highest level of security against invasive attack s and design theft, impl ementing the most robust and secure isp solution. these security features protect ip within the fp ga and protect the system from cloning, wholesale ?black box? copying of a de sign, invasive attacks, and explicit ip or data theft. glossary term explanation security header programming file programming file used to program the flashlock pass ke y and/or aes key into the device to secure the fpga , flashrom, and/or fbs. aes (encryption) key 128-bit key defined by the user wh en the aes encryption option is set in the actel designer software when genera ting the programming file. flashlock pass key 128-bit key defined by the user when the flashlock option is set in the actel designer software when generating the programming file. the flashlock key protects the security se ttings programmed to the device. once a device is programmed with flashlock, whatever settings were chosen at that time are secure. flashlock the combined security features that protect the device content from attacks. these features are the following: ? flash technology that does not require an external bitstream to program the device ? flashlock pass key that secures device co ntent by locking the security settings and preventing access to the device as defined by the user ? aes key that allows secure, encrypted device reprogrammability
security in low-pow er flash devices v1.3 12-25 references national institute of standards and techno logy. ?advanced encryption standard (aes) questions and answers.? 28 january 2002.(10 january 2005). see http://csrc.ni st.gov/archive/ aes/index1.html for more information. related documents handbook documents flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf programming proasic3/e using a microprocessor http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 http://www.actel.com/documents/lpd_isp_hbs.pdf user?s guides flashpro user's guide http://www.actel.com/documents/flashpro_ug.pdf
security in low-pow er flash devices 12-26 v1.3 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-014-3 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (june 2008) the "security support in low-p ower devices" section was revised to include new families and make the information more concise. 12-2 v1.1 (march 2008) the following changes were made to the family descriptions in table12-1low-power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 12-2 v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 12-2
v1.3 13-1 13 ? in-system programming (isp) of actel?s low- power flash devices using flashpro3 introduction actel's low-power flash devices are all in-syste m programmable. this do cument describes the general requirements for programming a device and specific requirem ents for the flashpro3 programmer. fusion, igloo, ? and proasic ? 3 devices offer a low-power, single -chip, live-at-power-up solution with the asic advantages of security and low unit cost through nonvolatile flash technology. each device contains 1 kbit of on-chip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications such as internet protocol (ip) addressing, user system preference storage, device serialization, or subscription-based business mo dels. fusion, igloo, and proasic3 devices offer the best in-system prog ramming (isp) solu tion, flashlock ? security features, and aes- decryption-based isp. isp architecture low-power flash devices support is p via jtag and require a single v pump voltage of 3.3 v during programming. in addition, programming via a microc ontroller in a target sy stem is also supported. refer to microprocessor programming of actel?s low-power flash devices . family-specific support: ? fusion, proasic3, and proasic3e devices support isp. ? proasic3l devices operate using a 1.2 v core voltage and support isp at 1.5 v only. voltage switching is required in-system to switch from a 1.2 v core to 1.5 v core for programming. ? igloo and iglooe v5 devices can be progra mmed in-system when the device is using a 1.5 v supply voltage to the fpga core. ? igloo, igloo plus, and iglooe v2 devices can operate using either a 1.2 v core voltage or a 1.5 v core voltage. although the device can operate at 1.2 v core vo ltage, the device can only be reprogrammed when all supplies (v cc , v cci , and v jtag ) are at 1.5 v. voltage switching is required in-syste m to switch from a 1.2 v core to 1.5 v core for programming. igloo devices cannot be programmed in-system when the device is in flash*freeze mode. the device should exit flash*freeze mode and be in normal operation for programming to start. programming operations in igloo devices can be ac hieved when the device is in normal operating mode and a 1.5 v core voltage is used. jtag 1532 fusion, igloo, and proasic3 devices support the jtag-based ieee 1532 standard for isp. to start jtag operations, the igloo device should exit fl ash*freeze? mode and be in normal operation before starting to send jtag commands to the device . as part of this support, when a device is in an unprogrammed state, all user i/o pins are disabl ed. this is achieved by keeping the global io_en signal deactivated, which also has the effect of disabling the input buffers. th e sample/preload instruction captures the status of pads in parallel and shifts them ou t as new data is shifted in for loading into the boundary scan register (bsr). wh en the device is in an unprogrammed state, the sample/preload instruction has no effect on i/o st atus; however, it will co ntinue to shift in new data to be loaded into the bsr. therefore, when sample/preload is used on an unprogrammed device, the bsr will be loaded with undefined da ta. for jtag timing inform ation on setup, hold, and fall times, refer to the flashpro user?s guide .
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 13-2 v1.3 isp support in low-power devices the low-power flash families listed in table 13-1 support the isp feat ure and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 13-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 13-1 . where the information applies to on ly one family or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 13-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.3 13-3 programming voltage (v pump ) and v jtag low-power flash devices support on-chip charge pu mps, and therefore require only a single 3.3 v programming voltage for the v pump pin during programming. when the device is not being programmed, the v pump pin can be left floating or can be ti ed (pulled up) to any voltage between 0 v and 3.6 v. during programming, the target board or the flashpro3 programmer can provide v pump . flashpro3 is capable of supplying v pump to a single device. if more than one device is to be programmed using flashpro3 on a given board, flashpro3 should not be relied on to supply the v pump voltage. low-power flash device i/os support a bank-based, voltage-supply ar chitecture that simultaneously supports multiple i/o voltage standards ( table 13-2 on page 13-3 ). by isolating the jtag power supply in a separate bank from the user i/os, lo w-power flash devices prov ide greater flexibility with supply selection and simpli fy power supply and printed circuit board (pcb) design. the jtag pins can be run at any voltage fro m 1.5 v to 3.3 v (nominal). acte l recommends that tck be tied to gnd or v jtag when not used. this preven ts a possible totemp ole current on the input buffer stage. for tdi, tms, and trst pins, the devi ces provide an internal nominal 10 k pull-up resistor. during programming, all i/o pins, except for jtag inte rface pins, are tristated and weakly pulled up to v cci . this isolates the part and prevents the sign als from floating. the jtag interface pins are driven by the flashpro3 during programming, including the trst pin, which is driven high. ieee 1532 (jtag) interface the supported industry-standard ieee 1532 prog ramming interface buil ds on the ieee 1149.1 (jtag) standard. ieee 1532 defines the standardized process and methodology for isp. both silicon and software issues are addre ssed in ieee 1532 to create a si mplified isp environment. any ieee 1532?compliant programmer can be used to program low-power flash devices. however, only limited security and flashrom fe atures are supported when usin g the ieee 1532 standard. the actel flashpro3 programmer was de veloped exclusively for these de vices and will support all the security and device serialization features. refer to the standard for detail ed information about ieee 1532. security unlike sram-based fpgas that require loading at power-up from an extern al source such as a microcontroller or boot prom, actel nonvolatile devices are live at power-up, and there is no bitstream required to load the device when power is applied. the unique flash-based architecture prevents reverse engineer ing of the programmed code on the device, because the programmed data is stored in nonvolatile memory cells. each nonvolatile memory cell is made up of small capacitors and any physical deconstruction of th e device will disrupt sto red electrical charges. each low-power flash device has a built-in 128-bit advanced encryption st andard (aes) decryption core, except for the 15 k and 30 k gate devices. any fpga core or flashr om content loaded into the device can optionally be sent as encrypted bitstream and decrypted as it is loaded. this is table 13-2 ? power supplies power supply programming mode current during programming v cc 1.5 v < 70 ma v cci 1.5 v / 1.8 v / 2.5 v / 3.3 v (bank-selectable) i/os are weakly pulled up. v jtag 1.5 v / 1.8 v / 2.5 v / 3.3 v < 20 ma v pump 3.0 v to 3.6 v < 80 ma note: all supply voltages should be at 1.5 v or hi gher, regardless of the setting during normal operation.
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 13-4 v1.3 particularly suitable for applicatio ns where device updates must be transmitted over an unsecured network such as the internet. th e embedded aes decryption core can prevent sensitive data from being intercepted ( figure 13-1 on page 13-4 ). a single 128-bit aes key (32 hex characters) is used to encrypt fpga core programming data and/or flashr om programming data in the actel tools. the low-power flash devices also decrypt with a single 128-bit aes key. in addition, low-power flash devices support a message authentication code (mac) for authentication of the encrypted bitstream on-chip. this allows the encrypted bitstream to be au thenticated and pr events erroneous data from being programmed into the device. the fpga core, flas hrom, and flash memory blocks (fbs), in fusion only, can be updated independentl y using a programming file that is aes-encrypted (cipher text) or uses plain text. security in arm-enabled low-power flash devices there are slight differences between the regular flash device and the arm ? -enabled flash devices, which have the m1 and m7 prefix. the aes key is used by actel and pre-programmed into the device to protect the arm ip. as a result, the design will be encrypted along with the arm ip, according to the details below. coremp7 device security arm7? (m7-enabled) devices are shipped with the following security features: ? fpga array enabled for aes encryp ted programming and verification ? flashrom enabled for plaintext read and write cortex-m1 device security cortex-m1?enabled devices are shipped wi th the following security features: ? fpga array enabled for aes-encryp ted programming and verification ? flashrom enabled for aes-encrypted write and verify fusion embedded flash memory en abled for aes encrypted write. figure 13-2 on page 13-5 shows different applicat ions for isp programming. figure 13-1 ? aes-128 security features actel designer software programming file generation with aes encryption flash device decrypted bitstream mac validation aes decryption fpga core, flashrom, fbs transmit medium / public network encrypted bistream user encryption aes key
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.3 13-5 1. in a trusted programming environment, you can program the device using the unencrypted (plaintext) programming file. 2. you can program the aes key in a trusted pr ogramming environment and finish the final programming in an untrusted environment using the aes-encrypted (cipher text) programming file. 3. for the remote isp updating/reprogramming, th e aes key stored in the device enables the encrypted programming bitstream to be tra nsmitted through the untrusted network connection. actel low-power flash devices also provide the uniq ue actel flashlock feature, which protects the pass key and aes key. unless the original flashloc k pass key is used to unlock the device, security settings cannot be modified. low-power flash devices do not su pport read-back of fpga core- programmed data; however, the flashrom contents can selectively be read back (or disabled) via the jtag port based on th e security settings established by the actel designer software. refer to security in low-pow er flash devices for more information. flashrom and programming files each low-power flash device has 1 kbit of on-chip, nonvolatile flash memory that can be accessed from the fpga core. this nonvolatile flashrom is arranged in eight pages of 128 bits ( figure 13-3 ). each page can be programmed independently, wi th or without the 128-bi t aes encryption. the flashrom can only be programmed via the ieee 1532 jtag port and cannot be programmed from the fpga core. in addition, during programming of the flashrom, the fpga core is powered down automatically by the on-chi p programming control logic. using flashrom combined with aes, many subscription-based applic ations or device serialization applications are po ssible. smartgen supports easy manage ment of the flashrom contents even over large numbers of devices. smartgen ca n support flashrom cont ents that contain the following: ?static values figure 13-2 ? different isp use models source plain text aes encryption source encrypted bitstream tcp/ip flashrom aes decryption fpga core igloo or proasic3 device option 1 option 2 option 3
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 13-6 v1.3 ? random numbers ? values read from a file ? independent updates of each page in addition, auto-incrementing of fields is poss ible. in applications where the flashrom content is different for each device, you have the option to generate a single stapl file for all the devices or individual serializatio n files for each device. for more in formation on how to generate the flashrom content for device serialization, refer to flashrom in actel?s lo w-power flas h devices . actel libero ? integrated designed envi ronment (ide) includes a un ique tool to support the generation and management of flashrom and fpga programming files. this tool is called flashpoint. depending on the applications, designers can use th e flashpoint software to generate a stapl file with different contents. in each ca se, optional aes encryption and/or different security settings can be set. in designer, when you click the programming file icon, flashpoint launches, and you can generate stapl file(s) with four different cases ( figure 13-4 on page 13-7 ). when the serial ization feature is used during the configuration of flashrom in smartgen, you can generate a single stapl file that will program all the devices or an individual stapl file for each device. the following cases present the fp ga core and flashrom programming file combinations that can be used for different applications. in each case, yo u can set the optional se curity settings (flashlock pass key and/or aes key) depending on the application. 1. a single stapl file or multiple stapl file s with multiple flashr om contents and the fpga core content. a single stapl file will be gene rated if the device seri alization feature is not used. you can program the whole flashrom or selectively program individual pages. 2. a single stapl file for the fpga core content 3. a single stapl file or multiple stapl files wi th multiple flashrom contents. a single stapl file will be generated if the device serializ ation feature is not used. you can program the whole flashrom or selectivel y program individual pages. 4. a single stapl file to config ure the security settings for th e device, such as the aes key and/or pass key. figure 13-3 ? flashrom architecture 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 byte number in page page number
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.3 13-7 programming solution for device programming, any ieee 1532?complian t programmer can be used; however, the flashpro3 programmer must be used to control the low-power flash device's rich security features and flashrom programming options. the flas hpro3 programmer is a low-cost portable programmer for the actel flash families. it can al so be used with a powered usb hub for parallel programming. general specif ications for the flashpro3 programmer are as follows: ? programming clock ? tck is used with a ma ximum frequency of 20 mhz, and the default frequency is 4 mhz. ? programming file ? stapl ? daisy chain ? supported. you can use the chainbuilder software to build the programming file for the chain. ? parallel programming ? supported. multiple flashpro3 programmers can be connected together using a powered usb hub or through the multiple usb ports on the pc. ? power supply ? the target board must provide v cc , v cci , v pump , and v jtag during programming. however, if there is only on e device on the target board, the flashpro3 programmer can generate the required v pump voltage from the usb port. figure 13-4 ? flexible programming file genera tion for different applications actel's designer software suite fpga core content single/multiple flashrom content(s) flashrom configuration file (*.ufc) smartgen fpga core content security settings single/multiple flashrom content(s) programming file (flashpoint) netlist security settings security settings security settings 1234
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 13-8 v1.3 isp programming header information the flashpro3 programming cabl e connector can be connected with a 10-pin, 0.1"-pitch programming header. the recommended programming headers are manufactured by amp (103310-1) and 3m (2510-6002ub). if you have limited board space, you can use a compact programming header manufactured by samtec (ftsh-105-01-l-d-k). using this compact programming header, you are required to order an additional header adapter manufactured by actel (fp3-26pin-adapter). existing proasic plus family customers who are using the sa mtec small programming header (ftsh- 113-01-l-d-k) and are planning to migrate to igloo or proasic3 devices can order a separate adapter kit from actel (fp3-10pin -adapter-kit), which contains a compact 10-pin adapter kit as well as 26-pin migration capability . table 13-3 ? programming header ordering code manufacturer part nu mber description amp 103310-1 10-pin, 0.1"-pitch cabl e header (right-angle pcb mount angle) 3m 2510-6002ub 10-pin, 0.1"-pitch ca ble header (straight pcb mount angle) samtec ftsh-113-01-l-d-k small programming header supported by flashpro and silicon sculptor samtec ftsh-105-01-l-d-k com pact programming header samtec ffsd-05-d-06.00-01-n 10-pin cable with 50 mil pitch sockets; included in fp3- 10pin-adapter-kit. actel fp3-10pin-adapter-kit compac t header and migration kit figure 13-5 ? programming header (top view) table 13-4 ? programming header pin numbers and description pin signal source description 1 tck programmer jtag clock 2 gnd 1 ? signal reference 3 tdo target board test data output 4 nc ? no connect 5 tms programmer test mode select 6v jtag target board jtag supply voltage 7v pump 2 programmer/target board programming supply voltage 8 ntrst programmer jtag test reset (hi-z with 10 k pull-down, high, low, or toggling) 9 tdi programmer test data input 10 gnd 1 ? signal reference notes: 1. both gnd pins must be connected. 2. flashpro3 can provide v pump if there is only one device on the target board. 12 34 56 78 9 tck tdo tms v tdi gnd nc trst gnd 10 pump v jtag
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.3 13-9 board-level considerations a bypass capacitor is required from v pump to gnd for all low-po wer flash devices during programming. this bypass capacitor protects the de vices from voltage spikes that may occur on the v pump supplies during th e erase and programming cycles. refer to pin descriptions for specific recommendations. for proper programming, 0.01 f and 0.33 f capaci tors (both rated at 16 v) are to be connected in parallel across v pump and gnd, and positioned as close to the fpga pins as possible. the bypass ca pacitor must be placed within 2.5 cm of the device pins. troubleshooting signal integrity symptoms of a signal integrity problem a signal integrity problem can ma nifest itself in many ways. the problem may show up as extra or dropped bits during serial communication, changing the meaning of the communication. there is a normal variation of threshold voltage and freque ncy response between pa rts even from the same lot. because of this, the effects of signal integrity may not always affect different devices on the same board in the same way. so metimes, replacing a device ap pears to make signal integrity problems go away, but this is just masking the pr oblem. different parts on identical boards will exhibit the same problem sooner or later. it is important to fix signal integrity problems early. unless the signal integrity problems are severe enough to completely block all communication between the device and the programmer, they ma y show up as subtle problems. some of the flashpro3 exit codes that are caus ed by signal integrity problems ar e listed below. signal integrity problems are not the only possible cause of these errors, but this list is intended to show where problems can occur. flashpro3 allows tck to be lowered from 24 mhz down to 1 mhz to allow you to address some signal integrit y problems that may oc cur with impedance mismatching at higher frequencies. chain integrity test error or analyze chain failure normally, the flashpro3 analyze chain command expects to see 0x2 on the tdo pin. if the command reports reading 0x0 or 0x3, it is seeing the tdo pin stuck at 0 or 1. the only time the tdo pin comes out of tristate is when the jtag tap state machine is in th e shift-ir or shift-dr state. if figure 13-6 ? board layout and progra mming header top view v cc v cci v jtag gnd tck tdo tms v pump tdi trst 1 tck 2 gnd 3 tdo 4 nc 5 tms 6 v jtag 7 v pump 8 trst 9 tdi 10 gnd low-power flash device v cc from the target board v jtag from the target board v cci from the target board polarizing notch
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 13-10 v1.3 noise or reflections on the tck or tms lines ha ve disrupted the correct state transitions, the device's tap state controller migh t not be in one of these two sta tes when the programmer tries to read the device. when this happens, the output is floating when it is read and does not match the expected data value. this can also be caused by a broken tdo net. only a small amount of data is read from the device during the analyze chai n command, so marginal problems may not always show up during this command. exit 11 this error occurs during the verify stage of pr ogramming a device. after programming the design into the device, the device is veri fied to ensure it is programmed correctly. the verification is done by shifting the programmi ng data into the device . an internal comparison is performed within the device to verify that all switches are programmed correctly. noise induced by poor signal integrity can disrupt the writes and reads or the verification process and produce a ve rification error. while technically a verification error, the root cause is often related to signal integrity. refer to the flashpro user's guide for other error messages and solu tions. for the most up-to-date known issues and so lutions, refer to http://www.actel.com/support . conclusion fusion, igloo, and proasic3 devices offer a low-cost, single-chip solution that is live at power-up through nonvolatile flash technology. the flashloc k pass key and 128-bit aes key security features enable secure isp in an untrusted environmen t. on-chip flashrom enables a host of new applications, including device serialization, subscription-based applications, and ip addressing. additionally, as the flashrom is nonvolatile, all of these services can be provided without battery backup. related documents handbook documents microprocessor programming of actel?s low-power flash devices http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf security in low-pow er flash devices http://www.actel.com/l pd_security_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf user?s guides flashpro user's guide http://www.actel.com/documents/flashpro_ug.pdf
in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.3 13-11 part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-015-3 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (june 2008) the "isp support in low-pow er devices" section was revised to include new families and make the in formation more concise. 13-2 v1.1 (march 2008) the following changes were made to the family descriptions in table13-1low-power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 13-2 v1.0 (january 2008) the "isp architecture" section was updated to included the igloo plus family in the discussion of family-specific supp ort. the text, "when 1.2 v is used, the device can be reprogrammed in-system at 1.5 v only" was revised to state, "although the device can operate at 1.2 v core voltage, the device can only be reprogrammed when all supplies (v cc , v cci , and v jtag ) are at 1.5 v." 13-1 the "isp support in low-pow er devices" section and table 13-1 low-power flash families were updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 13-2 the "security" section was updated to mention that 15 k gate devices do not have a built-in 128-bit decryption core. 13-3 table13-2power supplies was revised to remove the normal operation column and add a table note stating, "all supply voltages should be at 1.5 v or higher, regardless of the setting during normal operation." 13-3 the "isp programming header information" section was revised to change fp3-26pin-adapter to fp3-10pin-adapter-kit. table 13-3 programming header ordering code was updated with the same change, as well as adding the part number ffsd-05-d-06.00-01-n, a 10-pin cable with 50-mil-pitch sockets. 13-8 the "board-level consid erations" section was updated to describe connecting two capacitors in parallel across v pump and gnd for proper programming. 13-9 51900055-2/7.06 informatio n was added to the "programming voltage (vpump) and vjtag" section about the jtag interface pin. 13-3 51900055-1/1.05 actgen was changed to smartgen. n/a in figure 13-6 board layout and programming header top view , the order of the text was changed to: v jtag from the target board v cci from the target board v cc from the target board 13-9

v1.1 14-1 14 ? core voltage switching circuit for igloo and proasic3l in-system programming introduction the igloo ? and proasic ? 3l families offer devices that can be powered by either 1.5 v or 1.2 v core voltage. since igloo and proasic3l devices are flash-based, they can be programmed and reprogrammed multiple times in-system using ac tel flashpro3. actel flashpro3 us es the jtag standard interface (ieee 1532) and stapl file (ieee 1149) to program a device. programming can also be executed by other methods, such as an embedded microcon troller that follows the same standards above. all igloo and proasic3l devices must be programmed with the v cc core voltage at 1.5 v. therefore, applications using ig loo or proasic3l devices powered by a 1.2 v supply must switch the core supply to 1.5 v for in-system programming. the purpose of this document is to describe an easy-to-use and cost-effectiv e solution for switching the core supply voltage from 1.2v to 1.5v during in-sys tem programming for igloo and proasic3l devices.
core voltage switching circuit for ig loo and proasic3l in -system programming 14-2 v1.1 actel?s flash families suppor t voltage switching circuit the low-power flash families listed in table 14-1 support the voltage swit ching circuit feature and the functions describe d in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 14-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 14-1 . where the information applies to on ly one family or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 14-1 ? low-power flash families product line family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
core voltage switching circuit for ig loo and proasic3l in-system programming v1.1 14-3 circuit description applications that use igloo or proasic3l devices powered by a 1.2 v core supply must have a mechanism that switches the core voltage from 1. 2v to 1.5v during in-s ystem programming (isp). there are several possible techniques to meet th is requirement. actel re commends utilizing a linear voltage regulator, a resistor volt age divider, and an n-channel digital fet to set the appropriate v cc voltage, as shown in figure 14-1 . the main component of actel's re commended circuit is the ltc30 25 linear voltage regulator from lineartech. the output voltage of the ltc3025 on the out pin is set by the ratio of two external resistors, r37 and r38, in a voltage divider. the li near voltage regulator ad justs the voltage on the out pin to maintain the adj pin voltage at 0.4 v (referenced to ground). by using an r38 value of 40.2 k and an r37 value of 80.6 k , the output voltage on the out pin is 1.2 v. to achieve 1.5 v on the out pin, r44 can be used in parallel with r38. the out pin can now be used as a switchable source for the v cc supply. refer to the ltc3025 linear voltage regulator datasheet for more information. in figure 14-1 , the n-channel digital fet is used to enable and disable r 44. this fet is controlled by the jtag trst signal driv en by the flashpro3 programmer. duri ng programming of the device, the trst signal is driven high by th e flashpro3, and turns the n-chan nel digital fet on . when the fet is on, r44 becomes enabled as a pa rallel resistance to r 38, which forces the re gulator to set out to 1.5 v. when the flashpro3 is connected and not in programming mode or when it is not connected, the pull-down resistor, r10, will pull the trst signal low. when this signal is low, the n-channel digital fet is "open" and r44 is not part of the resistance seen by the lt c3025. the new resistance momentarily changes the voltage va lue on the adj pin, which in tu rn causes the output of the ltc3025 to compensate by setting out to 1.2 v. no w the device will run in regular active mode at the regular 1.2 v core voltage. figure 14-1 ? circuit diagram
core voltage switching circuit for ig loo and proasic3l in -system programming 14-4 v1.1 circuit verification the power switching circuit recomme nded above is implemented on actel's icicle board ( figure 14-2 ). on the icicle board, vjtagenb is used to control the n-channel digital fet; however, this circuit was modified to use trst instead of vjtagenb in th is application. there are three important aspects of this ci rcuit that were verified: 1. the rise on v cc from 1.2 v to 1.5 v when trst is high 2. v cc rises to 1.5 v before programming begins. 3. v cc switches from 1.5 v to 1.2 v when trst is low. verification steps 1. the rise on v cc from 1.2 v to 1.5 v when trst is high. in the oscilloscope plots ( figure 14-2 ), the trst from flashpro3 and the v cc core voltage of the igloo device are labeled. this plot shows the rise characteristic of the trst signal from flashpro3. once the trst signal is asserted high, the ltc3025 shown in figure 14-1 on page 14-3 senses the increase in voltage and changes the output from 1. 2 v to 1.5 v. it takes the circuit approximately 100 s to respond to tr st and change the volt age to 1.5 v on the v cc core. figure 14-2 ? core voltage on the ig loo agl125-qng132 device v cc signal trst signal
core voltage switching circuit for ig loo and proasic3l in-system programming v1.1 14-5 2. v cc rises to 1.5 v before programming begins. the oscilloscope plot in figure 14-3 shows a wider time interval for the programm ing algorithm and includes the tdi and tms signals from the flashpro3. these signals carry the programming information that is programmed into the device and should only start toggling after the v cc core voltage reaches 1.5 v. again, th e trst from flashpro3 and the v cc voltage core of the igloo device are labeled. as shown in figure 14-3 , tdi and tms are floating initially, and the core voltage is 1.2 v. when a programming command on the flas hpro3 is executed, the tr st is driven high and the tdi is momentarily driven to ground. in response to the high trst signal, the circuit responds and pulls the core voltage to 1.5 v. after 100 ms, trst is briefly driv en low by the flashpro software. this is expected behavior that ensures the device jtag state machine is in reset prior to programming. the trst remains hi gh for the duration of the pr ogramming. it can be seen in figure 14-3 that the v cc core voltage signal remains at 1.5 v for approximately 50 ms before information starts passing through on tdi and tms. this confirms th at the voltage switching circuit drives the v cc core supply voltage to 1.5 v prior to programming. figure 14-3 ? programming algorithm floating signal tdi/tms trst signal (purple) tms signal green v cc core voltage tdi signal (yellow)
core voltage switching circuit for ig loo and proasic3l in -system programming 14-6 v1.1 3. v cc switches from 1.5 v to 1.2 v when trst is low. in figure 14-4 , the trst signal and the v cc core voltage signal are labeled. as the trst is pulled to ground, the core voltage is obse rved to switch from 1.5 v to 1. 2 v. the observed fall time is approximately 2 ms. directc the above analysis is based on flashpro3 but there are other solu tions to isp, such as directc. directc is a microprocessor program that can be run in-system to program actel flash devices. for flashpro3, trst is the most conven ient control signal to use for the recommended ci rcuit. however, for directc, users may use any si gnal to control the fet. for ex ample, the directc code can be edited so that a separate non-jt ag signal can be asserted from th e microcontroller that signals the board that it is about to start programming the device. after asserting th e n-channel digital fet control signal, the progra mming algorithm must allow sufficient time for the supply to rise to 1.5 v before initiating directc programming. as seen in figure 14-3 on page 14-5 , 50 ms is adequate time. depending on the size of th e pcb and the capacitance on the v cc supply, results may vary from system to system. actel recommends using a co nservative value for the wait time to make sure that the v cc core voltage is at the right level. conclusion actel's igloo and proasic3l low-power fpgas offer 1.2 v core operation; however, they must be programmed with a core voltage of 1.5 v. since the device can have either a 1.2 v or a 1.5 v normal operation, there must be a way for the core voltag e to switch from 1.2 v to 1.5 v, which is required during in-system programming. the circuit explai ned in this document illustrates one simple, cost- effective way of handling this requirement. a jtag signal from the flashpro3 programmer allows the circuit to sense when programming is in progress, en abling it to switch to the correct core voltage. figure 14-4 ? trst toggled low trst signal v cc core signal
core voltage switching circuit for ig loo and proasic3l in-system programming v1.1 14-7 part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-028-1 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (august 2008) the "actel?s flash families support vo ltage switching circuit" section was revised to include new families an d make the information more concise. 14-2

boundary scan and ujtag

v1.3 15-1 15 ? boundary scan in low-power flash devices boundary scan low-power flash devices are comp atible with ieee standard 11 49.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. jtag operations are used during boundary scan testing. the basic boundary scan logic circuit is composed of the tap controller, test data registers, and instruction register ( figure 15-2 on page 15-4 ). low-power flash devices support three types of test data registers: bypass , device identification, and boundary scan. the bypass register is selected when no other register needs to be accessed in a device. this speeds up test data transfer to othe r devices in a test data path. the 32-bit device identification register is a shift re gister with four fields (lsb, id number, part number, and version). the boundary scan register observes and controls th e state of each i/o pin. each i/o cell has three boundary scan register cells, each with serial-in, serial-out, parallel-in, and parallel-out pins. tap controller state machine the tap controller is a 4-bit state machin e (16 states) that operates as shown in figure 15-1 . the 1s and 0s represent the values that must be present on tm s at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. the tap controller receives two control inputs (tms and tck) and gene rates control and clock signals for the rest of the test lo gic architecture. on power-up, th e tap controller enters the test- logic-reset state. to guarantee a reset of the co ntroller from any of the possible states, tms must remain high for five tck cycles. the trst pin can also be us ed to asynchronously place the tap controller in the test-logic-reset state. figure 15-1 ? tap controller state machine 1 test_logic_reset run_test_idle select_dr capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr select_ir capture_ir shift_ir exit1_ir pause_ir exit2_ir update_ir 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1
boundary scan in lo w-power flash devices 15-2 v1.3 actel?s flash families support the jtag feature the low-power flash families listed in table 15-1 support the jtag feature and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 15-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 15-1 . where the information applies to on ly one family or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 15-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proasic ? 3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo ? igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
boundary scan in low-power flash devices v1.3 15-3 boundary scan support in low-power devices the information in this document applies to all fusion, igloo, and proasi c3 devices. for igloo, igloo plus, and proasic3l devices, the flash*freeze pin must be deasserted for successful boundary scan operations. devices cannot en ter jtag mode directly from flash*freeze mode. boundary scan opcodes low-power flash devices support all ma ndatory ieee 1149.1 instructions (extest, sample/preload, and bypass) and the optional id code instruction ( table 15-2 ). boundary scan chain the serial pins are used to serial ly connect all the boundary scan register cells in a device into a boundary scan register chain ( figure 15-2 on page 15-4 ), which starts at the tdi pin and ends at the tdo pin. the parallel ports are co nnected to the internal core logi c i/o tile and the input, output, and control ports of an i/o buffer to capture and load data into the register to control or observe the logic state of each i/o. each test section is accessed through the tap, which has five associated pins : tck (test clock input), tdi, tdo (test data input and output), tms (test mo de selector), and trst (test reset input). tms, tdi, and trst are equipped with pu ll-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundary scan test usage. refer to the "jtag pins" description in pin descriptions for pull-up/-down recommendat ions for tdo and tck pins. table 15-2 ? boundary scan opcodes hex opcode extest 00 highz 07 usercode 0e sample/preload 01 idcode 0f clamp 05 bypass ff
boundary scan in lo w-power flash devices 15-4 v1.3 board level recommendations table 15-3 gives pull-down recommendations for the trst and tck pins. figure 15-2 ? boundary scan chain device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers table 15-3 ? trst and tck pull-down recommendations v jtag tie-off resistance* v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k * equivalent parallel resistance if more than one device is on jtag chain ( figure 15-3 )
boundary scan in low-power flash devices v1.3 15-5 related documents handbook documents pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf note: tck is correctly wired with an equivalent tie-off resistance of 500 , which satisfies the table for v jtag of 1.5 v. the resistor values for trst are not appropriate in this case, as the tie-off resistance of 375 is below the recommended minimum for v jtag = 1.5 v, but would be appropriate for a v jtag setting of 2.5 v or 3.3 v. figure 15-3 ? parallel resistance on jtag chain of devices tdi tdi tdi tdi tdo tdo tdo tdo jtag header actel fpga 1 actel fpga 2 actel fpga 3 actel fpga 4 2 k 2 k 2 k 2 k 1.5 v tck trst vjtag gnd 1.5 k 1.5 k 1.5 k 1.5 k
boundary scan in lo w-power flash devices 15-6 v1.3 part number and revision date this document contains content extracted from th e device architecture section of the datasheet. to improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage info rmation. no technical chan ges were made to the content unless explicitly listed. part number 51700094-019-3 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (june 2008) the "boundary scan support in low-power devices" section was revised to include new families and make the information more concise. 15-3 v1.1 (march 2008) the following changes were made to the family descriptions in table15-1low-power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 15-2 v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 15-2
v1.3 16-1 16 ? ujtag applications in actel?s low-power flash devices introduction in fusion, igloo, ? and proasic ? 3 devices, there is bidirectional access from the jtag port to the core versatiles during normal operation of the device ( figure 16-1 ). user jtag (ujtag) is the ability for the design to use the jtag ports for access to the device for up dates, etc. while regular jtag is used, the ujtag tiles, located at the southeast area of the die, are directly connected to the jtag test access port (tap) controller in normal operatin g mode. as a result, all the functional blocks of the device, such as clock conditioning circuits (ccc) with plls, sram blocks, embedded flashrom, flash memory blocks, and i/o tiles, can be reac hed via the jtag ports. the ujtag functionality is available by instantiating the ujtag macro directly in the source code of a design. access to the fpga core versatiles from the jtag ports enables us ers to implement differ ent applications using the tap controller (jtag port). this document introduces the ujtag tile functionality and discusses a few application examples. however, the possible applications are no t limited to what is presented in this document. ujtag can serve different purposes in many design s as an elementary or auxiliary part of the design. for detailed usage information, refer to boundary scan in low-power flash devices . figure 16-1 ? block diagram of using ujtag to read flashrom contents from addr [6:0] data[7:0] clk enable sdo sdi reset addr[6:0] data[7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] control ujtag address generation and data serlialization
ujtag applications in acte l?s low-power flash devices 16-2 v1.3 ujtag support in low-power devices the low-power flash fa milies listed in table 16-1 support the ujtag feature and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 16-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 16-1 . where the information applies to on ly one family or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 16-1 ? low-power flash families product line family * description fusion fusion mixed-signal fpga integrating proa sic3 fpga fabric, programmable analog block, support for arm ? cortex?-m1 soft processors and flash memory into a monolithic device igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
ujtag applications in acte l?s low-power flash devices v1.3 16-3 ujtag macro the ujtag tiles can be instantiated in a design using the ujtag macro from the fusion, igloo, or proasic3 macro library. note that "ujtag" is a reserved name and cannot be used for any other user-defined blocks. a bloc k symbol of the ujtag tile macro is presented in figure 16-2 . in this figure, the ports on the left side of the bloc k are connected to the jt ag tap controller, and the right-side ports are accessib le by the fpga core versatiles. the td i, tms, tdo, tck, and trst ports of ujtag are only provided for design simulation pu rposes and should be treated as external signals in the design netl ist. however, these ports must not be connected to any i/o buffer in the netlist. figure 16-3 on page 16-4 illustrates the correc t connection of the uj tag macro to the user design netlist. actel de signer software will auto matically connect these ports to the tap during place-and-route. table 16-2 gives the port descriptions for the rest of the ujtag ports: table 16-2 ? ujtag port descriptions port description uireg [7:0] this 8-bit bus carries the contents of the jtag instruction regi ster of each device. instruction register values 16 to 127 are not reserved and can be employed as user-defined instructions. urstb urstb is an active-low signal and will be asserted when the ta p controller is in test-logic-reset mode. urstb is asserted at power-up, and a pow er-on reset signal resets the tap controller. urstb will stay asserted until an external tap access changes the tap controller state. utdi this port is directly conn ected to the tap's tdi signal. utdo this port is the user tdo ou tput. inputs to the utdo port are sent to the tap tdo output mux when the ir address is in user range. udrsh active-high sign al enabled in the shiftdr tap state udrcap active-high signal enab led in the capturedr tap state udrck this port is directly conn ected to the tap's tck signal. udrupd active-high sign al enabled in the updatedr tap state figure 16-2 ? ujtag tile block symbol tdi tck tdo tms trst uireg0 uireg1 uireg2 uireg3 uireg4 uireg5 uireg6 uireg7 utdi utdo udrck udrcap udrsh udrupd urstb
ujtag applications in acte l?s low-power flash devices 16-4 v1.3 ujtag operation there are a few basic functions of the ujtag macr o that users must understand before designing with it. the most important fundamental concept of the ujtag design is its connection with the tap controller state machine. tap controller state machine the 16 states of the tap contro ller state machine are shown in figure 16-4 on page 16-5 . the 1s and 0s, shown adjacent to the sta te transitions, represent the tm s values that must be present at the time of a rising tck edge for a state transiti on to occur. in the state s that include the letters "ir," the instruct ion register operates; in the states that contain the letters "dr," the test data register operates. the tap controller receives tw o control inputs, tms and tck, and generates control and clock signals for the rest of the test logic. on power-up (or the assertion of trst), the tap controller ente rs the test-logic-reset state. to reset the controller from any other state, tms must be held high for at least five tck cycles. after reset, the tap state changes at the rising edge of tck, based on the value of tms. note: do not connect jtag pins (tdo, tdi, tms, tck, or trst) to i/os in the design. figure 16-3 ? connectivity method of ujtag macro tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] inputs outputs tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] inputs outputs a) correct instantiation b) incorrect instantiation fpga versatiles fpga versatiles
ujtag applications in acte l?s low-power flash devices v1.3 16-5 ujtag port usage uireg[7:0] hold the contents of the jtag instruct ion register. the uireg vector value is updated when the tap controller state mach ine enters the update_ir state. in structions 16 to 127 are user- defined and can be employed to encode multiple applications and commands within an application. loading new instructions into the uireg vector requires users to send appropriate logic to tms to put the tap controll er in a full ir cycle starting from the select ir_scan state and ending with the update_ir state. utdi, utdo, and udrck are directly connected to the jtag tdi, tdo, and tck ports, respectively. the tdi input can be used to provide either data (t ap controller in the shift_dr state) or the new contents of the instruction register (t ap controller in the shift_ir state). udrsh, udrupd, and udrcap are high when the tap controller state machine is in the shift_dr, update_dr, and capture_dr states, respectively. therefore, they act as flags to indicate the stages of the data shift process. these flags are useful fo r applications in which blocks of data are shifted into the design from jtag pins. for example, an active udrsh can indicate that utdi contains the data bitstream, and udrupd is a candida te for the end-of -data-stream flag. as mentioned earlier, users should not connect the tdi, tdo, tck, tms, and trst ports of the ujtag macro to any port or net of the design ne tlist. the designer soft ware will automatically handle the port connection. figure 16-4 ? tap controller state diagram run_test/ idle 0 test_logic_reset 1 0 1 select_ dr_scan update_dr exit2_dr pause_dr exit1_dr shift_dr capture_dr select_ ir_scan update_ir exit2_ir pause_ir exit1_ir shift_ir capture_ir 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1
ujtag applications in acte l?s low-power flash devices 16-6 v1.3 typical ujtag applications bidirectional access to the jtag port from versa tiles?without putting the device into test mode? creates flexibility to implement many different ap plications. this section describes a few of these. all are based on importing/exporting data through the ujtag tiles. clock conditioning circuitry ?dynamic reconfiguration in low-power flash devices, cccs, which include plls, can be configured dynamically through either an 81-bit embedded shift register or static flash programming switches. these 81 bits control all the characteristics of the ccc: routing mux archit ectures, delay values, divider values, etc. table 16-3 lists the 81 configuration bits in the ccc. the embedded 81-bit shift register (for the dynami c configuration of the ccc) is accessible to the versatiles, which, in turn, have access to the uj tag tiles. therefore, the ccc configuration shift register can receive and load the new configuration data stream from jtag. dynamic reconfiguration eliminates the need to reprogram the device when reconfiguration of the ccc functional blocks is needed. the ccc configur ation can be modified wh ile the device continues to operate. employing th e ujtag core requires the user to design a module to provide the configuration data and control the ccc configuratio n shift register. in esse nce, this is a user- designed tap controller re quiring chip resources. table 16-3 ? configuration bits of fusion, igloo, and proasic3 ccc blocks bit number control function 80 reset enable 79 dyncsel 78 dynbsel 77 dynasel <76:74> vcosel [2:0] 73 statcsel 72 statbsel 71 statasel <70:66> dlyc [4:0] <65:61> dlyb {4:0] <60:56> dlyglc [4:0] <55:51> dlyglb [4:0] <50:46> dlygla [4:0] 45 xdlysel <44:40> fbdly [4:0] <39:38> fbsel <37:35> ocmux [2:0] <34:32> obmux [2:0] <31:29> oamux [2:0] <28:24> ocdiv [4:0] <23:19> obdiv [4:0] <18:14> oadiv [4:0] <13:7> fbdiv [6:0] <6:0> findiv [6:0]
ujtag applications in acte l?s low-power flash devices v1.3 16-7 similar reconfiguration capability exists in the actel proasic plus ? family. the only difference is the number of shift register bits controlling the ccc (27 in proasic plus and 81 in igloo, proasic3, and fusion). fine tuning in some applications, design constants or parame ters need to be modifi ed after programming the original design. the tuning process can be done using the ujtag tile without reprogramming the device with new values. if the parameters or constants of a design are stored in distributed registers or embedded sram bloc ks, the new values can be shifted onto the jtag tap controller pins, replacing the old va lues. the ujtag tile is used as the ?bridge? for data tr ansfer between the jtag pins and the fpga versatiles or sram logic. figure 16-5 shows a flow chart example for fine- tuning application steps using the ujtag tile. in figure 16-5 , the tms signal sets the ta p controller state machine to the appropriate states. the flow mainly consists of two steps: a) shifting the defined instructio n and b) shifting the new data. if the target parameter is constantly used in the de sign, the new data can be shifted into a temporary shift register from utdi. the udrsh output of uj tag can be used as a sh ift-enable signal, and udrck is the shift clock to the shift register . once the shift process is completed and the tap controller state is moved to the update_dr state , the udrupd output of the ujtag can latch the new parameter value from the temporary register into a permanent locati on. this avoids any interruption or malfunctioning during the serial shift of the new value. figure 16-5 ? flow chart example of fine-tun ing an application using ujtag yes no tap controller in test_logic_reset state set tap state to shift_ir shift the user-defined instruction of tuning application set tap state to update_ir latch the recorded data onto the location of stored parameter uireg equal to the user-defined instruction set tap state to shift_dr shift data into tdi and record utdi in a shift register set tap state in update_dr
ujtag applications in acte l?s low-power flash devices 16-8 v1.3 silicon testing and debugging in many applications, the design ne eds to be tested, debugged, and veri fied on real si licon or in the final embedded application. to debug and test th e functionality of designs, users may need to monitor some internal logic (or ne ts) during device operation. the approach of adding design test pins to monitor the critical intern al signals has many disadvantages, such as limiting the number of user i/os. furthermore, adding external i/os fo r test purposes may require additional or dedicated board area for testing and debugging. the ujtag tiles of low-power flash devices offer a flexible and cost-effective solution for silicon test and debug applications. in this solution, the signals under test are shifted out to the tdo pin of the tap controller. th e main advantage is that all the te st signals are monito red from the tdo pin; no pins or additional board-level resources are required. figure 16-6 illustrates this technique. multiple test nets are brought into an internal mux architecture. the selection of the mux is done using the contents of the tap cont roller instruction register, wher e individual instr uctions (values from 16 to 127) correspond to di fferent signals under test. the selected test signal can be synchronized with the rising or falling edge of tck (optional) and sent out to utdo to drive the tdo output of jtag. the test and debug procedure is not limited to the example in figure 16-5 on page 16-7 . users can customize the debug and test interf ace to make it appropriate for their applications. for example, multiple test signals can be registered and then se nt out through utdo, each at a different edge of tck. in other words, n signals are samp led with an f tck / n sampling rate. the bandwidth of the information sent out to tdo is always proportional to the frequency of tck. sram initialization users can also initialize embedded srams of the lo w-power flash devices. the initialization of the embedded sram blocks of the design can be done using ujtag tiles, where the initialization data is imported using the tap controller. similar functionality is available in proasic plus devices using jtag. the guidelines for implementation and design examples are given in the ram initialization and rom emulation in proasic plus devices application note. srams are volatile by nature; data is lost in th e absence of power. ther efore, the initialization process should be done at each power-up if necessary. figure 16-6 ? ujtag usage example in tes t and debug applications tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] clk dq internal test nets instruction decode to scope channel
ujtag applications in acte l?s low-power flash devices v1.3 16-9 flashrom read-back using jtag the low-power flash architecture contains a de dicated nonvolatile flashrom block, which is formatted into eight 128-bit pages. for more information on flashrom, refer to flashrom in actel?s low-power flash devices . the contents of flashrom are av ailable to the versatiles during normal operation through a read operation. as a result, the ujtag macro can be used to provide the flashrom contents to the jtag port duri ng normal operation. figure 16-7 illustrates a simple block diagram of using ujtag to read the contents of flashrom during normal operation. the flashrom read address can be provided from outside the fpga throug h the tdi input or can be generated internally using the core logic. in either case, data serialization logic is required ( figure 16-7 ) and should be designed using the versatile core logic. flashrom contents are read asynchronously in parall el from the flash memory and shifted out in a synchronous serial format to tdo. shifting the se rial data out of the seri alization block should be performed while the tap is in udrsh mode. the coordination between tck and the data shift procedure can be done using the tap state machine by monitori ng udrsh, udrcap, and udrupd. conclusion actel low-power flash fpgas offer many unique advantages, such as security, nonvolatility, reprogrammablity, and low power?all in a single chip. in addition, fusion, igloo, and proasic3 devices provide access to the jtag port from core versa tiles while the device is in normal operating mode. a wide range of available user-defined jtag opcodes allows users to implement various types of applications, exploiting this feature of these devices. the connection between the jtag port and core tiles is implemented through an embedded and hardwired ujtag tile. a ujtag tile can be instantiated in designs using the ujtag library cell. this document presents multiple examples of ujtag applications, such as dynamic reconfiguration, silicon test and debug, fine- tuning of the design, and ram initialization. each of these applications offers many useful advantages. figure 16-7 ? block diagram of using ujtag to read flashrom contents from addr [6:0] data[7:0] clk enable sdo sdi reset addr[6:0] data[7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] control ujtag address generation and data serlialization
ujtag applications in acte l?s low-power flash devices 16-10 v1.3 related documents application notes ram initialization and rom emulation in proasic plus devices http://www.actel.com/documents/apa_ram_initd_an.pdf handbook documents boundary scan in lo w-power flash devices http://www.actel.com/documen ts/lpd_boundaryscan_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information part number 51700094-020-3 revised october 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (june 2008) the "ujtag support in low-power devices" section was revised to include new families and make the in formation more concise. 16-2 the title of table 16-3 configuration bits of fusion, igloo, and proasic3 ccc blocks was revised to include fusion. 16-6 v1.1 (march 2008) the following changes were made to the family descriptions in table16-1low-power flash families : ? proasic3l was updated to include 1.5 v. ? the number of plls for proasi c3e was changed from five to six. 16-2 v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 16-2
board-level requirements

v1.1 17-1 17 ? power-up/-down behavior of low-power flash devices introduction actel?s low-power flash devices are flash-based fpgas manufactured on a 0.13 m process node. these devices offer a single-chip, reprogrammable solution and support level 0 live at power-up (lapu) due to their no nvolatile architecture. actel's four low-power flash fpga families ar e optimized for logic ar ea, i/o features, and performance. igloo ? devices are optimized for power, m aking them the indu stry's lowest power programmable solution. igloo plus fpgas offer enhanced i/o features beyond those of the igloo ultra-low power soluti on for i/o-intensive low-power applications. proasic3 ? l fpgas balance low power with high performance. the proa sic3 family is actel's high-performance flash fpga solution. actel?s low-power flash devices exhibit very low transient current on each power supply during power-up. the peak value of the transient curre nt depends on the device size, temperature, voltage levels, and power-up sequence. the following devices can have inputs driv en in while the device is not powered: ? igloo (agl015 and agl030) ? igloo plus (aglp030, aglp060, aglp125) ? iglooe (agle600, agle3000) ? proasic3l (a3pe3000l) ? proasic3 (a3p015 and a3p030) ? proasic3e (a3pe600, a3pe1500, a3pe3000) ? military proasic3el (a3pe600l, a3pe3000l, but not a3p1000) ? rt proasic3 (rt3pe600l, rt3pe3000l) the driven i/os do not pull up power planes, and th e current draw is limited to very small leakage current, making them suitable fo r applications that require cold -sparing. these devices are hot- swappable, mean ing they can be inserted in a live power system. 1 1. for more details on the levels of hot-swap compatibility in actel?s low-power flash devices, refer to the "hot-swap support" section in the i/o structures chapter of the handbook for the device you are using.
power-up/-down behavior of low-power flash devices 17-2 v1.1 actel?s flash families support power-up behavior the low-power flash families listed in table 17-1 support power-up behavior and the functions described in this document. igloo terminology in documentation, the terms igloo families and igloo devices refe r to all of the igloo products as listed in table 17-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e terms proasic3 families and proasic3 devices refer to all of the proasic3 families as listed in table 17-1 . where the information applies to on ly one family or limited devices, these exclusions will be explicitly stated. to further understand the differences between the igloo and proasic3 families, refer to the industry?s lowest power fpgas portfolio . table 17-1 ? low-power flash families product line family * description igloo igloo ultra-low-power 1.2 v to 1.5 v fp gas with flash* freeze technology iglooe higher density igloo fpgas with six plls and additional i/o standards igloo plus igloo fpgas with enhanced i/o capabilities proasic3 proasic3 low-power, high-performance 1.5 v fpgas proasic3e higher density proasic3 fpgas with six plls and additional i/o standards proasic3l proasic3 fpgas supporting 1.2 v to 1.5 v with flash*freeze technology automotive proasic3 proasic3 fpgas qualified fo r automotive applications military proasic3/el military temperature a3pe600l, a3p1000, and a3pe3000l rt proasic3 radiation-tolerant rt3pe600l and rt3pe3000l note: *the family names link to the appropriate datasheet, including product brief, dc and switching characteristics, and packaging information.
power-up/-down behavior of proasic3/e devices v1.1 17-3 power-up/down sequence and transient current actel's low-power flash devices use the following main voltage pins during normal operation: 2 ?v ccplx ?v jtag ?v cc : voltage supply to the fpga core ?v cc is 1.5 v 0.075 v for igloo, igloo plus , and proasic3 device s operating at 1.5 v. ?v cc is 1.2 v 0.06 v for igloo, igloo plus , and proasic3l devices operating at 1.2 v. ? v5 devices will require a 1.5v v cc supply, where as v2 device s can utilize either 1.2 v or 1.5 v v cc . ?v cci bx: supply voltage to the bank's i/o output buffers and i/o logic. bx is the i/o bank number. ? vmvx: quiet supply voltage to the input buffers of each i/o bank. x is the bank number. (note: igloo plus devices do not have vmvx supply pins.) the i/o bank vmv pin must be tied to the v cci pin within the same bank . therefore, the supplies that need to be powered up/down during normal operation are v cc and v cci . these power supplies can be powered up/down in any sequence during normal operation of igloo, igloo plus, proasic3l, and proasic3 fpgas. during power-up, i/o s in each bank will remain tristated until the last supply (either v cci bx or v cc ) reaches its functional activation voltage. similarly, during power- down, i/os of each bank are tristated once th e first supply reaches its brownout deactivation voltage. although actel's low-power flash devices have no power-up or power-down sequencing requirements, actel identifies the following power conditions that will result in higher than normal transient current. use this informatio n to help maximize power savings: actel recommends tying v ccplx to v cc and using proper filtering circuits to decouple v cc noise from the pll. a. if v ccplx is powered up before v cc , a static current of up to 5 ma (typical) per pll may be measured on v ccplx . i. the current vanishes as soon as v cc reaches v ccplx voltage level. ii. the same current is observed at power-down (v cc before v ccplx ). b. if v ccplx is powered up simultaneously or after v cc : i. actel's low-power flash devices exhi bit very low transient current on v cc . for proasic3 devices, the maximum transient current on v cc does not exceed the maximum standby current specif ied in the device datasheet. the source of transient current, also known as inrush current, varies depending on the fpga technology. due to their volati le technology, the internal re gisters in sram fpgas must be initialized before configuration can start. this in itialization is the source of significant inrush current in sram fpgas during power-up. due to the nonvolatile nature of flash technology, low- power flash devices do not requir e any initialization at power-up , and there is very little or no crossbar current through pmos and nmos devices. therefore, the transient current at power-up is significantly less than for sram fpgas. figure 17-1 on page 17-4 illustrates the types of power consumption by sram fpgas compared to actel's antifuse and flash fpgas. 2. for more information on actel fpga voltage supplie s, refer to the appropriate datasheet located at http://www.actel.com/techdocs/ds .
power-up/-down behavior of low-power flash devices 17-4 v1.1 transient current on v cc the characterization of th e transient current on v cc is performed on nearly all devices within the igloo, proasic3l, and proasic3 families. a sample size of five units is used from each device family member. all the device i/os are intern ally pulled down while the transient current measurements are performed. for proasic3 devices, the measurements at typical conditions show that the maximum transient current on v cc , when the power supply is powered at ramp-rates ranging from 15 v/ms to 0.15 v/ms, does not exceed the maximum sta ndby current specified in the device datasheets. refer to proasic3 dc and swit ching char acteristics and proasic3e dc and switching characteristics for more information. similarly, igloo, igloo plus, and proasic3l devices exhibit very low transient current on v cc . the transient current does not exceed the typical operat ing current of the device while in active mode. the characterization of agl600-fg256 v2 and v5 devices has shown that the transient current on v cc is typically in the range of 1?5 ma. transient current on v cci the characterization of the transient current on v cci is performed on nearly all devices within the igloo, igloo plus, proa sic3l, and proasic3 fa milies, similar to v cc transient current measurements. for proasic3 devi ces, the measurements at typi cal conditions show that the maximum transient current on v cci , when the power supply is powe red at ramp-rates ranging from 33 v/ms to 0.33 v/ms, does not exceed the maximum standby current specified in the device datasheet. refer to proasic3 dc and switching characteristics and proasic3e dc and switching characteristics for more information. similarly, igloo, igloo plus, and proasic3l de vices exhibit very low transient current on v cci . the transient current does not exceed the typical operat ing current of the device while in active mode. the characterization of agl600-fg256 v2 and v5 devices has shown that the transient current on v cci is typically in the range of 1?2 ma. figure 17-1 ? types of power consumption in sram fpgas and actel nonvolatile fpgas sram actel fpgas time (or frequency) current configuration sram fpgas power-on inrush sram fpgas active frequency dependent static system supply voltage
power-up/-down behavior of proasic3/e devices v1.1 17-5 i/o behavior at power-up/-down this section discusses the behavior of device i/os, used and unused, during power-up/-down of v cc and v cci . as mentioned earlier, vmvx and v cci bx are tied together, an d therefore, inputs and outputs are powered up/down at the same time. i/o state during power-up/-down this section discusses the charac teristics of i/o behavior during device power-up and power-down. before the start of power-up, all i/os are in tris tate mode. the i/os will remain tristated during power-up until the last voltage supply (v cc or v cci ) is powered to its functi onal level (power supply functional levels ar e discussed in the "power-up to func tional time" section on page 17-6 ). after the last supply reaches the functi onal level, the outputs will exit the tristate mode and drive the logic at the input of the output buffer. similarly, the input buffers will pass the external logic into the fpga fabric once the last supply reaches the functional level. the beha vior of user i/os is independent of the v cc and v cci sequence or the state of ot her voltage supplies of the fpga (v pump and v jtag ). figure 17-2 shows the output buffer driving high and its behavior during power-up with 10 k external pull-down. in figure 17-2 , v cc is powered first, and v cci is powered 5 ms after v cc . figure 17-3 on page 17-6 shows the state of the i/o when v cci is powered about 5 ms before v cc . in the circuitry shown in figure 17-3 on page 17-6 , the output is externally pulled down. during power-down, device i/os become tristated once the first power supply (v cc or v cci ) drops below its brownout voltage level. the i/o behavior during power-down is also independent of voltage supply sequencing. figure 17-2 ? i/o state when v cc is powered before v cci
power-up/-down behavior of low-power flash devices 17-6 v1.1 power-up to functional time at power-up, device i/os exit the tristate mode and become functional once the last voltage supply in the power-up sequence (v cci or v cc ) reaches its function al activation level. the power-up?to? functional time is th e time it takes for the last supply to power up from ze ro to its func tional level. note, the functional leve l of the power supply during power- up may vary slightly within the specification in differen t ramp-rates. refer to table 17-2 for the functi onal level of the voltage supplies at power-up. typical i/o behavior during power-up to functional time is illustrated in figure 17-2 on page 17-5 and figure 17-3 . actel?s low-power flash devices meet level 0 lapu ; that is, they can be functional prior to v cc reaching the regulated voltage required. this im portant advantage distinguishes low-power flash devices from their sram-based counterparts. sram -based fpgas, due to thei r volatile technology, require hundreds of milliseconds after power-up to configure th e design bitstream before they become functional. refer to figure 17-4 on page 17-7 and figure 17-5 on page 17-8 for more information. figure 17-3 ? i/o state when v cci is powered before v cc table 17-2 ? power-up functional ac tivation levels for v cc and v cci device v cc functional activation level (v) v cci functional activation level (v) proasic3, igloo, igloo plus, and proasic3l families running at v cc = 1.5 v* 0.85 v 0.25 v 0.9 v 0.3 v igloo, igloo plus, and proasic3l families running at v cc = 1.2 v* 0.85 v 0.2 v 0.9 v 0.15 v note: v5 devices will require a 1.5 v v cc supply, where as v2 devices can utilize either 1.2 v or 1.5 v v cc .
power-up/-down behavior of proasic3/e devices v1.1 17-7 figure 17-4 ? i/o state as a function of v cci and v cc voltage levels for igloo v5 , igloo plus v5, proasic3l, and proasic3 devices, running at v cc = 1.5 v 0.075 v region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v v cc v cc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specifcation. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v = v + vt cc cci v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification
power-up/-down behavior of low-power flash devices 17-8 v1.1 figure 17-5 ? i/o state as a function of v cci and v cc voltage levels for iglo o v2, igloo plus v2, and proasic3l devices, running at v cc = 1.2 v 0.06 v region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.14 v,1.425 v, 1.7 v, 2.3 v, or 3.0 v v cc v cc = 1.14 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.2 v deactivation trip point: v d = 0.75 v 0.2 v activation trip point: v a = 0.9 v 0.15 v deactivation trip point: v d = 0.8 v 0.15 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification. v cc = v cci + vt
power-up/-down behavior of proasic3/e devices v1.1 17-9 brownout voltage brownout is a condition in which the voltage supp lies are lower than norm al, causing the device to malfunction as a result of insufficient power. in general, actel does not guarantee the functionality of the design inside the flash fpga if voltag e supplies are below th eir minimum recommended operating condition. actel has performed measurem ents to characterize the brownout levels of fpga power supplies. refer to table 17-3 for device-specific brownout deactivation levels. for the purpose of characterization, a di rect path from the device inpu t to output is monitored while voltage supplies are lowered gradua lly. the brownout point is define d as the voltage level at which the output stops following the input. characteriza tion tests performed on several igloo, proasic3l, and proasic3 devices in typical oper ating conditions showed the brownout voltage levels to be within the specification. during device power-down, the device i/os become tristated once the first supply in the power- down sequence drops below its brownout deactivation voltage. pll behavior at br ownout condition when pll power supply voltage and/or v cc levels drop below the v cc brownout levels mentioned above for 1.5 v and 1.2 v devices, the pll output lock signal goes low and/or the output clock is lost. the following sections explain pll behavi or during and after the brownout condition. v ccpll and v cc tied together in this condition, both v cc and v ccpll drop below the 0.75 v ( 0.25 v or 0.2 v) brownout level. during the brownout recovery, once v ccpll and v cc reach the activation point (0.85 0.25 v or 0.2 v) again, the pll output lo ck signal may still remain low with the pll outp ut clock signal toggling. if this condition occurs, there are tw o ways to recover the pll output lock signal: 1. cycle the power supplies of the pll (power off and on) by using the pll powerdown signal. 2. turn off the input refere nce clock to the pll and then turn it back on. only v ccpll is at brownout in this case, only v ccpll drops below the 0.75 v ( 0.25 v or 0.2 v) brownout level and the v cc supply remains at nominal reco mmended operating voltage (1.5 v 0.075 v for 1.5 v devices and 1.2 v 0.06 v for 1.2 v devices). in this condition, the pll beha vior after brownout recovery is similar to initial power-up condition, and th e pll will regain lock automatically after v ccpll is ramped up above the activation level (0.85 0.25 v or 0.2 v). no interventi on is necessary in this case. only v cc is at brownout in this condition, v cc drops below the 0.75 v ( 0.25 v or 0.2 v) brownout level and v ccpll remains at nominal recommended operating voltage (1.5 v 0.075 v for 1.5 v devices and 1.2 v 0.06 v for 1.2 v devices). during the brownout recovery, once v cc reaches the ac tivation point again (0.85 0.25 v or 0.2 v), th e pll output lock signal may sti ll remain low with the pll output clock signal toggling. if this condition occurs, there are two ways to recover the pll output lock signal: 1. cycle the power supplies of the pll (power off and on) by using the pll powerdown signal. 2. turn off the input refere nce clock to the pll and then turn it back on. it is important to note that actel recommend s using a monotonic power supply or voltage regulator to ensure proper power-up behavior. table 17-3 ? brownout deactivation levels for v cc and v cci devices v cc brownout deactivation level (v) v cci brownout deactivation level (v) proasic3, igloo, igloo plus and proasic3l families running at v cc = 1.5 v 0.75 v 0.25 v 0.8 v 0.3 v igloo, igloo plus, and proasic3l families running at v cc = 1.2 v 0.75 v 0.2 v 0.8 v 0.15 v
power-up/-down behavior of low-power flash devices 17-10 v1.1 internal pull-up and pull-down low-power flash device i/os are equipped with internal weak pu ll-up/-down resistors that can be used by designers. if used, these internal pull-up/-down resistors wi ll be activated during power-up, once both v cc and v cci are above their functional activation level. simila rly, during power-down, these internal pull-up/-down resi stors will turn off once the first supply voltage falls below its brownout deactivation level. cold-sparing in cold-sparing applications, volt age can be applied to device i/os before and during power-up. cold-sparing applications rely on three important characteristics of the device: 1. i/os must be tristated before and during power-up. 2. voltage applied to the i/os must not power up any part of the device. 3. v cci should not exceed 3.6 v, per datasheet specifications. as described in the "power-up to functional time" section on page 17-6 , actel?s low-power flash i/os are tristated before and during po wer-up until the la st voltage supply (v cc or v cci ) is powered up past its functional level. furthermore, applying voltage to the fpga i/os does not pull up v cc or v cci and, therefore, does not pa rtially power up the device. table 17-4 includes the cold-sparing test results on a3pe600-pq208 device s. in this test, leakage curren t on the device i/o and residual voltage on the power supply rails were measur ed while voltage was ap plied to the i/o before power-up. v cci must not exceed 3.6 v, as stated in the datash eet specification. theref ore, proasic3e devices meet all three requirements stated earlier in this section and are su itable for cold-sparing applications. the following devices and families support cold-sparing: ? igloo: agl015 and agl030 ? all igloo plus ? all iglooe ? proasic3l: a3pe3000l ? proasic3: a3p015 and a3p030 ? all proasic3e ? military proasic3el: a3pe600l and a3pe3000l ? rt proasic3: rt3pe600l and rt3pe3000l the following devices and families do not support cold-sparing: ? igloo: agl060, agl125, agl250, agl600, agl1000 ? proasic3: a3p060, a3p125, a 3p250, a3p400, a3p600, a3p1000 ? proasic3l: a3p250l, a3p600l, a3p1000l ? military proasic3: a3p1000 table 17-4 ? cold-sparing test results for a3pe600 devices device i/o residual voltage (v) leakage current v cc v cci input 0 0.003 <1 a output 0 0.003 <1 a
power-up/-down behavior of proasic3/e devices v1.1 17-11 hot-swapping hot-swapping is the operation of hot insertion or hot removal of a card in a powered-up system. the i/os need to be configured in hot-insertio n mode if hot-swapping co mpliance is required. for more details on the levels of ho t-swap compatibility in low-power flash devices, refer to the "hot- swap support" section in the i/o structures chap ter of the handbook for the device you are using. the following devices and fami lies support hot-swapping: ? igloo: agl015 and agl030 ? all igloo plus ? all iglooe ? proasic3l: a3pe3000l ? proasic3: a3p015 and a3p030 ? all proasic3e ? military proasic3el: a3pe600l and a3pe3000l ? rt proasic3: rt3pe600l and rt3pe3000l the following devices and families do not support hot-swapping: ? igloo: agl060, agl125, agl250, agl600, agl1000 ? proasic3: a3p060, a3p125, a 3p250, a3p400, a3p600, a3p1000 ? proasic3l: a3p250l, a3p600l, a3p1000l ? military proasic3: a3p1000 conclusion actel's low-power flash fpgas provide an excellen t programmable logic solu tion for a broad range of applications. in addition to high performance, low cost, security, nonvolatility, and single chip, they are live at power-up (meet level 0 of the la pu classification) and offer clear and easy-to-use power-up/-down characteristics. unlike sram fpgas, low-power fl ash devices do not require any specific power-up/-down sequencing and have extremely low power-up inrush current in any power-up sequence. actel low-power flash fpgas also support both cold-sparing and hot- swapping for applications re quiring these capabilities.
power-up/-down behavior of low-power flash devices 17-12 v1.1 related documents datasheets proasic3 dc and switching characteristics http://www.actel.com/documents/pa3genspecs_ds.pdf proasic3e dc and swit ching characteristics http://www.actel.com/documents/pa3egenspecs_ds.pdf handbook documents i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in iglo oe and proasic3e device s http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf part number and revision date this document was a previously published handbook chapter that only discussed proasic3/e (power-up behavior of proasic3/e devices, part number: 51700094-021), and has now been updated to include data for igloo and proasic3l families. part number 51700094-027-1 revised october 2008
power-up/-down behavior of proasic3/e devices v1.1 17-13 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (august 2008) the "introduction" section was updated to add military proasic3el and rt proasic3 devices to the list of devices th at can have inputs driven in while the device is not powered. 17-1 the "actel?s flash families suppo rt power-up behavior" section was revised to include new families and make the information more concise. 17-2 the "cold-sparing" section was revised to add military proasic3/el and rt proasic3 devices to the li sts of devices with and wi thout cold-sparing support. 17-10 the "hot-swapping" section was revised to add military proasic3/el and rt proasic3 devices to the lists of devi ces with and without hot-swap support. 17-11 v1.3 (march 2008) this document was revised, renamed, and assigned a new part number. it now includes data for the ig loo and proasic3l families. n/a v1.2 (january 2008) 51700094-021-2 the "handbook documents" section was updated to include the three different i/o structure handbook chapters. 17-12 v1.1 (january 2008) 51700094-021-1 the first sentence of the "pll behavior at brownout condition" section was updated to read, "when pll power supply voltage and/or v cc levels drop below the v cc brownout levels (0.75 v 0.25 v), the pll output lock signal goes low and/or the output clock is lost." 17-9 v1.0 (january 2008) 51700094-021-0 the "pll behavior at brownout condition" section was added. 17-9

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