APCI-SER4 2192-09100-000-000 j592 APCI-SER4 page 1 introduction the APCI-SER4 is a 32-bit pci local bus board which provides 4 channels of rs232/422/485 serial communications. it utilises two 85230 enhanced serial communication controllers. each channel can be independently configured for asynchronous or synchronous protocols, baud rate and signalling standards. the board supports communication speeds of up to 115kbaud (asynchronous) and 1.8mbaud (synchronously). all serial channel signals are routed to a 50 way d-type connector. features ? 4 serial communications channels ? powerful and versatile 85230 enhanced serial communications controllers ? rs232, rs485 and rs422 signal levels supported ? transmit and receive fifo?s ? interrupt facility ? board access led (red) ? user led (green) ? industry standard i/o via 50 way d-type ? pci 2.1 compatible bus interface ? plug and play software compatible ? ce compliant design ? operating temperature range 0 to +70c ? power consumption 250ma@+5v, 70ma@+12, 60ma@-12v ? mtbf: 350,014 hours (using generic figures from mil-hdbk-217f at ground benign) getting started ? power down your pc system. ? install the board in a spare pci slot (see installation for ce compliance). ? power up system with msdos. ? run apci.exe (supplied on the utility disk), this will search for the board and check i/o access. if this fails, check board is correctly located. warning this board contains c c m m o o s s devices which may be damaged by static electricity. please ensure anti- static precautions are taken at all times when handling this board. if for any reason this board is returned to arcom control systems, please ensure it is adequately packed to prevent damage during shipment.
page 2 oper ation pci bus interface the pci bus is a high speed alternative to i sa bus, it has been designed to o ver come some of the limitations of i sa bus, and pro vide faster throughput for i/o intensive peripher al devices. pci bus also supports plug and play configur ation which allo ws the system softwar e to allocate r esour ces during initialisation helping to o ver come r esour ce conflicts, which might exist in a system. the apci-s e r4 uses a single chip pci bus slave controller which is designed and manufactur ed b y pl x t echnology. this device has been designed to fully support the pci 2.1 specification and pro vides plug and play softwar e capabilities. during po wer-up initialisation the pci b ios will detect the car d and assign a unique i/o addr ess location and interrupt line. this ensur es that ther e ar e no r esour ce conflicts on the pci bus. multiple car ds ar e supported through this mechanism without the need for addr ess decode links. the pl x device contains a standar d type 00h configur ation space header. the table belo w sho ws the r egisters within this header which ar e r equir ed for configur ation of the apci-s e r4. configuration space header these r egisters can be accessed using pci b ios functions. please contact ar coms customer support team (t el: 01223 412428) for a copy of the pci b ios specification if r equir ed. enhanced s erial communication contr ollers the apci-s e r4 contains two 85230 enhanced serial communication controllers (e scc), each device pro vides two full-duplex communication channels. the serial interface lines from these devices ar e buffer ed on boar d b y rs232 and rs485/422 devices. the e scc is a versatile and po werful device and r equir es car eful initialisation. f or this r eason it is r ecommended that the e scc manufactur ers manual is used. this may be obtained b y contacting ar coms customer support team (t el:01223 412428). it should be noted that these devices ar e not compatible with the pc 8250-type ua r t . the or der in which r egisters ar e initialised is important and a r egister may need to be accessed mor e than once during initialisation. unr eliable oper ation may be experienced if short cuts ar e taken. f or examples of basic e scc initialisation, please r efer to the progr ams on the utility disk. each e scc occupies four i/o locations in the apci-s e r4 indexed i/o map; two consecutive locations per channel. the lo wer addr ess of each pair is used to select the appropriate r egister within the device, and to r ead/write data to the r egister. the higher addr ess pro vides dir ect connection to the r eceive and tr ansmit data latches. the internal e scc r egisters ar e accessed using an indexed addr essing scheme like the apci-s e r4. the appropriate index must be written each time a r egister is accessed. ther efor e each r ead/write oper ation to a r egister must be pr eceded with a write to the index r egister. after a r ead/write oper ation the index is r eset to 0. 2192-09100-000-000 j592 APCI-SER4 offset 00-01h 02-03h 18-1b h 2c-2dh 2e-2f h 3ch register name v endor i d device i d base addr ess r egister subsystem v endor i d subsystem i d interrupt line description i d of pci device manufactur er i d of pci device i d of boar d manufactur er i d of boar d interrupt line assigned to device i/o base addr ess assigned to car d value 10b5h (pl x t echnology) 9050h 0000xxxx 13ab h (a r c o m) 0592h (apci-s e r4) 0x
page 3 2192-09100-000-000 j592 APCI-SER4 initialising escc control registers the follo wing procedur e is r equir ed to access the e scc r egisters. 1. w rite the control r egister index (for the appropriate channel) to the apci-s e r4 base addr ess. 2. w rite the e scc r egister index to the apci-s e r4 base+1 addr ess. 3. w rite the new data to the apci-s e r4 base+1 addr ess. 4. r epeat steps 2 and 3 for each of the e scc r egisters. transmitting and receiving data the follo wing tables sho w the steps r equir ed to tr ansmit and r eceive deta in polled mode from channel 2. transmit data receive data baud rates each serial channel has a 16-bit baud r ate counter which is used for both tr ansmit and r eceive data oper ations. in asynchronous mode, the e scc can use a x16, x32 or x64 clock. the follo wing table sho ws some typical baud r ates and their time constants, when the x16 mode is selected: the baud r ate counter is set b y writing the lo w b yte of the time constant to e scc r egister 12 (decimal) and the upper b yte to r egister 13 (decimal). as the boar d r ates sho wn in the table abo ve all have time constants of less than 256, their upper b ytes ar e all zero . interrupts the apci-s e r4 has one interrupt signal which is routed to an i r q line during the pci b ios initialisation. this interrupt line is expanded on boar d to pro vide two interrupt sour ces. these interrupts ar e connected to the output signals from the e scc devices. an interrupt sour ce r egister has been pro vided at index 10h. the interrupt service routine must r ead this r egister to determine which device gener ated the interrupt r equest. if bit 0 in this r egister is set (logic ?1?) channel 1 or 2 has r equested the interrupt, if bit 7 is set channel 3 or 4 has r equested the interrupt all other bits will be zero . action w rite 02h to the base addr ess r ead from base+1 addr ess w rite 03h to the base addr ess w rite data to be tr ansmitted to base+1 addr ess l ogically a n d the value with 04h explanation sets the apci-s e r4 to r ead r egister 0 on channel 2. r eads s tatus sets apci-s e r4 to write to data r egister on channel 2. data is written to the tr ansmit buffer if bit is set the tx buffer is empty and another b yte can be sent. if bit is zero continue to r ead status. action w rite 02h to the base addr ess r ead from base+1 addr ess w rite 03h to the base addr ess r ead from base+1 addr ess l ogically a n d the value with 01h explanation sets the apci-s e r4 to r ead r egister 0 on channel 2. r eads s tatus sets apci-s e r4 to r ead from the data r egister on channel 2. data in r eceive buffer is r ead if bit is set ther e is a b yte in the r eceive r egister. if bit is zero continue to r ead status. baud 9600 19200 38400 115200 time constant 22 10 4 0
i/o map the apci-s e r4 uses an indexed addr essing scheme to access the on-boar d devices and special function r egisters. t wo consecutive i/o locations ar e r equir ed to implement this scheme, the base addr ess is used to set the index value and the base+1 addr ess is used to access the device. the i/o base addr ess is set b y the pci b ios during initialisation (r efer to the pci b u s section of this manual for details). a pci b ios function call may be used to determine the base addr ess once the system has been initialised. multiple boar ds may be used in a system as each will be given a unique i/o addr ess. index r egisters s pecial f unction r egisters page 4 2192-09100-000-000 j592 APCI-SER4 index 00 00 01 02 02 03 04 04 05 06 06 07 08-0f 10 register name s1 c1 d1 s1 c1 d1 s1 c1 d1 s1 c1 d1 n/a i nt read/write r ead w rite r ead/w rite r ead w rite r ead/w rite r ead w rite r ead/w rite r ead w rite r ead/w rite n/a r ead comments channel 1 s tatus channel 1 control channel 1 data channel 2 s tatus channel 2 control channel 2 data channel 3 s tatus channel 3 control channel 3 data channel 4 s tatus channel 4 control channel 4 data not used interrupt line s tatus index 80 81 register name user l e d boar d ident read/write w rite r ead comments 01h s witches l e d on 00h s witches l e d of f always r eturns 10h for apci-s e r4
links throughout this section a ?+? indicates the default link position. default link p ositions ther e ar e thr ee functions defined b y the links on the apci-s e r4: whether the serial lines ar e rs232 or rs485/422 (and ho w some of them ar e connected); synchronous clock sour cing; and r eceiver enabling/disabling. the first digit of the link number r efers to the channel i.e lk13 r efers to channel 1. the links define whether some of the lines connecting to the e scc for that channel ar e at rs232 or rs485/422 levels, and in some cases which lines go to the 50-way connector. some of the serial lines ar e not affected b y these links. this is either because they have a connection on the 50-way connector , which is not shar ed with a differ ent function or level, or because the device can oper ate at either level. rs232/485 and rs422 - serial signal connections page 5 2192-09100-000-000 j592 APCI-SER4 link lk10 channel 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 ribbon cable pin no. 9 8 4 7 19 18 14 17 29 28 24 27 39 38 34 37 a+ position rs232 dtr ct s tx r t s dtr ct s tx r t s dtr ct s tx r t s dtr ct s tx r t s b position rs485/422 dcd? dtr+ tx+ dtr? dcd? dtr+ tx+ dtr? dcd? dtr+ tx+ dtr? dcd? dtr+ tx+ dtr? lk11 lk12 lk13 lk20 lk21 lk22 lk23 lk30 lk31 lk32 lk33 lk40 lk41 lk42 lk43
2192-09100-000-000 page 6 j592 APCI-SER4 s ynchr onous clock selection, r s23 2 and r s485/422 enabling/disabling ther e ar e four groups of nine pins: each group contains thr ee two-position links. they ar e lk14a-c, lk24a-c, lk34a-c and lk44a-c. the first digit of the link number r efers to the channel; the letter r efers to the function. the ?a? links control r eceiver enables. if a link is inserted in position a on one of these links, the r eceive buffer is enabled when r t s is active. if the link is in position b, the r eceive buffer is permanently enabled. the ?b? links change the function of ribbon cable wir es 3, 13, 23 and 33. p osition a connects to the rs485 tr ansmitted data signal, position b connects to the 85230 trx c clock inputs via rs232 buffers. the ?c? links change the function of ribbon cable wir es 5, 15, 25 and 35. p osition a connects to the rs485 r eceive data signal, position b connects to the 85230 r tx c clock inputs via rs232 buffers. lk14a lk14a a b+ rx buffer enabled when r t s active rx buffer is permanently enabled lk14b lk14b a b+ pin 3 of d-t ype connects rs485 tx data pin 3 of d-t ype connects to 85230 trx c clock input via rs232 buffer lk14c lk14c a b+ pin 5 of d-t ype connects to rs485 rx data pin 5 of d-t ype connects to 85230 r tx c clock input via rs232 buffer lk24a lk24a a b+ rx buffer enabled when r t s active rx buffer is permanently enabled lk24b lk24b a b+ pin 13 of d-t ype connects rs485 tx data pin 13 of d-t ype connects to 85230 trx c clock input via rs232 buffer lk24c lk24c a b+ pin 15 of d-t ype connects to rs485 rx data pin 15 of d-t ype connects to 85230 r tx c clock input via rs232 buffer lk34a lk34a a b+ rx buffer enabled when r t s active rx buffer is permanently enabled lk34b lk34b a b+ pin 23 of d-t ype connects rs485 tx data pin 23 of d-t ype connects to 85230 trx c clock input via rs232 buffer lk34c lk34c a b+ pin 25 of d-t ype connects to rs485 rx data pin 25 of d-t ype connects to 85230 r tx c clock input via rs232 buffer lk44a lk44a a b+ rx buffer enabled when r t s active rx buffer is permanently enabled lk44b lk44b a b+ pin 33 of d-t ype connects rs485 tx data pin 33 of d-t ype connects to 85230 trx c clock input via rs232 buffer lk44c lk44c a b+ pin 35 of d-t ype connects to rs485 rx data pin 35 of d-t ype connects to 85230 r tx c clock input via rs232 buffer
page 7 2192-09100-000-000 j592 APCI-SER4 user configur ation r ecor d sheet link lk10 lk11 lk12 lk13 lk20 lk21 lk22 lk23 lk30 lk31 lk32 lk33 lk40 lk41 lk42 lk43 lk14a lk14b lk14c lk24a lk24b lk24c lk34a lk34b lk34c lk44a lk44b lk44c default a a a a a a a a a a a a a a a a b b b b b b b b b b b b user
2192-09100-000-000 page 8 j592 APCI-SER4 d-50 i/o connector (p l1) pin assignments the pin assignments ar e listed with the pin number of the d-50 connector and also the pin number when a 50-way i dc ribbon cable is connected to the d-50. the pin assignments conform to the ar com signal conditioning system (scs) and may be connected to an external signal conditioning boar d. ribbon cable pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 d-type pin no. 1 34 18 2 35 19 3 36 20 4 37 21 5 38 22 6 39 23 7 40 24 8 41 25 9 42 26 10 43 27 11 44 28 12 45 29 13 46 30 14 47 31 rs232 signal name 0v 0v n/c tx1 n/c rx1 r t s1 ct s1 dtr1 dcd1 0v s e e lk14 n/c tx2 n/c rx2 r t s2 ct s2 dtr2 dcd2 0v s e e lk24 n/c tx3 n/c rx3 r t s3 ct s3 dtr3 dcd3 0v s e e lk34 n/c tx4 n/c rx4 r t s4 ct s4 dtr4 dcd4 0v s e e lk44 rs485/rs422 signal name ribbon cable pin no. d-type pin no. rs232 signal name rs485/rs422 signal name 0v 0v txb1 txa1 rxb1 rxa1 dtr b1 dtra1 43 44 45 46 47 48 49 50 15 48 32 16 49 33 17 50 n/c n/c n/c n/c -12v +12v +5v +5v n/c n/c n/c n/c -12v +12v +5v +5v dcdb1 dcd a1 0v s e e lk14 txb2 txa2 rxb2 rxa2 dtr b2 dtra2 dcdb2 dcd a2 0v s e e lk24 txb3 txa3 rxb3 rxa3 dtr b3 dtra3 dcdb3 dcd a3 0v s e e lk34 txb4 txa4 rxb4 rxa4 dtr b4 dtra4 dcdb4 dcd a4 0v s e e lk44
page 9 2192-09100-000-000 j592 APCI-SER4 installation for ce compliance t o maintain compliance with the r equir ements of the e mc dir ective (89/336/e ec), this product must be corr ectly installed. the pc system in which the boar d is housed must be ce compliant as declar ed b y the manufactur er. the type of external i/o cable r equir ed can be chosen accor ding to the notes belo w: 1. r emo ve the co ver of the pc observing any additional instructions of the pc manufactur er. 2. l ocate the boar d in a spar e pci slot and pr ess gently but firmly into place. 3. ensur e that the metal br acket attached to the boar d is fully seated. 4. fit the br acket clamping scr ew and firmly tighten this on the br acket. note:- good contact of the br acket to the chassis is essential. 5. r eplace the co ver of the pc observing any additional instructions of the pc manufactur er. cable cable length 1 metr e or less : ribbon cable satisfactory. cable 1 metr e to 3 meters : commer cial scr eened cable. > 3 meters or noisy environment : use fully scr eened cable with metal backshells e.g. ar com c ab50ce the follo wing standar ds have been applied to this product: bs e n50081-1 : 1992 generic emissions s tandar d, r esidential, commer cial, light industry bs e n50082-1 : 1992 generic immunity s tandar d, r esidential, commer cial, light industry bs e n55022 : 1995 it e emissions, class b, limits and methods.
2192-09100-000-000 page 10 j592 APCI-SER4 product information f ull information about other ar com products is available via the f f a a x x - - o o n n - - d d e e m m a a n n d d s s y y s s t t e e m m , (t elephone numbers ar e listed belo w), or b y contacting our w w e e b b s s i i t t e e in the u k at: w w w w w w . . a a r r c c o o m m . . c c o o . . u u k k , or in the u s at: w w w w w w . . a a r r c c o o m m c c o o n n t t r r o o l l s s . . c c o o m m u u s s e e f f u u l l c c o o n n t t a a c c t t i i n n f f o o r r m m a a t t i i o o n n c c u u s s t t o o m m e e r r s s u u p p p p o o r r t t s s a a l l e e s s t el: +44 (0)1223 412 428 t el: +44 (0)1223 411 200 f ax: +44 (0)1223 403 400 f ax: +44 (0)1223 410 457 e-mail: support@ar com.co .uk e-mail sales@ar com.co .uk or for the us e-mail icpsales@ar comcontrols.com u u n n i i t t e e d d k k i i n n g g d d o o m m arcom control systems ltd clifton road cambridge cb1 4wh, uk tel: 01223 411 200 fax: 01223 410 457 fod: 01223 240 600 u u n n i i t t e e d d s s t t a a t t e e s s arcom control systems inc 13510 south oak street kansas city mo 64145 usa tel: 816 941 7025 fax: 816 941 0343 fod: 800 747 1097 f f r r a a n n c c e e arcom control systems centre d?affaires scaldy 23 rue colbert 7885 saint quentin cedex, france tel: 0800 90 84 06 fax: 0800 90 84 12 fod: 0800 90 23 80 g g e e r r m m a a n n y y kostenlose infoline: tel: 0130 824 511 fax: 0130 824 512 fod: 0130 860 449 i i t t a a l l y y numeroverde: fod: 1678 73600 b b e e l l g g i i u u m m groen nummer: tel: 0800 7 3192 fax: 0800 7 3191 n n e e t t h h e e r r l l a a n n d d s s gratis 06 nummer: tel: 06022 11 36 fax: 06022 11 48 the choice of boards or systems is the responsibility of the buyer, and the use to which they are put cannot be the liability o f arcom control systems ltd. however, arcom?s sales team is always available to assist you in making your decision. arcom control systems ltd operate a company-wide quality management system which has been certified by the british standards institution (bsi) as compliant with iso9001:1994 r evision histor y manual issue a v1 iss 1 980313 first r eleased in this format. pcb comments ? 1997 arcom control systems ltd arcom control systems is a subsidiary of fairey group plc. specifications are subject to change without notice and do not form part of any contract. all trademarks recognised.
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