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  user?s manual v850es/fx3-l 32-bit single-chip microcontroller hardware v850es/fe3-l: pd70f3610 pd70f3611 pd70f3612 pd70f3613 pd70f3614 document no. u18743ee1v2um00 date published june 2008 ? nec electronics 2008 printed in germany v850es/ff3-l: pd70f3615 pd70f3616 pd70f3617 pd70f3618 pd70f3619 v850es/fg3-l: pd70f3620 pd70f3621 pd70f3622
2 user?s manual u18743ee1v2um00
3 user?s manual u18743ee1v2um00 notes for cmos devices 1. precaution against esd for semiconductors strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2. handling of unused input pins for cmos no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull- down circuitry. each unused pin should be connected to vdd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3. status before initialization of mos devices power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 user?s manual u18743ee1v2um00 legal notes  the information in this document is current as of june 2008. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/ or types are available in every country. please check with an nec sales representative for availability and additional information.  no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document.  nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such nec electronics products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others.  descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.  while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire- containment and anti-failure features.  nec electronics products are classified into the following three quality grades: ?standard?, ?special? and ?specific?. the "specific" quality grade applies only to nec electronics products developed based on a customer-designated ?quality assurance program? for a specific application. the recommended applications of nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.
5 user?s manual u18743ee1v2um00 the quality grade of nec electronics products is ?standard? unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact nec electronics sales representative in advance to determine nec electronics 's willingness to support a given application. note 1. "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. 2. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). 3. superflash ? is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. this product uses superflash ? technology licensed from silicon storage technology, inc. caution this document is a draft (a momentary snapshot) of a document under work. future versions of this document will not hold a history list of changes towards this draft document.
6 user?s manual u18743ee1v2um00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify:  device availability  ordering information  product release schedule  availability of related technical literature  development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth)  network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. for further information please contact: nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044 4355111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554,| u.s.a. tel: 408 5886000 http://www.am.necel.com/ [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211 6503-0 http://www.eu.necel.com/ united kingdom branch cygnus house, sunrise parkway linford wood milton keynes, mk14 6np, u.k. tel: 01908 691133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01 30675800 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 6387200 filiale italiana via fabio filzi, 25a 20124 milano, italy tel: 02 667541 branch the netherlands steijgerweg 6 5616 hs eindhoven, the netherlands tel: 040 2654010 [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010 82351155 http://www.cn.necel.com/ nec electronics shanghai ltd. room 2511-2512, bank of china tower, 200 yincheng road central, pudong new area, shanghai 200120, p.r. china tel: 021 5888 5400 http://www.cn.necel.com/ nec electronics hong kong ltd. unit 1601-1613, 16/f., tower 2 grand century place 193 prince edward road west, mongkok, kowloon, hong kong tel: 2886 9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r.o.c. tel: 02 8175-9600 nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/
7 user?s manual u18743ee1v2um00 preface readers this manual is intended for users who want to understand the functions of the concerned microcontrollers. purpose this manual presents the hardware manual for the concerned microcontrollers. organization this system specification describes the following sections:  pin function  cpu function  internal peripheral function module instances these microcontrollers may contain several instances of a dedicated module. in general the different instances of such modules are identified by the index ?n?, where ?n? counts from 0 to the number of instances minus one. legend symbols and notation are used as follows:  weight in data notation: left is high order column, right is low order column  active low notation: xxx (pin or signal name is over-scored) or /xxx (slash before signal name)  memory map address: high order at high stage and low order at low stage note additional remark or tip caution item deserving extra attention numeric notation:  binary: xxxx or xxx b  decimal: xxxx  hexadecimal: xxxx h or 0x xxxx prefixes representing powers of 2 (address space, memory capacity): k (kilo): 2 10 = 1024  m (mega): 2 20 = 1024 2 = 1,048,576 g (giga): 2 30 = 1024 3 = 1,073,741,824 register contents: x, x = don?t care diagrams block diagrams do not necessarily show the exact wiring in hardware but the functional structure. timing diagrams are for functional explanation purposes only, without any relevance to the real hardware implementation.
8 user?s manual u18743ee1v2um00 related documents the related documents indicated in this publication may include preliminary versions. preliminary versions are not marked as such. refer to http://www.eu.necel.com/docuweb/ to obtain the latest version of above documents. further information for further information see http://www.ee.nec.de . document name document no. v850es user?s manual architecture u15943ej3v0um00 self-programming application note u16929ee3v0an00
9 user?s manual u18743ee1v2um00 table of contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.2 features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3.1 internal units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3.2 structure of the manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.1 v850es/fe3-l ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4.2 v850es/ff3-l ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.4.3 v850es/fg3-l ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 chapter 2 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.2 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.1.3 noise elimination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 port group configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2.2 pin function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.3 pin data input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.2.4 configuration of pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.2.5 open drain configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.3 port buffers diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.4 port type diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.4.1 port type c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.4.2 port type c-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4.3 port type d0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.4 port type d0-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.5 port type d1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.4.6 port type d1-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.4.7 port type d1-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.4.8 port type d3-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.4.9 port type d1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.4.10 port type d1o1-ui. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.4.11 port type d2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.4.12 port type e01-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.4.13 port type e10-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.14 port type e10-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.15 port type e11-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.4.16 port type e11-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.17 port type e21-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.18 port type ex0-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.4.19 port type ex1-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.4.20 port type ex1-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.4.21 port type ex2-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4.22 port type f010x-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4.23 port type f010x-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10 table of contents user?s manual u18743ee1v2um00 2.4.24 port type f100x-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.25 port type f1010-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.4.26 port type f101x-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.4.27 port type f1100o0-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.4.28 port type f1100o1-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.4.29 port type f1100-u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.4.30 port type f1110-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.4.31 port type f113x-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.4.32 port type f1x10-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.4.33 port type f3x1x-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.4.34 port type f1xx0o1-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.4.35 port type fx010-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.4.36 port type fx01x-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.4.37 port type fx103-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.4.38 port type fx10x-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 2.4.39 port type fx10x-ui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.4.40 port type fx110-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.4.41 port type fx120-ufi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.4.42 port type fx123-ufi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.4.43 port type fx12x-ufi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.4.44 port type fx13x-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.4.45 port type fx210-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 2.4.46 port type fx2x0-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2.4.47 port type fxx10-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.4.48 port type fxx1x-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.49 port type fxx2x-u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.5 port group configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.5.1 port group configuration lists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.5.2 alphabetic pin function list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 2.5.3 port group 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.5.4 port group 1 (v850es/fg3-l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.5.5 port group 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.5.6 port group 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.5.7 port group 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.5.8 port group 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.5.9 port group 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.5.10 port group cm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.5.11 port group cs (v850es/ff3-l, v850es/fg3-l) . . . . . . . . . . . . . . . . . . . . 123 2.5.12 port group ct (v850es/ff3-l, v850es/fg3-l) . . . . . . . . . . . . . . . . . . . . 124 2.5.13 port group dl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 2.6 noise elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.6.1 analog filtered inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.6.2 digitally filtered inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 2.7 pin functions in reset and power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.8 recommended connection of unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 2.9 package pins assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 2.9.1 v850es/fe3-l package pins assignment. . . . . . . . . . . . . . . . . . . . . . . . . . 132 2.9.2 v850es/ff3-l package pins assignment. . . . . . . . . . . . . . . . . . . . . . . . . . 133 2.9.3 v850es/fg3-l package pins assignment . . . . . . . . . . . . . . . . . . . . . . . . . 134
11 table of contents user?s manual u18743ee1v2um00 chapter 3 cpu system functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 3.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 3.2 cpu register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.2.1 general purpose registers (r0 to r31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.2.2 system register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 3.3 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.3.1 normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.3.2 flash programming mode (flash memory devices only) . . . . . . . . . . . . . . . 146 3.3.3 on-chip debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 3.4 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 3.4.1 cpu address space and physical address space . . . . . . . . . . . . . . . . . . . . 147 3.4.2 program and data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3.5 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.5.1 memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.5.2 recommended use of data address space. . . . . . . . . . . . . . . . . . . . . . . . . 154 3.6 write protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 3.6.1 write protection control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 chapter 4 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.1.2 clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.1.3 power save modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.1.4 start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.2 clock generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.2.1 general clock generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.2.2 pll control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.2.3 stand-by control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.2.4 prescaler3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.2.5 clock monitor control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 4.2.6 selector control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 4.3 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.3.1 option byte 0000 007a h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.3.2 option byte 0000 007b h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 4.4 clock generator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.4.1 overview of clock operation control settings. . . . . . . . . . . . . . . . . . . . . . . . 191 4.4.2 operation state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 4.4.3 power save modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.4.4 available clocks in power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.4.5 power save mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.4.6 controlling the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.4.7 watch dog timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.4.8 clkout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.4.9 operation of prescaler3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 4.4.10 operation of the clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 chapter 5 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
12 table of contents user?s manual u18743ee1v2um00 5.2 non-maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 5.2.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 5.2.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 5.2.3 non-maskable interrupt status flag (np) . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 5.2.4 nmi control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 5.3 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.3.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 5.3.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 5.3.3 priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 5.3.4 xxicn - maskable interrupt control registers . . . . . . . . . . . . . . . . . . . . . . . . 237 5.3.5 imrm - interrupt mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 5.3.6 ispr - in-service priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 5.3.7 maskable interrupt status flag (id) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.3.8 external maskable interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.4 external interrupts edge detection configuration . . . . . . . . . . . . . . . . . . . . . . . . 244 5.5 software exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 5.5.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 5.5.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 5.5.3 exception status flag (ep). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 5.6 exception trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 5.6.1 illegal opcode definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 5.6.2 debug trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 5.7 multiple interrupt processing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 5.8 interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 5.9 periods in which interrupts are not acknowledged . . . . . . . . . . . . . . . . . . . . . . . 255 chapter 6 key interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 6.1 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 6.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 6.3 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 chapter 7 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 7.1 code flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 7.1.1 code flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 7.1.2 code flash memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 7.1.3 code flash memory functional outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 7.1.4 code flash memory erasure and rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 7.2 flash programming with flash programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 7.2.1 programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 7.2.2 communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 7.2.3 pin connection with flash programmer pg-fp4 . . . . . . . . . . . . . . . . . . . . . 269 7.2.4 flash memory programming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 7.3 code flash self-programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 7.3.1 self-programming enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 7.3.2 self-programming library functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 7.3.3 secure self-programming (boot cluster swapping) . . . . . . . . . . . . . . . . . . . 279 7.3.4 interrupt handling during flash self-programming . . . . . . . . . . . . . . . . . . . . 283 7.4 variable reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 7.5 flash mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
13 table of contents user?s manual u18743ee1v2um00 7.5.1 prdselh register - product selection code register high . . . . . . . . . . . . . 288 chapter 8 data protection and security . . . . . . . . . . . . . . . . . . . . . . . . 289 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 8.2 n-wire debug interface protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 8.3 flash programmer and self-programming protection . . . . . . . . . . . . . . . . . . . . 291 chapter 9 bus control unit (bcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 9.1.1 peripheral i/o area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 9.1.2 npb access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 9.1.3 bus properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 9.1.4 boundary operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 9.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 9.2.1 bcu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 chapter 10 16-bit timer/event counter aa . . . . . . . . . . . . . . . . . . . . . . 305 10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 10.2 function outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.4 input selection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 10.5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 10.6 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 10.6.1 anytime write and reload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 10.6.2 interval timer mode (taanmd2 to taanmd0 = 000 b ) . . . . . . . . . . . . . . . . 331 10.6.3 external event counter mode (taanmd2 to taanmd0 = 001 b ). . . . . . . . . 335 10.6.4 external trigger pulse mode (taanmd2 to taanmd0 = 010 b ). . . . . . . . . . 339 10.6.5 one-shot pulse mode (taanmd2 to taanmd0 = 011 b ) . . . . . . . . . . . . . . 342 10.6.6 pwm mode (taanmd2 to taanmd0 = 100 b ) . . . . . . . . . . . . . . . . . . . . . . 345 10.6.7 free-running mode (taanmd2 to taanmd0 = 101 b ) . . . . . . . . . . . . . . . . 350 10.6.8 pulse width measurement mode (taanmd2 to taanmd0 = 110b)356 10.6.9 32-bit capture in free-running cascade mode . . . . . . . . . . . . . . . . . . . . . 363 10.6.10 capture operation on delayed input clock . . . . . . . . . . . . . . . . . . . . . . . . . . 368 chapter 11 16-bit interval timer m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 11.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 11.3 timer m registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 11.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 11.4.1 interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 11.4.2 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 chapter 12 timer aa synchroneous operation . . . . . . . . . . . . . . . . 377 chapter 13 watch timer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 13.1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 13.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
14 table of contents user?s manual u18743ee1v2um00 13.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.4.1 operation as watch timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 13.4.2 operation as interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 13.4.3 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 chapter 14 watchdog timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 14.1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 14.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 14.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 14.4 watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 14.5 watchdog timer operation in power save mode . . . . . . . . . . . . . . . . . . . . . . . . . 390 chapter 15 asynchronous serial interface (uartd) . . . . . . . . . . . 391 15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 15.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 15.3 uartd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 15.4 interrupt request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 15.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 15.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 15.5.2 sbf transmission/reception format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 15.5.3 sbf transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 15.5.4 sbf reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 15.5.5 data consistency check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 15.5.6 uart transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 15.5.7 continuous transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 15.5.8 uart reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 15.5.9 reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 15.5.10 parity types and operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 15.5.11 receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 15.6 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 15.7 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 chapter 16 clocked serial interface (csib) . . . . . . . . . . . . . . . . . . . . . 427 16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 16.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 16.3 csib control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 16.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 16.4.1 single transfer mode (master mode, transmission/reception mode). . . . . . 436 16.4.2 single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . 438 16.4.3 continuous mode (master mode, transmission/reception mode) . . . . . . . . 439 16.4.4 continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 440 16.4.5 continuous reception mode (error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 16.4.6 continuous mode (slave mode, transmission/reception mode) . . . . . . . . . 442 16.4.7 continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . 445 16.4.8 clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 16.5 output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 16.6 operation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
15 table of contents user?s manual u18743ee1v2um00 chapter 17 i 2 c bus (iic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 17.2 i 2 c pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 17.3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 17.4 iic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 17.5 i 2 c bus mode functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 17.5.1 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 17.6 i 2 c bus definitions and control methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 17.6.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 17.6.2 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 17.6.3 transfer direction specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 17.6.4 acknowledge signal (ack ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 17.6.5 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 17.6.6 wait signal (wait ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 17.7 i 2 c interrupt request signals (intiicn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 17.7.1 master device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 17.7.2 slave device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 17.7.3 slave device operation (when receiving extension code) . . . . . . . . . . . . . . 495 17.7.4 operation without communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 17.7.5 arbitration loss operation (operation as slave after arbitration loss) . . . . . . 499 17.7.6 operation when arbitration loss occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 17.8 interrupt request signal (intiicn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.9 address match detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.10 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.11 extension code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 17.12 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 17.13 wakeup function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 17.14 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 17.15 communication operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 17.15.1 master operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 17.15.2 master operation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 17.15.3 slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 17.16 timing of data communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 chapter 18 can controller (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 18.1.1 overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 18.1.2 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 18.2 can protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 18.2.1 frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 18.2.2 frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 18.2.3 data frame and remote frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 18.2.4 error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 18.2.5 overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 18.3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 18.3.1 determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 18.3.2 bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 18.3.3 multi masters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 18.3.4 multi cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
16 table of contents user?s manual u18743ee1v2um00 18.3.5 can sleep mode/can stop mode function . . . . . . . . . . . . . . . . . . . . . . . . . 542 18.3.6 error control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 18.3.7 baud rate control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 18.4 connection with target system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 18.5 internal registers of can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 18.5.1 can module register and message buffer addresses . . . . . . . . . . . . . . . . 553 18.5.2 can controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 18.5.3 can registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 18.5.4 register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 18.6 bit set/clear function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 18.7 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 18.8 can controller initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 18.8.1 initialization of can module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 18.8.2 initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 18.8.3 redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 18.8.4 transition from initialization mode to operation mode. . . . . . . . . . . . . . . . . 600 18.8.5 resetting error counter cnerc of can module. . . . . . . . . . . . . . . . . . . . . 601 18.9 message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 18.9.1 message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 18.9.2 receive data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 18.9.3 receive history list function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 18.9.4 mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 18.9.5 multi buffer receive block function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 18.9.6 remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 18.10 message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 18.10.1 message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 18.10.2 transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 18.10.3 automatic block transmission (abt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 18.10.4 transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 18.10.5 remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 18.11 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 18.11.1 can sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 18.11.2 can stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 18.11.3 example of using power saving modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 18.12 interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 18.13 diagnosis functions and special operational modes . . . . . . . . . . . . . . . . . . . . . 624 18.13.1 receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 18.13.2 single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 18.13.3 self-test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 18.13.4 receive/transmit operation in each operation mode. . . . . . . . . . . . . . . . . . 627 18.14 time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 18.14.1 time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 18.15 baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 18.15.1 baud rate setting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 18.15.2 representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . 633 18.16 operation of can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 chapter 19 a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 19.1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 19.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
17 table of contents user?s manual u18743ee1v2um00 19.3 adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 19.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 19.4.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 19.4.2 trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 19.4.3 operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 19.4.4 power-fail compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 19.5 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 19.6 how to read a/d converter characteristics table . . . . . . . . . . . . . . . . . . . . . . . . . 696 chapter 20 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 20.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 20.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 20.3 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 chapter 21 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 21.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 21.1.1 general reset performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 21.1.2 reset at power-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 21.1.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 21.1.4 reset by watchdog timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 21.1.5 reset by clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 21.1.6 reset by low-voltage detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 21.2 reset registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 chapter 22 low-voltage detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 22.1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 22.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 22.3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 22.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 22.4.1 reset generation from lvi (lvim.lvimd = 1) . . . . . . . . . . . . . . . . . . . . . . 719 22.4.2 interrupt generation from lvi (lvim.lvimd = 0) . . . . . . . . . . . . . . . . . . . . 720 22.4.3 disabling the lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 22.4.4 ram retention voltage detection operation . . . . . . . . . . . . . . . . . . . . . . . . . 722 chapter 23 on-chip debug unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 23.1 functional outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 23.1.1 debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 23.2 controlling the n-wire interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 23.3 n-wire enabling methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 23.3.1 starting normal operation after reset and respoc . . . . . . . . . . . . . . . . 728 23.3.2 starting debugger after reset and respoc . . . . . . . . . . . . . . . . . . . . . . 728 23.3.3 n-wire activation by reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 23.4 connection to n-wire emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 23.4.1 kel connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 23.5 restrictions and cautions on on-chip debug function . . . . . . . . . . . . . . . . . . . 734 chapter 24 differences fx3-l to fx3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
18 table of contents user?s manual u18743ee1v2um00 appendix a special function registers . . . . . . . . . . . . . . . . . . . . . . . . . 737 a.1 can registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 a.2 other special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 appendix b registers access times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 b.1 timer aa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 b.2 timer m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 b.3 watchdog timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 b.4 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 b.5 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 b.6 asynchronous serial interface (uartd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 b.7 clocked serial interface (csib) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 b.8 can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 b.9 all other registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
19 user?s manual u18743ee1v2um00 chapter 1 introduction the v850es/fx3-l is a product line in nec electronics? v850 family of single- chip microcontrollers designed for automotive applications. 1.1 general the v850es/fx3-l single-chip microcontroller devices make the performance gains attainable with 32-bit risc-based controllers available for embedded control applications. the integrated v850es cpu offers easy pipeline handling and programming, resulting in compact code size comparable to 16-bit cisc cpus. the v850es/fx3-l devices provide an excellent combination of general purpose peripheral functions like serial communication interfaces, timers/ counters, measurement and control functions, with full can network support. the devices offer specific power-saving modes to manage the power consumption effectively under varying conditions. thus equipped, the v850es/fx3-l product line is ideally suited for automotive body applications. it is also an excellent choice for other applications where a combination of sophisticated peripheral functions and can network support is required. (1) v850es cpu the v850es cpu core is a 32-bit risc processor. through the use of basic instructions that can be executed in one clock period combined with an optimized pipeline architecture, it achieves marked improvements in instruction execution speed. in addition, to make it ideal for use in digital control applications, a 32-bit hardware multiplier supports multiply instructions, saturated multiply instructions, bit operation instructions, etc. through two-byte basic instructions and instructions compatible with high level languages, the object code efficiency in a c compiler is increased, and program size can be reduced. further, because the on-chip interrupt controller provides high-speed interrupt response and processing, the devices are well suited for high level real-time control applications. (2) on-chip flash memory the v850es/fx3-l microcontrollers have on-chip flash memory. it is possible to program the controllers directly in the target environment where they are mounted. with this feature, system development time can be reduced and system maintainability after shipping can be markedly improved.
20 chapter 1 introduction user?s manual u18743ee1v2um00 (3) a full range of software development tools a development system is available that includes an optimized c compiler, debugger, in-circuit emulator, simulator, system performance analyzer, and other elements. 1.2 features summary the v850es/fx3-l series includes the following microcontrollers:  v850es/fe3-l ? pd70f3610 ? pd70f3611 ? pd70f3612 ? pd70f3613 ? pd70f3614  v850es/ff3-l ? pd70f3615 ? pd70f3616 ? pd70f3617 ? pd70f3618 ? pd70f3619  v850es/fg3-l ? pd70f3620 ? pd70f3621 ? pd70f3622 the common cpu core provides:  81 instructions  32 general registers (32 bits each)  comprehensive instruction set: ? v850es (compatible with v850 plus added powerful instructions for reducing code and increasing execution speed) ? signed multiplication (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits) in 1 to 5 clocks ? saturated operation instructions (with overflow/underflow detection) ? 32-bit shift instructions in 1 clock cycle ? bit manipulation instructions ? load/store instructions with long/short format ? signed load instructions
21 introduction chapter 1 user?s manual u18743ee1v2um00 the following table gives an overview of the most outstanding controller features. table 1-1 v850es/fx3-l features (1/2) series name v850es/fe3-l v850es/ff3-l v850es/fg3-l product ?f3610 ?f3611 ?f3612 ?f3613 ?f3614 ?f3615 ?f3616 ?f3617 ?f3618 ?f3619 ?f3620 ?f3621 ?f3622 cpu v850es (32 bit risc) internal memory code flash 64 kb 96 kb 128 kb 192 kb 256 kb 64 kb 96 kb 128 kb 192 kb 256 kb 128 kb 192 kb 256 kb ram 6 kb 6 kb 8 kb 12 kb 16 kb 6 kb 6 kb 8 kb 12 kb 16 kb 8 kb 12 kb 16 kb operating clock max. cpu frequency 20 mhz pll ratio x 8 mainosc operates on 4 mhz to 16 mhz crystal subosc operates on rc or crystal low speed internal oscillator typ. 240 khz high speed internal oscillator typ. 8 mhz i/o ports 51 67 84 timers ta a 5 ch tmm 1 ch watch 1 ch wdt2 1 ch a/d converter 10 bits x 10 ch 10 bits x 12 ch 10 bits x 16 ch serial interfaces uart/lin 2 ch 3 ch csi 2 ch iic 1 ch can 1 ch
22 chapter 1 introduction user?s manual u18743ee1v2um00 interrupts external (incl. nmi) 9 ch 12 ch internal 39 ch 42 ch other functions power save modes halt, idle1, idle2, sub_idle, stop key return input 8 ch clock monitor ye s poc power-on-clear typical below 3.5 v a lvi low-voltage detection typical below 3.7 v / 4.0 v (selectable by software) a on-chip debug ye s operating voltage 3.3 v to 5.5 v a package 64-pin qfp 80-pin qfp 100-pin qfp a) refer to electrical target specification table 1-1 v850es/fx3-l features (2/2) series name v850es/fe3-l v850es/ff3-l v850es/fg3-l product ?f3610 ?f3611 ?f3612 ?f3613 ?f3614 ?f3615 ?f3616 ?f3617 ?f3618 ?f3619 ?f3620 ?f3621 ?f3622
23 introduction chapter 1 user?s manual u18743ee1v2um00 1.3 description the following figure provides a functional block diagram of the v850es/fe3-l, v850es/ff3-l, and v850es/fg3-l microcontrollers. figure 1-1 v850es/fe3-l, v850es/ff3-l, v850es/fg3-l block diagram bus control unit internal bus power supply key interrupt ports p00 to p06 p10 tp p11 p70 to 715 p90 to p915 p50 to p55 p40 to p42 p30 to p39 kr0 to kr7 interrupt controller nmi intp0 to intp7 code flash memory ram pcm0 to pcm3 pcs0 to pcs1 pct0,1,4,6 pdl0 to pdl13 ddi ddo dck drst on-chip debug unit dms main oscillator with pll x1 x2 xt1 xt2 sub oscillator internal oscillator 240 khz pcl clock monitor clock generator memory access power and reset 16-bit timers taa0 to taa4 tiaa00 to tiaa40 tiaa01 to tiaa41 toaa00 to toaa40 toaa01 to toaa41 timers auxiliary functions bus bridge cpu core system controller standby controller cpu reset poc clkout low voltage detector internal oscillator 8 mhz 16-bit timer m watch timer watchdog timer 2 internal timers intp8 to intp11 serial interfaces sda00 scl00 can0 crxd0 ctxd0 i 2 c csib0 to csib1 sib0 to sib1 sob0 to sob1 sckb0 to sckb1 brg uartd0 to uartd1 rxdd0 to rxdd1 asckd0 txdd0 to txdd1 brg uartd2 rxdd2 txdd2 brg note 1 10-bit adc 10/12/16 channels adtrg avref0 avss control interfaces ani12 to ani15 note 3 ani0 to ani9 ani10 to ani11 note 2 note 2,3 note 4 note 5 note 6 note 1
24 chapter 1 introduction user?s manual u18743ee1v2um00 table 1-2 on page 24 summarizes the different features of the v850es/fe3-l, v850es/ff3-l, v850es/fg3-l series devices, marked as ?notes? in figure 1-1 on page 23 . table 1-2 v850es/fe3-l, v850es/ff3-l, v850es/fg3-l feature set differences note feature v850es/fe3-l v850es/ff3-l v850es/fg3-l 1intp8,9,10, uartd2 ?? 2 ani10 to ani11 ? ? 3 ani12 to ani15 ?? 4 code flash refer to ?memory? on page 151 5 ram refer to ?memory? on page 151 6 ports refer to ?pin functions? on page 31
25 introduction chapter 1 user?s manual u18743ee1v2um00 1.3.1 internal units cpu the cpu can execute almost all instruction processing, such as address calculation, arithmetic and logic operations, and data transfer, in one clock under control of a five-stage pipeline. dedicated hardware units such as a multiplier and a 32-bit barrel shifter are provided to speed up complicated instruction processing. bus control unit the bus control unit (bcu) and memory controller (memc) control the access to on-chip peripheral i/os. rom the rom consists of an internal flash memory and consists of the code flash. for the available sizes, refer to table 1-1 on page 21 . ram for the available ram sizes, refer to table 1-1 on page 21 . ports general-purpose port functions and control pin functions are available. clock generator the clock generator generates the system clocks. it has four independent oscillators to ensure system operability if the main oscillator should fail and to provide low-speed clocks in power-save modes. clock monitor the clock monitor monitors the main oscillator. in case of failure, it can switch the system to a different oscillator. on-chip debug function an on-chip debug function that uses the n-wire interface is provided. interrupt controller the interrupt controller (intc) processes non-maskable and maskable interrupt requests from the on-chip peripheral hardware and external sources. eight levels of priorities can be specified for these interrupt requests, and multiple servicing control can be performed on interrupt sources. key interrupt function a key interrupt request signal can be generated by applying a falling edge to key input pins on eight channels. uartd the uarts provide 2-wire asynchronous serial interfaces. csib the clocked serial interfaces are 3-wire variable-length serial interfaces. can controller the can controller is a small-scale digital data transmission system that transfers data between units. a/d converter this is a high-speed, high-resolution 10-bit a/d converter with 24 analog input pins. this converter is of successive approximation type. timers/counters five 16-bit timers/event counters taa and one 16-bit interval timer tmm are provided. watch timer the watch timer (wt) output forms the reference for the bookkeeping of daytime and calendar. watchdog timer 2 the watchdog timer (wdt2) is used to detect a program loop and system errors. when the watchdog timer overflows, it generates a non-maskable interrupt request signal or a system reset signal. 1.3.2 structure of the manual this manual explains how to use the v850es/fx3-l microcontroller devices. it provides comprehensive information about the building blocks, their features, and how to set registers in order to enable or disable specific functions. the manual provides individual chapters for the building blocks. these chapters are organized according to the grouping in the diagram.
26 chapter 1 introduction user?s manual u18743ee1v2um00  core functions ?pin functions? on page 31 ?cpu system functions? on page 135 ?clock generator? on page 179 ?interrupt controller (intc)? on page 221 ?key interrupt function? on page 257  memory access ?flash memory? on page 259 timers ?16-bit timer/event counter aa? on page 305 ?16-bit interval timer m? on page 371 ?watch timer functions? on page 379 ?watchdog timer 2? on page 385  serial interfaces ?asynchronous serial interface (uartd)? on page 391 ?clocked serial interface (csib)? on page 427 ?i 2 c bus (iic)? on page 457 ?can controller (can)? on page 527  control interfaces ?a/d converter (adc)? on page 663  power and reset ?power supply scheme? on page 701 ?reset? on page 705 ?low-voltage detector? on page 713  auxiliary functions ?on-chip debug unit? on page 723
27 introduction chapter 1 user?s manual u18743ee1v2um00 1.4 ordering information 1.4.1 v850es/fe3-l ordering information part number package on-chip flash memory quality grade a remark upd70f3610m1gba-gah-ax 64-pin plastic lqfp (0.5mm, 10 x 10 mm 2 ) 64 kb a without power-on- clear circuit upd70f3610m1gba1-gah-ax a1 upd70f3610m1gba2-gah-ax a2 upd70f3610m2gba-gah-ax a with power-on- clear circuit upd70f3610m2gba1-gah-ax a1 upd70f3610m2gba2-gah-ax a2 upd70f3610m1gaa-gan-ax 64-pin plastic lqfp (0.4mm, 7x 7mm 2 ) a without power-on- clear circuit upd70f3610m1gaa1-gan-ax a1 upd70f3610m1gaa2-gan-ax a2 upd70f3610m2gaa-gan-ax a with power-on- clear circuit upd70f3610m2gaa1-gan-ax a1 upd70f3610m2gaa2-gan-ax a2 upd70f3611m1gba-gah-ax 64-pin plastic lqfp (0.5mm, 10 x 10 mm 2 ) 96 kb a without power-on- clear circuit upd70f3611m1gba1-gah-ax a1 upd70f3611m1gba2-gah-ax a2 upd70f3611m2gba-gah-ax a with power-on- clear circuit upd70f3611m2gba1-gah-ax a1 upd70f3611m2gba2-gah-ax a2 upd70f3611m1gaa-gan-ax 64-pin plastic lqfp (0.4mm, 7x 7mm 2 ) a without power-on- clear circuit upd70f3611m1gaa1-gan-ax a1 upd70f3611m1gaa2-gan-ax a2 UPD70F3611M2GAA-GAN-AX a with power-on- clear circuit upd70f3611m2gaa1-gan-ax a1 upd70f3611m2gaa2-gan-ax a2 upd70f3612m1gba-gah-ax 64-pin plastic lqfp (0.5mm, 10 x 10 mm 2 ) 128 kb a without power-on- clear circuit upd70f3612m1gba1-gah-ax a1 upd70f3612m1gba2-gah-ax a2 upd70f3612m2gba-gah-ax a with power-on- clear circuit upd70f3612m2gba1-gah-ax a1 upd70f3612m2gba2-gah-ax a2 upd70f3612m1gaa-gan-ax 64-pin plastic lqfp (0.4mm, 7x 7mm 2 ) a without power-on- clear circuit upd70f3612m1gaa1-gan-ax a1 upd70f3612m1gaa2-gan-ax a2 upd70f3612m2gaa-gan-ax a with power-on- clear circuit upd70f3612m2gaa1-gan-ax a1 upd70f3612m2gaa2-gan-ax a2
28 chapter 1 introduction user?s manual u18743ee1v2um00 upd70f3613m1gba-gah-ax 64-pin plastic lqfp (0.5mm, 10 x 10 mm 2 ) 192kb a without power-on- clear circuit upd70f3613m1gba1-gah-ax a1 upd70f3613m1gba2-gah-ax a2 upd70f3613m2gba-gah-ax a with power-on- clear circuit upd70f3613m2gba1-gah-ax a1 upd70f3613m2gba1-gah-ax a1 upd70f3614m1gba-gah-ax 256kb a without power-on- clear circuit upd70f3614m1gba1-gah-ax a1 upd70f3614m1gba2-gah-ax a2 upd70f3614m2gba-gah-ax a with power-on- clear circuit upd70f3614m2gba1-gah-ax a1 upd70f3614m2gba1-gah-ax a1 a) the operating ambient temperature of each quality grades is as follows: a: -40 to +85 c, a1: -40 to +110 c, a2: -40 to +125 c part number package on-chip flash memory quality grade a remark
29 introduction chapter 1 user?s manual u18743ee1v2um00 1.4.2 v850es/ff3-l ordering information part number package on-chip flash memory quality grade a remark upd70f361m1gba-gah-ax 80-pin plastic lqfp (0.5mm, 12 x 12 mm 2 ) 64 kb a without power-on- clear circuit upd70f3615m1gba1-gah-ax a1 upd70f3615m1gba2-gah-ax a2 upd70f3615m2gba-gah-ax a with power-on- clear circuit upd70f3615mgba1-gah-ax a1 upd70f3615m2gba2-gah-ax a2 upd70f3616m1gba-gah-ax 96 kb a without power-on- clear circuit upd70f3616m1gba1-gah-ax a1 upd70f3616m1gba2-gah-ax a2 upd70f3616m2gba-gah-ax a with power-on- clear circuit upd70f3616m2gba1-gah-ax a1 upd70f3616m2gba2-gah-ax a2 upd70f3617m1gba-gah-ax 128 kb a without power-on- clear circuit upd70f3617m1gba1-gah-ax a1 upd70f3617m1gba2-gah-ax a2 upd70f3617m2gba-gah-ax a with power-on- clear circuit upd70f3617m2gba1-gah-ax a1 upd70f3617m2gba2-gah-ax a2 upd70f3618m1gba-gah-ax 192kb a without power-on- clear circuit upd70f3618m1gba1-gah-ax a1 upd70f3618m1gba2-gah-ax a2 upd70f3618m2gba-gah-ax a with power-on- clear circuit upd70f3618m2gba1-gah-ax a1 upd70f3618m2gba1-gah-ax a1 upd70f3619m1gba-gah-ax 256kb a without power-on- clear circuit upd70f3619m1gba1-gah-ax a1 upd70f3619m1gba2-gah-ax a2 upd70f3619m2gba-gah-ax a with power-on- clear circuit upd70f3619m2gba1-gah-ax a1 upd70f3619m2gba1-gah-ax a1 a) the operating ambient temperature of each quality grades is as follows: a: -40 to +85 c, a1: -40 to +110 c, a2: -40 to +125 c
30 chapter 1 introduction user?s manual u18743ee1v2um00 1.4.3 v850es/fg3-l ordering information part number package on-chip flash memory quality grade a a) the operating ambient temperature of each quality grades is as follows: a: -40 to +85 c, a1: -40 to +110 c, a2: -40 to +125 c remark upd70f3620m1gba-gah-ax 100-pin plastic lqfp (0.5mm, 14 x 14 mm 2 ) 128 kb a without power-on- clear circuit upd70f3620m1gba1-gah-ax a1 upd70f3620m1gba2-gah-ax a2 upd70f3620m2gba-gah-ax a with power-on- clear circuit upd70f3620m2gba1-gah-ax a1 upd70f3620m2gba2-gah-ax a2 upd70f3621m1gba-gah-ax 192kb a without power-on- clear circuit upd70f3621m1gba1-gah-ax a1 upd70f3621m1gba2-gah-ax a2 upd70f3621m2gba-gah-ax a with power-on- clear circuit upd70f3621m2gba1-gah-ax a1 upd70f3621m2gba1-gah-ax a1 upd70f3622m1gba-gah-ax 256kb a without power-on- clear circuit upd70f3622m1gba1-gah-ax a1 upd70f3622m1gba2-gah-ax a2 upd70f3622m2gba-gah-ax a with power-on- clear circuit upd70f3622m2gba1-gah-ax a1 upd70f3622m2gba1-gah-ax a1
31 user?s manual u18743ee1v2um00 chapter 2 pin functions this chapter lists the ports of the microcontroller. it presents the configuration of the ports for alternative functions. noise elimination on input signals is explained and a recommendation for the connection of unused pins is given at the end of the chapter. 2.1 overview the microcontroller offers various pins for input/output functions, so-called ports. the ports are organized in port groups. to allocate other than general purpose input/output functions to the pins, several control registers are provided. for a description of the terms pin, port or port group, see ?terms? on page 35 . features summary  number of ports and port groups:  configuration possible for individual pins.  for many pins, the connection of a pull-up resistor can be selected. v850es/fe3-l v850es/ff3-l v850es/fg3-l port groups 8 10 11 i/o ports 51 67 84
32 chapter 2 pin functions user?s manual u18743ee1v2um00 2.1.1 description the v850es/fe3-l, v850es/ff3-l, and v850es/fg3-l microcontrollers have the port groups shown below. figure 2-1 v850es/fe3-l, v850es/ff3-l, v850es/fg3-l port groups port group 0 p00 to p06 port group 4 p40 to p42 port group 5 p50 to p55 port group 3 p30 to p35 p36 p37 p38 p39 fg3-l only ff3-l/fg3-l only port group 1 p10 p11 fg3-l only port group 7 p70 to p79 p710 p711 p712 to p715 fg3-l only ff3-l/fg3-l only port group 9 p90 p91 fg3-l only p96 to p99 p92 to p95 p910 to p912 p913 to p915 port group cm pcm0 pcm1 pcm2 pcm3 ff3-l/fg3-l only port group cs pcs0 pcs1 ff3-l/fg3-l only port group ct pct0 pct1 pct4 pct6 ff3-l/fg3-l only port group dl pdl12 pdl13 fg3-l only pdl8 to pdl11 ff3-l/fg3-l only pdl0 to pdl7
33 pin functions chapter 2 user?s manual u18743ee1v2um00 port group overview ta b l e 2 - 1 gives an overview of the port groups. for each port group it shows the supported functions in port mode and in alternative mode. any port group can operate in 8-bit or 1-bit units. port groups 3, 6, 9 and dl can additionally operate in 16-bit units. note not all port groups and functions in ta b l e 2 - 1 are available for all products of the v850es/fx3-l product line. for detailed information which port groups and functions are available for a dedicated product, refer to ?2.4 port type diagrams? . pin configuration to define the function and the electrical characteristics of a pin, several control registers are provided.  for a general description of the registers, see ?port group configuration registers? on page 36 .  for every port, detailed information on the configuration registers is given in table 2-1 functions of each port group port group name function port mode alternative mode 0 7-bit input/output  external interrupt 0 to 3  non-maskable interrupt  n-wire debug interface reset  a/d converter 0 external trigger input  timer taa3 channels  timer taa4 channels  can0 transmit/receive data 1 2-bit input/output  external interrupt 9 and 10 3 10-bit input/output  external interrupt 7 and 8  timer taa0 channels  timer taa1 channels  can0 transmit/receive data  uartd0 transmit/receive data  uartd0 baud rate clock input 4 3-bit input/output  key interrupt input 0 to 2  clocked serial interface csib0 data/clock line 5 6-bit input/output  key interrupt input 0 to 5  n-wire debug interface signals 7 16-bit input/output  a/d converter 0 inputs 9 16-bit input/output  external interrupt 4 to 6  key interrupt input 6 to 7  timer taa2 channels  clocked serial interface csib1 data/clock line  uartd1 transmit/receive data  i 2 c data/clock line  programmable clock output cm 6-bit input/output  cpu system clock output cs 8-bit input/output  ct 8-bit input/output  dl 16-bit input/output 
34 chapter 2 pin functions user?s manual u18743ee1v2um00 ?port type diagrams? on page 51 .
35 pin functions chapter 2 user?s manual u18743ee1v2um00 2.1.2 terms in this section, the following terms are used: pin denotes the physical pin. every pin is uniquely denoted by its pin number. a pin can be used in several modes. depending on the selected mode, a pin name is allocated to the pin.  port group denotes a group of pins. the pins of a port group have a common set of port mode control registers.  port mode / port a pin in port mode works as a general purpose input/output pin. it is then called ?port?. the corresponding name is pnm. for example, p04 denotes port 4 of port group 0. it is referenced as ?port p04?.  alternative mode in alternative mode, a pin can work in various non-general purpose input/ output functions, for example, as the input/output pin of on-chip peripherals. the corresponding pin name depends on the selected function. for example, pin intp0 denotes the pin for one of the external interrupt inputs. note that for example p03 and intp0 denote the same physical pin. the different names indicate the function in which the pin is being operated.  port type a control circuit evaluates the settings of the configuration registers. there are different types of control circuits, called ?port types?. 2.1.3 noise elimination the input signals at some pins are passing a filter to remove noise and glitches. the microcontroller supports both analog and digital filters. see ?noise elimination? on page 126 for a detailed description.
36 chapter 2 pin functions user?s manual u18743ee1v2um00 2.2 port group configuration registers this section starts with an overview of all configuration registers and then presents all registers in detail. the configuration registers are classified in the following groups:  ?pin function configuration? on page 37  ?pin data input/output? on page 43  ?configuration of pull-up resistors? on page 45 2.2.1 overview for the configuration of the individual pins of the port groups, the following registers are used: n = 0, 1, 3 to 5, 7, 9 , cm, cs, ct, dl table 2-2 registers for port group configuration register name shortcut function port mode control register pmcn pin function configuration port mode register pmn port function control register pfcn port function control expansion register pfcen on-chip debug mode register ocdm port register pn pin data input/output pull-up resistor option register pun configuration of pull-up resistors port function register pfn open drain configuration
37 pin functions chapter 2 user?s manual u18743ee1v2um00 2.2.2 pin function configuration the registers for pin function configuration define the general function of a pin:  port mode or alternative mode  in port mode: input mode or output mode  in alternative mode: selection of one of the alternative functions in alternative mode  normal mode or on-chip debug mode (n-wire interface) an overview of the register settings is given in the table below. table 2-3 pin function configuration (overview) function registers i/o ocdm pmc pm pfce pfc port mode (output) 0 0 0xxo port mode (input) 1 x x i alternative mode (alternative function 1) 1x 0 0 i/o a a) in alternative mode, the corresponding port type defines whether a pin is in input mode or output mode. alternative mode (alternative function 2) 1 alternative mode (alternative function 3) 1 0 alternative mode (alternative function 4) 1 on-chip debug mode b b) in on-chip debug mode, the corresponding pins are automatically set as input or output pins to provide the n-wire interface. in this mode, the configuration of these pins can not be changed by the pin configuration registers. 1xxxxi/o
38 chapter 2 pin functions user?s manual u18743ee1v2um00 (1) pmcn - port mode control register the pmcn register specifies whether the individual pins of port group n are in port mode or in alternative mode. for port groups with up to eight ports, this is an 8-bit register. for port groups with up to 16 ports, this is a 16-bit register. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port type diagrams? on page 51 initial value 00 h or 0000 h . this register is initialized by any reset. caution when changing the function of a port from port mode (pcmnm = 0) to external interrupt input (pcmnm = 1) an advertent interrupt may occur. therefore, it is recommended to follow the below procedure: 1. to select the alternative input function intpn (i), set pfce.pfcenm and pfc.pfcnm accordingly. 2. set pmcnm = 1 to change to the alternative mode. 3. wait until the delay of the noise elimination filter has passed. 4. set intnic.intnif = 0 to clear the interrupt request. 5. clear intnic.intnmk (or clear intmr.intnmk) to enable the interrupt. in step 3 you must wait for a certain time span because the external interrupt pins are equipped with noise elimination filters. the filters cause a delay in which the interrupt request flag intnic.intnif is set. this flag must be cleared (step 4). 76543210 pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pmcn15 pmcn14 pmcn13 pmcn12 pmcn11 pmcn10 pmcn9 pmcn8 pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-4 pmcn register contents bit position bit name function 7 to 0 or 15 to 0 pmcn[7:0] or pmc[15:0] specifies the operation mode of the corresponding pin 0: port mode 1: alternative mode
39 pin functions chapter 2 user?s manual u18743ee1v2um00 (2) pmn - port mode register the pmn register specifies whether the individual pins of the port group n are in input mode or in output mode. for port groups with up to eight ports, this is an 8-bit register. for port groups with up to 16 ports, this is a 16-bit register. note if a pin is in alternative mode (pmcn.pmcnm = 1) and the corresponding pmn bit is set (pmn.pmnm = 1), then the pin behaves as in input port mode: reading pn.pmn reads the pin status. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port type diagrams? on page 51 initial value ff h or ffff h . this register is initialized by any reset. 76543210 pmn7 pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pmn15 pmn14 pmn13 pmn12 pmn11 pmn10 pmn9 pmn8 pmn7 pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-5 pmn register contents bit position bit name function 7 to 0 or 15 to 0 pmn[7:0] or pmn[15:0] specifies input/output mode of the corresponding pin 0: output mode (output enabled) 1: input mode (output disabled)
40 chapter 2 pin functions user?s manual u18743ee1v2um00 (3) pfcn - port function control register if a pin is in alternative mode (pmcn.pmcnm = 1) some pins offer up to four alternative functions. the pfcn register together with the pfcen register specifies which function of a pin is to be used. the corresponding port type defines whether a pin is in input or output mode. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port type diagrams? on page 51 initial value 00 h . this register is initialized by any reset. 76543210 pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pfcn15 pfcn14 pfcn13 pfcn12 pfcn11 pfcn10 pfcn9 pfcn8 pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-6 pfcn register contents bit position bit name function 7 to 0 pfcn[7:0] see ?pin function configuration (overview)? on page 37 for details 15 to 0 pfcn[15:0] see ?pin function configuration (overview)? on page 37 for details
41 pin functions chapter 2 user?s manual u18743ee1v2um00 (4) pfcen - port function control expansion register if a pin is in alternative mode (pmcn.pmcnm = 1) some pins offer up to four alternative functions. the pfcen together with the pfcn register specifies which function of a pin is to be used. the corresponding port type defines whether a pin is in input or output mode. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port type diagrams? on page 51 initial value 00 h or 0000 h . this register is initialized by any reset. 76543210 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pfcen15 pfcen14 pfcen13 pfcen12 pfcen11 pfcen10 pfcen9 pfcen8 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-7 pfcen register contents bit position bit name function 7 to 0 pfcen[7:0] see ?pin function configuration (overview)? on page 37 for details 15 to 0 pfcen[15:0] see ?pin function configuration (overview)? on page 37 for details
42 chapter 2 pin functions user?s manual u18743ee1v2um00 (5) ocdm - on-chip debug mode register the 8-bit ocdm register specifies whether dedicated pins of the microcontroller operate in normal operation mode or can be used for on-chip debugging (n-wire interface). the setting of this register concerns only those pins that can be used for the n-wire interface: p05/drst , p52/ddi, p53/ddo, p54/dck, and p55/dms. to make these pins available for on-chip debugging, bit ocdm.ocdm0 must be set while pin drst is high. if the on-chip debug mode is selected, the corresponding pins are automatically set as input or output pins, respectively. setting of bits pmn.pmnm is not necessary. for more details refer to ?on-chip debug unit? on page 723 . writing to this register is protected by a special sequence of instructions. please refer to ?cpu system functions? on page 135 for details. access this register can be read/written in 8-bit and 1-bit units. the register can only be written if a low level (?0?) is input to the p05/drst pin. address ffff f9fc h initial value 00 h /01 h :  after power-on-clear reset, the normal operation mode is selected (ocdm.ocdm0 = 0).  after external reset , the dedicated pins are available for on-chip debugging (ocdm.ocdm0 = 1).  after any other reset, bit ocdm0 holds the same value as before the reset. note if the pins p05/drst , p52/ddi, p53/ddo, p54/dck, and p55/dms are used as n-wire interface pins their configuration can not be changed by the pin configuration registers. drst pull-down resistor drst (p05) is equipped with an internal pull-down resistor. connection of the resistor is controlled by ocdm.ocdm0: 0: resistor detached from p05/drst 1: resistor attached to p05/drst this ensures that the microcontroller is operating correctly, even if the pins are in n-wire mode, but no debugger is connected. 76543210 0000000ocdm0 rrrrrrrr/w table 2-8 ocdm register contents bit position bit name function 0 ocdm0 enables/disables n-wire interface: 0: pins are used in normal operation mode (port mode or alternative mode). drst pull-down resistor not connected 1: pins are used in on-chip debug mode. drst pull-down resistor connected
43 pin functions chapter 2 user?s manual u18743ee1v2um00 2.2.3 pin data input/output if a pin is in port mode, the registers for pin data input/output specify the input and output data. (1) pn - port register if a pin is in port mode (pmcn.pmcnm = 0), data is input from or output to an external device by writing or reading the pn register. for port groups with up to eight ports, this is an 8-bit register. for port groups with up to 16 ports, this is a 16-bit register. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port type diagrams? on page 51 initial value undefined. note after reset, the ports are in input mode (pmn.pmnm = 1). the read input value is determined by the port pins. note the value written to register pn is retained until a new value is written to register pn. port mode in port mode (pmcn.pmcnm = 0), register pmn specifies whether a pin is in input or in output mode. data is written to or read from the pn register as follows: 76543210 pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pn15 pn14 pn13 pn12 pn11 pn10 pn9 pn8 pn7 pn6 pn5 pn4 pn3 pn2 pn1 pn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-9 pn register contents bit position bit name function 7 to 0 or 15 to 0 pn[7:0] or pn[15:0] data, see table 2-10 on page 43 and table 2-11 on page 44 for details. table 2-10 writing/reading register pn in port mode (pmcn.pmcnm = 0) function pm i/o write to pn? ?and output contents of pn to pins 0 o ?without affecting the pin status 1 i read from pn? ?and thus read the pin status 1 i ?and disregard the pin status 0 o
44 chapter 2 pin functions user?s manual u18743ee1v2um00 alternative mode in alternative mode (pmcn.pmcnm = 1), the corresponding port type defines whether a pin is in input or output mode. however, register pmn influences the writing/reading of register pn. in alternative mode, data is written to or read from the pn register as follows: caution although 1-bit operations (read-modify-write operations) on pn registers are intended to modify only a single bit, the entire pn register is read. after the single bit has been modified, the contents of the complete register is written back. if the ports of the register pn contain both input and output ports pnm, the read of pn returns  the contents of the register pn for output ports  the pin status of input ports, but not the pn register bits that means the read value of pn may be different to the contents of the pn register at bit positions, which are assigned to input ports. thus the contents of pn may differ to the previous value not just in the bit that was to be modified, but also in other bits. example:  register p1 has the contents 00 h .  port p10 is configured as an output port, all other ports of port group 1 (ports p11 to p17) are configured as input ports.  the port pins of ports p11 to p17 all have the level ?1?.  bit p1.p10 is set to 1 by a 1-bit operation. afterwards, register p1 holds the value ff h instead of the expected value 01 h , since bits p11 to p17 have be overwritten with the corresponding pin levels ?1?. table 2-11 writing/reading register pn in alternative mode (pmcn.pmcnm = 1) function pm i/o write to pn without affecting the pin status x? read from pn? ?and read the value of the alternative output function (for pins in alternative output function) 0? ?and disregard the pin status (for pins in alternative input function) ?and thus read the pin status 1 i
45 pin functions chapter 2 user?s manual u18743ee1v2um00 2.2.4 configuration of pull-up resistors (1) pun - port pull-up resistor option register the pun register specifies whether a pull-up resistor is connected to the pin. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port type diagrams? on page 51 initial value 00 h or 0000 h .. this register is cleared by any reset. caution in port mode, (pmcnm bit = 0), the punm bit of the pun register is valid only when pmnm bit of pmn register is 0 (output mode). if pmnm bit = 1 (input mode), the setting value of pun register is invalid (pull-up resistor is detached). 76543210 pun7 pun6 pun5 pun4 pun3 pun2 pun1 pun0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pun15 pun14 pun13 pun12 pun11 pun10 pun9 pun8 pun7 pun6 pun5 pun4 pun3 pun2 pun1 pun0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-12 pun register contents bit position bit name function 7 to 0 or 15 to 0 pun[7:0] or pun[15:0] specifies whether a pull-up resistor is connected to the corresponding pin: 0: no pull-up resistor connected 1: pull-up resistor connected
46 chapter 2 pin functions user?s manual u18743ee1v2um00 2.2.5 open drain configuration (1) pfn - port function register if a pin is in alternative mode (pmcn.pmcnm = 1), the pfn register specifies normal output or open-drain output. for port groups with up to eight ports, this is an 8-bit register. for port groups with up to 16 ports, this is a 16-bit register. note the settings of pfn are only valid in alternative mode. access this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. address see ?port type diagrams? on page 51 initial value 00f h or 0000 h . this register is initialized by any reset. 76543210 pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 r/w r/w r/w r/w r/w r/w r/w r/w 1514131211109876543210 pfn15 pfn14 pfn13 pfn12 pfn11 pfn10 pfn9 pfn8 pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w table 2-13 pfn register contents bit position bit name function 7 to 0 or 15 to 0 pfn[7:0] or pfn[15:0] specifies normal output or open-drain output 0: normal output 1: open-drain output
47 pin functions chapter 2 user?s manual u18743ee1v2um00 2.3 port buffers diagrams this chapter presents the block diagrams of all buffer types. the tables in ?port group configuration lists? on page 100 informs also about the buffer type, used for each port. (1) buffer type 2 figure 2-2 block diagram: buffer type 2 (2) buffer type 5 figure 2-3 block diagram: buffer type 5 in
48 chapter 2 pin functions user?s manual u18743ee1v2um00 (3) buffer type 5-af figure 2-4 block diagram: buffer type 5-af (4) buffer type 5-k figure 2-5 block diagram: buffer type 5-k
49 pin functions chapter 2 user?s manual u18743ee1v2um00 (5) buffer type 5-w figure 2-6 block diagram: buffer type 5-w (6) buffer type 11-g figure 2-7 block diagram: buffer type 11-g
50 chapter 2 pin functions user?s manual u18743ee1v2um00 (7) buffer type 16 figure 2-8 block diagram: buffer type 16
51 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4 port type diagrams this chapter presents the block diagrams of all port types. the tables in the detailed descriptions of each port group from ?port group 0? on page 108 onwards informs also about the port type, used for each port. 2.4.1 port type c figure 2-9 port type c block diagram note for v850es/fe3-l, v850es/ff3-l, v850es/fg3-l products the input buffer has schmitt trigger (40/80%) characteristic internal bus (a) output buffer control pmn selector wr pm wr port address rd pmn pmmn selector (b) input buffer control
52 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.2 port type c-u figure 2-10 port type c-u block diagram internal bus (a) output buffer control (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr port address rd pmn pmmn selector (b) input buffer control
53 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.3 port type d0 figure 2-11 port type d0 block diagram internal bus (a) output buffer control pmn selector wr pm wr pmc wr port address rd pmcmn pmn pmmn 1st alternate function (d) output data selection selector (b) input buffer control
54 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.4 port type d0-u figure 2-12 port type d0-u block diagram internal bus (a) output buffer control (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn 1st alternate function (d) output data selection selector (b) input buffer control
55 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.5 port type d1 figure 2-13 port type d1 block diagram internal bus (a) outp ut buff er co ntrol pmn selector wr pm wr pmc wr port address rd pmcmn pmn pmmn selector (b) input buffer control 1st alternate f unction (e) alternat e fu nctio n in put control
56 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.6 port type d1-u figure 2-14 port type d1-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn selector (b) input buff er control 1st alternate f unction (e) alternat e fu nctio n in put control
57 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.7 port type d1-ui figure 2-15 port type d1-ui block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn selector (b) input buff er control 1st alternate f unction (e) alternate function input control wr intr intrmn wr intf intfmn edge detector noise remov al
58 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.8 port type d3-ui figure 2-16 port type d3-ui block diagram internal bus (a) output buff er control (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn selector (b) input buff er control 1st alternate f unction (intpx) (e) alternate function input control wr intr intrmn wr intf intfmn edge detector noise remov al 1st alternate f unction (rxddy )
59 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.9 port type d1a figure 2-17 port type d1a block diagram internal bus (a) output buffer control pmn selector wr pm wr pmc wr port address rd pmcmn pmn pmmn selector (b) input buffer control 1st alternate function pch nch
60 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.10 port type d1o1-ui figure 2-18 port type d1o1-ui block diagram wr o cdm ocdm0 internal bus (a) output buffer control (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn selector (b) input buffer control 1st alternate f unction (e) alternate function input control wr intr intrmn wr intf intfmn edge detector noise remov al (f) on-chip debug input control _drst signal (on-chip debug mode) pocres (g ) pull-down c ontr ol nch
61 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.11 port type d2 figure 2-19 port type d2 block diagram internal bus (a) output buffer control pmn selector wr pm wr pm c wr port address rd pmcmn pmn pmmn 1st alternate f unction (d) outp ut dat a s electio n selector (b) input buff er control 1st alternate f unction (e) a lternate function input control output enable signal 1 in alternative mode input enable signal 1 in alternative mode
62 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.12 port type e01-u figure 2-20 port type e01-u block diagram internal bus (a) output buffer control (c) pull-up co ntrol wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 1st alternate f unction (d) output dat a s election selector (b) input buffer control 2nd alternate f unction (e) alternat e function input control
63 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.13 port type e10-u figure 2-21 port type e10-u block diagram internal bus (a) output buffer control (c) pull-up co ntrol wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate f unction (d) output dat a s election selector (b) input buffer control 1st alternate f unction (e) alternat e function input control
64 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.14 port type e10-ui figure 2-22 port type e10-ui block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate f unction (d) outp ut dat a s electio n selector (b) input buff er control 1st alternate f unction (e) alternate function input control wr intr intrmn wr intf intfmn edge detector noise remov al
65 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.15 port type e11-u figure 2-23 port type e11-u block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn selector (b) input buffer control 1st alternate function (e) alternate function input control 2nd alternate function
66 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.16 port type e11-ui figure 2-24 port type e11-ui block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn selector (b) input buffer control 1st alternate function (e) alternate function input control wr intr intrmn wr intf intfmn edge detector 2nd alternate function noise removal
67 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.17 port type e21-u figure 2-25 port type e21-u block diagram internal bu s (a) output buffer control (c) pull - up control wr p fc evdd pmn selector wr p u pumn p ch wr pm wr pm c wr port address rd pmcmn pmn pmmn pfcmn 1st alternate function (d) output data selection selector (b) input buffer control 1st alternate function (e) a lternate function input control 2nd alternate function output enable signal 1 in alternative mode
68 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.18 port type ex0-u figure 2-26 port type ex0-u block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate function (d) output data selection selector (b) input buffer control
69 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.19 port type ex1-u figure 2-27 port type ex1-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up co ntrol wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn selector (b) input buffer control 2nd alternate f unction (e) alternat e function input control
70 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.20 port type ex1-ui figure 2-28 port type ex1-ui block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn selector (b) input buff er control 2nd alternate f unction (e) alternate function input control wr intr intrmn wr intf intfmn edge detector noise remov al
71 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.21 port type ex2-u figure 2-29 port type ex2-u block diagram internal bu s (a) output buff er control (c) pull - up control wr p fc evdd pmn selector wr p u pumn p ch wr pm wr pm c wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate f unction (d) output data selection selector (b) input buff er control 2nd alternate f unction (e) a lternate function input control output enable signal 2 in alternative mode
72 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.22 port type f010x-u figure 2-30 port type f010x-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 1st alternate f unction (d) outp ut dat a s electio n selector (b) input buffer control 2nd alternate f unction (e) alternat e fu nctio n in put control wr pfce pfcemn 3rd alternate f unction
73 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.23 port type f010x-ui figure 2-31 port type f010x-ui block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 1st alternate f unction (d) outp ut dat a s electio n selector (b) input buffer control wr pfce pfcemn 2nd alternate f unction (e) alternat e fu nctio n in put control 3rd alternate f unction
74 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.24 port type f100x-u figure 2-32 port type f100x-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate f unction (d) outp ut dat a s electio n selector (b) input buffer control 1st alternate f unction (e) alternat e fu nctio n in put control wr pfce pfcemn 3rd alternate f unction
75 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.25 port type f1010-u figure 2-33 port type f1010-u block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate function (d) output data selection selector (b) input buffer control 1st alternate function (e) alternate function input control wr pfce pfcemn 3rd alternate function 4th alternate function
76 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.26 port type f101x-u figure 2-34 port type f101x-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn (d) outp ut dat a s electio n selector (b) input buffer control 1st alternate f unction (e) alternat e fu nctio n in put control wr pfce pfcemn 3rd alternate f unction 2nd alternate f unction
77 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.27 port type f1100o0-u figure 2-35 port type f1100o0-u block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 3rd alternate function (d) output data selection selector (b) input buffer control 1st alternate function (e) alternate function input control wr pfce pfcemn 2nd alternate function 4th alternate function ocdm signal on-chip debug function
78 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.28 port type f1100o1-u figure 2-36 port type f1100o1-u block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 3rd alternate function (d) output data selection selector (b) input buffer control 1st alternate function (e) alternate function input control wr pfce pfcemn 2nd alternate function 4th alternate function ocdm signal on-chip debug function
79 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.29 port type f1100-u figure 2-37 port type f1100-u block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 3rd alternate function (d) output data selection selector (b) input buffer control 1st alternate function (e) 1st alternate function input control wr pfce pfcemn 2nd alternate function 4th alternate function
80 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.30 port type f1110-ui figure 2-38 port type f1110-ui block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 4th alternate function (d) output data selection selector (b) input buffer control 1st alternate function (e) alternate function input control wr intr intrmn wr intf intfmn wr pfce pfcemn edge detector 2nd alternate function 3rd alternate function noise removal
81 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.31 port type f113x-ui figure 2-39 port type f113x-ui block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn selector (b) input buffer control 3rd alternate function (intpx) wr intr intrmn wr intf intfmn wr pfce pfcemn edge detector 2nd alternate function (e) alternate function input control 1st alternate function noise removal 3rd alternate function (rxddy)
82 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.32 port type f1x10-ui figure 2-40 port type f1x10-ui block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 4th alternate f unction (d) output data selection selector (b) input buffer control 1st alternate f unction (e) alternat e fu nctio n in put control wr intr intrmn wr intf intfmn wr pfce pfcemn edge detector 3rd alternate f unction noise remov al
83 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.33 port type f3x1x-ui figure 2-41 port type f1x1x-ui block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn selector (b) input buffer control 1st alternate f unction (intpx) (e) alternat e fu nctio n in put control wr intr intrmn wr intf intfmn wr pfce pfcemn edge detector 3rd alternate f unction noise remov al 1st alternate f unction (rxddy )
84 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.34 port type f1xx0o1-u figure 2-42 port type f1xx0o1-u block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn (d) output data selection selector (b) input buffer control 1st alternate function (e) alternate function input control wr pfce pfcemn 4th alternate function ocdm signal on-chip debug function
85 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.35 port type fx010-u figure 2-43 port type fx010-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate f unction (d) outp ut dat a s electio n selector (b) input buffer control 3rd alternate f unction (e) alternat e fu nctio n in put control wr pfce pfcemn 4th alternate f unction
86 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.36 port type fx01x-u figure 2-44 port type fx01x-u block diagram internal bus (a) output buff er control (c) pull - up control wr p fc evdd pmn selector wr p u pumn p ch wr pm wr pm c wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate f unction (d) output data selection selector (b) input buff er control 3rd alternate f unction (e) a lternat e function input control wr p fce pfcemn
87 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.37 port type fx103-ui figure 2-45 port type fx103-ui block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 3rd alternate function (d) output data selection selector (b) input buffer control 2nd & 4th alternate function (intpx) wr intr intrmn wr intf intfmn wr pfce pfcemn edge detector (e) alternate function input control noise removal 4th alternate function (rxddy) share control
88 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.38 port type fx10x-u figure 2-46 port type fx10x-u block diagram internal bus (a) output buff er control (c) pull - up control wr p fc evdd pmn selector wr p u pumn p ch wr pm wr pm c wr port address rd pmcmn pmn pmmn pfcmn 2nd alternate f unction (d) output data selection selector (b) input buff er control 3rd alternate f unction (e) a lternat e function input control wr p fce pfcemn
89 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.39 port type fx10x-ui figure 2-47 port type fx10x-ui block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 3rd alternate f unction (d) output data selection selector (b) input buffer control 2nd alternate f unction (e) alternat e fu nctio n in put control wr intr intrmn wr intf intfmn wr pfce pfcemn edge detector noise remov al
90 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.40 port type fx110-u figure 2-48 port type fx110-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn 4th alternate f unction (d) outp ut dat a s electio n selector (b) input buffer control 2nd alternate f unction (e) alternat e fu nctio n in put control wr pfce pfcemn 3rd alternate f unction
91 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.41 port type fx120-ufi figure 2-49 port type fx120-ufi block diagram wr intr intrmn wr intf intfmn internal bus (a) output buffer control (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn 4th alternate f unction (d) output data selection selector (b) input buffer control (e) alternate function input control wr pfce pfcemn wr pfc pfcmn 3rd alternate f unction wr pf pfmn 2nd alternate f unction edge detector noise remov al 3rd alternate f unction
92 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.42 port type fx123-ufi figure 2-50 port type fx123-ufi block diagram wr intr intrmn wr intf intfmn internal bus (a) output buffer control (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn (d) output data selection selector (b) input buffer control (e) alternate function input control wr pfce pfcemn wr pfc pfcmn 3rd alternate function wr pf pfmn 2nd & 4th alternate function (intpx) edge detector noise removal 4th alternate function (rxddy) 3rd alternate function share control
93 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.43 port type fx12x-ufi figure 2-51 port type fx12x-ufi block diagram wr intr intrmn wr intf intfmn internal bus (a) output buffer control (c) pull-up control evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn (d) output data selection selector (b) input buffer control (e) alternate function input control wr pfce pfcemn wr pfc pfcmn 3rd alternate function wr pf pfmn 2nd alternate function edge detector noise removal 3rd alternate function
94 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.44 port type fx13x-u figure 2-52 port type fx13x-u block diagram internal bus (a) output buffer control (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn selector (b) input buffer control (e) alternate function input control wr pfce pfcemn 2nd & 3rd alternate function (krx) 3rd alternate function (rxddy) share control
95 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.45 port type fx210-u figure 2-53 port type fx210-u block diagram internal bus (a) output buffer control (c) pull - up control evdd pmn selector wr p u pumn p ch wr pm wr pm c wr port address rd pmcmn pmn pmmn 4th alternate function (d) output data selection selector (b) input buffer control 2nd alternate function (e) a lternate function input control 3rd alternate function output enable signale 2 in alternative mode wr p fce pfcemn wr p fc pfcmn 2nd alternate function
96 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.46 port type fx2x0-u figure 2-54 port type fx2x0-u block diagram internal bus (a) output buffer control (c) pull - up control evdd pmn selector wr p u pumn p ch wr pm wr pm c wr port address rd pmcmn pmn pmmn 4th alternate f unction (d) outp ut dat a s electio n selector (b) input buff er control 2nd alternate f unction (e) a lternat e function input control wr p fce pfcemn wr p fc pfcmn 2nd alternate f unction output enable signale 2 in alternative mode
97 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.47 port type fxx10-u figure 2-55 port type fxx10-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn (d) outp ut dat a s electio n selector (b) input buffer control wr pfce pfcemn 3rd alternate f unction (e) alternat e fu nctio n in put control 4th alternate f unction
98 chapter 2 pin functions user?s manual u18743ee1v2um00 2.4.48 port type fxx1x-u figure 2-56 port type fxx1x-u block diagram internal bus (a) outp ut buff er co ntrol (c) pull-up control wr pfc evdd pmn selector wr pu pumn pch wr pm wr pmc wr port address rd pmcmn pmn pmmn pfcmn selector (b) input buffer control wr pfce pfcemn 3rd alternate f unction (e) alternat e fu nctio n in put control
99 pin functions chapter 2 user?s manual u18743ee1v2um00 2.4.49 port type fxx2x-u figure 2-57 port type fxx2x-u block diagram wr p fc internal bus (a) output buff er control (c) pull - up control wr p fce evdd pmn selector wr p u pu mn p ch wr pm wr pm c wr port address rd pmcmn pmn pmmn pfcemn 3rd alternate f unction (d) output data selection selector (b) input buff er control 3rd alternate f unction (e) a lternate function input control pfcmn output enable signale 3 in alternative mode
100 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5 port group configuration this section provides an overview of the port groups ( ta bl e 2 - 1 4 ) and of the pin functions ( table 2-14 on page 100 ). in table 2-40 on page 130 it is listed how the pin functions change if the microcontroller is reset. in the subsections, for every port group the settings of the configuration registers is listed. further, the addresses and initial values of the configuration registers are given. see ?port group 0? on page 108 to ?port group dl? on page 125 . 2.5.1 port group configuration lists ta b l e 2 - 1 4 provides an overview of the functions available at each port pin. table 2-14 v850es/fe3-l, v850es/ff3-l, v850es/fg3-l port group list (1/3) port group name port name alternative outputs alternative inputs buffer type 0 p00 toaa31 tiaa31 5-w p01 toaa30 tiaa30 5-w p02 toaa40 nmi/tiaa40 5-w p03 toaa41 intp0/tiaa41/adtrg 5-w p04 ? intp1/crxd0 5-w p05 ? intp2/drst 5-af p06 ctxd0 intp3 5-w 1 a p10 ? intp9 5-w p11 ? intp10 5-w 3 p30 txdd0 ? 5-w p31 ? rxdd0/intp7 5-w p32 toaa00/toaa01 asckd0/tiaa00 5-w p33 toaa01/ctxd0 tiaa01 5-w p34 toaa10 tiaa10/crxd0 5-w p35 toaa11 tiaa11 5-w p36 a ?? 5-w p37 a ?? 5-w p38 b txdd2 a ?5-w p39 b ? rxdd2 a /intp8 a 5-w 4 p40 ? sib0/kr0/ 5-w p41 sob0 kr1 5-w p42 sckb0 sckb0/kr2 5-w 5 p50 ? kr0 5-w p51 ? kr1 5-w p52 ? kr2/ddi 5-w p53 ddo kr3 5-w p54 ? kr4/dck 5-w p55 ? kr5/dms 5-w
101 pin functions chapter 2 user?s manual u18743ee1v2um00 7 p70 ? ani0 11-g p71 ? ani1 11-g p72 ? ani2 11-g p73 ? ani3 11-g p74 ? ani4 11-g p75 ? ani5 11-g p76 ? ani6 11-g p77 ? ani7 11-g p78 ? ani8 11-g p79 ? ani9 11-g p710 b ?ani1011-g p711 b ?ani1111-g p712 a ?ani1211-g p713 a ?ani1311-g p714 a ?ani1411-g p715 a ?ani1511-g 9 p90 txdd1 kr6 5-w p91 ? kr7/rxdd1 5-w p92 a ?? 5-w p93 a ?? 5-w p94 a ?? 5-w p95 a ?? 5-w p96 toaa21 tiaa21 5-w p97 toaa20 sib1/tiaa20 5-w p98 sob1 ? 5-w p99 sckb1 sckb1 5-w p910 a ?? 5-w p911 a ?? 5-w p912 a ?? 5-w p913 pcl intp4 5-w p914 sda00 sda00/intp5 5-w p915 scl00 scl00/intp6 5-w cm pcm0 ? ? 5 pcm1 clkout ? 5 pcm2 b ?? 5 pcm3 b ?? 5 cs b pcs0 ? ? 5 pcs1 ? ? 5 table 2-14 v850es/fe3-l, v850es/ff3-l, v850es/fg3-l port group list (2/3) port group name port name alternative outputs alternative inputs buffer type
102 chapter 2 pin functions user?s manual u18743ee1v2um00 ct b pct0 ? ? 5 pct1 ? ? 5 pct4 ? ? 5 pct6 ? ? 5 dl pdl0 ? ? 5-k pdl1 ? ? 5-k pdl2 ? ? 5-k pdl3 ? ? 5-k pdl4 ? ? 5-k pdl5 ? flmd1 5-k pdl6 ? ? 5-k pdl7 ? ? 5-k pdl8 b ?? 5-k pdl9 b ?? 5-k pdl10 b ?? 5-k pdl11 b ?? 5-k pdl12 a ?? 5-k pdl13 a ?? 5-k a) v850es/fg3-l only b) v850es/ff3-l, v850es/fg3-l only table 2-14 v850es/fe3-l, v850es/ff3-l, v850es/fg3-l port group list (3/3) port group name port name alternative outputs alternative inputs buffer type
103 pin functions chapter 2 user?s manual u18743ee1v2um00
104 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5.2 alphabetic pin function list ta b l e 2 - 1 5 provides a list of all pin function names in alphabetic order. the table does not list differences between the various devices of the v850es/ fx3-l. these are listed in table 2-14 on page 100 . table 2-15 alphabetic pin functions list (1/3) pin name i/o pin function port pin number fe3 ff3 fg3 adtrg i a/d converter 0 external trigger input p03 15 6 18 ani0 i a/d converter 0 input 0 to 15 p70 64 80 100 ani1 p71 63 79 99 ani2 p72 62 78 98 ani3 p73 61 77 97 ani4 p74 60 76 96 ani5 p75 59 75 95 ani6 p76 58 74 94 ani7 p77 57 73 93 ani8 p78 56 72 92 ani9 p79 55 71 91 ani10 p719?7090 ani11 p711?6989 ani12 p712 ? ? 88 ani13 p713 ? ? 87 ani14 p714 ? ? 86 ani15 p715 ? ? 85 asckd0 i uartd0 baud rate clock input p32 24 24 27 avref0 ? a/d converter 0 reference voltage input ? 1 1 1 avss ? a/d converter 0 ground ? 2 2 2 bvdd ? i/o buffer supply voltage ? ? ? 70 bvss ? i/o buffer supply ground ? ? ? 69 clkout o cpu system clock output pcm1 46 50 62 crxd0 i can receive data p04 16 7 19 p34 262629 ctxd0 o can0 transmit data p06 18 18 21 p33 252528 dck i n-wire interface clock p54 34 36 41 ddi i n-wire interface debug data input p52 30 34 39 ddo o n-wire interface debug data output p53 31 35 40 dms i n-wire interface debug mode select input p55 35 37 42 drst i n-wire debug interface reset p05 17 17 20 evdd ? port buffer supply voltage ? 33 31 5, 34 evss ? port buffer supply voltage ? 32 30 33
105 pin functions chapter 2 user?s manual u18743ee1v2um00 flmd0 ? flash programming mode setting pin ? 3 8 8 flmd1 i flash programming mode setting pin pdl5 52 62 76 intp0 i external interrupts intp0 - intp10 p03 15 6 18 intp1 p04 16 7 19 intp2 p05 17 17 20 intp3 p06 18 18 21 intp4 p913 42 44 56 intp5 p914 43 45 57 intp6 p915 44 46 58 intp7 p31 23 23 26 intp8 p39 ? ? 36 intp9 p10 ? ? 3 intp10 p11??4 kr0 i key interrupt kr0 - kr7 p40 19 19 22 p50 283237 kr1 p41 20 20 23 p51 293338 kr2 p42 21 21 24 p52 303439 kr3 p53 31 35 40 kr4 p54 34 36 41 kr5 p55 35 37 42 kr6 p90 36 38 43 kr7 p91 37 39 44 nmi i non-maskable interrupt p02 14 5 17 pcl o programmable clock output p913 42 44 56 regc ? external voltage regulator capacitor connection ? 5 10 10 reset i reset input ? 9 14 14 rxdd0 i uartd receive data p31 23 23 26 rxdd1 p91 37 39 44 rxdd2 p39 36 sckb0 i/o clocked serial interface clock lines p42 21 21 24 sckb1 p99 41 43 52 scl00 i/o i 2 c0 clock line p915 44 46 58 sda00 i/o i 2 c0 data line p914 43 45 57 sib0 i clocked serial interface data input p40 19 19 22 sib1 p97 39 41 50 sob0 o clocked serial interface data output p41 20 20 23 sob1 p98 40 42 51 table 2-15 alphabetic pin functions list (2/3) pin name i/o pin function port pin number fe3 ff3 fg3
106 chapter 2 pin functions user?s manual u18743ee1v2um00 tiaa00 i timer taa channel 0 capture trigger input p32 24 24 27 tiaa10 p33 25 25 28 tiaa20 p97 39 41 50 tiaa30 p01 13 4 7 tiaa40 p02 14 5 17 tiaa01 i timer taa channel 1 capture trigger input p34 26 26 29 tiaa11 p35 27 27 30 tiaa21 p96 38 40 49 tiaa31 p00 12 3 6 tiaa41 p03 15 6 18 toaa00 o timer taa channel 0 signal output p32 24 24 27 toaa10 p34 26 26 29 toaa20 p97 39 41 50 toaa30 p01 13 4 7 toaa40 p02 14 5 17 toaa01 o timer taa channel 1 signal output p32 24 24 27 p33 252528 toaa11 p35 27 27 30 toaa21 p96 38 40 49 toaa31 p00 12 3 6 toaa41 p03 15 6 18 txdd0 o uartd transmit data p30 22 22 25 txdd1 p90 363843 txdd2 p38 35 vdd ? core supply voltage ? 4 9 9 vss ? core supply ground ? 6 11 11 x1 i main clock resonator connection ? 7 12 12 x2 ? main clock resonator connection ? 8 13 13 xt1 i sub oscillator resonator connection ? 10 15 15 xt2 ? sub oscillator resonator connection ? 11 16 16 table 2-15 alphabetic pin functions list (3/3) pin name i/o pin function port pin number fe3 ff3 fg3
107 pin functions chapter 2 user?s manual u18743ee1v2um00 note the following alternative functions are provided on two pins each: thus you can select on which pin the alternative function should appear. refer to ?pin function configuration? on page 37 . caution make sure an alternative input function is only supplied from a single pin at the same time. an alternative output function can be output on several pins concurrently. for example, if p40 operates as key interrupt kr0, p50 must not operate as key interrupt kr0. unit alternative function i/o port 1 port 2 timer toaa01 o p33 p32 can ctxd0 o p06 p33 crxd0 i p04 p34 key interrupt kr0 i p40 p50 kr1 i p41 p51 kr2 i p42 p52
108 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5.3 port group 0 port group 0 is a 7-bit port group. in alternative mode, it comprises pins for the following functions:  external interrupt (intp0 to intp3)  non-maskable interrupt (nmi)  n-wire debug interface reset (drst )  a/d converter 0 external trigger input (adtrg)  timer taa3 channels (tiaa30, tiaa31 and toaa30, toaa31)  timer taa4 channels (tiaa40, tiaa41 and toaa40, toaa41)  can0 transmit/receive data (ctxd0, crxd0) port group 0 includes the following pins: note alternative functions crxd0 and ctxd0 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?alphabetic pin function list? on page 104 . table 2-16 port group 0: pin functions and port types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter only for tiaanm, nmi, intpn, drst , adtrg inputs b: analog and digital noise filter ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmc = 0) alternative mode (pmcnm = 1) on-chip debug mode (ocdm0 = 1) pfce = 0 pfce = 1 function 1 pfc = 0 function 2 pfc = 1 function 3 pfc = 0 function 4 pfc = 1 p00 tiaa31 (i) toaa31 (o) ? ? ? p00 (i) e10-u a s2 p01 tiaa30 (i) toaa30 (o) ? ? ? p01 (i) e10-u a s2 p02 nmi (i) prohibited tiaa40 (i) toaa40 (o) ? p02 (i) f1x10-ui a s2 p03 intp0 (i) adtrg (i) tiaa41 (i) toaa41 (o) ? p03 (i) f1110-ui a s2 p04 intp1 (i) crxd0 (i) ? ? ? p04 (i) e11-ui a s1 p05 intp2 (i) ? ? ? drst (i) p05 (i) or drst (i) c c) the pin function after reset depends on the reset source, that means on bit ocdm.ocdm0. refer to ?ocdm - on-chip debug mode register? on page 42 and to ?on-chip debug unit? on page 723 . d101-ui a s2 p06 intp3 (i) ctxd0 (o) ? ? ? p06 (i) e10-ui b s2
109 pin functions chapter 2 user?s manual u18743ee1v2um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-17 port group 0: configuration registers register address initial value used bits pmc0 ffff f440 h 00 h x pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 pm0 ffff f420 h ff h x pm06 pm05 pm04 pm03 pm02 pm01 pm00 pfc0 ffff f460 h 00 h x pfc06 x pfc04 pfc03 pfc02 pfc01 pfc00 pfce0 ffff f700 h 00 h xxxxpfce03pfce02xx ocdm ffff f9fc h 00 h / 01 h a a) depends on the reset source (refer to ?ocdm - on-chip debug mode register? on page 42 and to ?on-chip debug unit? on page 723 ) 0000000ocdm0 p0 ffff f400 h undefined x p06 p05 p04 p03 p02 p01 p00 pu0 ffff fc40 h 00 h x pu06 pu05 pu04 pu03 pu02 pu01 pu00
110 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5.4 port group 1 (v850es/fg3-l) note port group 1 is available only for v850es/fg3-l. port group 1 is a 2-bit port group. in alternative mode, it comprises pins for the following functions:  external interrupt (intp9 and intp10) port group 1 includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-18 port group 1: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter only for intpn inputs b: analog and digital noise filter ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm = 0) alternative mode (pmcnm = 1) p10 intp9 (i) p10 (i) d1-ui a s2 p11 intp10 (i) p11 (i) d1-ui a s2 table 2-19 port group 1: configuration registers register address initial value used bits pmc1 ffff f442 h 00 h xxxxxxpmc11pmc10 pm1 ffff f422 h ff h xxxxxxpm11pm10 p1 ffff f402 h undefined xxxxxxp11p10 pu1 ffff fc42 h 00 h xxxxxxpu11pu10
111 pin functions chapter 2 user?s manual u18743ee1v2um00 2.5.5 port group 3 port group 3 is a 10-bit port group. in alternative mode, it comprises pins for the following functions:  external interrupt (intp7 and intp8)  timer taa0 channels (tiaa00, tiaa01 and toaa00, toaa01)  timer taa1 channels (tiaa10, tiaa11 and toaa10, toaa11)  can0 transmit/receive data (ctxd0, crxd0)  uartd0 transmit/receive data (txdd0, rxdd0)  uartd0 baud rate clock input (asckd0) port group 3 includes the following pins: x note alternative functions crxd0, ctxd0, and toaa01 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?pin function configuration? on page 37 . table 2-20 port group 3: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter only for intpn, tiaanm inputs b: analog and digital noise filter ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm =0) alternative mode (pmcnm = 1) pfce = 0 pfce = 1 function 1 pfc = 0 function 2 pfc = 1 function 3 pfc = 0 function 4 pfc = 1 p30 txdd0 (o) ? ? ? p30 (i) d0-u ? s1 p31 rxdd0 (i) intp7 (i) ???p31 (i) d3-ui a s1 p32 asckd0 (i) toaa01 (o) tiaa00 (i) toaa00 (o) p32 (i) f1010-u a s2 p33 tiaa01 (i) toaa01 (o) ctxd0 (o) prohibited p33 (i) f100x-u a s2 p34 tiaa10 (i) toaa10 (o) crxd0 (i) prohibited p34 (i) f101x-u a s1 p35 tiaa11 (i) toaa11 (o) ? ? p35 (i) e10-u a s2 p36 c c) not available for v850es/fe3-l, v850es/ff3-l ? ? ? ? p36 (i) c-u ? s1 p37 c ? ? ? ? p37 (i) c-u ? s1 p38 c txdd2(o) c ???p38 (i)c-u d d0-u d) for v850es/ff3-l ?s1 p39 c rxdd2 (i) c / intp8 (i) c ???p39 (i)c-u d d3-ui as1
112 chapter 2 pin functions user?s manual u18743ee1v2um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-21 port group 3: configuration registers register address initial value used bits v850es/fe3-l pmc3l ffff f446 h 00 h x x pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pm3l ffff f426 h ff h x x pm35 pm34 pm33 pm32 pm31 pm30 pfc3l ffff f466 h 00 h x x pfc35 pfc34 pfc33 pfc32 x x pfce3l ffff f706 h 00 h xxxpfec34pfce33pfce32xx p3l ffff f406 h undefined x x p35 p34 p33 p32 p31 p30 pu3l ffff fc46 h 00 h x x pu35 pu34 pu33 pu32 pu31 pu30 v850es/ff3-l pmc3l ffff f446 h 00 h x x pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pm3l ffff f426 h ff h x x pm35 pm34 pm33 pm32 pm31 pm30 pm3h ffff f427 h ff h xxxxxxpm39pm38 pm3 (16 bit) ffff f426 h ffff h pm315 to pm38 (pm3h) pm37 to pm30 (pm3l) pfc3l ffff f466 h 00 h x x pfc35 pfc34 pfc33 pfc32 x x pfce3l ffff f706 h 00 h xxxpfec34pfce33pfce32xx p3l ffff f406 h undefined x x p35 p34 p33 p32 p31 p30 p3h ffff f407 h undefinedxxxxxxp39p38 p3 (16 bit) ffff f406 h undefined p315 to p38 (p3h) p37 to p30 (p3l) pu3l ffff fc46 h 00 h x x pu35 pu34 pu33 pu32 pu31 pu30 pu3h ffff fc47 h 00 h xxxxxxpu39pu38 pu3 (16 bit) ffff fc46 h 0000 h pu315 to pu38 (pu3h) pu37 to pu30 (pu3l) v850es/fg3-l pmc3l ffff f446 h 00 h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pmc3h ffff f447 h 00 h xxxxxxpmc39pmc38 pmc3 (16 bit) ffff f446 h 0000 h pmc315 to pmc38 (pmc3h) pmc37 to pmc30 (pmc3l) pm3l ffff f426 h ff h pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3h ffff f427 h ff h xxxxxxpm39pm38 pm3 (16 bit) ffff f426 h ffff h pm315 to pm38 (pm3h) pm37 to pm30 (pm3l) pfc3l ffff f466 h 00 h x x pfc35 pfc34 pfc33 pfc32 x x pfce3l ffff f706 h 00 h xxxpfec34pfce33pfce32xx p3l ffff f406 h undefined p37 p36 p35 p34 p33 p32 p31 p30 p3h ffff f407 h undefinedxxxxxxp39p38 p3 (16 bit) ffff f426 h undefined p315 to p38 (p3h) p37 to p30 (p3l) pu3l ffff fc46 h 00 h pu37 pu36 pu35 pu34 pu33 pu32 pu31 pu30 pu3h ffff fc47 h 00 h xxxxxxpu39pu38 pu3 (16 bit) ffff fc46 h 0000 h pu315 to pu38 (pu3h) pu37 to pu30 (pu3l)
113 pin functions chapter 2 user?s manual u18743ee1v2um00 2.5.6 port group 4 port group 4 is a 3-bit port group. in alternative mode, it comprises pins for the following functions:  external interrupt (intp14)  key interrupt input (kr0 to kr2)  clocked serial interface csib0 data/clock line (sib0, sob0, sckb0) port group 4 includes the following pins: note alternative functions kr0 to kr2 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?pin function configuration? on page 37 . access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-22 port group 4: pin functions and buffer pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter only for krn, intpn inputs b: analog and digital noise filter ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm =0) alternative mode (pmcnm = 1) pfce = 0 pfce = 1 function 1 pfc = 0 function 2 pfc = 1 function 3 pfc = 0 function 4 pfc = 1 p40 sib0 (i) kr0 (i) ? ? p40 (i) e11-u a s1 p41 sob0 (o) kr1 (i) ? ? p41 (i) e01-u a s2 p42 sckb0 (i/o) kr2 (i) ? ? p42 (i) e21-u a s2 table 2-23 port group 4: configuration registers register address initial value used bits pmc4 ffff f448 h 00 h xxxxxpmc42pmc41pmc40 pm4 ffff f428 h ff h xxxxxpm42pm41pm40 pfc4 ffff f468 h 00 h xxxxxpfc42pfc41pfc40 p4 ffff f408 h undefinedxxxxxp42p41p40 pu4 ffff fc48 h 00 h xxxxxpu42pu41pu40
114 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5.7 port group 5 port group 5 is an 8-bit port group. in alternative mode, it comprises pins for the following functions:  key interrupt input 0 to 5 (kr0 to kr5)  n-wire debug interface signals (ddi, ddo, dck, dms) port group 5 includes the following pins: note alternative functions kr0 to kr2 are provided on two pins each. thus you can select on which pin the alternative function should appear. refer to ?pin function configuration? on page 37 . table 2-24 port group 5: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter only for krn, tiabnm inputs b: analog and digital noise filter ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmc = 0) alternative mode (pmcnm = 1) on-chip debug mode (ocdm0 = 1) pfce = 0 pfce = 1 function 1 pfc = 0 function 2 pfc = 1 function 3 pfc = 0 function 4 pfc = 1 p50 kr0 (i) ? ? ? ? p50 (i) d1-u a s2 p51 kr1 (i) ? ? ? ? p51 (i) d1-u a s2 p52 kr2 (i) ? ? ? ddi (i) p52 (i) or ddi (i) c c) the pin function after reset depends on the reset source, that means on bit ocdm.ocdm0. refer to ?ocdm - on-chip debug mode register? on page 42 and to ?on-chip debug unit? on page 723 . d101-u a s2 p53 kr3 (i) ? ? ? ddo (o) p53 (i) or ddo (o) c d101-u a s2 p54 kr4 (i) ? ? ? dck (i) p54 (i) or dck (i) c d101-u a s2 p55 kr5 (i) ? ? ? dms (i) p55 (i) or dms (i) c d101-u a s2
115 pin functions chapter 2 user?s manual u18743ee1v2um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-25 port group 5: configuration registers register address initial value used bits pmc5 ffff f44a h 00 h x x pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 pm5 ffff f42a h ff h x x pm55 pm54 pm53 pm52 pm51 pm50 ocdm ffff f9fc h 00 h / 01 h a a) depends on the reset source (refer to ?ocdm - on-chip debug mode register? on page 42 and to ?on-chip debug unit? on page 723 ) 0000000ocdm0 p5 ffff f40a h undefined x x p55 p54 p53 p52 p51 p50 pu5 ffff fc4a h 00 h x x pu55 pu54 pu53 pu52 pu51 pu50
116 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5.8 port group 7 port group 7 is a 16-bit port group. it includes pins for the following functions:  a/d converter 0 inputs port group 7 includes the following pins: table 2-26 port group 7: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter; b: analog and digital noise filter; ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm = 0) alternative mode (pmcnm = 1) p70 ani0 (i) p70 (i) d1a ? x p71 ani1 (i) p71 (i) d1a ? x p72 ani2 (i) p72 (i) d1a ? x p73 ani3 (i) p73 (i) d1a ? x p74 ani4 (i) p74 (i) d1a ? x p75 ani5 (i) p75 (i) d1a ? x p76 ani6 (i) p76 (i) d1a ? x p77 ani7 (i) p77 (i) d1a ? x p78 ani8 (i) p78 (i) d1a ? x p79 ani9 (i) p79 (i) d1a ? x p710 c c) not available for v850es/fe3-l ani10 (i) p710 (i) d1a ? x p711 c ani11 (i) p711 (i) d1a ? x p712 d d) not available for v850es/fe3-l and v850es/ff3-l ani12 (i) p712 (i) d1a ? x p713 d ani13 (i) p713 (i) d1a ? x p714 d ani14 (i) p714 (i) d1a ? x p715 d ani15 (i) p715 (i) d1a ? x
117 pin functions chapter 2 user?s manual u18743ee1v2um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. caution the port status cannot be read if the port is used as an analog input. table 2-27 port group 7: configuration registers register address initial value used bits pmc7l ffff f44e h 00 h pmc77 pmc76 pmc75 pmc74 pmc73 pmc72 pmc71 pmc70 pmc7h ffff f44f h 00 h pmc715 a pmc714 a pmc713 a pmc712 a a) not available for v850es/fe3-l and v850es/ff3-l pmc711 b pmc710 b b) not available for v850es/fe3-l pmc79 pmc78 pm7l ffff f42e h ff h pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 pm7h ffff f42f h ff h pm715 a pm714 a pm713 a pm712 a pm711 b pm710 b pm79 pm78 p7l ffff f40e h undefined p77 p76 p75 p74 p73 p72 p71 p70 p7h ffff f40f h undefined p715 a p714 a p713 a p712 a p711 b p710 b p79 p78
118 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5.9 port group 9 port group 9 is an 16-bit port group. in alternative mode, it comprises pins for the following functions:  external interrupt (intp4 to intp6)  key interrupt input 6 to 7 (kr6 to kr7)  timer taa2 channels (tiaa20, tiaa21 and toaa20, toaa21)  clocked serial interface csib1 data/clock line (sob1, sib1, sckb1)  uartd1 transmit/receive data (txdd1, rxdd1) i 2 c data/clock line (sda00, scl00)  programmable clock output (pcl) note if p914 and p915 are in output port mode (pmc9.pmc9m = 0 and pm9.pm9m = 0), the pf9h register specifies normal output or open-drain output.
119 pin functions chapter 2 user?s manual u18743ee1v2um00 table 2-28 port group 9: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter only for krn, tiabnm inputs b: analog and digital noise filter ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm = 0) alternative mode (pmcnm = 1) pfce = 0 pfce = 1 function 1 pfc = 0 function 2 pfc = 1 function 3 pfc = 0 function 4 pfc = 1 p90 prohibited kr6 (i) txdd1 (o) prohibited p90 (i) fx10x -u as2 p91 prohibited kr7 (i) rxdd1 (i) kr7 (i) prohibited p91 (i) fx13x -u as1 p92 c c) not available for v850es/fe3-l and v850es/ff3-l ? ? ? ?p92 (i)c-u ?s2 p93 c ? ? ? ?p93 (i)c-u ?s2 p94 c ? ? ? ?p94 (i)c-u ?s2 p95 c ? ? ? ?p95 (i)c-u ?s2 p96 prohibited prohibited tiaa21 (i) toaa21 (o) p96 (i) fxx10 -u as2 p97 prohibited sib1 (i) tiaa20 (i) toaa20 (o) p97 (i) fx110 -u as2 p98 prohibited sob1 (o) prohibited prohibited p98 (i) ex0-u ? s2 p99 prohibited sckb1 (i/o) prohibited prohibited p99 (i) ex2-u a s2 p910 c ? ? ? ?p910 (i)c-u ?s2 p911 c ? ? ? ?p911 (i)c-u ?s1 p912 c ? ? ? ?p912 (i)c-u ?s2 p913 prohibited intp4 pcl (o) intp4 (i) p913 (i) fx10x -ui as1 p914 prohibited intp5 sda00 (i/o) intp5 (i) p914 (i) fx12x -ufi as1 p915 prohibited intp6 scl00 (i/o) prohibited p915 (i) fx12x -ufi as1
120 chapter 2 pin functions user?s manual u18743ee1v2um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-29 port group 9: v850es/fe3-l, v850es/ff3-l configuration registers register address initial value used bits pmc9l ffff f452 h 00 h pmc97pmc96xxxxpmc91pmc90 pmc9h ffff f453 h 00 h pmc915 pmc914 pmc913 x x x pmc99 pmc98 pmc9 (16 bit) ffff f452 h 0000 h pmc915 to pmc98 (pmc9h) pmc97 to pmc90 (pmc9l) pm9l ffff f432 h ff h pm97 pm96 x x x x pm91 pm90 pm9h ffff f433 h ff h pm915 pm914 pm913 x x x pm99 pm98 pm9 (16 bit) ffff f432 h ffff h pm915 to pm98 (pm9h) pm97 to pm90 (pm9l) pfc9l ffff f472 h 00 h pfc97pfc96xxxxpfc91pfc90 pfc9h ffff f473 h 00 h pfc915 pfc914 pfc913 x x x pfc99 pfc98 pfc9 (16 bit) ffff f472 h 0000 h pfc915 to pfc98 (pfc9h) pfc97 to pfc90 (pfc9l) pfce9l ffff f712 h 00 h pfce97 pfce96 x x x x pfce91 pfce90 pfce9h ffff f713 h 00 h pfce915 pfce914 pfce913 x x x x x pfce9 (16 bit) ffff f712 h 0000 h pfce915 to pfce98 (pfce9h) pfce97 to pfce90 (pfce9l) p9l ffff f412 h undefined p97p96xxxxp91p90 p9h ffff f413 h undefined p915 p914 p913 x x x p99 p98 p9 (16 bit) ffff f412 h undefined p915 to p98 (p9h) p97 to p90 (p9l) pu9l ffff fc52 h 00 h pu97 pu96 x x x x pu91 pu90 pu9h ffff fc53 h 00 h pu915 pu914 pu913 x x x pu99 pu98 pu9 (16 bit) ffff fc52 h 0000 h pu915 to pu98 (pu9h) pu97 to pu90 (pu9l) pf9h ffff fc73 h 00 h pf915 pf914 x x x x x x
121 pin functions chapter 2 user?s manual u18743ee1v2um00 access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-30 port group 9: v850es/fg3-l configuration registers register address initial value used bits pmc9l ffff f452 h 00 h pmc97pmc96xxxxpmc91pmc90 pmc9h ffff f453 h 00 h pmc915 pmc914 pmc913 x x x pmc99 pmc98 pmc9 (16 bit) ffff f452 h 0000 h pmc915 to pmc98 (pmc9h) pmc97 to pmc90 (pmc9l) pm9l ffff f432 h ff h pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9h ffff f433 h ff h pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 pm9 (16 bit) ffff f432 h ffff h pm915 to pm98 (pm9h) pm97 to pm90 (pm9l) pfc9l ffff f472 h 00 h pfc97pfc96xxxxpfc91pfc90 pfc9h ffff f473 h 00 h pfc915 pfc914 pfc913 x x x pfc99 pfc98 pfc9 (16 bit) ffff f472 h 0000 h pfc915 to pfc98 (pfc9h) pfc97 to pfc90 (pfc9l) pfce9l ffff f712 h 00 h pfce97 pfce96 x x x x pfce91 pfce90 pfce9h ffff f713 h 00 h pfce915 pfce914 pfce913 x x x x x pfce9 (16 bit) ffff f712 h 0000 h pfce915 to pfce98 (pfce9h) pfce97 to pfce90 (pfce9l) p9l ffff f412 h undefined p97 p96 p95 p94 p93 p92 p91 p90 p9h ffff f413 h undefined p915 p914 p913 p912 p911 p910 p99 p98 p9 (16 bit) ffff f412 h undefined p915 to p98 (p9h) p97 to p90 (p9l) pu9l ffff fc52 h 00 h pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 pu9h ffff fc53 h 00 h pu915 pu914 pu913 pu912 pu911 pu910 pu99 pu98 pu9 (16 bit) ffff fc52 h 0000 h pu915 to pu98 (pu9h) pu97 to pu90 (pu9l) pf9h ffff fc73 h 00 h pf915 pf914 x x x x x x
122 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5.10 port group cm port group cm is a 6-bit port group. in alternative mode, it comprises pins for the following functions:  cpu system clock output (clkout) port group cm includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-31 port group cm: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter; b: analog and digital noise filter; ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm = 0) alternative mode (pmcnm = 1) pcm0 ? pcm0 (i) c ? x pcm1 clkout (o) pcm1 (i) d0 ? x pcm2 c c) not available on v850es/fe3-l ?pcm2 (i)c?x pcm3 c ?pcm3 (i)c?x table 2-32 port group cm: configuration registers register address initial value used bits pmccm ffff f04c h 00 h xxxxxx pmccm1 x pmcm ffff f02c h ff h xxxxpmcm3 a a) not available for v850es/fe3-l pmcm2 pmcm1 pmcm0 pcm ffff f00c h undefinedxxxxpcm3 a pcm2 a pcm1 pcm0
123 pin functions chapter 2 user?s manual u18743ee1v2um00 2.5.11 port group cs (v850es/ff3-l, v850es/fg3-l) note port group cs is available only for v850es/ff3-l, v850es/fg3-l port group cs is an 8-bit port group. in alternative mode, it comprises pins for the following functions: port group cs includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-33 port group cs: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter; b: analog and digital noise filter; ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm = 0) alternative mode (pmcnm = 1) pcs0 ? pcs0 (i) c ? x pcs1 ? pcs1 (i) c ? x table 2-34 port group cs: configuration registers register address initial value used bits pmcs ffff f028 h ff h xxxxxxpmcs1pmcs0 pcs ffff f008 h undefinedxxxxxxpcs1pcs0
124 chapter 2 pin functions user?s manual u18743ee1v2um00 2.5.12 port group ct (v85 0es/ff3-l, v850es/fg3-l) note port group ct is available only for v850es/ff3-l, v850es/fg3-l. port group ct is an 8-bit port group. in alternative mode, it comprises pins for the following functions: port group ct includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. table 2-35 port group ct: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter; b: analog and digital noise filter; ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm = 0) alternative mode (pmcnm = 1) pct0 ? pct0 (i) c ? x pct1 ? pct1 (i) c ? x pct4 ? pct4 (i) c ? x pct6 ? pct6 (i) c ? x table 2-36 port group ct: configuration registers register address initial value used bits pmct ffff f02a h ff h xpmct6xpmct4xxpmct1pmct0 pct ffff f00a h undefined x pct6 x pct4 x x pct1 pct0
125 pin functions chapter 2 user?s manual u18743ee1v2um00 2.5.13 port group dl port group dl is an 16-bit input/output port group. port group dl includes the following pins: access all 8-bit registers can be accessed in 8-bit or 1-bit units. all 16-bit registers can be accessed in 16-bit units. table 2-37 port group dl: pin functions and buffer types pin functions in different modes pin function after reset port type noise filter a a) a: analog noise filter; b: analog and digital noise filter; ?: no noise filter input charact. b b) s1: schmitt trigger (30/70%); s2: schmitt trigger (40/80%); x: cmos port mode (pmcnm = 0) alternative mode (pmcnm = 1) pdl0 ? pdl0 (i) c ? s2 pdl1 ? pdl1 (i) c ? s2 pdl2 ? pdl2 (i) c ? s2 pdl3 ? pdl3 (i) c ? s2 pdl4 ? pdl4 (i) c ? s2 pdl5 flmd1 (i) pdl5 (i) c ? s2 pdl6 ? pdl6 (i) c ? s2 pdl7 ? pdl7 (i) c ? s2 pdl8 c c) not available for v850es/fe3-l ?pdl8 (i)c?s2 pdl9 c ?pdl9 (i)c?s2 pdl10 c ? pdl10 (i) c ? s2 pdl11 c ? pdl11 (i) c ? s2 pdl12 d d) not available for v850es/fe3-l, v850es/ff3-l ? pdl12 (i) c ? s2 pdl13 c ? pdl13 (i) c ? s2 table 2-38 port group dl: configuration registers register address initial value used bits pmdll ffff f024 h ff h pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 pmdlh a a) not available for v850es/fe3-l ffff f025 h ff h xxpmdl13 b b) not available for v850es/fe3-l, v850es/ff3-l pmdl12 b pmdl11 a pmdl10 a pmdl9 pmdl8 pmdl (16 bit) a ffff f024 h ffff h pmdl15 to pmdl8 (pmdlh) pmdl7 to pmdl0 (pmdll) pdll ffff f004 h undefined pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdlh a ffff f005 h undefined x x pdl13 b pdl12 b pdl11 a pdl10 a pdl9 pdl8 pdl (16 bit) a ffff f004 h undefined pdl15 to pdl8 (pdlh) pdl7 to pdl0 (pdll)
126 chapter 2 pin functions user?s manual u18743ee1v2um00 2.6 noise elimination the input signals at some pins are passing a filter to remove noise and glitches. the microcontroller supports both analog and digital filters. in table 2-16 on page 108 and in the following tables it is listed whether a pin is equipped with an analog filter, a digital filter, both analog and digital filter, or no filter at all. 2.6.1 analog filtered inputs the following input signals are passed through an analog filter to remove noise and glitches:  non-maskable interrupt (nmi)  external interrupts (intpn)  key interrupt inputs (krn)  timer taa trigger inputs (tiaanm)  a/d converter external input triggers (adtrg)  n-wire debug interface reset (drst) the analog filter suppresses input pulses that are shorter than a specified pulse width (refer to the electrical target specification). this assures the hold time for the external interrupt signals. the analog filter operates in all modes (normal mode and standby modes). it is only effective if the corresponding pin works in alternative input mode and not as a general purpose i/o port.
127 pin functions chapter 2 user?s manual u18743ee1v2um00 2.6.2 digitally filtered inputs the input signal intp3 is passed through both an analog and a digital filter. the digital filter operates in all modes, in which fxx is available. thus, it does not operate in standby modes (if fxt is used as the sampling clock, it can operate in standby modes). the digital filter is only effective if the corresponding pin works in alternative input mode and not as a general purpose i/o port. filter operation the input terminal signal is sampled with the sampling frequency f s. spikes shorter than n-1 sampling cycles are suppressed and no internal signal is generated. pulses longer than n sampling cycles are recognized as valid pulses and an internal signal is generated. the pulses between n-1 and n sampling cycles are eliminated as noise, or detected as a valid edge. the characteristics of the digital filter can be set by the nfc register. the characteristic of the digital noise filter is determined by the register nfc: f s is defined by nfc.nfc[2:0] f s is the sampling frequency. together with n it defines the minimum input terminal pulse width to be validated.  n is defined by nfc.nfsts possible values for n are 2 or 3. the filter operation is illustrated in figure 2-58 for nfc.nfsts = 0 (n = 3). figure 2-58 digital noise removal example for nfc.nfsts = 0 (n = 3) input terminal filter output
128 chapter 2 pin functions user?s manual u18743ee1v2um00 (1) nfc - digital noise filter control register the 8-bit nfc register specifies the noise elimination circuit for signal intp3. access this register can be read/written in 8-bit and 1-bit units. address ffff f318 h initial value 00 h . this register is cleared by any reset. note 1. f xx = system clock f xt = sub oscillator frequency). remark if fs is set to fxx/64, fxx/128, fxx/256, fxx/512, fxx/1024, or fxx/2048, it cannot be used to release the standby mode, because the sampling clock stops in the idle1, idle2 mode, or stop mode. in this case, set fs to fxt or connect the analog noise elimination circuit (setting not to execute digital noise elimination) to release the standby mode. caution after the sampling clock has been changed, it takes n sampling clocks (defined sampling frequency n = 3 or 2) to initialize the digital noise eliminator. therefore, if an intp3 valid edge is input within these n sampling clocks time after the sampling clock has been changed, an interrupt request signal may be generated. therefore, be careful about the following points when using the interrupt and 76543210 nfen nfsts 0 0 0 nfc2 nfc1 nfc0 r/w r/w r r r r/w r/w r/w table 2-39 nfc register contents bit position bit name function 7nfen enables/disables digital noise elimination at pin intp3: 0: digital noise elimination is disabled. 1: digital noise elimination is enabled. 6nfsts defines the number of sampling periods n of f s to validate the external signal: 0: n = 3 1: n = 2 2 to 0 nfc[2:0] defines the sampling frequency f s for digital noise removal: nfc2 nfc1 nfc0 sampling frequency f s 00 0 f xx /64 00 1 f xx /128 01 0 f xx /256 01 1 f xx /512 10 0 f xx /1024 10 1 f xt 11 0 setting prohibited 11 1
129 pin functions chapter 2 user?s manual u18743ee1v2um00 dma functions. when using the interrupt function, after the n sampling clocks (selected sampling frequency n = 3 or 2) have elapsed, enable interrupts after the interrupt request flag (pic3.pif3 bit) has been cleared. when using the dma function (started by intp3), enable dma after the n sampling clocks have elapsed.
130 chapter 2 pin functions user?s manual u18743ee1v2um00 2.7 pin functions in reset and power save modes the following table summarizes the status of the pins during reset and power save modes and after release of these operating states in normal operation mode. the reset source makes a difference concerning the n-wire debugger interface pins drst , ddi, ddo, dck and dms after reset release. an external reset or an internal power-on-clear switches all pins to input port mode, while all other internal reset sources make the pins available for the debugger. in contrast to all other power save modes the halt mode suspends only the cpu operation and has no effect on any pin status. m table 2-40 pin functions and reset / power save modes operating status pin status external reset during  p05/drst : p05 port input with internal pull-down resistor  all other pins: hi-impedence after  p05/drst : drst input with internal pull-down resistor  p52/ddi, p54/dck, p55/dms: ddi, dck, dms inputs  p53/ddo: ddo output  all other pins: input port mode power-on- clear (poc) during  p05/drst : p05 port input with internal pull-down resistor  all other pins: hi-impedence after input port mode all other reset sources during  p05/drst , p52/ddi, p53/ddi, p54/dck, p55/dms: same as before reset  all other pins: input port mode after halt mode during same as before halt mode after idle 1, idle 2, stop mode during same as before power save mode:  output signals are valid and output levels are remained.  input signals with wake-up capability a are valid.  input signals without wake-up capability are ignored. a) inputs with wake-up capability: external interrupts (intp0 to intp11, nmi) and can0 receive data (crxd0) after same as before power save mode
131 pin functions chapter 2 user?s manual u18743ee1v2um00 2.8 recommended connection of unused pins if a pin is not used, it is recommended to connect it as follows: note 1. when connecting the unused pins with a power supply or ground, it is recommended to connect the pins through a resistance of 1 to 10 k ? . 2. if the overall maximum output current exceeds its maximum value the output buffer can be damaged. we recommend the placement of a series resistor to prevent damage in case of accidentally enabled outputs. refer to the absolute maximum rating parameter in the electrical target specification. table 2-41 recommended connection of unused pins pin recommended connection port pins pins of port groups 0, 1, 3 to 5, 9 (except p05 of port group 0)  output pins: leave open  input pins: connect to evdd or evss via a resistor p05 of port group 0  output pins: leave open  input pins: connect to evss via a resistor pins of port groups 7  output pins: leave open  input pins: connect to avref0 or avss via a resistor pins of port groups cm, cs, ct, dl  output pins: leave open  input pins: connect to bvdd or bvss via a resistor non-port pins avref0 connect to vdd flmd0 connect to vss regc connect to regulator output stability capacity xt1 connect to vss via a resistor xt2 leave open not connect pins ic connect directly to vss via a resistor
132 chapter 2 pin functions user?s manual u18743ee1v2um00 2.9 package pins assignment the following figures shows the location of pins in top view. every pin is labelled with its pin number and all possible pin names. 2.9.1 v850es/fe3-l pack age pins assignment figure 2-59 v850es/fe3-l package pin assignment p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 pdl7 pdl6 pdl5/flmd1 pdl4 pdl3 pdl2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avref0 1 48 pdl1 avss 2 47 pdl0 flmd0 3 46 pcm1/clkout vdd 4 45 pcm0 regc 5 44 p915/intp6/scl00 vss 6 43 p914/intp5/sda00 x1 7 42 p913/intp4/pcl x2 8 41 p99/sckb1 9 40 p98/sob1 xt1 10 39 p97/sib1/tiaa20/toaa20 xt2 11 38 p96/tiaa21/toaa21 p00/tiaa31/toaa31 12 37 p91/kr7/rxdd1 p01/tiaa30/toaa30 13 36 p90/kr6/txdd1 p02/nmi/tiaa40/toaa40 14 35 p55/kr5/dms p03/intp0/adtrg/tiaa41/toaa41 15 34 p54/kr4/dck p04/intp1/crxd0 16 33 evdd 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p05/intp2/drst p06/intp3/ctxd0 p40/sib0/kr0 p41/sob0/kr1 p42/sckb0/kr2 p30/txdd0 p31/rxdd0/intp7 p32/asckd0/toaa01/tiaa00/toaa00 p33/tiaa01/toaa01/ctxd0 p34/tiaa10/toaa10/crxd0 p35/tiaa11/toaa11 p50/kr0 p51/kr1 p52/kr2/ddi p53/kr3ddo evss pd70f3610gb-gah pd70f3611gb-gah pd70f3612gb-gah pd70f3613gb-gah pd70f3 614gb-gah reset
133 pin functions chapter 2 user?s manual u18743ee1v2um00 2.9.2 v850es/ff3-l package pins assignment figure 2-60 v850es/ff3-l package pin assignment p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 pdl11 pdl10 pdl9 pdl8 pdl7 pdl6 pdl5/flmd1 pdl4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 avref0 1 60 pdl3 avss 2 59 pdl2 p00/tiaa31/toaa31 3 58 pdl1 p01/tiaa30/toaa30 4 57 pdl0 p02/nmi/tiaa40/toaa40 5 56 pct6 p03/intp0/adtrg/tiaa41/toaa41 6 55 pct4 p04/intp1/crxd0 7 54 pct1 flmd0 8 53 pct0 vdd 9 52 pcm3 regc 10 51 pcm2 vss 11 50 pcm1/clkout x1 12 49 pcm0 x2 13 48 pcs1 14 47 pcs0 xt1 15 46 p915/intp6/scl00 xt2 16 45 p914/intp5/sda00 p05/intp2/drst 17 44 p913/intp4/pcl p06/intp3/ctxd0 18 43 p99/sckb1 p40/sib0/kr0 19 42 p98/sob1 p41/sob0/kr1 20 41 p97/sib1/tiaa20/toaa20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p42/sckb0/kr2 p30/txdd0 p31/rxdd0/intp7 p32/asckd0/toaa01/tiaa00/toaa00 p33/tiaa01/toaa01/ctxd0 p34/tiaa10/toaa10/crxd0 p35/tiaa11/toaa11 p38 p39 evss evdd p50/kr0 p51/kr1 p54/kr4/dck p55/kr5/dms p90/kr6/txdd1 p91/kr7/rxdd1 p96/tiaa21/toaa21 pd70f3615gk-gak pd70f3616gk-gak pd70f3617gk-gak pd70f3618gk-gak pd70f3619gk-gak reset p53/kr3/ddo p52/kr2/ddi
134 chapter 2 pin functions user?s manual u18743ee1v2um00 2.9.3 v850es/fg3-l pack age pins assignment figure 2-61 v850es/fg3-l package pin assignment p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 p712/ani12 p713/ani13 p714/ani14 p715/ani15 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 pdl7 pdl6 pdl5/flmd1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 avref0 1 75 pdl4 avss 2 74 pdl3 p10/intp9 3 73 pdl2 p11/intp10 4 72 pdl1 evdd 5 71 pdl0 p00/tiaa31/toaa31 6 70 bvdd p01/tiaa30/toaa30 7 69 bvss flmd0 8 68 pct6 vdd 9 67 pct4 regc 10 66 pct1 vss 11 65 pct0 x1 12 64 pcm3 x2 13 63 pcm2 reset 14 62 pcm1/clkout xt1 15 61 pcm0 xt2 16 60 pcs1 p02/nmi/tiaa40/toaa40 17 59 pcs0 p03/intp0/adtrg/tiaa41/toaa41 18 58 p915/intp6/scl00 p04/intp1/crxd0 19 57 p914/intp5/sda00 p05/intp2/drst 20 56 p913/intp4/pcl p06/intp3/ctxd0 21 55 p912 p40/sib0/kr0 22 54 p911 p41/sob0/kr1 23 53 p910 p42/sckb0/kr2 24 52 p99/sckb1 p30/txdd0 25 51 p98/sob1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p31/rxdd0/intp7 p32/asckd0/toaa01/tiaa00/toaa00 p33/tiaa01/toaa01/ctxd0 p34/tiaa10/toaa10/crxd0 p35/tiaa11/toaa11 p36 p37 evss evdd p38/txdd2 p39/rxdd2/intp8 p50/kr0 p51/kr1 p52/kr2/ddi p53/kr3/ddo p54/kr4/dck p55/kr5/dms p90/kr6/txdd1 p91/kr7/rxdd1 p92 p93 p94 p95 p96/tiaa21/toaa21 p97/sib1/tiaa20/toaa20 pd70f3620gc-ueu pd70f3621gc-ueu pd70f3622gc-ueu
135 user?s manual u18743ee1v2um00 chapter 3 cpu system functions this chapter describes the registers of the cpu, the operation modes, the address space and the memory areas. 3.1 overview the cpu is founded on harvard architecture and it supports a risc instruction set. basic instructions can be executed in one clock period. optimized five- stage pipelining is supported. this improves instruction execution speed. in order to make the microcontroller ideal for use in digital control applications, a 16-bit hardware multiplier enables this cpu to support word/half-word multiply instructions, saturated multiply instructions, bit operation instructions, etc. features summary the cpu has the following special features:  memory space: ? 64 mb linear program space ? 4 gb linear data space  32 general purpose registers  internal 32-bit architecture  five-stage pipeline  efficient multiplication and division instructions  saturation logic (saturated operation instructions)  barrel shifter (32-bit shift in one clock cycle)  instruction formats: long and short  four types of bit manipulation instructions: set, clear, not, test
136 chapter 3 cpu system functions user?s manual u18743ee1v2um00 3.1.1 description the figure below shows a block diagram of the microcontroller, focusing on the cpu and modules that interact with the cpu directly. ta bl e 3 - 1 lists the bus types. figure 3-1 cpu system the shaded busses are used for accessing the configuration registers of the concerned modules. program counter general-purpose registers multiplier (16 x 16 ? 32) alu barrel shifter cpu v s b system controller bus bridge (bbr) instruction queue bus control unit (bcu) npb v d b v f b system registers rcu interface standby control unit (stbc) interrupt control unit (intc) table 3-1 bus types bus type function npb ? peripheral bus bus interface to the peripherals (internal bus). vsb ? system bus bus interface to the memory controller for access to the npb bus bridge bbr. vfb ? fetch bus interface to the internal rom (mask rom or code flash). vdb ? data bus interface to the internal ram.
137 cpu system functions chapter 3 user?s manual u18743ee1v2um00 3.2 cpu register set there are two categories of registers:  general purpose registers  system registers all registers are 32-bit registers. an overview is given in the figure below. for details, refer to v850es user?s manual architecture. figure 3-2 cpu register set some registers are write protected. that means, writing to those registers is protected by a special sequence of instructions. refer to ?write protected registers? on page 155 for more details. r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 0 r1 1 r1 2 r1 3 r1 4 r1 5 r1 6 r1 7 r1 8 r1 9 r2 0 r2 1 r2 2 r2 3 r2 4 r2 5 r2 6 r2 7 r2 8 r2 9 r3 0 r3 1 31 0 31 0 (zero register) (reserved for assembler) (interrupt stack pointer) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) (program counter) pc (callt base pointer) ctbp (status saving register during exception/debug trap) dbpsw (status saving register during exception/debug trap) dbpc (status saving register during callt execution) ctpsw (status saving register during callt execution) ctpc (program status word) psw (interrupt/execution source register) ecr (status saving register during nmi) fepsw (status saving register during nmi) fepc (status saving register during interrupt) eipsw (status saving register during interrupt) eipc
138 chapter 3 cpu system functions user?s manual u18743ee1v2um00 3.2.1 general purpose registers (r0 to r31) each of the 32 general purpose registers can be used as a data variable or address variable. however, the registers r0, r1, r3 to r5, r30, and r31 may implicitly be used by the assembler/compiler (see table ta b l e 3 - 2 ). for details refer to the documentation of your assembler/compiler. caution before using registers r1, r3 to r5, r30, and r31, their contents must be saved so that they are not lost. the contents must be restored to the registers after the registers have been used. table 3-2 general purpose registers register name usage operation r0 zero register always holds 0. it is used for operations using 0 and offset 0 addressing. a a) registers r0 and r30 are used by dedicated instructions. r1 assembler-reserved register used for 32-bit direct addressing. b b) registers r1, r3, r4, r5, and r31 may be used by the assembler/compiler. r2 user address/data variable register r3 stack pointer used to generate stack frame when function is called. b r4 global pointer used to access global variable in data area. b r5 text pointer used to indicate the start of the text area (where program code is located). b r6 to r29 user address/data variable registers r30 element pointer base pointer when memory is accessed by means of instructions sld (short format load) and sst (short format store). a r31 link pointer used when calling a function. b
139 cpu system functions chapter 3 user?s manual u18743ee1v2um00 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. additionally, the program counter holds the instruction address during program execution. to read/write the system registers, use instructions ldsr (load to system register) or stsr (store contents of system register), respectively, with a specific system register number (regid) indicated below. the program counter states an exception. it cannot be accessed via ldsr or stsr instructions. no regid is allocated to the program counter. example stsr 0, r2 stores the contents of system register 0 (eipc) in general purpose register r2. system register numbers the table below gives an overview of all system registers and their system register number (regid). it shows whether a load/store instruction is allowed ( ) for the register or not ( ? ). table 3-3 system register numbers regid system register name shortcut operand specification ldsr stsr 0 status saving register during interrupt (stores contents of pc) eipc 1 status saving register during interrupt (stores contents of psw) eipsw 2 status saving register during non-maskable interrupts (stores contents of pc) fepc 3 status saving register during non-maskable interrupts (stores contents of psw) fepsw 4 interrupt source register ecr ? 5 program status word psw 6 to 15 reserved (operations that access these register numbers cannot be guaranteed). ?? 16 status saving register during callt execution (stores contents of pc) ctpc 17 status saving register during callt execution (stores contents of psw) ctpsw 18 status saving register during exception/debug trap (stores contents of pc) dbpc a a) reading from this register is only enabled between a dbtrap exception (exception handler address 0000 0060 h ) and the exception handler terminating dbret instruction. dbtrap exceptions are generated upon ilgop detections (refer to ?interrupt controller (intc)? on page 221 ). 19 status saving register during exception/debug trap (stores contents of psw) dbpsw a 20 callt base pointer ctbp 21 to 31 reserved (operations that access these register numbers cannot be guaranteed). ??
140 chapter 3 cpu system functions user?s manual u18743ee1v2um00 (1) pc - program counter the program counter holds the instruction address during program execution. the lower 26 bits are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. branching to an odd address cannot be performed. bit 0 is fixed to 0. access this register can not be accessed by any instruction. initial value 0000 0000 h . the program counter is cleared by any reset. (2) eipc, fepc, dbpc, ctpc - pc saving registers the pc saving registers save the contents of the program counter for different occasions, see ta b l e 3 - 4 . when one of the occasions listed in ta bl e 3 - 4 occurs, except for some instructions, the address of the instruction following the one being executed is saved to the saving registers. for more details refer to table 3-9 on page 144 and to the ?interrupt controller (intc)? on page 221 . all pc saving registers are built up as the pc, with the initial value 0xxx xxxx h (x = undefined). note when multiple interrupt servicing is enabled, the contents of eipc or fepc must be saved by program?because only one pc saving register for maskable interrupts and non-maskable interrupts is provided, respectively. caution when setting the value of any of the pc saving registers, use even values (bit 0 = 0). if bit 0 is set to 1, the setting of this bit is ignored. this is because bit 0 of the program counter is fixed to 0. 31 26 25 1 0 fixed to 0 instruction address during execution 0 table 3-4 pc saving registers register shortcut saves contents of pc in case of status saving register during interrupt eipc  software exception  maskable interrupt status saving register during non-maskable interrupts fepc  non-maskable interrupt status saving register during exception/debug trap dbpc a a) reading from this register is only enabled between a dbtrap exception (excep- tion handler address 0000 0060 h ) and the exception handler terminating dbret instruction. dbtrap exceptions are generated upon ilgop detections (refer to ?interrupt controller (intc)? on page 221 ).  exception trap  debug trap  debug break  during a single-step operation status saving register during callt execution ctpc  execution of callt instruction
141 cpu system functions chapter 3 user?s manual u18743ee1v2um00 (3) psw - program status word the 32-bit program status word is a collection of flags that indicates the status of the program (result of instruction execution) and the status of the cpu. if the bits in the register are modified by the ldsr instruction, the psw will take on the new value immediately after the ldsr instruction has been executed. initial value 0000 0020 h . the program status is initialized by any reset. 31 876543210 fixed to 0 np ep id sat cy ov s z r r r/w r/w r/w r/w r/w r/w r/w r/w table 3-5 psw register contents (1/2) bit position flag function 7np indicates that non-maskable interrupt (nmi) servicing is in progress. this flag is set when nmi request is acknowledged, and multiple interrupt servicing is disabled. 0: nmi servicing is not in progress. 1: nmi servicing is in progress. 6ep indicates that exception processing is in progress. this flag is set when an exception occurs. even when this bit is set, interrupt requests can be acknowledged. 0: exception processing is not in progress. 1: exception processing is in progress. 5id indicates whether a maskable interrupt request can be acknowledged. 0: interrupts enabled. 1: interrupts disabled. note: setting this flag will disable interrupt requests even while the ldsr instruction is being executed. 4sat a for saturated operation processing instructions only: indicates that the operation result is saturated due to overflow. 0: not saturated. 1: saturated. note: 1. this is a cumulative flag: the bit is not automatically cleared if subsequent instructions lead to not saturated results. to clear this bit, use the ldsr instruction to set psw.sat = 0. 2. in a general arithmetic operation this bit is neglected. it is neither set nor cleared. 3cy carry/borrow flag. indicates whether a carry or borrow occurred as a result of the operation. 0: carry or borrow did not occur 1: carry or borrow occurred.
142 chapter 3 cpu system functions user?s manual u18743ee1v2um00 saturated operation instructions the following table shows the setting of flags pws.sat, pws.ov, and pws.s, depending on the status of the operation result. 2ov a overflow flag. indicates whether an overflow occurred as a result of the operation. 0: overflow did not occur. 1: overflow occurred. 1s a sign flag. indicates whether the result of the operation is negative. 0: result is positive or zero. 1: result is negative. 0z zero flag. indicates whether the result of the operation is zero. 0: result is not zero. 1: result is zero. a) in the case of saturate instructions, the sat, s, and ov flags will be set according to the result of the operation as shown in the table below. note that the sat flag is set only when the ov flag has been set during a satu- rated operation. table 3-5 psw register contents (2/2) bit position flag function table 3-6 saturation-processed operation result status of operation result flag status saturation-processed operation result sat ov s maximum positive value exceeded 1 1 0 7fff ffff h maximum negative value exceeded 1 1 1 8000 0000 h positive (maximum not exceeded) x a a) retains the value before operation. 0 0 operation result itself negative (maximum not exceeded) 1
143 cpu system functions chapter 3 user?s manual u18743ee1v2um00 (4) eipsw, fepsw, dbpsw, ctpswpsw saving registers the psw saving registers save the contents of the program status word for different occasions, see ta bl e 3 - 4 . when one of the occasions listed in ta bl e 3 - 4 occurs, the current value of the psw is saved to the saving registers. all psw saving registers are built up as the psw, with the initial value 0000 0xxx h (x = undefined). note when multiple interrupt servicing is enabled, the contents of eipsw or fepsw must be saved by program?because only one psw saving register for maskable interrupts and non-maskable interrupts is provided, respectively. caution bits 31 to 26 of eipc and bits 31 to 12 and 10 to 8 of eipsw are reserved for future function expansion (fixed to 0).when setting the value of eipc, fepc, or ctpc, use even values (bit 0 = 0). if bit 0 is set to 1, the setting of this bit is ignored. this is because bit 0 of the program counter is fixed to 0. table 3-7 psw saving registers register shortcut saves contents of psw in case of status saving register during interrupt eipsw  software exception  maskable interrupt status saving register during non-maskable interrupts fepsw  non-maskable interrupt status saving register during exception/debug trap dbpsw a a) reading from this register is only enabled between a dbtrap exception (excep- tion handler address 0000 0060 h ) and the exception handler terminating dbret instruction. dbtrap exceptions are generated upon ilgop detections (refer to ?interrupt controller (intc)? on page 221 ).  exception trap  debug trap  debug break  during a single-step operation status saving register during callt execution ctpsw  execution of callt instruction
144 chapter 3 cpu system functions user?s manual u18743ee1v2um00 (5) ecr - interrupt/exception source register the 32-bit ecr register displays the exception codes if an exception or an interrupt has occurred. with the exception code, the interrupt/exception source can be identified. for a list of interrupts/exceptions and corresponding exception codes, see table 3-9 on page 144 . initial value 0000 0000 h . this register is cleared by any reset. the following table lists the exception codes. 31 26 25 0 fecc eicc table 3-8 ecr register contents bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupts table 3-9 interrupt/execution codes interrupt/exception source classification exception code handler address value restored to eipc/fepc name trigg er non-maskable interrupts (nmi) nmi0 input interrupt 0010 h 0000 0010 h next pc (see note) nmi1 input interrupt 0020 h 0000 0020 h next pc (see note) nmi2 input interrupt 0030 h 0000 0030 h next pc (see note) maskable interrupt refer to ?interrupt controller (intc)? on page 221 interrupt refer to ?interrupt controller (intc)? on page 221  higher 16 bits: 0000 h  lower 16 bits: exception code next pc (see note) software exception trap0n (n = 0 to f h ) trap instruction exception 004n h 0000 0040 h next pc trap1n (n = 0 to f h ) trap instruction exception 005n h 0000 0050 h next pc exception trap (ilgop) illegal instruction code exception 0060 h 0000 0060 h next pc debug trap dbtrap instruction exception 0060 h 0000 0060 h next pc
145 cpu system functions chapter 3 user?s manual u18743ee1v2um00 if an interrupt (maskable or non-maskable) is acknowledged during instruction execution, generally, the address of the instruction following the one being executed is saved to the saving registers, except when an interrupt is acknowledged during execution of one of the following instructions:  load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w)  divide instructions (div, divh, divu, divhu)  prepare, dispose instruction (only if an interrupt is generated before the stack pointer is updated) in this case, the address of the interrupted instruction is restored to the eipc or fepc, respectively. execution is stopped, and after the completion of interrupt servicing the execution is resumed. (6) ctbp - callt base pointer the 32-bit callt base pointer is used with the callt instruction. the register content is used as a base address to generate both a 32-bit table entry address and a 32-bit target address. initial value undefined 31 30 29 28 27 26 25 1 0 0 0 0 0 0 0 base address 0 r a r a r a r a r a r a r/w r a) these bits may be written, but write is ignored.
146 chapter 3 cpu system functions user?s manual u18743ee1v2um00 3.3 operation modes this section describes the operation modes of the cpu and how the modes are specified. the following operation modes are available:  normal operation mode  flash programming mode after reset release, the microcontroller starts to fetch instructions from an internal boot rom which contains the internal firmware. the firmware checks the pins flmd0 and flmd1 (pdl5) to set the operation mode after reset release according to ta b l e 3 - 1 0 : note the flmd1 pin function is shared with the pdl5 pin. 3.3.1 normal operation mode in normal operation mode, the internal code flash memory is not re- programmed. after reset release, the firmware acquires the user's reset vector from the code flash memory. the reset vector contains the start address of the user?s program code. the firmware branches to that address. program execution is started. 3.3.2 flash programming mode (flash memory devices only) in flash programming mode, the internal code flash memory is erased and re-programmed. after reset release, the firmware initiates loading of the user's program code from the external flash programmer and programs the code flash memory. after detaching the external flash programmer, the microcontroller can be started up with the new user's program in normal operation mode. for more information see section ?flash memory? on page 259 . 3.3.3 on-chip debug mode by connecting an n-wire emulator, on-chip debugging can be executed. the n-wire emulator is connected through jtag type signals. in on-chip debug mode user?s code can be programmed into the flash. table 3-10 selection of operation modes pins operation mode flmd0 flmd1 (pdl5) 0 x normal operation mode (fetch from code flash) 1 0 flash programming mode 1 setting prohibited
147 cpu system functions chapter 3 user?s manual u18743ee1v2um00 afterwards the software can be evaluated using breakpoints and the user resources (such as memory and i/o can be read or written. for more information see chapter 23 on page 723 . 3.4 address space in the following sections, the address space of the cpu is explained. size and addresses of cpu address space and physical address space are explained. the address range of data space and program space together with their wrap- around properties are presented. 3.4.1 cpu address space and physical address space the cpu supports the following address space:  4 gb cpu address space with the 32-bit general purpose registers, addresses for a 4 gb memory can be generated. this is the maximum address space supported by the cpu.  64 mb physical address space the cpu provides 64 mb physical address space. that means that a maximum of 64 mb internal memory can be accessed. any 32-bit address is translated to its corresponding physical address by ignoring bits 31 to 26 of the address. thus, 64 addresses point to the same physical memory address. in other words, data at the physical address 0000 0000 h can additionally be accessed by addresses 0400 0000 h , 0800 0000 h , ?, f800 0000 h , or fc00 0000 h .
148 chapter 3 cpu system functions user?s manual u18743ee1v2um00 the 64 mb physical address space is seen as 64 images in the 4 gb cpu address space: figure 3-3 images in the cpu address space note the start address of the internal ram area depends on the product derivative. see ?internal ram area? on page 151 for details. ffff ffffh fc00 0000h fbff ffffh 0000 0000h image image image internal ram physical address space x3ff f000h x000 0000h image image f800 0000h f7ff ffffh 0800 0000h 07ff ffffh 0400 0000h 03ff ffffh cpu address space internal flash/rom x3ff x000h fixed peripheral i/o programmable peripheral i/o x3fe c000h use prohibited x3ff 0000h address bits a[31:26] = x note x3ff ffffh use prohibited
149 cpu system functions chapter 3 user?s manual u18743ee1v2um00 3.4.2 program and data space the cpu allows the following assignment of data and instructions to the cpu address space:  4 gb as data space the entire cpu address space can be used for operand addresses.  64 mb as program space only the lower 64 mb of the cpu address space can be used for instruction addresses. when an instruction address for a branch instruction is calculated and moved to the program counter (pc), then bits 31 to 26 are set to zero. figure 3-4 shows the assignment of the cpu address space to data and program space. figure 3-4 cpu address space ffff ffffh 0400 0000h 03ff ffffh 0000 0000h data area (4 gb linear) program area (64 mb linear) cpu address space
150 chapter 3 cpu system functions user?s manual u18743ee1v2um00 (1) wrap-around of data space if an operand address calculation exceeds 32 bits, only the lower 32 bits of the result are considered. therefore, the addresses 0000 0000 h and ffff ffff h are contiguous addresses. this results in a wrap-around of the data space: figure 3-5 wrap-around of data space (2) wrap-around of program space if an instruction address calculation exceeds 26 bits, only the lower 26 bits of the result are considered. therefore, the addresses 0000 0000 h and 03ff ffff h are contiguous addresses. this results in a wrap-around of the program space: figure 3-6 wrap-around of program space caution no instruction can be fetched from the 4 kb area of 03ff f000 h to 03ff ffff h because this area is defined as peripheral i/o area. therefore, do not execute any branch to this area. ffff fffeh ffff ffffh 0000 0000h 0000 0001h data space data space (-) direction (+) direction 03ff fffeh 03ff ffffh 0000 0000h 0000 0001h program space program space (-) direction (+) direction
151 cpu system functions chapter 3 user?s manual u18743ee1v2um00 3.5 memory in the following sections, the memory of the cpu is introduced. specific memory areas are described and a recommendation for the usage of the address space is given. 3.5.1 memory areas the internal memory of the cpu provides several areas:  internal code flash area  internal ram area  internal fixed peripheral i/o area  programmable peripheral i/o area the areas are briefly described below. (1) internal code flash area ta b l e 3 - 1 1 shows the size and address range of internal code flash area. (2) internal ram area ta b l e 3 - 1 2 shows the size and address range of internal ram area. table 3-11 internal code flash areas v850es/fx3-l product device code flash size address range v850es/fe3-l pd70f3610 64 kb 0000 0000 h to 0000 ffff h pd70f3611 96 kb 0000 0000 h to 0001 7fff h pd70f3612 128 kb 0000 0000 h to 0001 ffff h pd70f3613 192 kb 0000 0000 h to 0002 ffff h pd70f3614 256 kb 0000 0000 h to 0003 ffff h v850es/ff3-l pd70f3615 64 kb 0000 0000 h to 0000 ffff h pd70f3616 96 kb 0000 0000 h to 0001 7fff h pd70f3617 128 kb 0000 0000 h to 0001 ffff h pd70f3618 192 kb 0000 0000 h to 0002 ffff h pd70f3619 256 kb 0000 0000 h to 0003 ffff h v850es/fg3-l pd70f3620 128 kb 0000 0000 h to 0001 ffff h pd70f3621 192 kb 0000 0000 h to 0002 ffff h pd70f3622 256 kb 0000 0000 h to 0003 ffff h
152 chapter 3 cpu system functions user?s manual u18743ee1v2um00 note that the internal firmware, which is processed after reset, uses some ram (refer to ?reset? on page 705 ). (3) fixed peripheral i/o area the 4 kb area between addresses 03ff f000 h and 03ff ffff h is provided as the internal fixed peripheral i/o area. accesses to these addresses are passed over to the npb bus (internal bus). the following registers are memory-mapped to this area:  all registers of peripheral functions  registers of timers  configuration registers of interrupt and memory controllers  configuration registers of the clock controller for a list of all peripheral i/o registers, see ?special function registers? on page 737 . note 1. because the physical address space covers 64 mb, the address bits a[31:26] are not considered. thus, this 4 kb address space can also be addressed via the area ffff 0000 h to ffff ffff h . this has the advantage that the area can be indirectly addressed by an offset and the zero base r0. therefore, in this manual, all addresses of peripheral i/o registers in the 4 kb peripheral i/o area are given in the range ffff f000 h to ffff ffff h instead of 03ff f000 h to 03ff ffff h . 2. the fixed peripheral i/o area is mirrored to the upper 4 kb of the programmable peripheral i/o area ppa. if data is written to one area, it appears also in the other area. 3. program fetches cannot be executed from any peripheral i/o area. 4. word registers, that means 32-bit registers, are accessed in two half word accesses. the lower two address bits are ignored. table 3-12 internal ram areas v850es/fx3-l product device ram size address range v850es/fe3-l pd70f3610 6 kb 03ff d800 h ?03ffefff h pd70f3611 6 kb 03ff d800 h ?03ffefff h pd70f3612 8 kb 03ff d000 h ?03ffefff h pd70f3613 12 kb 03ff c000 h ?03ffefff h pd70f3614 16 kb 03ff b000 h ?03ffefff h v850es/ff3-l pd70f3615 6 kb 03ff d800 h ?03ffefff h pd70f3616 6 kb 03ff d800 h ?03ffefff h pd70f3617 8 kb 03ff d000 h ?03ffefff h pd70f3618 12 kb 03ff c000 h ?03ffefff h pd70f3619 16 kb 03ff b000 h ?03ffefff h v850es/fg3-l pd70f3620 8 kb 03ff d000 h ?03ffefff h pd70f3621 12 kb 03ff c000 h ?03ffefff h pd70f3622 16 kb 03ff b000 h ?03ffefff h
153 cpu system functions chapter 3 user?s manual u18743ee1v2um00 5. for registers in which byte access is possible, if half word access is executed:  during read operation: the higher 8 bits become undefined.  during write operation: the lower 8 bits of data are written to the register. caution 1. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. (4) programmable peripheral i/o area the 16 kb area between addresses 03fe c000 h and 03fe efff h is provided as a programmable peripheral i/o area (ppa). within the microcontroller, the usage and address range of the ppa are not configurable. the can modules registers and message buffers are allocated to the ppa. refer to ?can module register and message buffer addresses? on page 553 for information on how to calculate the register and message buffer addresses of the can modules. the base address of the ppa is specified by the peripheral area selection control register (bpc).  for the microcontroller , the base address of the ppa is fixed to 03fe c000 h . thus writing to bpc.pa[13:0] does not change the ppa base address. nevertheless the ppa must be enabled by setting bpc.pa15 = 1.  for the emulation tool , the ppa has to be enabled and the base address has to be set up by writing 8ffb h to the bpc register. to make software suitable for both microcontroller and emulation tool, it is recommended to include the set up of the ppa with bpc = 8ffb h in the software.
154 chapter 3 cpu system functions user?s manual u18743ee1v2um00 3.5.2 recommended use of data address space when accessing operand data in the data space, one register has to be used for address generation. this register is called pointer register. with relative addressing, an instruction can access operand data at all addresses that lie in the range of 32 kb relative to the address in the pointer register. by this offset addressing method load/store instructions can be accommodated in a single 32-bit instruction word, resulting in faster program execution and smaller code size. to enhance the efficiency of using the pointer in consideration of the memory map, the following is recommended: for efficient use of the relative addressing feature, the data segments should be located in the address range ffff f800 h to 0000 0000 h and 0000 0000 h to 0000 7fff h . the peripheral i/o registers and the internal ram is aligned to the upper bound, thus the registers and a part of the ram can be addressed via relative addressing, with base address 0 (r0). it is recommended to locate code flash memory data segments in the area up to 0000 7fff h , so access to these constant data can utilize also relative addressing. use the r0 register as pointer register for operand addressing. since the r0 register is fixed to zero by hardware, it can be used as a pointer register and, at the same time, for any other purposes, where a zero register is required. thus, no other general purpose register has to be reserved as pointer register. figure 3-7 example application of wrap-around 0000 7fffh (r0=)0000 0000h internal flash area fixed peripheral i/o area ffff f000h ffff efffh ffff 8000h internal ram area (4 kb) (28 kb) (1 mb) internal ram area (32 kb) ffff 0000h ffff 7fffh -32 kb +32 kb
155 cpu system functions chapter 3 user?s manual u18743ee1v2um00 3.6 write protected registers write protected registers are protected from inadvertent write access due to erroneous program execution, etc. write access to a write protected register is only given immediately after writing to a corresponding write enable register. for a write access to the write protected registers you have to use the following instructions: 1. store instruction (st/sst instruction) 2. bit operation instruction (set1/clr1/not1 instruction) incorrect store operations can be checked by a flag of the system status register (sys). when reading write protected registers, no special sequence is required. the following table gives an overview of the write protected registers and their corresponding write enable registers. example enable clock monitor the following example shows how to write to the write protected register clm. the example enables the clock monitor. do { _pr e rr = 0; di(); prcmd = 0x5a; clm = 0x01; e i(); } while (_pr e rr != 0) note 1. make sure that the compiler generates two consecutive assembler ?store? instructions to prcmd and clm from the associated c statements. 2. special care must be taken when writing to registers psc and prcmd. please refer to ?clock generator? on page 179 for details. 3. any value can be written to the prmcd register. table 3-13 overview of write protected registers write protected register shortcut corresponding write enable register shortcut for details see processor clock control register pcc command register prcmd ?clock generator? on page 179 main system clock mode register mcm clock monitor mode register clm power save control register psc reset source flag register resf ?reset? on page 705 internal ram data status register rams ?low-voltage detector? on page 713 low-voltage detection register lvim on-chip debug mode register ocdm ?on-chip debug unit? on page 723
156 chapter 3 cpu system functions user?s manual u18743ee1v2um00 since any action between writing to a write enable register and writing to a protected register destroys this sequence, the effects of interrupts have to be considered:  interrupts: in order to prevent any maskable interrupt to be acknowledged between the two write instructions in question, shield this sequence by di-ei (disable interrupt?enable interrupt). however, any non-maskable interrupt can still be acknowledged.
157 cpu system functions chapter 3 user?s manual u18743ee1v2um00 3.6.1 write protecti on control registers the following section describes the registers that control access to write protected registers. (1) prcmd - command register the 8-bit prcmd register protects other registers from inadvertent write access, so that the system does not stop in case of a program hang-up. after writing to the prcmd register, you are permitted to write once to one of the protected registers. this must be done immediately after writing to the prcmd register. after the second write action all protected registers are write- locked again. read accesses to any register are permitted between write access to the prcmd and the protected register. any value can be written to the prcmd register. nevertheless, writing ?00 h ? or the value to be stored to the protected register in the next instruction minimizes the use of cpu register and the program size. access this register can only be written in 8-bit units. address ffff f1fc h . initial value the contents of this register is undefined. an invalid write attempt to one of write protected registers sets the error flag sys.prerr. (2) sys - system register the 8-bit sys register indicates the status of a write attempt to a write protected register. access this register can be read/written in 8-bit or 1-bit units. address ffff f802 h . initial value 00 h . this register is cleared by any reset. 76543210 xxxxxxxx wwwwwwww 76543210 0000000prerr rrrrrrrr/w table 3-14 sys register contents bit position bit name function 0 prerr write error status: 0: write access was successful. 1: write access failed. you can clear this register by writing 0 to it. setting this register to 1 by software is not possible.
158 chapter 3 cpu system functions user?s manual u18743ee1v2um00
159 user?s manual u18743ee1v2um00 chapter 4 clock generator the clock generator provides the clock signals needed by the cpu and the on-chip peripherals. 4.1 overview the clock generator can generate the required clock signals from the following sources:  main oscillator?a built-in oscillator that requires an external crystal with a frequency between 4 mhz and 16 mhz  sub oscillator?a built-in oscillator that requires an external crystal (32,768 khz) or an external rc resonator (20 khz)  low-frequency internal oscillator?an internal oscillator without external components and a nominal frequency of 240 khz  high-frequency internal oscillator?an internal oscillator without external components and a nominal frequency of 8 mhz features summary special features of the clock generator are:  choice of oscillators to reduce power consumption in stand-by mode  pll synthesizer for the main oscillator: ? in clock-through mode: 4 mhz to 16 mhz main system clock f xx ? in pll (phase locked loop) mode main system clock f xx : - 8 mhz to 20 mhz with fixed frequency from pll  sub oscillator can be crystal controlled (f xt )  two internal internal oscillators (f rl = 240 khz and f rh = 8 mhz)  internal main system clock generation: ?f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt , f rl , f rh ? subclock mode: f xt or f rl selectable by an option byte in the code flash memory  peripheral clock generation ?f xp1 to f xp1 / 1024 ?f xp 1 =f xx or f xp 1 =f xx /2 selectable by an option byte  clock output function (clkout pin)  programmable clock output function (pcl pin)  individual clock source selection for cpu and groups of peripherals  specific power save modes  vital system registers are write-protected by a special write sequence  direct main oscillator clock feed-through for watch timer, watchdog timer, csib0, and can support  clock monitor for main oscillator
160 chapter 4 clock generator user?s manual u18743ee1v2um00 4.1.1 description the clock generator is built up as illustrated in the following figure. figure 4-1 block diagram of the clock generator the left-hand side of the figure shows how the four oscillators can be connected to the cpu and peripheral modules. software-controlled selectors allow you to specify the signal paths. mainosc the main oscillator (mainosc) oscillates at frequencies f x = 4 mhz to 16 mhz. after reset release, the main oscillator is stopped.starting the oscillation must be set via software. the main oscillator is equipped with a stop control. oscillation of the main clock oscillator is stopped in the stop mode or controlled by the pcc register. subosc the sub oscillator (subosc) oscillates at a frequency f xt of 32.768 khz (crystal connected) or typically 20 khz with an external rc circuit. 240 khz internal oscillator the low speed internal oscillator generates a clock f rl with a frequency of 240 khz typically. the oscillation can be stopped by means of the rcm register. the oscillation cannot be stopped, if this is disabled by option byte 007a h . f pll 1/2 selcntx.iselxx selector idle1,2 mode selcnt0.isel07 f xp1 pcc.ck[2:0] f xx f rl f rh mcm.mcm0 rc xtal prescaler3 pcc.ck3 pll(8) pllctl.pllon idle control prescaler2 wt, tmm0, taa1, taa3 wt, csib0 clkout mainosc pllctl.selpll xt1 subosc prescaler1 idle control idle2 mode idle control cpu system clock peripheral clocks wdt2 pcc.frc pcc.mfrc mainosc stop control stop mode 1/8 tmm0 1/2 ob_7a.stopxtal ob_7a.stoprcz 8 mhz internal oscillator 8 mhz internal oscillator stop control divider selector idle2 mode 240 khz internal oscillator ob_7b.plli[1:0] 1/2 ob_7b.prsi 1/128 pcl divider selector 1/8 idle control uartdn, taan, mlm cann rcm.rstop ob_7b.subclk 1/2 ob_7b.pllo rcm.hrstop pcc.mck pclm.pck[1:0] selcntx.iselxx prsm0, prscm0 registers wdt2, tmm0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 xt2 f xt f x f plli f pllo x1 x2 halt control halt mode cpu core clock clock monitor f pcl f xp2 f xp1 f xp1 /512 f xp2 f rh /8 f xp1 f xc f sc f x /128 f brg f xp1 to f xp1 /1024 f cpu f vbclk f rl /8 f xt f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f sc f rl f sc note: ob_7a.bitname and ob7b.bitname describe control bits of option byte 007a h and 007b h idle1,2 mode
161 clock generator chapter 4 user?s manual u18743ee1v2um00 8 mhz internal oscillator the high speed internal oscillator generates a clock f rh with a frequency of typically 8 mhz. after reset release, the 8 mhz internal oscillator is activated. the high speed internal oscillator is equipped with a stop control. the oscillation can be stopped by means of the rcm register. main system clock fxx the main system clock fxx can be derived from different sources:  clock-through mode: main system clock f xx derived from mainosc f x or internal oscillator f rh .  pll mode, main system clock f xx derived from f pllo (pll output). these modes can be selected by the bit pllctl.selpll. pll the pll circuit generates the base frequency f pll , which can be used as the main system clock f xx . input clock to the pll the mainosc f x . the pll is preceded by a frequency divider. the input of the pll (f plli ) can be set to f x , f x /2, or f x /4. the divider is set through an option byte in the code flash memory. the phase-locked loop circuit (pll) multiplies the mainosc clock f x or a fraction of it by eight. its input clock is called f plli , its output is f pllo . the pll is started or stopped by pllctl.pllon. for details on the pll see also ?controlling the pll? on page 215 . (1) system and cpu clocks the cpu system is clocked by two clocks: f vbclk supplies all remaining parts of the cpu system, like bcu, memc, intc. f cpu is derived from f vbclk supplies the cpu core and is subject to halt mode control. clock source for both clocks can be the output of the pll or any of the oscillators. the following table gives an overview of the available cpu clock sources. table 4-1 clock sources for the cpu clock source frequency description 8 mhz internal oscillator ~8 mhz default clock source after reset release. 240 khz internal oscillator ~240 khz default clock source if mainosc has stopped. subosc 32 khz or 20 khz selectable as clock source. mainosc 4 to 16 mhz cpu system clocks in clock-through mode pll up to 20 mhz for maximum performance
162 chapter 4 clock generator user?s manual u18743ee1v2um00 the clock sources mainosc, pll and 8 mhz internal oscillator can generate the master clock f xx . this clock forms the input to prescaler2. prescaler2 can divide the master clock f xx by 1, 2, 4, 8, 16 or 32. its operation is set in the pcc register. prescaler2, the subosc, or the 240 khz internal oscillator can generate the cpu core clock (f cpu ) and the cpu system clock (f vbclk ). the only difference between f vbclk and f cpu is that the latter can be stopped in halt mode. f vbclk is the clock supplied to the intc, rom, and ram blocks. it is directly available at the clkout pin. (2) peripheral clocks the middle and right-hand side of figure 4-1 on page 160 shows how the clocks for the peripheral modules are generated and distributed. peripheral base clock f xp1 f xx is the clock source for the peripheral base clock f xp1 . prescaler1 general purpose peripheral clocks are provided by fixed prescaler1. this prescaler generates the peripheral clocks (f xp1 to f xp1 /1024) to be supplied to on-chip peripheral functions such as timers, serial interfaces and a/ d converter. (3) special clocks the clock generator provides special clocks for certain peripherals. clock for uartdn, ta an, mlm this clock can be derived from f xp1 or f xp2 . both f xp1 and f xp2 have the same frequency which is either f xx or f xx /2, depending on the setting of bit prsi in the option bytes. note that f xp1 stops in all idle modes while f xp2 stops only in idle2 mode. the timers taa1 and taa3 can also be supplied with the subosc clock f xt . clock for tmm0 clock source for timer tmm can be any of the oscillators. the selection between f xp1 or f rh is made by bit selcnt0.isel07. clock for cann the can interfaces can be clocked by f xp1 or by f xc , as chosen by a bit in the selcntx register. select f xc when directly supplying the clock generated by a clock oscillator to the can controller. clock for wt after reset, the watch timer is clocked by the subosc (f xt ). this can be changed when the main oscillator has stabilized. wt can then be clocked by the output of prescaler3 that supplies also the csib0 block. prescaler3 serves as a baud rate generator. it is controlled by the registers prsm0 and prscm0. for details see also ?operation of prescaler3? on page 216 . pcl the clock generator has a programmable clock (pcl) output.this output can deliver a fraction of f plss (f plss divided by 4, 8, 16, or 32), which is derived from f pllo . it is controlled by register pclm and must be enabled by setting pclm.pcle. clkout this output provides the cpu system clock f vbclk . during the oscillation stability period, its state becomes hi-z.
163 clock generator chapter 4 user?s manual u18743ee1v2um00 clock for wdt2 this is the clock for the watchdog timer. the clock for wdt2 is available (and hence the watchdog timer running) as long as the chosen clock source (240 khz internal oscillator or mainosc) is active. note that the wdt2 operation is defined in option byte 007a h . (4) stand-by control in the block diagram, you find also boxes labelled ?idle control? or ?halt control?. these boxes symbolize the switches that are used to disable circuits when the microcontroller enters one of the various power save modes. for an introduction, see ?power save modes overview? on page 164 . (5) summary of clock signals 4.1.2 clock monitor the clock monitor supervises the operation of the mainosc. in case of malfunction, the clock monitor can generate a system reset. the monitor requires that the built-in 240 khz internal oscillator is active. for details see ?operation of the clock monitor? on page 217 . f x : mainosc clock is input clock to pll f xt : subosc clock f rl : 240 khz internal oscillator clock f rh : 8 mhz internal oscillator clock f plli : pll input clock. can be f x or a fraction of f x f pllo : pll output clock f pll : pll output clock f xx : main system clock f vbclk : cpu system clock f cpu : cpu core clock (same clock as f vbclk , but stops in halt mode) f xp1 : peripheral clock 1 (output of prescaler1, stops in idle1 mode) f xp2 : peripheral clock 2 (same frequency as f xp1 , but continues in idle1 mode) f xc : mainosc clock for cann interfaces (same frequency as f x , stops in idle1 and idle2 mode) f sc : sub clock
164 chapter 4 clock generator user?s manual u18743ee1v2um00 4.1.3 power save modes overview the power consumption of the system can be effectively reduced by using the stand-by modes and selecting the appropriate mode for the application. the available stand-by modes are listed below. the following explanations provide a general overview. for details, please refer to ?power save modes description? on page 196 and the register descriptions. halt mode mode in which only the operating clock of the cpu (f cpu ) is stopped. all other clocks remain active. this mode is entered by executing the halt instruction. all other power save modes are entered by setting registers. this mode allows quick recovery to the normal operating mode, because it is not necessary to wait for oscillators to be stable or the pll to be locked. idle1 mode mode in which all the internal operations of the chip except the oscillators, pll and flash memory are stopped. the pll holds the previous operating status. this mode allows quick return to the normal operating mode in response to a release signal, because it is not necessary to wait for oscillators to settle or the pll to lock. idle2 mode mode in which all the internal operations of the chip except the oscillators are stopped. stop mode in which all the internal operations of the chip except the sub oscillator are stopped. subclock operation mode in which the subclock is used as the cpu system clock f vbclk . subclock source can be the subosc (f xt ) or the 240 khz internal oscillator (f rl ). the selection is made by the subclk bit of the option byte 007b h . sub-idle mode a mode that can be entered during subclock operation. all the internal operations of the chip except the oscillator, pll and flash memory are stopped. the pll holds the previous operating status.
165 clock generator chapter 4 user?s manual u18743ee1v2um00 4.1.4 start conditions after securing the setup time of the 8 mhz internal oscillator, the cpu begins program execution. the oscillation stabilization time for the internal oscillator is ensured by hardware. the table below shows the state during reset and after reset release. table 4-2 oscillation during reset period or after reset release item during the reset period after releasing reset mainosc (f x ) stopped subosc (f xt ) continues oscillation 240 khz internal oscillator (f rl ) stopped starts oscillation 8 mhz internal oscillator (f rh ) stopped starts oscillation pll (f pllo ) stopped cpu system clock ( f vbclk ) stopped starts operation on 8 mhz internal oscillator f rh after internal oscillator stable. peripheral clocks f xp1 (and fractions thereof), f xp2 stopped starts operation on 8 mhz internal oscillator f rh after internal oscillator stable. programmable clock output pcl (f pcl ) disabled (low level) system clock output clkout (f vbclk ) stopped output of 8 mhz internal oscillator f rh after internal oscillator stable. must be enabled by software.
166 chapter 4 clock generator user?s manual u18743ee1v2um00 4.2 clock generator registers the clock generator is controlled and operated by means of the following registers (the list is sorted according to memory allocation): note some registers are write-protected to avoid inadvertent changes. data can be written to these registers only in a special sequence of instructions, so that the register contents is not easily rewritten in case of a program hang-up. writing to a protected register is only possible immediately after writing to the associated write protection register. for details please refer to ?cpu system functions? on page 135 . note in addition to the registers, control bits must be set in the code flash memory option bytes. for details see ?option bytes? on page 188 . table 4-3 clock generator register overview register name shortcut address write- protected by register power save control register psc ffff f1fe h prcmd selector control register 0 selcnt0 ffff f308 h selector control register 2 selcnt2 ffff f30c h selector control register 3 selcnt3 ffff f30e h oscillation stabilization time select register osts ffff f6c0 h pll lockup time specification register plls ffff f6c1 h oscillation stabilization timer status register ostc ffff f6c2 h internal oscillator oscillator mode register rcm ffff f80c h power save mode control register psmr ffff f820 h pll lock status register lockr ffff f824 h processor clock control register pcc ffff f828 h prcmd pll control register pllctl ffff f82c h cpu operation clock status register ccls ffff f82e h programmable clock mode register pclm ffff f82f h main system clock mode register mcm ffff f860 h prcmd clock monitor mode register clm ffff f870 h prcmd prescaler3 mode register prsm0 ffff f8b0 h prescaler3 compare register prscm0 ffff f8b1 h
167 clock generator chapter 4 user?s manual u18743ee1v2um00 the subsequent register descriptions are grouped as follows:  general clock generator registers: ? ?ccls - cpu operation clock status register? on page 168 ? ?mcm - main system clock mode register? on page 169 ? ?ostc - oscillation stabilization timer status register? on page 170 ? ?osts - oscillation stabilization time select register? on page 171 ? ?pcc - processor clock control register? on page 173 ? ?pclm - programmable clock mode register? on page 176  pll control registers: ? ?lockr - pll lock status register? on page 178 ? ?pllctl - pll control register? on page 179 ? ?plls - pll lockup time specification register? on page 180  stand-by control registers ? ?psc - power save control register? on page 181 ? ?psmr - power save mode control register? on page 182  prescaler3 control registers: ? ?prsm0 - prescaler3 mode register? on page 183 ? ?prscm0 - prescaler3 compare register? on page 183  clock monitor registers: ? ?clm - main oscillator clock monitor mode register? on page 184  selector control registers: ? ?selcnt0 - selector control register 0? on page 185 ? ?selcnt2 - selector control register 2? on page 186 ? ?selcnt3 - selector control register 3? on page 187
168 chapter 4 clock generator user?s manual u18743ee1v2um00 4.2.1 general clock generator registers the general clock generator registers control and reflect the operation of the clock generator. (1) ccls - cpu operation clock status register the ccls register indicates the cpu operation clock status. access this register can be read in 1-bit or 8-bit units. address ffff f82e h . initial value 00 h . the register is initialized by any reset. note if the watchdog timer wdt2 overflows before the oscillation stabilization time of the mainosc has elapsed, this is judged as an abnormal oscillation of the mainosc f x . thus the cpu system clock f vbclk is changed to internal oscillator f rl . 76543 2 1 0 00000 0 0cclsf rrrrr r r r table 4-4 ccls register contents bit position bit name function 0 cclsf cpu operating clock status: 0: operates on main system clock f xx or subclock f sc a . 1: operates on 240 khz internal oscillator f rl . a) subclock f sc is either f xt or f rl , depending on subclk bit of option byte 007b h .
169 clock generator chapter 4 user?s manual u18743ee1v2um00 (2) mcm - main system clock mode register the 8-bit mcm register specifies the main system clock (f xx ) source in clock- through mode and informs about its status. access this register can be read/written in 1-bit or 8-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?cpu system functions? on page 135 for details. address ffff f860 h . initial value 00 h . the register is initialized by any reset. 76543 2 1 0 00000 0mcsmcm0 rrrrr r r r/w table 4-5 mcm register contents bit position bit name function 1 mcs status of the main system clock f xx (in clock-through mode, if pllctl.selpll = 0): 0: operating on 8 mhz internal oscillator clock f rh . 1: operating on mainosc clock f x . 0 mcm0 clock selection of main system clock f xx : 0: clock source is the 8 mhz internal oscillator f rh (in clock-through mode). 1: clock source is ? mainosc f x (in clock-through mode, if pllctl.selpll = 0) ? pll output f pll (in pll mode, if pllctl.selpll = 1) caution: 1. when the oscillation of a previous clock switch is not steady, rewriting of this bit is prohibited. 2. the mcm0 can be set to 0 only, if the current mode is clock-through, i.e. pllctl.selpll = 0. do not change from pll mode or subclock operation mode directly to 8 mhz internal oscillator clock-through mode or vice versa.
170 chapter 4 clock generator user?s manual u18743ee1v2um00 (3) ostc - oscillation stabilization timer status register the 8-bit ostc register indicates the status of the main oscillator. access this register is read-only. address ffff f6c2 h . initial value 00 h . the register is initialized by any reset. remarks 1. the ostc register does not monitor the main clock status but indicates the process status, based on the oscillation stabilization time specified by the osts register. 2. when the main clock oscillator is stopped by the software (pcc.mck bit = 1) or entered into stop mode, the ostc register is set to 00h. if it is stopped due to abnormal oscillation, the status is maintained. 76543 2 1 0 00000 0 0msts rrrrr r r r table 4-6 ostc register contents bit position bit name function 0 msts oscillation stabilization status of mainosc: 0: mainosc stopped or waiting for oscillation stabilization. 1: mainosc oscillation stabilization ended.
171 clock generator chapter 4 user?s manual u18743ee1v2um00 (4) osts - oscillation stabilization time select register the 8-bit osts register specifies the oscillation stabilization time following reset release or release of the stop mode. the oscillation stabilization time and setup time are required when the stop mode and idle mode are released, respectively. access this register can be read/written in 1-bit or 8-bit units. address ffff f6c0 h . initial value 06 h . the register is initialized by any reset. 76543 2 1 0 0 0 0 osts4 osts3 osts2 osts1 osts0 r r r r/w r/w r/w r/w r/w table 4-7 osts register contents bit position bit name function 4 to 0 osts[4:0] time selection: osts4 a osts3 osts2 osts1 osts0 selection of oscillation stabilization / setup time b 00000 2 10 /fx 00001 2 11 /fx 00010 2 12 /fx 00011 2 13 /fx 00100 2 14 /fx 00101 2 15 /fx 00110 2 16 /fx 00111 2 17 /fx 01000 2 18 /fx 01001 2 19 /fx 01010 2 20 /fx 01011 2 21 /fx 1 0 0 0 0 setting prohibited 1 0 0 0 1 setting prohibited 10010 2 4 /fx 10011 2 5 /fx 10100 2 6 /fx 10101 2 7 /fx 10110 2 8 /fx 10111 2 9 /fx 11000 2 10 /fx 11001 2 11 /fx 11010 2 12 /fx 11011 2 13 /fx a) bit osts4 is only valid during idle2 mode release. in case of shifting to the stop mode at osts4 bit = 1, the oscillation stabilization time after stop mode release is the set period of the osts3-0 bits (osts4 bit is considered as 0).
172 chapter 4 clock generator user?s manual u18743ee1v2um00 note 1. when idle2 mode is released, set the stabilization time to the following requirements: ? in case of pll mode: pll lockup time requirements ? in case of clock-through mode: flash set up time requirement for the exact timing values, refer to the electrical target specification. 2. when stop mode is released, set the stabilization time to the following requirements: ? in case of pll mode: pll lockup time requirement ? in case of clock-through mode:flash set up time requirement for the exact timing values, refer to the electrical target specification. 3. if the required oscillation stabilization time of the mainosc exceeds the above times, set the value to the required oscillation stabilization time of the mainosc. b) for minimum oscillation stabilization / setup times refer to the electrical target specification.
173 clock generator chapter 4 user?s manual u18743ee1v2um00 (5) pcc - processor clock control register the 8-bit pcc register controls the cpu system clock f vbclk . access this register can be read/written in 1-bit and 8-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?cpu system functions? on page 135 for details. address ffff f828 h . initial value 40 h . the register is initialized by any reset. 76543 2 1 0 frc mck mfrc cls ck3 ck2 ck1 ck0 r/w r/w r/w r r/w r/w r/w r/w table 4-8 pcc register contents (1/2) bit position bit name function 7 frc use of built-in sub oscillator feedback resistor: 0: feedback resistor connected. 1: feedback resistor not connected. 6 mck operation of mainosc: 0: oscillation enabled. 1: oscillation stopped. note: 1. when the mck bit is set to 1 while the system is operating with the main system clock as the cpu clock, the operation of the main system clock does not stop. it stops after the cpu clock has been changed to the subclock. 2. when the main system clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has elapsed before switching back to the main system clock. 5 mfrc use of main oscillator on-chip feedback resistor: 0: feedback resistor connected. 1: feedback resistor not connected. 4 cls status of cpu system clock f vbclk : 0: main system clock f xx operation. 1: subclock f sc operation.
174 chapter 4 clock generator user?s manual u18743ee1v2um00 examples: main to subclock 1. confirmation of operating clock: confirm that the current clock is in main clock (mcs = 1). switching from the high speed internal oscillator clock operation to low-speed internal oscillator clock operation is prohibited. in the high-speed internal oscillation clock operation (mcs = 0), set the mcm.mcm0 bit = 1 and then confirm that the mcm.mcm0 bit = 1 again. 2. confirmation of cpu clock (fcpu) frequency: confirm that fcpu satisfies either of the following conditions.  when ob7b.sublck = 0, fcpu > subclock oscillation frequency (fxt) (32.768 khz) 4  when ob7b.subclk = 1, fcpu > low-speed internal oscillation clock frequency (frl) (typ.240 khz) 4 if the above conditions are not satisfied, change the ck2 to ck0 bits set- ting so as to satisfy the condition. at this time, do not change the ck3 bit. 3. setting the ck3 bit to ?1?: set via bit manipulation instruction. do not change the ck2-ck0 bits. 4. subclock operation: the maximum time required for switching to subclock operation or to low-speed internal oscillation clock operation after the ck3 bit is set to 1, is as follows:  when ob7b.subclk = 0: 1 / subclock oscillation frequency (fxt)  when ob7b.subclk = 1: 1 / low-speed internal oscillation frequency (frl) read the cls bit and confirm that the operation has been switched to the subclock or low-speed internal oscillation operation. 5. setting the mck bit to "1": set the mck bit = 1 to stop the main oscillator operation. caution: stop pll/sscg before stopping the main oscillator operation. in addition, stop the operation of internal peripheral functions which operate at the main clock frequency. 3 to 0 ck[3:0] clock selection: ck3 ck2 ck1 ck0 clock selection 0000 f xx 0001 f xx /2 0010 f xx /4 0011 f xx /8 0100 f xx /16 0101 f xx /32 0 1 1 x setting prohibited 1xxx subclock f sc (f xt or f rl ) a note: 1. do not change the cpu clock (by using the ck[3:0] bits) while clkout is being output. 2. use a bit manipulation instruction to manipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck[2:0] bits. a) preset in option byte 007b h . table 4-8 pcc register contents (2/2) bit position bit name function
175 clock generator chapter 4 user?s manual u18743ee1v2um00 subclock to main 1. setting the mck bit to "0": enables main clock oscillation. 2. software wait: insert wait status via program to wait until the oscillation stabilization time of the main clock oscillator (ostc.msts = 1) is elapsed. 3. setting the ck3 bit to "0": set via a bit manipulation instruction. do not change the ck2 to ck0 bits. main clock operation: the maximum time required for switching to the main clock operation which is specified by the ck2 to ck0 bits after the ck3 bit is set, is as follows.  when ob7b.subclk = 0: 1 / subclock oscillation frequency (fxt)  when ob7b.subclk = 1: 1 / low-speed internal oscillation frequency (frl) read the cls bit and confirm that the operation has been switched to the main clock operation. caution do not change to a different clock selection until the previous one has entered a stable status.
176 chapter 4 clock generator user?s manual u18743ee1v2um00 (6) pclm - programmable clock mode register the 8-bit pclm register specifies the setting the programmable clock output pcl. access this register can be read/written in 1-bit or 8-bit units. address ffff f82f h . initial value 00 h . the register is initialized by any reset. note a pcl clock is only output when the pll is in locked status. 76543 2 1 0 0 0 0 pcle 0 0 pck1 pck0 r r r r/w r r r/w r/w table 4-9 pclm register contents bit position bit name function 4 pcle pcl enable: 0: pcl disabled (pcl pin is fixed to low level). 1: pcl enabled. 1 to 0 pck[1:0] pcl clock frequency selection: pck1 pck0 pcl output clock 00 f pcl = f pllo /4 01 f pcl = f pllo /8 10 f pcl = f pllo /16 11 f pcl = f pllo /32
177 clock generator chapter 4 user?s manual u18743ee1v2um00 (7) rcm - internal oscillator mode register the 8-bit rcm register specifies the operation and informs about the status of the low-speed and high-speed internal oscillators. access this register can be read/written in 1-bit or 8-bit units. address ffff f80c h . initial value 80 h . the register is initialized by any reset. 76543 2 1 0 rsts 0 0 0 0 0 hrstop rstop rrrrr r r/wr/w table 4-10 rcm register contents bit position bit name function 7 rsts oscillation stability status of 8 mhz internal oscillator: 0: 8 mhz internal oscillator stopped or waiting for oscillation stability. 1: 8 mhz internal oscillator operating. 1 hrstop operation/stop of 8 mhz internal oscillator: 0: 8 mhz internal oscillator operating. 1: 8 mhz internal oscillator stopped. caution: when the cpu clock source is the 8 mhz internal oscillator, do not set this bit to 1. 0 rstop operation/stop of 240 khz internal oscillator: 0: 240 khz internal oscillator operating. 1: 240 khz internal oscillator stopped. note: setting this bit is ignored if bit rmopin of option byte 007a h is set. caution: when the cpu clock source is the 240 khz internal oscillator, do not set this bit to 1.
178 chapter 4 clock generator user?s manual u18743ee1v2um00 4.2.2 pll control registers the clock generator?s pll registers control and reflect the operation of the pll. (1) lockr - pll lock status register phase lock occurs at a given frequency following power application or immediately after the stop mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). this time until stabilization is called the lockup status, and the stabilized state is called the locked status. the lock register lockr includes a lock bit that reflects the pll frequency stabilization status. access this register is read-only, in 8-bit or 1-bit units. address ffff f824 h . initial value 01 h . the register is initialized by any reset. the lock register does not reflect the lock status of the pll in real time. the set/reset conditions are as follows: set conditions  upon system reset. this register is set to 01 h by reset and cleared to 00 h after the reset has been released and the oscillation stabilization time has elapsed.  in stop and idle2 mode.  upon setting the pll to stop (clearing bit pllctl.pllon).  upon stopping the main system clock and using the cpu with subclock (setting bits pcc.ck3 and pcc.mck to 1). clear conditions  after reset release and overflow of oscillation stabilization time counter (osts register default time).  when bit pllctl.pllon is changed from 0 to 1 after pll lockup timer overflow (time set by plls register).  after stop mode release and oscillation stabilization time counter overflow (time set by osts register), when the stop mode was set while the pll was in pll mode.  after idle2 mode release and oscillation stabilization timer overflow (time set by osts register), when the idle2 mode was set while the pll was in pll mode. note the pll can enter the locked status only, if the mainosc is enabled, i.e. pcc.mclk = 0. 76543 2 1 0 00000 0 0lock rrrrr r r r table 4-11 lockr register contents bit position bit name function 0 lock pll lock status check: 0: locked status. 1: unlocked status
179 clock generator chapter 4 user?s manual u18743ee1v2um00 (2) pllctl - pll control register the 8-bit pllctl register controls the pll function. access this register can be read or written in 8-bit or 1-bit units. address ffff f82c h . initial value 00 h . the register is initialized by any reset. note 1. the selpll bit can be set to 1 only ?if the pll clock frequency has stabilized ?and current mode is clock-through with mainosc f x as main system clock f xx , i.e. mcm.mcm0 = 1 if the pll is unlocked or mcm.mcm0 = 0 (clock-through mode with internal oscillator f rh ), selpll can not be changed to 1. thus you can not change from 8 mhz internal oscillator clock-through mode directly to pll mode. 2. when the pllon bit is cleared to 0, the selpll bit is automatically cleared to 0 (clock-through mode). 3. when the pllon bit = 1 and the main clock is stopped, pll stops the operation. 76543 2 1 0 0 0 0 0 0 0 selpll pllon rrrrr r r/wr/w table 4-12 pllctl register contents bit position bit name function 1 selpll main system clock f xx mode selection: 0: clock-through mode (f xx is mainosc f x or 8 mhz internal oscillator f rh clock, depending on mcm.mcm0). 1: pll mode (f xx is pll output f pll , if mcm.mcm0 = 1 as well). 0 pllon control of pll operation/stop: 0: pll stopped. 1: pll started. (after pll operation starts, a lockup time is required for frequency stabilization).
180 chapter 4 clock generator user?s manual u18743ee1v2um00 (3) plls - pll lockup time specification register the 8-bit plls register specifies the settling time of the pll. access this register can be read/written in 8-bit units. address ffff f6c1 h . initial value 03 h . the register is initialized by any reset. note for the exact lockup time, refer to the electrical target specification. caution do not change the setting of the ppls register during the pll lock-up time. 76543 2 1 0 0 0 0 0 0 plls2 plls1 plls0 rrrrrr/wr/wr/w table 4-13 plls register contents bit position bit name function 2 to 0 plls[2:0] pll lockup time selection: plls2 plls1 plls0 lockup time 010 2 12 /f x 011 2 13 /f x (default value) 100 2 14 /f x
181 clock generator chapter 4 user?s manual u18743ee1v2um00 4.2.3 stand-by control registers these registers control and reflect the various stand-by modes that can be entered for saving power. (1) psc - power save control register the 8-bit psc register controls the stand-by function. the stp bit of this register specifies the stand-by mode. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?write protected registers? on page 155 for details. address ffff f1fe h . initial value 00 h . the register is initialized by any reset. when writing to this register, follow the instructions given in ?cpu system functions? on page 135 . entering a power save mode requires some attention, refer to ?power save mode activation? on page 213 . caution entering a power save mode requires special attention, refer to ?power save mode activation? on page 213 . 76543 2 1 0 0nmi1mnmi0mintm 0 0 stp 0 r r/w r/w r/w r r r/w r table 4-14 psc register contents bit position bit name function 6 nmi1m stand-by mode release control by occurrence of intwdt2 signal: 0: enable releasing stand-by mode by intwdt2 signal. 1: disable releasing stand-by mode by intwdt2 signal. 5 nmi0m stand-by mode release control by nmi pin input: 0: enable releasing stand-by mode by nmi pin input. 1: disable releasing stand-by mode by nmi pin input. 4 intm stand-by mode release control by maskable interrupt request signal: 0: enable releasing stand-by mode by maskable interrupt request signal. 1: disable releasing stand-by mode by maskable interrupt request signal. 1 stp setting of stand-by mode: 0: normal mode. 1: stand-by mode. note: 1. stand-by modes that can be set by the stp bit: idle1 mode, idle2 mode, stop mode, and sub-idle mode. 2. before setting this bit, set the bits psmr.psm[1:0].
182 chapter 4 clock generator user?s manual u18743ee1v2um00 (2) psmr - power save mode control register the 8-bit psmr register is used to specify one of the power save modes. the setting becomes effective when the mode is entered by setting psc.stp to 1. access this register can be read/written in 1-bit or 8-bit units. address ffff f820 h . initial value 00 h . the register is initialized by any reset. for information on these modes, refer to ?power save modes description? on page 196 . 76543 2 1 0 0 0 0 0 0 0 psm1 psm0 rrrrr r r/wr/w table 4-15 psmr register contents bit position bit name function 1 to 0 psm[1:0] specification of operation in software stand-by mode: psm1 psm0 power save mode 0 0 idle1 mode 0 1 stop mode 1 0 idle2 mode or sub-idle mode a a) sub-idle mode is entered if the processor is in subclock mode (clocked by f xt or f rl ). 1 1 stop mode note: the psm0 and psm1 bits take effect after psc.stp = 1.
183 clock generator chapter 4 user?s manual u18743ee1v2um00 4.2.4 prescaler3 control registers these registers control the prescaler3 that generates f brg which can be applied to the watch timer and the clocked serial interface csib0. prescaler3 includes a clock divider, a counter, and a comparator. for details see ?operation of prescaler3? on page 216 . (1) prsm0 - prescaler3 mode register the prsm0 register controls the prescaler3 operation. access this register can be read/written in 8-bit units. address ffff f8b0 h . initial value 00 h . this register is cleared by any reset. note 1. do not change the values of bgcs0[1:0] during watch timer operation. 2. set the bgcs0[1:0] bits before setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers according to the main clock frequency that is used to obtain an f brg frequency of 32,768 khz. (2) prscm0 - prescaler3 compare register the prscm0 register specifies the compare value and hence the output frequency of f brg . access this register can be read/written in 8-bit units. address ffff f8b1 h . initial value 00 h . this register is cleared by any reset. 76543 2 1 0 0 0 0 bgce0 0 0 bgcs01 bgcs00 r r r r/w r r r/w r/w table 4-16 prsm0 register contents bit position bit name function 4 bgce0 prescaler3 output: 0: disabled. 1: enabled. 1 to 0 bgcs0[1:0] selection of counter clock: bgcs01 bgcs00 prescaler clock selection 00 f x 01 f x /2 10 f x /4 11 f x /8 76543 2 1 0 prscm7 prscm6 prscm5 prscm4 prscm3 prscm2 prscm1 prscm0 r/w r/w r/w r/w r/w r/w r/w r/w
184 chapter 4 clock generator user?s manual u18743ee1v2um00 note 1. do not rewrite the prscm0 register during watch timer operation. 2. set the prsm0 and prscm0 registers according to the main clock frequency that is used to obtain an f brg frequency of 32,768 khz. for details and a calculation example, please refer to ?operation of prescaler3? on page 216 . 4.2.5 clock monitor control registers these registers control and reflect the operation of the clock monitor. (1) clm - main oscillator clock monitor mode register the 8-bit clm register is used to enable the monitor for the main oscillator clock. access this register can be read/written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?cpu system functions? on page 135 for details. address ffff f870 h . initial value 00 h . this register is cleared by any reset. note 1. clm.clme can be set at any time. however, the clock monitor is only activated after the main oscillator has stabilized, indicated by ostc.msts = 1. 2. when reset is generated by the clock monitor, clm.clme is cleared to 0 and resf.clmrf is set to 1. 76543 2 1 0 00000 0 0clme rrrrr r r r/w table 4-17 clm register contents bit position bit name function 0 clme clock monitor enable: 0: clock monitor for main oscillator disabled. 1: clock monitor for main oscillator enabled. this bit can only be cleared by reset.
185 clock generator chapter 4 user?s manual u18743ee1v2um00 4.2.6 selector control registers these registers are used to select the clocks and functions of timers taan, tmm0 and serial interfaces uartdn, cann. note in this section, only the bits that refer to clock generation and distribution are described. for further information please refer to the descriptions of the on- chip peripherals. (1) selcnt0 - selector control register 0 the 8-bit selcnt0 register is used to specify the clock for timer tmm0. access this register can be read/written in 8-bit or 1-bit units. address ffff f308 h . initial value 00 h . the register is initialized by any reset.  v850es/fe3-l  v850es/ff3-l  v850es/fg3-l note ?r? bits marked with ?0? must not be changed from their default value ?0?. 76543210 isel07 0 0 isel04 isel03 isel02 0 isel00 r/w r r r/w r/w r/w r r/w 76543210 isel07 0 isel05 isel04 isel03 isel02 0 isel00 r/w r r/w r/w r/w r/w r r/w table 4-18 selcnt0 register contents bit position bit name function 7 isel07 selection of count clock for tmm0: 0: clock = f xp1 /512. 1: clock = f rh /8 . 6 to 0 isel0[6:0] refers to taan.
186 chapter 4 clock generator user?s manual u18743ee1v2um00 (2) selcnt2 - selector control register 2 the 8-bit selcnt2 register is used to specify the clock for uartd0, uartd1, can0 and taan. access this register can be read/written in 8-bit or 1-bit units. address ffff f30c h . initial value 00 h . the register is initialized by any reset. 76543210 isel27 isel26 isel25 isel24 isel23 isel22 isel21 isel20 r/w r/w r/w r/w r/w r/w r/w r/w table 4-19 selcnt2 register contents bit position bit name function 7 isel27 selection of uartd1 clock: 0: clock = f xp1 . the clock that stops in the idle1 mode. 1: clock = f xp2 . the clock that does not stop in the idle1 mode. 6 isel26 selection of uartd0 clock: 0: clock = f xp1 . 1: clock = f xp2 . 5 isel25 selection of can0 clock: 0: clock = f xp1 . 1: clock = f xc . 4 isel24 selection of taa4 counter clock: 0: clock = f xp1 . 1: clock = f xp2 . 3 isel23 selection of taa3 counter clock: 0: clock = f xp1 . 1: clock = f xp2 . 2 isel22 selection of taa2 counter clock: 0: clock = f xp1 . 1: clock = f xp2 . 1 isel21 selection of taa1 counter clock: 0: clock = f xp1 . 1: clock = f xp2 . 0 isel20 selection of taa0 counter clock: 0: clock = f xp1 . 1: clock = f xp2 .
187 clock generator chapter 4 user?s manual u18743ee1v2um00 (3) selcnt3 - selector control register 3 the 8-bit selcnt3 register is used to specify the clocks for uartd2. access this register can be read/written in 8-bit or 1-bit units. address ffff f30e h . initial value 00 h . the register is initialized by any reset.  v850es/fg3-l note ?r? bits marked with ?0? must not be changed from their default value ?0?. 76543210 0 0 0 0 0 isel32 0 0 rrr r rr/wr r table 4-20 selcnt3 register contents bit position bit name function 2 isel32 selection of uartd2 clock: 0: clock = f xp1 . 1: clock = f xp2 .
188 chapter 4 clock generator user?s manual u18743ee1v2um00 4.3 option bytes the code flash memory versions in this product series have an option data area where a block subject to mask options is specified. when writing a program to a code flash memory version, be sure to set the option data area corresponding to the following option bytes. the option bytes are used for:  enable or disable stopping the 240 khz internal oscillator by software  specifying the wdt2 operation mode  selection of subosc external connection (crystal or rc resonator)  selection of clock source in subclock operation mode (subosc or 240 khz internal oscillator)  selection of pll input clock  selection of pll output clock  selection of peripheral clock the option bytes are stored as 16-bit data at addresses 0000 007a h and 0000 007b h of the internal code flash memory. note in the following only the clock generator related option bytes settings are described. for a complete overview refer to ?flash mask options? on page 285 .
189 clock generator chapter 4 user?s manual u18743ee1v2um00 4.3.1 option byte 0000 007a h address 0000 007a h . note bits marked with ?0? must not be changed from their value ?0?. 76543210 stopxtal stoprcz 0 0 0 0 wdtmd1 rmopin table 4-21 setting of option byte 0000 007a h bit position bit name function 7 to 6 stopxtal, stoprcz selection of subosc mode: stopxtal stoprcz sub oscillator setting 0 0 crystal oscillator mode (32,768 khz) 1 1 rc oscillator mode (20 khz) other than above setting prohibited 1 wdtmd1 specifies wdt2 operation mode: 0: count operation : can be stopped by wdm2.wdcs24. input clock : selectable by wdtm2 register. 240 khz internal oscillator or mainosc. operation mode : selectable by wdtm2 register. nmi interrupt (intwdt2) or reset mode (wdt2res) selectable. 1: count operation : cannot be stopped. input clock : fixed to 240 khz internal oscillator. operation mode : fixed to reset mode (wdt2res) . 0 rmopin option that the 240 khz internal oscillator can be stopped by software: 0: can be stopped by software. 1: cannot be stopped.
190 chapter 4 clock generator user?s manual u18743ee1v2um00 4.3.2 option byte 0000 007b h address 0000 007b h . note bits marked with ?0? must not be changed from their value ?0?. 76543 2 1 0 subclk 0 0 latency pllo prsi plli1 plli0 table 4-22 setting of option byte 0000 007b h bit position bit name function 7 subclk clock source in subclock operating mode: 0: subosc selection. 1: 240 khz internal oscillator selection. 4 latency refer to ?flash mask options? on page 285 3 pllo pll output clock f pll and f xmpll selection: pllo f xmpll f pll 0 (setting prohibited) f pllo f pllo 1f pllo /2 f pllo /2 2 prsi divider setting for peripheral clocks f xp1 and f xp2 : 0: f xp1 , f xp2 = f xx 1: f xp1 , f xp2 = f xx /2 1 to 0 plli[1:0] pll input clock frequency selection: plli1 plli0 pll input clock 00 f plli = f x 01 f plli = f x /2 1x f plli = f x /4
191 clock generator chapter 4 user?s manual u18743ee1v2um00 4.4 clock generator operation this chapter describes the specific features of the clock generator. for details see:  ?overview of clock operation control settings? on page 191  ?operation state transitions? on page 192  ?power save modes description? on page 196  ?available clocks in power save modes? on page 211  ?controlling the pll? on page 215  ?watch dog timer clock? on page 215  ?clkout function? on page 215  ?operation of prescaler3? on page 216  ?operation of the clock monitor? on page 217 4.4.1 overview of clock ope ration control settings the following table gives an overview of the settings that specify the cpu system clock f vbclk . it identifies the register bits that must be set or cleared to generate specific f vbclk . table 4-23 cpu system clock settings ccls.cclsf pcc.cls pllctl.selpll mcm.mcm0 option byte 007b: subclk bit operation clock 0 0 (main system clock operation mode) 0 (clock-through mode) 0 (8 mhz internal oscillator mode) x a a) x = don?t care 8 mhz internal oscillator clock operation 1 (mainosc mode) mainosc clock operation 1 (pll mode) pll operation 1 (subclock operation mode) x 0 (subosc mode) subosc clock operation 1 (240 khz internal oscillator mode 2) 240 khz internal oscillator clock operation (sub) 1- 240 khz internal oscillator clock operation (security) other than above setting prohibited
192 chapter 4 clock generator user?s manual u18743ee1v2um00 4.4.2 operation state transitions the following figure illustrates the various state transitions. figure 4-2 operation state transition diagram note 1. when the pll operation mode is entered, secure the lockup time by using software and check the pll lock status by using the lockr.lock bit. 2. when changing the operation mode to the main clock oscillator mode, secure the oscillation stabilization time by using software and check the oscillation stabilization status by using the ostc.osts bit. enable the pll operation before the main clock oscillator is enabled or after the oscillation is stabilized. reset oscillation stabilization wait x1 main clock-through (pll = on) pll operation (pll = on) sub operation (x1 = on) (pll = on) note 1 each stby (halt/idle1/idle2/ software stop) stby (sub idle only) (x1 = on) (pll = on) stby (sub idle only) (x1 = off) (pll = off) sub operation (x1 = off) (pll = off) note 2 sub operation (x1 = on) (pll = off) stby (sub idle only) (x1 = on) (pll = off) each stby (halt/idle1/idle2/ software stop) x1 main through (pll = off) each stby (halt/idle1/idle2/ software stop) 8 mhz internal oscillator operation each stby (halt/idle1/idle2/ software stop)
193 clock generator chapter 4 user?s manual u18743ee1v2um00 (1) status transition from pll operation figure 4-3 stand-by transition from pll operation (pll = on) note 1. after the time set by the osts register has elapsed, the cpu returns to the pll mode. 2. after the time set by the osts register has elapsed, the cpu returns to the pll mode. if the watchdog timer overflows (reset) while the oscillation stabilization time is being counted, the cpu starts clock operation with the internal oscillator. (2) status transition from main clock-through operation (with pll on) figure 4-4 stand-by transition from x1 main clock-through operation (pll = on) note 1. after the time set by the osts register has elapsed, the cpu returns to the through mode. 2. after the time set by the osts register has elapsed, the cpu returns to the through mode. if the watchdog timer overflows (reset) while the oscillation stabilization time is counted, the cpu starts its clock operation with the internal oscillator. pll operation (pll = on) idle2 mode idle1 mode software stop mode halt mode x1 = on, pll = on x1 = off, pll = off x1 = on, pll = on x1 = on, pll = off note 2 note 1 x1 main clock-through mode (pll = on) idle2 mode idle1 mode software stop mode halt mode x1 = on, pll = on x1 = off, pll = off x1 = on, pll = on x1 = on, pll = off note 2 note 1
194 chapter 4 clock generator user?s manual u18743ee1v2um00 (3) status transition from main clock-through operation (with pll off) figure 4-5 stand-by transition from x1 main clock-through operation (pll = off) note 1. after the time set by the osts register has elapsed, the cpu returns to the through mode. 2. after the time set by the osts register has elapsed, the cpu returns to the through mode. if the watchdog timer overflows (reset) while the oscillation stabilization time is counted, the cpu starts its clock operation with the internal oscillator. x1 main clock-through mode (pll = off) idle2 mode idle1 mode software stop mode halt mode x1 = on, pll = off x1 = off, pll = off x1 = on, pll = off x1 = on, pll = off note 2 note 1
195 clock generator chapter 4 user?s manual u18743ee1v2um00 (4) status transition to / from subclock operation figure 4-6 status transition diagram (during subclock operation) normal operation mode (main clock operation) sub-idle mode subclock operation mode main clock operation setting subclock operation setting idle mode setting interrupt
196 chapter 4 clock generator user?s manual u18743ee1v2um00 4.4.3 power save modes description this section explains the various power save modes in detail. during power save mode during all power save modes, the pins behave as follows:  all output pins retain their function. that means all outputs are active, provided the required clock source is available.  all input pins remain as input pins.  all input pins with stand-by wake-up capability remain active, the function of all others is disabled. during all power save modes, the main oscillator clock monitor remains active, provided that the oscillator is operating. if the oscillator is switched off during stand-by, the clock monitor enters stand-by as well. wake-up signals the following signals can awake the controller from power save modes:  reset signals ? external reset ? power-on-clear reset respoc ? watchdog timer reset reswdt2 the watchdog timer must be configured to generate the reset in case of overflow and its input clock must be active during stand-by. ? clock monitor reset resclm the main oscillator must be active during stand-by.  non maskable interrupts ?nmi0 the appropriate port must be configured correctly. ?nmiwdt2 the watchdog timer must be configured to generate the interrupt in case of overflow and its input clock must be active during stand-by. table 4-24 stand-by modes mode functional outline halt mode mode in which only the operating clock of the cpu is stopped idle1 mode mode in which all the internal operations of the chip except the oscillator, pll and flash memory are stopped idle2 mode mode in which all the internal operations of the chip except the oscillator are stopped stop mode mode in which all the internal operations of the chip except the subclock oscillator are stopped subclock operation mode mode in which the subclock is used as the cpu system clock sub-idle mode mode in which all the internal operations of the chip except the oscillator, pll and flash memory are stopped, in the subclock operation mode
197 clock generator chapter 4 user?s manual u18743ee1v2um00  maskable interrupts ? any unmasked maskable interrupt note that not all these signals are available in all power save modes. note in the following tables the clock status ?operates? does not necessarily mean that the functions that use this clock source are operating as well. (1) halt mode in this mode, the clock oscillators continue operating, but clock supply to the cpu is stopped. clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the contents of the internal ram before the halt mode was set are retained. the on-chip peripheral functions that are not dependent upon the instruction processing of the cpu continue operating. the halt mode can reduce the average current consumption of the system if it is used with the normal operation mode for intermittent operation. entering halt mode when the halt instruction is executed in the normal operation mode, the halt mode is set. insert five or more nop instructions after the halt instruction. note if the halt instruction is executed while an interrupt request signal is held pending, the halt mode is set but is released immediately by the pending interrupt request. halt mode status the following table shows the operation status in the halt mode. table 4-25 controller status in halt mode (1/2) working condition without subclock with subclock mainosc (f x ) oscillation enabled subosc (f xt ) - oscillation enabled 240 khz internal oscillator (f rl ) oscillation enabled 8 mhz internal oscillator (f rh ) oscillation enabled pll (f pllo ) operable cpu stops operation port function holds status before halt mode is set timer/counter taa0 -taa4 taa0, 2, and 4: operable taa1 and 3: operable, when other than f xt is selected as the count clock operable tmm0 operable, when other than f xt is selected as the count clock operable watch timer (wt) operable watchdog timer (wdt2) operable ad converter operable serial interface uartd0-2 operable csib0-1 operable iic00 operable
198 chapter 4 clock generator user?s manual u18743ee1v2um00 leaving halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked internal interrupt request of a peripheral function that can operate in the halt mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). when the halt mode has been released, the normal operation mode is restored. (a) release by non-maskable interrupt request or unmasked maskable interrupt request the halt mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the halt mode is set in an interrupt routine, however, the operation is performed as follows:  if an interrupt request signal having a priority lower than that of the interrupt request currently being serviced is generated, the halt mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held.  if an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher than that of the interrupt request currently being serviced is generated, the halt mode is released, and this interrupt request signal is acknowledged. (b) releasing by reset input the operation is the same as the normal reset operation. can controller(can0) operable interrupt controller operable key interrupting function operable clock monitor operable power-on-clear circuit operable low-voltage detector operable voltage regulator operation continues internal data the cpu registers, states, data and all other internal data such as the contents of the internal ram are retained as they were before halt mode was set table 4-25 controller status in halt mode (2/2) working condition without subclock with subclock table 4-26 operation after halt mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed. the next instruction is executed.
199 clock generator chapter 4 user?s manual u18743ee1v2um00 (2) idle1 mode in the idle1 mode, the main oscillator, pll and flash memory continue operating, but clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is stopped, and the contents of the internal ram before the idle1 mode was set are retained. the cpu and other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that can operate on the subclock or external clock continue operating. the idle1 mode can reduce current consumption more than the halt mode because the operations of the on-chip peripheral functions are stopped. because the main oscillator is not stopped, however, the normal mode can be restored without securing the oscillation stabilization time, in the same manner as in the halt mode. entering idle1 mode the idle1 mode is set when the psm1 and psm0 bits of the psmr register are cleared to ?00? and the stp bit of the psc register is set to 1 in the normal operation mode. insert five or more nop instructions after the store instruction that manipulates the psc register to set the idle1 mode. idle1 mode status the following table shows the operation status in the idle1 mode. table 4-27 controller status in idle1 mode (1/2) working condition without subclock with subclock mainosc (f x ) oscillation enabled subosc (f xt ) - oscillation enabled 240 khz internal oscillator (f rl ) oscillation enabled 8 mhz internal oscillator (f rh ) oscillation enabled pll (f pllo ) operable cpu stops operation port function holds status before idle1 mode is set timer/counter taa0 -taa4 operable, if f xp2 is selected as the count clock taa0, 2, and 4: operable, if f xp2 is selected as the count clock. taa1 and 3: operable, if f xp2 or f xt is selected as the count clock a tmm0 operable, if f rh /8 , f rl /8 ir intwt is selected as the count clock operable if f rh /8, f rl /8, intwt or f xt is selected as count clock. watch timer (wt) operable, if clocked by prescaler3 operable watchdog timer (wdt2) operable ad converter b stops operation serial interface uartd0-2 uartd0: operable if either f xp2 or asckd0 is selected input clock uartd1-2: operable if f xp2 is selected as operation clock. csib0-1 operable, if sckbn is selected as input clock. iic00 stops operation can controller (can0) stops operation interrupt controller stops operation (but it is possible to leave idle1 mode) key interrupting function operable clock monitor operable
200 chapter 4 clock generator user?s manual u18743ee1v2um00 leaving idle1 mode the idle1 mode is released by a non-maskable interrupt request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked internal interrupt request signal of a peripheral function that can operate in the idle1 mode, or reset signal. note interrupt request signals that are disabled by the nmi1m, nmi0m, and intm bits of the psc register are invalid and do not release the idle1 mode. when digital noise elimination is enabled for intp3, the power save mode cannot be released using intp3 pin. for details, refer to ?pin functions? on page 31 . when the idle1 mode has been released, the normal operation mode is restored. power-on-clear circuit operable low-voltage detector operable voltage regulator operation continues internal data the cpu registers, states, data and all other internal data such as the contents of the internal ram are retained as they were before idle1 mode was set a) only when setting the iselxx bit =1 (f xp2 ), the count operation by f xt is also possible. b) to achieve low power consumption, stop the a/d converter before shifting to the idle1 mode. table 4-27 controller status in idle1 mode (2/2) working condition without subclock with subclock
201 clock generator chapter 4 user?s manual u18743ee1v2um00 (a) release by non-maskable interrupt request or unmasked maskable interrupt request the idle1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle1 mode is set in an interrupt routine, however, the operation is performed as follows:  if an interrupt request signal having a priority lower than that of the interrupt request currently being serviced is generated, the idle1 mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held.  if an interrupt request signal (including a non-maskable interrupt request signal) has a priority higher than that of the interrupt request currently being serviced is generated, the idle1 mode is released, and this interrupt request signal is acknowledged. (b) releasing by reset input the operation is the same as the normal reset operation. (3) idle2 mode in the idle2 mode, the main clock oscillator continues operating, but clock supply to the cpu, pll, flash memory, and the other on-chip peripheral functions is stopped. as a result, program execution is stopped, and the contents of the internal ram before the idle2 mode was set are retained. not only the cpu but also the other on-chop peripheral functions stop operating. however, the on-chip peripheral functions that can operate on the subclock or external clock continue operating. the idle2 mode can reduce current consumption more than the idle1 mode because the operations of the on-chip peripheral functions and flash memory are stopped. because the pll and flash memory are stopped, however, setup times for the pll and flash memory must be maintained after the idle2 mode is released. entering idle2 mode the idle2 mode is set when the psm1 and psm0 bits of the psmr register are set to ?10? and the stp bit of the psc register is set to 1 in the normal operation mode. note insert five or more nop instructions after the store instruction that manipulates the psc register to set the idle2 mode. table 4-28 operation after idle1 mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed. the next instruction is executed.
202 chapter 4 clock generator user?s manual u18743ee1v2um00 idle2 mode status the following table shows the operation status in the idle2 mode. leaving idle2 mode the idle2 mode is released by a non-maskable interrupt request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked internal interrupt request of a peripheral function that can operate in the idle2 mode, or reset signal. when the idle2 mode has been released, the normal operation mode is restored. note 1. interrupt request signals that are disabled by the nmi1m, nmi0m, and intm bits of the psc register are invalid and do not release the idle2 mode. 2. when digital noise elimination is enabled for intp3, the power save mode cannot be released using intp3 pin. for details, refer to ?pin functions? on page 31 . table 4-29 controller status in idle2 mode working condition without subclock with subclock mainosc (f x ) oscillation enabled subosc (f xt ) - oscillation enabled 240 khz internal oscillator (f rl ) oscillation enabled 8 mhz internal oscillator (f rh ) oscillation enabled pll (f pllo ) stops operation cpu stops operation port function holds status before idle2 mode is set timer/counter taa0 -taa4 stops operation tmm0 operable if f rh /8, f rl /8 or intwt is selected as count clock. operable if f rh /8, f rl /8, intwt or f xt is selected as count clock. watch timer (wt) operable, if clocked by prescaler3 operable watchdog timer (wdt2) operable ad convertor a a) to achieve low power consumption, stop the a/d converter before shifting to the idle2 mode. stops operation serial interface uartd0-2 uartd0: operable if asckd0 is selected as input clock uartd1-2: operation stops csib0-1 operable, if sckbn is selected as input clock. iic00 stops operation can controller (can0) stops operation interrupt controller stops operation (but it is possible to leave idle2 mode) key interrupting function operable clock monitor operable power-on-clear circuit operable low-voltage detector operable voltage regulator operation continuous internal data the cpu registers, states, data and all other internal data such as the contents of the internal ram are retained as they were before idle2 mode was set
203 clock generator chapter 4 user?s manual u18743ee1v2um00 (a) release by non-maskable interrupt request or unmasked maskable interrupt request the idle2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle2 mode is set in an interrupt routine, however, the operation is performed as follows:  if an interrupt request signal having a priority lower than that of the interrupt request currently being serviced is generated, the idle2 mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held.  if an interrupt request signal (including a non-maskable interrupt request signal) has a priority higher than that of the interrupt request currently being serviced is generated, the idle2 mode is released, and this interrupt request signal is acknowledged. (b) releasing by reset input the operation is the same as the normal reset operation. (c) securing setup time after release of idle2 mode secure the setup time of rom (flash memory) after releasing the idle2 mode.  releasing by non-maskable interrupt request signal or unmasked maskable interrupt request signal: the setup time is secured by setting the osts register. when a source that releases the idle2 mode occurs, an internal dedicated timer starts counting in accordance with the setting of the osts register. when this counter overflows, the normal operation mode is restored.  releasing by reset input (reset pin input or wdt2res occurrence) the operation is the same as the normal reset operation. the oscillation stabilization time is the default value of the osts register, 2 16 / f x . table 4-30 operation after idle2 mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after the specified setup time has elapsed. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed after the specified setup time has elapsed. the next instruction is executed after the specified setup time has elapsed.
204 chapter 4 clock generator user?s manual u18743ee1v2um00 figure 4-7 idle2 mode timing (4) stop mode in the stop mode, the subclock oscillator continues operating, but the main clock oscillator stops operating. moreover, clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is stopped, and the contents of the internal ram before the stop mode was set are retained. not only the cpu but also the other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that can operate on the subclock or external clock continue operating. the stop mode can reduce current consumption more than the idle2 mode because the operation of the main clock oscillator is stopped. when the subclock oscillator, internal oscillator, and external clock are not used, the current consumption can be substantially reduced with only a leakage current flowing. entering stop mode the stop mode is set when the psm1 and psm0 bits of the psmr register are set to ?01? or ?11?, and the stp bit of the psc register is set to 1 in the normal operation mode. insert five or more nop instructions after the store instruction that manipulates the psc register to set the stop mode. stop mode status the following table shows the operation status in the stop mode. oscillation waveform rom circuit stops. counting of setup time main clock idle mode status interrupt request table 4-31 controller status in stop mode (1/2) working condition without subclock with subclock mainosc (f x ) stops operation subosc (f xt ) - oscillation enabled 240 khz internal oscillator (f rl ) oscillation enabled 8 mhz internal oscillator (f rh ) stops operation pll (f pllo ) stops operation cpu stops operation port function holds status before stop mode is set
205 clock generator chapter 4 user?s manual u18743ee1v2um00 note 1. if the stop mode is set while the a/d converter is operating, the a/d converter is automatically stopped and starts operating again after the stop mode is released. however, in that case, the a/d conversion results up to the second conversion after the stop mode is released are invalid (the third or later conversion results are valid). all the a/d conversion results before the stop mode was set are invalid. 2. the power consumption in stop mode is the same, no matter whether the a/d converter was operating or stopped before the stop mode was set. leaving stop mode the stop mode is released by a non-maskable interrupt request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked internal interrupt request signal of a peripheral function that can operate in the stop mode, or reset signal. when the stop mode has been released, the normal operation mode is restored. note 1. interrupt request signals that are disabled by the nmi1m, nmi0m, and intm bits of the psc register are invalid and do not release the stop mode. 2. when digital noise elimination is enabled for intp3, the power save mode cannot be released using intp3 pin. for details, refer to ?pin functions? on page 31 . (a) release by non-maskable interrupt request or unmasked maskable interrupt request timer/counter taa0 -taa4 stops operation tmm0 operable if fbrg (clock of dividing frequency of prescaler3) is selected as count clock. operable if f rl /8, intwt or f xt is selected as count clock. watch timer (wt) stops operation operable if f xt is selected as count clock. watchdog timer (wdt2) operable if f rl is selected as count clock. ad convertor stops operation serial interface uartd0-2 uartd0: operable if asckd0 is selected input clock uartd1-2: operation stops. csib0-1 operable, if sckbn is selected as input clock. iic00 stops operation can controller (can0) stops operation interrupt controller stops operation (but it is possible to leave stop mode) key interrupting function operable clock monitor stops operation power-on-clear circuit operable low-voltage detector operable voltage regulator operation continuous internal data the cpu registers, states, data and all other internal data such as the contents of the internal ram are retained as they were before stop mode was set table 4-31 controller status in stop mode (2/2) working condition without subclock with subclock
206 chapter 4 clock generator user?s manual u18743ee1v2um00 the stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the stop mode is set in an interrupt routine, however, the operation is performed as follows:  if an interrupt request signal with a priority lower than that the interrupt request currently being serviced is generated, the stop mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held.  if an interrupt request signal (including a non-maskable interrupt request signal) with a priority higher than that of the interrupt request currently being serviced is generated, the stop mode is released, and this interrupt request signal is acknowledged. (b) securing setup time after release of stop mode the main clock / 8mhz internal oscillator stop operating when the stop mode is set. therefore, secure the oscillation stabilization time of the clock oscillator(s) after releasing the stop mode. releasing by non-maskable interrupt request signal or unmasked maskable interrupt request signal:  the setup time is secured by setting the osts register.  when a source that releases the stop mode occurs, an internal dedicated timer starts counting in accordance with the setting of the osts register. when this counter overflows, the normal operation mode is restored. figure 4-8 stop mode timing for main clock operation table 4-32 operation after stop mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after the specified oscillation stabilization time has elapsed. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed after the oscillation stabilization time has elapsed. the next instruction is executed after the oscillation stabilization time has elapsed. stop mode status mainosc wavefrom main clock interrupt request stop mode osc start osc setup time
207 clock generator chapter 4 user?s manual u18743ee1v2um00 (c) releasing by reset input the operation is the same as the normal reset operation. (5) subclock operation mode when the subclock operation mode is set, the cpu system clock f vbclk is changed from the main system clock to the subclock. subclock can be f xt or f rl . the selection is made by the subclk bit of the option byte 007b h . check that the cpu system clock has been changed by using the cls bit of the pcc register. when the mck bit of the pcc register is set to 1, the operation of the main clock oscillator is stopped. consequently, the entire system operates on the subclock. in the subclock operation mode, the subclock is used as the cpu system clock, so that the current consumption can be reduced from that in the normal operation mode. in addition, a current consumption close to that in the stop mode can be achieved by stopping the operation of the main clock oscillator. entering subclock mode the subclock operation mode is set when the ck3 bit of the pcc register is set to 1 in the normal operation mode. note 1. changing the value of the ck2 to ck0 bits of the pcc register is prohibited when the ck3 bit is manipulated (0 to 1 or 1 to 0). set the ck3 bit by using a bit manipulation instruction. for details of the pcc register, refer to ?pcc - processor clock control register? on page 173 . 2. if the following condition is not satisfied, change the ck2 to ck0 bits so as to satisfy the condition and move to subclock operation mode. internal system clock (fclk) > subclock (fsc) 4 subclock mode status the following table shows the operation status in subclock mode. table 4-33 controller status in subclock mode (1/2) working condition with mainosc operating with mainosc stopped mainosc (f x ) oscillation enabled subosc (f xt ) oscillation enabled 240 khz internal oscillator (f rl ) oscillation enabled 8 mhz internal oscillator (f rh ) oscillation enabled pll (f pllo ) operable stops operation a cpu operable port function settable timer/counter taa0 -taa4 operable stops operation tmm0 operable operable if f rh /8, f rl /8, intwt or f xt is selected as count clock. watch timer (wt) operable operable if f xt is selected as count clock. watchdog timer (wdt2) operable operable if f rl is selected as count clock. ad convertor operable stops operation
208 chapter 4 clock generator user?s manual u18743ee1v2um00 note 1. when stopping the main clock, be sure to stop the pll (by clearing the pllon bit of the pllctl register to 0). 2. when the cpu is operating on the subclock and main clock oscillation is stopped, accessing a register in which a wait occurs is disabled. if a wait is generated, it can be released only by reset . leaving subclock mode the subclock operation mode is released by clearing the ck3 bit to 0 or by a reset signal. note 1. changing the set value of the ck2 to ck0 bits of the pcc register is prohibited when the ck3 bit is manipulated (set the ck3 bit by using a bit manipulation instruction). for details of the pcc register, refer to ?pcc - processor clock control register? on page 173 . 2. when digital noise elimination is enabled for intp3, the power save mode cannot be released using intp3 pin. for details, refer to ?pin functions? on page 31 . when the main clock is stopped (pcc.mck = 1), clear the mck bit to 0, secure the oscillation stabilization time of the main clock by software, and then clear the ck3 bit to 0. when the subclock operation mode is released, the normal operation mode is restored. (6) sub-idle mode in the sub-idle mode, the clock oscillator continues operating, but clock supply to the cpu, flash memory, and the other on-chip peripheral functions is stopped. as a result, program execution is stopped, and the contents of the internal ram before the sub-idle mode was set is retained. not only the cpu but also serial interface uartd0-2 operable uartd0: operable if asckd0 is selected input clock uartd1-2: operation stops csib0-1 operable operable if sckbn input clock is selected as operation clock. iic00 operable stops operation can controller (can0) operable stops operation interrupt controller operable key interrupting function operable clock monitor operable power-on-clear circuit operable low-voltage detector operable voltage regulator operation continuous internal data settable a) set pll to stop (pllctl.pllon = 0) when you stop the main clock oscillation circuit. table 4-33 controller status in subclock mode (2/2) working condition with mainosc operating with mainosc stopped
209 clock generator chapter 4 user?s manual u18743ee1v2um00 the other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that can operate on the subclock continue operating. the sub-idle mode can reduce current consumption more than the subclock operation mode because the operations of the cpu, flash memory, and other on-chip peripheral functions are stopped. if the sub-idle mode is set after the main clock is stopped, a current consumption close to that in the stop mode can be achieved. entering sub-idle mode the sub-idle mode is set when the psm1 and psm0 bits of the psmr register are set to ?10? and the stp bit of the psc register is set to 1 while the processor is in the subclock operation mode. note insert five or more nop instructions after the store instruction that manipulates the psc register to set the sub-idle mode. sub-idle mode status the following table shows the operation status in sub-idle mode. table 4-34 controller status in sub-idle mode working condition when main clock oscillator oscillates when main clock oscillator stops 240 khz internal oscillator (f rl ) oscillation enabled 8 mhz internal oscillator (f rh ) oscillation enabled pll (f pllo ) operable stops operation a a) stop the pll (pllctl.pllon = 0) when you stop the main clock oscillation circuit. cpu stops operation port function the settings of the previous mode are maintained timer/counter taa0 -taa4 stops operation tmm0 operable if f rh /8, f rl /8 or f xt is selected as count clock. watch timer (wt) operable operable if f xt is selected as count clock. watchdog timer (wdt2) operable operable if f rl is selected as count clock. ad convertor stops operation serial interface uartd0-2 uartd0: operable, if asckd0 is selected as input clock uartd1-2: operation stops csib0-1 operable if sckbn input clock is selected as operation clock. iic00 stops operation can controller (can0-3) stops operation interrupt controller stops operation (but it is possible to leave sub idle mode) key interrupting function operable clock monitor operable power-on-clear circuit operable low-voltage detector operable voltage regulator operation continuous internal data the cpu registers, statuses, data and all other internal data such as the contents of the internal ram are retained as they were before sub idle mode was set
210 chapter 4 clock generator user?s manual u18743ee1v2um00 leaving sub-idle mode the sub-idle mode is released by a non-maskable interrupt request signal (nmi pin input or intwdt2 signal), unmasked external interrupt request signal, unmasked internal interrupt request of a peripheral function that can operate in the sub-idle mode, or reset signal. the pll returns to the operation status before the sub-idle mode was set. when the sub-idle mode is released by an interrupt request signal, the subclock operation mode is restored. when the sub-idle mode is released by reset , the normal operation mode is restored. note 1. interrupt request signals that are disabled by the nmi1m, nmi0m, and intm bits of the psc register are invalid and do not release the sub-idle mode. 2. when digital noise elimination is enabled for intp3, the power save mode cannot be released using intp3 pin. for details, refer to ?pin functions? on page 31 . (a) release by non-maskable interrupt request or unmasked maskable interrupt request the sub-idle mode is released by a non-maskable interrupt signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the sub-idle mode is set in an interrupt routine, however, the operation is performed as follows:  interrupt request signals that are set (disabled) by the nmi1m, nmi0m, and intm bits of the psc register are invalid and do not release the sub-idle mode.  if an interrupt request signal having a priority lower than that of the interrupt request currently being serviced is generated, the sub-idle mode is released, but the interrupt request with the lower priority is not acknowledged. the interrupt request signal itself is held.  if an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher than that of the interrupt request currently being serviced is generated, the sub-idle mode is released, and this interrupt request signal is acknowledged. (b) releasing by reset input the operation is the same as the normal reset operation. table 4-35 operation after sub-idle mode is released by interrupt request signal releasing source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address, or the next instruction is executed. the next instruction is executed.
211 clock generator chapter 4 user?s manual u18743ee1v2um00 4.4.4 available clocks in power save modes the following table gives an overview of the clock signals available in the various stand-by modes. table 4-36 clock operation in power save modes operation status f x /f plli note2 f xt note2 f rl note2 f rh note2 f pll f pcl f xx f xp1 f vbclk f cpu f xp2 f xc reset period xoxxxxx xxxx from reset release to 8 mhz internal oscillator setup xoooxox xxxx 8 mhz internal oscillator note1 run enable o enable o enable oo ooo enable halt mode enable o enable o enable oo o xo enable idle1 mode enable o enable o enable xx xxox stop mode x o enable xxxx xxxx from stop release to oscillation stabilization enable o enable oxox x xo enable mainosc note1 run o o enable enable enable oo oooo halt mode o o enable enable enable oo o xoo idle1 mode o o enable enable enable xx xxox idle2 mode o o enable enable xxx xxxx from idle2 release to setup oo enable enable xxx xxxx stop mode x o enable xxxx xxxx from stop release to oscillation stabilization oo enable enable xxx xxxx pll/ note1 run o o enable enable ooo oooo halt mode o o enable enable ooo o xoo idle1 mode o o enable enable ox x x xox idle2 mode o o enable enable xxx xxxx from idle2 release to setup oo enable enable xxx xxxx stop mode x o enable xxxx xxxx from stop release to oscillation stabilization oo enable enable xxx xxxx subosc note1 run enable o enable enable enable enable enable oo enable enable idle mode enable o enable enable enable xx xxxx 240 khz internal oscillator- sub note1 run enable oo enable enable enable enable oo enable enable halt mode enable oo enable enable xx xxxx 240 khz internal oscillator- security note1 run - o o enable - enable enable oo enable enable halt mode - o o enable - enable enable ox enable enable
212 chapter 4 clock generator user?s manual u18743ee1v2um00 o: operating x: stopped enable: operation enable (by control register and option bytes setting) note 1. the working conditions are the following: 2. the clock signals are: - 8 mhz internal oscillator: 8 mhz internal oscillator clock operation - mainosc: mainosc clock operation - pll: pll clock operation - subosc: subosc clock operation - 240 khz internal oscillator- sub: 240 khz internal oscillator clock operation for sub - 240 khz internal oscillator- security: 240 khz internal oscillator clock operation for security f x : mainosc clock f xt : subosc clock f rl : 240 khz internal oscillator clock f rh : 8 mhz internal oscillator clock f pll : pll output clock f pcl : programmable clock output f xx : main system clock f vbclk : cpu system clock f cpu :cpu core clock f xp1 : peripheral clock (prescaler1) f xp2 :clock for uartd, taa f xc :clock for can
213 clock generator chapter 4 user?s manual u18743ee1v2um00 4.4.5 power save mode activation in the following procedures are described how to securely entering a power save mode. (1) halt mode for entering the halt mode proceed as follows: 1. mask all interrupts which shall not have wake-up capability by xxic.xxmk = 0 and discard all possibly pending interrupts by xxic.xxif = 0. 2. unmask all interrupts which shall have wake-up capability by xxic.xxmk = 1. 3. execute the ?halt? instruction. (2) idle1, idle2 and stop mode for entering these power save mode proceed as follows: 1. in case maskable interrupts shall be used for wake-up unmask these interrupts by imrm.xxmk = 0 (refer to ?imrm - interrupt mask registers? on page 240 ). 2. mask all other interrupts, i.e. ? none wake-up capable interrupts ? wake-up capable interrupts which shall not be used for wake-up by imrm.xxmk = 1. this prevents the power save mode entry procedure from being interrupted by these interrupts. 3. it is recommended to disable interrupt acknowledgement by the ?di? instruction. 4. specify the desired power save mode in psm.psm[1:0]. 5. enable writing to the write-protected register psc by writing to prcmd. 6. write to psc for specifying permitted wake-up events and activate the power save mode by setting psc.stp to 1. example the following example shows how to initialize and enter a idle1, idle2 or stop power save mode. first the desired power save mode is specified (idle2 mode in this example, that means psmr.psm[1:0] = 10 b ). the psc register is a write-protected register, and the prcmd register is the corresponding write-enable register. prcmd has to be written immediately before writing to psc.
214 chapter 4 clock generator user?s manual u18743ee1v2um00 in this example, maskable interrupts are permitted to leave the power save mode. be aware of the following notes when entering power save mode using the above sequence: note 1. it is recommended to disable maskable interrupt acknowledgement in general by the ?di? instruction (step 3.) to prevent any pending interrupt from being served during the power save mode set-up procedure. this makes it also possible to completely control the process after wake-up, since no pending interrupt will be unintentional acknowledged. before enabling interrupt acknowledgement by the ?ei? instruction (step 16.) after wake-up, all unwanted interrupts can be discarded by setting xxic.xxif = 0 (step 15.). since the wake-up capability of the unmasked wake-up interrupts is not affected by ?di?, such interrupts shall be masked (step 1.) by imrm.xxmk = 1. 2. the store instruction to prcmd will not allow to acknowledge any interrupt until processing of the subsequent instruction is complete. that means, an interrupt will not be acknowledged before the store to psc. this presupposes that both store instructions are performed consecutively, as shown in the above example. if another instruction is placed between steps 7 and 8, an interrupt request may be acknowledged in between, and the power save mode may not be entered. however if the ?di? instruction was executed before (step 3.) none interrupt will be acknowledged anyway. 3. at least 5 ?nop? instructions must follow the power down mode setting, that means after the write to psc. the microcontroller requires this time to enter power down mode. 4. any data can be written to the prcmd register. in the example the same data is written, minimizing the number of used registers. 5. no special sequence is required for reading the psc register. 3. // xxic.xxmk = 0 // mask all none wake-up interrupts 4. // xxic.xxmk = 1 // unmask all wake-up interrupts 5. di 6. mov 0x02,r10 7. st.b 10,psmr[r0] // psmr.psm[1:0] = 10b: idle2 mode 8. mov 0x62,r10 9. st.b r10,prcmd[r0] // enable write to psc 10. st.b r10,psc[r0] // wake up by maskable interrupts // and enter power save mode 11. nop 12. nop 13. nop 14. nop 15. nop 16. // after wake-up 17. // xxic.xxif = 0 // discard all unwanted pending interrupts 18. ei
215 clock generator chapter 4 user?s manual u18743ee1v2um00 4.4.6 controlling the pll using the pll after the reset signal has been released, the pll has to be started by pllctl.pllon = 1, after the main oscillator has stabilized (ostc.msts = 1). since the default mode is the clock-through mode (pllctl.selpll = 0), select the pll mode (pllctl.selpll = 1).  to operate the pll from the stopped status, set pllctl.pllon = 1, and then set pllctl.selpll = 1 after the lockr.lock bit = 0 (the lockup time can be counted by setting the lockup time to the plls register and monitoring the lock flag of the lockr register).  to stop the pll, first select the clock-through mode (pllctl.selpll = 0), wait for 8 clocks or more, and then stop the pll (set pllctl.pllon = 0). when shifting to the idle2 or stop mode while remaining in the pll operation mode, set the osts register as follows:  stop mode: oscillation stabilization time > pll lockup time  idle2 mode: setup time > pll lockup time when shifting to the idle1 mode, the pll does not stop. stop the pll if necessary. not using the pll the clock-through mode (pllctl.selpll = 0) is selected after the reset signal has been released. the pll is stopped by default. 4.4.7 watch dog timer clock after reset release, the watchdog timer wdt2 is operating on the 240 khz internal oscillator (f rl /8 = 30 khz approx.). when the mainosc has stabilized, the watchdog timer can be clocked by the mainosc (f x /128). 4.4.8 clkout function the clock output function is used to output the cpu system clock (f vbclk ) from the clkout pin. the status of the clkout pin is the same as the cpu system clock. the pin can output the clock when it is in the operable status. it outputs a low level in the stopped status.
216 chapter 4 clock generator user?s manual u18743ee1v2um00 4.4.9 operation of prescaler3 prescaler3 generates the clock f brg by dividing the main oscillator output signal f x . (1) description prescaler3 consists of a clock divider, a counter, and a comparator. figure 4-9 prescaler3 block diagram (2) calculation the relation between the main oscillator clock (f x ), prescaler clock divider selection prsm0.bgcs0[1:2], prscm0 compare register value, and output clock f brg is as follows: f brg = f x / (2 m n 2) where f brg = output clock frequency f x = input clock frequency m = bgcs0[1:0] value (0 to 3) n = prscm0 register value (1 to ff h ). if prscm0 = 00 h : n = 256 example if f x = 4 mhz m = 0 n = 3d h then f brg = 32,787 khz
217 clock generator chapter 4 user?s manual u18743ee1v2um00 4.4.10 operation of the clock monitor the clock monitor samples the main clock by using the on-chip 240 khz internal oscillator. it generates a reset request signal when the oscillation of the main clock has stopped. (1) description the functional block diagram is shown below. figure 4-10 clock monitor block diagram the clock monitor samples the main oscillator signal f x . the clock monitor is clocked by the on-chip 240 khz internal oscillator (f rl ). the resclm reset signal is generated when the mainosc clock fails. mainosc f x 240 khz internal oscillator f rl resclm enable/disable clm.clme (lnternal reset signal) table 4-37 operation status of clock monitor (when clm.clme bit = 1, during internal oscillator operation) cpu system clock f vbclk operation mode status of mainosc status of internal oscillator clock status of clock monitor main clock halt mode oscillates oscillates a operates b idle1 mode, idle2 mode oscillates oscillates a operates b stop mode stops oscillates a stops subclock (mck bit of pcc register = 0) sub-idle mode oscillates oscillates a operates b subclock (mck bit of pcc register = 1) sub-idle mode stops oscillates a stops during reset ? stops stops stops a) internal oscillator can be stopped by setting the rstop bit of the rcm register to 1 only when ?internal oscillator can be stopped? is specified by an option function. b) the clock monitor is stopped when the internal oscillator is stopped.
218 chapter 4 clock generator user?s manual u18743ee1v2um00 (2) start and stop the clock monitor operation must be enabled by setting bit clm.clme to 1. once this bit has been set, it cannot be cleared to 0 by any means other than reset. the clock monitor is automatically started as soon as the main oscillator is stable, indicated by ostc.msts = 1. the clock monitor automatically stops under the following conditions:  while oscillation stabilization time is being counted after stop mode is released  when the main clock is stopped (pcc.mck bit = 1 during subclock operation, or pcc.cls bit = 0 during main clock operation)  when the sampling clock is stopped (240 khz internal oscillator)  when the cpu operates with 8 mhz internal oscillator  when the cpu operates with 240 khz internal oscillator (3) operation when main clock oscillation is stopped (clme bit = 1) if oscillation of the main clock is stopped when the clme bit = 1, an internal reset signal is generated as shown in the following figure. figure 4-11 when oscillation of main clock is stopped (4) operation in stop mode or after stop mode is released if the stop mode is set with the clme bit = 1, the monitor operation is stopped in the stop mode and while the oscillation stabilization time is being counted. after the oscillation stabilization time, the monitor operation is automatically started. four internal oscillator clocks main clock internal oscillator clock internal reset signal
219 clock generator chapter 4 user?s manual u18743ee1v2um00 figure 4-12 operation in stop mode or after stop mode is released (5) operation when main clock is stopped during subclock operation (cls bit of the pcc register = 1) or when the main clock is stopped by setting the mck bit of the pcc register to 1, the monitor operation is stopped until the main clock operation is started (cls bit of pcc register = 0). the monitor operation is automatically started when the main clock operation is started. figure 4-13 operation when main clock is stopped (arbitrary) clock monitor status during monitor monitor stops during monitor clme internal oscillator clock main clock cpu operation normal operation software stop oscillation stabilization time normal operation oscillation stops oscillation stabilization time (set by osts register) clock monitor status during monitor monitor stops monitor stops during monitor clme internal oscillator clock main clock cpu operation oscillation stops subclock operation main clock operation oscillation stabilization time (set by osts register) oscillation stabilization time count by software pccmck bit = 1
220 chapter 4 clock generator user?s manual u18743ee1v2um00 (6) operation during and after power save modes main oscillator stopped if the main oscillator is stopped, the clock monitor changes to stand-by. when the main oscillator is restarted after power save mode release, the clock monitor restarts automatically. internal oscillator stopped when the 240 khz internal oscillator is stopped, the clock monitor?s operation is suspended. operation is automatically resumed as soon as the internal oscillator is restarted.
221 user?s manual u18743ee1v2um00 chapter 5 interrupt controller (intc) this controller is provided with a dedicated interrupt controller (intc) for interrupt servicing and can process a large amount of maskable and two non- maskable interrupt requests. an interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. generally, an exception takes precedence over an interrupt. this controller can process interrupt requests from the on-chip peripheral hardware and external sources. moreover, exception processing can be started by the trap instruction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). eight levels of software-programmable priorities can be specified for each interrupt request. starting of interrupt servicing takes no fewer than 5 system clocks after the generation of an interrupt request. 5.1 features  interrupts ? non-maskable interrupts: 2 sources ? maskable interrupts: ? 8 levels of programmable priorities (maskable interrupts) ? multiple interrupt control according to priority ? masks can be specified for each maskable interrupt request ? noise elimination, edge detection and valid edge specification, level detection for external interrupt request signals ? wake-up capable (analogue noise elimination for external interrupt request signals)  exceptions ? software exceptions: 2 channels with each 16 sources ? exception traps: 2 sources (illegal opcode exception and debug trap) maskable interrupts v850es/fe3-l v850es/ff3-l v850es/fg3-l internal 39 42 external 8 11
222 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 note 1. default priority: the priority order when two or more maskable type interrupt/exception source default priority exception code handler address restored pc name control register generating source generating unit reset reset ? reset input by internal source reset ? 0000h 00000000h undef. non? maskable nmi ? nmi pin valid edge input pin ? 0010h 00000010h nextpc intwdt2 ? wdt2 overflow wdt2 ? 0020h 00000020h nextpc software exception trap0n (n = 0 to f h ) ? trap instruction ? ? 004nh 00000040h nextpc trap1n (n = 0 to f h ) ? trap instruction ? ? 005nh 00000050h nextpc exception trap ilgop/ dbg0 ? illegal opcode/dbtrap instruction ? ? 0060h 00000060h nextpc maskable intlvil lvilic low voltage detection (voltage falling below reference level) poclvi 0 0080h 00000080h nextpc intlvih lvihic low voltage detection (voltage rising above reference level) poclvi 1 0090h 00000090h nextpc intp0 pic0 external interrupt 0 pin 2 00a0h 000000a0h nextpc intp1 pic1 external interrupt 1 pin 3 00b0h 000000b0h nextpc intp2 pic2 external interrupt 2 pin 4 00c0h 000000c0h nextpc intp3 pic3 external interrupt 3 pin 5 00d0h 000000d0h nextpc intp4 pic4 external interrupt 4 pin 6 00e0h 000000e0h nextpc intp5 pic5 external interrupt 5 pin 7 00f0h 000000f0h nextpc intp6 pic6 external interrupt 6 pin 8 0100h 00000100h nextpc intp7 pic7 external interrupt 7 pin 9 0110h 00000110h nextpc inttaa0ov taa0ovic taa0 overflow taa0 15 0170h 00000170h nextpc inttaa0cc0 taa0ccic0 taa0 capture 0 / compare 0 match taa0 16 0180h 00000180h nextpc inttaa0cc1 taa0ccic1 taa0 capture 1 / compare 1 match taa0 17 0190h 00000190h nextpc inttaa1ov taa1ovic taa1 overflow taa1 18 01a0h 000001a0h nextpc inttaa1cc0 taa1ccic0 taa1 capture 0 / compare 0 match taa1 19 01b0h 000001b0h nextpc inttaa1cc1 taa1ccic1 taa1 capture 1 / compare 1 match taa1 20 01c0h 000001c0h nextpc inttaa2ov taa2ovic taa2 overflow taa2 21 01d0h 000001d0h nextpc inttaa2cc0 taa2ccic0 taa2 capture 0 / compare 0 match taa2 22 01e0h 000001e0h nextpc inttaa2cc1 taa2ccic1 taa2 capture 1 / compare 1 match taa2 23 01f0h 000001f0h nextpc inttaa3ov taa3ovic taa3 overflow taa3 24 0200h 00000200h nextpc inttaa3cc0 taa3ccic0 taa3 capture 0 / compare 0 match taa3 25 0210h 00000210h nextpc inttaa3cc1 taa3ccic1 taa3 capture 1 / compare 1 match taa3 26 0220h 00000220h nextpc inttaa4ov taa4ovic taa4 overflow taa4 27 0230h 00000230h nextpc inttaa4cc0 taa4ccic0 taa4 capture 0 / compare 0 match taa4 28 0240h 00000240h nextpc inttaa4cc1 taa4ccic1 taa4 capture 1 / compare 1 match taa4 29 0250h 00000250h nextpc inttm0eq0 tm0eqic0 tmm0 compare match tmm0 30 0260h 00000260h nextpc intcb0r cb0ric csib0 reception completion / reception error csib0 31 0270h 00000270h nextpc intcb0t cb0tic csib0 consecutive transmission write enable csib0 32 0280h 00000280h nextpc
223 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 interrupt requests are generated at the same time. the highest priority is 0. 2. restored pc: the value of the pc saved to eipc or fepc when interrupt/exception processing is started. however, the value of the pc saved when an interrupt is acknowledged during division (div, divh, divu, divhu) instruction execution is the value of the pc of the current instruction (div, divh, divu, divhu). 3. nextpc: the pc value that starts the processing following interrupt/exception processing. 4. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). maskable intcb1r cb1ric csib1 reception completion / reception error csib1 33 0290h 00000290h nextpc intcb1t cb1tic csib1 consecutive transmission write enable csib1 34 02a0h 000002a0h nextpc intud0s ud0sic uartd0 status interrupt uartd0 35 02b0h 000002b0h nextpc intud0r ud0ric uartd0 reception completion uartd0 36 02c0h 000002c0h nextpc intud0t ud0tic uartd0 consecutive transmission enable uartd0 37 02d0h 000002d0h nextpc intud1s ud1sic uartd1 status interrupt uartd1 38 02e0h 000002e0h nextpc intud1r ud1ric uartd1 reception completion uartd1 39 02f0h 000002f0h nextpc intud1t ud1tic uartd1 consecutive transmission enable uartd1 40 0300h 00000300h nextpc intiic0 iic0ic iic0 transfer completion iic0 41 0310h 00000310h nextpc intad adic a/d conversion completion ad 42 0320h 00000320h nextpc intc0err c0erric can0 error can0 43 0330h 00000330h nextpc intc0wup c0wupic can0 wake?up can0 44 0340h 00000340h nextpc intc0rec c0recic can0 reception can0 45 0350h 00000350h nextpc intc0trx c0trxic can0 transmission can0 46 0360h 00000360h nextpc intkr kric key return interrupt kr 51 03b0h 000003b0h nextpc intwti wtiic watch timer interval wt 52 03c0h 000003c0h nextpc intwt wtic watch timer reference time wt 53 03d0h 000003d0h nextpc reserved ? ? ? 54 03e0h 000003e0h nextpc intfl flic flash programming completion flash 55 03f0h 000003f0h nextpc intp8 a pic8 external interrupt 8 pin 56 0400h 00000400h nextpc intp9 a pic9 external interrupt 9 pin 57 0410h 00000410h nextpc intp10 a pic10 external interrupt 10 pin 58 0420h 00000420h nextpc intud2s a ud2sic uartd2 status interrupt uartd2 64 0480h 00000480h nextpc intud2r a ud2ric uartd2 reception completion uartd2 65 0490h 00000490h nextpc intud2t a ud2tic uartd2 consecutive transmission enable uartd2 66 04a0h 000004a0h nextpc a) not available for v850es/fe3-l, v850es/ff3-l type interrupt/exception source default priority exception code handler address restored pc name control register generating source generating unit
224 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 5.2 non-maskable interrupts a non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (di) status. non-maskable interrupts of this microcontroller are available for the following requests:  nmi: nmi pin input  intwdt2: non-maskable watchdog timer interrupt request when the valid edge, specified by the intr0.intr02 and intf0.intf02, is detected atthe nmi pin, the nmi interrupt occurs. the watchdog timer interrupt request is only effective as non-maskable interrupt if wdtm2.wdm2[1:0] = 01 b is chosen in the watchdog timer mode register. if multiple non-maskable interrupts are generated at the same time, the highest priority servicing is executed according to the following priority order (the lower priority interrupt is ignored): intwdt2 > nmi note that if a nmi from port pin or intwdt2 request is generated while nmi from port pin is being serviced, the service is executed as follows. (1) if a nmi is generated while nmi is being serviced the new nmi request is held pending regardless of the value of the psw.np bit. the pending nmivc request is acknowledged after servicing of the current nmi request has finished (after execution of the reti instruction). (2) if a intwdt2 request is generated while nmi is being serviced if the psw.np bit remains set (1) while nmi is being serviced, the new intwdt2 request is held pending. the pending intwdt2 request is acknowledge after servicing of the current nmi request has finished (after execution of the reti instruction). if the psw.np bit is cleared (0) while nmi is being serviced, the newly generated intwdt2 request is executed (nmi servicing is halted). caution 1. although the values of the pc and psw are saved to an nmi status save register (fepc, fepsw) when a non-maskable interrupt request is generated, only the nmi can be restored by the reti instruction at this time. because intwdt2 cannot be restored by the reti instruction, the system must be reset after servicing this interrupt. 2. if psw.np is cleared to 0 by the ldsr instruction during non-maskable interrupt servicing, a nmi interrupt afterwards cannot be acknowledged correctly.
225 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 figure 5-1 example of non-maskable interrupt request acknowledgement operation: multiple nmi requests generated at the same time nmi and intwdt2 requests generated simultaneously nmi and intwdt2 requests (generated simultaneously) main routine intwdt2 servicing system reset
226 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 figure 5-2 example of non-maskable interrupt request acknowledgement operation: nmi request generated during nmi servicing main routine nmi request intwdt2 request nmi servicing (held pending) system reset nmi request generated during nmi servicing nmi being serviced nmi nmi nmi request generated during nmi servicing intwdt2 request generated during nmi servicing (np = 1 retained before nmi1 request) intwdt2 request generated during nmi servicing (np=0 set before intwdt2 request) intwdt2 nmi request generated during intwdt2 servicing nmi request generated during intwdt2 servicing main routine nmi request nmi request nmi servicing (held pending) servicing of pending nmi main routine nmi request (invalid) system reset main routine (invalid) system reset main routine nmi request nmi servicing system reset np = 0 main routine nmi request nmi servicing system reset np = 0 (held pending) intwdt2 servicing request servicing intwdt2 request generated during nmi servicing (np=0 set after intwdt2 request) servicing request request request intwdt2 request servicing servicing intwdt2 intwdt2 intwdt2 intwdt2 intwdt2 intwdt2 intwdt2
227 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 5.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following processing, and transfers control to the handler routine: 1. saves the restored pc to fepc. 2. saves the current psw to fepsw. 3. writes exception code 0010h to the higher halfword (fecc) of ecr. 4. sets the np and id bits of the psw and clears the ep bit. 5. sets the handler address corresponding to the non-maskable interrupt to the pc, and transfers control. the processing configuration of a non-maskable interrupt is shown in figure 5-3 . figure 5-3 processing configuration of non-maskable interrupt non-m as k ab le interr u pt re qu e s t fepc re s tored pc fepsw psw ecr.fecc exception code psw.np 1 psw.ep 0 psw.id 1 pc nmi-h a ndler a ddre ss 0 psw.np intc a cknowledgement cpu proce ss ing 1 nmi inp u t interr u pt s ervice interr u pt re qu e s t pending
228 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 5.2.2 restore (1) nmi execution is restored from the non-maskable interrupt (nmi) processing by the reti instruction. when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. 1. restores the values of the pc and the psw from fepc and fepsw, respectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. 2. transfers control back to the address of the restored pc and psw. figure 5-4 illustrates how the reti instruction is processed. figure 5-4 reti instruction processing caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during non-maskable interrupt processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. note the solid line indicates the cpu processing flow. psw.ep reti in s tr u ction psw.np origin a l proce ss ing re s tored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw
229 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 (2) intwdt2 restoring by reti instruction is not possible. perform a system reset after interrupt servicing. 5.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that indicates that non-maskable interrupt (nmi) processing is under execution. this flag is set when an nmi interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. 5.2.4 nmi control the nmi can be configured to generate a non-maskable interrupt upon a rising, falling or both edges at the nmi pin. to enable respectively disable the nmi and to configure the edge refer to ?external interrupts edge detection configuration? on page 244 . 31 876543210initial value psw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 np ep id sat cy ov s z 00000020h bit position bit name function 7np indicates whether nmi interrupt processing is in progress. 0: no nmi interrupt processing 1: nmi interrupt currently being processed
230 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 5.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. this microcontroller has up to 52 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). when an interrupt request has been acknowledged, the acknowledgement of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt processing routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the interrupt control register). note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. however, if multiple interrupts are executed, the following processing is necessary. 1. save eipc and eipsw in memory or a general-purpose register before executing the ei instruction. 2. execute the di instruction before executing the reti instruction, then reset eipc and eipsw with the values saved in (1). 5.3.1 operation if a maskable interrupt occurs, the cpu performs the following processing, and transfers control to a handler routine: 1. saves the restored pc to eipc. 2. saves the current psw to eipsw. 3. writes an exception code to the lower halfword of ecr (eicc). 4. sets the id bit of the psw and clears the ep bit. 5. sets the handler address corresponding to each interrupt to the pc, and transfers control. the processing configuration of a maskable interrupt is shown in figure 5-5 .
231 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 figure 5-5 maskable interrupt processing note for the ispr register, see ?ispr - in-service priority register? on page 242 . an int input masked by the interrupt controllers and an int input that occurs while another interrupt is being processed (when psw.np = 1 or psw.id = 1) are held pending internally by the interrupt controller. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new maskable interrupt processing. int inp u t xxif = 1 no xxmk = 0 no i s the interr u pt m as k rele as ed? ye s ye s no no no m as k ab le interr u pt re qu e s t interr u pt re qu e s t pending psw.np psw.id 1 1 interr u pt re qu e s t pending 0 0 interr u pt proce ss ing cpu proce ss ing intc a ccepted ye s ye s ye s priority higher th a n th a t of interr u pt c u rrently proce ss ed? priority higher th a n th a t of other interr u pt re qu e s t? highe s t def au lt priority of interr u pt re qu e s t s with the sa me priority? eipc eipsw ecr.eicc psw.ep psw.id pc re s tored pc psw exception code 0 1 h a ndler a ddre ss
232 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 5.3.2 restore recovery from maskable interrupt processing is carried out by the reti instruction. when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. 1. restores the values of the pc and the psw from eipc and eipsw because the ep bit of the psw is 0 and the np bit of the psw is 0. 2. transfers control to the address of the restored pc and psw. figure 5-6 illustrates the processing of the reti instruction. figure 5-6 reti instruction processing note 1. for the ispr register, see ?ispr - in-service priority register? on page 242 . 2. the solid lines show the cpu processing flow. caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. psw.ep reti in s tr u ction psw.np re s tore s origin a l proce ss ing 1 1 0 0 pc psw corre s ponding b it of ispr note eipc eipsw 0 pc psw fepc fepsw
233 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 5.3.3 priorities of maskable interrupts this microcontroller provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxprn) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, refer to the interrupt/exception source list table. the programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of psw is automatically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction in the interrupt service program) to set the interrupt enable mode.
234 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 figure 5-7 example of processing in which another interrupt request is issued while an interrupt is being processed (1/2) caution the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. m a in ro u tine ei ei interr u pt re qu e s t a (level 3 ) proce ss ing of a proce ss ing of b proce ss ing of c interr u pt re qu e s t c (level 3 ) proce ss ing of d proce ss ing of e ei interr u pt re qu e s t e (level 2) proce ss ing of f ei proce ss ing of g interr u pt re qu e s t g (level 1) interr u pt re qu e s t h (level 1) proce ss ing of h interr u pt re qu e s t b i s a cknowledged b ec aus e the priority of b i s higher th a n th a t of a a nd interr u pt s a re en ab led. altho u gh the priority of interr u pt re qu e s t d i s higher th a n th a t of c, d i s held pending b ec aus e interr u pt s a re di sab led. interr u pt re qu e s t f i s held pending even if interr u pt s a re en ab led b ec aus e it s priority i s lower th a n th a t of e. interr u pt re qu e s t h i s held pending even if interr u pt s a re en ab led b ec aus e it s priority i s the sa me as th a t of g. interr u pt re qu e s t b (level 2) interr u pt re qu e s t d (level 2) interr u pt re qu e s t f (level 3 )
235 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 note 1. to in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. figure 5-8 example of processing in which another interrupt request is issued while an interrupt is being processed (2/2) m a in ro u tine ei interr u pt re qu e s t i (level 2) proce ss ing of i proce ss ing of k interr u pt re qu e s t j (level 3 ) proce ss ing of j interr u pt re qu e s t l (level 2) ei ei ei interr u pt re qu e s t o (level 3 ) interr u pt re qu e s t s (level 1) interr u pt re qu e s t k (level 1) proce ss ing of l proce ss ing of n proce ss ing of m proce ss ing of s proce ss ing of u proce ss ing of t interr u pt re qu e s t m (level 3 ) interr u pt re qu e s t n (level 1) proce ss ing of o interr u pt re qu e s t p (level 2) interr u pt re qu e s t q (level 1) interr u pt re qu e s t r (level 0) interr u pt re qu e s t u (level 2) note 2 interr u pt re qu e s t t (level 2) note 1 proce ss ing of p proce ss ing of q proce ss ing of r ei if level s 3 to 0 a re a cknowledged interr u pt re qu e s t j i s held pending b ec aus e it s priority i s lower th a n th a t of i. k th a t occ u r s a fter j i s a cknowledged b ec aus e it h as the higher priority. interr u pt re qu e s t s m a nd n a re held pending b ec aus e proce ss ing of l i s performed in the interr u pt di sab led s t a t us . pending interr u pt re qu e s t s a re a cknowledged a fter proce ss ing of interr u pt re qu e s t l. at thi s time, interr u pt re qu e s t s n i s a cknowledged fir s t even tho u gh m h as occ u rred fir s t b ec aus e the priority of n i s higher th a n th a t of m. pending interr u pt re qu e s t s t a nd u a re a cknowledged a fter proce ss ing of s . bec aus e the prioritie s of t a nd u a re the sa me, u i s a cknowledged fir s t b ec aus e it h as the higher def au lt priority, reg a rdle ss of the order in which the interr u pt re qu e s t s h a ve b een gener a ted.
236 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 caution the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. note 1. lower default priority 2. higher default priority figure 5-9 example of processing interrupt requests simultaneously generated caution the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. note to in the figure are the temporary names of interrupt requests shown for the sake of explanation. def au lt priority a > b > c m a in ro u tine ei interr u pt re qu e s t a (level 2) interr u pt re qu e s t b (level 1) interr u pt re qu e s t c (level 1) proce ss ing of interr u pt re qu e s t b . . proce ss ing of interr u pt re qu e s t c proce ss ing of interr u pt re qu e s t a interr u pt re qu e s t b a nd c a re a cknowledged fir s t a ccording to their prioritie s . bec aus e the prioritie s of b a nd c a re the sa me, b i s a cknowledged fir s t a ccording to the def au lt priority. nmi re qu e s t
237 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 5.3.4 xxicn - maskable interrupt control registers an interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. access this register can be read/written in 1-bit or 8-bit units. address ffff f110 h to ffff f194 h initial value 47 h . the register is initialized by any reset note xx: identification name of each peripheral unit (lvil, lvih, p, taa0ov-taa4ov, taa0cc-taa4cc, tm0eq, cb0r-cb1r, cb0t-cb1t, ud0s-ud2s, ud0r- ud2r, ud0t-ud2t, iic0, ad, c0err, c0wup, c0rec, c0trx, kr, wti, wt, fl) the address and the availability of each interrupt control register for each device is shown in the following table. note the symbols used in the table mean: : register available for the device ?: register not available for the device 76543210 xxicn xxifn xxmkn 0 0 0 xxpr2 xxpr1 xxpr0 bit position bit name function 7xxifn this is an interrupt request flag. 0: interrupt request not issued 1: interrupt request issued the flag xxifn is reset automatically by the hardware if an interrupt request is acknowledged. 6xxmkn this is an interrupt mask flag. 0: enables interrupt processing 1: disables interrupt processing (pending) 2 to 0 xxpr2 to xxpr0 8 levels of priority order are specified for each interrupt. xxpr2 xxpr1 xxpr0 interrupt priority specification bit 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest)
238 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 address register v850es/fe3-l/ v850es/ff3-l v850es/fg3-l fffff110h lvilic ? fffff112h lvihic ? fffff114h pic0 ? fffff116h pic1 ? fffff118h pic2 ? fffff11ah pic3 ? fffff11ch pic4 ? fffff11eh pic5 ? fffff120h pic6 ? fffff122h pic7 ? fffff12eh taa0ovic ? fffff130h taa0ccic0 ? fffff132h taa0ccic1 ? fffff134h taa1ovic ? fffff136h taa1ccic0 ? fffff138h taa1ccic1 ? fffff13ah taa2ovic ? fffff13ch taa2ccic0 ? fffff13eh taa2ccic1 ? fffff140h taa3ovic ? fffff142h taa3ccic0 ? fffff144h taa3ccic1 ? fffff146h taa4ovic ? fffff148h taa4ccic0 ? fffff14ah taa4ccic1 ? fffff14ch tm0eqic0 ? fffff14eh cb0ric ? fffff150h cb0tic ? fffff152h cb1ric ? fffff154h cb1tic ? fffff156h ud0sic ? fffff158h ud0ric ? fffff15ah ud0tic ? fffff15ch ud1sic ? fffff15eh ud1ric ? fffff160h ud1tic ? fffff162h iic0ic ? fffff164h adic ? fffff166h c0erric ? fffff168h c0wupic ? fffff16ah c0recic ? fffff16ch c0trxic ?
239 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 fffff176h kric ? fffff178h wtiic ? fffff17ah wtic ? fffff17eh flic ? ? fffff180h pic8 ? fffff182h pic9 ? fffff184h pic10 ? fffff190h ud2sic ? fffff192h ud2ric ? fffff194h ud2tic ? address register v850es/fe3-l/ v850es/ff3-l v850es/fg3-l
240 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 5.3.5 imrm - interrupt mask registers these registers set the interrupt mask state for the maskable interrupts. the xxmkn bit of the imrm registers is equivalent to the xxmkn bit of the xxicn register.  16 bit imrm registers are accessible through ? 16 bit imrm via the given
and can be read/written in 16-bit units ? 8 bit imrml = imrm[7:0] registers via the given
and can be read/written in 8- and 1-bit units ? 8 bit imrmh = imrm[15:8] registers via
+ 1 and can be read/ written in 8- and 1-bit units  8 bit imrm registers are accessible through ? 8 bit imrm or imrml registers via the given
and can be read/written in 8- and 1-bit units caution 1. mask bits without function, indicated with ?1?, must not be altered. make sure to set them ?1? when writing to the register. 2. the device file defines the xxmkn bit of the xxicn register as a reserved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). xx: identification name of each peripheral unit (see the note in ?xxicn - maskable interrupt control registers? on page 237 (1) imr0 - interrupt mask register 0 (2) imr1 - interrupt mask register 1 bit position bit name function 15 to 0 xxmkn interrupt mask flag. 0: interrupt servicing enabled 1: interrupt servicing disabled (pending) 15 14 13 12 11 10 9 8 address initial value imr0 taa0ovmk 1 1 1 1 1 pmk7 pmk6 fffff100h ffffh 76543210 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvihmk lvilmk 15 14 13 12 11 10 9 8 address initial value imr1 cb0rmk tm0eqmk0 taa4ccmk1 taa4ccmk0 taa4ovmk taa3ccmk1 taa3ccmk0 taa3ovmk fffff102h ffffh 76543210 taa2ccmk1 taa2ccmk0 taa2ovmk taa1ccmk1 taa1ccmk0 taa1ovmk taa0ccmk1 taa0ccmk0
241 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 (3) imr2 - interrupt mask register 2 (4) imr3 - interrupt mask register 3  v850es/fe3-l  v850es/ff3-l  v850es/fg3-l (5) mr4 - interrupt mask register 4  v850es/fg3-l 15 14 13 12 11 10 9 8 address initial value imr2 0 c0trxmk c0recmk c0wupmk c0errmk admk iic0mk ud1tmk fffff104h ffffh 76543210 ud1rmk ud1smk ud0tmk ud0rmk ud0smk cb1tmk cb1rmk cb0tmk 15 14 13 12 11 10 9 8 address initial value imr3 11111111 fffff106h ffffh 76543210 flmk 1 wtmk wtimk krmk 1 1 1 15 14 13 12 11 10 9 8 address initial value imr3 1 1 1 1 1 pmk10 pmk9 pmk8 fffff106h ffffh 76543210 flmk 1 wtmk wtimk krmk 1 1 1 15 14 13 12 11 10 9 8 address initial value imr4 11111111 fffff108h ffffh 76543210 1 1 1 1 1 ud2tmk ud2rmk ud2smk
242 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 5.3.6 ispr - in-service priority register this register holds the priority level of the maskable interrupt currently acknowledged. when an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. note n = 0 to 7 (priority level) caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) state, the value of the ispr register after the bits of the register have been set by acknowledging the interrupt may be read. to accurately read the value of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di). 76543210address initial value ispr ispr7 ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 fffff1fah 00h bit position bit name function 7 to 0 ispr7 to ispr0 indicates priority of interrupt currently acknowledged 0: interrupt request with priority n not acknowledged 1: interrupt request with priority n acknowledged
243 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 5.3.7 maskable interrupt status flag (id) the id flag is bit 5 of the psw and this controls the maskable interrupt?s operating state, and stores control information regarding enabling or disabling of interrupt requests. 5.3.8 external maskable interrupts this microcontroller provides maskable external interrupts intpn with the following features:  analog input filter (refer to ?analog filtered inputs? on page 126 )  digital input filter for intp3 (refer to ?digitally filtered inputs? on page 127 )  interrupt detection selectable for each interrupt input: ? rising edge ? falling edge ? both edges: rising and falling edge for configuration of the external interrupt events refer to ?external interrupts edge detection configuration? on page 244 . 31 876543210initial value psw 0 00000000000000000000000 np ep id sat cy ov s z 00000020h bit position bit name function 5id indicates whether maskable interrupt processing is enabled or disabled. 0: maskable interrupt request acknowledgement enabled 1: maskable interrupt request acknowledgement disabled (pending) this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing to psw. non-maskable interrupt requests and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during the acknowledgement disabled period (id = 1) is acknowledged when the pifn bit of picn register is set to 1, and the id flag is reset to 0.
244 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 5.4 external interrupts edge detection configuration the microcontroller provides the maskable external interrupts intpn and one non-maskable interrupt (nmi). intpn and nmi can be configured to generate interrupts upon rising, falling or both edges. two register sets are provided to specify edges and levels for each external interrupt. intrm the intrm registers specify the rising edge for edge detection of corresponding external interrupt signals. this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. intfm the intfm registers specify the falling edge for edge detection of corresponding external interrupt signals. this register can be read/written in 8-bit and 1-bit units. 16-bit registers can also be read/written in 16-bit units. caution when the function of the dedicated pin is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, first clear intrm.intrmk / intfm.intfmk (k = 0 to 15) to 0, and then set the port mode. (1) intr0/intf0 - external interrupt edge specification register 0 bit position bit name function 15 to 0 intrm[15:0] specifies the edge detection for external interrupt signals 0: no detection at rising edge 1: detection at rising edge bit position bit name function 15 to 0 intfm[15:0] specifies the edge detection for external interrupt signals 0: no detection at falling edge 1: detection at falling edge 76543210address initial value intr0 0 intr06 intr05 intr04 intr03 intr02 0 0 ffff fc20h 00h intp3 intp2 intp1 intp0 nmi 76543210address initial value intf0 0 intf06 intf05 intf04 intf03 intf02 0 0 ffff fc00h 00h intp3 intp2 intp1 intp0 nmi
245 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 (2) intr1/intf1 - external interrupt edge specification register 1  v850es/fg3-l (3) intr3/intf3 - external interrupt edge specification register 3  v850es/fe3-l  v850es/ff3-l  v850es/fg3-l 76543210address initial value intr1000000intr11intr10ffff fc22h00h intp10 intp9 76543210address initial value intf1000000intf11intf10ffff fc02h00h intp10 intp9 76543210address initial value intr3l 0 0 0 0 0 0 intr31 0 ffff fc26h 0000h intp7 76543210address initial value intf3l 0 0 0 0 0 0 intf31 0 ffff fc06h 0000h intp7 15 14 13 12 11 10 9 8 address initial value intr3 a a) both bytes of this 16-bit register can also be accessed bytewise with ? intr3l = intr3[7:0] under the address ffff fc26h ? intr3h = intr3[15:8] under the address ffff fc27h 0 0 0 0 0 0 intr39 0 ffff fc26h 0000h intp8 76543210 000000intr310 intp7 15 14 13 12 11 10 9 8 address initial value intf3 a 0 0 0 0 0 0 intf39 0 ffff fc06h 0000h intp8 76543210 000000intf310 intp7
246 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 a) both bytes of this 16-bit register can also be accessed bytewise with ? intf3l = intf3[7:0] under the address ffff fc06h ? intf3h = intf3[15:8] under the address ffff fc07h
247 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 5.5 software exception a software exception is generated when the cpu executes the trap instruction, and can be always acknowledged. 5.5.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine: 1. saves the restored pc to eipc. 2. saves the current psw to eipsw. 3. writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). 4. sets the ep and id bits of the psw. 5. sets the handler address (00000040h or 00000050h) corresponding to the software exception to the pc, and transfers control. figure 5-10 illustrates the processing of a software exception. figure 5-10 software exception processing note trap instruction format: trap vector (the vector is a value from 0 to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 0 to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. trap in s tr u ction eipc eipsw ecr.eicc psw.ep psw.id pc re s tored pc psw exception code 1 1 h a ndler a ddre ss cpu proce ss ing exception proce ss ing note
248 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 5.5.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instruction, the cpu carries out the following processing and shifts control to the restored pc?s address. 1. loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. 2. transfers control to the address of the restored pc and psw. figure 5-11 illustrates the processing of the reti instruction. figure 5-11 reti instruction processing caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. note the solid lines show the cpu processing flow. psw.ep reti in s tr u ction pc psw eipc eipsw psw.np origin a l proce ss ing re s tored pc psw fepc fepsw 1 1 0 0
249 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 5.5.3 exception status flag (ep) the ep flag is bit 6 of psw, and is a status flag used to indicate that exception processing is in progress. it is set when an exception occurs. 5.6 exception trap an exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. for this microcontroller, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 5.6.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 23 to 26) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an instruction applicable to this illegal instruction is executed. note : arbitrary (1) operation if an exception trap occurs, the cpu performs the following processing, and transfers control to the handler routine: 1. saves the restored pc to dbpc. 2. saves the current psw to dbpsw. 3. sets the np, ep, and id bits of the psw. 4. sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. figure 5-12 illustrates the processing of the exception trap. 31 876543210initial value psw 0 00000000000000000000000 np ep id sat cy ov s z 00000020h bit position bit name function 6ep shows that exception processing is in progress. 0: exception processing not in progress. 1: exception processing in progress. 1 5 1 1 1 0 54 0 3 1 2 7 2 6 2 3 2 2 1 6 111111 0111 0 to 1111
250 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 figure 5-12 exception trap processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. 1. loads the restored pc and psw from dbpc and dbpsw. 2. transfers control to the address indicated by the restored pc and psw. figure 5-13 illustrates the restore processing from an exception trap. figure 5-13 restore processing from exception trap note the dbpc and dbpsw registers can be accessed only when the dbtrap instruction is executed. exception tr a p (ilgop) occ u r s dbpc dbpsw psw.np psw.ep psw.id pc re s tored pc psw 1 1 1 00000060h exception proce ss ing cpu proce ss ing dbret in s tr u ction pc psw dbpc dbpsw j u mp to a ddre ss of re s tored pc
251 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 5.6.2 debug trap the debug trap is an exception that can be acknowledged every time and is generated by execution of the dbtrap instruction. when the debug trap is generated, the cpu performs the following processing. (1) operation when the debug trap is generated, the cpu performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode. 1. saves the restored pc to dbpc. 2. saves the current psw to dbpsw. 3. sets the np, ep and id bits of the psw. 4. sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. figure 5-14 illustrates the processing of the debug trap. figure 5-14 debug trap processing (2) restore recovery from a debug trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. 1. loads the restored pc and psw from dbpc and dbpsw. 2. transfers control to the address indicated by the restored pc and psw. dbtrap in s tr u ction dbpc dbpsw psw.np psw.ep psw.id pc re s tored pc psw 1 1 1 00000060h exception proce ss ing cpu proce ss ing
252 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 figure 5-15 illustrates the restore processing from a debug trap. figure 5-15 restore processing from debug trap 5.7 multiple interrupt processing control multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first. if there is an interrupt request with a lower priority level than the interrupt request currently being processed, that interrupt request is held pending. maskable interrupt multiple processing control is executed when an interrupt has an enable status (id = 0). thus, if multiple interrupts are executed, it is necessary to have an interrupt enable status (id = 0) even for an interrupt processing routine. if a maskable interrupt enable or a software exception is generated in a maskable interrupt or software exception service program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. dbret in s tr u ction pc psw dbpc dbpsw j u mp to a ddre ss of re s tored pc
253 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 (1) acknowledgment of maskable interrupts in service program service program of maskable interrupt or exception (2) generation of exception in service program service program of maskable interrupt or exception the priority order for multiple interrupt processing control has 8 levels, from 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. setting of the priority order level is done using the pprn0 to pprn2 bits of the interrupt control request register (plcn), which is provided for each maskable interrupt request. after system reset, an interrupt request is masked by the pmkn bit and the priority order is set to level 7 by the pprn0 to pprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) ... ... eipc saved to memory or register eipsw saved to memory or register ei instruction (interrupt acknowledgment enabled) ... ... ... di instruction (interrupt acknowledgment disabled) saved value restored to eipsw saved value restored to eipc reti instruction maskable interrupt acknowledgment ... ... eipc saved to memory or register eipsw saved to memory or register ... trap instruction ... saved value restored to eipsw saved value restored to eipc reti instruction exception such as trap instruction acknowledged.
254 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00 interrupt processing that has been suspended as a result of multiple processing control is resumed after the processing of the higher priority interrupt has been completed and the reti instruction has been executed. a pending interrupt request is acknowledged after the current interrupt processing has been completed and the reti instruction has been executed. caution in a non-maskable interrupt processing routine (time until the reti instruction is executed), maskable interrupts are suspended and not acknowledged. 5.8 interrupt response time the following table describes the interrupt response time (from interrupt generation to start of interrupt processing). except in the following cases, the interrupt response time is a minimum of 5 clocks.  during software or hardware stop mode  when there are two or more successive interrupt request non-sampling instructions (see ?periods in which interrupts are not acknowledged? on page 255 ).  when the interrupt control register is accessed figure 5-16 pipeline operation at interrupt request acknowledgment (outline) note int1 to int4: interrupt acknowledgement processing ifx: invalid instruction fetch idx: invalid instruction decode note if the same interrupt occurs during the interrupt acknowledge time of 5 cycles, this new interrupt will discarded. the next interrupt of the same source will only be registered after these 5 cycles. if id ex vbclk (inp u t) in s tr u ction 1 in s tr u ction 2 interr u pt a cknowledgement oper a tion in s tr u ction (fir s t in s tr u ction of interr u pt s ervice ro u tine) interr u pt re qu e s t if id ex mem wb ifx idx int1 int2 int 3 int4 5 s y s tem clock s
255 interrupt controller (intc) chapter 5 user?s manual u18743ee1v2um00 5.9 periods in which interrupts are not acknowledged an interrupt is acknowledged while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt non-sample instruction and the next instruction. the interrupt request non-sampling instructions are as follows:  ei instruction  di instruction  ldsr reg2, 0x5 instruction (for psw)  the store instruction for the interrupt control register (plcn), in-service priority register (ispr), and command register (prcmd). the store instruction for the following registers and set1, not1, clr1 instruction.  interrupt registers: interrupt control register (xxicn), interrupt mask registers 0 to 7 (imr0 to imr7)  in-service priority register (ispr)  command register (prcmd)  power save control register (psc)  on-chip debug mode register (ocdm) peripheral emulation register 1 (pemu1) interrupt response time (internal system clocks) condition internal interrupt external interrupt minimum 4 4 + analog delay time the following cases are exceptions:  in idle/software stop mode  external bit access  two or more interrupt request non- sample instructions are executed  access to interrupt control register maximum 6 (in case of latency = 2) 7 (in case of latency = 3) 6 + analog delay time (in case of latency = 2) 7 + analog delay time (in case of latency = 3)
256 chapter 5 interrupt controller (intc) user?s manual u18743ee1v2um00
257 user?s manual u18743ee1v2um00 chapter 6 key interrupt function 6.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the key return mode register (krm). figure 6-1 key return block diagram table 6-1 assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
258 chapter 6 key interrupt function user?s manual u18743ee1v2um00 6.2 control register (1) krm - key return mode register the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. access this register can be read/written in 8-bit or 1-bit units. address ffff f300 h . initial value 00 h . this register is cleared by any reset. caution if the krm register is changed, the interrupt request signal intkr may be generated. to prevent this, change the krm register after disabling interrupts (di), and then enable interrupts (ei) after clearing the interrupt request flag (kric.krif = 0). note for the alternate-function pin settings, see ?pin functions? on page 31 . 6.3 cautions 1. if a low level is input to any of the kr0 to kr7 pins, the intkr signal is not generated even if the falling edge of another pin is input. 2. if the krm register is changed, an interrupt request signal (intkr) may be generated. to prevent this, change the krm register after disabling interrupts (di), and then enable interrupts (ei) after clearing the interrupt request flag (kric.krif bit) to 0. 3. to use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation with the krm register. to switch from the key return pin to the port pin, disable the operation with the krm register and then set the port pin. 4. before writing a new value to the krm register write a value of 0x00 to the krm register first. 76543 2 1 0 krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 r/w r/w r/w r/w r/w r/w r/w r/w table 6-2 lockr register contents bit name function krmn control of key return mode: 0: does not detect key return signal. 1: detects key return signal.
259 user?s manual u18743ee1v2um00 chapter 7 flash memory the following v850es/fx3-l devices are equipped with internal flash memory : the code flash memory is attached to the dedicated fetch bus interface of the v850 cpu core. it is used for non-volatile storage of program code and constant data. flash memory is commonly used in the following development environments and applications:  for altering software after solder-mounting of the microcontroller on the target system.  for differentiating software in small-scale production of various models.  for data adjustment when starting mass production.  for facilitating inventory management.  for updating software after shipment. the flash memory can be written in different ways:  by a flash programmer equipped with a suitable adapter (off-board write)  mounted on the target board by connecting a dedicated flash programmer to the target system (on-board write)  by the microcontroller?s application software (self-programming) additionally a flash memory address space is provided to hold various configuration settings, called option bytes. via the option bytes start-up configurations can be set for e.g. the clock generator and the watchdog timer. the option bytes can be written by use of an external flash programmer and in self-programming mode. product device code flash size v850es/fe3-l pd70f3610 64 kb pd70f3611 96 kb pd70f3612 128 kb pd70f3613 192 kb pd70f3614 256 kb v850es/ff3-l pd70f3615 64 kb pd70f3616 96 kb pd70f3617 128 kb pd70f3618 192 kb pd70f3619 256 kb v850es/fg3-l pd70f3620 128 kb pd70f3621 192 kb pd70f3622 256 kb
260 chapter 7 flash memory user?s manual u18743ee1v2um00 7.1 code flash memory overview 7.1.1 code flash memory features  4-byte/1 cpu clock access during instruction fetch  all-blocks or multiple blocks batch erase or single block erase  erase/write with single power supply  communication with dedicated flash programmer via various serial interfaces  on-board and off-board programming  flash memory programming by self-programming
261 flash memory chapter 7 user?s manual u18743ee1v2um00 7.1.2 code flash memory mapping the microcontroller?s internal code flash memory area is divided into blocks of 2 kb respectively 4 kb blocks and can be programmed/erased in block units. all or some of the blocks can also be erased at once. following figures list the block structures and address assignments for all v850es/fx3-l devices with code flash memory. additional information comprise:  boot swap cluster size configurable size of boot cluster for secure self-programming, refer to ?secure self-programming (boot cluster swapping)? on page 279 .  interleave interleave configuration of the flash memory blocks.  cpu branch latency number of additional cpu clock cycles during instruction fetches of non- linear code. the cpu branch latency may be configurable by the latency control bit of the option byte at address 0000 007b h . figure 7-1 code flash memory configuration for v850es/fx3-l devices. ... block 127 (2 kb) 0003 ffffh address 0003 f800h ... block 95(2 kb) 0002 ffffh 0002 0800h ... block 63(2 kb) 0001 ffffh 0001 f800h ... block 47(2 kb) 0001 7fffh 0001 7800h ... ... block 31 (2 kb) 0000 ffffh 0000 f800h ... block 0 (2 kb) block 0 (2 kb) block 0 (2 kb) block 0 (2 kb) block 0 (2 kb) 0000 07ffh 0000 0000h 64 kb 96 kb 128 192 kb 256 kb code flash size 8/16/32 kb 8/16/32/64 kb boot swap cluster sizes pd70f3610 pd70f3615 pd70f3611 pd70f3616 pd70f3612 pd70f3617 pd70f3620 pd70f3613 pd70f3618 pd70f3621 pd70f3614 pd70f3619 pd70f3622 products
262 chapter 7 flash memory user?s manual u18743ee1v2um00 7.1.3 code flash memory functional outline serial programming the internal flash memory of the microcontroller can be rewritten by using the rewrite function of a dedicated flash programmer, regardless of whether the microcontroller has already been mounted on the target system or the device is not mounted (off-board/on-board programming). since there is no functional difference between on-board and off-board programming by an external flash programmer, both will be gathered as ?serial programming? - in contrast ?to self-programming?. self-programming the self-programming facility, which facilitates rewriting of the flash memory by the user program, is ideal for program updates after production and shipment, since no additional programming equipment is required. during self- programming some software services as well as interrupt serving can still be in operation, e.g to sustain communication with other devices. while the self-programming mode can be initiated from the normal operation mode the external flash programmer mode is entered immediately after release of a system reset. refer to ?flash memory programming control? on page 271 for details on how to enter normal operation or serial flash programming mode. extra area the flash memory contains an extra area, used to store the settings of security and protection functions, the variable reset vector and other flash relevant information. the extra area is not mapped into the cpu?s address space, thus is not directly accessible by the user?s program. the extra area?s settings can only be read and modified by an external programmer or by self-programming. boot swap a boot swap function makes safe re-programming of the flash memory possible and is used to maintain an operable software version, even if re- programming fails for any reason, e.g. in a power fail situation. for further information concerning boot swapping refer to ?secure self- programming (boot cluster swapping)? on page 279 . protection a set of protection flags can be specified during flash memory programming to prohibit access the flash memory in different ways, implying read-out, rewrite and erase protections. by these means the code flash memory can be protected against read-out and rewrite of the flash memory content by unauthorized persons. for further information concerning data protection refer to ?data protection and security? on page 289 . variable reset vector the variable reset vector function allows flexible assignment of the application program start by redefinition of the reset vector. for further information concerning the variable reset vector refer to ?variable reset vector? on page 284 .
263 flash memory chapter 7 user?s manual u18743ee1v2um00 table 7-2 on page 264 summarizes the functions used to modify flash memory content. table 7-1 flash memory write methods environment interface outline operation mode serial programming serial i/f (uart, csi) flash memory programming is done by an external flash programmer. the device may be mounted on the target system (on- board) or unmounted (off-board) by using a suitable programming adapter board. in either case the communication between the device and the flash progammer is using a serial interface. for details refer to ?flash programming with flash programmer? on page 266 . flash memory programming mode self- programming self-programming library flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of off-board/on-board programming. the self-programming library provides all necessary functions to be called by the application software. for details refer to ?code flash self-programming? on page 277 . normal operation mode
264 chapter 7 flash memory user?s manual u18743ee1v2um00 the following table lists the available flash memory protection functions. for details refer to ?data protection and security? on page 289 . table 7-2 basic functions for flash memory modifications function functional outline support ( : supported, : not supported) serial programming self-programming block erasure the contents of specified memory blocks are erased. ? multiple block erasure the contents of the specified successive multiple blocks are erased. ? chip erasure the contents of the entire memory area is erased all at once. the extra area - except the boot block cluster protection flag - is also erased. x a a) in self-programming mode all blocks can be specified to be erased at once by block erasure. note that the extra area is not erased in this case. write writing to specified addresses, and a verify check to see if write level is secured are performed. ? verify data read from the flash memory is compared with data transferred from the flash programmer. x b b) can be carried out by the user?s program. checksum microcontroller internally calculated checksum over the entire flash memory content is compared with the checksum calculated by the serial programmer x blank check the erasure status of the entire memory is checked. ? protection settings following functions can be prohibited:  chip erase  block erase  write  read  rewriting of the boot block cluster ? c c) except protection against rewriting of the boot block cluster all other protections have no effect in self-program- ming mode. protection settings can be activated in self-programming mode. already activate protection settings can not be deactivated. table 7-3 protection functions function functional outline applicable ( : applies, : doesn?t apply) serial programming self-programming chip erase command prohibit erasure of the entire flash (including the extra area a ) or single blocks impossible. ? block erase command prohibit erasure of single blocks impossible. ? program command prohibit erasure and rewrite of single blocks impossible. ? read command prohibit read-out of any flash content impossible. ? rewriting boot area prohibit erasure (by block or chip erase) or writing of the boot block cluster impossible. ?
265 flash memory chapter 7 user?s manual u18743ee1v2um00 7.1.4 code flash memory erasure and rewrite erasure according to its block structure the flash memory can be erased in two different modes.  all-blocks batch erasure (chip erase) all blocks are erased all together.  block erasure each 2 kb flash memory block can be erased separately. in self-programming mode any number of contiguous flash memory blocks can be erased all together. rewrite in self- and serial programming mode it is possible to rewrite the flash memory in smaller units than one block. once a complete block has been erased it can be rewritten in units of 8 bytes. each unit can be rewritten only once after erasure of the complete block. a) the boot block cluster protection flag is not erased.
266 chapter 7 flash memory user?s manual u18743ee1v2um00 7.2 flash programming with flash programmer a dedicated flash programmer can be used for external writing of the flash memory.  on-board programming the contents of the flash memory can be rewritten with the microcontroller mounted on the target system. mount a connector that connects the flash programmer on the target system.  off-board programming the flash memory of the microcontroller can be written before the device is mounted on the target system, by using a dedicated programming adapter. 7.2.1 programming environment the necessary environment to write a program to the flash memory of the microcontroller is shown below. figure 7-2 environment to write program to flash memory a host machine is required for controlling the flash programmer. following microcontroller serial interfaces can be used as the interface between the flash programmer and the microcontroller:  asynchroneous serial interface uart  clocked serial interface csi  serial debug interface n-wire if a csi interface is used with handshake, the flash programmer?s hs signal is connected to a certain v850 port, in the following generally named as hsport. the port used as hsport for this product is given in table 7-6 . flash memory programming off-board requires a dedicated programming adapter. in this chapter the terms uart and csi may be used generically for the dedicated interface types and channels the microcontroller provides. uart and csi signal names are used accordingly. host machine rs-232-c usb flash programmer pg-fp4 (f la s h pro 4 v ) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve v850 microcontroller note: flmd1 connection may be replaced by a pull-down resistor on the board flmd0 (flmd1 note ) v dd v ss reset uart/csi n-wire hs
267 flash memory chapter 7 user?s manual u18743ee1v2um00 7.2.2 communication mode the communication between the flash programmer and the microcontroller utilizes the asynchronous serial interface uart or optionally the synchronous serial interface csi. for programming via the synchronous serial interface csi without handshake and with handshake modes are supported. in the latter mode the port pin hsport is used for the programmer?s handshake signal hs. (1) uart the external flash programmer offers various choices of available baud rates. figure 7-3 communication with flash programmer via uart (2) csi without handshake the external flash programmer offers various choices of available clock rates. figure 7-4 communication with flash programmer via csi without handshake the flash programmer outputs a transfer clock and the microcontroller operates as a slave. flash programmer v dd v ss reset txd rxd flmd0 (flmd1 note ) flmd0 (flmd1 note ) v dd gnd reset rxd txd pg-fp4 ( flas hp ro 4) cxxxxxx bxxxxx axxxx xxx y y y xx xx x x x xx x x x x x x xx xx y y y y statve v850 microcontroller note: flmd1 connection may be replaced by a pull-down resistor on the board flash programmer flmd0 (flmd1 note ) v dd v ss reset so si sck flmd0 (flmd1 note ) v dd gnd reset si so sck pg-fp4 (f la sh pr o 4) cxxxxxx bxxxxx axxxx x x x y y y x xx xx xx xxx x xx x x x xx x y yy y statve v850 microcontroller note: flmd1 connection may be replaced by a pull-down resistor on the board
268 chapter 7 flash memory user?s manual u18743ee1v2um00 (3) csi with handshake (csi + hs) the external flash programmer offers various choices of available clock rates. figure 7-5 communication with flash programmer via csi with handshake the flash programmer outputs a transfer clock and the microcontroller operates as a slave. (4) n-wire serial clock dck: up to 1 mhz figure 7-6 communication with flash programmer via n-wire flash programmer v dd v ss reset so si sck hsport v dd flmd0 (flmd1 note ) flmd0 (flmd1 note ) gnd reset si so sck hs pg-fp4 ( f lash p ro4 ) cxxxxxx bxxxxx axxxx x xx y yy xx x x x xx xx x x x xx x x x x x y y y y statve v850 microcontroller note: flmd1 connection may be replaced by a pull-down resistor on the board p ro 4 ) x xx y yy xx xx x xx xx x x x xx x x x x x y y y y flash programmer pg-fp4 ( f lash cxxxxxx bxxxxx axxxx s tat v e v dd v dd flmd1 flmd0 v ss gnd ddo s i/rxd ddi s o/txd dck s ck flmd0 dm s dr s t re s et v850 microcontroller
269 flash memory chapter 7 user?s manual u18743ee1v2um00 7.2.3 pin connection with flash programmer pg-fp4 a connector must be mounted on the target system to connect the flash programmer for on-board writing. in addition, functions to switch between the normal operation mode and flash memory programming mode and to control the microcontroller?s reset pin must be provided on the board. when the flash memory programming mode is set, all the pins not used for flash memory programming are in the same status as immediately after reset. if the pg-fp4 is used as the flash programmer, it generates the signals listed in ta b l e 7 - 4 for the microcontroller. for details, refer to the pg-fp4 user?s manual (u15260e). note : must be connected. : does not have to be connected. table 7-4 signals generated by flash programmer pg-fp4 pg-fp4 controller connection signal name i/o pin function pin name uart csi csi + hs n-wire flmd0 output write enable/disable flmd0 ?? flmd1 output write enable/disable flmd1 v dd i/o v dd voltage generation/ voltage monitor v dd ?? gnd ? ground v ss ?? clk output clock output to the controller x1 reset output reset signal reset ?? si/rxd input receive signal so/txd ?? so/txd output transmit signal si/rxd ?? sck output transfer clock sck ? hs input handshake signal for csi + hs communication hsport v dd1 v ss1
270 chapter 7 flash memory user?s manual u18743ee1v2um00 table 7-5 wiring of v850es/fx3-l flash writing adapters for csib flash programmer (fg-fp4) connection pin name of fa board pin uarta0 csib0 + hs csib0 n-wire signal name i/o pin function pin name pin name pin name pin name si/rxd i receive signal si txda0 sob0 so/txd o transmit signal so rxda0 sib0 sck o transfer clock sck not needed sckb0 clk o clock to v850 microcontroller x1 leave open x2 leave open reset o reset signal reset reset flmd0 i write voltage flmd0 flmd0 flmd1 i write voltage flmd1 flmd1 hs i handshake signal for csi + hs reserve/ hs not needed pcm0 not needed not needed vdd ? vdd voltage generation/ voltage monitor vdd v dd bv dd ev dd av ref0 gnd ? ground gnd v ss bv ss ev ss av ss table 7-6 v850es/fx3-l pin numbers for serial programming pin name port v850es/fe3-l pin nr. v850es/ff3-l pin nr. v850es/fg3-l pin nr. txdd0 p30 22 22 25 rxdd0 p31 23 23 26 sib0 p40 19 19 22 sob0 p41 20 20 23 sckb0 p42 21 21 24 reset ?91414 flmd0 ? 3 8 8 flmd1 pdl5 52 61 76 pcm0 pcm0 45 49 61 drst p05 17 17 20 ddi p52 30 34 39 ddo p53 31 35 40 dck p54 34 36 41 dms p55 35 37 42
271 flash memory chapter 7 user?s manual u18743ee1v2um00 7.2.4 flash memory programming control the procedure to program the flash memory is illustrated below. figure 7-7 flash memory programming procedure note: a reset pulse is required to initiate the selection of the flash programming mode. reset/flmd0 pulse supply
272 chapter 7 flash memory user?s manual u18743ee1v2um00 (1) operation mode control to rewrite the contents of the flash memory by using the flash programmer, set the microcontroller in the flash memory programming mode. to set this mode, set the flmd0 and flmd1 pins as shown in ta b l e 7 - 7 o n page 272 and release reset . in the normal operation mode, vss is input to the flmd0 pin. a pull-down resistor at the flmd0 pin ensures normal operation mode if no flash programmer is connected. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. additionally the flmd1 pin has to hold vss level. an example of connection of the flmd0 and flmd1 pins is shown below. flmd1 can be connected to ground via a resistor. alternatively the flmd1 pin may also be connected directly to the flmd1 signal of the flash programmer. figure 7-8 example of connection to flash programmer pg-fp4 once started in normal operation mode (flmd0 = 0), flmd0 pin is used for enabling self-programming. refer also to 7.3 on page 277 . table 7-7 operation mode setting pins operation mode flmd0 flmd1 v ss don?t care normal operation mode v dd v ss flash programming mode v dd setting prohibited v850 pg-fp4 flmd0 flmd1 flmd0 flmd1 v850 pg-fp4 flmd0 flmd1 flmd0 flmd1
273 flash memory chapter 7 user?s manual u18743ee1v2um00 (2) potential conflicts with on-board signal connections serial i/o signals if other devices are connected to the serial interface pins in use for flash memory programming in on-board programming mode take care that the concerned signals do not conflict with the signals of the flash programmer and the microcontroller. output pins of the other devices must be isolated or set in high impedance state. ensure that the other devices do not malfunction because of flash programmer signals. figure 7-9 potential conflicts with serial interfaces signals reset pay attention in particular if the flash programmer?s reset signal is connected also to an on-board reset generation circuit. the reset output of the reset generator may ruin the flash programming process and may need to be isolated or disabled. figure 7-10 potential conflict with reset v850 c output input flash programm er other device input flash programm er other device input v850 c v850 c input flash programm er other device input isolate or disable isolate or disable isolate or disable or hi-z flash programm er reset generator v850 c isolate or disable reset reset
274 chapter 7 flash memory user?s manual u18743ee1v2um00 ports the v850 port pins adopts following status during serial programming: ports used for programming are configured as uart respectively csi pins. all other pins remain in their default state after reset release. in case the default state after reset of the pins not used for programming is inport port or high -impedance output port, pay attention to other devices connected to these pins. if these devices require defined levels at the pins, the ports may have to be connected to v dd or v ss via a resistors. oscillators connect all oscillator pins in the same way as in the normal operation mode. drst during flash memory programming, input a low level to drst or leave it open. do not input a high level. power supply supply the same power to all power supply pins, including reference voltages, power regulator pins, etc., as in the normal operation mode.
275 flash memory chapter 7 user?s manual u18743ee1v2um00 (3) selection of the communication mode the communication interface is chosen by applying a specified number of pulses to the flmd0 pin after reset release. note that this is handled by the flash programmer. figure 7-11 on page 275 gives an example how the uart is established for the communication between the flash programmer and the microcontroller. figure 7-11 selection of communication mode note the number of clocks to be inserted differs depending on the chosen communication mode. for details, refer to table 7-8 on page 275 . when uart has been selected after reception of the flmd0 pulses with 9600 bps, the flash programmer changes the baud rate according to the user?s choice via the flash programmer?s user interface. at first the programmer sends two 00 h bytes, which are used by the microcontoller to measure the baud rate and to set up it?s own baud rate accordingly. table 7-8 flmd0 pulses for communication mode setting flmd0 pulses communication mode remarks 0 uart communication rate: 9600 bps (after reset), lsb first 8 csi v850es/fx3-l performs slave operation, msb first 11 csi + hs v850es/fx3-l performs slave operation, msb first other ? setting prohibited v dd v dd r eset (input) f lmd1 (input) f lmd0 (input) rxd (input) txd (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released
276 chapter 7 flash memory user?s manual u18743ee1v2um00 (4) communication commands the flash programmer sends commands to the microcontroller. depending on the commands, the microcontroller returns status information or the requested data. figure 7-12 communication commands exchange the following table lists the flash memory control commands of the microcontroller. all these commands are issued by the flash programmer, and the microcontroller performs the corresponding processing. flash programmer command status data pg-fp4 (f la sh p r o 4 ) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x xx x x x x x x y y y y statve v850 microcontroller table 7-9 flash memory control commands classification command name support function csib csib + hs uartd blank check block blank check command ?? checks erasure status of entire memory. erase chip erase command ?? erases all memory contents. block erase command ?? erases memory contents of specified block. write write command ?? writes data by specifying write address and number of bytes to be written, and executes verify check. verify verify command ?? compares input data with all memory contents. system setting and control reset command ?? escapes from each status. oscillation frequency setting command ?? sets oscillation frequency. baud rate setting command ?? sets baud rate when uart is used. silicon signature command ?? reads silicon signature information. version acquisition command ?? reads version information of device. status command ? ? acquires operation status. protection setting command ?? sets protection against chip erasure, block erasure, and writing.
277 flash memory chapter 7 user?s manual u18743ee1v2um00 7.3 code flash self-programming this v850 microcontroller supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. by using this flash macro service and a self-programming library, provided by nec, the user?s program is able to rewrite the flash memory with data, transferred in advance to the internal ram. thus the user program can be upgraded and constant data can be rewritten in the field. figure 7-13 concept of self-programming during self-programming access to the flash memory is not possible. thus program execution is only possible by instruction fetching from internal ram. consequently the instructions of user re-programming software routines, which shall remain in operation during the self-programming procedure, must be copied from the flash memory to the internal ram prior to activating the self- programming. since interrupt processing by using the interrupt vectors in the flash memory is also impossible during self-programming, a special feature is provided to re-route interrupt acknowledges to the internal ram (refer to ?interrupt handling during flash self-programming? on page 283 ). it is recommended to refer to the application note ?self-programming? (document nr. u16929ee) for comprehensive information concerning flash self-programming. this document explains also the functions of the self- programming library. the latest version of this document and the library can be loaded via the url http://www.eu.necel.com user?s re-programming routine self-programming library flash macro service flash memory flash function execution flash information erase, write internal ram
278 chapter 7 flash memory user?s manual u18743ee1v2um00 7.3.1 self-programming enable the self-programming functions can be started out of the normal user mode of the microcontroller. the microcontroller must be set into self-programming mode via the self- programming library. for security reasons writing and erasing of the flash memory must be additionally permitted by setting the external flmd0 pin to high level. note that flmd0 holds low level in normal operation mode after reset release. this requires some external components or wiring, e.g. connecting an output port to flmd0. figure 7-14 self-programming enable when self-programming has been completed, the voltage on the flmd0 pin must be returned to vss. 7.3.2 self-programmi ng library functions code flash memory self-programming by the user?s program is supported by the self-programming library. this library provides a set of c function calls to carry out basic functions like  blank-check/erase/rewrite/verify of the flash  boot cluster swapping, including definition of boot block clusters  definition of the variable reset vector  setting of protection flags  obtain various information concerning the code flash memory detailed information how to use the library functions is given in the application note: ?self-programming library for embedded single voltage flash? (document no. u16929ee). the up-to-date version of the self-programming library and the above mentioned application note can be obtained from http://www.eu.necel.com . r eset signal f lmd0 pin v dd 0 v v dd 0 v self-programming write/erase permitted normal operation mode normal operation mode
279 flash memory chapter 7 user?s manual u18743ee1v2um00 7.3.3 secure self-programmi ng (boot cluster swapping) the v850 flash microcontrollers support a mechanism to swap a cluster of code flash memory blocks, starting from address 0000 0000 h , with another cluster of the same size, located immediately above the first one. caution boot cluster swapping is only supported, if the variable reset vector remains in its default state 0000 0000 h . if the reset vector is changed to other values, boot cluster swapping is not possible. boot swap cluster a group of boot blocks to be swapped. the cluster of blocks starting at address 0000 0000 h is named active boot swap cluster, since it contains the entry point of the user?s program at the default reset vector 0000 0000 h . boot swap flag which of the two clusters is the active boot block cluster is controlled by the boot swap flag, that can be defined during flash programming via the self- programming library. the boot swap flag is stored in the flash memory extra area. figure 7-15 on page 279 shows an example of the boot block swapping function with a cluster size of 4 flash memory blocks. after inverting the boot_flag - it becomes not(boot_flag) - blocks 4 to 7 become the active boot block cluster. thus after next reset release the user?s program starts from the new boot swap cluster. figure 7-15 boot swap cluster swapping function block 0 block 3 block 2 block 1 block 4 block 7 block 6 block 5 last block block 8 inactive boot swap cluster block 0 block 3 block 2 block 1 block 4 block 7 block 6 block 5 last block block 8 boot_flag not(boot_flag) 0000 0000h active boot swap cluster
280 chapter 7 flash memory user?s manual u18743ee1v2um00 secure self- programming the boot cluster swapping function enables secure self-programming. in case the boot code shall be rewritten, the new code can be written to the inactive boot block cluster, while the boot_flag remains in its previous state. if rewriting of the boot block cluster has been completed successfully, the boot_flag can be inverted, making the new boot code active. if rewriting of the new boot code fails for any reason, e.g. power fail or unintended reset, the old boot code still remains active and rewriting can be started again. boot block cluster the boot code size itself may be smaller than the boot swap cluster size. the number of flash memory blocks, which are part of the boot code, are named boot block cluster. the number of boot blocks, which are member of the cluster, can be defined during self-programming via the self-programming library. the boot block cluster size determines the boot swap cluster size. this is automatically evaluated from the number of boot blocks, defined during self- programming. table 7-10 on page 281 shows the relation between the number of boot blocks, the boot block cluster size and the boot swap cluster. number of boot blocks the numer of boot blocks has to be defined by the user during self-programming. it determines the blocks, which are subject to the boot block cluster protection, that allows to protect the boot blocks from any erase or write process.
281 flash memory chapter 7 user?s manual u18743ee1v2um00 table 7-10 relation between boot block and boot swap cluster number of boot blocks a a) the number of boot blocks has to be defined by the user during self-programming or via the external program- mer during serial programming. devices with 2 kb blocks ( 256 kb code flash) boot block cluster boot swap cluster 00h 0000 0000h - 0000 07ffh (2 kb) 0000 0000h - 0000 1fffh (8 kb) 01h resv - 0000 0fffh (4 kb) 02h resv - 0000 17ffh (6 kb) 03h resv - 0000 1fffh (8 kb) 04h resv - 0000 27ffh (10 kb) 0000 0000h - 0000 3fffh (16 kb) ... ... 07h resv - 0000 3fffh (16 kb) 08h resv - 0000 47ffh (18 kb) 0000 0000h - 0000 7fffh (32 kb) ... ... 0fh resv - 0000 7fffh (max. 32 kb) 10h resv - 0000 87ffh (34 kb) 0000 0000h - 0000 7fffh (64 kb) ... ... 1fh resv - 0000 ffffh (64 kb) 20h resv - 0001 07ffh (66 kb) ... ... 7fh resv - 0003 ffffh (256 kb) 80h setting prohibited ... ffh
282 chapter 7 flash memory user?s manual u18743ee1v2um00 figure 7-16 on page 282 illustrates an example with following settings:  number of boot blocks: 2 (boot block cluster contains 2 blocks), thus the active boot block cluster comprises ? if boot_flag: blocks 0and 1 ? if not(boot_flag): blocks 4 and 5  active boot swap clusters comprises ? if boot_flag: blocks 0 to 3 ? if not(boot_flag): blocks 4 to 7 figure 7-16 boot cluster swapping function boot block protection to prohibit rewriting of the boot blocks, the boot block cluster protection flag can be set during flash memory programming. when this flag is set, the blocks of the active boot block cluster can neither be erased nor written. boot cluster swapping is impossible as well. note that only the blocks of the active boot block cluster are protected. in the example according to figure 7-16 on page 282 , for instance, blocks 0 and 1 would be prohibited, while blocks 2 and 3 could still be erased and written. caution once the boot block cluster protection has been activated, it can never be deactivated again. for further information concerning flash memory protection flags refer to ?data protection and security? on page 289 . block 0 block 3 block 2 block 1 block 4 block 7 block 6 block 5 last block block 8 block 0 block 3 block 2 block 1 block 4 block 7 block 6 block 5 last block block 8 boot_flag not(boot_flag) 0000 0000h active boot swap cluster inactive boot block cluster active boot block cluster inactive boot swap cluster
283 flash memory chapter 7 user?s manual u18743ee1v2um00 7.3.4 interrupt handling dur ing flash self-programming this microcontroller provides functions to maintain interrupt servicing during the self-programming procedure. since neither the interrupt vector table nor the interrupt handler routines, which are normally located in the flash memory, are accessible while self- programming is active, interrupt acknowledges have to be re-routed to non- flash memory, i.e. to the internal ram. therefore two prerequisites are necessary to enable interrupt servicing during self-programming:  the concerned interrupt handler routine needs to be copied to the internal ram. the user has to initiate this copy process.  the concerned interrupt acknowledge has to be re-routed to that handler. re-routing to the handler is done by the internal firmware. thus the user doesn?t have to care about. the internal firmware and the self-programming library provide functions to initialize and process such interrupts. the interrupt handler routines can be copied from flash to the internal ram by use of self-programming library functions. the addresses of the interrupt handler routines are set up via the self- programming library as well. note 1. note that this special interrupt handling adds some interrupt latency time. 2. special interrupt handling is done only during the flash programming environment is activated. if self-programming is deactivated, the normal interrupt vector table in the flash memory is used. all interrupt vectors are relocated to one entry point in the internal ram:  new entry point of all maskable interrupts is the 1st address of the internal ram. a handler routine must check the interrupt source. the interrupt request source can be identified via the interrupt/exception source register ecr.eicc (refer to ?system register set? on page 139 )  new entry point of all non maskable interrupts is the word address following the maskable interrupt entry, i.e. the second address of the internal ram. the interrupt request source can be identified via the interrupt/exception source register ecr.fecc (refer to ?system register set? on page 139 ). in general a jump to a special handler routine will be placed at the 1st and 2nd internal ram address, which identifies the interrupt sources and branches to the correct interrupt service routine. the function serving the interrupt needs to be compiled as an interrupt function (i.e. terminate with a reti instruction, save/restore all used registers, etc.). it is recommended to refer to the application note ?self-programming? (document nr. u16929ee) for comprehensive information concerning flash self-programming. this document explains also the functions of the self- programming library. the latest version of this document can be loaded via the url http://www.eu.necel.com
284 chapter 7 flash memory user?s manual u18743ee1v2um00 7.4 variable reset vector this microcontroller provides a facility to specify the address of the first user software instruction to be executed after reset release. by default the first user?s instruction to be executed after reset, i.e. the reset vector, is the one stored at address 0000 0000 h . during flash programming another reset vector address can be specified, the so called variable reset vector. the variable reset vector is stored in the flash memory extra area. the variable reset vector can be modified in all flash programming modes. the self-programming library supports this function. note the variable reset vector only determines the user?s program start after reset. the vector table is not affected. it is always located at address 0000 0000 h .
285 flash memory chapter 7 user?s manual u18743ee1v2um00 7.5 flash mask options in the option data area, a block subject to mask options is specified. make sure to set the option data area corresponding to the following option bytes in the program at address 007a h /007b h as default data. caution if the flash memory is programmed during a debug session with the on-chip debugger and the options bytes have been changed, a target reset command has to be issued in order to make the new option byte settings effective.
286 chapter 7 flash memory user?s manual u18743ee1v2um00 address set value setting 007a h 00 h internal oscil- lator: can be stopped. wdt2: count clock can be selected. overflow signal can be selected from intwdt2 or wdt2res. sub oscilla- tor: crystal resonator connection 01 h internal oscil- lator: cannot be stopped. wdt2: count clock can be selected. overflow signal can be selected from intwdt2 or wdt2res. sub oscilla- tor: crystal resonator connection 02 h internal oscil- lator: can be stopped. wdt2: count clock is fixed to internal oscillator. overflow signal is fixed to wdt2res. sub oscilla- tor: crystal resonator connection 03 h internal oscil- lator: cannot be stopped. wdt2: count clock is fixed to internal oscillator. overflow signal is fixed to wdt2res. sub oscilla- tor: crystal resonator connection c0 h internal oscil- lator: can be stopped. wdt2: count clock can be selected. overflow signal can be selected from intwdt2 or wdt2res. sub oscilla- tor: rc oscillation connection c1 h internal oscil- lator: cannot be stopped. wdt2: count clock can be selected. overflow signal can be selected from intwdt2 or wdt2res. sub oscilla- tor: rc oscillation connection c2 h internal oscil- lator: can be stopped. wdt2: count clock is fixed to internal oscillator. overflow signal is fixed to wdt2res. sub oscilla- tor: rc oscillation connection c3 h internal oscil- lator: cannot be stopped. wdt2: count clock is fixed to internal oscillator. overflow signal is fixed to wdt2res. sub oscilla- tor: rc oscillation
287 flash memory chapter 7 user?s manual u18743ee1v2um00 76543210 0000 007b h subclk 0 0 0 pllo prsi plli1 plli0 plli1 plli0 selection of pll input clock to pll 00f plli = f x 01f plli = fx/2 1xf plli = fx/4 prsi peripheral clock selection 0 f xp1, f xp2 = f xx 1 f xp1, f xp2 = f xx /2 pllo pll output clock selection 0 setting prohibited 1f pll = f pllo /2 subclk clock source at sublock operating mode 0subosc selection 1 240 khz internal oscillator selection
288 chapter 7 flash memory user?s manual u18743ee1v2um00 7.5.1 prdselh register - product selection code register high the 16-bit prdselh register specifies the ram start address of the device. access the register can be accessed in 16-bit units. address fffffcca h initial value device depending (for details see table below) 15 14 13 12 11 10 9 8 prdselhxxxxxxxx rrrrrrrr 76543210 x x x x ram3 ram2 ram1 ram0 rrrrrrrr ram3 ram2 ram1 ram0 ram start address 0 0 0 1 03ffd800h 0 0 1 0 03ffd000h 0 0 1 1 03ffc000h 0 1 0 0 03ffb000h
289 user?s manual u18743ee1v2um00 chapter 8 data protection and security 8.1 overview the microcontroller supports various methods for securing safe (re-)programming of the internal flash memory and protecting of the flash memory data against undesired access, such as illegal read-out or illegal reprogramming. security functions security functions provide countermeasures against unexpected failures during reprogramming processes. these are basically:  secure self-programming  secure bootloader update  boot swapping  boot block cluster protection these functions are described in detail in ?flash memory? on page 259 . protection functions protection functions provide a set of mechanisms to protect the internal flash memory data from being read, erased or altered by unauthorized persons. these are basically:  on-chip (n-wire) debug interface protection  flash memory erase/write/read protection via the serial programming interface some interfaces offer in general access to the internal flash memory: n-wire debug interface, external flash programmer interfaces and self-programming facilities. all of these interfaces need to be considered for a proper protection concept. the following sections give an overview about supported protection methods. 8.2 n-wire debug interface protection in general read-out of the flash memory contents is possible via the n-wire debug interface, but protection against illegal read-out can be enabled. for protection of the flash memory, the usage of the debug interface can be protected and it can be disabled. the debug interface is protected via a 10-byte id code and an internal flag (n-wire use enable flag). when the debugger is started, the status of a flag is queried (n-wire use enable flag). set this flag to zero to disable the use of the n-wire in-circuit emulator. when debugging is enabled (n-wire use enable flag is set), you have to enter a 10-byte id code via the debugger. the code is compared with the id code stored in the internal flash memory. if the codes do not match, debugging is not possible. the n-wire use enable flag can be set or reset while reprogramming the flash by an external flash writer or with the self-programming feature. the flag is located at bit 7 at address 0000 0079 h .
290 chapter 8 data protection and security user?s manual u18743ee1v2um00 you can specify your own 10-byte id code and program it to the internal flash memory by an external flash writer or with the self-programming feature. the id code is located in the address range 0000 0070 h to 0000 0079 h . the protection levels are summarized in ta b l e 8 - 1 note 1. after you have set protection levels 1 or 2, set the ?block erase disable flag? in the flash extra area. otherwise, an unauthorized person could erase the block that contains the id code or the ?n-wire use enable flag?, respectively, and thus suspend the protection. table 8-1 possible results of id code comparison n-wire use enable flag id code protection level 0x a a) codes are not compared level 2: full protection n-wire debug interface cannot be used. b b) once the n-wire debug interface has been set as ?use-prohibited?, it cannot be used until the flash memory is re-programmed. 1 user-specific id code level 1: id code protection user id code n-wire debug interface can only be used if the user enters the correct id code. id code is all ones c c) this is the default state after the flash memory has been erased. level 0: id code protection with default id code n-wire debug interface can be used if the user enters the default id code ff h for all id bytes.
291 data protection and security chapter 8 user?s manual u18743ee1v2um00 8.3 flash programmer and self-programming protection in general, illegal read-out and re-programming of the flash memory contents is possible via the flash writer interface and the self-programming feature.the available flash memory protection methods are as follows. serial programming it is possible to prohibit any access from external via the serial programming interface,e.g. by an external flash programmer. with maximum protection the internal flash memory can not be erased, read-out or written at all, neither in block units nor the entire flash memory. self-programming during self-programming all operations to erase, read or program the flash memory is under control of the user?s program. thus no further protection functions in self-programming mode are considered. one exception is the boot block protection, which applies also in self-programming mode. protection flags the protection flags can be set respectively reset by an external flash programmer, provided the effective protection level allows to do so. in self-programming mode the effective protection flags can not be reset, but other ones can be set to enhance the protection level. the protection flags are stored in the flash memory extra area. each protection function can be used in combination with the others at the same time. (1) write protection flag set this flag to disable the programming function via external flash programmer interfaces. no flash memory content can be written from external, if this flag is set. erasure of single blocks is prohibited as well. this flag does not affect the self-programming interface. in self-programming mode writing of the flash memory is further on possible. (2) chip erase protection flag set this flag to disable the chip erase function via external flash programmer interfaces. no flash memory content can be erased - neither in single blocks nor the entire flash memory - from external, if this flag is set. chip erase is not available in self-programming mode, though it is possible to erase the entire flash memory content by block erase of all blocks all together. note that the contents of the extra area is not erased by this means. i.e. protection flags, variable reset vector, etc. are still valid. (3) block erase protection flag set this flag to disable the feature to erase single blocks via external flash programmer interfaces. single blocks can not be erased. chip erase is still possible, provided the chip erase protection flag is not set. this flag does not affect the self-programming interface. in self-programming mode erasure of single blocks or sets of contiguous blocks of the flash memory is further on possible.
292 chapter 8 data protection and security user?s manual u18743ee1v2um00 (4) read-out protection flag set this flag to disable the feature that allows reading back the flash memory via external flash programmer interfaces. no flash content can be read out. this flag does not affect the self-programming interface. in self-programming mode read-out of flash memory content is further on possible. (5) boot block cluster protection flag set this flag to disable erasure and rewrite of the boot block cluster. the boot block cluster can not be manipulated in any way (no erase/write). this applies in serial and self-programming mode. once this flag is set, it is impossible to reset this flag. thus the boot block cluster content can not be changed any more. for the explanation of the boot block cluster refer to ?secure self-programming (boot cluster swapping)? on page 279 . all protection flags are reset after shipment of the device, thus no protection is enabled at all. once a protection flag has been set, i.e. the protection is effective, it can not be reset by any means, except after a chip erase, which erases the entire flash memory including the extra area. consequently without prior chip erase the protection level can only be increased, but not decreased. table 8-2 protection functions overview function functional outline applicable ( : applies, : doesn?t apply) serial programming self-programming block erase command prohibit erasure of single blocks impossible. once block erase protection is enabled, disable is only possible after chip erase. ? chip erase command prohibit erasure of the entire flash (including the extra area) or single blocks impossible. once chip erase protection is enabled, all protection flag settings can not be changed any more. ? program command prohibit erasure and rewrite of single blocks impossible. once write protection is enabled, disable is only possible after chip erase. ? read command prohibit read-out of any flash content impossible. once read protection is enabled, disable is only possible after chip erase. ? rewriting boot block cluster prohibit erasure (by block or chip erase) or writing of the boot block cluster impossible. once rewrite protection of the boot block cluster is enabled, it can not be disabled any more. ?
293 data protection and security chapter 8 user?s manual u18743ee1v2um00 note ?: not supported note : execution enabled, : execution disabled, ?: not supported table 8-3 rewriting operation when erasing/writing is enabled/prohibited prohibition state programming mode block erasure chip erasure write boot area none boot area boot area none boot area rewriting boot area enabled all enabled self-programming yes ? yes serial programming yes yes yes block erase command prohibited self-programming yes ? yes serial programming no yes yes chip erase command prohibited self-programming yes ? yes serial programming no no yes write command prohibited self-programming yes ? yes serial programming no yes no rewriting boot area prohibited all enabled self-programming no yes ? no yes serial programming yes no yes block erase command prohibited self-programming yes ? yes serial programming no yes yes chip erase command prohibited self-programming yes ? yes serial programming no no yes write command prohibited self-programming yes ? yes serial programming no yes no table 8-4 read operation when reading is enabled/prohibited prohibition state programming mode read read command enabled self-programming serial programming read command prohibited self-programming serial programming
294 chapter 8 data protection and security user?s manual u18743ee1v2um00
295 preliminary user?s manual u18743ee1v2um00 chapter 9 bus control unit (bcu) the bus control unit bcu controls the access to on-chip peripheral i/os. 9.1 description the figure below shows a block diagram of the modules that are necessary for accessing the on-chip peripherals. figure 9-1 bus and memory control block diagram busses the busses are abbreviated as follows:  npb: nec peripheral bus  vsb: v850 system bus  vdb: v850 data bus  vfb: v850 fetch bus bcu the bus control unit (bcu) controls the access to the on-chip peripherals. . internal bus (npb) bus control unit cpu bus bridge v s b vdb vfb on-chip peripheral i/o
296 chapter 9 bus control unit (bcu) preliminary user?s manual u18743ee1v2um00 9.1.1 peripheral i/o area two areas of the address range are reserved for the registers of the on-chip peripheral functions. these areas are called ?peripheral i/o areas?: (1) fixed peripheral i/o area the fixed peripheral i/o area holds the registers of the on-chip peripheral i/o functions. note because the address space covers 64 mb, the address bits a[31:26] are not considered. therefore, in this manual, all addresses of peripheral i/o registers in the 4 kb peripheral i/o area are given in the range ffff f000 h to ffff ffff h instead of 03ff f000 h to 03ff ffff h . table 9-1 peripheral i/o areas name address range size fixed peripheral i/o area 03ff f000 h to 03ff fff h 4 kb programmable peripheral i/o area (ppa) 03fe c000 h to 03fe efff h 12 kb
297 bus control unit (bcu) chapter 9 preliminary user?s manual u18743ee1v2um00 (2) programmable peripheral i/o area (ppa) with this microcontroller, usage and address range of the ppa are not configurable. the ppa extends the fixed peripheral i/o area and assigns an additional 12 kb address space for accessing on-chip peripherals. the figure below illustrates the programmable peripheral i/o area (ppa). figure 9-2 programmable peripheral i/o area the can modules registers and message buffers are allocated to the ppa. refer to ?can module register and message buffer addresses? on page 553 for information how to calculate the register and message buffer addresses of the can modules. note 1. the fixed peripheral i/o area is mirrored to the upper 4 kb of the programmable peripheral i/o area. if data is written in one area, data having the same contents is also written in the other area. 2. to make software suitable for both microcontroller and emulation tool, it is recommended to include the set up of the base address in the software. see ?bpc - peripheral area selection control register? on page 301 . 03ff ffffh 03ff f000h 03fe efffh 03fe c000h peripheral i/o register programmable peripheral i/o register npb (nec peripheral bus) dedicated area for fcan controller peripheral i/o area programmable peripheral i/o area (4 kb) (12 kb) (4 kb) same area
298 chapter 9 bus control unit (bcu) preliminary user?s manual u18743ee1v2um00 9.1.2 npb access timing all accesses to the peripheral i/o areas are passed over to the npb bus via the vsb - npb bus bridge bbr. read and write access times to registers via the npb depend on the register (refer to ?registers access times? on page 749 ), the system clock vbclk and the setting of the vswc register. the cpu operation during an access to a register via the npb depends also on the kind of peripheral i/o area:  fixed peripheral i/o area during a read or write access the cpu operation stops until the access via the npb is completed.  programmable peripheral i/o area during a read access the cpu operation stops until the read access via the npb is completed. during a write access the cpu operation continues operation, provided any preceded npb access is already finished. if a preceded npb access is still ongoing the cpu stops until this access is finished and the npb is cleared. caution pay attention at write accesses to npb peripheral i/o registers via the programmable peripheral i/o area. since the cpu may continue operation, even though the data has not yet been transferred to its destination register, inconsistencies may occur between the program flow and the status of the registers. in particular register set-ups which change an operational status of a certain module require special notice, like, for instance, masking/unmasking of interrupts via maskable interrupt control registers xxic, enabling/disabling timers, etc.
299 bus control unit (bcu) chapter 9 preliminary user?s manual u18743ee1v2um00 9.1.3 bus properties this section summarizes the properties of the internal bus. (1) bus access the number of cpu clocks necessary for accessing each resource is as follows: note unit: clocks/access (2) endian format the endian format is fixed to little endian format. the endian format defines the byte order in which word data is stored. ?little endian? means that the low-order byte of the word is stored in memory at the lowest address, and the high-order byte at the highest address. therefore, the base address of the word addresses the low-order byte: figure 9-3 little endian addresses within a word 9.1.4 boundary operation conditions the microcontroller device has the following boundary operation conditions: (1) program space instruction fetches from the internal peripheral i/o area are inhibited and yield nop operations. if a branch instruction exists at the upper limit of the internal ram area, a pre-fetch operation (invalid fetch) that straddles over the internal peripheral i/o area does not occur. table 9-2 number of bus access clocks bus cycle configuration internal rom (32 bits) internal ram (32 bits) with latency = 0 with latency = 1 instruction fetch normal access 1 1 1 a a) in case of contention with data access, the instruction fetch from internal ram takes 2 clocks. branch 241 operand data access 1 4 1 31 24 23 16 15 8 0 7 byte 3 byte 2 byte 1 byte 0 + 3 + 2 + 1 access via addresses byte position bit number
300 chapter 9 bus control unit (bcu) preliminary user?s manual u18743ee1v2um00 (2) data space the microcontroller device is provided with an address misalign function. by this function, data of any format (word: 32 bit, halfword: 16 bit, byte: 8 bit) can be placed to any address in memory, even though the address is not aligned to the data format (that means address 4n for words, address 2n for halfwords).  unaligned halfword data access when the lsb of the address is a0 = 1, two byte accesses are performed.  unaligned word data access ? when the lsb of the address is a0 = 1, two byte and one halfword accesses are performed. in total it takes 3 bus cycles. ? when the lsbs of the address are a[1:0] =10 b , two halfword accesses are performed. note accessing data on misaligned addresses takes more than one bus cycle to complete data read/write. consequently, the bus efficiency will drop.
301 bus control unit (bcu) chapter 9 preliminary user?s manual u18743ee1v2um00 9.2 registers access to the on-chip peripherals is controlled and operated by registers of the bus control unit (bcu): 9.2.1 bcu registers the following registers are part of the bcu. they define the usage of the programmable peripheral i/o area (ppa) and the data bus width. (1) bpc - peripheral area selection control register the 16-bit bpc register enables/disables the ppa and it determines the starting address of the ppa.  for the microcontroller, the base address of the ppa is fixed to 03fe c000 h . thus writing to bpc.pa[13:0] does not change the ppa base address. nevertheless the ppa must be enabled by setting bpc.pa15 = 1.  for the emulation tool, the ppa has to be enabled and the base address has to be set up by writing 8ffb h to the bpc register. to make software suitable for both microcontroller and emulation tool, it is recommended to include the set up of the ppa with bpc = 8ffb h in the software. access this register can be read/written in 16-bit units. address ffff f064 h initial value 0000 h caution the bits marked with 0 must always be 0. the base address pba of the programmable peripheral area sets the start address of the 16 kb ppa in a range of 256 mb. the 256 mb page is mirrored 16 times to the entire 32-bit address range. table 9-3 bus and memory control register overview module register name shortcut address bus control unit (bcu) peripheral area selection control register bpc ffff f064 h internal peripheral function wait control register vswc ffff f06e h 1514131211109876543210 pa15 0 pa13 pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 table 9-4 bpc register contents bit position bit name function 15 pa15 select usage of programmable peripheral i/o area (ppa). 0: ppa disabled 1: ppa enabled 11 to 0 pa[13:0] bits pa[13:0] specify bits 27 to 14 of the starting address of the ppa. the other bits of the address are fixed to 0.
302 chapter 9 bus control unit (bcu) preliminary user?s manual u18743ee1v2um00 the base address pba is calculated by pba = bpc.pa[13:0] x 2 14 ta b l e 9 - 5 shows how the addresses of the programmable peripheral area are assembled. the base address pba is highlighted. (2) vswc - internal peripheral function wait control register the 8-bit vswc register controls the bus access wait for the on-chip peripheral i/o registers. the data wait states are based on the system clock. access to on-chip peripheral i/o registers is made in 3 clocks (without wait), however, waits may be required depending on the operation frequency. set the values described below to the vswc register in accordance with the operation frequency used. access this register can be read/written in 8-bit units. address ffff f06e h initial value 77 h table 9-5 address range of programmable peripheral area (12 kb) 31 ? 28 27 ? 14 13 ? 1 0 bit 0 ? 0 bpc.pa[13:0] 1 ? 1 1 ?? ? 0 ? 0 bpc.pa[13:0] 0 ? 0 1 0 ? 0 bpc.pa[13:0] 0 ? 0 0 pba 76543210 0 suwl2 suwl1 suwl0 0 vswl2 vswl1 vswl0 rr/wr/wr/wrr/wr/wr/w table 9-6 vswc register contents (1/2) bit position bit name function 6 to 4 suwl[2:0] address setup wait for internal bus: suwl2 suwl1 suwl0 number of address setup wait states 00 0 0 0 0 1 1 cpu system clock (vbclk) 0 1 0 2 cpu system clock (vbclk) 0 1 1 3 cpu system clock (vbclk) 1 0 0 4 cpu system clock (vbclk) 1 0 1 5 cpu system clock (vbclk) 1 1 0 6 cpu system clock (vbclk) 1 1 1 7 cpu system clock (vbclk)
303 bus control unit (bcu) chapter 9 preliminary user?s manual u18743ee1v2um00 the following setups are recommended for vswc: note 1. the bits marked with 0 must always be 0. 2. this register must be initialized after reset . 2 to 0 vswl[2:0] data wait for internal bus: vswl2 vswl1 vswl0 number of data wait states 00 0 0 0 0 1 1 cpu system clock (vbclk) 0 1 0 2 cpu system clock (vbclk) 0 1 1 3 cpu system clock (vbclk) 1 0 0 4 cpu system clock (vbclk) 1 0 1 5 cpu system clock (vbclk) 1 1 0 6 cpu system clock (vbclk) 1 1 1 7 cpu system clock (vbclk) table 9-6 vswc register contents (2/2) bit position bit name function table 9-7 recommended timing for internal bus system clock (f cpu ) 16 mhz 20 mhz suwl 0 0 vswl 0 1 vswc 00 h 01 h
304 chapter 9 bus control unit (bcu) preliminary user?s manual u18743ee1v2um00
305 user?s manual u18743ee1v2um00 chapter 10 16-bit timer/event counter aa the v850es/fx3-l microcontrollers have following instances of the 16-bit timer/event counter aa: throughout this chapter, the individual instances of timer aa are identified by ?n?, for example, taanctl0 for the taan control register 0. the timer is upward compatible to timer p used in various other devices of the v850e and the v850es family. it offers new additional features for enhanced output control 10.1 features timer aa (taa) is a 16-bit timer/event counter provided with general-purpose functions. taa can perform the following operations.  16-bit-accuracy pwm output timer  interval timer  external event counter function  timer synchronised operation function withother timers aa channels (refer to ?timer aa synchroneous operation? on page 377 )  one-shot pulse output  pulse interval and frequency measurement counter  free running function  external trigger pulse output function  32-bit capture timer function by cascading 2 channels of taa taa v850es/ fe3-l v850es/ ff3-l v850es/ fg3-l instances 5 names taa0 to taa4
306 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 10.2 function outline  capture trigger input signal 2  external trigger input signal 1  clock select 8  external event count input 1  readable counter 1  capture/compare reload register 2  capture/compare match interrupt 2  timer output (toaan0, toaan1) 2  32-bit capture by cascading two timer aa ( ta a 0 + ta a 1 , ta a 2 + ta a 3 , ta a 5 + ta a 6 ) . 10.3 configuration taa includes the following hardware. timer aa (taa) pins are alternate function of port pins. for how to set the alternate function, refer to the description of the registers in ?pin functions? on page 31 . the block diagram of the timer taa is shown below. figure 10-2 to figure 10-3 show the block diagrams of the input circuits of the different timers taan. table 10-1 timer taa registers and external connections item configuration timer register 16-bit counter registers  taan timer capture/compare registers 0, 1 (taanccr0, taanccr1)  taan timer read buffer register (taancnt)  ccr0 buffer register, ccr1 buffer register input selection registers selector control registers (selcnt0, selcnt3) timer output toaan0, toaan1 timer input tiaan0, tiaan1 control registers  taan control registers 0, 1 (taanctl0, taanctl1)  taan i/o control registers 0 to 2 and 4 (taanioc0 to taanioc2, taanioc4)  taan option registers 0, 1 (taanopt0, taanopt1)
307 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-1 block diagram of timer aa inter nal b us taanccr0 taanccr1 counter control t r igger control taancnt0 clear 16-bit counter ccr0 b uff er register ccr1 b uff er register taanctl1 taansye taanest taaneee taanmd2-0 taanopt0 taanccs1-0 taanovf taanioc1 taanis3-0 taanioc0 taance taance inttaancc0 taanctl0 taance taancks2-0 taanioc2 taaness1-0 taanets1-0 selector selector f xp1 or f xp2 f xp1 /2 or f xp2 /2 f xp1 /4 or f xp2 /4 f xp1 /8 f xp1 /16 f xp1 /32 f xp1 /64 selector inter nal b us edge detector edge detector edge detector edge detector load load inttaanov inttaancc1 t oaan0 output controller capture/compare selection function t oaan1 taanioc4 taanopt1 taancse input circuit (see separate figure) f xp1 /128 or f xp1 /256 or f xt
308 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-2 input circuit of taa0 (left) and taa1 (right) figure 10-3 input circuit of taa3 edge detector edge detector selcnt0 inter nal bu s tiaa00 tiaa01 inttm0eq0 tsout from can0 edge detector edge detector s elcnt0 tiaa10 tiaa11 rxdd0 internal bus rxdd1 edge detector edge detector selcnt0 tiaa30 tiaa31 rxdd2 inter nal bu s
309 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (1) taanccr0 - taa capture/compare register 0 the taanccr0 register is a 16-bit register that operates either as capture register or as a compare register. in free-running mode, this register can be used as a capture register or as a compare register specified by bit taanopt0.taanccs0. in the pulse width measurement mode, this register can be used only as a capture register (the compare function cannot be used.) in all modes other than free-running mode and pulse width measurement mode, this register is used as a compare register. this register can be read/written in 16-bit units. after a reset , taanccr0 register default status is compare register. reset input clears this register to 0000h. caution when external event counter mode is used, do not set taanccr0 register to 0000h.  when used as a compare register, taanccr0 can be rewritten when taance = 1, as shown below:  when used as capture register, the count value is stored in taanccr0 upon capture trigger (tiaan0) input edge detection. note 1. the value of taanccr0 register can be read/written when taance bit of taan control register 0 (taanctl0) equals 1. 2. access to the taanccr0 register is prohibited when the main clock is stopped in the subclock mode. address: taa0ccr0 fffff596h, taa1ccr0 fffff5a6h, taa2ccr0 fffff5b6h, taa3ccr0 fffff5c6h, taa4ccr0 fffff5d6h 1514131211109876543210 r/w after reset taanccr0 r/w 0000h taa operation mode taanccr0 register writing method pwm mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode any time write pulse width measurement mode not applicable (used as capture register)
310 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 (2) taanccr1 - taa capture/compare register 1 the taanccr1 register is a 16-bit register that operates either both as a capture register or as a compare register. in free-running mode, this register can be used as a capture register or as a compare register specified by bit taanopt0.taanccs1. in the pulse width measurement mode, this register can be used only as a capture register (the compare function cannot be used.) in all modes other than free-running mode and pulse width measurement mode, this register is used as a compare register. after reset , taanccr1 register default status is compare register. reset input clears this register to 0000h. caution when external event counter mode is used, do not set taanccr1 register to 0000h.  when used as a compare register taanccr1 can be rewritten when taance = 1, as below mentioned.  when used as a capture register count value is stored in taanccr1 upon capture trigger (tiaan1) input edge detection. note 1. the value of taanccr1 register can be read/written when taance bit of taan control register 0 (taanctl0) equals 1. 2. access to the taanccr1 register is prohibited when the main clock is stopped in the subclock mode. address: taa0ccr1 fffff598h, taa1ccr1 fffff5a8h, taa2ccr1 fffff5b8h, taa3ccr1 fffff5c8h, taa4ccr1 fffff5d8h 1514131211109876543210 r/w after reset taanccr1 r/w 0000h taa operation mode taanccr1 register writing method pwm mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode any time write pulse width measurement mode not applicable (used as capture register)
311 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (3) taancnt - taa counter read buffer register taancnt register is a read buffer register that can read 16-bit counter values. this register is read-only, using a 16-bit memory manipulation instruction. reset input sets this register to 0000h. when taance bit of taanctl0 equals 0, 0000h is read from this register. the value of the register is read when taance bit = 1. address: taa0cnt fffff59ah, taa1cnt fffff5aah, taa2cnt fffff5bah, taa3cnt fffff5cah, taa4cnt fffff5dah 1514131211109876543210 r/w after reset taancnt r 0000h
312 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 10.4 input selection registers these registers are used to select the inputs to timers. note 1. in this section, only the bits that refer to timer aa input selections are described. for further information concerning the other bits please refer to ?clock generator? on page 179 . 2. enable the related peripheral function only after setting/changing the selcntn registers. (1) selcnt0 - selector control register 0 access this register can be read/written in 8-bit or 1-bit units. address ffff f308 h . initial value 00 h . this register is initialized by any reset.  v850es/fe3-l  v850es/ff3-l  v850es/fg3-l note ?r? bits marked with ?0? must not be changed from their default value ?0?. 76543210 isel07 0 0 isel04 isel03 isel02 0 isel00 r/w r r r/w r/w r/w r r/w 76543210 isel07 0 isel05 isel04 isel03 isel02 0 isel00 r/w r r/w r/w r/w r/w r r/w table 10-2 selcnt0 register contents bit position bit name function 7 isel07 refers to clock generator 6 isel06 selection of tiaa31: 0: tiaa31 pin 1: rxdd3 pin 5 isel05 selection of tiaa30: 0: tiaa30 pin 1: rxdd2 pin 4 isel04 selection of tiaa11: 0: tiaa11 pin 1: rxdd1 pin 3 isel03 selection of tiaa10: 0: tiaa10 pin 1: rxdd0 pin 2 isel02 selection of tiaa01: 0: tiaa01 pin 1: inttm0eq0 signal from tmm 0 isel00 selection of tiaa00: 0: tiaa00 pin 1: tso ut signal from can0
313 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 note if the inttm0eq0 interrupt signal is used for the tiaa01 input signal, use in the following range. tmm operation clock period taa operation clock period x 4 (2) selcnt3 - selector control register 3 access this register can be read/written in 8-bit or 1-bit units. address ffff f30e h . initial value 00 h . this register is initialized by any reset.  v850es/fg3-l note ?r? bits marked with ?0? must not be changed from their default value ?0?. 76543210 0 0 0 0 0 isel32 0 0 rrr r rr/wr r table 10-3 selcnt3 register contents bit position bit name function 2 isel32 refers to clock generator
314 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 10.5 control registers (1) taanctl0 - taa control register 0 taan control register 0 is an 8-bit register that controls the operation of timer aa. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. the taanctl0 register is prohibited from writing during operation (taance=1). however, the taance bit can be rewritten. note in the following modes taanctl0.taance cannot be set to ?1?:  slave timer in synchroneous operation mode if the timer is operated as the slave timer in synchroneous operation mode, i.e. taanctl1.taansye = 1.  slave timer in 32-bit cascaded capture mode if timer taan is operated in 32-bit capture mode for capturing the upper 16 bit, i.e. taanopt1.taancse = 1 (n = 1, 3). address: taa0ctl0 fffff590h, taa1ctl0 fffff5a0h, taa2ctl0 fffff5b0h, taa3ctl0 fffff5c0h, taa4ctl0 fffff5d0h symbol76543 2 1 0r/w after reset ta a n c t l 0 taan ce 0000 taan cks2 taan cks1 taan cks0 r/w 00h taance timer aan operation control 0 disable internal operating clock operation (taan is asynchronously reseted) 1 enable internal operating clock operation internal operating clock control and taan asynchronous reset are performed with the taance bit. when taance bit is cleared to 0, the internal operating clock of taan stops (fixed to low level) and taan is reset asynchronously. when the taance bit is set to 1, the internal operating clock is enabled within 2 input clocks, and taan counts up.
315 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 note 1. prsi can be set by the option bytes: refer to ?flash memory? on page 259 for details. caution set bits taancks2 to taancks0 only when taance = 0. when taance bit setting is changed from 0 to 1, taancks2 to taancks0 bits can be set simultaneously. when the main clock is stopped, the count operation with the subclock is not available. selcnt2.isel2[4:0] taanctl0 register selection of internal count clock input n = 0, 2, 4 n = 1, 3 taan cks2 taan cks1 taan cks0 prsi = 0 prsi = 1 prsi = 0 prsi = 1 0 000 f xp1 f xx f xx /2 f xx f xx /2 1f xp2 a a) f xp2 has the same frequency as f xx , but doesn't stop in idle1 mode. refer to ?clock generator? on page 179 for details. f xx f xx /2 f xx f xx /2 0 001 f xp1 /2 f xx /2 f xx /4 f xx /2 f xx /4 1f xp2 /2 f xx /2 f xx /4 f xx /2 f xx /4 0 010 f xp1 /4 f xx /4 f xx /8 f xx /4 f xx /8 1f xp2 /4 f xx /4 f xx /8 f xx /4 f xx /8 x 011f xp1 /8 f xx /8 f xx /16 f xx /8 f xx /16 x 100f xp1 /16 f xx /16 f xx /32 f xx /16 f xx /32 x 101f xp1 /32 f xx /32 f xx /64 f xx /32 f xx /64 x 110f xp1 /64 f xx /64 f xx /128 f xx /64 f xx /128 x 111 f xp1 /128 f xx /128 f xx /256 ? ? f xt ??f xt f xt
316 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 (2) taanctl1 - taa timer control register 1 taan control register 1 is an 8-bit register that controls the operation of timer aa. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. address: taa0ctl1 fffff591h, taa1ctl1 fffff5a1h, taa2ctl1 fffff5b1h, taa3ctl1 fffff5c1h, taa4ctl1 fffff5d1h symbol76543 2 1 0r/w after reset taanctl1 taan sye taan est taan eee 00 taan md2 taan md1 taan md0 r/w 00h taansye synchroneous operation mode enable control 0 independent operation mode (asynchronous operation mode) 1 synchroneous operation mode (specification of slave operation) in this mode, timer aa can operate in synchronization with a master timer. if taansye = 1, taanctl0.taance cannot be set to ?1?. for the synchroneous operation mode, refer to ?timer aa synchroneous operation? on page 377 . caution: be sure to clear the taansye to 0, if taan is used as the master timer respectively, set the taansye = 1, if taan is used as slave timer. taanest software trigger control 0 no operation 1 in one-shot pulse mode: one-shot pulse software trigger in external trigger pulse output mode: pulse output software trigger the taanest bit functions as a software trigger in the one-shot pulse mode or external trigger pulse output mode (this bit is invalid in any other mode). by setting taanest to 1 when taance = 1, a software trigger is issued. therefore, be sure to set taanest to 1 after setting taance = 1. the tiaan0 pin is used for an external trigger. the read value of the taanest bit is always 0. taaneee count clock selection 0 use the internal clock (clock selected with taancks2 to taancks0 bits of taanctl0 register) 1 use external clock (input edge of tiaan0) the valid edge is specified with taanees1 and taanees0 bits when taaneee bit = 1 (external clock tiaan0).
317 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 caution 1. set bits taaneee and taanmd2 to taanmd0 when taance = 0. (the same value can be written when taance = 1.) the operation is not guaranteed when rewriting is performed when taance = 1. if rewriting was mistakenly performed, clear taance to 0 and then set the bits again. 2. in the external event count mode the external event count input is selected regardless of the value of thetaaneee bit. 3. set the count clock to internal clock (taaneee = 0) when you use an external trigger pulse mode, the single shot pulse mode, and the pulse length measurement mode. 4. set the edge detection of the tiaan0 capture input to no detection when you use an external event count mode (taanees1 of the taanioc2 register and taanees0 = 00). taanmd2 taanmd1 taanmd0 timer mode selection 0 0 0 interval timer mode 0 0 1 external event counter mode 0 1 0 external trigger pulse output mode 0 1 1 one-shot pulse mode 100pwm mode 1 0 1 free-running mode 1 1 0 pulse width measurement mode 1 1 1 setting prohibited
318 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 (3) taanioc0 - taa dedicated i/o control register 0 the taanioc0 register is an 8-bit register that controls the timer output. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution 1. rewrite bits taanolm and taanoem when taance = 0 (the same value can be written when taance = 1.). if rewriting was mistakenly performed, clear taance to 0 and then set the bits again. 2. to enable the timer output, be sure to set the corresponding alternate- function pins taanis3 to taanis0 of the taanioc1 register to ?no edge detection? and invalidate the capture operation. then set the corresponding alternate-function port to output mode. note m = 0, 1 address: taa0ioc0 fffff592h, taa1ctl0 fffff5a2h, taa2ioc0 fffff5b2h, taa3ioc0 fffff5c2h, taa4ioc0 fffff5d2h symbol76543210r/w after reset taanioc00000 taan ol1 taan oe1 taan ol0 taan oe0 r/w 00h taanolm toaanm output level setting 0 normal output 1 inverted output this bit can be used to invert the timer output taa noem toaanm output setting 0 timer output is disabled (low level and high level are output from toaanm pin when taanolm = 0 and taanolm = 1, respectively.) 1 timer output is enabled (toaanm pin outputs pulses.)
319 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (4) taanioc1 - taa dedicated i/o control register 1 the taanioc1 register is an 8-bit register that controls the valid edge for the external input signals (tiaan0 and tiaan1). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution 1. bits taanis3 to taanis0 are valid only in the free-running capture mode and pulse width measurement mode. in all the other modes, capture operation is not performed. 2. if used as the capture input, be sure to set the corresponding alternate- function pins taanoe1 and taanoe0 of the taanioc0 register to ?timer output is disabled? and set the capture input valid edge. then set the corresponding alternate-function port to input mode. 3. in the external event count mode (taanctl1.taaneee = 1), set the tiaan0 capture input to "no edge detection" (taanis1 and taaniso bits = 00). address: taa0ioc1 fffff593h, taa1ioc1 fffff5a3h, taa2ioc1 fffff5b3h, taa3ioc1 fffff5c3h, taa4ioc1 fffff5d3h symbol76543210r/w after reset taanioc10000 taan is3 taan is2 taan is1 taan is0 r/w 00h taanis3 taanis2 capture input (tiaan1) valid edge setting 0 0 no edge detection (capture operation is invalid) 0 1 detection of rising edge 1 0 detection of falling edge 1 1 detection of both edges taa nis1 taanis0 capture input (tiaan0) valid edge detection 0 0 no edge detection (capture operation is invalid) 0 1 detection of rising edge 1 0 detection of falling edge 1 1 detection of both edges
320 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 rewrite during timer operation if the edge specification for the capture operation shall be changed, while the timer remains in operation (taanctl0.taance = 1), only a single bit of the edge specification bits taanioc1.taanis[k:i] of a dedicated capture input may be changed with a single write operation. consequently proceed as follows (tiaan0 is used exemplarily):  change from rising edge to falling edge: ? current status is taanioc1.taanis[1:0] = 01 b : ?rising edge? ? set taanioc1.taanis[1:0] = 00 b : specify ?no edge? ? set taanioc1.taanis[1:0] = 10 b : specify ?falling edge?  change from falling edge to rising edge: ? current status is taanioc1.taanis[1:0] = 10 b : ?falling edge? ? set taanioc1.taanis[1:0] = 00 b : specify ?no edge? ? set taanioc1.taanis[1:0] = 01 b : specify ?rising edge?  change from rising or falling edge to both edges: ? current status is taanioc1.taanis[1:0] = 01 b or 10 b : ?rising? or ?falling edge? ? set taanioc1.taanis[1:0] = 11 b : specify ?both edges?
321 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (5) taanioc2 - taa i/o control register 2 the taanioc2 register is an 8-bit register that controls the valid edge for external event count input signals (tiaan0) and external trigger input signal (tiaan0). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution 1. rewrite taanees1, taanees0, taanets1, and taanets0 bits when taance = 0 (the same value can be written when taance = 1). if rewriting was mistakenly performed, clear taance to 0 and then set the bits again. 2. taanees1 and taanees0 bits are valid only when taaneee = 1 or when the external event count mode has been set (taanctl1.taanmd[2:0] = 001 b ). 3. taanets1 and taanets0 bits are only valid when the external trigger pulse output mode or one-shot pulse mode is set (taanmd[2:0] = 010 b or 011 b ). address: taa0ioc2 fffff594h, taa1ioc2 fffff5a4h, taa2ioc2 fffff5b4h, taa3ioc2 fffff5c4h, taa4ioc2 fffff5d4h symbol7654 3 2 1 0r/w after reset taan ioc2 0000 taan ees1 taan ees0 ta a n ets1 taan ets0 r/w 00h taanees1 taanees0 external event count input valid edge setting (tiaan0) 0 0 no edge detection(external event count is invalid). 0 1 detection of rising edge 1 0 detection of falling edge 1 1 detection of both edges taanets1 taanets0 external trigger input valid edge detection (tiaan0) 0 0 no edge detection (external trigger is invalid). 0 1 detection of rising edge 1 0 detection of falling edge 1 1 detection of both edges
322 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 rewrite during timer operation if the edge specification for the external event count input and external trigger input shall be changed, while the timer remains in operation (taanctl0.taance = 1), only a single bit of the edge specification bits taanioc2.taanees[k:i] / taanioc2.taanets[k:i] of a dedicated capture input may be changed with a single write operation. consequently proceed as follows (tiaan0 is used exemplarily): in external event counter mode:  change from rising edge to falling edge: ? current status is taanioc2.taanees[1:0] = 01 b : ?rising edge? ? set taanioc2.taanees[1:0] = 00 b : specify ?no edge? ? set taanioc2.taanees[1:0] = 10 b : specify ?falling edge?  change from falling edge to rising edge: ? current status is taanioc2.taanees[1:0] = 10 b : ?falling edge? ? set taanioc2.taanees[1:0] = 00 b : specify ?no edge? ? set taanioc2.taanees[1:0] = 01 b : specify ?rising edge?  change from rising or falling edge to both edges: ? current status is taanioc2.taanees[1:0] = 01 b or 10 b : ?rising? or ?falling edge? ? set taanioc2.taanees[1:0] = 11 b : specify ?both edges? in external trigger mode:  change from rising edge to falling edge: ? current status is taanioc2.taanets[1:0] = 01 b : ?rising edge? ? set taanioc2.taanets[1:0] = 00 b : specify ?no edge? ? set taanioc2.taanets[1:0] = 10 b : specify ?falling edge?  change from falling edge to rising edge: ? current status is taanioc2.taanetss[1:0] = 10 b : ?falling edge? ? set taanioc2.taanets[1:0] = 00 b : specify ?no edge? ? set taanioc2.taanets[1:0] = 01 b : specify ?rising edge?  change from rising or falling edge to both edges: ? current status is taanioc2.taanets[1:0] = 01 b or 10 b : ?rising? or ?falling edge? ? set taanioc2.taanets[1:0] = 11 b : specify ?both edges? ensure the input level is not changing while the taanioc2 register is modified.
323 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (6) taanioc4 - taa i/o control register 4 the taanioc4 register is an 8-bit register that controls the output function of timer aa. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. note 1. after forcing the output level to either active or inactive, the toaan1 (toaan0) maintains this level (i.e. no toggling afterwards) until the taanos1 (taanos0) and taanor1 (taanor0) are cleared to standard operation. 2. the forcing of an output level is executed at the time of the next upcoming toggle event, while the freeze becomes effective immediately. 3. writing to taanioc4 is also possible, when taanctl0.taance = 1. 4. the taanioc4 register can be used in the interval mode or the free running mode. in other modes set this register to 00h. 5. in the free running mode, the setting's of the taanioc4 register becomes effective only if the compare function is selected. when the capture function is selected, it is invalid. address: taa0ioc4 fffff59ch, taa1ioc4 fffff5ach, taa2ioc4 fffff5bch, taa3ioc4 fffff5cch, taa4ioc4 fffff5dch symbol7654 3 2 1 0r/w after reset taanioc40000 taan os1 taan or1 ta a n os0 taan or0 r/w 00h ta anos1 taanor1 toggle control of toaan1 0 0 standard operation. 0 1 force output level to inactive at next toggle event 1 0 force output level to active at next toggle event 1 1 freeze current output level. taanos0 taanor0 toggle control of toaan0 0 0 standard operation. 0 1 force output level to inactive at next toggle event 1 0 force output level to active at next toggle event 1 1 freeze current output level.
324 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 (7) taanopt0 - taa option register 0 the taanopt0 register is an 8-bit register used to set the capture/compare operation and detect overflow. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution rewrite taanccs1 and taanccs0 bits when taance = 0 (the same value can be written when taance = 1.). if rewriting was mistakenly performed, clear taance to 0 and then set the bits again. address: taa0opt0 fffff595h, taa1opt0 fffff5a5h, taa2opt0 fffff5b5h, taa3opt0 fffff5c5h, taa4opt0 fffff5d5h, taa5opt0 fffff5e5h, taa6opt0 fffff5f5h, taa7opt0 fffff605h symbol76 5 4 321<0>r/w after reset taanopt0 0 0 taan ccs1 taan ccs0 000 taan ovf r/w 00h taanccs1 taanccr1 register capture/compare selection 0 compare register selection 1 capture register selection the taanccs1 bit setting is valid only in the free-running mode. taanccs0 taanccr0 register capture/compare selection 0 compare register selection 1 capture register selection the taanccs0 bit setting is valid only in the free-running mode. taanovf timer aa overflow detection set (1) overflow occurrence reset (0) taanovf bit write or taance = 0  the taanovf bit is set when the 16-bit counter value overflows from ffffh to 0000h in the free-running mode and the pulse width measurement mode.  an interrupt request signal (inttaanov) is generated as soon as taanovf bit is set (1). the inttaanov signal is not generated in any mode other than free-running mode and the pulse width measurement mode.  the taanovf bit is not cleared even when the taanovf bit and the taanopt0 register are read when taanovf = 1.  the taanovf bit can be both read and written, but 1 cannot be written to the taanovf bit from the cpu. writing 1 has no influence on timer aa operation.
325 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (8) taanopt1 - taa option register 1 the taanopt1 register is an 8-bit register used to set the 32-bit capture mode by cascading two timer aa. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. note n = 1, 3 note 1. when setting taancse, the timer becomes the upper 16-bit of a 32-bit timer. 2. if taancse = 1, taanctl0.taance is forced to ?0?. 3. cascading is only available for capture with free-running counter. 4. the following pairs of timers can be cascaded:  ta a 0 a n d ta a 1 (taa0 will become master and will hold the lower 16-bit value)  ta a 2 a n d ta a 3 (taa2 will become master and will hold the lower 16-bit value) the table below shows the effects of the taancse flag on the timer operation: n=1 or 3; m= (n-1). for details on the 32-bit capture mode, please refer to ?32-bit capture in free- running cascade mode? on page 363 . address: taa1opt1 fffff5adh, taa3opt1 fffff5cdh symbol76 5 4 321<0>r/w after reset taanopt1 taan cse 00 00000r/w00h taa ncse taanccr1 register capture/compare selection 0 16-bit non-cascaded mode 1 set 32-bit cascaded capture mode. timer aan becomes the upper 16- bit and slave. the master timer is taam with m = n - 1. taancse=0 tancse=1 operating clock macro clock from clock tree macro clock of taam count enable taance bit of taanctl0 taamce bit of taam count clock selected by taancks[2:0] counter overflow from taam capture signal 0 tiaan0 input with edge filter as selected by taanis[1:0] tiaam0 with edge filter selected for taam capture signal 1 tiaan1 input with edge filter as selected by taanis[3:2] tiaam1 with edge filter selected for taam capture interrupt inttaancc0 or inttaancc1 inttaamcc0 or inttaamcc1
326 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 10.6 operation timer aa can perform the following operations when not in cascade mode: note 1. to use the external trigger pulse output mode, one-shot pulse mode, or pulse width measurement mode, select a count clock by clearing the taaneee bit of the taanctl1 register to 0. 2. when the external event count function is used, set the edge detection of the tiaan0 capture input to "no edge detection" (taanis1 and taanis0 bits of taanioc1 register to "00"). operation taanest software trigger bit tiaan0 external trigger input taaneee count clock selection capture/ compare selection compare write interval timer mode invalid invalid internal/tiaan0 pin compare only any time write external event counter mode invalid invalid external only compare only any time write external trigger pulse output mode note valid valid internal only compare only reload one-shot pulse output mode note valid valid internal only compare only any time write pwm mode invalid invalid internal/tiaan0 pin compare only reload free-running mode invalid invalid internal/tiaan0 pin capture/compare selectable any time write pulse width measurement mode note invalid invalid internal only capture only not applicable
327 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 10.6.1 anytime write and reload taanccr0 and taanccr1 register rewrite is possible for timer aa during timer operation (taance = 1), but the write method (any time write, reload) differs depending on the mode. (1) anytime write when data is written to the taanccrm register during timer operation, it is transferred at any time to ccrm buffer register and used as the 16-bit counter comparison value. figure 10-4 flowchart of basic operation for anytime write note 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. m = 0, 1 s ta rt initial settings inttaancc0 output timer operation enable (taance=1). transfer of taanccr0, taanccr1 values to ccr0 and ccr1 buffer registers   rewrite taanccr0. transfer to ccr0 buffer register rewrite taanccr1. transfer to ccr1 buffer register match between ccr0 buffer register and 16-bit counter 16-bit counter clear and start
328 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-5 timing diagram for anytime write d01, d02: setting values of taanccr0 register (0000h to ffffh) d11, d12: setting values of taanccr1 register (0000h to ffffh) the above timing chart illustrates an example of the operation in the interval timer mode. d11 d11 d01 d01 d12 d02 d12 d01 d01 d02 d02 d11 d11 d12 d12 0000h 0000h taance = 1 16-bit counter taanccr0 taanccr1 ccr0 buffer register ccr1 buffer register inttaancc0 inttaancc1
329 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (2) reload when data is written to the taanccr0 and taanccr1 registers during timer operation, it is compared with the value of the 16-bit counter via the ccrm buffer register. the values of the taanccr0 and taanccr1 registers can be rewritten when taance = 1. so that the set values of the taanccr0 and taanccr1 registers are compared with the value of the 16-bit counter (the set values are reloaded to the ccrm buffer register), the value of the taanccr0 register must be rewritten and then a value must be written to the taanccr1 register before the value of the 16-bit counter matches the value of taanccr0. when the value of the taanccr0 register matches the value of the 16-bit counter, the values of the taanccr0 and taanccr1 registers are reloaded. whether the next reload timing is made valid or not is controlled by writing to the taanccr1 register. therefore, write the same value to the taanccr1 register when it is necessary to rewrite the value of only the taanccr0 register. figure 10-6 flowchart of basic operation for reload caution writing to the taanccr1 register includes an operation to enable reload. therefore, rewrite the taanccr1 register after rewriting the taanccr0 register. s ta rt initial setting enable timer operation (taance=1) transfer value of taanccrm to ccrm buffer register inttaancc0 output rewrite taanccr0. rewrite taanccr1. reload is enabled taanccr0 matches 16-bit counter. clear and start 16-bit counter. value of taanccrm is reloaded to ccrm buffer register.   
330 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 note 1. above flowchart illustrates an example of the pwm mode operation. 2. m = 0, 1 figure 10-7 timing chart for reload note reload is not performed because taanccr1 register is not written. d01, d02, d03: setting value of taanccr0 register (0000h to ffffh) d11, d12: setting value of taanccr1 register (0000h to ffffh) above flowchart illustrates pwm mode operation. d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 d 03 0000h d 11 d 12 taance = 1 note d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter taanccr0 taanccr1 inttaancc0 inttaancc1 ccr0 buff er register ccr1 buff er register note s ame value write d 02 d 12
331 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 10.6.2 interval timer mode (taanmd2 to taanmd0 = 000 b ) in the interval timer mode, an interrupt request signal (inttaancc0) is generated upon a match between the setting value of the taanccr0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. the taanccr0 register can be rewritten when taance = 1, and when a value is set to taanccr0 with a write instruction from the cpu, it is transferred to the ccr0 buffer register through any time write mode, and is compared with the 16-bit counter value. in the interval timer mode, the 16-bit counter is cleared only upon a match between the value of the 16-bit counter and the value of the ccr0 buffer register. 16-bit counter clearing using the taanccr1 register is not performed. however, the setting value of the taanccr1 register is transferred to the ccr1 buffer register and compared with the value of the 16-bit counter, and an interrupt request (inttaancc1) is output if these values match. in addition, toaa1n pin output is also possible by setting the taanoe1 bit to 1. when the taanccr1 register is not used, it is recommended to set ffffh as the setting value for the taanccr1 register. when performing timer output with the toaan1 pin, set the same values to the taanccr0 register and the taanccr1 register since the 16-bit timer counter cannot be cleared with the taanccr1 register. figure 10-8 flowchart of basic operation in interval timer mode s ta r t initial settings  clock selection (taanctl0: taanck s [2:0])  interval mode setting (taanctl1: taanmd[2:0] = 000b)  compare register setting (taanopt0: taancc s [1:0]= 00) timer operation enable (taance = 1) transfer of taanccr0, taanccr1 values to ccr0 buffer register and ccr1 buffer register match between 16-bit counter and ccr1 buffer register note inttaancc1 output match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start inttaancc0 output
332 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 note the 16-bit counter is not cleared when its value matches the value of taanccr1. figure 10-9 basic operation timing in interval timer mode when d1 > d2 > d3; only taanccr0 register value is written, and toaan0 and toaan1 are not output (taanoe0 = 0, taanoe1 = 0, taanol0 = 0, taanol1 = 1) note the 16-bit counter is not cleared when its value matches the value of taanccr1. d1, d2: setting values of taanccr0 register (0000h to ffffh) d3: setting value of taanccr1 register (0000h to ffffh) interval time (t dn )= (dn + 1) (count clock cycle) taance = 1 d 1 d 1 d 2 d 1 0000h 0000h d 3 d 3 d 2 d 1 d 2 d 3 d 3 d 3 ffffh 16-bit counter note taanccr0 taanccr1 inttaancc0 inttaancc1 toaan0 toaan1 t d1 t d1 t d2 l h ccr0 buffer register ccr1 buffer register
333 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-10 basic operation timing in interval timer mode when d1 = d2; taanccr0 and taanccr1 are not rewritten, and toaan0 and toaan1 are output (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 1) d1: setting value of taanccr0 register (0000h to ffffh) d2: setting value of taanccr1 register (0000h to ffffh) interval time (t dn ) = (dn + 1) (count clock cycle) 0000h d 1 d 1 ffffh taanccr0 taanccr1 inttaancc0 inttaancc1 toaan0 toaan1 0000h d 2 d 2 taance = 1 d 1 = d 2 d 1 = d 2 d 1 = d 2 t d1 = t d2 t d1 = t d2 t d1 = t d2 16-bit counter ccr0 buffer register ccr1 buffer register
334 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 when a new value is written to the taanccr0 register that is smaller than the taan counter value at that moment, the counter will run to up to ffffh and restart counting at 0000h. when the value of the counter then matches the taanccr0 register a compare event will occur.. figure 10-11 rewriting of the compare register with a smaller value than the current counter value d 1 d 1 d 2 d 1 d 2 d 2 ffffh 16-bit counter taanccr0 inttaancc0 taance bit d 2 rewrite of taanccr0 register
335 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 10.6.3 external event counter mode (taanmd2 to taanmd0 = 001 b ) in the external event count mode, the external event count input (tiaan0 pin input) is used as a count-up signal. regardless of the setting of the taaneee bit of the taanctl0 register, 16-bit timer/event counter aa counts up the external event count input (tiaan0 pin input) when it is set in the external event count mode. in the external event count mode, an interrupt request (inttaancc0) is generated when the set value of the taanccr0 register matches the value of the 16-bit counter, and the value of the 16-bit counter is cleared. when a value is set to the taanccr0 register with a write instruction from the cpu, it is transferred to the ccr0 buffer register through any time write, and is compared with the 16-bit counter value. in the external event counter mode, the 16-bit counter is cleared only upon a match between the value of the 16-bit counter and the value of the ccr0 buffer register. the 16-bit counter can not be cleared using taanccr1 register. however, the setting value of the taanccr1 register is transferred to the ccr1 buffer register and compared with the value of the 16-bit counter, and an interrupt request (inttaancc1) is output if these values match. moreover, toaanm pin output is also possible by setting the taanoem bit to 1. when performing timer output with the toaan1 pin, set the same values to taanccr0 register and taanccr1 register since the 16-bit counter cannot be cleared with ccr1 buffer register. the taanccr0 register can be rewritten when taance = 1. when taanccr1 register is not used, it is recommended to set taanccr1 register to ffffh.
336 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-12 flowchart of basic operation in external event counter mode note 1. selection of the taaneee bit has no influence. 2. the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccr1 buffer register. 3. m = 0, 1 start 16-bit counter matches ccr0 buffer register. clear and start 16-bit counter inttaancc0 output 16-bit counter matches ccr1 buffer register note 2 inttaancc1 output initial setting note 1  clock selection (taanctl0: taancks[2:0])  set external event count mode (taanctl1: taanmd[2:0] = 001b)  set valid edge (taanioc2: taanees[1:0])  compare register setting (taanccr0 and taanccr1) (taanopt0: taanccs[1:0]=00) timer operation enable (taance = 1) transfer of taanccr0, taanccr1 values to ccr0 buffer register and ccr1 buffer register
337 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-13 basic operation timing in external event counter mode when d1 > d2 > d3; rewrite taanccr0 only; toaan1 is not output (taanoe0 = 0, taanoe1 = 0, taanol0 = 0, taanol1 = 1) d1, d2: setting values of taanccr0 register (0000h to ffffh) d3: setting value of taanccr1 register (0000h to ffffh) number of event counts = (dn + 1) taance = 1 d 1 d 1 d 2 d 1 0000h 0000h d 3 d 3 d 2 d 1 d 2 d 3 d 3 d 3 ffffh 16-bit counter taanccr0 taanccr1 inttaancc0 inttaancc1 toaan1 ccr0 buff er register ccr1 buff er register h
338 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-14 basic operation timing in external event counter mode when d1 = d2; taanccr0 and taanccr1 are not rewritten, toaan1 is output (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 1) d1: setting value of taanccr0 register (0000h to ffffh) d2: setting value of taanccr1 register (0000h to ffffh) number of event count = (dn + 1) 0000h d 1 d 1 ffffh 16-bit counter taanccr0 taanccr1 inttaancc0 inttaancc1 toaan1 ccr0 buff er register ccr1 buff er register 0000h d 2 d 2 taance = 1 d 1 = d 2 d 1 = d 2 d 1 = d 2
339 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 10.6.4 external trigger pulse mode (taanmd2 to taanmd0 = 010 b ) when taance = 1 in the external trigger pulse mode, the 16-bit counter stops at ffffh and waits for a trigger condition (input of an external trigger (tiaan0 pin input) or sw trigger by setting of taanest bit)). when the counter detects the trigger condition. the duty factor of the signal output from the toaan1 pin is set by a reload register (taanccr1) and the period is set by a compare register (taanccr0). rewriting the taanccr0 and taanccr1 registers is enabled when ta a n c e = 1 . to ensure that the selected values of the taanccr0 and taanccr1 registers after rewriting are compared with the value of the 16-bit counter (reloaded to the ccrm buffer register), the taanccr0 register and then the taanccr1 register must be written before the value of the 16-bit counter matches the value of the taanccr0 register. when the value of the taanccr0 register later matches the value of the 16-bit counter, the values of the taanccr0 and taanccr1 registers are reloaded to the ccrm buffer register. whether the next reload timing is made valid or not is controlled by writing to the taanccr1 register. therefore, write the same value to the taanccr1 register when it is necessary to rewrite the value of only the taanccr0 register. reload is invalid when only the taanccr0 register is rewritten. to stop timer aa, clear taance to 0. if the edge of the external trigger (tiaan0 pin input) is detected more than once in the external trigger pulse mode, the 16-bit counter is cleared at the point of edge detection, and resumes counting up. to realize the same function as the external trigger pulse mode by using a software trigger instead of the external trigger input (tiaan0 pin input) (software trigger pulse mode), a software trigger is generated by setting the taanest bit of the taanctl1 register to 1. when using a software trigger, a square wave that has one cycle of the pwm waveform as half of its own cycle can also be outputed from the toaan0 pin. the waveform of the external trigger pulse is output from toaan1. a toggle output is produced from the toaan0 pin when the value of the taanccr0 register matches the value of the 16-bit counter. in the external trigger pulse mode, the capture function of the taanccr0 and taanccr1 registers cannot be used because these registers can be used only as compare registers. caution in the external trigger pulse mode, select the internal clock (taaneee bit of taanctl1 register = 0) for the count clock. note 1. for the reload operation when taanccr0 and taanccr1 are rewritten during timer operation, refer to ?pwm mode (taanmd2 to taanmd0 = 100 b )? on page 345 . 2. m = 0, 1
340 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-15 flowchart of basic operation in external trigger pulse output mode note the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccr1 buffer register. inttaancc1 output note 1 inttaancc0 output initial settings  clock selection (taanctl0: taancks[2:0], taanctl1: taaneee=0)  external trigger pulse output mode setting (taanctl1: taanmd[2:0] = 010b)  compare register setting (taanccr0, taa,ccr1) (taanopt0: taanccs[1:0] = 00) timer operation enable (taance = 1) transfer of taanccr0, taanccr1 values to ccr0 buffer register and ccr1 buffer register external trigger (tiaan0 pin) input, or taanest = 1 16-bit counter start match between 16-bit counter and ccr1 buffer register note 1 match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start start 16-bit counter clear & start external trigger pin input (tiaan0) note
341 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-16 basic operation timing in external trigger pulse output mode (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 0) note the 16-bit counter is not cleared when it matches the ccr1 buffer register. d01, d02: setting value of taanccr0 register (0000h to ffffh) d11, d12: setting value of taanccr1 register (0000h to ffffh) duty of toaan1 output = (set value of taanccr1 register) / (set value of taa0ccr0 register) cycle of toaan1 output = (set value of taanccr0 register + 1) ? (count clock cycle) taance = 1 0000h d 01 d 11 d 01 d 02 d 12 d 01 d 02 d 02 ffffh 16-bit counter note d 11 d 12 0000h d 12 d 11 d 11 external trigger (tiaan0 pin) taanccr0 taanccr1 toaan1 toaan0 ccr0 buffer register ccr1 buffer register
342 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 10.6.5 one-shot pulse mode (taanmd2 to taanmd0 = 011 b ) when taance is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the taanest bit (to 1) or a trigger that is input when the edge of the tiaan0 pin is detected, while holding ffffh. when the trigger is input, the 16-bit counter starts counting up. when the value of the 16-bit counter matches the value of the ccr1 buffer register that has been transferred from the taan ccr1 register, toaan1 goes high. when the value of the 16-bit counter matches the value of the ccr0 buffer register that has been transferred from the taanccr0 register, toaan1 goes low, and the 16-bit counter is cleared to 0000h and stops. input of a second or subsequent trigger is ignored while the 16-bit counter is operating. be sure to input a second trigger while the 16-bit counter is stopped at 0000h. in the one shot pulse mode, rewriting the taanccr0 and taanccr1 registers is enabled when taance = 1. the set values of the taanccr0 and taanccr1 registers become valid after a write instruction from the cpu is executed. they are then transferred to the ccr0 and ccr1 buffer registers, and compared with the value of the 16-bit counter. the waveform of the one- shot pulse is output from the toaan1 pin. the toaan0 pin produces a toggle output when the value of the 16-bit counter matches the value of the taanccr0 register. in the one-shot pulse mode, the taanccr0 and taanccr1 registers function only as compare registers. they cannot be used as capture registers. caution 1. in the one-shot pulse mode, select the internal clock (taaneee bit of taanctl1 register = 0) as the count clock. 2. in the one-shot pulse mode, it is prohibited to set the taanccr1 register to 0000h.
343 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-17 flowchart of basic operation in one-shot pulse mode note 1. only the taanest bit of the taanctl1 register can be rewritten during the timer operation (taance = 1). 2. the 16-bit counter is not cleared upon a match between the values of the 16-bit counter and the ccr1 buffer register. caution the 16-bit counter is not cleared when a trigger input is performed during the count-up operation of the 16-bit counter. star t initial settings  clock selection (taanctl1: taaneee = 0) (taanctl0: taancks[2:0])  one-shot pulse mode setting (taanctl1: taanmd[2:0]=011)  compare register setting (taanccr0, taanccr1) timer operation enable (taance = 1) transfer of taanccr0, taanccr1 values to ccr0 buffer register and ccr1 buffer register match between 16-bit counter and ccr1 buffer register note 2 match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start trigger wait status, 16-bit counter in standby at ffffh external trigger (tiaan0 pin) input, or taanest = 1 16-bit counter start trigger wait status, 16-bit counter in standby at 0000h inttaancc0 output inttaancc1 output note 1
344 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-18 timing of basic operation in one-shot pulse mode (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 0) note the 16-bit counter starts counting up when either taanest = 1 is set or the external trigger (tiaan0) is input. d0: setting value of taanccr0 register (0000h to ffffh) d1: setting value of taanccr1 register (0000h to ffffh) active level period of toaan1 pin output is (setting value of taanccr0 - setting value of taanccr1 + 1) count clock period output delay period = (setting value of taanccr 1 register) count clock period taance = 1 taane s t = 1 d 1 d 0 d 1 d 0 d 1 d 0 d 0 d 0 d 1 d 1 ffffh 16-bit counter external trigger (tiaan0 pin) taanccr0 inttaancc0 taanccr1 inttaancc1 toaan1 toaan0 ccr0 buffer register cc1 buffer register 0000h 0000h note
345 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 10.6.6 pwm mode (taanmd2 to taanmd0 = 100 b ) in the pwm mode, taan capture/compare register 1 (taanccr1) is used to set the duty factor and taan capture/compare register 0 (taanccr0) is used to set the cycle. by using these two registers and operating the timer, variable- duty pwm is output. rewriting the taanccr0 and taanccr1 registers is enabled when ta a n c e = 1 . so that the set values of the taanccr0 and taanccr1 registers are compared with the value of the 16-bit counter (reloaded to the ccr0 and ccr1 buffer registers), the taanccr0 register must be rewritten and then a value must be written to the taanccr1 register before the value of the 16-bit counter matches the value of the taanccr0 register. the values of the taanccr0 and taanccr1 registers are reloaded when the value of the taanccr0 register later matches the value of the 16-bit counter. whether the next reload timing is made valid or not is controlled by writing to the taanccr1 register. therefore, write the same value to the taanccr1 register even when only the value of the taanccr0 register needs to be rewritten. reload is invalid when only the value of the taanccr0 register is rewritten. to stop timer aa, clear taance to 0. the waveform of pwm is output from the toaan1 pin. the toaan0 pin produces a toggle output when the 16-bit counter matches the taanccr0 register. in the pwm mode, the taanccr0 and taanccr1 registers are used only as compare registers. they cannot be used as capture registers.
346 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-19 flowchart of basic operation in pwm mode when values of taanccr0, taanccr1 registers are not rewritten during timer operation s ta rt inttaancc0 output enable timer operation (taance = 1) transfer value of taanccrm register to ccrm buffer register 16-bit counter matches taanccr1. toaan1 outputs inactive level. 16-bit counter matches taanccr0. clear and start 16-bit counter. toaan1 outputs active level. inttaancc1 output initial setting ? s elect clock. (taanctl0: taanck s [2:0]) ? s et pwm mode. (taanctl1: taanmd[2:0] = 100b) s et compare register. (taanccr0, taanccr1) ?
347 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-20 flowchart of basic operation in pwm mode when values of taanccr0, taanccr1 registers are rewritten during timer operation note 1. the timing of <2> in the above flowchart may differ depending on the rewrite timing of steps <1> and <3> and the value of taanccr1, but make sure that step <3> comes after step <1>. 2. m = 0, 1 s ta rt inttaancc0 output 16-bit counter matches ccr1 buffer register. toaan1 outputs inactive level. enable timer operation (taance = 1) transfer value of taanccrm register to ccrm buffer register 16-bit counter matches taanccr1. toaan1 outputs inactive level. rewrite taanccr0. rewrite taanccr1. 16-bit counter matches taanccr0. clear and start 16-bit counter. toaan1 outputs active level. inttaancc1 output reload is enabled note 1 <1> <2> <3> inttaancc0 output inttaancc1 output initial setting ? s elect clock. (taanctl0: taanck s [2:0]) ? s et pwm mode. (taanctl1: taanmd[2:0] = 100b) s et compare register. (taanccr0, taanccr1) ? ccr0 buffer register matches 16-bit counter. ? clear and start 16-bit counter. ? value of taanccrm is reloaded to ccrm buffer register. ?
348 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-21 basic operation timing in pwm mode when rewriting taanccr1 value (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 0) d00: set value of taanccr0 register (0000h to ffffh) d10, d11, d12, d13: set value of taanccr1 register (0000h to ffffh) duty of toaan1 output = (set value of taanccr1 register) / (set value of taanccr0 register + 1) cycle of toaan1 output = (set value of taanccr0 register + 1) x (count clock cycle) toggle width of toaan0 output = (set value of taanccr0 register + 1) x (count clock period) taance = 1 16-bit counter taanccr0 taanccr1 toaan1 toaan0 ccr0 buffer register ccr1 buffer register 0000h 0000h d 10 d 11 d 12 d 13 d 00 d 00 d 00 d 00 d 00 d 00 d 10 d 10 d 10 d 11 d 11 d 12 d 12 d 13 ffffh
349 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-22 basic operation timing in pwm mode when taanccr0, taanccr1 values are rewritten (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 0) note reload is not performed because the taanccr1 register was not rewritten. d00, d01, d02, d03: setting values of taanccr0 register (0000h to ffffh) d10, d11, d12, d13: setting values of taanccr1 register (0000h to ffffh) duty of toaan1 output = (set value of taanccr1 register) / (set value of taanccr0 register + 1) cycle of toaan1 output = (set value of taanccr0 register + 1) x (count clock cycle) toggle width of toaan0 output = (set value of taanccr0 register + 1) x (count clock cycle) note to output a 0% duty pwm signal set the taanccr1 register to 0. to output a 100% duty pwm signal set the taanccr1 register to the value of the ccr0 register +1. do not set a value of ffffh to the ccr1 register. taance = 1 16-bit counter taanccr0 taanccr1 toaan1 toaan0 0000h 0000h d 10 d 11 d 12 d 12 d 00 d 00 d 10 d 10 d 11 d 11 d 11 d 12 d 12 d 12 d 00 d 01 d 02 d 03 d 01 d 01 d 01 d 02 d 02 d 03 ffffh s ame value write note ccr0 buffer register ccr1 buffer register
350 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 10.6.7 free-running mode (t aanmd2 to taanmd0 = 101 b ) in the free-running mode, both the interval function and the compare function can be realized by operating the 16-bit counter as a free-running counter and selecting capture/compare operation with the taanccs1 and taanccs0 bits. the settings of the taanccs1 and taanccs0 bits of the taanopt0 register are valid only in the free-running mode.  using taanccr1 register as compare register an interrupt is output upon a match between the 16-bit counter and the ccr1 buffer register in the free-running mode. rewrite during compare timer operation is enabled and performed with any time write mode. (once the compare value has been written, synchronization with the internal clock is done and this value is used as the 16-bit counter comparison value.) when timer output (toaan1) has been enabled, toaan1 performs toggle output upon a match between the 16-bit counter and the ccr1 buffer register.  using taanccr1 register as capture register the value of the 16-bit counter is saved to the taanccr1 register upon tiaan1 pin edge detection.  using taanccr0 register as compare register an interrupt is output upon a match between the 16-bit counter and the ccr0 buffer register in the free-running mode. rewrite during compare timer operation is enabled and performed with any time write mode. (once the compare value has been written, synchronization with the internal clock is done and this value is used as the 16-bit counter comparison value.) when timer output (toaan0) has been enabled, toaan0 performs toggle output upon a match between the 16-bit counter and the ccr0 buffer register.  using taanccr0 register as capture register the value of the 16-bit counter is saved to the taanccr0 register upon tiaan0 pin edge detection. caution when the taaneee bit of aanctl1 register is set to 1 and the count clock is set to the external event count input, the taanccr0 register cannot be used as the capture register. taanccs1 operation 0 use taanccr1 register as compare register 1 use taanccr1 register as capture register taanccs0 operation 0 use taanccr0 register as compare register 1 use taanccr0 register as capture register
351 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-23 flowchart of basic operation in free-running mode s tart initial settings  clock selection (taanctl0: taanck s [2:0])  ta a n c c s [1:0] setting timer operation enable (taance = 1) free-running mode setting (taanctl1: taanmd[2:0] = 101b) taancc s [1:0] = 00 ta a n c c s [1:0] = 01 taancc s [1:0] = 10 taancc s [1:0] = 11 transfer of taanccr0 and taanccr1 values to ccr0 and ccr1 buffer registers timer operation enable (taance = 1) transfer of taanccr1 value to ccr1 buffer register timer operation enable (taance = 1) transfer of taanccr0 value to ccr0 buffer register timer operation enable (taance = 1) 16-bit counter overflow 16-bit counter overflow 16-bit counter overflow 16-bit counter overflow tiaan0 edge detection, capture of 16-bit counter value to taanccr0. tiaan1 edge detection, capture of 16-bit counter value to taanccr1. match between ccr1 buffer and 16-bit counter match between ccr0 buffer and 16-bit counter tiaan1 edge detection, capture of 16-bit counter value to taanccr1. tiaan0 edge detection, capture of 16-bit counter value to taanccr0. match between ccr0 buffer and 16-bit counter match between ccr1 buffer and 16-bit counter tiaan0 edge detection setting (taani s 1, taani s 0) tiaan1 edge detection setting (taani s 3, taani s 2) tiaan0, tiaan1 edge det. setting (taani s [3:0])
352 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 (1) when taanccs1 = 0, and taanccs0 = 0 settings (interval function description, compare function) when taance = 1 is set, the 16-bit c ounter counts from 0000h to ffffh and the free-running count-up operation continues until taance = 0 is set. in this mode, when a value is written to the taanccr0 and taanccr1 registers, they are transferred to the ccr0 buffer register and the ccr1 buffer register (any time write mode). in this mode, no one-shot pulse is output even when an one-shot pulse trigger is input. moreover, when taanoem = 1 is set, toaanm performs toggle output upon a match between the 16-bit counter and the ccrm buffer register. figure 10-24 basic operation timing in free-running mode (taanccs1 = 0, taanccs0 = 0) (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 0) d00, d01: setting values of taanccr0 register (0000h to ffffh) d10, d11: setting values of taanccr1 register (0000h to ffffh) toaan0 output toggle width = (setting values of taanccr0 register) (count clock cycle) toaan1 output toggle width = (setting values of taanccr1 register) toaanm output goes high when counting is started. note m = 0, 1 taance = 1 0000h d 00 d 00 d 00 d 00 d 11 d 11 d 01 d 01 d 01 ffffh 16-bit counter taanccr0 toaan0 toaan1 inttaanov taanovf clear by writing 0 to taanovf clear by writing 0 to taanovf inttaancc0 match interrupt inttaancc1 match interrupt taanccr1 ccr0 buffer register ccr1 buffer register 0000h d 10 d 10 d 10 d 11 d 11
353 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (2) when taanccs1 = 1 and taanccs0 = 1 settings (capture function description) when taance = 1, the 16-bit counter counts from 0000h to ffffh and free- running count-up operation continues until taance = 0 is set. during this time, values are captured by capture trigger operation and are written to the taanccr0 and taanccr1 registers. regarding capture close to the overflow (ffffh), judgment is made using the overflow flag (taanovf). however, if overflow occurs twice (two or more free- running cycles), the capture trigger interval cannot be judged with the taanovf flag. in this case, the system should be revised. figure 10-25 basic operation timing in free-running mode (taanccs1 = 1, taanccs0 = 1) (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 0) d00, d01, d02, d03: values captured to taanccr0 register (0000h to ffffh) d10, d11, d12: values captured to taanccr1 register (0000h to ffffh) tiaan0: set to rising edge detection (taanis1, taanis0 = 01) tiaan1: set to falling edge detection (taanis3, taanis2 = 10) taance = 1 d 00 d 10 d 11 d 12 d 00 d 01 d 03 d 02 d 12 d 11 d 10 d 02 d 03 d 01 ffffh 0000h 0000h 16-bit counter taanccr0 tiaan1 tiaan0 inttaanov inttaancc0 capture interrupt inttaancc1 capture interrupt taanccr1 toaan1 toaan0 l l
354 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 (3) when taanccs1 = 1 and taanccs0 = 0 when taance = 1 is set, the counter counts from 0000h to ffffh and free- running count-up operation continues until taance = 0 is set. the taanccr0 register is used as a compare register. an interrupt signal is output upon a match between the value of the 16-bit counter and the setting value transferred to the ccr0 buffer register from th e taanccr0 register as an interval function. even if taanoe1 = 1 to realize the output function, taanccr1 register cannot control toaan1 because it is used as capture register. figure 10-26 basic operation timing in free-running mode (taanccs1 = 1, taanccs0 = 0) (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 0) d00, d01: setting compare values of taanccr0 register (0000h to ffffh) d10, d11, d12, d13, d14, d15: values captured to taanccr1 register (0000h to ffffh) tiaan1: set to detection of both rising and falling edges (taanis3, taanis2 = 11) d 11 d 10 0000h d 13 d 15 d 14 d 12 taance=1 d 00 d 00 d 01 d 10 d 00 d 01 d 11 d 13 d 12 d 14 d 15 d 00 d 01 0000h ffffh 16-bit counter taanccr0 taanccr1 inttaancc0 mactch interrupt ccr0 buffer register tiaan1
355 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (4) when taanccs1 = 0 and taancs0 = 1 when taance is set to 1, the 16-bit counter counts from 0000h to ffffh and free-running count-up operation continues until taance = 0 is set. the taanccr1 register is used as a compare register. an interrupt signal is output upon a match between the value of the 16-bit counter and the setting value of the taanccr1 register as an interval function. when taanoe1 = 1 is set, toaan1 performs toggle output upon mach between the value of the 16-bit counter and the setting value of the taanccr1 register. even if taanoe0 = 1 to realize the output function, taanccr0 register cannot control toaan0 because it is used as capture register. figure 10-27 basic operation timing in free-running mode (taanccs1 = 0, taanccs0 = 1) (taanoe0 = 1, taanoe1 = 1, taanol0 = 0, taanol1 = 0) d00, d01, d02, d03: values captured to taanccr0 register (0000h to ffffh) d10, d11, d12: setting compare value of taanccr1 register (0000h to ffffh) tiaan0: set to falling edge detection (taanis1, taanis0 = 10) (5) overflow flag when the counter overflows from ffffh to 0000h in the free-running mode, the overflow flag (taanovf) is set to 1 and an overflow interrupt (inttaanov) is output. the overflow flag is cleared by the cpu when writing 0 to it. taance = 1 d 00 d 11 d 11 d 10 d 10 d 12 d 12 d 10 d 01 d 11 d 02 d 12 d 03 d 11 d 00 d 02 d 03 d 01 ffffh 0000h 0000h 16-bit counter taanccr0 toaan1 tiaan0 toaan0 l inttaanov inttaancc0 capture interrupt inttaancc1 match interrupt taanccr1 ccr1 buffer register
356 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 10.6.8 pulse width measurement mode (taanmd2 to taanmd0 = 110b) in the pulse width measurement mode, free-running count is performed. the value of the 16-bit counter is saved to capture register 0 (taanccr0), or capture register 1 (taanccr1) respectively, and the 16-bit counter is cleared upon edge detection of the tiaan0 pin, or tiaan1 respectively. the external input pulse width can be measured as a result. however, when measuring a large pulse width that exceeds 16-bit counter overflow, perform judgment with the overflow flag, e.g by counting the overflow count by using the overflow interrupt. depending on the selected capture input sources and specified edge detection three different measurement methods can be applied. 1. pulse period measurement 2. alternating pulse width and pulse space measurement. 3. simultaneous pulse width and pulse space measurement: both capture inputs are required to measure pulse width and pulse space simultaneously. the measurements methods are explained in the following sub-chapters. caution in the pulse width measurement mode, select the internal clock (taaneee of taanctl1 register = 0).
357 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (1) pulse period measurement the pulse period of a signal can be measured in the pulse width measurement mode, when the edge detection of one of the inputs tiaan0 and tiaan1 is set either to ?rising edge? or ?falling edge?. the detection of the other input should be set to ?no edge detection?. by detection of the specified edge the resulting value is captured in the corresponding capture register (taanccr0 or taanccr1), and the timer is cleared and restarts counting. figure 10-28 flowchart of pulse period measurement note 1. external pulse input is possible for both tiaan0 and tiaan1, but only one should be selected for the pulse period measurement. specify either ?rising edge? or ?falling edge? for edge detection. specify the edge of the external input pulse that is not used as ?no edge detection?. 2. m = 0, 1 s tart initial settings ? clock selection (taanctl0: taanck s 2 to taanck s 0) ? pulse width measurement mode setting (taanctl1: taanmd2 to taanmd0 = 110b) ? capture register setting (taanccr0, taanccr1) timer operation enable (taance = 1) s pecified edge input to tiaanm (rising or falling edge), capture of value to taanccrm, 16-bit counter clear & start tiaan1/tiaan0 edge detection setting note 1 (taani s 3 to taani s 0)
358 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-29 basic operation timing of pulse period measurement (taanoe0 = 0, taanoe1 = 0, taanol0 = 0, taanol1 = 0) d 00 , d 01 , d 02 : values captured to taanccr0 register (0000h to ffffh) tiaan0: set to detection of rising edge (taanis1, taanis0 = 01b) tiaan1: set to no edge detection (taanis3, taanis2 = 00b) d 00 d 00 d 01 d 01 d 02 d 02 ffffh 0000h 16-bit counter tiaan0 taancc0 inttaanccr0 inttaanov taanovf ffffh taance = 1 cleared by writing 0 from cpu
359 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (2) alternating pulse width and pulse space measurement the pulse period of a signal can be measured in the pulse width measurement mode alternating in one capture register, when the edge detection of one of the inputs tiaan0 and tiaan1 is set to ?both rising and falling edges?. the detection of the other input should be set to ?no edge detection?. by detection of a falling or rising edge the resulting value is captured in the corresponding capture register (taanccr0 or taanccr1), and the timer is cleared and restarts counting. figure 10-30 flowchart of alternating pulse width and pulse space measurement note 1. external pulse input is possible for both tiaan0 and tiaan1, but only one should be selected for the alternating pulse width and pulse space measurement. specify ?both rising and the falling edges? for edge detection. specify the edge of the external input pulse that is not used as ?no edge detection?. 2. m = 0, 1 s tart initial settings ? clock selection (taanctl0: taanck s 2 to taanck s 0) ? pulse width measurement mode setting (taanctl1: taanmd2 to taanmd0 = 110b) ? capture register setting (taanccr0, taanccr1) timer operation enable (taance = 1) rising edge input to tiaanm, capture of value to taanccrm, 16-bit counter clear & start tiaan1/tiaan0 edge detection setting note 1 (taani s 3 to taani s 0) falling edge input to tiaanm, capture of value to taanccrm, 16-bit counter clear & start
360 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-31 basic operation timing of alternating pulse width and pulse space measurement (taanoe0 = 0, taanoe1 = 0, taanol0 = 0, taanol1 = 0) d 00 , d 01 , d 02 , d 03 , d 04 : values captured to taanccr0 register (0000h to ffffh) tiaan0: set to detection of both rising and falling edges (taanis1, taanis0 = 11b) tiaan1: set to no edge detection (taanis3, taanis2 = 00b) pulse width = captured value count clock cycle if the valid edge is not input even when the 16-bit counter counted up to ffffh, an overflow interrupt request signal (nttaanov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (taanopt0.taanovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pulse width can be calculated as follows. pulse width = (10000h taanovf bit set (1) count + captured value) count clock cycle d 00 d 00 d 01 d 01 d 02 d 02 ffffh 0000h 16-bit counter tiaan0 taanccr0 inttaancc0 inttaanov taanovf ffffh taance = 1 d 03 d 03 d 04 d 04 cleared by writing 0 from cpu
361 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 (3) simultaneous pulse width and pulse space measurement pulse width and pulse space can be measure simultaneously in the pulse width measurement mode, when the signal is input to both inputs tiaan0 and tiaan1, where both inputs detect opposite edges. by detection of the specified edge the resulting values of pulse width or pulse space are captured in the corresponding capture registers (taanccr0, taanccr1), and the timer is cleared and restarts counting. figure 10-32 flowchart of simultaneous pulse width and pulse space measurement note 1. external pulse input must be input to both tiaan0 and tiaan1. specify ?rising edge? for edge detection of first input, and ?falling edge? for the second input, or vice versa. 2. x = 0, 1 y = 0 when x = 1; y = 1 when x = 0 s tart initial settings ? clock selection (taanctl0: taanck s 2 to taanck s 0) ? pulse width measurement mode setting (taanctl1: taanmd2 to taanmd0 = 110b) ? capture register setting (taanccr0, taanccr1) timer operation enable (taance = 1) rising edge input to tiaanx, capture of value to taanccrx, 16-bit counter clear & start tiaan1/tiaan0 edge detection setting note 1 (taani s 3 to taani s 0) falling edge input to tiaany, capture of value to taanccry, 16-bit counter clear & start
362 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-33 basic operation timing of simultaneous pulse width and pulse space measurement (taanoe0 = 0, taanoe1 = 0, taanol0 = 0, taanol1 = 0) note the signal to measure has to be assigned to both inputs, tiaan0 and tiaan1. d 00 , d 01 , d 02 : values captured to taanccr0 register (0000h to ffffh) d 10 , d 11 : values captured to taanccr1 register (0000h to ffffh) tiaan0: set detection to rising edge (taanis1, taanis0 = 01b) tiaan1: set detection to falling edge (taanis3, taanis2 = 10b) d 00 d 10 d 01 ffffh 16-bit counter tiaan0, tiaan1 note ffffh taance = 1 d 11 d 02 d 00 d 01 d 02 0000h taanccr0 d 10 d 11 0000h taanccr1 inttaancc0 inttaancc1 inttaanov taanovf cleared by writing 0 from cpu
363 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 10.6.9 32-bit capture in free-running cascade mode two timer aa (taa0 in combination with taa1, or taa2 in combination with taa3) can be cascaded to operate as a 32-bit capture timer. in cascade mode, the timer with the lower number (taa0 or taa2) is used to control the operation (master timer). both cascaded timers have to be initialized as free- running timers. figure 10-34 block diagram of taam and taan in 32-bit capture mode taamccr0 counter control trigger control taamcnt0 16-bit counter taamctl1 taamopt0 taamioc1 taamioc0 taamce taamce inttaamcc0 taamctl0 taamioc2 s elector s elector s elector edge detector edge detector inttaamov inttaamcc1 toaam0 toaam1 taamioc3 taamopt1 taamc s e=0 edge detector edge detector taanccr0 taanccr1 counter control trigger control taancnt0 clear 16-bit counter taanctl1 taanopt0 taanioc0 taance inttaancc0 s elector s elector inttaanov inttaancc1 output controller capture/compare selection function taanioc3 taanopt1 taanc s e=1 taamtrg1 taamtrg0 taamov taamce taamce inttaamov taamtrg1 taamtrg0 tmaan tmaam taamccr1 clear ccr1 buffer register load load output controller capture/compare selection function load load ccr1 buffer register ccr0 buffer register ccr0 buffer register input circuit (see separate figure) note 2 f xp1 or f xp2 f xp1 /2 or f xp2 /2 f xp1 /4 or f xp2 /4 f xp1 /8 f xp1 /16 f xp1 /32 f xp1 /64 f xp1 /128 or f xt
364 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 note 1. m = 0, 2 n = 1, 3 2. the 32-bit capture in cascade free-running mode is not available for taa4. 3. explanation of signals can be found in figure 10-1 on page 307 . 4. block diagrams of the input circuits can be found in figure 10-2 on page 308 to figure 10-3 on page 308 , figure 10-34 shows the block diagram of taam and taan in cascade mode. signals that are irrelevant in cascade mode are not shown, the connections to the internal bus are also hidden for better readability of the image, as figure 10-1 on page 307 can be used for a in-depth look of each timer. note cascading of two taa is only allowed for free-running mode with both capture/ compare registers set to capture mode. proper operation of taam and taan is not guaranteed for any other setting. figure 10-35 shows the recommended flow for setting up taam and taan in cascade mode. as taam is used for general control, taan is set up first and set in cascaded operation by setting the taancse bit to 1. then taam is initialized by selecting the proper clock setting and capture trigger input. only tiaam0 and tiaam1 can be used as external capture trigger. note when cascading taam and taan, set taancse=1 and taamcse=0. operation starts when the count enable flag of taam (taamce) is set to 1. the counter of taam is used for the lower 16-bit of the 32-bit count value, while the upper 16-bit are handled by taan. whenever the counter of taam overflows, the counter is cleared to 0, interrupt inttaamov is generated and the counter of taan is incremented by 1. when the counter of taan overflows, the counter is also cleared to 0 and interrupt inttaanov is generated. when a capture trigger 0/1 is detected by taam, a capture of the lower 16-bit counter value to taamccr0/1 and of the upper 16-bit counter value to taanccr0/1 at the same time. the interrupts of the taam will indicate the capture (inttaamcc0/1). figure 10-36 on page 366 shows an example of a 32-bit capture timing.
365 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-35 basic flow of 32-bit capture mode initial settings for upper 16-bit timer (tmaan)   free-running mode setting (taanctl1: taanmd[2:0] = 101b) timer operation enable (taamce = 1) both timer (tmaam, tmaan) start upper 16-bit counter overflow lower 16-bit counter overflow tiaam1 edge detection, capture of lower 16-bit counter value to taamccr1 and upper 16-bit counter value to taanccr1. tiaam0 and tiaam1 edge detection setting (taami s [1:0] and taami s [3:2]) s ta rt s et capture operation (taanopt0: taancc s [1:0] = 11b)  s et cascade operation (taanopt1: taanc s e = 1) initial settings for lower 16-bit timer (tmaam)   free-running mode setting (taamctl1: taammd[2:0] = 101b) s et capture operation (taamopt0: taamcc s [1:0] = 11b)  clock selection (taamctl0: taamck s [2:0]) tiaam0 edge detection, capture of lower 16-bit counter value to taamccr0 and upper 16-bit counter value to taanccr0. inttaamcc1 output inttaamcc0 output inttaamov output inttaanov output
366 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 figure 10-36 basic timing of 32-bit capture mode note m = 0, 2 n = 1,3 as the 32-bit resolution is achieved by cascading two individual taa, a direct read of the 32-bit capture value is not possible. to ensure that the data is not corrupted during read operation, the following procedure for reading needs to be followed: taamce = 1 d 10 d 11 d 12 d 00 d 01 d 03 d 02 d 12 d 11 d 10 01 ffffh 0000h 16-bit counter tmaam taamccr0 tiaam1 tiaam0 inttaamov inttaamcc0 inttaamcc1 taamccr1 d 00 d 02 d 03 d 0000h toaam1 toaan1 toaam0 toaan0 l l 16-bit counter tmaan ffffh 0000h 0001h 0002h 0000h taanccr0 0000h 0001h 0001h 0002h 0000h taanccr1 0002h 0002h 0000h l inttaanov
367 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00 figure 10-37 flow of 32-bit read (capture or counter value) disabling the capture interrupt (inttaamccr0/1) is not required if the read sequence is done in the interrupt service routine, as nesting of the same interrupt is not possible. however, if the read operation is done in a normal routine while the interrupt signal is also assigned to a interrupt service routine, disabling the interrupt is mandatory, otherwise corrupted data might be read. the same flow can be used for reading the timer counter value. in this case the relevant interrupt which pending flags needs to be cleared and checked is inttaamov. please note that you can either read the upper 16-bit counter (taancnt) and then the lower 16-bit counter (taamcnt) or vice versa. while both methods work, the read values can be slightly different, as the count operation of the lower 16-bit counter continues while the upper 16-bit timer is read:  when reading the upper 16-bit first, the lower 16-bit might be incremented during that read.  when reading the lower 16-bit first, the value might be already ?old? after reading the upper 16-bit. the software programmer needs to decide which method is considered better for the application. no ye s s ta rt inttaamccr0/1 pending? end disable inttaamccr0/1 read tmaanccr0/1 and store as upper 16-bit capture value read tmaamccr0/1 and store as lower 16-bit capture value. clear inttaamccr0/1 pending flag enable inttaamccr0/1
368 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00 10.6.10 capture operation on delayed input clock if during capture operation the first capture event triggers before the first edge of the count clock occurs a value of ffffh and not a value of 0000h may be stored in the taanccrm registers. ffffh 0001h 0000h 16-bit counter count clock taanccr0 taance ffffh tiaan0 sampling clock 0000h capture trigger input capture trigger input ffffh 0002h 0000h 16-bit counter count clock taanccr0 taance ffffh tiaan0 sampling clock 0000h capture trigger input capture trigger input (b) pulse-width measurement mode (a) free running mode
369 16-bit timer/event counter aa chapter 10 user?s manual u18743ee1v2um00
370 chapter 10 16-bit timer/event counter aa user?s manual u18743ee1v2um00
371 user?s manual u18743ee1v2um00 chapter 11 16-bit interval timer m the microcontroller includes a 16-bit interval timer m (tmm0). 11.1 features timer m (tmm) supports only a clear & start mode. it does not support a free- running mode. to use timer m in a manner equivalent to in the free-running mode, set the compare register to ffff h and start the 16-bit counter. a match interrupt will occur when the timer overflows.  interval function  clock selection 8  simple counter 1 (the simple counter is a counter that does not use a counter read buffer. this counter cannot be read during timer count operation.)  simple compare 1 (the simple compare register is a register that does not use a compare write buffer. no data can be written to this compare register during timer count operation.)  compare match interrupt 1 11.2 configuration tmm consists of the following hardware. table 11-1 configuration of tmm item configuration timer register 16-bit counter register tmm0 compare register 0 (tm0cmp0) control register tmm0 control register 0 (tm0ctl0)
372 chapter 11 16-bit interval timer m user?s manual u18743ee1v2um00 figure 11-1 block diagram of timer m 11.3 timer m registers (1) tm0cmp0 - tmm0 compare register 0 the tm0cmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000 h . caution changing the tm0cmp0 register contents is prohibited while the timer is operating (tm0ce = 1). thus rewriting with the same value is permitted. tm0ctl0 internal bus f xp1 f xp1 /2 f xp1 /4 f xp1 /64 f rh /8 or f xp1 /512 intwt f rl /8 f xt 16-bit counter clear inttm0eq 0 tm0cmp0 tm0ce tm0cks2 tm0cks1 tm0cks0 selector controller address: ffff f694 h 1514131211109876543210 r/winitial value tm0cmp0 r/w 0000 h
373 16-bit interval timer m chapter 11 user?s manual u18743ee1v2um00 (2) tm0ctl0 - tmm0 control register 0 the tm0ctl0 register is an 8-bit register that controls the operation of tmm. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00 h . caution changing the tm0ctl0.tm0cks[2:0] bits is prohibited while the timer is operating (tm0ce = 1). thus rewriting of these bits with the same value is permitted. the tm0ctl.tm0ce bit can be changed at any time. note prsi can be set by the option bytes: refer to ?flash memory? on page 259 for details. caution 1. set tm0cks2 to tm0cks0 bits at tm0ce = 0. when the tm0ce bits is set from 0 to 1, the tm0cks2 to tm0cks0 bits can be set at the same time. 2. set bit 6-3 to 0. address: ffff f690 h symbol76543 2 1 0r/w after reset tm0ctl0 tm0ce 0 0 0 0 tm0cks2 tm0cks1 tm0cks0 r/w 00 h tm0ce control of operation of timer m0 0 disable internal operating clock operation (asynchronously reset tmm0). 1 enable internal operating clock operation. the tm0ce bit controls the internal operating clock and asynchronously reset of tmm0. when this bit is cleared to 0, the internal operating clock of tmm is stopped, and tmm0 is asynchronously reset. when the tm0ce bit is set to 1, the internal operating clock is enabled within two input clocks, and the timer counts up. selcnt0 register a a) refer to chapter ?clock generator? on page 179 for details of selcnt0 register. tm0ctl0 register selection of internal count clock sel07 bit tm0cks2 tm0cks1 tm0cks0 input prsi = 0 prsi = 1 x 000f xp1 f xx f xx /2 x 001f xp1 /2 f xx /2 f xx /4 x 010f xp1 /4 f xx /4 f xx /8 x 011f xp1 /64 f xx /64 f xx /128 0 100 f xp1 /512 f xx /512 f xx /1024 1 f rh /8 x 101 intwt x 110 f rl /8 x 111 f xt
374 chapter 11 16-bit interval timer m user?s manual u18743ee1v2um00 note f xx : main system clock frequency f rl : low frequency internal oscillator clock frequency (240 khz) f rh : high frequency internal oscillator clock frequency (8 mhz) f xt : sub oscillator frequency r 11.4 operation 11.4.1 interval timer mode in the interval timer mode, a match interrupt signal (inttm0eq0) is output when the value of the 16-bit counter matches the value of tmm0 compare register 0 (tm0cmp0). at the same time, the counter is cleared to 0000 h and starts counting up. when ffff h is set to the tm0cmp0 register, timer m performs an operation similar to that in the free-running mode. figure 11-2 timing of operation in interval timer mode caution to set m clocks as the interval period, set the tm0cmp0 register to m ? 1.
375 16-bit interval timer m chapter 11 user?s manual u18743ee1v2um00 11.4.2 cautions (1) clock generator and clock enable timing because the second clock is the first pulse of the timer count-up signal when the tm0ce bit is changed from 0 to 1, the timer counts one clock less. figure 11-3 count operation start timing
376 chapter 11 16-bit interval timer m user?s manual u18743ee1v2um00
377 user?s manual u18743ee1v2um00 chapter 12 timer aa synchroneous operation timers aa have a timer synchronized operation function, also named tuned operation mode. master timer and incorporated slave timers of the corresponding timer group (listed in ta b l e 1 2 - 1 ) start and clock synchronously. when the master timer is cleared, the slave timers are cleared synchronously, too. setup in the following the procedure is described how to set up the master and slave timer for synchroneous operation. exemplarily taam is used as the master timer, taan is used as the slave timer.  slave timer setup ? taanctl1.taansye = 1: enable synchroneous operation ? taanctl1.taanmd[2:0] = 101 b : free-running mode ? taanccr0/1: set compare value  master timer setup: ? taamctl1.taammd[2:0] =101 b : free-running mode =100 b : pwm mode =111 b : triangular wave pwm mode ? taamccr0/1: set compare value ? taamctl0.taamc = 1: enable operation table 12-2 and table 12-3 show the timer modes that can be used in the synchroneous operation mode. table 12-1 synchroneous operation mode of timers master timer slave timer v850es/fe3-l v850es/ff3-l v850es/fg3-l taa0 taa1 ?? taa2 taa3 ?? table 12-2 timer modes usable in synchroneous operation mode master timer slave timer free-running mode pwm mode triangular wave pwm mode taa0 taa1 ? taa2 taa3 ?
378 chapter 12 timer aa synchroneous operation user?s manual u18743ee1v2um00 the timing of transmitting data from the taanccrm compare register to the ccrm registers is as follows: table 12-3 timer output functions synch channel timer pin free-running mode pwm mode triangular wave pwm mode synch off synch on synch off synch on synch off synch on ch0 taa0 (master) toaa00 toggle toggle toggle toggle n/a n/a toaa01 toggle toggle pwm pwm n/a n/a taa1 (slave) toaa10 toggle toggle toggle pwm n/a n/a toaa11 toggle toggle pwm pwm n/a n/a ch1 taa2 (master) toaa20 toggle toggle toggle toggle n/a n/a toaa21 toggle toggle pwm pwm n/a n/a taa3 (slave) toaa30 toggle toggle toggle pwm n/a n/a toaa31 toggle toggle pwm pwm n/a n/a free-running mode: timing at which the cpu writes the registers (?anytime write?). pwm mode, triangular wave pwm mode: timing at which timer counter ccr0 and compare register toaan0 of master timer match.
379 user?s manual u18743ee1v2um00 chapter 13 watch timer functions 13.1 functions the watch timer has the following functions. watch timer  interval timer the watch timer and interval timer functions can be used at the same time. figure 13-1 block diagram of watch timer note 1. the prescaler3 output f brg is also used for csib0. for details refer to ?clock generator? on page 179 . 2. f xt : sub oscillator frequency f w : watch timer clock frequency intwt: watch timer interrupt intwti: interval timer interrupt internal bus watch timer operation mode register (wtm) f brg f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 r o t c e l e s r o t c e l e s r o t c e l e s r o t c e l e s reset note 1
380 chapter 13 watch timer functions user?s manual u18743ee1v2um00 (1) watch timer the watch timer generates interrupt requests (intwt) at time intervals of 0.5 or 0.25 seconds by using the sub oscillator (nominal f xt = 32.768 khz). caution when using a clock f brg obtained by dividing the main clock f x by prescaler3 as the watch timer count clock f w , set the prsm0 and prscm0 registers according to the main clock frequency that is used so as to obtain a divided clock frequency of 32.768 khz. if 32.768 khz cannot be generated, a clock correction software is necessary to realize the watch function. (2) interval timer the watch timer generates an interrupt request (intwti) at time intervals specified in advance. note f w : watch timer clock frequency f xt : sub oscillator frequency 13.2 configuration the watch timer consists of the following hardware. table 13-1 interval time of interval imer interval time operation at f w = f xt = 32.768 khz 2 4 1/f w 488 s 2 5 1/f w 977 s 2 6 1/f w 1.95 ms 2 7 1/f w 3.91 ms 2 8 1/f w 7.81 ms 2 9 1/f w 15.6 ms 2 10 1/f w 31.2 ms 2 11 1/f w 62.5 ms table 13-2 configuration of watch timer item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm)
381 watch timer functions chapter 13 user?s manual u18743ee1v2um00 13.3 control registers the watch timer operation mode register (wtm) controls the watch timer. before operating the watch timer, set the count clock and the interval time. (1) wtm - watch timer operation mode register the wtm register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. note f xt : sub oscillator frequency f brg : prescaler3 output frequency f w : watch timer clock frequency
382 chapter 13 watch timer functions user?s manual u18743ee1v2um00 caution rewrite the wtm2 to wtm7 bits while both the wtm0 and wtm1 bits are 0. note 1. f w : watch timer clock frequency 2. values in parentheses apply to operation with f w = 32.768 khz 13.4 operation 13.4.1 operation as watch timer the watch timer generates an interrupt request at fixed time intervals. the watch timer operates using time intervals of 0.5 or 0.25 seconds with the sub oscillator (32.768 khz). the count operation starts when the wtm1 and wtm0 bits of the wtm register are set to 11. when the wtm0 bit is cleared to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops. the time of the watch timer can be adjusted by clearing the wtm1 bit to 0 and then the 5-bit counter. at this time, an error of up to 15.6 ms may occur. the interval timer may be cleared by clearing the wtm0 bit to 0. however, because the 5-bit counter is cleared at the same time, an error of up to 0.5 seconds may occur when the watch timer overflows (intwt). 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clears after operation stops starts wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stops operation (clears both prescaler and 5-bit counter) enables operation wtm0 0 1 watch timer operation enable
383 watch timer functions chapter 13 user?s manual u18743ee1v2um00 13.4.2 operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. the interval time can be selected by the wtm4 to wtm7 bits of the wtm register. note f w : watch timer clock frequency f xt : sub oscillator frequency f brg : prescaler3 output frequency table 13-3 interval time of itimer wtm7 wtm6 wtm5 wtm4 interval time 00002 4 1/f w 488 s (operating at f w = f xt = 32.768 khz) 00012 5 1/f w 977 s (operating at f w = f xt = 32.768 khz) 0 010 2 6 1/f w 1.95 ms (operating at f w = f xt = 32.768 khz) 00112 7 1/f w 3.91 ms (operating at f w = f xt = 32.768 khz) 01002 8 1/f w 7.81 ms (operating at f w = f xt = 32.768 khz) 01012 9 1/f w 15.6 ms (operating at f w = f xt = 32.768 khz) 01102 10 1/f w 31.3 ms (operating at f w = f xt = 32.768 khz) 01112 11 1/f w 62.5 ms (operating at f w = f xt = 32.768 khz) 10002 4 1/f w 488 s (operating at f w = f brg = 32.768 khz) 10012 5 1/f w 977 s (operating at f w = f brg = 32.768 khz) 10102 6 1/f w 1.95 ms (operating at f w = f brg = 32.768 khz) 10112 7 1/f w 3.91 ms (operating at f w = f brg = 32.768 khz) 11002 8 1/f w 7.81 ms (operating at f w = f brg = 32.768 khz) 11012 9 1/f w 15.6 ms (operating at f w = f brg = 32.768 khz) 11102 10 1/f w 31.3 ms (operating at f w = f brg = 32.768 khz) 11112 11 1/f w 62.5 ms (operating at f w = f brg = 32.768 khz)
384 chapter 13 watch timer functions user?s manual u18743ee1v2um00 figure 13-2 operation timing of watch timer/interval timer note f w : watch timer clock frequency values in parentheses apply to operation with count clock f w = 32.768 khz. n: number of interval timer operations 13.4.3 cautions the following time is required before the first watch timer interrupt request signal (intwt) is generated after operation is enabled (wtm1 and wtm0 bits of wtm register = 1). it takes 0.515625 seconds for the first intwt signal to be generated (2 9 1/32768 = 0.015625 s longer). the intwt signal is then generated every 0.5 seconds. figure 13-3 example of generation of watch timer interrupt request signal (intwt) (when interrupt period = 0.5 s) start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt
385 user?s manual u18743ee1v2um00 chapter 14 watchdog timer 2 14.1 functions watchdog timer 2 has the following functions.  default-start watchdog timer  reset mode: reset operation upon overflow of watchdog timer 2 (generation of wdt2res signal)  non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal)  input selectable from main clock and 240 khz internal oscillator as the source clock caution 1. watchdog timer 2 is automatically started after reset release. source clock is a 240 khz internal oscillator. 2. by flash mask option, operation of wdt2 can be set fixed to 240 khz internal oscillator source clock and reset mode. only the interval time can be changed. changing of clock source and operation mode is not possible. 3. in case wdt2 shall not be used or clock source and operation mode shall be changed, flash mask option should not be set for fixing 240 khz internal oscillator source clock and reset mode. in this case, after reset, the settings should be changed before the first wdt2 overflow. alternatively wdt2 should be cleared once, and required changes should be performed within the next interval time. 4. the wdtm2 register can be written only once after reset. even if the default setting of wdtm2 shall not be changed, it is recommended to once write the default value to wdtm2 in order to activate the write protection mechanism. 5. the reti instruction can not be used to restore from the interrupt service routine of the non-maskable intwdt2. therefore a system reset must be performed after completion of the intwdt2 service routine.
386 chapter 14 watchdog timer 2 user?s manual u18743ee1v2um00 figure 14-1 block diagram of watchdog timer 2 note f x : oscillation frequency f rl : internal oscillator clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdt2res: watchdog timer 2 reset signal 14.2 configuration watchdog timer 2 consists of the following hardware. table 14-1 configuration of watchdog timer 2 f x /128 wdt2res (internal reset signal) wdcs22 intwdt2 wdcs21 wdcs20 wdcs23 wdcs24 0 wdm21 wdm20 f x /2 16 to f x /2 23 f rl /2 12 to f rl /2 19 3 clear 3 2 run2 f rl /8 clock input controller output controller selector internal bus 16-bit counter watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) item configuration control registers watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte)
387 watchdog timer 2 chapter 14 user?s manual u18743ee1v2um00 14.3 control registers (1) wdtm2 - watchdog timer 2 mode register the wdtm2 register sets the operation mode, operation clock and overflow time of watchdog timer 2. access the register can be read/written in 8-bit units. this register can be read any number of times, but it can be written only once following reset release. address ffff f6d0 h initial value 67 h . the register is initialized by any reset. 76543210 0 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 r/w r/w r/w r/w r/w r/w r/w r/w table 14-2 selection of operation mode wdm21 wdm20 function 0 0 stops operation 0 1 non-maskable interrupt request mode (generation of intwdt2) 1 x reset mode (generation of reswdt2)
388 chapter 14 watchdog timer 2 user?s manual u18743ee1v2um00 caution 1. if the wdtm2 register is rewritten twice after reset, an overflow signal is forcibly generated. if the watchdog timer has stopped operation, wdtm2 can be written several times without generating an overflow. 2. to stop wdt2 securely,  stop the internal oscillator by rcm.rstop = 1 (must be permitted by flash mask options)  set wdtm2 = 1f h 3. in order to ensure that the watchdog timer does not overflow, and thus generate a watchdog event, during the register settings are changed, write to wdte first for restarting the timer. table 14-3 watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected clock period 240 khz (typ.) 000002 12 /f rl 17.1 ms 000012 13 /f rl 34.1 ms 000102 14 /f rl 68.3 ms 000112 15 /f rl 136.5 ms 001002 16 /f rl 273.1 ms 001012 17 /f rl 546.1 ms 001102 18 /f rl 1,092.3 ms 00111 2 19 /f rl (default) 2,184.5 ms f x = 4 mhz f x = 16 mhz 01000 2 16 /f x 16.4 ms 4.1 ms 01001 2 17 f x 32.8 ms 8.2 ms 01010 2 18 /f x 65.5 ms 16.4 ms 01011 2 19 /f x 131.1 ms 32.8 ms 01100 2 20 /f x 262.1 ms 65.3 ms 01101 2 21 /f x 524.3 ms 131.1 ms 01110 2 22 /f x 1,048.6 ms 262.2 ms 01111 2 23 /f x 2,097.2 ms 524.3 ms 1 stop
389 watchdog timer 2 chapter 14 user?s manual u18743ee1v2um00 (2) wdte - watchdog timer enable register the counter of watchdog timer 2 is cleared and counting restarted by writing ac h to the wdte register. access the register can be read/written in 8-bit units. address ffff f6d1 h initial value 9a h . the register is initialized by any reset. caution 1. when a value other than ac h is written to the wdte register, an overflow signal is forcibly output. 2. when a 1-bit memory manipulation instruction is executed for the wdte register, an overflow signal is forcibly output. 3. the read value of the wdte register is 9a h (which differs from written value ac h ). 14.4 watchdog timer operation watchdog timer 2 automatically starts in the reset mode after reset is released. the wdtm2 register can be written only once following reset using byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm2 register using an 8-bit memory manipulation instruction. after this, the operation of watchdog timer 2 cannot be stopped/changed again. the wdcs24 to wdcs20 bits of the wdtm2 register are used to select the watchdog timer 2 loop detection time interval. writing ac h to the wdte register clears the counter of watchdog timer 2 and starts the count operation again. after the count operation has started, write ac h to wdte within the loop detection time interval. if the time interval expires without ac h being written to the wdte register, a reset signal (wdt2res) or a non-maskable interrupt request signal (intwdt2) is generated, depending on the set values of the wdm21 and wdm20 bits of the wdtm2 register. when not using watchdog timer 2, write 1fh to the wdtm2 register. if the non-maskable interrupt request mode is set, execution cannot return from non-maskable interrupt servicing by using the reti instruction. therefore, execute system reset after completion of interrupt servicing. 76543210 r/w r/w r/w r/w r/w r/w r/w r/w
390 chapter 14 watchdog timer 2 user?s manual u18743ee1v2um00 14.5 watchdog timer operation in power save mode if the watchdog timer overflows while the device is in power save mode, following procedures take place:  watchdog timer in reset operation mode (wdtm2.wdm21 = 1): a device reset is executed.  watchdog timer in nmi operation mode (wdtm2.wdm2[1:0] = 01 b ): the nmi is not served, the device wakes up from power save mode and continues with normal operation.
391 user?s manual u18743ee1v2um00 chapter 15 asynchronous serial interface (uartd) the v850es/fx3-l microcontrollers have following instances of the universal asynchronous serial interface uartd: throughout this chapter, the individual instances of uartd are identified by ?n?, for example, udnctl0 for the uartdn control register 0. 15.1 features  transfer rate: 300 bps to 1500 kbps (using dedicated baud rate generator)  full-duplex communication: ? internal uartd receive data register n (udnrx) ? internal uartd transmit data register n (udntx)  2-pin configuration: ? txddn: transmit data output pin ? rxddn: receive data input pin  reception error and status output function ?parity error ? framing error ?overrun error ? data consistency error ?sbf receive error  interrupt sources: 3 ? reception complete interrupt (intudnr): this interrupt occurs upon transfer of receive data from the shift register to receive buffer register n after serial transfer completion, in the reception enabled status. ? transmission enable interrupt (intudnt): this interrupt occurs upon transfer of transmit data from the transmit buffer register to the shift register in the transmission enabled status. ? status interrupt (intudns): this interrupt occurs upon reception of erroneous data and the data consistency and sbf reception during lin communication.  character length: 7, 8 bits  parity function: odd, even, 0, none  transmission stop bit: 1, 2 bits uartd v850es/fe3-l v850es/ff3-l v850es/fg3-l instances 2 3 names uartd0 to uart1 uartd0 to uart2
392 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00  on-chip dedicated baud rate generator  msb-/lsb-first transfer selectable  transmit/receive data inverted input/output possible  13 to 20 bits selectable for the sbf (sync break field) in the lin (local interconnect network) communication format ? recognition of 11 bits or more possible for sbf reception in lin communication format ? sbf reception flag provided  sbf reception can be detected during data communication.  bus monitor function to keep data consistency of the transmit data 15.2 configuration the block diagram of the uartdn is shown below. figure 15-1 block diagram of asynchronous serial interface uartdn note for the configuration of the baud rate generator, see figure 15-11 on page 419 . internal bus udnctl0 udnstr udnctl1 udnctl2 receive shift register udnrx filter selector udntx transmission controller reception controller baud rate generator intudnr intudns intudnt txddn rxddn reception unit transmission unit transmit shift register baud rate generator selector internal bus udnotp0 clock selector udnotp1 f xp1 or f xp2 f xp1 /2 f xp1 /4 . . . f xp1 /1024 asckd0 note note: external clock asckd0 is only available for uartd0 send and receive data comparison
393 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 uartdn consists of the following hardware units. table 15-1 configuration of uartdn (1) uartdn control register 0 (udnctl0) the udnctl0 register is an 8-bit register used to specify the uartdn operation. (2) uartdn control register 1 (udnctl1) the udnctl1 register is an 8-bit register used to select the input clock for the uartdn. (3) uartdn control register 2 (udnctl2) the udnctl2 register is an 8-bit register used to control the baud rate for the uartdn. (4) uartdn option control register 0 (udnopt0) the udnopt0 register is an 8-bit register used to control the serial transfer for the uartdn. (5) uartdn option control register 1 (udnopt1) the udnopt1 register is an 8-bit register used to control the serial transfer for the uartdn. (6) uartdn status register (udnstr) the udnstrn register consists of flags indicating the error contents when a reception error occurs, the inconsistency between transmit and receive data and successful sbf reception during lin communication. each one of the reception error flags is set (to 1) upon occurrence of a reception error and is reset (to 0) by reading the udnstr register. (7) uartdn receive shift register this is a shift register used to convert the serial data input to the rxddn pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the udnrx register. this register cannot be manipulated directly. item configuration registers uartdn control register 0 (udnctl0) uartdn control register 1 (udnctl1) uartdn control register 2 (udnctl2) uartdn option control register 0 (udnopt0) uartdn status register (udnstr) uartdn receive shift register uartdn receive data register (udnrx) uartdn transmit shift register uartdn transmit data register (udntx)
394 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 (8) uartdn receive data register (udnrx) the udnrx register is an 8-bit register that holds receive data. when 7 characters are received, 0 is stored in the highest bit (when data is received lsb first). in the reception enabled status, receive data is transferred from the uartdn receive shift register to the udnrx register in synchronization with the completion of shift-in processing of 1 frame. transfer to the udnrx register also causes the reception complete interrupt request signal (intudnr) to be output. (9) uartdn transmit shift register the transmit shift register is a shift register used to convert the parallel data transferred from the udntx register into serial data. when 1 byte of data is transferred from the udntx register, the shift register data is output from the txddn pin. this register cannot be manipulated directly. (10) uartdn transmit data register (udntx) the udntx register is an 8-bit transmit data buffer. transmission starts when transmit data is written to the udntx register. when data can be written to the udntx register (when data of one frame is transferred from the udntx register to the uartdn transmit shift register), the transmission enable interrupt request signal (intudnt) is generated.
395 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 15.3 uartd registers (1) udnctl0 - uartdn control register 0 the udnctl0 register is an 8-bit register that controls the uartdn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 10h. udnpwr disable uartdn operation (uartdn reset asynchronously) enable uartdn operation udnpwr 0 1 uartdn operation control udnctl0 udntx e udnrx e udndi r udnps 1 udnps 0 udnc l udnsl 6543 2 1 ud2ctl0 fffffa20h, ud3ctl0 fffffa30h, ud4ctl0 fffffa40h, ud5ctl0 fffffa50h ud6ctl0 fffffa60h, ud7ctl0 fffffa70h the uartdn operation is controlled by the udnpwr bit. the txddn pin output is fixed to high level by clearing the udnpwr bit to 0 (fixed to low level if udnopt0.udntdl bit = 1). disable transmission operation enable transmission operation udntxe 0 1 transmission operation enable ? to start transmission, set the udnpwr bit to 1 and then set the udntxe bit to 1. to stop transmission clear the udntxe bit to 0 and then udnpwr bit to 0. ? to initialize the transmission unit, clear the udntxe bit to 0, wait for two cycles of the base clock, and then set the udntxe bit to 1 again. disable reception operation enable reception operation udnrxe 0 1 reception operation enable ? to enable reception, set the udnpwr bit to 1 and then set the udnrxe bit to 1. to stop reception, clear the udnrxe bit to 0 and then udnpwr bit to 0. to initialize the reception unit, clear the udnrxe bit to 0, wait for two periods of the base clock, and then set the udnrxe bit to 1 again. the reception is enabled after the udnrxe bit is set to 1 and two cycles of base clock have passed. the rising edge detection of the rxdd pin is enabled after the udnrxe bit is set to 1 and four cycles of the base clock have passed. 7 0 ? ?
396 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 note for details of parity, see ?parity types and operations? on page 416 . (2) udnctl1- uartdn control register 1 for details, see ?udnctl1 - uartdn control register 1? on page 420 . (3) udnctl2 - uartdn control register 2 for details, see ?udnctl2 - uartdn control register 2? on page 421 . 7 bits 8 bits udncl 0 1 specification of data character length of 1 frame of transmit/receive data ? this register can be rewritten only when the udnpwr bit = 0 or the udntxe bit = the udnrxe bit = 0. ? when the transmission/reception is performed in the lin format, set the udncl bit to 1. 1 bit 2 bits udnsl 0 1 specification of length of stop bit for transmit data this register can be rewritten only when the udnpwr bit = 0 or the udntxe bit = the udnrxe bit = 0. ? this register is rewritten only when the udnpwr bit = 0 or the udntxe bit = the udnrxe bit = 0. ? if reception with 0 parity is selected during reception, a parity check is not performed. therefore, since the udnstr.udnpe bit is not set, no error interrupt is output. ? when transmission and reception are performed in the lin format, clear the udnps1 and udnps0 bits to 00. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check udnps1 0 0 1 1 parity selection during transmission parity selection during reception udnps0 0 1 0 1 msb-first transfer lsb-first transfer udndir 0 1 transfer direction selection this register can be rewritten only when the udnpwr bit = 0 or the udntxe bit = the udnrxe bit = 0. when the transmission/reception is performed in the lin format, set the udndir bit to 1.
397 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 (4) udnopt0 - uartdn option control register 0 the udnopt0 register is an 8-bit register that controls the serial transfer operation of the uartdn register. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 14h.. after reset: 04h address: ud0opt0: fffffa03, ud1opt0: fffffa13 ud2opt0: fffffa23, ud3opt0: fffffa33 ud4opt0: fffffa43, ud5opt0: fffffa53 ud6opt0: fffffa63, ud7opt0: fffffa73 76543210 udnopt0 udnsrf udnsrt udnstt udnsls2 udnsls1 udnsls0 udntdl udnrdl r/w r/w r/w r/w r/w r/w r/w r/w r/w udnsrf sbf reception flag 0 when the udnctl0.udnpwr bit = udnctl0.udnrxe bit = 0 are set. also upon normal end of sbf reception. 1 during sbf reception.  sbf (sync brake field) reception is judged during lin communication.  the udnsrf bit is held at 1 when an sbf reception error occurs, and then if the sbf reception is started again and ended normally, the udnsrf bit is cleared to 0.clearing by the instruction is disabled.  udnsrf bit is read-only. when the udnsrf = 1, the judgment process that sbf reception ended normally differs depending on the values of the sbf reception mode selection bit (udnsrs). if the udnsrs bit = 0, when any high level inputs including noises are applied to the reception input data even only for a second, the judgment of whether the low level period is more than 11 bits or not is executed. if the udnsrs bit = 1, the received input data is sampled along with the set baud rate and when the low level period is 11 bits or more, it is judged as the successful sbf reception. udnsrt sbf reception trigger 0- 1 sbf reception trigger.  this is the sbf reception trigger bit during lin communication, and when read, ?0? is always read. for sbf reception, set the udnsrt bit (to 1) to enable sbf reception.  set the udnsrt bit after setting the udnctl0.udnpwr bit and udnctl0.udnrxe bit = 1.  the udnsrt bit can be set during the reception but the reception is aborted. the updating of the status flag, output of the interrupt request flag, and the data saving are not performed so the receive data set during the reception is not guaranteed.  after the udnsrt bit is set, re-setting of the udnsrt bit is disabled until the sbf reception is succeeded, udnsrf is cleared, and the interrupt request signal is fallen.  the detection of the sbf reception starts at the next falling edge of the reception input data. if the udnsrt is set during the sbf reception, the sbf cannot be received, so other reception operations are not performed until the next sbf reception is succeeded.
398 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 note 1. to cancel the sbf reception enable status without receiving the sbf, set the udnpwr bit = 0 or udnrxe bit = 0. 2. the confirmation method of sbf receive completion while the udnsrt bit is set depends on the values of the sbf reception mode selection bit (udnsrs). if the udnsrs bit is cleared to 0, it is confirmed by receive completion interrupt which is detected after the setting of the sbf reception trigger bit. if the udnsrs bit is set to 1, it is confirmed by whether the sbf receive success flag (udnssf) is 1 when status interrupt is detected after the setting of the sbf reception trigger bit. it can also be confirmed by the udnsrf bit = 0 after the receive interrupt or the status interrupt is detected. in any case, after the sbf reception is completed, the uart normal reception is operated at the next reception. 3. data transmission while udndcs bit = 1 during udnsrf bit = 1 is prohibited. however, the sbf transmission is enabled. before starting the sbf transmission by udnopt0.udnstt=1 make sure that no data transfer is ongoing, that means check that udnstr.udntsf=0. note the udntdl bit control inverts the txddn output level regardless of the values of the udnpwr and udntxe bits. therefore, if the udntdl bit is set to 1 while the operation is disabled, the txddn outputs the low level. udnstt sbf transmission trigger 0- 1 sbf transmition trigger note .  this is the sbf transmittion trigger bit during lin communication, and when read, ?0? is always read.  set the udnstt bit after setting the udnpwr bit = udntxe bit = 1. udnsls2 1 1 1 0 0 0 0 1 udnsls1 0 1 1 0 0 1 1 0 udnsls0 1 0 1 0 1 0 1 0 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output sbf transmit length selection ? the output level of the txddn pin can be inverted using the udntdl bit. ? this register can be set when the udnpwr bit = 0 or when the udntxe bit = 0. this register can be set when the udnpwr bit = 0 or when the udntxe bit = 0. normal output of transfer data inverted output of transfer data udntdl 0 1 transmit data level bit ? the output level of the rxddn pin can be inverted using the udnrdl bit. ? this register can be set when the udnpwr bit = 0 or the udnrxe bit = 0. normal input of transfer data inverted input of transfer data udnrdl 0 1 receive data level bit
399 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 (5) udnopt1 - uartdn option control register 1 the udnopt1 register is an 8-bit register that controls the serial transfer operation of the uartdn register. this register can be read or written in 8-bit units. reset input sets this register to 00h. note 1. this bit should only be set when the lin communication is used. otherwise set this bit to 0. 2. when this bit is set to 1, it is necessary to set ud0dcs to 1. note 1. this bit should only be set when the lin communication is used. otherwise set this bit to 0. 2. when this bit is used, the data bit length doesn't prohibits the eight bit fixation and the addition of the parity bit. after reset: 00h address: ud0opt1: fffffa05, ud1opt1: fffffa15 ud2opt1: fffffa25, ud3opt1: fffffa35 ud4opt1: fffffa45, ud5opt1: fffffa55 ud6opt1: fffffa65, ud7opt1: fffffa75 76543210 udnopt1 0 0 0 0 0 0 udnsrs udndcs r/w r/w r/w r/w r/w r/w r/w r/w r/w udnsrs sbf reception mode selection bit 0 a new sbf can't be detected while the communication is in progress.when the low level is detected at the stop bit position, it is recognized as framing error. 1 a new sbf can be detected while the communication is in progress.when the low level is detected at the stop bit position a waiting state is generated until high level is detected. when the width of the low level is 11 bits or more, it is recognized as new sbf. udndcs data consistency check selection bit 0 data consistency is not checked 1 data consistency is checked when data is transmitted using the lin protocoll, this bit selects the handling of the consistency checking of data. when udndcs = 1 the transmitted data and received data are compared and the mismatch is detected. in that case a status interrupt request signal (udtis) is generated.
400 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 (6) udnstr - uartdn status register the udnstr register is an 8-bit register that displays the uartdn transfer status and reception error contents. this register can be read or written in 8-bit or 1-bit units, but the udntsf bit is a read-only bit, while the udnssf, udndce, udnpe, udnfe, and udnove bits can both be read and written. however, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). the initialization conditions are shown below. note to clear the status flag, use a 1-bit manipulation instruction or write the inverted value of the read value using a 8-bit manipulation instruction to clear all bits together. register/bit initialization conditions udnstr register  reset  udnctl0.udnpwr = 0 udnssf  udnctl0.udnrxe = 0  udnopt1.udnsrs = 0 udndce  udnctl0.udnrxe = 0  udnopt1.udndcs = 0 udntsf bit  udnctl0.udntxe = 0 udnpe, udnfe, udnove bits  0 write  udnctl0.udnrxe = 0 after reset: 00h address: ud0str: fffffa04, ud1str: fffffa14 ud2str: fffffa24, ud3str: fffffa34 ud4str: fffffa44, ud5str: fffffa54 ud6str: fffffa64, ud7str: fffffa74 76543210 udnstr udntsf 0 0 udnssf udndce udnpe udnfe udnove r/w r r/w r/w r/w r/w r/w r/w r/w udntsf transfer status flag 0  when the udnpwr bit = 0 or the udntxe bit = 0 has been set.  when, following transfer completion, there was no next data transfer from udntx register  when there is no next transmit data at the udntx bit after the sbf transmission has been completed 1  write to udntxb bit  when the sbf transmission trigger bit (udnsst) is set the udntsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the udntsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the udntsf bit = 1. during the communication the udntsf bit is cleared after 2 clocks.
401 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 udnssf sbf receive successful flag 0 when the udnpwr bit = 1or the udnrxe bit = 0 or the udnsrs bit = 0 or the udnssf bit = 0 has been set 1 when a consecutive low level (sbf) of 11 bits or more is received and the sbf reception mode bit udnsrs has been set. when the sbf receive mode selection bit is set in lin communication mode, it is necessary to read this bit by the status interrupt processing and to confirm the beginning of a new frame slot. this bit is maintained until 0 is written. it is always 0 for ud0srs = 0. when 1 is written to this bit, the value is retained. udndce data consistency error flag 0 when the udnpwr bit = 0 or the udntxe bit = 0 or the udndcs bit = 0 or udndce bit = 0 has been set. 1 this bit is set when the transmit data is not consistent to receive data in lin communication mode. the send data is compared with the receive data when data is transmitted in lin communication mode. when a mismatch is detected, this bit becomes 1. the bit is maintained until 0 is written. it is always 0 for ud0dcs = 0. when 1 is written to this bit, the value is retained. udnpe parity error flag 0  when the udnpwr bit = 0 or the udnrxe bit = 0 has been set.  when 0 has been written 1 when parity of data and parity bit do not match during reception.  the operation of the udnpe bit is controlled by the settings of the udnctl0.udnps1 and udnctl0.udnps0 bits.  the udnpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained. udnfe framing error flag 0  when the udnpwr bit = 0 or the udnrxe bit = 0 has been set  when 0 has been written 1 when no stop bit is detected during reception  only the first bit of the receive data stop bits is checked, regardless of the value of the udnctl0.udnsl bit.  the udnfe bit can be both read and written, but it can only be cleared by the value is retained writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit. udnove overrun error flag 0  when the udnpwr bit = 0 or the udnrxe bit = 0 has been set.  when 0 has been written 1 when receive data has been set to the udnrxb register and the next receive operation is completed before that receive data has been read  when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer.  the udnove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the value is retained
402 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 (7) udnrx - uartdn receive data register the udnrx register is an 8-bit buffer register that stores parallel data converted by the receive shift register. the data stored in the receive shift register is transferred to the udnrx register upon completion of reception of 1 byte of data. during lsb-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits 6 to 0 of the udnrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the udnrx register and the lsb always becomes 0. when an overrun error (udnove) occurs, the receive data at this time is not transferred to the udnrx register and is discarded. this register is read-only, in 8-bit units. in addition to reset input, the udnrx register can be set to ffh by clearing the udnctl0.udnpwr bit to 0. (8) udntx - uartdn transmit data register the udntx register is an 8-bit register used to set transmit data. this register can be read or written in 8-bit units. reset input sets this register to ffh. when the transmission is enabled (udnpwr = 1 and udntxe = 1) the write to the udntx register triggers the start of the transmission. be sure to execute the transmit data write during transmission after the transmission interrupt request (intudnt) is generated. if the the next data is written before the transmission is completed the continuous transmission is enabled. udnrx 6 5 4 3 2 1 after reset: ffh r address: ud0rx fffffa06h, ud1rx fffffa16h, ud2rx fffffa26h, ud3rx fffffa36h , ud4rx fffffa46h 7 0 udntx 6 5 4 3 2 1 after reset: ffh r/w address : ud0tx fffffa07h, ud1tx fffffa17h, ud2tx fffffa27h, ud3tx fffffa37h, ud4tx fffffa47h 7 0
403 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 15.4 interrupt request signals the following three interrupt request signals are generated from uartdn.  reception complete interrupt request signal (intudnr)  status interrupt request signal (intudns)  transmission enable interrupt request signal (intudnt) (1) reception complete interrupt request signal (intudnr) a reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the udnrx register in the reception enabled status. in case of erroneous reception, the status interrupt intudns is generated instead of intudnr. no reception complete interrupt request signal is generated in the reception disabled status. (2) transmission enable interrupt request signal (intudnt) if transmit data is transferred from the udntx register to the uartdn transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated. (3) status interrupt request signal (intudns) a status interrupt request is generated if an error condition occurred during reception, as reflected by udnstr.udnpe (parity error flag), udnstr.udnfe (framing error flag), udnstr.udnove (overrun error flag), the data is not consistent between data transmit and data reception. when the sbf reception mode selection bit is set in lin communication mode (udnsrs bit = 1), the status interrupt request signal is generated when a consecutive low level (sbf) of 11 bits or more is received.
404 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 15.5 operation 15.5.1 data format full-duplex serial data reception and transmission is performed. as shown in the figures below, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of msb/lsb-first transfer are performed using the udnctl0 register. moreover, control of uart output/inverted output for the txddn bit is performed using the udnopt0.udntdl bit.  start bit 1 bit  character bits 7 bits/8 bits  parity bit even parity/odd parity/0 parity/no parity  stop bit 1 bit/2 bits (1) uartd transmit/receive data format (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 data frame s tart bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit s top bit 1 data frame s tart bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit s top bit
405 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txddn inversion (d) 7-bit data length, lsb first, odd parity, 2 stop bits, transfer data: 36h (e) 8-bit data length, lsb first, no parity, 1 stop bit, transfer data: 87h 1 data frame s tart bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit s top bit 1 data frame s tart bit d0 d1 d2 d3 d4 d5 d6 parity bit s top bit s top bit 1 data frame s tart bit d0 d1 d2 d3 d4 d5 d6 d7 s top bit
406 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 15.5.2 sbf transmissi on/reception format the uartd has an sbf (sync break field) transmission/reception control function to enable use of the lin function. about lin lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to control the switches, actuators, and sensors, and these are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is 15% or less. figure 15-2 and figure 15-3 outline the transmission and reception manipulations of lin. figure 15-2 lin transmission manipulation outline note 1. the interval between each field is controlled by software. 2. sbf output is performed by hardware. the output width is the bit length set by the udnopt0.udnsbl2 to udnopt0.udnsbl0 bits. if even finer output width adjustments are required, such adjustments can be performed using the udnctln.udnbrs7 to udnctln.udnbrs0 bits. 3. 80h transfer in the 8-bit mode is substituted for the wakeup signal frame. lin-bus wake-up signal frame synch break field synch field ident field data field data field check sum field intudnr interrupt txddn (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission
407 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 4. a transmission enable interrupt request signal (intudnt) is output at the start of each transmission. the intudnt signal is also output at the start of each sbf transmission. figure 15-3 lin reception manipulation outline note 1. the wakeup signal is sent by the pin edge detector, uartdn is enabled, and the sbf reception mode is set. 2. upon detection of the sbf reception of 11 or more bits, normal sbf reception end is judged. when the sbf reception mode selection bit (udnsrs) is set to "0", the receive completion interrupt request signal (intudnr) is generated, and when the udnsrs is set to "1", the status interrupt request signal (intudns) is generated. upon detection of sbf reception of less than 11 bits, an sbf reception error is judged, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. when sbf reception ends normally, if the sbf reception mode selection bit (udnsrs) is "0", the receive completion interrupt request signal (intudnr) is generated, and if the udnsrs is "1", the status interrupt request signal (intudns) is generated and the sbf reception success flag (udnssf) is set. if the sbf reception trigger bit (udnsrt) is "1", the error detection for the overrun, parity, and framing (udnove, udnpe, udnfe) is not performed during the sbf reception. moreover, the data transfer from the receive shift register to the receive data register (udnrx) is not performed, either. at this time, the udnrx holds the prior value. 4. the rxddn pin is connected to ti (capture input) of the timer, the transfer rate is calculated, and the baud rate error is calculated. the value of the udnctl2 register obtained by correcting the baud rate error after dropping uartd enable is set again, causing the status to become the reception status. reception interrupt (intudnr) edge detection capture timer disable disable enable rxddn (input) enable note 2 13 bits sbf reception note 3 note 4 note 1 sf reception id reception data transmission data transmission note 5 data transmission lin-bus wake-up signal frame synch break field synch field ident field data field data field check sum field
408 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 5. check-sum field distinctions are made by software. uartdn is initialized following csf reception, and the processing for setting the sbf reception mode again is performed by software. when the udnsrs bit = 1, the sbf reception can be performed automatically without setting to the sbf reception mode again. 15.5.3 sbf transmission when the udnctl0.udnpwr bit = udnctl0.udntxe bit = 1, the transmission enabled status is entered, and sbf transmission is started by setting (to 1) the sbf transmission trigger (udnopt0.udnstt bit). thereafter, a low level the width of bits 13 to 20 specified by the udnopt0.udnsls2 to udnopt0.udnsls0 bits is output. a transmission enable interrupt request signal (intudnt) is generated upon sbf transmission start. following the end of sbf transmission, the udnstt bit is automatically cleared. thereafter, the uart transmission mode is restored. transmission is suspended until the data to be transmitted next is written to the udntx register, or until the sbf transmission trigger (udnstt bit) is set. figure 15-4 sbf transmission 15.5.4 sbf reception the reception enabled status is achieved by setting the udnctl0.udnpwr bit to 1 and then setting the udnctl0.udnrx bit to 1. the sbf reception wait status is set by setting the sbf reception trigger (udnopt0.udnstr bit) to 1. in the sbf reception wait status, similarly to the uart reception wait status, the rxddn pin is monitored and start bit detection is performed. following detection of the low level, reception is started and the internal counter counts up according to the set baud rate. when a high level is received and if the sbf width is 11 or more bits, when sbf receiving mode selection bit (udnsrs) is ?0? the reception completion interrupt request signal (intudnr) is generated. when the udnsrs bit is ?1? the sbf reception success flag (udnssf) is set at the same time as generating a status interrupt request signal (intudns). the udnopt0.udnsrf bit is automatically cleared and sbf reception ends. error detection for the udnstr.udnove, udnstr.udnpe, and udnstr.udnfe intudnt interrupt 1 2 3 4 5 6 7 8 9 10 11 12 13 stop bit settin g of uanstt bit udntsf
409 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 bits is suppressed and uart communication error detection processing is not performed. moreover, data transfer of the uartdn reception shift register and udnrx register is not performed and ffh, the initial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the sbf reception mode is returned to. the udnsrf bit is not cleared at this time. the sbf mode can be selected between a single sbf receive mode and an any time sbf receive mode in the udnopt1 register (udnopt1.udnsrs). the status of a successful reception of the sbf is shown y the udnopt1.udnsrs bit in the udnopt1 register. (a) normal sbf reception (detection of stop bit in more than 10.5 bits) (b) sbf reception error (detection of stop bit in 10.5 or fewer bits) note the udnsrf bit is reset by setting the udnsrt bit to "1", and cleared by normal sbf reception. udnsrf 1 2 3 4 5 6 11.5 7 8 9 10 11 intudnr interrupt ud0srf 1 2 3 4 5 6 10.5 7 8 9 10 intudnr interrupt
410 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 15.5.5 data consistency check the uartd incorporates a data consistency check function to detect a mismatch between the transmit data written to transmit register (udntx) and the data on the bus when the device operates in master mode. the data consistency is checked by comparing the transmit data in the transmit register (udntx) and the receive data in the receive register (udnrx). in case of a mismatch the data consistency error flag (udnstr.udndce) is set and a status interrupt request (intudns) occurs. the consistency check of the send data and the input data terminal level is done even if the reception is disabled (udnrxe = 0) during sending. in that case also the reception completion interrupt request signal (intudnr), the udnssf, udnfe, udnove and the status interrupt request signal (intudns) will not be generated as well. receive data does not need to be read. refer to ?uartdn status register (udnstr)? on page 393 for details. (a) timing example of data consistency error (udnsrf = 0) d0 start bit stop bit d1 d2 d3 d4 d5 d6 d7 d0 start bit stop bit d1 d2 d3 d4 d5 d6 d7 udntx signal udnrx signal udnstr. udntsf udnstr. udndce intudns internal error detection mismatch detection communication stops
411 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 (b) timing example of data consistency error when there is a delay between transmit and receive operation d0 start bit stop bit d1 d2 d3 d4 d5 d6 d7 d0 start bit stop bit d1 d2 d3 d4 d5 d6 d7 udntx signal 0xd5 udnrx signal 0xaa udnstr. udntsf udnstr. udndce intudns internal error detection reception end communication stops
412 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 15.5.6 uart transmission first, set the transmission enabled status by performing the following procedures.  specify the operation clock by the uartd control register 1 (udnctl1)  specify the baud rate by the uartd control register 2 (udnctl2)  specify the output logic level by the uartd option control register 0 (udnopt0).  specify the transmit destination, parity, data character length, stop bit length by the uartd control register 0 (udnctl0).  set the power bit and the transmission enabled bit (udnpwr = 1, udntxe = 1) write of the transmit data to the transmission buffer register (udntx) starts transmission. the data which is saved in the udntx register is transferred to the transmit shift register (udntxs). then, the start bit, parity bit, and stop bit are added and the data is output serially from the txddn to the data. moreover, at the timing that the transfer to udntxs of the data stored in udntx is completed, a transmission interrupt request signal (intudnt) is generated. once intudnt is generated, the next data can be written to udntx. note lsb first start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intudnt
413 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 15.5.7 continuous transmission procedure uartdn can write the next transmit data to the udntx register when the uartdn transmit shift register starts the shift operation. the transmit timing of the uartdn transmit shift register can be judged from the transmission enable interrupt request signal (intudnt). an efficient communication rate is realized by writing the data to be transmitted next to the udntx register during transfer. caution during continuous transmission execution, perform initialization after checking that the udnstr.udntsf bit is 0. the transmit data cannot be guaranteed when initialization is performed while the udntsf bit is 1. figure 15-5 continuous transmission processing flow start register settings udntx write ye s ye s no no occurrence of transmission interrupt? required number of writes performed? end
414 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 figure 15-6 continuous transmission op eration timing ?transmission start figure 15-7 continuous transmission operation timing?transmission end 15.5.8 uart reception first, set the reception enabled status by the next operations to monitor the rxddn input and perform the start bit detection.  specify the operation clock by the uartd control register 1 (udnctl1)  specify the baud rate by the uartd control register 2 (udnctl2)  specify the output logic level by the uartd option control register 0 (udnopt0) start data (1) data (1) txddn udntx transmission shift register intudnt udntsf data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start start data (n ? 1) data (n ? 1) data (n ? 1) data (n) ff data (n) udttxd udntx transmission shift register intudnt udntsf udnpwr or udntxe bit parity stop stop start data (n) parity parity stop
415 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00  specify the communication direction, parity, data character length, and stop bit length by the uartd control register 0 (udnctl0).  set the power bit and the reception enabled bit (udnpwr = 1, udnrxe = 1). when the sampling of the input level of the rxddn pin is performed and the falling edge is detected, the data sampling of the rxddn input is started. the start bit is recognized if the rxddn pin is low level after the time of a half bit is passed after the detection of the falling edge (shown in the figure below). after a start bit has been recognized, the receive operation starts, and serial data is stored in the receive shift register according to the set baud rate. when the reception complete interrupt request signal (intudnr) is output upon reception of the stop bit, the data stored in the receive shift register is written to the receive data register (udnrx). however, if an overrun error occurs (udnove = 1), the receive data at this time is not transferred to the udnrx register and is discarded. even if a parity error (udnpe = 1) or a framing error (udnfe = 1) occurs during reception, reception continues until the reception position of the first stop bit, and the reception data is transferred to the udnrx. in any case of the reception errors, intudns is output after the following reception completion, but not intudnr. when the communication direction, parity, data character length, and the stop bit length are changed, clear the power bit (udnpwr = 0) or clear both the transmission enabled bit and the reception enabled bit (udntxe = 0, udnrxe = 0), and then change the setting. figure 15-8 uart reception caution 1. be sure to read the udnrx register even when a reception error occurs. if the udnrx register is not read, an overrun error occurs during reception of the next data. 2. the operation during reception is performed assuming that there is only one stop bit. a second stop bit is ignored. 3. when reception is completed, read the udnrx register after the reception complete interrupt request signal (intudnr) has been generated, and clear the udnpwr or udnrxe bit to 0. if the udnpwr or udnrxe bit is cleared to 0 before the intudnr signal is generated, the read value of the udnrx register cannot be guaranteed. 4. if receive completion processing (intudnr signal generation) of uartdn start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intudnr udnrx
416 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 and the udnpwr bit = 0 or udnrxe bit = 0 conflict, the intudnr signal may be generated in spite of these being no data stored in the udnrx register. to complete reception without waiting intudnr signal generation, be sure to clear (0) the interrupt request flag (udnrif) of the udnric register, after setting (1) the interrupt mask flag (udnrmk) of the interrupt control register (udnric) and then set (1) the udnpwr bit = 0 or udnrxe bit = 0. note 1. if the low level is always input to the rxddn pin, it is not judged as the start bit. 2. in continuous reception, immediately after the stop bit is detected at the first reception bit (when the reception completion interrupt is generated), the next start bit can be detected. 3. if the udnrdl = 1 (receive data inversion input) is selected, when the reception is started, change the data reception pin to the uart receive pin mode and then enable the reception. if the pin mode is changed after the reception is enabled, the start bit is detected faultily if the pin level at this time is high level. 15.5.9 reception errors errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. data reception result error flags are set in the udnstr register and a status interrupt request signal intudns is output when an error occurs. it is possible to ascertain which error occurred during reception by reading the contents of the udnstr register. clear the reception error flag by writing 0 to it after reading it. table 15-2 reception error causes note note that even in case of a parity or framing error, data is transferred from the receive shift register to the receive data register udnrx. consequently the data from udnrx must be read. otherwise an overrun error udnstr.udnove will occur at reception of the next data. in case of an overrun error, the receive shift register data is not transferred to udnrx, thus the previous data is not overwritten. 15.5.10 parity types and operations caution when using the lin function, fix the udnps1 and udnps0 bits of the udnctl0 register to 00. error flag reception error cause udnpe parity error received parity bit does not match the setting udnfe framing error stop bit not detected udnove overrun error reception of next data completed before data was read from receive buffer
417 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 the parity bit is used to detect bit errors in the communication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (1) even parity  during transmission the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data:1 ? even number of bits whose value is ?1? among transmit data:0  during reception the number of bits whose value is ?1? among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (2) odd parity  during transmission opposite to even parity, the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so that it is an odd number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1  during reception the number of bits whose value is ?1? among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (3) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity error occurs, regardless of whether the parity bit is 0 or 1. (4) no parity no parity bit is added to the transmit data. reception is performed assuming that there is no parity bit. no parity error occurs since there is no parity bit.
418 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 15.5.11 receive data noise filter this filter samples the rxddn pin using the base clock of the prescaler output. when the same sampling value is read twice, the match detector output changes and the rxddn signal is sampled as the input data. therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see figure 15-10 ). see ?base clock? on page 419 regarding the base clock. moreover, since the circuit is as shown in figure 15-9 , the processing that goes on within the receive operation is delayed by 3 clocks in relation to the external signal status. figure 15-9 noise filter circuit figure 15-10 timing of rxddn signal judged as noise match detector in base clock (f uclk ) rxdan qin ld_en q internal signal c internal signal b in q internal signal a internal signal b base clock rxddn (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match
419 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 15.6 baud rate generator the dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartdn. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. (1) baud rate generator configuration figure 15-11 configuration of baud rate generator (a) base clock when the udnctl0.udnpwr bit is 1, the clock selected by the udnctl1.udncks[3:0] bits are supplied to the 8-bit counter. this clock is called the base clock. when the udnpwr bit = 0, f uclk is fixed to the low level. (b) serial clock generation a serial clock can be generated by setting the udnctl1 register and the udnctl2 register. the base clock is selected by udnctl1.udncks3 to udnctl1.udncks0 bits. the frequency division value for the 8-bit counter can be set using the udnctl2.udnbrs[7:0] bits. f uclk selector udnpwr 8-bit counter match detector baud rate udnctl2: udnbrs7 to udnbrs0 1/2 udnpwr, udntxen bit (or udnrxe bit) udnctl1: udncks3 to udncks0 f xp1 or f xp2 f xp1 /2 f xp1 /4 . . . f xp1 /1024 asckd0 note note: external clock asckd0 is only availabel for uartd0
420 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 (2) udnctl1 - uartdn control register 1 the udnctl1 register is an 8-bit register that selects the uartdn base clock. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution clear the udnctl0.udnpwr bit to 0 before rewriting the udnctl1 register. note prsi can be set by the option bytes: refer to ?flash memory? on page 259 for details. after reset: 00h address: ud0ctl1: fffffa01, ud1ctl1: fffffa11 ud2ctl1: fffffa21 76543210 udnctl1 0 0 0 0 udncks3 udncks2 udncks1 udncks0 r/w r r r r r/w r/w r/w r/w selcntm register a a) for detailed information concerning the selcntm register refer to ?clock generator? on page 179 . udnctl1 register input clock (f clk ) iseln udncks3 udncks2 udncks1 udncks0 input prsi = 0 prsi = 1 0 0000 f xp1 f xx f xx /2 1f xp2 b b) f xp2 has hte same frequency as f xp1 , but does not stop in idle1 mode. f xx f xx /2 x0001f xp1 /2 f xx /2 f xx /4 x0010f xp1 /4 f xx /4 f xx /8 x0011f xp1 /8 f xx /8 f xx /16 x0100f xp1 /16 f xx /16 f xx /32 x0101f xp1 /32 f xx /32 f xx /64 x0110f xp1 64 f xx /64 f xx /128 x0111f xp1 /128 f xx /128 f xx /256 x1000f xp1 /256 f xx /256 f xx /512 x1001f xp1 /512 f xx /512 f xx /1024 x1010f xp1 /1024 f xx /1024 f xx /2048 x 1 0 1 1 ? ascka0 c c) asckd0 is an external clock only for uartd0. for uartd1-5 the setting is prohibited. other than above ? setting prohibited
421 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 (3) udnctl2 - uartdn control register 2 the udnctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartdn. this register can be read or written in 8-bit units. reset input sets this register to ffh. caution clear the udnctl0.udnpwr bit to 0 or clear the udntxe and udnrxe bits to 00 before rewriting the udnctl2 register. note f uclk : clock frequency selected by udnctl1.udncks[3:0] (4) baud rate the baud rate is obtained by the following equation. f uclk = frequency of base clock selected by the udnctl1.udncks[3:0]. k = value set using the udnctl2.udnbrs[7:0] bits (k = 4, 5, 6, ?, 255) udnbrs7 udnctl2 udnbrs 6 udnbrs 5 udnbrs 4 udnbrs 3 udnbrs 2 udnbrs 1 udnbrs0 6 5 4 3 2 1 after reset ffh r/w address: ud0ctl2 fffffa02h, ud1ctl2 fffffa12h, ud2ctl2 fffffa22h 7 0 udn brs7 0 0 0 0 : 1 1 1 1 udn brs6 0 0 0 0 : 1 1 1 1 udn brs5 0 0 0 0 : 1 1 1 1 udn brs4 0 0 0 0 : 1 1 1 1 udn brs3 0 0 0 0 : 1 1 1 1 udn brs2 0 1 1 1 : 1 1 1 1 udn brs1 0 0 1 : 0 0 1 1 udn brs0 0 1 0 : 0 1 0 1 default (k) 4 5 6 : 252 253 254 255 serial clock f uclk /4 f uclk /5 f uclk /6 : f uclk /252 f uclk /253 f uclk /254 f uclk /255 setting prohibited b aud rate f uclk 2k -------------- - [bp s] =
422 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 (5) baud rate error the baud rate error is obtained by the following equation. caution 1. the baud rate error during transmission must be within the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in (7) allowable baud rate range during reception. example  base clock frequency f xx = 20 mhz  setting value of ? prsi = 0: f xp1 = f xx = 20mhz ? udnctl1.udncks[3:0] = 0001 b : f uclk = f xp1 /2 = 10 mhz ? udnctl2.udnbrs[7:0] = 0011 0100 b : k = 52  target baud rate = 153,600 bps  actual baud rate = 10 mhz / (2 52) = 153,846 [bps]  baud rate error = (153,846/153,600 ? 1) 100 = 0.160 [%] (6) baud rate setting example e rror (%) actual baud rate (baud rate with error) target baud rate (correct baud rate) --------------------------------------------------------------------------- - 1 ? () 100 [% ] = table 15-3 baud rate generator setting data (normal operation, f xp1 =20mhz, prsi = 0) target baud rate udnctl1 udnctl2 actual baud rate [bps] baud rate error (%) [bps] selector divider divider k 300 08h 256 82h 130 300.48 0.16 600 08h 256 41h 65 600.96 0.16 1,200 07h 128 41h 65 1,201.92 0.16 2,400 06h 64 41h 65 2,403.85 0.16 4,800 05h 32 41h 65 4,807.69 0.16 9,600 04h 16 41h 65 9,615.38 0.16 19,200 03h 8 41h 65 19,230.77 0.16 31,250 02h 4 50h 80 31,250.00 0.00 38,400 02h 4 41h 65 38,461.54 0.16 76,800 01h 2 41h 65 76,923.08 0.16 153,600 00h 1 41h 65 153,846.15 0.16 312,500 00h 1 20h 32 312.500 0.0
423 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 table 15-4 baud rate generator setting data (normal operation, f xp1 =16mhz, prsi = 0) target baud rate udnctl1 udnctl2 actual baud rate [bps] baud rate error (%) [bps] selector divider divider k 300 08h 256 68h 104 300.48 0.16 600 08h 256 34h 52 600.96 0.16 1,200 07h 128 34h 52 1,201.92 0.16 2,400 06h 64 34h 52 2,403.85 0.16 4,800 05h 32 34h 52 4,807.69 0.16 9,600 04h 16 34h 52 9,615.38 0.16 19,200 03h 8 34h 52 19,230.77 0.16 31,250 03h 8 20h 32 31,250.00 0.00 38,400 02h 4 34h 52 38,461.54 0.16 76,800 01h 2 34h 52 76,923.08 0.16 153,600 00h 1 34h 52 153,846.15 0.16 312,500 00h 1 1ah 26 307,692.31 ?1.54
424 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 (7) allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error during reception must be set within the allowable error range using the following equation. figure 15-12 allowable baud rate range during reception as shown in figure 15-12 , the receive data latch timing is determined by the counter set using the udnctl2 register following start bit detection. the transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, the following is the theoretical result. fl = (brate) - 1 brate:uartdn baud rate k: setting value of udnctl2.udnbrs[7:0] fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: therefore, the maximum baud rate that can be received by the destination is as follows. fl 1 data frame (11 fl) flmin flmax uartn transfer rate s tart bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate s top bit s tart bit bit 0 bit 1 bit 7 parity bit latch timing s top bit s tart bit bit 0 bit 1 bit 7 parity bit s top bit f l min 11 fl k2 ? 2 k ----------- - fl ? 21k 2 + 2k ------------------- fl == b r max flmin 11 ? () 1 ? 22k 21k 2 + ------------------- b rate ==
425 asynchronous serial interface (uartd) chapter 15 user?s manual u18743ee1v2um00 similarly, obtaining the following maximum allowable transfer rate yields the following. therefore, the minimum baud rate that can be received by the destination is as follows. obtaining the allowable baud rate error for uartdn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 15-5 maximum/minimum allowable baud rate error note 1. the reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: setting value of udnctl2.udnbrs[7:0] 10 1 1 ------ flmax 11 fl k 2 + 2 k ------------ fl ? 21k 2 ? 2k ------------------ - f l == flmax 21k 2 ? 20k ------------------ - fl 11 = b r min flmax 11 ? () 1 ? 20k 21 k 2 ? ------------------ - brate == division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4+2.32% - 2.43% 8+3.52% - 3.61% 20 +4.26% - 4.30% 50 +4.56% - 4.58% 100 +4.66% - 4.67% 255 +4.72% - 4.72%
426 chapter 15 asynchronous serial interface (uartd) user?s manual u18743ee1v2um00 (8) baud rate during continuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. however, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result. figure 15-13 transfer rate during continuous transfer assuming 1 bit data length: fl; stop bit length: flstp; and base clock frequency: f uclk , we obtain the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + (2/f uclk ) 15.7 cautions when the clock supply to uartdn is stopped (for example, in idle1, idle2, or stop mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. the txddn pin output also holds and outputs the value it had immediately before the clock supply was stopped. however, the operation is not guaranteed after the clock supply is resumed. therefore, after the clock supply is resumed, the circuits should be initialized by setting the udnctl0.udnpwr, udnctl0.udnrxen, and udnctl0.udntxen bits to 000. s tart bit bit 0 bit 1 bit 7 parity bit s top bit fl 1 data frame fl fl fl fl fl fl flstp s tart bit of 2nd byte s tart bit bit 0
427 user?s manual u18743ee1v2um00 chapter 16 clocked serial interface (csib) the v850es/fx3-l microcontrollers have following instances of the clocked serial interface csib: throughout this chapter, the individual instances of csib are identified by ?n?, for example, cbnctl0 for the csibn control register 0. 16.1 features  transfer rate: 8 mbps to 2 kbps (using dedicated baud rate generator)  master mode and slave mode selectable  8-bit to 16-bit transfer, 3-wire serial interface  2 interrupt request signals (intcbnt and intcbnr)  serial clock and data phase switchable  transfer data length selectable in 1-bit units between 8 and 16 bits  transfer data msb-first/lsb-first switchable  3-wire transfer sobn: serial data output sibn: serial data input sckbn: serial clock input/output transmission mode, reception mode, and transmission/reception mode specifiable  baud rate generator input for csib0 csib v850es/fe3-l v850es/ff3-l v850es/fg3-l instances 2 names csib0 to csib1
428 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 16.2 configuration the following shows the block diagram of csibn. figure 16-1 block diagram of csibn note for details on the setting of f ck refer to ?cbnctl1 - csibn control register 1? on page 432 . csibn includes the following hardware. internal bus cbnctl2 cbnctl0 cbnstr controller intcbnr sobn intcbnt cbntx so latch phase control shif t register cbnrx cbnctl1 phase control sibn sckbn r o t c e l e s f xp1 /2 f xp1 /4 f xp1 /8 f xp1 /16 f xp1 /32 f xp1 /64 f brg (n=0) or t oaa01(n=1) or f xp1 /128(n=2,3) table 16-1 configuration of csibn item configuration registers csibn receive data register (cbnrx) csibn transmit data register (cbntx) control registers csibn control register 0 (cbnctl0) csibn control register 1 (cbnctl1) csibn control register 2 (cbnctl2) csibn status register (cbnstr)
429 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 (1) cbnrx - csibn receive data register the cbnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. the receive operation is started by reading the cbnrx register in the reception enabled status. if the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the cbnrxl register. reset input clears this register to 0000h. in addition to reset input, the cbnrx register can be initialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. (2) cbntx - csib transmit data register the cbntx register is a 16-bit buffer register used to write the csibn transfer data. this register can be read or written in 16-bit units. the transmit operation is started by writing data to the cbntx register in the transmission enabled status. if the transfer data length is 8 bits, the lower 8 bits of this register are read/write in 8-bit units as the cbntxl register. reset input clears this register to 0000h. in addition to reset input, the cbntx register can be initialized by clearing the cbnpwr bit of the cbnctl0 register. note the communication start conditions are shown below:  transmission mode (cbntxe bit = 1, cbnrxe bit = 0): write to cbntx register  transmission/reception mode (cbntxe bit = 1, cbnrxe bit = 1): write to cbntx register  reception mode (cbntxe bit = 0, cbnrxe bit = 1): read from cbnrx register after reset: 0000h r address : cb0rx fffffd04h, cb1rx fffffd14h, cbnrx after reset 0000h r/w address : cb0tx fffffd06h, cb1tx fffffd16h cbntx
430 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 16.3 csib control registers the following registers are used to control csibn.  csibn control register 0 (cbnctl0)  csibn control register 1 (cbnctl1)  csibn control register 2 (cbnctl2)  csibn status register (cbnstr) (1) cbnctl0 - csibn control register 0 cbnctl0 is a register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. . after reset: 04h addr ess: cb0ctl0: fffffd00, cb1ctl0: fffffd10 cb2ctl0: fffffd20, cb2ctl0: fffffd30 76543210 udnopt0 cbnpwr cbntxe note1 cbnrxe note1 cbndir note1 00 cbntws note1 cbnsce r/w r/w r/w r/w r/w r r r/w r/w cbnpwr specification of csibn operation disable/enable 0 disable csibn operation and reset the cbnstr register. 1 enable csibn operation. the cbnpwr bit controls the csibn operation and resets the internal circuit. cbntxe specification of transmit operation disable/enable 0 disable transmit operation 1 enable transmit operation the sobn output is low level and transmission is disabled when the cbntxe bit is 0. cbnrxe specification of transmit operation disable/enable 0 disable receive operation 1 enable receive operation  when the cbnrxe bit is cleared to 0, no reception complete interrupt is output even when the prescribed data is transferred in order to disable the receive operation, and the receive data (cbnrx register) is not updated. cbndir specification of transfer direction mode (msb/lsb) 0 msb first 1 lsb first cbntms transfer mode specification 0 single transfer mode 1 continuous transfer mode
431 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 note 1. these bits can only be rewritten when the cbnpwr bit = 0. however, the cbnpwr can be set to 1 at the same time as these bits are rewritten. 2. to abort reception/transmission forcibly, clear the cbnpwr bit (not the cbntxe bit or cbnrxe bit) to 0. the clock output stops at this time. cbnsce specification of start transfer disable/enable 0 reception start trigger invalid 1 recepetion start trigger valid this bit controls the behaviour upon a communication start trigger in master/slave single/continuous reception mode. to start the reception operation set the bit to 1 before performing a dummy read to the cbnrx register. to stop the reception operation in  single reception mode clear the cbnsce bit before reading the final data from the cbnrx register.  continuous reception mode clear the cbnsce bit at least one communication clock before the completion of the last data reception. for details refer to chapter 16.4?operation? on page 436.
432 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 (2) cbnctl1 - csibn control register 1 cbnctl1 is an 8-bit register that controls the csibn serial transfer operation. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution the cbnctl1 register can be rewritten only when the cbnctl0.cbnpwr bit = 0. cbn cks2 cbn cks1 cbn cks0 input input clock mode a a) m: master mode; s: slave mode n = 0 n = 1 prsi = 0 prsi = 1 prsi = 0 prsi = 1 000f xp1 /2 b b) do not use the csibn if fxp1 = frh (high speed internal oscillator clock) f xx /2 f xx /4 f xx /2 f xx /4 m 001f xp1 /4 b f xx /4 f xx /8 f xx /4 f xx /8 m 010f xp1 /8 b f xx /8 f xx /16 f xx /8 f xx /16 m 011f xp1 /16 b f xx /16 f xx /32 f xx /16 f xx /32 m 100f xp1 /32 b f xx /32 f xx /64 f xx /32 f xx /64 m 101f xp1 /64 b f xx /64 f xx /128 f xx /64 f xx /128 m 110 f brg c c) the baud rate generator output is also used for the watch timer. f brg ?m toaa01 d d) output of taa0 ? toaa01 m f xp1 /128 ? ? m 1 1 1 external clock sckbn s 0 cbnckp 0 0 1 1 specification of data transmission/ reception timing in relation to sckbn cbnctl1 0 cbndap 0 1 0 1 0 cbnck p cbndap cbncks 2 cbncks1 cbncks0 after reset 00h r/w address : cb0ctl1 fffffd01h, cb1ctl1 fffffd11h, d 7 d 6 d 5 d 4 d 3 d 2 d 1 d0 sckbn (i/o) sibn capture sobn (output) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d0 sckbn (i/o) sibn capture sobn (output) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d0 sckbn (i/o) sibn capture (output) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d0 sckbn (i/o) sibn capture (output) communication type 1 communication type 2 communication type 3 communication type 4
433 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 note prsi can be set by the option bytes: refer to ?flash memory? on page 259 for details. (3) cbnctl2 - csibn control register 2 cbnctl2 is an 8-bit register that controls the number of csibn serial transfer bits. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution the cbnctl2 register can be rewritten only when the cbnctl0.cbnpwr bit = 0 or when both the cbntxe and cbnrxe bits = 0. note if the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the lsb of the cbntx and cbnrx registers. after reset: 00h r/w address : cb0ctl2 fffffd02h, cb1ctl2 fffffd12h, 0 cbnctl2 0 0 0 cbncl 3 cbncl 2 cbncl 1 cbncl 0 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits cbncl3 0 0 0 0 0 0 0 0 1 cbncl2 0 0 0 0 1 1 1 1 cbncl1 0 0 1 1 0 0 1 1 cbncl0 0 1 0 1 0 1 0 1 serial register bit length
434 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 transfer data length change function the csibn transfer data length can be set in 1-bit units between 8 and 16 bits using the cbnctl2.cbncl3 to cbnctl2.cbncl0 bits. when the transfer bit length is set to a value other than 16 bits, set the data to the cbntx or cbnrx register starting from the lsb, regardless of whether the transfer start bit is the msb or lsb. any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. figure 16-2 (i) transfer bit length = 10 bits, msb first figure 16-3 (ii) transfer bit length = 12 bits, lsb first 15 10 9 0 s obn s ibn insertion of 0 0 s obn 11 12 15 s ibn insertion of 0
435 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 (4) cbnstr - csibn status register cbnstr is an 8-bit register that displays the csibn status. this register can be read or written in 8-bit or 1-bit units, but the cbntsf flag is read-only. reset input clears this register to 00h. in addition to reset input, the cbnstr register can be initialized by clearing (0) the cbnctl0.cbnpwr bit. note in case of an overrun error, the reception interrupt intcbnr behaves different, depending on the transfer mode:  continuous transfer mode the reception interrupt intcbnr is generated.  single transfer mode no interrupt is generated. in either case the overflow flag cbnstr.cbnove is set to 1 and the previous data in cbnrx will be overwritten with the new data. cbntsf communication stopped communicating cbntsf 0 1 communication status flag cbnstr 0 0 0 0 0 0 cbnove after reset 00h r/w address: cb0str fffffd03h, cb1str fffffd13h ? during transmission, this register is set when data is prepared in the cbntx register, and during reception, it is set when a dummy read of the cbnrx register is performed. when transfer ends, this flag is cleared to 0 at the last edge of the clock. no overrun overrun cbnove 0 1 overrun error flag ? an overrun error occurs when the next reception starts without performing a cpu read of the value of the receive buffer, upon completion of the receive operation. the cbnove flag displays the overrun error occurrence status in this case. ? the cbnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it. < > < >
436 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 16.4 operation 16.4.1 single transfer mode (mas ter mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (see 16.3 (2) cbnctl1 - csibn control register 1), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe, and cbnsce bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) write transfer data to the cbntx register (transmission start). (6) the reception complete interrupt request signal (intcbnr) is output. (7) read the cbnrx register before clearing the cbnpwr bit to 0. (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop operation of csibn (end of transmission/reception). to continue transfer, repeat steps (5) to (7) before (8). in transmission mode or transmission/reception mode, communication is not started by reading the cbnrx register. cbntx write (55h) cbnrx read (aah) (aah) (55h) 1 0 1 1 0 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (transmit data) sckbn cbntx aah 00h 00h cbnrx shift register intcbnr note sibn sobn 0 0 0 1 0 0 1 0 1 1 cbntsf cbnsce (1) (5) (6) (8) (7) (2) (3) (4)
437 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 note 1. in single transmission or single transmission/reception mode, the intcbnt signal is not generated. when communication is complete, the intcbnr signal is generated. 2. the processing of steps (3) and (4) can be set simultaneously. caution in case the csib interface is operating in  single transmit/reception mode (cbnctl0.cbntms = 0)  communication type 2 respectively type 4 (cbnctl1.cbndap = 1) pay attention to following effect: in case the next transmit should be initiated immediately after the occurrence of the reception completion interrupt intcbnr any write to the cbntx register is ignored as long as the communication status flag is still reflecting an ongoing communication (cbntsf = 1). thus the new transmission will not be started. for transmitting data continuously use one of the following options:  use continuous transfer mode (cbnctl0.cbntms = 1).  if single transfer mode (cbnctl0.cbntms = 0) should be used, cbnstr.cbntsf = 0 needs to be verified before writing data to the cbntx register.
438 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 16.4.2 single transfer mode (master mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (see 16.3 (2) cbnctl1 - csibn control register 1), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe and cbnctl0.cbnsce bits to 1, cbnctl0.txe to 0, at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. (7) set the cbnsce bit to 0 to set the final receive data status. (8) read the cbnrx register before setting the cbnpwr bit to "0". (9) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the csibn operation (end of reception). to continue transfer, repeat steps (5) and (6) before (7). (at this time, (5) is not a dummy read, but a receive data read combined with the reception trigger.) note the processing of steps (3) and (4) can be set simultaneously. (aah) 1 0 1 1 00 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (receive data) sckbn cbnrx cbnrx read (55h) shift register cbnsce cbntsf intcbnr sibn sobn 0 l (1) (2) (3) (4) (5) (6) (7) (9) (8) cbnrx read (aah) aah 00h 00h
439 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 16.4.3 continuous mode (master mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 3 (see 16.3 (2) cbnctl1 - csibn control register 1), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbntxe, cbnrxe, and cbnsce bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) write transfer data to the cbntx register (transmission start). (6) the transmission enable interrupt request signal (intcbnt) is received and transfer data is written to the cbntx register. (7) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (8) (7) (7) (6) (5) (1) (2) (3) (4) 96h 00h cch 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 55h cbntx sckbn sobn sibn intcbnt intcbnr cbntsf cbnsce shift register so latch cbnrx 0 0 0 0 aah 96h cch 1 1 1 0 0 0 00h 1 01 0 0
440 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation of csibn (end of transmission/reception). to continue transfer, repeat steps (5) to (7) before (8). in transmission mode or transmission/reception mode, the communication is not started by reading the cbnrx register. 16.4.4 continuous mode (mast er mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 2 (see 16.3 (2) cbnctl1 - csibn control register 1), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe bit to 1 and specify the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit to 1 to enable the csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (7) set the cbnctl0.cbnsce bit = 0 while the last data being received to set the final receive data status. (8) (6) (6) (7) (5) (1) (2) (3) (4) 1 0 0 0 0 0 0 01 1 1 1 1 55h s ckbn cbn s ce s ibn intcnr cbn t s f s hift register cbn rx 1 1 0 55h aah aah 00h 00h s obn l
441 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation of csibn (end of reception). to continue transfer, repeat steps (5) and (6) before (7). 16.4.5 continuous re ception mode (error) msb first (cbnctl0.cbndir bit = 0), communication type 2 (see 16.3 (2) cbnctl1 - csibn control register 1), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe bit to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit = 1 to enable csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. (7) if the data could not be read before the end of the next transfer, the cbnstr.cbnove flag is set to 1 upon the end of reception and the reception interrupt intcbnr is output again. (8) (9) (10) (7) (6) (5) aah 00h 00h 1 0 0 0 0 0 01 1 1 1 1 s ckbn s ibn intcbnr cbnove 55h 55h 0 1 0 aah 1 (1) (2) (3) (4) s obn l cbnt s f s hift register cbnrx
442 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 (8) overrun error processing is performed after checking that the cbnove bit = 1 in the intcbnr interrupt servicing. (9) clear cbnove bit to 0. (10)check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation csibn (end of reception). 16.4.6 continuous mode (slave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 2 (see 16.3 (2) cbnctl1 - csibn control register 1), transfer data length = 8 bits (cbnctl2.csncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (8) (7) (7) (6) (5) 96h 00h cch 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 55h cbntx sckbn sobn sibn intcbnt intcbnr shift register so latch cbnrx 0 0 0 0 0 0 aah 96h cch 1 0 0 0 1 1 cbntsf cbnsce 00h (1) (2) (3) (4)
443 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 (3) set the cbntxe, cbnrxe and cbnsce bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the transmission/reception enabled status. (4) set the cbnpwr bit to 1 to enable supply of the csibn operation. (5) write the transfer data to the cbntx register. (6) the transmission enable interrupt request signal (intcbnt) is received and the transfer data is written to the cbntx register. (7) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register. (8) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation of csibn (end of transmission/reception). to continue transfer, repeat steps (5) to (7) before (8). note in order to start the entire data transfer the cbntx register has to be written initially, as done in step (5) above. if this step is omitted also no data will be received.
444 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 discontinued transmission in case the csib is operating in continuous slave transmission mode (cbnctl0.cbntms = 1, cbnctl1.cbncks[2:0] = 111 b ) and new data is not written to the cbntx register the sobn pin outputs the level of the last bit. figure 16-4 outlines this behaviour. figure 16-4 discontinued slave transmission the example shows the situation that two data bytes (55 h , aa h ) are transmitted correctly, but the third (96 h ) fails. (1) data 55 h is written (by the cpu) to cbntx. (2) the master issues the clock sckbn and transmission of 55 h starts. (3) intcbnt is generated and the next data aa h is written to cbntx promptly, i.e. before the first data has been transmitted completely. (4) transmission of the second data aa h continues correctly and intcbnt is generated. but this time the next data is not written to cbntx in time. (5) since there is no new data available in cbntx, but the master continuous to apply sckbn clocks, sobn remains at the level of the transmitted last bit. (6) new data (96 h ) is written to cbntx. (7) with the next sckbn cycle transmission of the new data (96 h ) starts. as a consequence the master receives a corrupted data byte from (5) onwards, which is made up of a random number of the repeated last bit of the former data and some first bits of the new data. 0 s ckbn s obn intcbnt cbntx cbnt s f 1010 01 1 1 0 10 10 10 55h aah 1001011 0 96h (1) (2) (4) (5) (6) (7) (3)
445 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 16.4.7 continuous mode (sla ve mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (see 16.3 (2) cbnctl1 - csibn control register 1), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0, 0, 0, 0) (1) clear the cbnctl0.cbnpwr bit to 0. (2) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (3) set the cbnctl0.cbnrxe and cbnctl0.cbnsce bits to 1 at the same time as specifying the transfer mode using the cbndir bit, to set the reception enabled status. (4) set the cbnpwr bit = 1 to enable csibn operation. (5) perform a dummy read of the cbnrx register (reception start trigger). (6) the reception complete interrupt request signal (intcbnr) is output. read the cbnrx register. (7) check that the cbnstr.cbntsf bit = 0 and set the cbnpwr bit to 0 to stop the operation of csibn (end of reception). to continue transfer, repeat steps (5) and (6) before (7). (7) (6) (6) (5) 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn sibn intcbn r cbn tsf cbnsce shift register cbn rx 1 1 55h aah 00h 00h aah 0 (1) (2) (3) (4)
446 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 16.4.8 clock timing figure 16-5 (i) communication type 1 (cbnckp = 0, cbndap = 0) figure 16-6 (ii) communication type 3 (cbnckp = 1, cbndap = 0) d6 d5 d4 d3 d2 d1 sckbn sobn d0 d7 sibn capture reg-r/w intcbnt interrupt cbntsf intcbnr interrupt note note d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf
447 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 figure 16-7 (iii) communication type 2 (cbnckp = 0, cbndap = 1) figure 16-8 (iv) communication type 4 (cbnckp = 1, cbndap = 1) note 1. the intcbnt interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. in the single transmission or single transmission/reception modes, the intcbnt interrupt request signal is not generated, but the intcbnr interrupt request signal is generated upon completion of communication. 2. the intcbnr interrupt occurs if reception is correctly completed and receive data is ready in the cbnrx register while reception is enabled, and if an overrun error occurs. in the single mode, the intcbnr interrupt request signal is generated even in the transmission mode, upon completion of communication. d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt note 1 intcbnr interrupt note 2 cbntsf
448 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 16.5 output pins (1) sckbn pin when csibn operation is disabled (cbnctl0.cbnpwr bit = 0), the sckbn pin output status is as follows. note the output level of the sckbn pin changes if any of the cbnctl1.cbnckp and cbncks2 to cbncks0 bits is rewritten. (2) sobn pin when csibn operation is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. note 1. the sobn pin output changes when any one of the cbnctl0.cbntxe, cbnctl0.cbndir bits, and cbnctl1.cbndap bit is rewritten. 2. : don?t care cbnckp cbncks2 cbncks1 cbncks0 sckbn pin output 0 don?t care don?t care don?t care fixed to high level 1 1 1 1 high impedance other than above fixed to low level cbntxe cbndap cbndir sobn pin output 0 fixed to low level 1 0 sobn latch value (low level) 1 0 cbntxn value (msb) 1 cbntxn value (lsb)
449 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 16.6 operation flow (1) single transmission note set the cbnsce bit to 1 in the initial setting. caution in the slave mode, data cannot be correctly transmitted if the next transfer clock is input earlier than the cbntx register is written. start no yes intcbnt interrupt signal? data to be transferred next exists? end yes ye s initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register (start transfer). cbnpwr bit = 0 (cbnctl0) ye s cbntsf bit = 1? (cbnstr) no
450 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 (2) single reception note set the cbnsce bit to 1 in the initial setting. caution in the single mode, data cannot be correctly received if the next transfer clock is input earlier than the cbnrx register is read. start no intcbnr interrupt signal? last data? end ye s ye s no initial setting (cbnctl0 note , cbnctl1 registers, etc.) cbnrx register dummy read (start reception) cbnsce bit = 0 (cbnctl0) cbnpwr bit = 0 (cbnctl0) cbnrx register read cbnrx register read
451 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 (3) single transmission/reception note 1. set the cbnsce bit to 1 in the initial setting. 2. if the next transfer is reception only, dummy data is written to the cbntx register. caution even in the single mode, the cbnstr.cbnove flag is set to 1. if only transmission is used in the transmission/reception mode, therefore, programming without checking the cbnove flag is recommended. start initial setting (cbnctl0 note 1 , cbnctl1 registers, etc.) write cbntx register (start transfer). end cbnpwr bit = 0, cbntxe bit = cbnrxe bit = 0 (cbnctl0) no transmission/reception transmission reception intcbnr interrupt signal? yes transfer end? write cbntx register note 2 . read cbnrx register. read cbnrx register. no yes transfer end? write cbntx register note 2 . no yes transfer end? write cbntx register note 2 . no yes b b a a
452 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 (4) continuous transmission note set the cbnsce bit to 1 in the initial setting. start no ye s intcbnt interrupt signal? data to be transferred next exists? end ye s ye s initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register (start transfer). cbnpwr bit = 0 (cbnctl0) ye s cbntsf bit = 1? (cbnstr) no
453 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 (5) continuous reception note set the cbnsce bit to 1 in the initial setting. caution in the master mode, the clock is output without limit when dummy data is read from the cbnrx register. to stop the clock, execute the flow marked ? in the above flowchart. in the slave mode, malfunction due to noise during communication can be prevented by executing the flow marked ? in the above flowchart. before resuming communication, set the cbnctl0.cbnsce bit to 1, and read dummy data from the cbnrx register. start end no no ye s intcbnr bit = 1? cbnove bit = 1? (cbnstr) no ye s initial setting (cbnctl0 note , cbnctl1 registers, etc.) cbnrx register dummy read (start reception) cbnrx register read cbnrx register read cbnrx register read cbnrx register read ye s is data being received last data? cbnsce bit = 0 (cbnctl0) cbnsce bit = 1 (cbnctl0) no intcbnr interrupt signal? ye s cbnove bit clear (cbnstr)
454 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00 (6) continuous transmission/reception note set the cbnsce bit to 1 in the initial setting. start end no no intcbnr interrupt signal? yes no intcbnt interrupt signal? yes initial setting (cbnctl0 note , cbnctl1 registers, etc.) write cbntx register. cbnrx register read ye s yes is data completely received last data? no write cbntx register. yes is data being transferred last data? no cbnove bit = 0? (cbnstr) cbnove bit clear (cbnstr) cbnpwr bit = 0 (cbnctl0)
455 clocked serial interface (csib) chapter 16 user?s manual u18743ee1v2um00 caution 1. when transferring transmit data and receive data using dma transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. check that the no overrun error has occurred by reading the cbnstr.cbnove bit after dma transfer has been completed. 2. in regards to registers that are forbidden from being rewritten during operations (cbnctl0.cbnpwr bit is 1), if rewriting has been carried out by mistake during operations, set the cbnctl0.cbnpwr bit to 0 once, then initialize csibn. registers to which rewriting during operation are prohibited are shown below. cbnctl0 register: cbntxe, cbnrxe, cbndir, cbntms bit cbnctl1 register: cbnckp, cbndap, cbncks2-cbncks0 bit cbnctl2 register: cbncl3-cbncl0 bit 3. in the single transfer mode (cbnctl0.cbntms bit = 0), when the cbnctl1.cbndap bit is set to 1 and the next reception/transmission are started by using the receive completion interrupt intcbnr, the reception/ transmission operations from the second time are not performed for 0.5 clocks of the sckbn after the receive completion interrupt intcbnr is generated. to perform the continuous transfer, use the continuous transfer mode. 4. when csibn is operated in slave mode input an external clock via sckbn pin only after the transmission -/and/or reception process is started.
456 chapter 16 clocked serial interface (csib) user?s manual u18743ee1v2um00
457 user?s manual u18743ee1v2um00 chapter 17 i 2 c bus (iic) this microcontroller has one instance of this i 2 c bus interface. note throughout this chapter, the individual instances of this i 2 c bus interface identified by ?n? (n = 0). 17.1 features the i2c provides a synchronous serial interface with the following features:  supports master and slave mode  8-bit data transfer  transfer speed ? up to 100 kbit/s (standard mode) ? up to 400 kbit/s (fast mode)  two wire interface ? scln: serial clock ? sdan: serial data  noise filter on scln and sdan input 17.2 i 2 c pin configuration the i 2 c function requires to define the pins scl0n and sda0n as input and open drain output pins simultaneously. in the following, the pin configuration registers are listed to be set up properly for i 2 c:  pmc9.pmc914, pmc9.pmc915 = 1: alternative mode  pfce9.pfce914 = pfce9.pfce915 = 1, together with pfc9.pfc914 = pfc9.pfc915 = 0: select alternative function 3  pf9.pfc914 = pf9.pfc915 = 1: open drain output
458 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.3 configuration the block diagram of the i 2 cn is shown below. figure 17-1 block diagram of i 2 cn iicen dq cln1, cln0 sdan scln intiicn lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn stcfn iicbsyn stcenn iicrsvn cldn dadn smcn dfcn cln1 cln0 clxn prescaler internal bus internal bus iic control register n (iiccn) iic status register n (iicsn) set clear slave address register n (svan) noise eliminator match signal iic shift register n (iicn) so latch star t condition generator data hold time correction circuit acknowledge output circuit wake-up controller n-ch open-drain output acknowledge detector star t condition detector stop condition detector serial clock counter interrupt request signal generator noise eliminator serial clock controller serial clock wait controller bus status detector iic clock select register n (iiccln) iic function expansion register n (iicxn) iic flag register n (iicfn) n-ch open-drain output ocksn0 iic division clock select register m (ocksn) ocksn1 ocksthn ocksenn prescaler iiclkps = f xp1 to f xp1 /5 iiclktc f xp1
459 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 a serial bus configuration example is shown below. figure 17-2 serial bus configuration example using i 2 c bus i 2 cn includes the following hardware. s da s cl s da +v dd +v dd s cl s da s cl s lave cpu3 address 3 s da s cl s lave ic address 4 s da s cl s lave ic address n master cpu1 s lave cpu1 address 1 s erial data bus s erial clock master cpu2 s lave cpu2 address 2 table 17-1 configuration of i 2 cn item configuration registers iic shift register n (iicn) slave address register n (svan) control registers iic control register n (iiccn) iic status register n (iicsn) iic flag register n (iicf0n) iic clock select register n (iiccln) iic function expansion register n (iicxn) iic division clock select registers (ocksn)
460 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (1) iic shift register n (iicn) the iicn register converts 8-bit serial data into 8-bit parallel data and vice versa, and can be used for both transmission and reception. write and read operations to the iicn register are used to control the actual transmit and receive operations. (2) slave address register n (svan) the svan register sets local addresses when in slave mode. (3) so latch the so latch is used to retain the output level of the sda0n pin. (4) wakeup controller this circuit generates an interrupt request when the address received by this register matches the address value set to the svan register or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated following either of two triggers:  falling edge of eighth or ninth clock of the serial clock (set by iiccn.wtimn bit)  interrupt occurrence due to stop condition detection (set by iiccn.spien bit) (8) serial clock controller in master mode, this circuit generates the clock output via the scl0n pin from the sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals.
461 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the scl0n pin. (12) start condition generator a start condition is issued when the iiccn.sttn bit is set. however, in the communication reservation disabled status (iicfn.iicrsvn = 1), this request is ignored and the iicfn.stcfn bit is set if the bus is not released (iicfn.iicbsyn = 1). (13) bus status detector whether the bus is released or not is ascertained by detecting a start condition and stop condition. however, the bus status cannot be detected immediately after operation, so set the bus status detector to the initial status by using the iicfn.stcenn bit. (14) stop condition generator a stop condition is generated when the iicc0.spt0 bit is set.
462 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.4 iic registers the i 2 c interfaces are controlled by the following registers.  iic control registers iiccn  iic status registers iicsn  iic flag registers iicfn  iic clock select registers iiccln  iic function expansion registers iicxn  iic division clock select registers ocksn the following registers are also used.  iic shift registers iicn  slave address registers svan
463 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (1) iiccn - iicn control registers the iiccn registers enable/stop i 2 cn operations, set the wait timing, and set other i 2 c operations. these registers can be read or written in 8-bit or 1-bit units. set the spie0, wtim0, and acke0 bits when the iice bit is 0 or during the wait period. when setting the iice0 bit from "0" to "1", these bits can also be set at the same time. reset input sets this register to 00h. after reset: 00 h r/w address: iicc0 fffffd82 h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn iicen specification of i 2 cn operation enable/disable 0 operation stopped. iicsn register reset note 1 . internal operation stopped. 1 operation enabled. condition for clearing (iicen = 0) condition for setting (iicen = 1)  cleared by instruction  after reset  set by instruction lreln exit from communications 0 normal operation 1 this exits from the current communication operation and sets stand-by mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0n and sda0n lines are set to high impedance. the sttn and sptn bits and the mstsn, excn, coin, trcn, ackdn, and stdn bits of the iicsn register are cleared. the stand-by mode following exit from communications remains in effect until the following communication entry conditions are met.  after a stop condition is detected, restart is in master mode.  an address match occurs or an extension code is received after the start condition. condition for clearing (lreln = 0) note 2 condition for setting (lreln = 1)  automatically cleared after execution  after reset  set by instruction wreln wait cancellation control 0 wait not cancelled 1 wait cancelled. this setting is automatically cleared after wait is cancelled. condition for clearing (wreln = 0) note 2 condition for setting (wreln = 1)  automatically cleared after execution  after reset  set by instruction
464 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 note 1. the iics register, iicfn.stcfn and iicfn.iicbsyn bits, and iiccln.cldn and iiccln.dadn bits are reset. 2. this flag?s signal is invalid when the iicen = 0. note this flag?s signal is invalid when the iicen = 0. spien enable/disable generation of interrupt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spien = 0) note 2 condition for setting (spien = 1)  cleared by instruction  after reset  set by instruction wtimn control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for the master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for the master device. in order to generate the ninth clock on scln, the wait status must be cancelled by writing to iicn or setting iiccn.wreln = 1. consequently the ninth clock will be delayed until the wait status is cancelled. during address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. this bit setting becomes valid when the address transfer is completed. in master mode, a wait is inserted at the falling edge of the ninth clock during address transfer. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, however, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtimn = 0) note condition for setting (wtimn = 1)  cleared by instruction  after reset  set by instruction acken acknowledgement control 0 acknowledgment disabled. 1 acknowledgment enabled. during the ninth clock period, the sda0n line is set to low level. the acke0 bit setting is invalid for address reception. in this case, ack is generated when the addresses match. however, the acke0 bit setting is valid for reception of the extension code. condition for clearing (acken = 0) note condition for setting (acken = 1) note  cleared by instruction  after reset  set by instruction
465 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 note 1. clearing the iicen bit to 0 invalidates the signals of this flag. 2. the sttn bit is 0 if it is read immediately after data setting. caution if the i2c0 operation is enabled (iice0 bit = 1) when the scl00 line is high level and the sda00 line is low level, the start condition is detected immediately. to avoid this, after enabling the i2c0 operation, immediately set the lrel0 bit to 1 with a bit manipulation instruction. remark the lrel0 and wrel0 bits are 0 when read after the data has been set. sttn start condition trigger 0 start condition is not generated. 1 when bus is released (in stop mode): a start condition is generated (for starting as master). the sda0n line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, the scl0n line is changed to low level. during communication with a third party: if the communication reservation function is enabled (iicfn.iicrsvn = 0)  this trigger functions as a start condition reserve flag. when set, it releases the bus and then automatically generates a start condition. if the communication reservation function is disabled (iicrsvn = 1)  the iicfn.stcfn bit is set. this trigger does not generate a start condition. in the wait state (when master device): a restart condition is generated after the wait is released. cautions concerning set timing for master reception: cannot be set during transfer. can be set only when the acken bit has been set to 0 and the slave has been notified of final reception. for master transmission: a start condition cannot be generated normally during the ack period. set during the wait periodafter the ninth clock output. for slave: even when the communication reservation function is disabled (iicrsvn bit = 1), the communication reservation status is entered. setting to 1 at the same time as the spt0 bit is prohibited. when the stt0 bit is set to 1, setting the stt0 bit to 1 again is disabled until the bit is cleared to 0. condition for clearing (sttn = 0) note condition for setting (sttn = 1)  cleared by loss in arbitration  cleared after start condition is generated by master device  when the lreln = 1 (communication save)  when the iicen= 0 (operation stop)  after reset  set by instruction
466 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 note 1. set the sptn bit only in master mode. however, when the iicrsvn bit is 0, the sptn bit must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see ?cautions? on page 511 . 2. clearing the iicen bit to 0 invalidates the signals of this flag. 3. the sptn bit is 0 if it is read immediately after data setting. caution when the trcn = 1, the wreln bit is set during the ninth clock and wait is cancelled, after which the trcn bit is cleared and the sda0n line is set to high impedance. sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device?s transfer). after the sda0n line goes to low level, either set the scl0n line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sda0n line is changed from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set during transfer. can be set only when the acken bit has been set to 0 and during the wait period after the slave has been notified of final reception. for master transmission: a stop condition cannot be generated normally during the ack period. set (1) during the wait period.  sptn cannot be set at the same time as the sttn bit.  the sptn bit can be set only when in master mode note 1 .  when the wtimn bit has been set to 0 and the sptn bit is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. when the ninth clock must be output to apply the ack on the bus by the receiving device, proceed as follows: - change iiccn.wtimn from 0 to 1 in order to receive an additional interrupt after the ninth clock. - cancel the wait state by iiccn.wreln = 1 or by writing to the iicn register. - upon the interrupt after the ninth clock require to set the stop condition by iiccn.stpn = 1. by this the wait status will be cancelled and the stop condition will be generated on the bus.  when the spt0 bit is set to 1, setting the spt0 bit to 1 again is disabled until the bit is cleared to 0. condition for clearing (sptn = 0) note 2 condition for setting (sptn = 1)  cleared by loss in arbitration  automatically cleared after stop condition is detected  when the lreln = 1 (communication save)  when the iicen = 0 (operation stop)  after reset  set by instruction
467 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (2) iicsn - iicn status registers the iicsn registers indicate the status of the i 2 cn bus. these registers are read-only, in 8-bit or 1-bit units. the iics0 register can only be read when the iicc0.stt0 bit is 1 or during the wait period.  when the cpu operates with the subclock and the main clock oscillation is stopped  when the cpu operates with the low speed internal oscillation clock reset input sets this register to 00h. note any bit manipulation instruction targeting this register also clears this bit. after reset: 00h r address: iics0 fffffd86 h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn mstsn master device status 0 slave device status or communication stand-by status 1 master device communication status condition for clearing (mstsn = 0) condition for setting (mstsn = 1)  when a stop condition is detected  when the aldn = 1 (arbitration loss)  cleared by lreln = 1 (communication save)  when the iicen bit changes from 1 to 0 (operation stop)  after reset  when a start condition is generated aldn arbitration loss detection 0 this status means either that there was no arbitration or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the mstsn bit is cleared. condition for clearing (aldn = 0) condition for setting (aldn = 1)  automatically cleared after the iicsn register is read note  when the iicen bit changes from 1 to 0 (operation stop)  after reset  when the arbitration result is a ?loss?.
468 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn = 0) condition for setting (excn = 1)  when a start condition is detected  when a stop condition is detected  cleared by lreln = 1 (communication save)  when the iicen bit changes from 1 to 0 (operation stop)  after reset  when the higher four bits of the received address data are either ?0000? or ?1111? (set at the rising edge of the eighth clock). coin matching address detection 0 addresses do not match. 1 addresses match. condition for clearing (coin = 0) condition for setting (coin = 1)  when a start condition is detected  when a stop condition is detected  cleared by lreln bit = 1 (communication save)  when the iicen bit changes from 1 to 0 (operation stop)  after reset  when the received address matches the local address (svan register) (set at the rising edge of the eighth clock). trcn transmit/receive status detection 0 receive status (other than transmit status). the sda0n line is set to high impedance. 1 transmit status. the value in the so latch is enabled for output to the sda0n line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trcn = 0) condition for setting (trcn = 1)  when a stop condition is detected  cleared by lreln = 1 (communication save)  when the iicen bit changes from 1 to 0 (operation stop)  cleared by wreln = 1 note  when the aldn bit changes from 0 to 1 (arbitration loss)  after reset master  when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave  when a start condition is detected when not used for communication master  when a start condition is generated slave  when ?1? is input by the first byte?s lsb (transfer direction specification bit) ackdn ack detection 0 ack was not detected.
469 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 note the trcn bit is cleared and sda0n line becomes high impedance when the wreln bit is set and the wait state is canceled at the ninth clock by trcn = 1. 1 ack was detected. condition for clearing (ackdn = 0) condition for setting (ackd = 1)  when a stop condition is detected  at the rising edge of the next byte?s first clock  cleared by lreln = 1 (communication save)  when the iicen bit changes from 1 to 0 (operation stop)  after reset  after the sda0n bit is set to low level at the rising edge of the scl0n pin?s ninth clock stdn start condition detection 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn = 0) condition for setting (stdn = 1)  when a stop condition is detected  at the rising edge of the next byte?s first clock following address transfer  cleared by lreln = 1 (communication save)  when the iicen bit changes from 1 to 0 (operation stop)  after reset  when a start condition is detected spdn stop condition detection 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spdn = 0) condition for setting (spdn = 1)  at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition  when the iicen bit changes from 1 to 0 (operation stop)  after reset  when a stop condition is detected
470 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (3) iicfn - iicn flag registers the registers set the i 2 cn operation mode and indicate the i 2 c bus status. these registers can be read or written in 8-bit or 1-bit units. however, the stcfn and iicbsyn bits are read-only. iicrsvn enables/disables the communication reservation function. the initial value of the iicbsyn bit is set by using the stcenn bit (see ?cautions? on page 511 ). the iicrsvn and stcenn bits can be written only when operation of i 2 cn is disabled (iiccn.iicen = 0). after operation is enabled, iicfn can be read. reset input sets this register to 00h. after reset: 00 h r/w note address: iicf0 fffffd8a h <7><6>5432<1><0> iicfn stcfn iicbsyn 0000stcenniicrsvn stcfn sttn clear 0 start condition issued 1 start condition cannot be issued, sttn bit cleared condition for clearing (stcfn = 0) condition for setting (stcfn = 1)  cleared by iiccn.sttn = 1  when iicc0.iice0 bit = 0  after reset  when start condition is not issued and sttn flag is cleared during communication reservation is disabled (iicrsvn = 1). iicbsyn i 2 cn bus status 0 bus released status 1 bus communication status condition for clearing (iicbsyn = 0) condition for setting (iicbsyn = 1)  when stop condition is detected  when iicc0.iice0 bit = 0  after reset  when start condition is detected  by setting the iiccn.iicen bit when the stcenn = 0 stcenn initial start enable trigger 0 start conditions cannot be generated until a stop condition is detected following operation enable (iicen bit = 1). 1 start conditions can be generated even if a stop condition is not detected following operation enable (iicen = 1). condition for clearing (stcenn = 0) condition for setting (stcenn = 1)  when start condition is detected  after reset  setting by instruction
471 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 note bits 6 and 7 are read-only bits. caution 1. write the stcenn bit only when operation is stopped (iicen = 0). 2. when the stcenn = 1, the bus released status (iicbsyn = 0) is recognized regardless of the actual bus status immediately after the i 2 cn bus operation is enabled. therefore, to issue the first start condition (sttn = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. 3. write the iicrsvn bit only when operation is stopped (iicen = 0). iicrsvn communication reservation function disable bit 0 communication reservation enabled 1 communication reservation disabled condition for clearing (iicrsvn = 0) condition for setting (iicrsvn = 1)  clearing by instruction  after reset  setting by instruction
472 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (4) iiccln - iicn clock select registers the iiccln registers set the transfer clock for the i 2 cn bus. these registers can be read or written in 8-bit or 1-bit units. however, the cldn and dadn bits are read-only. the smcn, cln1, and cln0 bits are set by the combination of the iicxn.clxn bit and the ocksthn, ocksn[1:0] bits of the ocksn register (see ?transfer rate setting? on page 475 ). reset input clears these registers to 00 h . note bits 4 to 7 of iiccln are read-only bits. after reset: 00h r/w note address: iiccl0 fffffd84 h 76<5><4>3210 iiccln 0 0 cldndadnsmcndfcn cln1 cln0 cldn detection of scl0n pin level (valid only when iiccn.iicen = 1) 0 the scl0n pin was detected at low level. 1 the scl0n pin was detected at high level. condition for clearing (cldn = 0) condition for setting (cldn = 1)  when the scl0n pin is at low level  when the iicen = 0 (operation stop)  after reset  when the scl0n pin is at high level dadn detection of sda0n pin level (valid only when iicen = 1) 0 the sda0n pin was detected at low level. 1 the sda0n pin was detected at high level. condition for clearing (dadn = 0) condition for setting (dad0n = 1)  when the sda0n pin is at low level  when the iicen = 0 (operation stop)  after reset  when the sda0n pin is at high level smcn operation mode switching 0 operation in standard mode. 1 operation in fast-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. the digital filter can be used only in fast-speed mode. in fast-speed mode, the transfer clock does not vary regardless of the dfcn bit setting (on/off). the digital filter is used to eliminate noise in fast-speed mode.
473 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (5) iicxn - iicn function expansion registers the iicxn registers provide additional transfer data rate configuration in fast- speed mode. setting of the iicxn.clxn is performed in combination with the iiccln.smcn, iiccln.cln[1:0], ocksn.ocksthn and ocksn.ocksn[1:0] (refer to ?transfer rate setting? on page 475 ) reset input clears these registers to 00 h . after reset: 00 h r/w address: iicx0 fffffd85 h 76543210 iicxn0000000clxn
474 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (6) ocksn - iicn division clock select registers the ocksn registers control the i 2 cn division clock. these registers can be read or written in 8-bit units. reset input sets this register to 00h. note prsi can be set by the option bytes: refer to ?flash memory? on page 259 for details. after reset: 00h r/w address: ocks0 fffff340 h 76543210 ocksn 0 0 0 ocksenn ocksthn 0 ocksn1 ocksn0 ocksenn operation setting of i 2 c division clock 0 disable i 2 c division clock operation. 1 enable i 2 c division clock operation. ocksthn ocksn1 ocksn0 selection of i 2 c division clock iiclkps prsi = 0 prsi = 1 000f xx /2 f xx /4 001f xx /3 f xx /6 010f xx /4 f xx /8 011f xx /5 f xx /10 1xxf xx f xx /2
475 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (7) transfer rate setting the nominal transfer rate of the i 2 c interface is determined by the root clock source f xp1 . the frequency of fxp1 can be set to fxp1or fxp1/2 by the prsi bit of the option byte (007bh). the f xp1 can be divided by 1 to 5, configured by ocksn.ocksthn and ocksn.ockstn[1:0] (refer to ?ocksn - iicn division clock select registers? on page 474 ). the output clock of this divider is named iiclkps.  iiclkps is passed through another configurable divider that finally outputs the clock for the serial transfer iiclktc. this divider is configured by iiccln.cl[1:0] and iicxn.clx0 according to the following tables: note the i 2 c interface input clock iiclkps must lie in the range of 1 mhz to 10 mhz. the following tables summarize the transfer rate settings: note prsi can be set by the option bytes: refer to ?flash memory? on page 259 for details. prsi iiccln.smcn mode table 0 0 standard table 17-2 on page 475 0 1 fast-speed table 17-3 on page 476 1 0 standard table 17-4 on page 476 1 1 fast-speed table 17-5 on page 477 table 17-2 prsi = 0: transfer rate settings in standard mode (iiccln.smcn = 0) iicxn. clxn iiccln. cln1 iiccln. cln0 selected clock ocksn transfer clock possible main system clock range (fxx) (reference) transfer speed from to 00 0 fxx/2 10h fxx/88 4 mhz 8.38 mhz 45.5khz ~ 95.2khz fxx/3 11h fxx/132 6 mhz 12.57 mhz 45.5khz ~ 95.2khz fxx/4 12h fxx/176 8 mhz 16.76 mhz 45.5khz ~ 95.2khz fxx/5 13h fxx/220 10 mhz 20.00 mhz 45.5khz ~ 90.9khz fxx 18h fxx/44 4 mhz 4.19 mhz 90.9khz ~ 95.2khz 00 1 fxx/2 10h fxx/172 8.38 mhz 16.76 mhz 48.7khz ~ 97.4khz fxx/3 11h fxx/258 12.57 mhz 20.00 mhz 48.7khz ~ 77.5khz fxx/4 12h fxx/344 16.76 mhz 20 mhz 48.7khz ~ 58.1khz fxx 13h fxx/86 4.19 mhz 8.38 mhz 48.7khz ~ 97.4khz 0 1 0 fxx ? fxx/86 4.19 mhz 8.38 mhz 48.7khz ~ 97.4khz 01 1 fxx/2 10h fxx/132 12.80 mhz 97.0khz fxx/3 11h fxx/198 19.20 mhz 97.0khz fxx 18h fxx/66 6.40 mhz 97.0khz other than above setting prohibited ? ? ? ?
476 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 table 17-3 prsi = 0: transfer rate settings in fast-speed mode (iiccln.smcn = 1) iicxn. clxn iiccln. cln1 iiccln. cln0 selected clock ocksn transfer clock possible main system clock range (fxx) (reference) transfer speed from to 00 x fxx/2 10h fxx/48 8 mhz 16.76 mhz 166.7khz ~ 349.2khz fxx/3 11h fxx/72 12 mhz 20 mhz 166.7khz ~ 277.8khz fxx/4 12h fxx/96 16 mhz 20 mhz 166.7khz ~ 208.3khz fxx/5 13h fxx/120 20 mhz 166.7khz 0 1 0 fxx 18h fxx/24 4 mhz 8.38 mhz 166.7khz ~ 349.2khz 01 1 fxx/2 10h fxx/36 12.80 mhz 355.6khz fxx/3 11h fxx/54 19.20 mhz 355.6khz fxx 18h fxx/18 6.4 mhz 355.6khz 10 x fxx/2 10h fxx/24 8 mhz 8.38 mhz 333.3khz ~ 349.2khz fxx/3 11h fxx/36 12 mhz 12.57 mhz 333.3khz ~ 349.2khz fxx/4 12h fxx/48 16 mhz 16.67 mhz 333.3khz ~ 349.2khz fxx/5 13h fxx/60 20 mhz 333.3khz fxx 18h fxx/12 4 mhz 4.19 mhz 333.3khz ~ 349.2khz 1 1 0 fxx ? fxx/12 4 mhz 4.19 mhz 333.3khz ~ 349.2khz other than above setting prohibited ? ? ? ? table 17-4 prsi = 1: transfer rate settings in standard mode (iiccln.smcn = 0) iicxn. clxn iiccln. cln1 iiccln. cln0 selected clock ocksn transfer clock possible main system clock range (fxx) (reference) transfer speed from to 00 0 fxx/4 10h fxx/176 8 mhz 16.76 mhz 45.5khz ~ 95.2khz fxx/6 11h fxx/264 12 mhz 20.00 mhz 45.5khz ~ 95.2khz fxx/8 12h fxx/352 16 mhz 20.00 mhz 45.5khz ~ 95.2khz fxx/10 13h fxx/440 20 mhz 45.5khz fxx/2 18h fxx/88 4 mhz 8.38 mhz 90.9khz ~ 95.2khz 00 1 fxx/4 10h fxx/344 16.76 mhz 20.00 mhz 48.7khz ~ 97.4khz fxx/2 18h fxx/172 8.38 mhz 16.76 mhz 48.7khz ~ 97.4khz 0 1 0 fxx/2 ? fxx/172 8.38 mhz 16.76 mhz 48.7khz ~ 97.4khz 0 1 1 fxx/2 18h fxx/132 12.80 mhz 97.0khz other than above setting prohibited ? ? ? ?
477 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 table 17-5 prsi = 1: transfer rate settings in fast-speed mode (iiccln.smcn = 1) iicxn. clxn iiccln. cln1 iiccln. cln0 selected clock ocksn transfer clock possible main system clock range (fxx) (reference) transfer speed from to 00 x fxx/4 10h fxx/96 16 mhz 20.00 mhz 166.7khz ~ 208.3khz fxx/2 18h fxx/48 8 mhz 8.38 mhz 166.7khz ~ 349.2khz 0 1 0 fxx/2 ? fxx/48 8 mhz 8.38 mhz 166.7khz ~ 349.2khz 0 1 1 fxx/2 18h fxx/36 12.80 mhz 355.6khz 10 x fxx/4 10h fxx/48 16 mhz 16.76 mhz 333.3khz ~ 349.2khz fxx/2 18h fxx/24 8 mhz 8.38 mhz 333.3khz ~ 349.2khz 1 1 0 fxx/2 ? fxx/24 8 mhz 8.38 mhz 333.3khz ~ 349.2khz other than above setting prohibited ? ? ? ?
478 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 clock stretching heavy capacitive load and the dimension of the external pull-up resistor on the i 2 c bus pins may yield extended rise times of the rising edge of scln and sdan. since the controller senses the level of the i 2 c bus signals it recognizes such situation and takes countermeasures by stretching the clock scln in order to ensure proper high level time t sclh of scln. after the microcontroller releases the (open-drain) scln pin it waits until the scln level exceeds the valid high level threshold v thh . then it does not pull scln to low level before the nominal high level time t sclh_nom has elapsed. this mechanism is the same used, when a slow i 2 c slave device is pulling down scln to low level to initiate a wait state. note it is assumed that the rise time f r is much bigger than the fall time f f . figure 17-3 shows an example. figure 17-3 clock stretching of scln the effective clock frequency appearing at the scln pin calculates to f scl_eff = 1 / (t scl_nom + t r ) with a nominal frequency of f scl_nom = 355.6 khz (t scl_nom = 2.812 s and a rise time of t r = 135 ns the effective frequency is f eff = 339.31 khz. t r t sclh t scll t r t scl_nom t scl_eff scl signal effective scl clock v thh
479 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (8) iicn - iicn shift registers the iicn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. these registers can be read or written in 8- bit units, but data should not be written to the iicn register during a data transfer. access (read/write) this register only during the wait period. accessing this register in communication states other than the wait period is prohibited. however, for the master device, this register can be written once only after the transmission trigger bit (iicc0.stt0 bit) has been set to 1. a wait state is released by writing the iicn register during the wait period, and data transfer is started. reset input clears these registers to 00 h . (9) svan - iicn slave address registers the svan registers hold the i 2 c bus?s slave addresses. these registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. rewriting these registers is prohibited when the iics0.std0 bit = 1 reset input sets this register to 00h. after reset: 00 h r/w address: ic0 fffffd80 h 76543210 iicn after reset: 00 h r/w address: sva0 fffffd83 h 76543210 svan 0
480 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.5 i 2 c bus mode functions 17.5.1 pin functions the serial clock pin (scl0n) and serial data bus pin (sda0n) are configured as follows. scl0n this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. sda0n this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 17-4 pin configuration diagram v dd scl0n sda0n scl0n sda0n v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
481 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition?, "address", "transfer direction specification", "data" and ?stop condition? output via the i 2 c bus?s serial data bus is shown below. figure 17-5 i 2 c bus serial data transfer timing the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0n) is continuously output by the master device. however, in the slave device, the scl0n pin?s low-level period can be extended and a wait can be inserted. 17.6.1 start condition a start condition is met when the scl0n pin is high level and the sda0n pin changes from high level to low level. the start condition for the scl0n and sda0n pins is a signal that the master device outputs to the slave device when starting a serial transfer. the slave device can defect the start condition. figure 17-6 start condition a start condition is output when the iiccn.sttn bit is set (1) after a stop condition has been detected (iicsn.spdn bit = 1). when a start condition is detected, the iicsn.stdn bit is set (1). 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 s cl0n s da0n s tart condition address r/w ack data data s top condition ack ack h s cl0n s da0n
482 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 caution when the iicc0.iice0 bit of the microcontroller is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. be sure to set the iicc0.iice0 bit to 1 when the scl00 and sda00 lines are high level. 17.6.2 addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the svan register. if the address data matches the values of the svan register, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition. figure 17-7 address note the interrupt request signal (intiicn) is generated if a local address or extension code is received during slave device operation. the slave address and the eighth bit, which specifies the transfer direction as described in ?transfer direction specification? on page 483 , are written together to iic shift register n (iicn) and then output. received addresses are written to the iicn register. the slave address is assigned to the higher 7 bits of the iicn register. address s cl0n 1 s da0n intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w
483 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.6.3 transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 17-8 transfer direction specification note the intiicn signal is generated if a local address or extension code is received during slave device operation. 17.6.4 acknowledge signal (ack ) the acknowledge signal (ack ) is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. the detection of ack is confirmed with the iics0.ackd0 bit. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following three factors:  reception was not performed normally.  the final data was received.  the receiving device (slave) does not exist for the specified address. when the receiving device sets the sda0n line to low level during the ninth clock, the ack signal becomes active (normal receive response). when the iiccn.acken bit is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes the iicsn.trcn bit to be set. when this trcn bit?s value is 0, it indicates receive mode. therefore, the acken bit should be set to 1. when the slave device is receiving (when trcn bit = 0), if the slave device does not need to receive any more data after receiving several bytes, clearing s cl0n 1 s da0n intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note
484 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 the acken bit to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trcn bit = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, clearing the acken bit to 0 will prevent the ack signal from being returned. this prevents the msb from being output via the sda0n line (i.e., stops transmission) during transmission from the slave device. figure 17-9 ack signal when the local address is received, an ack signal is automatically output in synchronization with the falling edge of the scl0n pin?s eighth clock regardless of the value of the acken bit. no ack signal is output if the received address is not a local address. the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected (iiccn.wtimn bit = 0): the ack signal is output at the falling edge of the scl0n pin?s eighth clock if the acken bit is set to 1 before wait cancellation. when 9-clock wait is selected (iiccn.wtimn bit = 1): the ack signal is automatically output at the falling edge of the scl0n pin?s eighth clock if the acken bit has already been set to 1. s cl0n 1 s da0n 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack
485 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.6.5 stop condition when the scl0n pin is high level, changing the sda0n pin from low level to high level generates a stop condition. a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. when used as the slave device, the start condition can be detected. figure 17-10 stop condition a stop condition is generated when the iiccn.sptn bit is set to 1. when the stop condition is detected, the iicsn.spdn bit is set to 1 and the intiicn signal is generated when the iiccn.spien bit is set to 1. h s cl0n s da0n
486 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.6.6 wait signal (wait ) the wait signal (wait ) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0n pin to low level notifies the communication partner of the wait status. when the wait status has been cancelled for both the master and slave devices, the next data transfer can begin. (1) when master device has a nine-clock wait and slave device has an eight- clock wait (master: transmission, slave: reception, and iiccn.acken bit = 1) figure 17-11 wait signal (1/2) s cl0n 6 s da0n 78 9 123 s cl0n iicn 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iicn s cl0n acken master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iicn data write (cancel wait) s lave wait after output of eighth clock. ffh is written to iicn register or iiccn.wreln bit is set to 1. transfer lines wait signal from slave wait signal from master
487 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (2) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acken bit = 1) figure 17-12 wait signal (2/2) a wait may be automatically generated depending on the setting of the iiccn.wtimn bit. normally, when the iiccn.wreln bit is set to 1 or when ffh is written to the iicn register on the receiving side, the wait status is cancelled and the transmitting side writes data to the iicn register to cancel the wait status. the master device can also cancel the wait status via either of the following methods.  by setting the iiccn.sttn bit to 1  by setting the iiccn.sptn bit to 1 s cl0n 6 s da0n 789 123 s cl0n iicn 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iicn s cl0n acken master master and slave both wait after output of ninth clock. iicn data write (cancel wait) s lave ffh is written to iicn register or wreln bit is set to 1. output according to previously set acken bit value transfer lines wait signal from master /slave wait signal from slave
488 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.7 i 2 c interrupt request signals (intiicn) the following shows the value of the iicsn register at the intiicn interrupt request signal generation timing and at the intiicn signal timing. 17.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) < 1 > when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 1: iicsn register = 1000x110b ? 2: iicsn register = 1000x000b ? 3: iicsn register = 1000x000b (wtimn bit = 1) ? 4: iicsn register = 1000xx00b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 ? 1: iicsn register = 1000x110b ? 2: iicsn register = 1000x100b ? 3: iicsn register = 1000xx00b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care d7 to d0 d7 to d0 sp ack r/w ack ack r/w ack d7 to d0 ack ack sp d7 to d0
489 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) < 1 > when wtimn bit = 0 sttn bit = 1 sptn bit = 1 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 1: iicsn register = 1000x110b ? 2: iicsn register = 1000x000b (wtimn bit = 1) ? 3: iicsn register = 1000xx00b (wtimn bit = 0) ? 4: iicsn register = 1000x110b (wtimn bit = 0) ? 5: iicsn register = 1000x000b (wtimn bit = 1) ? 6: iicsn register = 1000xx00b ? 7: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 sttn bit = 1 sptn bit = 1 ? 1 ? 2 ? 3 ? 4 ? 5 ? 1: iicsn register = 1000x110b ? 2: iicsn register = 1000xx00b ? 3: iicsn register = 1000x110b ? 4: iicsn register = 1000xx00b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0
490 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) < 1 > wh en wtim n bi t = 0 sptn bit = 1 ? ? 1 ? 2 ? 3 ? 4 ? 5 ? 1: iicsn register = 1010x110b ? 2: iicsn register = 1010x000b ? 3: iicsn register = 1010x000b (wtimn bit = 1) ? 4: iicsn register = 1010xx00b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 sptn bit = 1 ? ? 1 ? 2 ? 3 ? 4 ? 1: iicsn register = 1010x110b ? 2: iicsn register = 1010x100b ? 3: iicsn register = 1010xx00b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 st ad6 to ad0 r/w ack ack d7 to d0 ack sp d7 to d0 st ad6 to ad0 r/w ack ack d7 to d0 ack sp d7 to d0
491 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.7.2 slave device operation (1) start ~ address ~ data ~ data ~ stop <1> when wtimn bit = 0 ? 1: iicsn register = 0001x110b ? 2: iicsn register = 0001x000b ? 3: iicsn register = 0001x000b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 1: iicsn register = 0001x110b 2: iicsn register = 0001x100b 3: iicsn register = 0001xx00b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 r/w ack d7 to d0 ack ack sp d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 r/w ack d7 to d0 ack ack sp d7 to d0 ? ? ?
492 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address match) ? 1: iicsn register = 0001x110b ? 2: iicsn register = 0001x000b ? 3: iicsn register = 0001x110b ? 4: iicsn register = 0001x000b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 (after restart, address match) 1: iicsn register = 0001x110b 2: iicsn register = 0001xx00b 3: iicsn register = 0001x110b 4: iicsn register = 0001xx00b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 ? 1 ? 2 ? 3 ? 4 ? 5 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 ? 5 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? ? ? ?
493 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) ? 1: iicsn register = 0001x110b ? 2: iicsn register = 0001x000b ? 3: iicsn register = 0010x010b ? 4: iicsn register = 0010x000b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, extension code reception) ? 1: iicsn register = 0001x110b ? 2: iicsn register = 0001xx00b ? 3: iicsn register = 0010x010b ? 4: iicsn register = 0010x110b ? 5: iicsn register = 0010xx00b ? 6: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 to 2 ? 1 ? 2 ? 3 ? 4 ? 5 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 ? 6 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 5
494 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address mismatch (= not extension code)) 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 00000x10b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 (after restart, address mismatch (= not extension code)) ? 1: iicsn register = 0001x110b ? 2: iicsn register = 0001xx00b ? 3: iicsn register = 00000x10b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 ? 1 ? 2 ? 3 ? 4 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? ? ?
495 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.7.3 slave device operation (w hen receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when wtimn bit = 0 ? 1: iicsn register = 0010x010b ? 2: iicsn register = 0010x000b ? 3: iicsn register = 0010x000b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010x100b 4: iicsn register = 0010xx00b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 st ad6 to ad0 ? 1 ? 2 ? 3 ? 5 d7 to d0 d7 to d0 sp ack r/w ack ack r/w ack d7 to d0 ack ack sp d7 to d0 ? 4 ? ? ? ?
496 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (2) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address match) ? 1: iicsn register = 0010x010b ? 2: iicsn register = 0010x000b ? 3: iicsn register = 0001x110b ? 4: iicsn register = 0001x000b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 (after restart, address match) 1: iicsn register = 0010x010b ? 2: iicsn register = 0010x110b ? 3: iicsn register = 0010xx00b ? 4: iicsn register = 0001x110b ? 5: iicsn register = 0001xx00b ? 6: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 ? 1 ? 2 ? 3 ? 4 ? 5 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 ? 6 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 5 ?
497 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (3) start ~ code ~ data ~ start ~ code ~ data ~ stop ? 1: iicsn register = 0010x010b ? 2: iicsn register = 0010x000b ? 3: iicsn register = 0010x010b ? 4: iicsn register = 0010x000b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 (after restart, extension code reception) ? 1: iicsn register = 0010x010b ? 2: iicsn register = 0010x110b ? 3: iicsn register = 0010xx00b ? 4: iicsn register = 0010x010b ? 5: iicsn register = 0010x110b ? 6: iicsn register = 0010xx00b ? 7: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 1 ? 2 ? 3 ? 4 ? 7 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 5 ? 6
498 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (4) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, address mismatch (= not extension code)) ? 1: iicsn register = 0010x010b ? 2: iicsn register = 0010x000b ? 3: iicsn register = 00000x10b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 (after restart, address mismatch (= not extension code)) ? 1: iicsn register = 0010x010b ? 2: iicsn register = 0010x110b ? 3: iicsn register = 0010xx00b ? 4: iicsn register = 00000x10b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 ? 1 ? 2 ? 3 ? 4 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 ? 5 st ad6 to ad0 r/w r/w ack ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0
499 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop 17.7.5 arbitration loss operati on (operation as slave after arbitration loss) (1) when arbitration loss occurs during transmission of slave address data ? 1: iicsn register = 00000001b remarks 1. ? : generated only when spien bit = 1 2. n = 0 st ad6 to ad0 ? 1 r/w ack d7 to d0 ack ack sp d7 to d0 <1> when wtimn bit = 0 ? 1: iicsn register = 0101x110b (example: when aldn bit is read during interrupt servicing) ? 2: iicsn register = 0001x000b ? 3: iicsn register = 0001x000b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 ? 1: iicsn register = 0101x110b (example: when aldn bit is read during interrupt servicing) ? 2: iicsn register = 0001x100b ? 3: iicsn register = 0001xx00b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 r/w ack d7 to d0 ack ack sp d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 r/w ack d7 to d0 ack ack sp d7 to d0
500 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (2) when arbitration loss occurs during transmission of extension code < 1 > wh en wtim n bi t = 0 ? 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) ? 2: iicsn register = 0010x000b ? 3: iicsn register = 0010x000b ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 <2> when wtimn bit = 1 ? 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) ? 2: iicsn register = 0010x110b ? 3: iicsn register = 0010x100b ? 4: iicsn register = 0010xx00b ? 5: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 4 r/w ack d7 to d0 ack ack sp d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 ? 5 r/w ack d7 to d0 ack ack sp d7 to d0 ? 4
501 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.7.6 operation when arbitration loss occurs (1) when arbitration loss occurs during transmission of slave address data (2) when arbitration loss occurs during transmission of extension code ? 1: iicsn register = 01000110b (example: when aldn bit is read during interrupt servicing) ? 2: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 2. n = 0 st ad6 to ad0 ? 1 ? 2 r/w ack d7 to d0 ack ack sp d7 to d0 ? 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software ? 2: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 st ad6 to ad0 ? 1 ? 2 r/w ack d7 to d0 ack ack sp d7 to d0
502 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (3) when arbitration loss occurs during data transfer <1> when wtimn bit = 0 ? 1: iicsn register = 10001110b ? 2: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) ? 3: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 2. n = 0 <2> when wtimn bit = 1 ? 1: iicsn register = 10001110b ? 2: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) ? 3: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 2. n = 0 st ad6 to ad0 ? 1 ? 3 r/w ack d7 to d0 ack ack sp d7 to d0 ? 2 st ad6 to ad0 ? 1 ? 3 r/w ack d7 to d0 ack ack sp d7 to d0 ? 2
503 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (4) when arbitration loss occurs due to restart condition during data transfer (5) when arbitration loss occurs due to stop condition during data transfer <1> not extension code (example: address mismatch) ? 1: iicsn register = 1000x110b ? 2: iicsn register = 01000110b (example: when aldn bit is read during interrupt servicing) ? 3: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 <2> extension code ? 1: iicsn register = 1000x110b ? 2: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software ? 3: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 ? 1 ? 2 ? 3 st ad6 to ad0 r/w r/w ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 1 ? 2 ? 3 st ad6 to ad0 r/w r/w ack ack ack sp d7 to d0 d7 to d0 st ad6 to ad0 ? 1: iicsn register = 1000x110b ? 2: iicsn register = 01000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 n = 0 ? 1 ? 2 st ad6 to ad0 r/w ack d7 to d0 st
504 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (6) when arbitration loss occurs due to low level of sda0n pin when attempting to generate a restart condition (7) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition when wtimn bit = 1 sttn bit = 1 ? 1: iicsn register = 1000x110b ? 2: iicsn register = 1000xx00b ? 3: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 ? 1 ? 2 ? 3 ? 4 st ad6 to ad0 r/w ack ack ack sp d7 to d0 d7 to d0 ack d7 to d0 ? when wtimn bit = 1 sttn bit = 1 ? ? 1: iicsn register = 1000x110b ? 2: iicsn register = 1000xx00b ? 3: iicsn register = 01000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 st ad6 to ad0 ? 1 ? 3 r/w ack d7 to d0 ack sp ? 2
505 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (8) when arbitration loss occurs due to low level of sda0n pin when attempting to generate a stop condition when wtimn bit = 1 sptn bit = 1 ? ? 1: iicsn register = 1000x110b ? 2: iicsn register = 1000xx00b ? 3: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) ? 4: iicsn register = 00000001b remarks 1. ? : always generated ? : generated only when spien bit = 1 x: don?t care 2. n = 0 ? 1 ? 2 ? 3 ? 4 st ad6 to ad0 r/w ack ack ack d7 to d0 d7 to d0 ack sp d7 to d0
506 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.8 interrupt request signal (intiicn) the setting of the iiccn.wtimn bit determines the timing by which the intiicn register is generated and the corresponding wait control, as shown below. note 1. the slave device?s intiicn signal and wait period occur at the falling edge of the ninth clock only when there is a match with the address set to the svan register. at this point, the ack signal is output regardless of the value set to the iiccn.acken bit. for a slave device that has received an extension code, the intiicn signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the intiicn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not match the contents of the svan register and an extension code is not received, neither the intiicn signal nor a wait occurs. 3. the numbers in the table indicate the number of the serial clock?s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception  slave device operation: interrupt and wait timing are determined regardless of the wtimn bit.  master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtimn bit. (2) during data reception  master/slave device operation: interrupt and wait timing is determined according to the wtimn bit. (3) during data transmission  master/slave device operation: interrupt and wait timing is determined according to the wtimn bit. table 17-6 intiicn generation timing and wait control wtimn bit during slave device operation during master device operation address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 98 8 1 9 notes 1, 2 9 note 2 9 note 2 99 9
507 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting the iiccn.wreln bit to 1 ? by writing to the iicn register ? by start condition setting (iiccn.sttn bit = 1) note ? by stop condition setting (iiccn.sptn bit = 1) note note master only when an 8-clock wait has been selected (wtimn bit = 0), the output level of the ack signal must be determined prior to wait cancellation. (5) stop condition detection the intiicn signal is generated when a stop condition is detected. 17.9 address match detection method in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match detection is performed automatically by hardware. the intiicn signal occurs when a local address has been set to the svan register and when the address set to the svan register matches the slave address sent by the master device, or when an extension code has been received. 17.10 error detection in i 2 c bus mode, the status of the serial data bus pin (sda0n) during data transmission is captured by the iicn register of the transmitting device, so the data of the iicn register prior to transmission can be compared with the transmitted iicn data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match.
508 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.11 extension code  when the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (iicsn.excn bit) is set for extension code reception and an interrupt request signal (intiicn) is issued at the falling edge of the eighth clock. the local address stored in the svan register is not affected.  if 11110xx0 is set to the svan register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the intiicn signal occurs at the falling edge of the eighth clock ? higher four bits of data match: excn bit = 1 ? seven bits of data match: iicsn.coin bit = 1  since the processing after the interrupt request signal occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set the iiccn.lreln bit to 1 and the cpu will enter the next communication wait state. table 17-7 extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
509 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.12 arbitration when several master devices simultaneously output a start condition (when the iiccn.sttn bit is set to 1 before the iicsn.stdn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (iicsn.aldn bit) is set to 1 via the timing by which the arbitration loss occurred, and the scl0n and sda0n lines are both set to high impedance, which releases the bus. arbitration loss is detected based on the timing of the next interrupt request signal (the eighth or ninth clock, when a stop condition is detected, etc.) and the setting of the aldn bit to 1, which is made by software. for details of interrupt request timing, see ?i 2 c interrupt request signals (intiicn)? on page 488 . figure 17-13 arbitration timing example master 1 master 2 transfer lines s cl0n s da0n s cl0n s da0n s cl0n s da0n master 1 loses arbitration hi-z hi-z
510 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 note 1. when the iiccn.wtimn bit = 1, an interrupt request signal occurs at the falling edge of the ninth clock. when the wtimn bit = 0 and the extension code?s slave address is received, an interrupt request signal occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spien bit to 1 for master device operation. 17.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request signal (intiicn) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt request signals from occurring when addresses do not match. when a start condition is detected, wakeup stand-by mode is set. this wakeup stand-by mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, the iiccn.spien bit is set regardless of the wakeup function, and this determines whether interrupt request signals are enabled or disabled. table 17-8 status during arbitration and interrupt request signal generation timing status during arbitration interrupt request generation timing transmitting address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission transmitting extension code read/write data after extension code transmission transmitting data ack signal transfer period after data reception when restart condition is detected during data transfer when stop condition is detected during data transfer when stop condition is output (when iiccn.spien bit = 1) note 2 when sda0n pin is low level while attempting to output restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output restart condition when stop condition is output (when iiccn.spien bit = 1) note 2 when dsa0n pin is low level while attempting to output stop condition at falling edge of eighth or ninth clock following byte transfer note 1 when scl0n pin is low level while attempting to output restart condition
511 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.14 cautions (1) when iicfn.stcenn bit = 0 immediately after the i 2 cn operation is enabled, the bus communication status (iicfn.iicbsyn bit = 1) is recognized regardless of the actual bus status. to execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccln register. <2> set the iiccn.iicen bit. <3> set the iiccn.sptn bit. (2) when iicfn.stcenn bit = 1 immediately after i 2 cn operation is enabled, the bus released status (iicbsyn bit = 0) is recognized regardless of the actual bus status. to issue the first start condition (iiccn.sttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) when the iicc0.iice0 bit of the microcontroller is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. be sure to set the iicc0.iice0 bit to 1 when the scl00 and sda00 lines are high level. (4) determine the operation clock frequency by the iiccl0, iicx0, and ocks0 registers before enabling the operation (iicc0.iice0 bit = 1). to change the operation clock frequency, clear the iicc0.iice0 bit to 0 once. (5) after the iicc0.stt0 and iicc0.spt0 bits have been set to 1, they must not be re-set without being cleared to 0 first. (6) if transmission has been reserved, set the iiccn.spie0 bit to 1 so that an interrupt request is generated by the detection of a stop condition. after an interrupt request has been generated, the wait state will be released by writing communication data to i2c0, then transferring will begin. if an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait state because an interrupt request was not generated. however, it is not necessary to set the spie0 bit to 1 for the software to detect the iics0.msts0 bit."
512 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.15 communication operations 17.15.1 master operation 1 the following shows the flowchart for master communication when the communication reservation function is enabled (iicfn.iicrsvn bit = 0) and the master operation is started after a stop condition is detected (iicfn.stcenn bit = 0).
513 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 figure 17-14 master operation flowchart (1) iiccn h iicen = spien = wtimn = sptn = 1 iiccln h select transfer clock sttn = 1 start acken = 0 no no no no no no no no no yes yes yes yes yes yes yes intiicn = 1? wtimn = 0 acken = 1 intiicn = 1? intiicn = 1? trcn = 1? ackdn = 1? mstsn = 1? yes no intiicn = 1? intiicn = 1? ackdn = 1? wreln = 1 start reception yes (stop condition detection) wait wait time is secured by software yes (start condition generation) communication reservation start iicn write transfer stop condition detection, start condition generation by communication reservation generate stop condition (no slave with matching address) no (receive) address transfer completion yes (transmit) end start iicn write transfer data processing transfer completed? generate stop condition sptn = 1 (restart) end transfer completed? data processing
514 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 17.15.2 master operation 2 the following shows the flowchart for master communication when the communication reservation function is disabled (iicrsvn bit = 1) and the master operation is started without detecting a stop condition (stcenn bit = 1). figure 17-15 master operation flowchart (2) no (receive) iiccln h iicfn h iiccn h iicen = spien = wtimn = 1 sttn = 1 start no ye s iicbsyn = 0? no ye s wtimn = 0 acken = 1 wreln = 1 start reception acken = 0 sptn = 1 generate stop condition no ye s yes (transmit) intiicn = 1? no ye s ye s intiicn = 1? no ye s intiicn = 1? no ye s ackdn = 1? no ye s no ackdn = 1? trcn = 1? stcfn = 0? end transfer clock selection iicfn register setting iiccn register initial setting wait time is secured by software insert wait start iicn write transfer stop master communication master communication is stopped because bus is occupied yes (address transfer completion) start iicn write transfer generate stop condition (no slave with matching address) end data processing data processing reception completed? transfer completed? (restart)
515 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.15.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiicn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiicn interrupt servicing performs only status change processing and that the actual data communication is performed during the main processing. figure 17-16 software outline during slave operation therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main processing instead of intiicn signal. (1) communication mode flag this flag indicates the following communication statuses.  clear mode: data communication not in progress  communication mode data communication in progress (valid address detection stop condition detection, ack signal from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. this is the same status as an intiicn interrupt during normal data transfer. this flag is set in the interrupt processing block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clear processing (the address match is regarded as a request for the next data). i 2 c intiicn signal s etting, etc. s etting, etc. flag data main processing interrupt servicing
516 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 (3) communication direction flag this flag indicates the direction of communication and is the same as the value of iicsn.trcn bit. the following shows the operation of the main processing block during slave operation. start i 2 cn and wait for the communication enabled status. when communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmission operation until the master device stops returning ack signal. when the master device stops returning ack signal, transfer is complete. for reception, receive the required number of data and do not return ack signal for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart condition. this causes exit from communications.
517 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 figure 17-17 slave operation flowchart (1) the following shows an example of the processing of the slave device by an intiicn interrupt (it is assumed that no extension codes are used here). ye s ye s ye s ye s ye s ye s ye s ye s no no no no no no no no s ta rt communication mode? communication mode? communication mode? ready? ready? read data clear ready flag clear ready flag communication direction flag = 1? wtimn = 1 wreln = 1 acken = 0 wreln = 1 acken = wtimn = 1 ackdn = 1? wreln = 1 clear communication mode flag data processing data processing transfer completed? iicn data iiccn xxh iicen = 1 iiccln xxh iicfn xxh s election of transfer flag iicfn register setting
518 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 during an intiicn interrupt, the status is confirmed and the following steps are executed. <1> when a stop condition is detected, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, the communication mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, when the ready flag is set, operation returns from the interrupt while the iic0n bus remains in the wait status. note <1> to <3> in the above correspond to <1> to <3> in figure 17-18 . figure 17-18 slave operation flowchart (2) ye s ye s ye s no no no intiicn generated s et ready flag interrupt servicing completed interrupt servicing completed interrupt servicing completed termination processing s pdn = 1? s tdn = 1? coin = 1? lreln = 1 clear communication mode communication direction flag trcn s et communication mode flag clear ready flag <1> <2> <3>
519 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 17.16 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the iicsn.trcn bit, which specifies the data transfer direction, and then starts serial communication with the slave device. the shift operation of the iicn register is synchronized with the falling edge of the serial clock pin (scl0n). the transmit data is transferred to the so latch and is output (msb first) via the sda0n pin. data input via the sda0n pin is captured by the iicn register at the rising edge of the scl0n pin. the data communication timing is shown below.
520 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 figure 17-19 example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) start condition ~ address note to cancel slave wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l l l h h h l l acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data iicn ffh transmit s tart condition receive (when excn = 1) note note
521 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 figure 17-20 example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data note to cancel slave wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l l l l l h h h h l l l l l acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data iicn ffh note iicn ffh note iicn data transmit receive note note
522 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 figure 17-21 example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition note to cancel slave wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l l l h h h l acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data iicn address iicn ffh note iicn ffh note s top condition s tart condition transmit note note (when s pien = 1) receive (when s pien = 1)
523 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 figure 17-22 example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address note to cancel master wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l h h l acken m s t s n s ttn l l s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iicn address iicn ffh note note iicn data s tart condition
524 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00 figure 17-23 example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data note to cancel master wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h h l l l l l l h h h l l l l l acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iicn data iicn data iicn ffh note iicn ffh note
525 i 2 c bus (iic) chapter 17 user?s manual u18743ee1v2um00 figure 17-24 example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition note to cancel master wait, write ffh to iicn or set wreln. iicn ackdn s tdn s pdn wtimn h h l l l h acken m s t s n s ttn s ptn wreln intiicn trcn iicn ackdn s tdn s pdn wtimn acken m s t s n s ttn s ptn wreln intiicn trcn s cl0n s da0n processing by master device transfer lines processing by slave device 1234567892 1 d7d6d5d4d3d2d1d0ad5 ad6 iicn address iicn ffh note note iicn data s top condition s tart condition (when s pien = 1) n- ack (when s pien = 1)
526 chapter 17 i 2 c bus (iic) user?s manual u18743ee1v2um00
527 user?s manual u18743ee1v2um00 chapter 18 can controller (can) these microcontrollers feature an on-chip n-channel can (controller area network) controller that complies with the can protocol as standardized in iso 11898. the number of can channels is given in the table below: throughout this chapter, the individual channels of can are identified by ?n?, for example, c0gmctrl for the can0 global control register. throughout this chapter, the can message buffer registers are identified by ?m? (m = 0 to 31), for example c0mdata4m for can0 message data byte 4 of message buffer register m. can v850es/fe3-l v850es/ff3-l v850es/fg3-l channels 1 names can0
528 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.1 features  compliant with iso 11898 and tested according to iso/dis 16845 (can conformance test)  standard frame and extended frame transmission/reception enabled  transfer rate: 1 mbps max. (if can clock input 8 mhz, for 32 channels)  32 message buffers per channel  receive/transmit history list function  automatic block transmission function  multi-buffer receive block function  mask setting of four patterns is possible for each channel  data bit time, communication baud rate and sample point can be controlled by can module bit-rate prescaler register (cnbrp) and bit rate register (cnbtr) ? as an example the following sample-point configurations can be configured: ? 66.7%, 70.0%, 75.0%, 80.0%, 81.3%, 85.0%, 87.5% ? baud rates in the range of 10 kbps up to 1000 kbps can be configured  enhanced features: ? each message buffer can be configured to operate as a transmit or a receive message buffer ? transmission priority is controlled by the identifier or by mailbox number (selectable) ? a transmission request can be aborted by clearing the dedicated transmit-request flag of the concerned message buffer. ? automatic block transmission operation mode (abt) ? time stamp function for can channels 0 to n in collaboration with timers taa0 to taan capture channels
529 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.1.1 overview of functions table 18-1 presents an overview of the can controller functions. table 18-1 overview of functions function details protocol can protocol iso 11898 (standard and extended frame transmission/reception) baud rate maximum 1 mbps (can clock input 8 mhz) data storage storing messages in the can ram number of messages  32 message buffers per channel  each message buffer can be set to be either a transmit message buffer or a receive message buffer. message reception  unique id can be set to each message buffer.  mask setting of four patterns is possible for each channel.  a receive completion interrupt is generated each time a message is received and stored in a message buffer.  two or more receive message buffers can be used as a fifo receive buffer (multi-buffer receive block function).  receive history list function message transmission  unique id can be set to each message buffer.  transmit completion interrupt for each message buffer  message buffer number 0 to 7 specified as the transmit message buffer can be set for automatic block transfer. message transmission interval is programmable (automatic block transmission function (hereafter referred to as ?abt?)).  transmission history list function remote frame processing remote frame processing by transmit message buffer time stamp function  the time stamp function can be set for a message reception when a 16-bit timer is used in combination.  time stamp capture trigger can be selected (sof or eof in a can message frame can be detected.).  the time stamp function can be set for a transmit message. diagnostic function  readable error counters  ?valid protocol operation flag? for verification of bus connections  receive-only mode  single-shot mode  can protocol error type decoding  self-test mode release from bus-off state  forced release from bus-off (by ignoring timing constraint) possible by software.  no automatic release from bus-off (software must re-enable). power save mode  can sleep mode (can be woken up by can bus)  can stop mode (cannot be woken up by can bus)
530 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.1.2 configuration the can controller is composed of the following four blocks.  npb interface this functional block provides an npb (nec peripheral i/o bus) interface and means of transmitting and receiving signals between the can module and the host cpu.  mcm (memory control module) this functional block controls access to the can protocol layer and to the can ram within the can module.  can protocol layer this functional block is involved in the operation of the can protocol and its related settings. can ram this is the can memory functional block, which is used to store message ids, message data, etc. figure 18-1 block diagram of can module ctxdn crxdn cpu can module note: the can input clock can be chosen from - the main oscillator clock f xc - the peripheral clock f xp1 refer to chapter ?clock generator? for f can selection control. can ram npb (nec peripheral i/o bus) mcm (message control module) npb interface interrupt request can protocol layer can transceiver message buffer 0 message buffer 1 message buffer 2 f can note message buffer 3 message buffer m cnmask1 cnmask2 cnmask3 cnmask4 ... intcntrx intcnrec intcnerr intcnwup can_h can_l can bus tsoutcn
531 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.2 can protocol can (controller area network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class c). can is prescribed by iso 11898. for details, refer to the iso 11898 specifications. the can specification is generally divided into two layers: a physical layer and a data link layer. in turn, the data link layer includes logical link and medium access control. the composition of these layers is illustrated below. figure 18-2 composition of layers note can controller specification 18.2.1 frame format (1) standard format frame  the standard format frame uses 11-bit identifiers, which means that it can handle up to 2,048 messages. (2) extended format frame  the extended format frame uses 29-bit (11 bits + 18 bits) identifiers, which increases the number of messages that can be handled to 2,048 2 18 messages.  an extended format frame is set when ?recessive level? (cmos level of ?1?) is set for both the srr and ide bits in the arbitration field. physical layer prescription of signal level and bit description data link layer note logical link control (llc) medium access control (mac) acceptance filtering overload report recovery management data capsuled/not capsuled frame coding (stuffing/no stuffing) medium access management error detection error report acknowledgement s eriated/not seriated higher lower
532 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.2.2 frame types the following four types of frames are used in the can protocol. table 18-2 frame types (1) bus value the bus values are divided into dominant and recessive.  dominant level is indicated by logical 0.  recessive level is indicated by logical 1.  when a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 18.2.3 data frame and remote frame (1) data frame a data frame is composed of seven fields. figure 18-3 data frame note d: dominant = 0 r: recessive = 1 frame type description data frame frame used to transmit data remote frame frame used to request a data frame error frame frame used to report error detection overload frame frame used to delay the next data frame or remote frame r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8>
533 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (2) remote frame a remote frame is composed of six fields. figure 18-4 remote frame note 1. the data field is not transferred even if the control field?s data length code is not ?0000 b ?. 2. d: dominant = 0 r: recessive = 1 (3) description of fields (a) start of frame (sof) the start of frame field is located at the start of a data frame or remote frame. figure 18-5 start of frame (sof) note d: dominant = 0 r: recessive = 1  if dominant level is detected in the bus idle state, a hard-synchronization is performed (the current tq is assigned to be the sync segment).  if dominant level is sampled at the sample point following such a hard-synchronization, the bit is assigned to be a sof. if recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a disturbance only. no error frame is generated in such case. r d interframe space end of frame (eof) ack field crc field control field arbitration field s tart of frame ( s of) remote frame <1> <2> <3> <5> <6> <7> <8> r d 1 bit s tart of frame (interframe space or bus idle) (arbitration field)
534 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (b) arbitration field the arbitration field is used to set the priority, data frame/remote frame, and frame format. figure 18-6 arbitration field (in standard format mode) caution 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. note d: dominant = 0 r: recessive = 1 figure 18-7 arbitration field (in extended format mode) caution 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. note d: dominant = 0 r: recessive = 1 table 18-3 rtr frame settings table 18-4 frame format setting (ide bit) and number of identifier (id) bits r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) (1 bit) (1 bit) id28 id18 r d r1 r0 rtr ide srr identifier identifier arbitration field (control field) (11 bits) (18 bits) id17 id0 (1 bit) (1 bit) (1 bit) id28 id18 frame type rtr bit data frame 0 (d) remote frame 1 (r) frame format srr bit ide bit number of bits standard format mode none 0 (d) 11 bits extended format mode 1 (r) 1 (r) 29 bits
535 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (c) control field the control field sets ?dlc? as the number of data bytes in the data field (dlc = 0 to 8). figure 18-8 control field note d: dominant = 0 r: recessive = 1 in a standard format frame, the control field?s ide bit is the same as the r1 bit. table 18-5 data length setting caution in the remote frame, there is no data field even if the data length code is not 0000 b . r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) data length code data byte count dlc3 dlc2 dlc1 dlc0 0000 0 bytes 0001 1 byte 0010 2 bytes 0011 3 bytes 0100 4 bytes 0101 5 bytes 0110 6 bytes 0111 7 bytes 1000 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0
536 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (d) data field the data field contains the amount of data (byte units) set by the control field. up to 8 units of data can be set. figure 18-9 data field note d: dominant = 0 r: recessive = 1 (e) crc field the crc field is a 16-bit field that is used to check for errors in transmit data. figure 18-10 crc field note d: dominant = 0 r: recessive = 1  the polynomial p(x) used to generate the 15-bit crc sequence is expressed as follows. p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1  transmitting node: transmits the crc sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field.  receiving node: compares the crc sequence calculated using data bits that exclude the stuffing bits in the receive data with the crc sequence in the crc field. if the two crc sequences do not match, the node issues an error frame. r d data 0 (8 bits) m s b l s b data 7 (8 bits) m s b l s b data field (crc field) (control field) r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field or control field)
537 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (f) ack field the ack field is used to acknowledge normal reception. figure 18-11 ack field note d: dominant = 0 r: recessive = 1  if no crc error is detected, the receiving node sets the ack slot to the dominant level.  the transmitting node outputs two recessive-level bits. (g) end of frame (eof) the end of frame field indicates the end of data frame/remote frame. figure 18-12 end of frame (eof) note d: dominant = 0 r: recessive = 1 (h) interframe space the interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next.  the bus state differs depending on the error status. ? error active node the interframe space consists of a 3-bit intermission field and a bus idle field. figure 18-13 interframe space (error active node) r d ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field) r d end of frame (7 bits) (interframe space or overload frame) (ack field) r d interframe space intermission (3 bits) bus idle (0 to bits) (frame) (frame)
538 chapter 18 can controller (can) user?s manual u18743ee1v2um00 note 1. bus idle: state in which the bus is not used by any node. 2. d: dominant = 0 r: recessive = 1 ? error passive node the interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. figure 18-14 interframe space (error passive node) note 1. bus idle: state in which the bus is not used by any node. suspend transmission: sequence of 8 recessive-level bits transmitted from the node in the error passive status. 2. d: dominant = 0 r: recessive = 1 usually, the intermission field is 3 bits. if the transmitting node detects a dominant level at the third bit of the intermission field, however, it executes transmission.  operation in error status table 18-6 operation in error status r d interframe space intermission (3 bits) s uspend transmission (8 bits) bus idle (0 to bits) (frame) (frame) error status operation error active a node in this status can transmit immediately after a 3-bit intermission. error passive a node in this status can transmit 8 bits after the intermission.
539 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.2.4 error frame an error frame is output by a node that has detected an error. figure 18-15 error frame note d: dominant = 0 r: recessive = 1 table 18-7 definition of error frame fields no. name bit count definition <1> error flag 1 6 error active node: outputs 6 dominant-level bits consecutively. error passive node: outputs 6 recessive-level bits consecutively. if another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> error flag 2 0 to 6 nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> error delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> error bit ? the bit at which the error was detected. the error flag is output from the bit next to the error bit. in the case of a crc error, this bit is output following the ack delimiter. <5> interframe space/ overload frame ? an interframe space or overload frame starts from here. <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag 2 error flag 1 error bit error frame
540 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.2.5 overload frame an overload frame is transmitted under the following conditions.  when the receiving node has not completed the reception operation  if a dominant level is detected at the first two bits during intermission  if a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter note the can is internally fast enough to process all received frames not generating overload frames. figure 18-16 overload frame note d: dominant = 0 r: recessive = 1 table 18-8 definition of overload frame fields no name bit count definition <1> overload flag 6 outputs 6 dominant-level bits consecutively. <2> overload flag from other node 0 to 6 the node that received an overload flag in the interframe space outputs an overload flag. <3> overload delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here. <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload fram e overload delimiter overload flag overload flag frame overload frame
541 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.3 functions 18.3.1 determining bus priority (1) when a node starts transmission:  during bus idle, the node that output data first transmits the data. (2) when more than one node starts transmission:  the node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value).  the transmitting node compares its output arbitration field and the data level on the bus. table 18-9 determining bus priority (3) priority of data frame and remote frame  when a data frame and a remote frame are on the bus, the data frame has priority because its rtr bit, the last bit in the arbitration field, carries a dominant level. note if the extended-format data frame and the standard-format remote frame conflict on the bus (if id28 to id18 of both of them are the same), the standard-format remote frame takes priority. 18.3.2 bit stuffing bit stuffing is used to establish synchronization by appending 1 bit of inverted-level data if the same level continues for 5 bits, in order to prevent a burst error. table 18-10 bit stuffing level match continuous transmission level mismatch stops transmission at the bit where mismatch is detected and starts reception at the following bit transmission during the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 inverted-level bit of data is inserted before the following bit. reception during the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, reception is continued after deleting the next bit.
542 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.3.3 multi masters as the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 18.3.4 multi cast although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. 18.3.5 can sleep mode/can stop mode function the can sleep mode/can stop mode function puts the can controller in waiting mode to achieve low power consumption. the controller is woken up from the can sleep mode by bus operation but it is not woken up from the can stop mode by bus operation (the can stop mode is controlled by cpu access). 18.3.6 error control function (1) error types table 18-11 error types type description of error detection state detection method detection condition transmission/ reception field/frame bit error comparison of the output level and level on the bus (except stuff bit) mismatch of levels transmitting/ receiving node bit that is outputting data on the bus at the start of frame to end of frame, error frame and overload frame. stuff error check of the receive data at the stuff bit 6 consecutive bits of the same output level receiving node start of frame to crc sequence crc error comparison of the crc sequence generated from the receive data and the received crc sequence mismatch of crc receiving node crc field form error field/frame check of the fixed format detection of fixed format violation receiving node crc delimiter ack field end of frame error frame overload frame ack error check of the ack slot by the transmitting node detection of recessive level in ack slot transmitting node ack slot
543 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (2) output timing of error frame (3) processing in case of error the transmission node re-transmits the data frame or remote frame after the error frame. (however, it does not re-transmit the frame in the single-shot mode.) (4) error state (a) types of error states the following three types of error states are defined by the can specification:  error active  error passive bus-off these types of error states are classified by the values of the tec7 to tec0 bits (transmission error counter bits) and the rec6 to rec0 bits (reception error counter bits) as shown in table 18-13 . the present error state is indicated by the can module information register (cninfo). when each error counter value becomes equal to or greater than the error warning level (96), the tecs0 or recs0 bit of the cninfo register is set to 1. in this case, the bus state must be tested because it is considered that the bus has a serious fault. an error counter value of 128 or more indicates an error passive state and the tecs1 or recs1 bit of the cninfo register is set to 1.  if the value of the transmission error counter is greater than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the boff bit of the cninfo register is set to 1.  if only one node is active on the bus at startup (i.e., a particular case such as when the bus is connected only to the local station), ack is not returned even if data is transmitted. consequently, re-transmission of the error frame and data is repeated. in the error passive state, however, the transmission error counter is not incremented and the bus-off state is not reached. table 18-12 output timing of error frame type output timing bit error, stuff error, form error, ack error error frame output is started at the timing of the bit following the detected error. crc error error frame output is started at the timing of the bit following the ack delimiter.
544 chapter 18 can controller (can) user?s manual u18743ee1v2um00 table 18-13 types of error states note the value of the transmission error counter (tec) is invalid when the boff bit is set to 1. if an error that increments the value of the transmission error counter by +8 while the counter value is in a range of 248 to 255, the counter is not incremented and the bus-off state is assumed. type operation value of error counter indication of cninfo register operation specific to error state error active transmission 0 to 95 tecs1, tecs0 = 00 outputs an active error flag (6 consecutive dominant-level bits) on detection of the error. reception 0 to 95 recs1, recs0 = 00 transmission 96 to 127 tecs1, tecs0 = 01 reception 96 to 127 recs1, recs0 = 01 error passive transmission 128 to 255 tecs1, tecs0 = 11 outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). reception 128 or more recs1, recs0 = 11 bus-off transmission 256 or more (not indicated) note boff = 1, tecs1, tecs0 = 11 communication is not possible. messages are not stored when receiving frames, however, the following operations of <1>, <2>, and <3> are done. <1> tsout toggles. <2> rec is incremented/decremented. <3> valid bit is set. if the can module is entered to the initialization mode and then transition request to any operation mode is made, and when 11 consecutive recessive-level bits are detected 128 times, the error counter is reset to 0 and the error active state can be restored.
545 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (b) error counter the error counter counts up when an error has occurred, and counts down upon successful transmission and reception. the error counter is updated immediately after error detection. (c) occurrence of bit error in intermission an overload frame is generated. caution if an error occurs, it is controlled according to the contents of the transmission error counter and reception error counter before the error occurred. the value of the error counter is incremented after the error flag has been output. table 18-14 error counter state transmission error counter (tec7 to tec0 bits) reception error counter (rec6 to rec0 bits) receiving node detects an error (except bit error in the active error flag or overload flag). no change +1 (when reps = 0) receiving node detects dominant level following error flag of error frame. no change +8 (when reps = 0) transmitting node transmits an error flag. [as exceptions, the error counter does not change in the following cases.] <1> ack error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> a stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. +8 no change bit error detection while active error flag or overload flag is being output (error-active transmitting node) +8 no change bit error detection while active error flag or overload flag is being output (error-active receiving node) no change +8 (reps bit = 0) when the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant-level bits. when the node detects 8 consecutive dominant levels after a passive error flag +8 (transmitting) +8 (during reception, when reps = 0) when the transmitting node has completed transmission without error ( 0 if error counter = 0) ?1 no change when the receiving node has completed reception without error no change  ?1 (1 rec6 to rec0 127, when reps = 0)  0 (rec6 to rec0 = 0, when reps = 0)  value of 119 to 127 is set (when reps = 1)
546 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (5) recovery from bus-off state when the can module is in the bus-off state, the can module permanently sets its output signals (ctxdn) to recessive level. the can module recovers from the bus-off state in the following bus-off recovery sequence. 1. a request to enter th e can initialization mode 2. a request to enter a can operation mode (a)recovery operation through normal recovery sequence (b)forced recovery operation that skips recovery sequence (a) recovery from bus-off state through normal recovery sequence the can module first issues a request to enter the initialization mode (refer too timing <1> in figure 18-17 on page 547 ). this request will be immediately acknowledged, and the opmode bits of the cnctrl. register are cleared to 000 b . processing such as analyzing the fault that has caused the bus-off state, re-defining the can module and message buffer using application software, or stopping the operation of the can module can be performed by clearing the gom bit to 0. next, the module requests to change the mode from the initialization mode to an operation mode (refer to timing <2> in figure 18-17 on page 547 ). this starts an operation to recover the can module from the bus-off state. the conditions under which the module can recover from the bus-off state are defined by the can protocol iso 11898, and it is necessary to detect 11 consecutive recessive-level bits 128 times. at this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. when the recovery conditions are satisfied (refer to timing <3> in figure 18-17 on page 547 ), the can module can enter the operation mode it has requested. until the can module enters this operation mode, it stays in the initialization mode. completion to be requested operation mode can be confirmed by reading the opmode bits of the cnctrl register. during the bus-off period and bus-off recovery sequence, the boff bit of the cninfo register stays set (to 1). in the bus-off recovery sequence, the reception error counter (rec[6:0]) counts the number of times 11 consecutive recessive-level bits have been detected on the bus. therefore, the recovery state can be checked by reading rec[6:0]. caution 1. in the bus-off recovery sequence, rec[6:0] counts up (+1) each time 11 consecutive recessive-level bits have been detected. even during the bus-off period, the can module can enter the can sleep mode or can stop mode. to start the bus-off recovery sequence, it is necessary to transit to the initialization mode once. however, when the can module is in either can sleep mode or can stop mode, transition request to the initialization mode is not accepted, thus you have to release the can sleep mode first. in this case, as soon as the can sleep mode is released, the bus-off recovery sequence starts and no transition to initialization mode is necessary. if the can module detects a dominant edge on the can bus while in sleep mode even during bus-off, the sleep mode will be left and the bus-off recovery sequence will start. 2. during the bus-off recovery sequence, when the request to change the mode from the initialization mode to an operation mode is generated to execute the buss-off recovery sequence again, the reception error counter (rec [6:0]) is cleared. in this case, it is required to detect 11 consecutive recessive-level bits 128 times again on the bus.
547 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-17 recovery from bus-off state through normal recovery sequence (b) forced recovery operation that skips bus-off recovery sequence the can module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. here is the procedure. first, the can module requests to enter the initialization mode. for the operation and points to be noted at this time, ?recovery from bus-off state through normal recovery sequence? on page 546 . next, the module requests to enter an operation mode. at the same time, the ccerc bit of the cnctrl register must be set to 1. as a result, the bus-off recovery sequence defined by the can protocol iso 11898 is skipped, and the module immediately enters the operation mode. in this case, the module is connected to the can bus after it has monitored 11 consecutive recessive-level bits. for details, refer to the processing in figure 18-54 on page 656 . caution this function is not defined by the can protocol iso 11898. when using this function, thoroughly evaluate its effect on the network system. ?error-passive? 00h 00h 00h 00h 80h tec[7:0] ffh boff bit in cninfo register opmode[2:0] in cnctrl register (user writings) opmode[2:0] in cnctrl register (user readings) tec[7:0] in cnerc register reps, rec[6:0] in cnerc register tec > ffh 00h 00h 00h ffh < tec [7:0] ?bus-off? ?bus-off-recovery-sequence? ?error-active? 00h tec[7:0] < 80h 00h reps, rec[6:0] < 80h 00h reps, rec[6:0] 80h <1> <2> <3> undefined
548 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (6) initializing can module error counter register (cnerc) in initialization mode if it is necessary to initialize the can module error counter register (cnerc) and can module information register (cninfo) for debugging or evaluating a program, they can be initialized to the default value by setting the ccerc bit of the cnctrl register in the initialization mode. when initialization has been completed, the ccerc bit is automatically cleared to 0. caution 1. this function is enabled only in the initialization mode. even if the ccerc bit is set to 1 in a can operation mode, the cnerc and cninfo registers are not initialized. 2. the ccerc bit can be set at the same time as the request to enter a can operation mode.
549 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.3.7 baud rate control function (1) prescaler the can controller has a prescaler that divides the clock (f can ) supplied to can. this prescaler generates a can protocol layer basic system clock (f tq ) derived from the can module system clock (f canmod ), and divided by 1 to 256 ( ?cnbrp - cann module bit rate prescaler register? on page 580 ). (2) data bit time (8 to 25 time quanta) one data bit time is defined as shown in figure 18-18 on page 549 . the can controller sets time segment 1, time segment 2, and resynchronization jump width (sjw) of data bit time, as shown in figure 18-18 . time segment 1 is equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the can protocol specification. time segment 2 is equivalent to phase segment 2. figure 18-18 segment setting table 18-15 segment setting note 1. ipt: information processing time 2. tq: time quanta reference: the can protocol specification defines the segments constituting the data bit time as shown in figure 18-19 . segment name settable range notes on setting to conform to can specification time segment 1 (tseg1) 2tq to 16tq - time segment 2 (tseg2) 1tq to 8tq ipt of the can controller is 0tq. to conform to the can protocol specification, therefore, a length less or equal to phase segment 1 must be set here. this means that the length of time segment 1 minus 1tq is the settable upper limit of time segment 2. resynchronization jump width (sjw) 1tq to 4tq the length of time segment 1 minus 1tq or 4 tq, whichever is smaller. data bit time(dbt) phase segment 1 prop segment sync segment phase segment 2 time segment 1(tseg1) time segment 2 (tseg2) sample point (spt)
550 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-19 configuration of data bit time defi ned by can specification table 18-16 configuration of data bi t time defined by can specification note ipt: information processing time segment name settable range notes on setting to conform to can specification sync segment (synchronization segment) 1 this segment starts at the edge where the level changes from recessive to dominant when hardware synchronization is established. prop segment programmable to 1 to 8 or more this segment absorbs the delay of the output buffer, can bus, and input buffer. the length of this segment is set so that ack is returned before the start of phase segment 1. time of prop segment (delay of output buffer) + 2 (delay of can bus) + (delay of input buffer) this segment compensates for an error of data bit time. the longer this segment, the wider the permissible range but the slower the communication speed. phase segment 1 programmable to 1 to 8 phase segment 2 phase segment 1 or ipt, whichever greater sjw programmable from 1tq to length of segment 1 or 4tq, whichever is smaller this width sets the upper limit of expansion or contraction of the phase segment during resynchronization. phase segment 1 prop segment s ync segment phase segment 2 s ample point ( s pt) s jw data bit time(dbt)
551 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (3) synchronizing data bit  the receiving node establishes synchronization by a level change on the bus because it does not have a sync signal.  the transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) hardware synchronization this synchronization is established when the receiving node detects the start of frame in the interframe space.  when a falling edge is detected on the bus, that tq means the sync segment and the next segment is the prop segment. in this case, synchronization is established regardless of sjw. figure 18-20 adjusting synchronization of data bit (b) resynchronization synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously).  the phase error of the edge is given by the relative position of the detected edge and sync segment. 0: if the edge is within the sync segment positive: if the edge is before the sample point (phase error) negative: if the edge is after the sample point (phase error) if phase error is positive: phase segment 1 is lengthened by specified sjw. if phase error is negative: phase segment 2 is shortened by specified sjw.  the sample point of the data of the receiving node moves relatively due to the ?discrepancy? in the baud rate between the transmitting node and receiving node. s tart of frame interframe space can bus bit timing phase segment 1 prop segment s ync segment phase segment 2
552 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-21 resynchronization 18.4 connection with target system the can module has to be connected to the can bus using an external transceiver. figure 18-22 connection to can bus can bus bit timing can bus bit timing phase segment 1 prop segment s ync segment phase segment 2 phase segment 1 prop segment s ync segment phase segment 2 s ample point s ample point if phase error is negative if phase error is positive can module transceiver ctxdn crxdn can l can h
553 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.5 internal registers of can controller 18.5.1 can module register and message buffer addresses in this chapter all register and message buffer addresses are defined as address offsets to different base addresses. since all registers are accessed via the programmable peripheral area the bottom address is defined by the bpc register (refer to ?programmable peripheral i/o area? on page 153 or to ?programmable peripheral i/o area (ppa)? on page 297 ). the addresses given in the following tables are offsets to the programmable peripheral area base address pba. the setting of bpc is fixed to 8ffb h . this setting defines the programmable peripheral area base address pba = 03fe c000 h table 18-17 lists all base addresses used throughout this chapter. in the following respectively are used for the base address names for can channel n. table 18-17 can module base addresses base address name base address of address address for bpc =8ffb h c0rbaseaddr can0 registers pba + 000 h 03fe c000 h c0mbaseaddr can0 message buffers pba + 100 h 03fe c100 h
554 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.5.2 can controller configuration table 18-18 list of can controller registers item register name can global registers cann global control register (cngmctrl) cann global clock selection register (cngmcs) cann global automatic block transmission control register (cngmabt) cann global automatic block transmission delay setting register (cngmabtd) can module registers cann module mask 1 register (cnmask1l, cnmask1h) cann module mask 2 register (cnmask2l, cnmask2h) cann module mask 3 register (cnmask3l, cnmask3h) cann module mask 4 registers (cnmask4l, cnmask4h) cann module control register (cnctrl) cann module last error information register (cnlec) cann module information register (cninfo) cann module error counter register (cnerc) cann module interrupt enable register (cnie) cann module interrupt status register (cnints) cann module bit rate prescaler register (cnbrp) cann module bit rate register (cnbtr) cann module last in-pointer register (cnlipt) cann module receive history list register (cnrgpt) cann module last out-pointer register (cnlopt) cann module transmit history list register (cntgpt) cann module time stamp register (cnts) message buffer registers cann message data byte 01 register m (cnmdata01m) cann message data byte 0 register m (cnmdata0m) cann message data byte 1 register m (cnmdata1m) cann message data byte 23 register m (cnmdata23m) cann message data byte 2 register m (cnmdata2m) cann message data byte 3 register m (cnmdata3m) cann message data byte 45 register m (cnmdata45m) cann message data byte 4 register m (cnmdata4m) cann message data byte 5 register m (cnmdata5m) cann message data byte 67 register m (cnmdata67m) cann message data byte 6 register m (cnmdata6m) cann message data byte 7 register m (cnmdata7m) cann message data length register m (cnmdlcm) cann message configuration register m (cnmconfm) cann message id register m (cnmidlm, cnmidhm) cann message control register m (cnmctrlm)
555 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.5.3 can registers overview (1) can0 module registers the following table lists the address offsets to the can0 register base address: c0rbaseaddr = pba table 18-19 can0 global and module registers address offset register name symbol r/w access after reset 1-bit 8-bit 16-bit 000 h can0 global control register c0gmctrl r/w 0000 h 002 h can0 global clock selection register c0gmcs 0f h 006 h can0 global automatic block transmission register c0gmabt 0000 h 008 h can0 global automatic block transmission delay register c0gmabtd 00 h 040 h can0 module mask 1 register c0mask1l undefined 042 h c0mask1h undefined 044 h can0 module mask 2 register c0mask2l undefined 046 h c0mask2h undefined 048 h can0 module mask 3 register c0mask3l undefined 04a h c0mask3h undefined 04c h can0 module mask 4 register c0mask4l undefined 04e h c0mask4h undefined 050 h can0 module control register c0ctrl 0000 h 052 h can0 module last error code register c0lec 00 h 053 h can0 module information register c0info r 00 h 054 h can0 module error counter register c0erc 0000 h 056 h can0 module interrupt enable register c0ie r/w 0000 h 058 h can0 module interrupt status register c0ints 0000 h 05a h can0 module bit-rate prescaler register c0brp ff h 05c h can0 module bit-rate register c0btr 370f h 05e h can0 module last in-pointer register c0lipt r undefined 060 h can0 module receive history list register c0rgpt r/w xx02 h 062 h can0 module last out-pointer register c0lopt r undefined 064 h can0 module transmit history list register c0tgpt r/w xx02 h 066 h can0 module time stamp register c0ts 0000 h
556 chapter 18 can controller (can) user?s manual u18743ee1v2um00 the addresses in the following table denote the address offsets to the can #n message buffer base address: cnmbaseaddr, with m being the message buffer number. example can0, message buffer m = 14 = e h , byte 6 c0mdata614 has the address e h x 20 h + 6 h + c0mbaseaddr note the message buffer register number m in the register symbols has 2 digits, for example, c0mdata01m = c0mdata0100 for m = 0. table 18-20 can0 message buffer registers address offset register name symbol r/w access after reset 1-bit 8-bit 16-bit mx20 h + 0 h can #n message data byte 01 register m cnmdata01m r/w undefined mx20 h + 0 h can #n message data byte 0 register m cnmdata0m undefined mx20 h + 1 h can #n message data byte 1 register m cnmdata1m undefined mx20 h + 2 h can #n message data byte 23 register m cnmdata23m undefined mx20 h + 2 h can #n message data byte 2 register m cnmdata2m undefined mx20 h + 3 h can #n message data byte 3 register m cnmdata3m undefined mx20 h + 4 h can #n message data byte 45 register m cnmdata45m undefined mx20 h + 4 h can #n message data byte 4 register m cnmdata4m undefined mx20 h + 5 h can #n message data byte 5 register m cnmdata5m undefined mx20 h + 6 h can #n message data byte 67 register m cnmdata67m undefined mx20 h + 6 h can #n message data byte 6 register m cnmdata6m undefined mx20 h + 7 h can #n message data byte 7 register m cnmdata7m undefined mx20 h + 8 h can #n message data length register m cnmdlcm 0000 xxxx b mx20 h + 9 h can #n message configuration register m cnmconfm undefined mx20 h + a h can #n message identifier register m cnmidlm undefined mx20 h + c h cnmidhm undefined mx20 h + e h can #n message control register m cnmctrlm 0x00 0000 0000 0000 b
557 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.5.4 register bit configuration table 18-21 can global register bit configuration address offset a a) base address: symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 00 h cngmctrl (w)0000000clear gom 01 h 000000set efsdset gom 00 h cngmctrl (r)000000efsdgom 01 h mbon000000 0 02 h cngmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 06 h cngmabt (w)0000000clear abttrg 07 h 000000set abtclr set abttrg 06 h cngmabt (r)000000abtclrabttrg 07 h 0000000 0 08 h cngmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0 table 18-22 can module register bit configuration (1/2) address offset a symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 40 h cnmask1l cmid7 to cmid0 41 h cmid15 to cmid8 42 h cnmask1h cmid23 to cmid16 43 h 0 0 0 cmid28 to cmid24 44 h cnmask2l cmid7 to cmid0 45 h cmid15 to cmid8 46 h cnmask2h cmid23 to cmid16 47 h 0 0 0 cmid28 to cmid24 48 h cnmask3l cmid7 to cmid0 49 h cmid15 to cmid8 4a h cnmask3h cmid23 to cmid16 4b h 0 0 0 cmid28 to cmid24 4c h cnmask4l cmid7 to cmid0 4d h cmid15 to cmid8 4e h cnmask4h cmid23 to cmid16 4f h 0 0 0 cmid28 to cmid24 50 h cnctrl (w) 0 clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 51 h set ccerc set al 0set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 50 h cnctrl (r) ccerc al valid ps mode1 ps mode0 op mode2 op mode1 op mode0 51 h 000 0 0 0rstattstat
558 chapter 18 can controller (can) user?s manual u18743ee1v2um00 52 h cnlec (w)00000000 52 h cnlec (r) 0 0 0 0 0 lec2 lec1 lec0 53 h cninfo 0 0 0 boff tecs1 tecs0 recs1 recs0 54 h cnerc tec7 to tec0 55 h reps rec6 to rec0 56 h cnie (w) 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 57 h 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 56 h cnie (r) 0 0 cie5 cie4 cie3 cie2 cie1 cie0 57 h 00000000 58 h cnints (w) 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 59 h 00000000 58 h cnints (r) 0 0 cints5 cints4 cints3 cints2 cints1 cints0 59 h 00000000 5a h cnbrp tqprs7 to tqprs0 5c h cnbtr 0 0 0 0 tseg13 to tseg10 5d h 0 0 sjw1, sjw0 0 tseg22 to tseg20 5e h cnlipt lipt7 to lipt0 60 h cnrgpt (w) 0 0 0 0 0 0 0 clear rovf 61 h 00000000 60 h cnrgpt (r) 0 0 0 0 0 0 rhpm rovf 61 h rgpt7 to rgpt0 f62 h cnlopt lopt7 to lopt0 64 h cntgpt (w)0000000clear tovf 65 h 00000000 64 h cntgpt (r) 0 0 0 0 0 0 thpm tovf 65 h tgpt7 to tgpt0 66 h cnts (w) 0 0 0 0 0 clear tslock clear tssel clear tsen 67 h 000 0 0set tslock set tssel set tsen 66 h cnts (r) 0 0 0 0 0 tslock tssel tsen 67 h 00000000 68 h to ff h - access prohibited (reserved for future use) a) base address: table 18-22 can module register bit configuration (2/2) address offset a symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8
559 can controller (can) chapter 18 user?s manual u18743ee1v2um00 note for calculation of the complete message buffer register addresses refer to ?can registers overview? on page 555 . table 18-23 message buffer register bit configuration address offset a a) base address: symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 0 h cnmdata01m message data (byte 0) 1 h message data (byte 1) 0 h cnmdata0m message data (byte 0) 1 h cnmdata1m message data (byte 1) 2 h cnmdata23m message data (byte 2) 3 h message data (byte 3) 2 h cnmdata2m message data (byte 2) 3 h cnmdata3m message data (byte 3) 4h cnmdata45m message data (byte 4) 5 h message data (byte 5) 4 h cnmdata4m message data (byte 4) 5 h cnmdata5m message data (byte 5) 6 h cnmdata67m message data (byte 6) 7 h message data (byte 7) 6 h cnmdata6m message data (byte 6) 7 h cnmdata7m message data (byte 7) 8 h cnmdlcm 0 mdlc3 mdlc2 mdlc1 mdlc0 9 h cnmconfm ows rtr mt2 mt1 mt0 0 0 ma0 a h cnmidlm id7 id6 id5 id4 id3 id2 id1 id0 b h id15 id14 id13 id12 id11 id10 id9 id8 c h cnmidhm id23 id22 id21 id20 id19 id18 id17 id16 d h ide 0 0 id28 id27 id26 id25 id24 e h cnmctrlm (w) 000clear mow clear ie clear dn clear trq clear rdy f h 0000set ie0set trqset rdy e h cnmctrlm (r) 0 0 0 mow ie dn trq rdy f h 00muc00000
560 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.6 bit set/clear function the can control registers include registers whose bits can be set or cleared via the cpu and via the can interface. an operation error occurs if the following registers are written directly. do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.  cann global control register (cngmctrl)  cann global automatic block transmission control register (cngmabt)  cann module control register (cnctrl)  cann module interrupt enable register (cnie)  cann module interrupt status register (cnints)  cann module receive history list register (cnrgpt)  cann module transmit history list register (cntgpt)  cann module time stamp register (cnts)  cann message control register (cnmctrlm) all the 16 bits in the above registers can be read via the usual method. use the procedure described in figure 18-23 below to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the bit status after set/clear operation is specified in figure 18-26 ). figure 18-23 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register.
561 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-23 example of bit setting/clearing operations (1) bit status after bit setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set no change clear bit status r egister?s current value write value register?s value after write operation clear clear no change no change set 1514131211109876543210 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set 0 ... 7 clear 0 ... 7 status of bit n after bit set/clear operation 0 0 no change 010 101 1 1 no change
562 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.7 control registers (1) cngmctrl - cann global control register the cngmctrl register is used to control the operation of the can module. access this register can be read/written in 16-bit units. address + 000 h initial value 0000 h . the register is initialized by any reset. (a) cngmctrl read caution 1. while the mbon bit is cleared (to 0), software access to the message buffers (cnmdata0m, cnmdata1m, cnmdata01m, cnmdata2m, cnmdata3m, cnmdata23m, cnmdata4m, cnmdata5m, cnmdata45m, cnmdata6m, cnmdata7m, cnmdata67m, cnmdlcm, cnmconfm, cnmidlm, cnmidhm, and cnmctrlm), or registers related to transmit history or receive history (cnlopt, cntgpt, cnlipt, and cnrgpt) is disabled. 2. this bit is read-only. even if 1 is written to the mbon bit while it is 0, the value of the mbon bit does not change, and access to the message buffer registers, or registers related to transmit history or receive history remains disabled. note the mbon bit is cleared (to 0) when the can module enters can sleep mode/ can stop mode, or when the gom bit is cleared (to 0). the mbon bit is set (to 1) when the can sleep mode/can stop mode is released, or when the gom bit is set (to 1). 15 14 13 12 11 10 9 8 mbon0000000 76543210 000000efsdgom mbon bit enabling access to message buffer register, transmit/receive history registers 0 write access and read access to the message buffer register and the transmit/receive history list registers is disabled. 1 write access and read access to the message buffer register and the transmit/receive history list registers is enabled. efsd bit enabling forced shut down 0 forced shut down by gom bit = 0 disabled. 1 forced shut down by gom bit = 0 enabled.
563 can controller (can) chapter 18 user?s manual u18743ee1v2um00 caution to request forced shut down, the gom bit must be cleared to 0 in a subsequent, immediately following access after the efsd bit has been set to 1. if access to another register (including reading the cngmctrl register) is executed without clearing the gom bit immediately after the efsd bit has been set to 1, the efsd bit is forcibly cleared to 0, and the forced shut down request is invalid. caution the gom can be cleared only in the initialization mode or immediately after efsd bit is set (to 1). (b) cngmctrl write caution set the gom bit and efsd bit always separately. gom global operation mode bit 0 can module is disabled from operating. 1 can module is enabled to operate. 15 14 13 12 11 10 9 8 000000 set efsd set gom 76543210 0000000 clear gom set efsd efsd bit setting 0 no change in efsd bit. 1 efsd bit set to 1. set gom clear gom gom bit setting 01 gom bit cleared to 0. 10 gom bit set to 1. other than above no change in gom bit.
564 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (2) cngmcs - cann global clock selection register the cngmcs register is used to select the can module system clock. access this register can be read/written in 8-bit units. address + 002 h initial value 0f h . the register is initialized by any reset. note f can = clock supplied to can 76543210 0 0 0 0 ccp3 ccp2 ccp1 ccp0 ccp3 ccp2 ccp1 ccp1 can module system clock (f canmod ) 0000f can /1 0001f can /2 0010f can /3 0011f can /4 0100f can /5 0101f can /6 0110f can /7 0111f can /8 1000f can /9 1001f can /10 1010f can /11 1011f can /12 1100f can /13 1101f can /14 1110f can /15 1111f can /16 (default value)
565 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (3) cngmabt - cann global automatic block transmission control register the cngmabt register is used to control the automatic block transmission (abt) operation. access this register can be read/written in 16-bit units. address + 006 h initial value 0000 h . the register is initialized by any reset. (a) cngmabt read note 1. set the abtclr bit to 1 while the abttrg bit is cleared to 0. the operation is not guaranteed if the abtclr bit is set to 1 while the abttrg bit is set to 1. 2. when the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared to 0 as soon as the requested clearing processing is complete. caution 1. do not set the abttrg bit (1) in the initialization mode. if the abttrg bit is set in the initialization mode, the operation is not guaranteed after the can module has entered the normal operation mode with abt. 2. do not set the abttrg bit (1) while the cnctrl.tstat bit is set (1). confirm tstat = 0 directly in advance before setting abttrg bit. 15 14 13 12 11 10 9 8 00000000 76543210 000000abtclrabttrg abtclr automatic block transmission engine clear status bit 0 clearing the automatic transmission engine is completed. 1 the automatic transmission engine is being cleared. abttrg automatic block transmission status bit 0 automatic block transmission is stopped. 1 automatic block transmission is under execution.
566 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (b) cngmabt write caution before changing the normal operation mode with abt to the initialization mode, be sure to set the cngmabt register to the default value (0000 h ) and confirm the cngmabt register is surely initialized to the default value (0000 h ). 15 14 13 12 11 10 9 8 000000 set abtclr set abttrg 76543210 0000000 clear abttrg set abtclr automatic block transmission engine clear request bit 0 the automatic block transmission engine is in idle status or under operation. 1 request to clear the automatic block transmission engine. after the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the abttrg bit to 1. set abttrg clear abttrg automatic block transmission start bit 0 1 request to stop automatic block transmission. 1 0 request to start automatic block transmission. other than above no change in abttrg bit.
567 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (4) cngmabtd - cann global automatic block transmission delay register the cngmabtd register is used to set the interval at which the data of the message buffer assigned to abt is to be transmitted in the normal operation mode with abt. access this register can be read/written in 8-bit units. address + 008 h initial value 00 h . the register is initialized by any reset. caution 1. do not change the contents of the cngmabtd register while the abttrg bit is set to 1. 2. the timing at which the abt message is actually transmitted onto the can bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an abt message (message buffers 8 to 31) is made. 76543210 0 0 0 0 abtd3 abtd2 abtd1 abtd0 abtd3 abtd2 abtd1 abtd0 data frame interval during automatic block transmission in dbt a a) unit: data bit time (dbt) 00000 dbt (default value) 00012 5 dbt 00102 6 dbt 00112 7 dbt 01002 8 dbt 01012 9 dbt 01102 10 dbt 01112 11 dbt 10002 12 dbt other than above setting prohibited
568 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (5) cnmaskal, cnmaskah - cann module mask control register (a = 1 to 4) the cnmaskal and cnmaskah registers are used to extend the number of receivable messages into the same message buffer by masking part of the identifier (id) comparison of a message and invalidating the id of the masked part. (a) cann module mask 1 register (cnmask1l, cnmask1h) access these registers can be read/written in 16-bit units. address cnmask1l: + 040 h cnmask1h: + 042 h initial value undefined. (b) cann module mask 2 register (cnmask2l, cnmask2h) access these registers can be read/written in 16-bit units. address cnmask2l: + 044 h cnmask2h: + 046 h initial value undefined. cnmask1l 15 14 13 12 11 10 9 8 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cnmask1h 15 14 13 12 11 10 9 8 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cnmask2l 15 14 13 12 11 10 9 8 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cnmask2h 15 14 13 12 11 10 9 8 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16
569 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (c) cann module mask 3 register (cnmask3l, cnmask3h) access these registers can be read/written in 16-bit units. address cnmask3l: + 048 h cnmask3h: + 04a h initial value undefined. (d) cann module mask 4 register (cnmask4l, cnmask4h) access these registers can be read/written in 16-bit units. address cnmask4l: + 04c h cnmask4h: + 04e h initial value undefined. note masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, the cmid17 to cmid0 bits are ignored. therefore, only the cmid28 to cmid18 bits of the received id are masked. the same mask can be used for both the standard and extended ids. cnmask3l 15 14 13 12 11 10 9 8 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cnmask3h 15 14 13 12 11 10 9 8 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cnmask4l 15 14 13 12 11 10 9 8 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 cnmask4h 15 14 13 12 11 10 9 8 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmid28 to cmid0 mask pattern setting of id bit 0 the id bits of the message buffer set by the cmid28 to cmid0 bits are compared with the id bits of the received message frame. 1 the id bits of the message buffer set by the cmid28 to cmid0 bits are not compared with the id bits of the received message frame (they are masked).
570 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (6) cnctrl - cann module control register the cnctrl register is used to control the operation mode of the can module. access this register can be read/written in 16-bit units. address + 050 h initial value 0000 h . the register is initialized by any reset. (a) cnctrl read note 1. the rstat bit is set to 1 under the following conditions (timing)  the sof bit of a receive frame is detected  on occurrence of arbitration loss during a transmit frame 2. the rstat bit is cleared to 0 under the following conditions (timing)  when a recessive level is detected at the second bit of the interframe space  on transition to the initialization mode at the first bit of the interframe space note 1. the tstat bit is set to 1 under the following conditions (timing)  the sof bit of a transmit frame is detected 2. the tstat bit is cleared to 0 under the following conditions (timing)  during transition to bus-off state  on occurrence of arbitration loss in transmit frame  on detection of recessive level at the second bit of the interframe space  on transition to the initialization mode at the first bit of the interframe space 15 14 13 12 11 10 9 8 000000rstattstat 76543210 ccerc al valid psmode1 psmode0 opmode2 opmode1 opmode0 rstat reception status bit 0 reception is stopped. 1 reception is in progress. tstat transmission status bit 0 transmission is stopped. 1 transmission is in progress.
571 can controller (can) chapter 18 user?s manual u18743ee1v2um00 note 1. the ccerc bit is used to clear the cnerc and cninfo registers for re-initialization or forced recovery from the bus-off state. this bit can be set to 1 only in the initialization mode. 2. when the cnerc and cninfo registers have been cleared, the ccerc bit is also cleared to 0 automatically. 3. the ccerc bit can be set to 1 at the same time as a request to change the initialization mode to an operation mode is made. 4. the ccerc bit is read-only in the can sleep mode or can stop mode. 5. the receive data may be corrupted in case of setting the ccerc bit to (1) immediately after entering the init mode from self-test mode. note the al bit is valid only in the single-shot mode. note 1. detection of a valid receive message frame is not dependent upon storage in the receive message buffer (data frame) or transmit message buffer (remote frame). 2. clear the valid bit (0) before changing the initialization mode to an operation mode. 3. if only two can nodes are connected to the can bus with one transmitting a message frame in the normal mode and the other in the receive-only mode, the valid bit is not set to 1 before the transmitting node enters the error passive state, because in receive-only mode no acknowledge is generated. 4. to clear the valid bit, set the clear valid bit to 1 first and confirm that the valid bit is cleared. if it is not cleared, perform clearing processing again. ccerc error counter clear bit 0 the cnerc and cninfo registers are not cleared in the initialization mode. 1 the cnerc and cninfo registers are cleared in the initialization mode. al bit to set operation in case of arbitration loss 0 re-transmission is not executed in case of an arbitration loss in the single-shot mode. 1 re-transmission is executed in case of an arbitration loss in the single-shot mode. valid valid receive message frame detection bit 0 a valid message frame has not been received since the valid bit was last cleared to 0. 1 a valid message frame has been received since the valid bit was last cleared to 0.
572 chapter 18 can controller (can) user?s manual u18743ee1v2um00 caution 1. transition to and from the can stop mode must be made via can sleep mode. a request for direct transition to and from the can stop mode is ignored. 2. the mbon flag of cngmctrl must be checked after releasing a power save mode, prior to access the message buffers again. 3. can sleep mode requests are kept pending, until cancelled by software or entered on appropriate bus condition (bus idle). software can check the actual status by reading psmode. caution transit to initialization mode or power saving modes may take some time. be sure to verify the success of mode change by reading the values, before proceeding. note the opmode0 to opmode2 bits are read-only in the can sleep mode or can stop mode. psmode1 psmode0 power save mode 0 0 no power save mode is selected. 0 1 can sleep mode 1 0 setting prohibited 1 1 can stop mode opmode2 opmode1 opmode0 operation mode 000 no operation mode is selected (can module is in the initialization mode). 0 0 1 normal operation mode 010 normal operation mode with automatic block transmission function (normal operation mode with abt) 0 1 1 receive-only mode 1 0 0 single-shot mode 101self-test mode other than above setting prohibited
573 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (b) cnctrl write 15 14 13 12 11 10 9 8 set ccerc set al 0 set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 76543210 0 clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 set ccerc setting of ccerc bit 1 ccerc bit is set to 1. other than above ccerc bit is not changed. set al clear al setting of al bit 0 1 al bit is cleared to 0. 1 0 al bit is set to 1. other than above al bit is not changed. clear valid setting of valid bit 0 valid bit is not changed. 1 valid bit is cleared to 0. set psmode0 clear psmode0 setting of psmode0 bit 0 1 psmode0 bit is cleared to 0. 1 0 psmode0 bit is set to 1. other than above psmode0 bit is not changed. set psmode1 clear psmode1 setting of psmode1 bit 0 1 psmode1 bit is cleared to 0. 1 0 psmode1 bit is set to 1. other than above psmode1 bit is not changed. set opmode0 clear opmode0 setting of opmode0 bit 0 1 opmode0 bit is cleared to 0. 1 0 opmode0 bit is set to 1. other than above opmode0 bit is not changed.
574 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (7) cnlec - cann module last error information register the cnlec register provides the error information of the can protocol. access this register can be read/written in 8-bit units. address + 052 h initial value 00 h . the register is initialized by any reset. note 1. the contents of the cnlec register are not cleared when the can module changes from an operation mode to the initialization mode. 2. if an attempt is made to write a value other than 00 h to the cnlec register by software, the access is ignored. set opmode1 clear opmode1 setting of opmode1 bit 0 1 opmode1 bit is cleared to 0. 1 0 opmode1 bit is set to 1. other than above opmode1 bit is not changed. set opmode2 clear opmode2 setting of opmode2 bit 0 1 opmode2 bit is cleared to 0. 1 0 opmode2 bit is set to 1. other than above opmode2 bit is not changed. 76543210 0 0 0 0 0 lec2 lec1 lec0 lec2 lec1 lec0 last can protocol error information 000no error 001stuff error 010form error 011ack error 100 bit error. (the can module tried to transmit a recessive-level bit as part of a transmit message (except the arbitration field), but the value on the can bus is a dominant-level bit.) 101 bit error. (the can module tried to transmit a dominant-level bit as part of a transmit message, ack bit, error frame, or overload frame, but the value on the can bus is a recessive-level bit.) 1 1 0 crc error 111undefined
575 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (8) cninfo - cann module information register the cninfo register indicates the status of the can module. access this register is read-only in 8-bit units. address + 053 h initial value 00 h . the register is initialized by any reset. 76543210 0 0 0 boff tecs1 tecs0 recs1 recs0 boff bus-off state bit 0 not bus-off state (transmit error counter 255). (the value of the transmit error counter is less than 256.) 1 bus-off state (transmit error counter > 255). (the value of the transmit error counter is 256 or more.) tecs1 tecs0 transmission error counter status bit 00 the value of the transmission error counter is less than that of the warning level (< 96). 01 the value of the transmission error counter is in the range of the warning level (96 to 127). 1 0 undefined 11 the value of the transmission error counter is in the range of the error passive or bus-off status ( 128). recs1 recs0 reception error counter status bit 00 the value of the reception error counter is less than that of the warning level (< 96). 01 the value of the reception error counter is in the range of the warning level (96 to 127). 1 0 undefined 11 the value of the reception error counter is in the error passive range ( 128).
576 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (9) cnerc - cann module error counter register the cnerc register indicates the count value of the transmission/reception error counter. access this register is read-only in 16-bit units. address + 054 h initial value 0000 h . the register is initialized by any reset. note rec6 to rec0 of the reception error counter are invalid in the reception error passive state (cninfo.recs[1:0] = 11 b ). note the tec7 to tec0 bits of the transmission error counter are invalid in the bus-off state (cninfo.boff = 1). 15 14 13 12 11 10 9 8 reps rec6 rec5 rec4 rec3 rec2 rec1 rec0 76543210 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 reps reception error passive status bit 0 the reception error counter is not in the error passive range (< 128) 1 the reception error counter is in the error passive range ( 128) rec6 to rec0 reception error counter bit 0 to 127 number of reception errors. these bits reflect the status of the reception error counter. the number of errors is defined by the can protocol. tec7 to tec0 transmission error counter bit 0 to 255 number of transmission errors. these bits reflect the status of the transmission error counter. the number of errors is defined by the can protocol.
577 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (10) cnie - cann module interrupt enable register the cnie register is used to enable or disable the interrupts of the can module. access this register can be read/written in 16-bit units. address + 056 h initial value 0000 h . the register is initialized by any reset. (a) cnie read (b) cnie write 15 14 13 12 11 10 9 8 00000000 76543210 0 0 cie5 cie4 cie3 cie2 cie1 cie0 cie5 to cie0 can module interrupt enable bit 0 output of the interrupt corresponding to interrupt status register cintsx is disabled. 1 output of the interrupt corresponding to interrupt status register cintsx is enabled. 15 14 13 12 11 10 9 8 00 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 76543210 00 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 set cie5 clear cie5 setting of cie5 bit 0 1 cie5 bit is cleared to 0. 1 0 cie5 bit is set to 1. other than above cie5 bit is not changed. set cie4 clear cie4 setting of cie4 bit 0 1 cie4 bit is cleared to 0. 1 0 cie4 bit is set to 1. other than above cie4 bit is not changed. set cie3 clear cie3 setting of cie3 bit 0 1 cie3 bit is cleared to 0. 1 0 cie3 bit is set to 1. other than above cie3 bit is not changed.
578 chapter 18 can controller (can) user?s manual u18743ee1v2um00 set cie2 clear cie2 setting of cie2 bit 0 1 cie2 bit is cleared to 0. 1 0 cie2 bit is set to 1. other than above cie2 bit is not changed. set cie1 clear cie1 setting of cie1 bit 0 1 cie1 bit is cleared to 0. 1 0 cie1 bit is set to 1. other than above cie1 bit is not changed. set cie0 clear cie0 setting of cie0 bit 0 1 cie0 bit is cleared to 0. 1 0 cie0 bit is set to 1. other than above cie0 bit is not changed.
579 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (11) cnints - cann module interrupt status register the cnints register indicates the interrupt status of the can module. access this register can be read/written in 16-bit units. address + 058 h initial value 0000 h . the register is initialized by any reset. (a) cnints read (b) cnints write caution please clear the status bit of this register with software when the confirmation of each status is necessary in the interrupt processing, because these bits are not cleared automatically. 15 14 13 12 11 10 9 8 00000000 76543210 0 0 cints5 cints4 cints3 cints2 cints1 cints0 cints5 to cints0 can interrupt status bit 0 no related interrupt source event is pending. 1 a related interrupt source event is pending. interrupt status bit related interrupt source event cints5 wakeup interrupt from can sleep mode a a) the cints5 bit is set only when the can module is woken up from the can sleep mode by a can bus operation. the cints5 bit is not set when the can sleep mode has been released by software. cints4 arbitration loss interrupt cints3 can protocol error interrupt cints2 can error status interrupt cints1 interrupt on completion of reception of valid message frame to message buffer m cints0 interrupt on normal completion of transmission of message frame from message buffer m 15 14 13 12 11 10 9 8 00000000 76543210 00 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 clear cints5 to cints0 setting of cints5 to cints0 bits 0 cints5 to cints0 bits are not changed. 1 cints5 to cints0 bits are cleared to 0.
580 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (12) cnbrp - cann module bit rate prescaler register the cnbrp register is used to select the can protocol layer basic system clock (f tq ). the communication baud rate is set to the cnbtr register. access this register can be read/written in 8-bit units. address + 05a h initial value ff h . the register is initialized by any reset. figure 18-24 can module clock note f can : clock supplied to can f canmod : can module system clock f tq : can protocol layer basic system clock caution the cnbrp register can be write-accessed only in the initialization mode. 76543210 tqprs7 tqprs6 tqprs5 tqprs4 tqprs3 tqprs2 tqprs1 tqprs0 tqprs7 to tqprs0 can protocol layer base system clock (f tq ) 0f canmod /1 1f canmod /2 nf canmod /(n+1) : : 255 f canmod /256 (default value) ccp 3 ccp2 prescaler cann module bit-rate prescaler register (cnbrp) cann module clock selection register (cngmcs) baud rate generator cann bit-rate register (cnbtr) ccp1 ccp0 tqprs 0 f can f canmod f tq 0 0 0 0 tqprs1 tqprs2 tqprs3 tqprs4 tqprs5 tqprs6 tqprs7
581 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (13) cnbtr - cann module bit rate register the cnbtr register is used to control the data bit time of the communication baud rate. access this register can be read/written in 16-bit units. address + 05c h initial value 370f h . the register is initialized by any reset. figure 18-25 data bit time 15 14 13 12 11 10 9 8 0 0 sjw1 sjw0 0 tseg22 tseg21 tseg20 76543210 0 0 0 0 tseg13 tseg12 tseg11 tseg10 data bit time (dbt) time segment 1 (tseg1) phase segment 2 phase segment 1 sample point (spt) prop segment sync segment time segment 2 (tseg2) sjw1 sjw0 length of synchronization jump width 001t q 012t q 103t q 114t q (default value) tseg22 tseg21 tseg20 length of time segment 2 0001t q 0012t q 0103t q 0114t q 1005t q 1016t q 1107t q 1118t q (default value)
582 chapter 18 can controller (can) user?s manual u18743ee1v2um00 note t q = 1/f tq (f tq : can protocol layer basic system clock) (14) cnlipt - cann module last in-pointer register the cnlipt register indicates the number of the message buffer in which a data frame or a remote frame was last stored. access this register is read-only in 8-bit units. address + 05e h initial value undefined. note the read value of the cnlipt register is undefined if a data frame or a remote frame has never been stored in the message buffer. if the rhpm bit of the cnrgpt register is set to 1 after the can module has changed from the initialization mode to an operation mode, therefore, the read value of the cnlipt register is undefined. tseg13 tseg12 tseg11 tseg10 length of time segment 1 0 0 0 0 setting prohibited 00012t q a a) this setting must not be made when the cnbrp register = 00 h 00103t q a 00114t q 01005t q 01016t q 01107t q 01118t q 10009t q 100110t q 101011t q 101112t q 110013t q 110114t q 111015t q 111116t q (default value) 76543210 lipt7 lipt6 lipt5 lipt4 lipt3 lipt2 lipt1 lipt0 lipt7 to lipt0 last in-pointer register (cnlipt) 0 to 31 when the cnlipt register is read, the contents of the element indexed by the last in-pointer (lipt) of the receive history list are read. these contents indicate the number of the message buffer in which a data frame or a remote frame was last stored.
583 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (15) cnrgpt - cann module receive history list register the cnrgpt register is used to read the receive history list. access this register can be read/written in 16-bit units. address + 060 h initial value xx02 h . the register is initialized by any reset. (a) cnrgpt read 15 14 13 12 11 10 9 8 rgpt7 rgpt6 rgpt5 rgpt4 rgpt3 rgpt2 rgpt1 rgpt0 76543210 000000rhpmrovf rgpt7 to rgpt0 receive history list read pointer 0 to 31 when the cnrgpt register is read, the contents of the element indexed by the receive history list get pointer (rgpt) of the receive history list are read. these contents indicate the number of the message buffer in which a data frame or a remote frame has been stored. rhpm a a) the read value of the rgpt0 to rgpt7 bits is invalid when the rhpm bit = 1. receive history list pointer match 0 the receive history list has at least one message buffer number that has not been read. 1 the receive history list has no message buffer numbers that have not been read. rovf a a) if rovf is set, rhpm is no longer cleared on message storage, but rhpm is still set, if all entries of cnrgpt are read by software. receive history list overflow bit 0 all the message buffer numbers that have not been read are preserved. all the numbers of the message buffers in which a new data frame or remote frame has been received and stored are recorded to the receive history list (the receive history list has a vacant element). 1 at least 23 entries have been stored since the host processor has serviced the rhl last time (i.e. read cnrgpt). the first 22 entries are sequentially stored while the last entry can have been overwritten whenever newly received message is stored because all buffer numbers are stored at position lipt-1 when rovf bit is set. thus the sequence of receptions can not be recovered completely now.
584 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (b) cnrgpt write (16) cnlopt - cann module last out-pointer register the cnlopt register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. access this register is read-only in 8-bit units. address + 062 h initial value undefined note the value read from the cnlopt register is undefined if a data frame or remote frame has never been transmitted from a message buffer. if the cntgpt.thpm bit is set to 1 after the can module has changed from the initialization mode to an operation mode, therefore, the read value of the cnlopt register is undefined. 15 14 13 12 11 10 9 8 00000000 76543210 0000000 clear rovf clear rovf setting of rovf bit 0 rovf bit is not changed. 1 rovf bit is cleared to 0. 76543210 lopt7 lopt6 lopt5 lopt4 lopt3 lopt2 lopt1 lopt0 lopt7 to lopt0 last out-pointer of transmit history list (lopt) 0 to 31 when the cnlopt register is read, the contents of the element indexed by the last out-pointer (lopt) of the receive history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last.
585 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (17) cntgpt - cann module transmit history list register the cntgpt register is used to read the transmit history list. access this register can be read/written in 16-bit units. address + 064 h initial value xx02 h . the register is initialized by any reset. (a) cntgpt read note transmission from message buffers 0 to 7 is not recorded to the transmit history list in the normal operation mode with abt. 15 14 13 12 11 10 9 8 tgpt7 tgpt6 tgpt5 tgpt4 tgpt3 tgpt2 tgpt1 tgpt0 76543210 000000thpmtovf tgpt7 to tgpt0 transmit history list read pointer 0 to 31 when the cntgpt register is read, the contents of the element indexed by the read pointer (tgpt) of the transmit history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. thpm a a) the read value of the tgpt0 to tgpt7 bits is invalid when the thpm bit = 1. transmit history pointer match 0 the transmit history list has at least one message buffer number that has not been read. 1 the transmit history list has no message buffer numbers that have not been read. tovf a a) if tovf is set, thpm is no longer cleared on message transmission, but thpm is still set, if all entries of cntgpt are read by software. transmit history list overflow bit 0 all the message buffer numbers that have not been read are preserved. all the numbers of the message buffers to which a new data frame or remote frame has been transmitted are recorded to the transmit history list (the transmit history list has a vacant element). 1 at least 7 entries have been stored since the host processor has serviced the thl last time (i.e. read cntgpt). the first 6 entries are sequentially stored while the last entry can have been overwritten whenever a message is newly transmitted because all buffer numbers are stored at position lopt-1 when tovf bit is set. thus the sequence of transmissions can not be recovered completely now.
586 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (b) cntgpt write 15 14 13 12 11 10 9 8 00000000 76543210 0000000 clear tovf clear tovf setting of tovf bit 0 tovf bit is not changed. 1 tovf bit is cleared to 0.
587 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (18) cnts - cann module time stamp register the cnts register is used to control the time stamp function. access this register can be read/written in 16-bit units. address + 066 h initial value 0000 h . the register is initialized by any reset. (a) cnts read note the lock function of the time stamp function must not be used when the can module is in the normal operation mode with abt. remark the tsout signal is output from the can controller to the timer. for details, refer to chapter 10 on page 305 ." 15 14 13 12 11 10 9 8 00000000 76543210 0 0 0 0 0 tslock tssel tsen tslock time stamp lock function enable bit 0 time stamp lock function stopped. the tsout signal is toggled each time the selected time stamp capture event occurs. 1 time stamp lock function enabled. the tsout signal is toggled each time the selected time stamp capture event occurs. however, the tsout output signal is locked when a data frame has been correctly received to message buffer 0 a . a) the tsen bit is automatically cleared to 0. tssel time stamp capture event selection bit 0 the time capture event is sof. 1 the time stamp capture event is the last bit of eof. tsen tsout operation setting bit 0 tsout toggle operation is disabled. 1 tsout toggle operation is enabled.
588 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (b) cnts write 15 14 13 12 11 10 9 8 00000 set tslock set tssel set tsen 76543210 00000 clear tslock clear tssel clear tsen set tslock clear tslock setting of tslock bit 0 1 tslock bit is cleared to 0. 1 0 tslock bit is set to 1. other than above tslock bit is not changed. set tssel clear tssel setting of tssel bit 0 1 tssel bit is cleared to 0. 1 0 tssel bit is set to 1. other than above tssel bit is not changed. set tsen clear tsen setting of tsen bit 0 1 tsen bit is cleared to 0. 1 0 tsen bit is set to 1. other than above tsen bit is not changed.
589 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (19) cnmdataxm, cnmdatazm - cann message data byte register (x = 0 to 7, z = 01, 23, 45, 67) the cnmdataxm, cnmdatazm registers are used to store the data of a transmit/receive message. access the cnmdatazm registers can be read/written in 16-bit units. the cnmdataxm registers can be read/written in 8-bit units. address refer to ?can registers overview? on page 555. initial value undefined. cnmdata01m 15 14 13 12 11 10 9 8 mdata0115 mdata0114 mdata0113 mdata0112 mdata0111 mdata0110 mdata019 mdata018 76543210 m data 0 1 7 m data 0 1 6 m data 0 1 5 m data 0 1 4 m data 0 1 3 m data 0 1 2 m data 0 1 1 m data 0 1 0 cnmdata0m 76543210 m data 0 7 m data 0 6 m data 0 5 m data 0 4 m data 0 3 m data 0 2 m data 0 1 m data 0 0 cnmdata1m 76543210 m data 1 7 m data 1 6 m data 1 5 m data 1 4 m data 1 3 m data 1 2 m data 1 1 m data 1 cnmdata23m 15 14 13 12 11 10 9 8 mdata2315 mdata2314 mdata2313 mdata2312 mdata2311 mdata2310 mdata239 mdata238 76543210 m data 2 3 7 m data 2 3 6 m data 2 3 5 m data 2 3 4 m data 2 3 3 m data 2 3 2 m data 2 3 1 m data 2 3 0 cnmdata2m 76543210 m data 2 7 m data 2 6 m data 2 5 m data 2 4 m data 2 3 m data 2 2 m data 2 1 m data 2 0 cnmdata3m 76543210 m data 3 7 m data 3 6 m data 3 5 m data 3 4 m data 3 3 m data 3 2 m data 3 1 m data 3 0
590 chapter 18 can controller (can) user?s manual u18743ee1v2um00 cnmdata45m 15 14 13 12 11 10 9 8 mdata4515 mdata4514 mdata4513 mdata4512 mdata4511 mdata4510 mdata459 mdata458 76543210 m data 4 5 7 m data 4 5 6 m data 4 5 5 m data 4 5 4 m data 4 5 3 m data 4 5 2 m data 4 5 1 m data 4 5 0 cnmdata4m 76543210 m data 4 7 m data 4 6 m data 4 5 m data 4 4 m data 4 3 m data 4 2 m data 4 1 m data 4 0 cnmdata5m 76543210 m data 5 7 m data 5 6 m data 5 5 m data 5 4 m data 5 3 m data 5 2 m data 5 1 m data 5 0 cnmdata67m 15 14 13 12 11 10 9 8 mdata6715 mdata6714 mdata6713 mdata6712 mdata6711 mdata6710 mdata679 mdata678 76543210 m data 6 7 7 m data 6 7 6 m data 6 7 5 m data 6 7 4 m data 6 7 3 m data 6 7 2 m data 6 7 1 m data 6 7 0 cnmdata6m 76543210 m data 6 7 m data 6 6 m data 6 5 m data 6 4 m data 6 3 m data 6 2 m data 6 1 m data 6 0 cnmdata7m 76543210 m data 7 7 m data 7 6 m data 7 5 m data 7 4 m data 7 3 m data 7 2 m data 7 1 m data 7 0
591 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (20) cnmdlcm - cann message data length register m the cnmdlcm register is used to set the number of bytes of the data field of a message buffer. access this register can be read/written in 8-bit units. address refer to ?can registers overview? on page 555. initial value 0000xxxx b . the register is initialized by any reset. note the data and dlc value actually transmitted to can bus are as follows. caution 1. be sure to set bits 7 to 4 to 0000 b . 2. receive data is stored in as many cnmdataxm register as the number of bytes (however, the upper limit is 8) corresponding to dlc of the received frame. the cnmdataxm register in which no data is stored is undefined. 76543210 0 0 0 0 mdlc3 mdlc2 mdlc1 mdlc0 mdlc3 mdlc2 mdlc1 mdlc0 data length of transmit/receive message 00000 bytes 00011 byte 00102 bytes 00113 bytes 01004 bytes 01015 bytes 01106 bytes 01117 bytes 10008 bytes 1001setting prohibited (if these bits are set during transmission, 8-byte data is transmitted regardless of the set dlc value when a data frame is transmitted. however, the dlc actually transmitted to the can bus is the dlc value set to this register.) note 1010 1011 1100 1101 1110 1111 type of transmit frame length of transmit data dlc transmitted data frame number of bytes specified by dlc (however, 8 bytes if dlc 8) mdlc3 to mdlc0 bits remote frame 0 bytes
592 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (21) cnmconfm - cann message configuration register m the cnmconfm register is used to specify the type of the message buffer and to set a mask. access this register can be read/written in 8-bit units. address refer to ?can registers overview? on page 555. initial value undefined. note a remote frame is received and stored, regardless of the setting of ows and dn. a remote frame that satisfies the other conditions (id matches, rtr = 0, trq = 0) is always received and stored in the corresponding message buffer (interrupt generated, dn flag set, mdlc[3:0] updated, and recorded to the receive history list). 76543210 ows rtr mt2 mt1 mt0 0 0 ma0 ows overwrite control bit 0 the message buffer that has already received a data frame a is not overwritten by a newly received data frame. the newly received data frame is discarded. a) the ?message buffer that has already received a data frame? is a receive message buffer whose the cnmctrlm.dn bit has been set to 1. 1 the message buffer that has already received a data frame a is overwritten by a newly received data frame. rtr remote frame request bit a a) the rtr bit specifies the type of message frame that is transmitted from a mes- sage buffer defined as a transmit message buffer. even if a valid remote frame has been received, the rtr bit of the transmit message buffer that has received the frame remains cleared to 0. even if a remote frame whose id matches has been received from the can bus with the rtr bit of the transmit message buffer set to 1 to transmit a remote frame, that remote frame is not received or stored (interrupt generated, dn flag set, the mdlc0 to mdlc3 bits updated, and recorded to the receive history list). 0 transmit a data frame. 1 transmit a remote frame. mt2 mt1 mt0 message buffer type setting bit 0 0 0 transmit message buffer 0 0 1 receive message buffer (no mask setting) 0 1 0 receive message buffer (mask 1 set) 0 1 1 receive message buffer (mask 2 set) 1 0 0 receive message buffer (mask 3 set) 1 0 1 receive message buffer (mask 4 set) other than above setting prohibited
593 can controller (can) chapter 18 user?s manual u18743ee1v2um00 caution be sure to write 0 to bits 2 and 1. ma0 message buffer assignment bit 0 message buffer not used. 1 message buffer used.
594 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (22) cnmidlm, cnmidhm - cann message id register m the cnmidlm and cnmidhm registers are used to set an identifier (id). access these registers can be read/written in 16-bit units. address refer to ?can registers overview? on page 555. initial value undefined. caution 1. be sure to write 0 to bits 14 and 13 of the cnmidhm register. 2. be sure to align the id value according to the given bit positions into this registers. note that for standard id, the id value must be shifted to fit into id28 to id18 bit positions. cnmidlm 15 14 13 12 11 10 9 8 id15 id14 id13 id12 id11 id10 id9 id8 76543210 id7 id6 id5 id4 id3 id2 id1 id0 cnmidhm 15 14 13 12 11 10 9 8 ide 0 0 id28 id27 id26 id25 id24 76543210 id23 id22 id21 id20 id19 id18 id17 id16 ide format mode specification bit 0 standard format mode (id28 to id18: 11 bits) a a) the id17 to id0 bits are not used. 1 extended format mode (id28 to id0: 29 bits) id28 to id0 message id id28 to id18 standard id value of 11 bits (when ide = 0) id28 to id0 extended id value of 29 bits (when ide = 1)
595 can controller (can) chapter 18 user?s manual u18743ee1v2um00 (23) cnmctrlm - cann message control register m the cnmctrlm register is used to control the operation of the message buffer. access this register can be read/written in 16-bit units. address refer to ?can registers overview? on page 555. initial value 00x0 0000 0000 0000 b . the register is initialized by any reset. (a) cnmctrlm read 15 14 13 12 11 10 9 8 00muc00000 76543210 000mowiedntrqrdy muc a a) the muc bit is undefined until the first reception and storage is performed. bit indicating that message buffer data is being updated 0 the can module is not updating the message buffer (reception and storage). 1 the can module is updating the message buffer (reception and storage). mow a a) the mow bit is not set to 1 even if a remote frame is received and stored in the transmit message buffer with the dn bit = 1. message buffer overwrite status bit 0 the message buffer is not overwritten by a newly received data frame. 1 the message buffer is overwritten by a newly received data frame. ie message buffer interrupt request enable bit 0 receive message buffer: valid message reception completion interrupt disabled. transmit message buffer: normal message transmission completion interrupt disabled. 1 receive message buffer: valid message reception completion interrupt enabled. transmit message buffer: normal message transmission completion interrupt enabled. dn message buffer data update bit 0 a data frame or remote frame is not stored in the message buffer. 1 a data frame or remote frame is stored in the message buffer.
596 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (b) cnmctrlm write trq message buffer transmission request bit 0 no message frame transmitting request that is pending or being transmitted is in the message buffer. 1 the message buffer is holding transmission of a message frame pending or is transmitting a message frame. rdy message buffer ready bit 0 the message buffer can be written by software. the can module cannot write to the message buffer. 1 writing the message buffer by software is ignored (except a write access to the rdy, trq, dn, and mow bits). the can module can write to the message buffer. 15 14 13 12 11 10 9 8 0000 set ie 0 set trq set rdy 76543210 000 clear mow clear ie clear dn clear trq clear rdy clear mow setting of mow bit 0 mow bit is not changed. 1 mow bit is cleared to 0. set ie clear ie setting of ie bit 0 1 ie bit is cleared to 0. 1 0 ie bit is set to 1. other than above ie bit is not changed. clear dn setting of dn bit 1 dn bit is cleared to 0. 0 dn bit is not changed. set trq clear trq setting of trq bit 0 1 trq bit is cleared to 0. 1 0 trq bit is set to 1. other than above trq bit is not changed.
597 can controller (can) chapter 18 user?s manual u18743ee1v2um00 caution 1. set ie bit and rdy bit always separately. 2. do not set the dn bit to 1 by software. be sure to write 0 to bit 10. 3. do not set the trq bit and the rdy bit (1) at the same time. set the rdy bit (1) before setting the trq bit. 4. do not clear the rdy bit (0) during message transmission. follow the transmission abort process about clearing the rdy bit (0) for redefinition of the message buffer. 5. clear again when rdy bit is not cleared even if this bit is cleared. 6. be sure that rdy is cleared before writing to the other message buffer registers, by checking the status of the rdy bit. set rdy clear rdy setting of rdy bit 0 1 rdy bit is cleared to 0. 1 0 rdy bit is set to 1. other than above rdy bit is not changed.
598 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.8 can controller initialization 18.8.1 initialization of can module before can module operation is enabled, the can module system clock needs to be determined by setting the ccp[3:0] bits of the cngmcs register by software. do not change the setting of the can module system clock after can module operation is enabled. the can module is enabled by setting the gom bit of the cngmctrl register. for the procedure of initializing the can module, refer to ?operation of can controller? on page 637 . 18.8.2 initialization of message buffer after the can module is enabled, the message buffers contain undefined values. a minimum initialization for all the message buffers, even for those not used in the application, is necessary before switching the can module from the initialization mode to one of the operation modes.  clear the rdy, trq, and dn bits of all cnmctrlm registers to 0.  clear the ma0 bit of all cnmconfm registers to 0. 18.8.3 redefinition of message buffer redefining a message buffer means changing the id and control information of the message buffer while a message is being received or transmitted, without affecting other transmission/reception operations. (1) to redefine message buffer in initialization mode place the can module in the initialization mode once and then change the id and control information of the message buffer in the initialization mode. after changing the id and control information, set the can module to an operation mode. (2) to redefine message buffer during reception perform redefinition as shown in figure 18-38 . (3) to redefine message buffer during transmission to rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (see ?transmission abort process except for in normal operation mode with automatic block transmission (abt)? on page 616 and ?transmission abort process except for abt transmission in normal operation mode with automatic block transmission (abt)? on page 616 ). confirm that transmission has been aborted or completed, and then redefine the message buffer. after redefining
599 can controller (can) chapter 18 user?s manual u18743ee1v2um00 the transmit message buffer, set a transmission request using the procedure described below. when setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. figure 18-26 setting transmission request (trq) to transmit message buffer after redefinition caution 1. when a message is received, reception filtering is performed in accordance with the id and mask set to each receive message buffer. if the procedure in figure 18-38 on page 640 is not observed, the contents of the message buffer after it has been redefined may contradict the result of reception (result of reception filtering). if this happens, check that the id and ide received first and stored in the message buffer following redefinition are those stored after the message buffer has been redefined. if no id and ide are stored after redefinition, redefine the message buffer again. 2. when a message is transmitted, the transmission priority is checked in accordance with the id, ide, and rtr bits set to each transmit message buffer to which a transmission request was set. the transmit message buffer having the highest priority is selected for transmission. if the procedure in figure 18-26 on page 599 is not observed, a message with an id not having the highest priority may be transmitted after redefinition. execute transmission? wait for 1 bit of can data. s et trq bit s et trq bit = 1 clear trq bit = 0 ye s no redefinition completed end
600 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.8.4 transition from initializ ation mode to operation mode the can module can be switched to the following operation modes.  normal operation mode  normal operation mode with abt  receive-only mode  single-shot mode  self-test mode figure 18-27 transition to operation modes the transition from the initialization mode to an operation mode is controlled by the bit string opmode[2:0] in the cnctrl register. changing from one operation mode into another requires shifting to the initialization mode in between. do not change one operation mode to another directly; otherwise the operation will not be guaranteed. requests for transition from an operation mode to the initialization mode are held pending when the can bus is not in the interframe space (i.e., frame reception or transmission is in progress), and the can module enters the initialization mode at the first bit in the interframe space (the values of the opmode[2:0] bits are changed to 000 b ) . after issuing a request to change the mode to the initialization mode, read the opmode[2:0] bits until their value becomes 000 b to confirm that the module has entered the initialization mode (see figure 18-36 on page 638 ). can module channel invalid [receive-only mode] opmode[2:0]=03h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 03h [single-shot mode] opmode[2:0]=04h opmode[2:0] = 04h opmode[2:0] = 05h init mode opmode[2:0] = 00h efsd = 1 and gom = 0 all can modules are in init mode and gom = 0 gom = 1 reset reset released [normal operation mode with abt] opmode[2:0]=02h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 02h opmode[2:0] = 01h opmode[2:0] = 00h and can bus is busy. [normal operation mode] opmode[2:0]=01h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and can bus is busy. [self-test mode] opmode[2:0]=05h
601 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.8.5 resetting error counter cnerc of can module if it is necessary to reset the can module error counter cnerc and can module information register cninfo when re-initialization or forced recovery from the bus-off status is made, set the ccerc bit of the cnctrl register to 1 in the initialization mode. when this bit is set to 1, the cnerc and cninfo registers are cleared to their default values.
602 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.9 message reception 18.9.1 message reception in all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. all message buffers satisfying the following conditions are included in that evaluation (rx-search process).  used as a message buffer (ma0 bit of cnmconfm register set to 1.)  set as a receive message buffer (mt[2:0] bits of cnmconfm register are set to 001 b , 010 b , 011 b , 100 b , or 101 b .)  ready for reception (rdy bit of cnmctrlm register is set to 1.) when two or more message buffers of the can module receive a message, the message is stored according to the priority explained below. the message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. for example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same id, the received message is not stored in the message buffer linked to mask 1, even if that message buffer has not received a message and a message has already been received in the unmasked receive message buffer. in other words, when a condition has been set in two or more message buffers with different priorities, the message buffer with the highest priority always stores the message; the message is not stored in message buffers with a lower priority. this also applies when the message buffer with the highest priority is unable to store a message (i.e., when dn = 1 indicating that a message has already been received, but rewriting is disabled because ows = 0). in this case, the message is not actually stored in the candidate message buffer with the highest priority, but neither is it stored in a message buffer with a lower priority. table 18-24 mbrb priorities priority storing condition if same id is set 1 (high) unmasked message buffer dn bit = 0 dn bit = 1 and ows bit = 1 2 message buffer linked to mask 1 dn bit = 0 dn bit = 1 and ows bit = 1 3 message buffer linked to mask 2 dn bit = 0 dn bit = 1 and ows bit = 1 4 message buffer linked to mask 3 dn bit = 0 dn bit = 1 and ows bit = 1 5 (low) message buffer linked to mask 4 dn bit = 0 dn bit = 1 and ows bit = 1
603 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.9.2 receive data read to keep data consistency when reading can message buffers, perform the data reading according to figure 18-49 on page 651 to figure 18-51 on page 653 . during message reception, the can module sets dn of the cnmctrlm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process. during this storage process, the muc bit of the cnmctrlm register of the message buffer is set. (refer to figure 18-28 on page 603 .) the receive history list is also updated just before the storgage process. in addition, during storage process (muc = 1), the rdy bit of the cnmctrl register of the message buffer is locked to avoid the coincidental data wr by cpu. note the storage process may be disturbed (delayed) when the cpu accesses the message buffer. figure 18-28 dn and muc bit setting period (for standard id format) sof (1) id ide rtr r0 dlc data0-data7 crc ack eof c an std id format (11) (1) (1) (1) (4) (0-64) (16) (2) recessive dominant dn muc message store mdata,mdlc.midx- > mbuf (7) set dn & clear muc at the same timing cints1 set dn & muc at the same time ifs intrec1 operation of the can contoroller
604 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.9.3 receive hist ory list function the receive history list (rhl) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. the rhl consists of storage elements equivalent to up to 23 messages, the last in-message pointer (lipt) with the corresponding cnlipt register and the receive history list get pointer (rgpt) with the corresponding cnrgpt register. the rhl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the cnlipt register holds the contents of the rhl element indicated by the value of the lipt pointer minus 1. by reading the cnlipt register, therefore, the number of the message buffer that received and stored a data frame or remote frame first can be checked. the lipt pointer is utilized as a write pointer that indicates to what part of the rhl a message buffer number is recorded. any time a data frame or remote frame is received and stored, the corresponding message buffer number is recorded to the rhl element indicated by the lipt pointer. each time recording to the rhl has been completed, the lipt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the rgpt pointer is utilized as a read pointer that reads a recorded message buffer number from the rhl. this pointer indicates the first rhl element that the cpu has not read yet. by reading the cnrgpt register by software, the number of a message buffer that has received and stored a data frame or remote frame can be read. each time a message buffer number is read from the cnrgpt register, the rgpt pointer is automatically incremented. if the value of the rgpt pointer matches the value of the lipt pointer, the rhpm bit (receive history list pointer match) of the cnrgpt register is set to 1. this indicates that no message buffer number that has not been read remains in the rhl. if a new message buffer number is recorded, the lipt pointer is incremented and because its value no longer matches the value of the rgpt pointer, the rhpm bit is cleared. in other words, the numbers of the unread message buffers exist in the rhl. if the lipt pointer is incremented and matches the value of the rgpt pointer minus 1, the rovf bit (receive history list overflow) of the cnrgpt register is set to 1. this indicates that the rhl is full of numbers of message buffers that have not been read. when further message reception and storing occur, the last recorded message buffer number is overwritten by the number of the message buffer that received and stored the newly received message. in this case, after the rovf bit has been set (1), the recorded message buffer numbers in the rhl do not completely reflect the chronological order. however messages itself are not lost and can be located by cpu search in message buffer memory with the help of the dn-bit. caution if the history list is in the overflow condition (rovf is set), reading the history list contents is still possible, until the history list is empty (indicated by rhpm flag set). nevertheless, the history list remains in the overflow condition, until rovf is cleared by software. if rovf is not cleared, the rhpm flag will also not be updated (cleared) upon a message storage of newly received frame. this may lead to the situation, that rhpm indicates an empty history list, although a reception has taken place, while the history list is in the overflow state (rovf and rhpm are set).
605 can controller (can) chapter 18 user?s manual u18743ee1v2um00 as long as the rhl contains 23 or less entries the sequence of occurrence is maintained. if more receptions occur without reading the rhl by the host processor, complete sequence of receptions can not be recovered. figure 18-29 receive history list
606 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.9.4 mask function for any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. by using the mask function, the message id comparison can be reduced by masked bits, herewith allowing the reception of several different ids into one buffer. while the mask function is in effect, an identifier bit that is defined to be 1 by a mask in the received message is not compared with the corresponding identifier bit in the message buffer. however, this comparison is performed for any bit whose value is defined as 0 by the mask. for example, let us assume that all messages that have a standard-format id, in which bits id27 to id25 are 0 and bits id24 and id22 are 1, are to be stored in message buffer 14. the procedure for this example is shown below. 1. identifier to be stored in message buffer 2. identifier to be configured in message buffer 14 (example) (using cnmidl14 and cnmidh14 registers) note 1. id with the id27 to id25 bits cleared to 0 and the id24 and id22 bits set to 1 is registered (initialized) to message buffer 14. 2. message buffer 14 is set as a standard format identifier that is linked to mask 1 (mt[2:0] of cnmconf14 register are set to 010 b ). mask setting for can module 0(mask 1) (example) (using can0 address mask 1 registers l and h (c0maskl1 and c0maskh1)) 1: not compared (masked) 0: compared id28 id27 id26 id25 id24 id 23 id22 id21 id20 id19 id18 x0001x1xxxx id28 id27 id26 id25 id24 id 23 id22 id21 id20 id19 id18 x0001x1xxxx id17 id16 id15 id14 id13 id 12 id11 id10 id9 id8 id7 xxxxxxxxxxx id6 id5 id4 id3 id2 id1 id0 xxxxxxx cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 10000101111 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 11111111111 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1111111
607 can controller (can) chapter 18 user?s manual u18743ee1v2um00 the cmid27 to cmid24 and cmid22 bits are cleared to 0, and the cmid28, cmid23, and cmid21 to cmid0 bits are set to 1.
608 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.9.5 multi buffer receive block function the multi buffer receive block (mbrb) function is used to store a block of data in two or more message buffers sequentially with no cpu interaction, by setting the same id to two or more message buffers with the same message buffer type. these message buffers can be allocated anywhere in the message buffer memory, they do not even have to follow each other adjacently. suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and the same id is set to each message buffer. if the first message whose id matches an id of the message buffers is received, it is stored in message buffer 10. at this point, the dn bit of message buffer 10 is set, prohibiting overwriting the message buffer when subsequent messages are received. when the next message with a matching id is received, it is received and stored in message buffer 11. each time a message with a matching id is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and so on. even when a data block consisting of multiple messages is received, the messages can be stored and received without overwriting the previously received matching-id data. whether a data block has been received and stored can be checked by setting the ie bit of the cnmctrlm register of each message buffer. for example, if a data block consists of k messages, k message buffers are initialized for reception of the data block. the ie bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the ie bit in message buffer k-1 is set to 1 (interrupts enabled). in this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating that mbrb has become full. alternatively, by clearing the ie bit of message buffers 0 to (k-3) and setting the ie bit of message buffer k-2, a warning that mbrb is about to overflow can be issued. the basic conditions of storing receive data in each message buffer for the mbrb are the same as the conditions of storing data in a single message buffer. caution 1. mbrb can be configured for each of the same message buffer types. therefore, even if a message buffer of another mbrb whose id matches but whose message buffer type is different has a vacancy, the received message is not stored in that message buffer, but instead discarded. 2. mbrb does not have a ring buffer structure. therefore, after a message is stored in the message buffer having the highest number in the mbrb configuration, a newly received message will not be stored in the message buffer having the lowest message buffer number. 3. mbrb operates based on the reception and storage conditions; there are no settings dedicated to mbrb, such as function enable bits. by setting the same message buffer type and id to two or more message buffers, mbrb is automatically configured. 4. with mbrb, ?matching id? means ?matching id after mask?. even if the id set to each message buffer is not the same, if the id that is masked by the mask register matches, it is considered a matching id and the buffer that has this id is treated as the storage destination of a message. 5. the priority between mbrbs is mentioned in the table table 18-24 .
609 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.9.6 remote frame reception in all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions.  used as a message buffer (ma0 bit of cnmconfm register set to 1.)  set as a transmit message buffer (mt[2:0] bits in cnmconfm register set to 000 b )  ready for reception (rdy bit of cnmctrlm register set to 1.)  set to transmit message (rtr bit of cnmconfm register is cleared to 0.)  transmission request is not set. (trq bit of cnmctrlm register is cleared to 0.) upon acceptance of a remote frame, the following actions are executed if the id of the received remote frame matches the id of a message buffer that satisfies the above conditions.  the dlc[3:0] bit string in the cnmdlcm register store the received dlc value.  the cnmdata0m to cnmdata7m registers in the data area are not updated (data before reception is saved).  the dn bit of the cnmctrlm register is set to 1.  the cints1 bit of the cnints register is set to 1 (if the ie bit in the cnmctrlm register of the message buffer that receives and stores the frame is set to 1).  the receive completion interrupt (intcnrec) is output (if the ie bit of the message buffer that receives and stores the frame is set to 1 and if the cie1 bit of the cnie register is set to 1).  the message buffer number is recorded in the receive history list. caution when a message buffer is searched for receiving and storing a remote frame, overwrite control by the ows bit of the cnmconfm register of the message buffer and the dn bit of the cnmctrlm register are not checked. the setting of ows is ignored, and dn is set in any case. if more than one transmit message buffer has the same id and the id of the received remote frame matches that id, the remote frame is stored in the transmit message buffer with the lowest message buffer number.
610 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.10 message transmission 18.10.1 message transmission a message buffer with its trq bit set to 1 participates in the search for the most high-prioritized message when the following conditions are fulfilled. this behavior is valid for all operational modes.  used as a message buffer (ma0 bit of cnmconfm register set to 1.)  set as a transmit message buffer (mt[2:0] bits of cnmconfm register set to 000 b .)  ready for transmission (rdy bit of cnmctrlm register set to 1.) the can system is a multi-master communication system. in a system like this, the priority of message transmission is determined based on message identifiers (ids). to facilitate transmission processing by software when there are several messages awaiting transmission, the can module uses hardware to check the id of the message with the highest priority and automatically identifies that message. this eliminates the need for software-based priority control. transmission priority is controlled by the identifier (id). figure 18-30 message processing example after the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the trq bit set to 1 in advance) is transmitted. if a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. if the new transmission request has a higher priority, it is transmitted, unless transmission of a message with a low priority has already started. if transmission of a message with a low priority has already started, however, the new transmission request is transmitted later. to solve this priority inversion effect, the software can perform a transmission abort request for the lower priority message. the highest priority is determined according to the following rules. message no. the can module transmits messages in the following sequenc e. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2
611 can controller (can) chapter 18 user?s manual u18743ee1v2um00 note 1. if the automatic block transmission request bit abttrg is set to 1 in the normal operation mode with abt, the trq bit is set to 1 only for one message buffer in the abt message buffer group. if the abt mode was triggered by abttrg bit (1), one trq bit is set to 1 in the abt area (buffer 0 through 7). beyond this trq bit, the application can request transmissions (set trq bit to 1) for other tx-message buffers that do not belong to the abt area. in that case an interval arbitration process (tx-search) evaluates all tx-message buffers with trq bit set to 1 and chooses the message buffer that contains the highest prioritized identifier for the next transmission. if there are 2 or more identifiers that have the highest priority (i.e. identical identifiers), the message located at the lowest message buffer number is transmitted at first. upon successful transmission of a message frame, the following operations are performed.  the trq flag of the corresponding transmit message buffer is automatically cleared to 0.  the transmission completion status bit cints0 of the cnints register is set to 1 (if the interrupt enable bit (ie) of the corresponding transmit message buffer is set to 1).  an interrupt request signal intcntrx is output (if the cie0 bit of the cnie register is set to 1 and if the interrupt enable bit (ie) of the corresponding transmit message buffer is set to 1). 2. when changing the contents of a transmit buffer, the rdy flag of this buffer must be cleared before updating the buffer contents. as during internal transfer actions, the rdy flag may be locked temporarily, the status of rdy must be checked by software, after changing it. priority conditions description 1 (high) value of first 11 bits of id [id28 to id18]: the message frame with the lowest value represented by the first 11 bits of the id is transmitted first. if the value of an 11-bit standard id is equal to or smaller than the first 11 bits of a 29-bit extended id, the 11-bit standard id has a higher priority than a message frame with a 29-bit extended id. 2 frame type a data frame with an 11-bit standard id (rtr bit is cleared to 0) has a higher priority than a remote frame with a standard id and a message frame with an extended id. 3 id type a message frame with a standard id (ide bit is cleared to 0) has a higher priority than a message frame with an extended id. 4 value of lower 18 bits of id [id17 to id0]: if two or more transmission-pending extended id message frame has equal values in the first 11 bits of the id and the same frame type (equal rtr bit values), the message frame with the lowest value in the lower 18 bits of its extended id is transmitted first. 5 (low) message buffer number if two or more message buffers request transmission of message frames with the same id, the message from the message buffer with the lowest message buffer number is transmitted first.
612 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.10.2 transmit hist ory list function the transmit history list (thl) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. the thl consists of storage elements equivalent to up to seven messages, the last out-message pointer (lopt) with the corresponding cnlopt register, and the transmit history list get pointer (tgpt) with the corresponding cntgpt register. the thl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the cnlopt register holds the contents of the thl element indicated by the value of the lopt pointer minus 1. by reading the cnlopt register, therefore, the number of the message buffer that transmitted a data frame or remote frame first can be checked. the lopt pointer is utilized as a write pointer that indicates to what part of the thl a message buffer number is recorded. any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the thl element indicated by the lopt pointer. each time recording to the thl has been completed, the lopt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the tgpt pointer is utilized as a read pointer that reads a recorded message buffer number from the thl. this pointer indicates the first thl element that the cpu has not yet read. by reading the cntgpt register by software, the number of a message buffer that has completed transmission can be read. each time a message buffer number is read from the cntgpt register, the tgpt pointer is automatically incremented. if the value of the tgpt pointer matches the value of the lopt pointer, the thpm bit (transmit history list pointer match) of the cntgpt register is set to 1. this indicates that no message buffer numbers that have not been read remain in the thl. if a new message buffer number is recorded, the lopt pointer is incremented and because its value no longer matches the value of the tgpt pointer, the thpm bit is cleared. in other words, the numbers of the unread message buffers exist in the thl. if the lopt pointer is incremented and matches the value of the tgpt pointer minus 1, the tovf bit (transmit history list overflow) of the cntgpt register is set to 1. this indicates that the thl is full of message buffer numbers that have not been read. if a new message is received and stored, the message buffer number recorded last is overwritten by the message buffer number that transmitted its message afterwards. in this case, after the tovf bit has been set (1), therefore, the recorded message buffer numbers in the thl do not completely reflect the chronological order. however the other transmitted messages can be found by a cpu search applied to all transmit message buffers unless the cpu has not overwritten a transmit object in one of these buffers beforehand. in total up to six transmission completions can occur without overflowing the thl.
613 can controller (can) chapter 18 user?s manual u18743ee1v2um00 caution if the history list is in the overflow condition (tovf is set), reading the history list contents is still possible, until the history list is empty (indicated by thpm flag set). nevertheless, the history list remains in the overflow condition, until tovf is cleared by software. if tovf is not cleared, the thpm flag will also not be updated (cleared) upon successful transmission of a new message. this may lead to the situation, that thpm indicates an empty history list, although a successful transmission has taken place, while the history list is in the overflow state (tovf and thpm are set). figure 18-31 transmit history list last out - message pointer (lopt) - cpu confirms tx completion of message buffer 6, 9, and 2. - tx completion of message buffer 3, and 4. event: transmit history list get pointer (tgpt) - message buffer 8, 5, 6, and 10 completes transmission. - thl is full. - tovf is set. event: transmit history list (thl) message buffer 6 message buffer 9 message buffer 2 message buffer 7 0 1 2 3 4 5 6 7 - message buffer11, 13, and 14 completes transmission. - overflow situation occurs. event: tovf = 1 lopt is blocked tovf = 1 lopt is blocked tovf = 1 denotes that lopt equals tgpt - 1 while message buffer number stored to element indicated by lopt - 1. last out - message pointer (lopt) transmit history lis t get pointer (tgpt) transmit history list (thl) message buffer 7 message buffer 3 message buffer 4 0 1 2 3 4 5 6 7 transmit history list (thl) message buf fer 6 message buffer 10 message buffer 7 message buffer 3 message buffer 4 message buffer 8 message buffer 5 0 1 2 3 4 5 6 7 last out - message pointer (lopt) transmit history list get pointer (tgpt) transmit history list (thl) message buffe r 6 message buffer 14 message buffer 7 message buffer 3 message buffer 4 message buffer 8 message buffer 5 0 1 2 3 4 5 6 7 last out - message pointer (lopt) transmit history lis t get pointer (tgpt)
614 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.10.3 automatic block transmission (abt) the automatic block transmission (abt) function is used to transmit two or more data frames successively with no cpu interaction. the maximum number of transmit message buffers assigned to the abt function is eight (message buffer numbers 0 to 7). by setting the opmode[2:0] bits of the cnctrl register to 010 b , ?normal operation mode with automatic block transmission function? (hereafter referred to as abt mode) can be selected. to issue an abt transmission request, define the message buffers by software first. set the ma0 bit (1) in all the message buffers used for abt, and define all the buffers as transmit message buffers by setting the mt[2:0] bits to 000 b . be sure to set the same id for the message buffers for abt even when that id is being used for all the message buffers. to use two or more ids, set the id of each message buffer by using the cnmidlm and cnmidhm registers. set the cnmdlcm and cnmdata0m to cnmdata7m registers before issuing a transmission request for the abt function. after initialization of message buffers for abt is finished, the rdy bit needs to be set (1). in the abt mode, the trq bit does not have to be manipulated by software. after the data for the abt message buffers has been prepared, set the abttrg bit to 1. automatic block transmission is then started. when abt is started, the trq bit in the first message buffer (message buffer 0) is automatically set to 1. after transmission of the data of message buffer 0 is finished, the trq bit of the next message buffer, message buffer 1, is set automatically. in this way, transmission is executed successively. a delay time can be inserted by program in the interval in which the transmission request (trq ) is automatically set while successive transmission is being executed. the delay time to be inserted is defined by the cngmabtd register. the unit of the delay time is dbt (data bit time). dbt depends on the setting of the cnbrp and cnbtr registers. among transmit objects within the abt-area, the priority of the transmission id is not evaluated. the data of message buffers 0 to 7 are sequentially transmitted. when transmission of the data frame from message buffer 7 has been completed, the abttrg bit is automatically cleared to 0 and the abt operation is finished. if the rdy bit of an abt message buffer is cleared during abt, no data frame is transmitted from that buffer, abt is stopped, and the abttrg bit is cleared. after that, transmission can be resumed from the message buffer where abt stopped, by setting the rdy and abttrg bits to 1 by software. to not resume transmission from the message buffer where abt stopped, the internal abt engine can be reset by setting the abtclr bit to 1 while abt mode is stopped and the abttrg bit is cleared to 0. in this case, transmission is started from message buffer 0 if the abtclr bit is cleared to 0 and then the abttrg bit is set to 1. an interrupt can be used to check if data frames have been transmitted from all the message buffers for abt. to do so, the ie bit of the cnmctrlm register of each message buffer except the last message buffer needs to be cleared (0). if a transmit message buffer other than those used by the abt function (message buffers 8 to 31) is assigned to a transmit message buffer, the message to be transmitted next is determined by the priority of the transmission id of the abt message buffer whose transmission is currently
615 can controller (can) chapter 18 user?s manual u18743ee1v2um00 held pending and the transmission id of the message buffers other than those used by the abt function. transmission of a data frame from an abt message buffer is not recorded in the transmit history list (thl). caution 1. set the abtclr bit to 1 while the abttrg bit is cleared to 0 in order to resume abt operation at buffer no.0. if the abtclr bit is set to 1 while the abttrg bit is set to 1, the subsequent operation is not guaranteed. 2. if the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared immediately after the processing of the clearing request is completed. 3. do not set the abttrg bit in the initialization mode. if the abttrg bit is set in the initialization mode, the proper operation is not guaranteed after the mode is changed from the initialization mode to the abt mode. 4. do not set the trq bit of the abt message buffers to 1 by software in the normal operation mode with abt. otherwise, the operation is not guaranteed. 5. the cngmabtd register is used to set the delay time that is inserted in the period from completion of the preceding abt message to setting of the trq bit for the next abt message when the transmission requests are set in the order of message numbers for each message for abt that is successively transmitted in the abt mode. the timing at which the messages are actually transmitted onto the can bus varies depending on the status of transmission from other stations and the status of the setting of the transmission request for messages other than the abt messages (message buffers 8 to 31). 6. if a transmission request is made for a message other than an abt message and if no delay time is inserted in the interval in which transmission requests for abt are automatically set (cngmabtd register = 00 h ), messages other than abt messages may be transmitted not depending on their priority compared to the priority of the abt message. 7. do not clear the rdy bit to 0 when the abttrg bit = 1. 8. if a message is received from another node while normal operation mode with abt is active, the tx-message from the abt-area may be transmitted with delay of one frame although cngmabtd register was set up with 00 h .
616 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.10.4 transmissi on abort process (1) transmission abort process except for in normal operation mode with automatic block transmission (abt) the user can clear the trq bit of the cnmctrlm register to 0 to abort a transmission request. the trq bit will be cleared immediately if the abort was successful. whether the transmission was successfully aborted or not can be checked using the tstat bit of the cnctrl register and the cntgpt register, which indicate the transmission status on the can bus (for details, refer to the processing in figure 18-45 on page 647 ). (2) transmission abort process except for abt transmission in normal operation mode with automatic block transmission (abt) the user can clear the abttrg bit of the cngmabt register to 0 to abort a transmission request. after checking the abttrg bit of the cngmabt register = 0, clear the trq bit of the cnmctrlm register to 0. the trq bit will be cleared immediately if the abort was successful. whether the transmission was successfully aborted or not can be checked using the tstat bit of the cnctrl register and the cntgpt register, which indicate the transmission status on the can bus (for details, refer to the processing in figure 18-46 on page 648 ). (3) transmission abort process for abt transmission in normal operation mode with automatic block transmission (abt) to abort abt that is already started, clear the abttrg bit of the cngmabt register to 0. in this case, the abttrg bit remains 1 if an abt message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. this aborts abt. if the last transmission (before abt) was successful, the normal operation mode with abt is left with the internal abt pointer pointing to the next message buffer to be transmitted. in the case of an erroneous transmission, the position of the internal abt pointer depends on the status of the trq bit in the last transmitted message buffer. if the trq bit is set to 1 when clearing the abttrg bit is requested, the internal abt pointer points to the last transmitted message buffer (for details, refer to the process in figure 18-47 on page 649 ). if the trq bit is cleared to 0 when clearing the abttrg bit is requested, the internal abt pointer is incremented (+1) and points to the next message buffer in the abt area (for details, refer to the process in figure 18-48 on page 650 ). caution be sure to abort abt by clearing abttrg bit to 0. the operation is not guaranteed if aborting transmission is requested by clearing rdy. when the normal operation mode with abt is resumed after abt has been aborted and the abttrg bit is set to 1, the next abt message buffer to be transmitted can be determined from the following table.
617 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.10.5 remote frame transmission remote frames can be transmitted only from transmit message buffers. set whether a data frame or remote frame is transmitted via the rtr bit of the cnmconfm register. setting (1) the rtr bit sets remote frame transmission. status of trq of abt message buffer abort after successful transmission abort after erroneous transmission set (1) next message buffer in the abt area a a) the above resumption operation can be performed only if a message buffer ready for abt exists in the abt area. for example, an abort request that is issued while abt of message buffer 7 is in progress is regarded as completion of abt, rather than abort, if transmission of message buffer 7 has been successfully completed, even if the abttrg bit is cleared to 0. if the rdy bit in the next message buffer in the abt area is cleared to 0, the internal abt pointer is retained, but the resumption operation is not performed even if the abttrg bit is set to 1, and abt ends immediately. same message buffer in the abt area cleared (0) next message buffer in the abt area a next message buffer in the abt area a
618 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.11 power saving modes 18.11.1 can sleep mode the can sleep mode can be used to set the can controller to stand-by mode in order to reduce power consumption. the can module can enter the can sleep mode from all operation modes. release of the can sleep mode returns the can module to exactly the same operation mode from which the can sleep mode was entered. in the can sleep mode, the can module does not transmit messages, even when transmission requests are issued or pending. (1) entering can sleep mode the cpu issues a can sleep mode transition request by writing 01 b to the psmode[1:0] bits of the cnctrl register. this transition request is acknowledged only under the following conditions. 1. the can module is already in one of the following operation modes ? normal operation mode ? normal operation mode with abt ? receive-only mode ? single-shot mode ? self-test mode ? can stop mode in all the above operation modes 2. the can bus state is bus idle (the 4th bit in the interframe space is reces- sive). if the can bus is fixed to dominant, the request for transition to the can sleep mode is held pending. also the transition from can stop mode to can sleep mode is independent of the can bus state. 3. no transmission request is pending note if a sleep mode request is pending, and at the same time a message is received in a message box, the sleep mode request is not cancelled, but is executed right after message storage has been finished. this may result in afcan being in sleep mode, while the cpu would execute the rx interrupt routine. therefore, the interrupt routine must check the access to the message buffers as well as reception history list registers by using the mbon flag, if sleep mode is used. similarly, if a sleep mode request is pending, and at the same time a message is transmitted in a message box, the sleep mode request is not cancelled, but is executed. this may result in can being in sleep mode, while the cpu would execute the transmit interrupt routine. therefore, the interrupt routine must check the access to the message buffers as well as transmission history list registers by using the mbon flag, if sleep mode is used. if any one of the conditions mentioned above is not met, the can module will operate as follows.  if the can sleep mode is requested from the initialization mode, the can sleep mode transition request is ignored and the can module remains in the initialization mode.  if the can bus state is not bus idle (i.e., the can bus state is either transmitting or receiving) when the can sleep mode is requested in one of
619 can controller (can) chapter 18 user?s manual u18743ee1v2um00 the operation modes, immediate transition to the can sleep mode is not possible. in this case, the can sleep mode transition request has to be held pending until the can bus state becomes bus idle (the 4th bit in the interframe space is recessive). in the time from the can sleep mode request to successful transition, the psmode[1:0] bits remain 00 b . when the module has entered the can sleep mode, the psmode[1:0] bits are set to 01 b .  if a request for transition to the initialization mode and a request for transition to the can sleep mode are made at the same time while the can module is in one of the operation modes, the request for the initialization mode is enabled. the can module enters the initialization mode at a predetermined timing. at this time, the can sleep mode request is not held pending and is ignored.  even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has not been granted while the second request is made), the request for initialization has priority over the sleep mode request. the sleep mode request is cancelled when the initialization mode is requested. when a pending request for initialization mode is present, a subsequent request for sleep mode request is cancelled right at the point in time where it was submitted. (2) status in can sleep mode the can module is in the following state after it enters the can sleep mode:  the internal operating clock is stopped and the power consumption is minimized.  the function to detect the falling edge of the can reception pin (crxdn) remains in effect to wake up the can module from the can bus.  to wake up the can module from the cpu, data can be written to the psmode[1:0] bits of the can module control register (cnctrl), but nothing can be written to other can module registers or bits.  the can module registers can be read, except for the cnlipt, cnrgpt, cnlopt, and cntgpt registers.  the can message buffer registers cannot be written or read.  mbon bit of the can global control register (cngmctrl) is cleared.  a request for transition to the initialization mode is not acknowledged and is ignored.
620 chapter 18 can controller (can) user?s manual u18743ee1v2um00 (3) releasing can sleep mode the can sleep mode is released by the following events:  when the cpu writes 00 b to the psmode[1:0] bits of the cnctrl register  a falling edge at the can reception pin (crxdn) (i.e. the can bus level shifts from recessive to dominant) caution even if the falling edge belongs to the sof of a receive message, this message will not be received and stored. if the cpu has turned off the clock supply to the can module while the can module was in sleep mode, even subsequently the can sleep mode will not be released and psmode [1:0] will remain 01 b unless the clock to the can module is supplied again. in addition to this, the receive message will not be received after that. after releasing the sleep mode, the can module returns to the operation mode from which the can sleep mode was requested and the psmode[1:0] bits of the cnctrl register must be reset by software to 00 b . if the can sleep mode is released by a change in the can bus state, the cints5 bit of the cnints register is set to 1, regardless of the cie bit of the cnie register. after the can module is released from the can sleep mode, it participates in the can bus again by automatically detecting 11 consecutive recessive-level bits on the can bus. the user application has to wait until mbon = 1, before accessing message buffers again. when a request for transition to the initialization mode is made while the can module is in the can sleep mode, that request is ignored; the can module has to be released from sleep mode by software first before entering the initialization mode. caution 1. be aware that the release of can sleep mode by can bus event, and thus the wake up interrupt may happen at any time, even right after requesting sleep mode, if a can bus event occurs. 2. always reset the psmode[1:0] bits to 00 b , when waking up from can sleep mode, before accessing any other registers of the can module. 3. always clear the interrupt flag cints5, when waking up from can sleep mode.
621 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.11.2 can stop mode the can stop mode can be used to set the can controller to stand-by mode to reduce power consumption. the can module can enter the can stop mode only from the can sleep mode. release of the can stop mode puts the can module in the can sleep mode. the can stop mode can only be released (entering can sleep mode) by writing 01 b to the psmode[1:0] bits of the cnctrl register and not by a change in the can bus state. no message is transmitted even when transmission requests are issued or pending. (1) entering can stop mode a can stop mode transition request is issued by writing 11 b to the psmode[1:0] bits of the cnctrl register. a can stop mode request is only acknowledged when the can module is in the can sleep mode. in all other modes, the request is ignored. caution to set the can module to the can stop mode, the module must be in the can sleep mode. to confirm that the module is in the sleep mode, check that the psmode[1:0] bits = 01 b , and then request the can stop mode. if a bus change occurs at the can reception pin (crxdn) while this process is being performed, the can sleep mode is automatically released. in this case, the can stop mode transition request cannot be acknowledged. (2) status in can stop mode the can module is in the following state after it enters the can stop mode.  the internal operating clock is stopped and the power consumption is minimized.  to wake up the can module from the cpu, data can be written to the psmode[1:0] bits of the can module control register (cnctrl), but nothing can be written to other can module registers or bits.  the can module registers can be read, except for the cnlipt, cnrgpt, cnlopt, and cntgpt registers.  the can message buffer registers cannot be written or read.  mbon bit of the can global control register (cngmctrl) is cleared.  an initialization mode transition request is not acknowledged and is ignored. (3) releasing can stop mode the can stop mode can only be released by writing 01 b to the psmode[1:0] bits of the cnctrl register. after releasing the can stop mode, the can module enters the can sleep mode. when the initialization mode is requested while the can module is in the can stop mode, that request is ignored; the cpu has to release the stop mode and subsequently can sleep mode before entering the initialization mode. it is impossible to enter the other operation mode directly from the can stop mode not entering the can sleep mode, that request is ignored.
622 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.11.3 example of us ing power saving modes in some application systems, it may be necessary to place the cpu in a power saving mode to reduce the power consumption. by using the power saving mode specific to the can module and the power saving mode specific to the cpu in combination, the cpu can be woken up from the power saving status by the can bus. here is an example for using the power saving modes.  first, put the can module in the can sleep mode (psmode[1:0] = 01 b ). next, put the cpu in the power saving mode. if an edge transition from recessive to dominant is detected at the can reception pin (crxdn) in this status, the cints5 bit in the can module is set to 1. if the cie5 bit of the cnctrl register is set to 1, a wakeup interrupt (intwupn) is generated.  the can module is automatically released from can sleep mode (psmode = 00 b ) and returns to normal operation mode.  the cpu, in response to intwupn, can release its own power saving mode and return to normal operation mode. to further reduce the power consumption of the cpu, the internal clock - including that of the can module - may be stopped. in this case, the operating clock supplied to the can module is stopped after the can module has been put in can sleep mode. then the cpu enters a power saving mode in which the clock supplied to the cpu is stopped.  if an edge transition from recessive to dominant is detected at the can reception pin (crxdn) in this status, the can module can set the cints5 bit to 1 and generate the wakeup interrupt (intwupn) even if it is not supplied with the clock.  the other functions, however, do not operate, because clock supply to the can module is stopped, and the module remains in can sleep mode.  the cpu, in response to intwupn ? releases its power saving mode, ? resumes supply of the internal clocks - including the clock to the can module - after the oscillation stabilization time has elapsed, and ? starts instruction execution.  the can module is immediately released from the can sleep mode when clock supply is resumed, and returns to the normal operation mode (psmode = 00 b ).
623 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.12 interrupt function the can module provides 6 different interrupt sources. the occurrence of these interrupt sources is stored in interrupt status registers. four separate interrupt request signals are generated from the six interrupt sources. when an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. after an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software. table 18-25 list of can module interrupt sources supplements 1. this interrupt is generated when the transmission/reception error counter is at the warning level, or in the error passive or bus-off state. 2. this interrupt is generated when a stuff error, form error, ack error, bit error, or crc error occurs. 3. this interrupt is generated when the can module is woken up from the can sleep mode because a falling edge is detected at the can reception pin (can bus transition from recessive to dominant). no. interrupt status bit interrupt enable bit interrupt request signal interrupt source description name register name register 1 cints0 cnints cie0 a a) the ie bit (message buffer interrupt enable bit) in the cnmctrl register of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process . cnie intcntrx message frame successfully transmitted from message buffer m 2 cints1 cnints cie1 a cnie intcnrec valid message frame reception in message buffer m 3 cints2 cnints cie2 cnie intcnerr can module error state interrupt (supplement 1) 4 cints3 cnints cie3 cnie can module protocol error interrupt (supplement 2) 5 cints4 cnints cie4 cnie can module arbitration loss interrupt 6 cints5 cnints cie5 cnie intcnwup can module wakeup interrupt from can sleep mode (supplement 3)
624 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.13 diagnosis functions and special operational modes the can module provides a receive-only mode, single-shot mode, and self-test mode to support can bus diagnosis functions or the operation of special can communication methods. 18.13.1 receive-only mode the receive-only mode is used to monitor receive messages without causing any interference on the can bus and can be used for can bus analysis nodes. for example, this mode can be used for automatic baud-rate detection. the baud rate in the can module is changed until ?valid reception? is detected, so that the baud rates in the module match (?valid reception? means a message frame has been received in the can protocol layer without occurrence of an error and with an appropriate ack between nodes connected to the can bus). a valid reception does not require message frames to be stored in a receive message buffer (data frames) or transmit message buffer (remote frames). the event of valid reception is indicated by setting the valid bit of the cnctrl register (1). figure 18-32 can module terminal connection in receive-only mode in the receive-only mode, no message frames can be transmitted from the can module to the can bus. transmit requests issued for message buffers defined as transmit message buffers are held pending. in the receive-only mode, the can transmission pin (ctxdn) in the can module is fixed to the recessive level. therefore, no active error flag can be transmitted from the can module to the can bus even when a can bus error is detected while receiving a message frame. since no transmission can be issued from the can module, the transmission error counter the cnerc.tec7 to cnerc.tec0 bits are never updated. therefore, a can module in the receive-only mode does not enter the bus-off state. can macro rx tx ctxdn crxdn fixed to the recessive level
625 can controller (can) chapter 18 user?s manual u18743ee1v2um00 furthermore, in the receive-only mode ack is not returned to the can bus in this mode upon the valid reception of a message frame. internally, the local node recognizes that it has transmitted ack. an overload frame cannot be transmitted to the can bus. caution if only two can nodes are connected to the can bus and one of them is operating in the receive-only mode, there is no ack on the can bus. due to the missing ack, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. the transmitting node becomes error passive after transmitting the message frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred). after the message frame for the 17th time is transmitted, the transmitting node generates a passive error flag. the receiving node in the receive-only mode detects the first valid message frame at this point, and the valid bit is set to 1 for the first time. 18.13.2 single-shot mode in the single-shot mode, automatic re-transmission as defined in the can protocol is switched off. (according to the can protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has to be repeated without control by software.) all other behavior of single shot mode is identical to normal operation mode. features of single shot mode can not be used in combination with normal mode with abt. the single-shot mode disables the re-transmission of an aborted message frame transmission according to the setting of the al bit of the cnctrl register. when the al bit is cleared to 0, re-transmission upon arbitration loss and upon error occurrence is disabled. if the al bit is set to 1, re-transmission upon error occurrence is disabled, but re-transmission upon arbitration loss is enabled. as a consequence, the trq bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events:  successful transmission of the message frame  arbitration loss while sending the message frame  error occurrence while sending the message frame the events arbitration loss and error occurrence can be distinguished by checking the cints4 and cints3 bits of the cnints register respectively, and the type of the error can be identified by reading the lec[2:0] bits of the cnlec register. upon successful transmission of the message frame, the transmit completion interrupt bit cints0 of the cnints register is set to 1. if the cie0 bit of the cnie register is set to 1 at this time, an interrupt request signal is output.
626 chapter 18 can controller (can) user?s manual u18743ee1v2um00 the single-shot mode can be used when emulating time-triggered communication methods (e.g., ttcan level 1). caution the al bit is only valid in single-shot mode. it does not influence the operation of re-transmission upon arbitration loss in the other operation modes. 18.13.3 self-test mode in the self-test mode, message frame transmission and message frame reception can be tested without connecting the can node to the can bus or without affecting the can bus. in the self-test mode, the can module is completely disconnected from the can bus, but transmission and reception are internally looped back. the can transmission pin (ctxdn) is fixed to the recessive level. if the falling edge on the can reception pin (crxdn) is detected after the can module has entered the can sleep mode from the self-test mode, however, the module is released from the can sleep mode in the same manner as the other operation modes. to keep the module in the can sleep mode, use the can reception pin (crxdn) as a port pin. figure 18-33 can module terminal connection in self-test mode can macro rx tx ctxdn crxdn fixed to the recessive level
627 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.13.4 receive/transmit ope ration in each operation mode the following table shows outline of the receive/transmit operation in each operation mode. table 18-26 outline of the receive/transmit in each operation mode operation mode transmis- sion of data/ remote frame transmis- sion of ack transmis- sion of error/ overload frame transmis- sion retry automatic block transmis- sion (abt) set of valid bit store data to message buffer initialization mode no no no no no no no normal operation mode yes yes yes yes no yes yes normal operation mode with abt yes yes yes yes yes yes yes receive only mode no no no no no yes yes single-shot mode ye s ye s ye s n o a a) when the arbitration lost occurs, control of re-transmission is possible by the al bit of cnctrl register. no yes yes self-test mode ye s b b) each signals are not generated to outside, but generated into the can module. ye s b ye s b ye s b no yes b ye s b
628 chapter 18 can controller (can) user?s manual u18743ee1v2um00 18.14 time stamp function can is an asynchronous, serial protocol. all nodes connected to the can bus have a local, autonomous clock. as a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies). in some applications, however, a common time base over the network (= global time base) is needed. in order to build up a global time base, a time stamp function is used. the essential mechanism of a time stamp function is the capture of timer values triggered by signals on the can bus. 18.14.1 time stamp function the can controller supports the capturing of timer values triggered by a specific frame. an on-chip 16-bit capture timer unit in a microcontroller system is used in addition to the can controller. the 16-bit capture timer unit captures the timer value according to a trigger signal (tsout) for capturing that is output when a data frame is received from the can controller. the cpu can retrieve the time of occurrence of the capture event, i.e., the time stamp of the message received from the can bus, by reading the captured value. the tsout signal can be selected from the following two event sources and is specified by the tssel bit of the cnts register.  sof event (start of frame) (tssel = 0)  eof event (last bit of end of frame) (tssel = 1) the tsout signal is enabled by setting the tsen bit of the cnts register to 1. figure 18-34 timing diagram of capture signal tsout the tsout signal toggles its level upon occurrence of the selected event during data frame reception (in figure 18-34 , the sof is used as the trigger event source). to capture a timer value by using the tsout signal, the capture timer unit must detect the capture signal at both the rising edge and falling edge. this time stamp function is controlled by the tslock bit of the cnts register. when tslock is cleared to 0, the tsout signal toggles upon occurrence of the selected event. if tslock is set to 1, the tsout signal toggles upon occurrence of the selected event, but the toggle is stopped as the tsen bit is automatically cleared to 0 as soon as the message storing to the message buffer 0 starts. this suppresses the subsequent toggle occurrence by the tsout signal, so that the time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data frame was received in message buffer 0. t t sout sof sof sof sof
629 can controller (can) chapter 18 user?s manual u18743ee1v2um00 caution the time stamp function using the tslock bit stops toggle of the tsout signal by receiving a data frame in message buffer 0. therefore, message buffer 0 must be set as a receive message buffer. since a receive message buffer cannot receive a remote frame, toggle of the tsout signal cannot be stopped by reception of a remote frame. toggle of the tsout signal does not stop when a data frame is received in a message buffer other than message buffer 0. for these reasons, a data frame cannot be received in message buffer 0 when the can module is in the normal operation mode with abt, because message buffer 0 must be set as a transmit message buffer. in this operation mode, therefore, the function to stop toggle of the tsout signal by the tslock bit cannot be used. 18.15 baud rate settings 18.15.1 baud rate setting conditions make sure that the settings are within the range of limit values for ensuring correct operation of the can controller, as follows. 5tq spt (sampling point) 17 tq spt = tseg1 + 1 8 tq dbt (data bit time) 25 tq dbt = tseg1 + tseg2 + 1tq = tseg2 + spt 1 tq sjw (synchronization jump width) 4tq sjw dbt ? spt 4 tseg1 16 [3 setting value of tseg1[3:0] 15] 1 tseg2 8 [0 setting value of tseg2[2:0] 7] note 1. tq = 1/f tq (f tq : can protocol layer basic system clock) 2. tseg1[3:0] (bits 3 to 0 of can bit rate register (cnbtr)) 3. tseg2[2:0] (bits 10 to 8 of can bit rate register (cnbtr))
630 chapter 18 can controller (can) user?s manual u18743ee1v2um00 table 18-27 shows the combinations of bit rates that satisfy the above conditions. table 18-27 settable bit rate combinations (1/3) valid bit rate setting cnbtr register setting value sampling point (unit %) dbt length sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.9 22 1 5 8 8 1100 111 63.6 22 1 7 7 7 1101 110 68.2 22 1 9 6 6 1110 101 72.7 22 1 11 5 5 1111 100 77.3 21 1 4 8 8 1011 111 61.9 21 1 6 7 7 1100 110 66.7 21 1 8 6 6 1101 101 71.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 20 1 3 8 8 1010 111 60.0 20 1 5 7 7 1011 110 65.0 20 1 7 6 6 1100 101 70.0 20 1 9 5 5 1101 100 75.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 19 1 2 8 8 1001 111 57.9 19 1 4 7 7 1010 110 63.2 19 1 6 6 6 1011 101 68.4 19 1 8 5 5 1100 100 73.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 18 1 1 8 8 1000 111 55.6 18 1 3 7 7 1001 110 61.1 18 1 5 6 6 1010 101 66.7 18 1 7 5 5 1011 100 72.2 18 1 9 4 4 1100 011 77.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 17 1 2 7 7 1000 110 58.8
631 can controller (can) chapter 18 user?s manual u18743ee1v2um00 17 1 4 6 6 1001 101 64.7 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 16 1 1 7 7 0111 110 56.3 16 1 3 6 6 1000 101 62.5 16 1 5 5 5 1001 100 68.8 16 1 7 4 4 1010 011 75.0 16 1 9 3 3 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 15 1 2 6 6 0111 101 60.0 15 1 4 5 5 1000 100 66.7 15 1 6 4 4 1001 011 73.3 15 1 8 3 3 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 14 1 1 6 6 0110 101 57.1 14 1 3 5 5 0111 100 64.3 14 1 5 4 4 1000 011 71.4 14 1 7 3 3 1001 010 78.6 14 1 9 2 2 1010 001 85.7 14 1 11 1 1 1011 000 92.9 13 1 2 5 5 0110 100 61.5 13 1 4 4 4 0111 011 69.2 13 1 6 3 3 1000 010 76.9 13 1 8 2 2 1001 001 84.6 13 1 10 1 1 1010 000 92.3 12 1 1 5 5 0101 100 58.3 12 1 3 4 4 0110 011 66.7 12 1 5 3 3 0111 010 75.0 table 18-27 settable bit rate combinations (2/3) valid bit rate setting cnbtr register setting value sampling point (unit %) dbt length sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0]
632 chapter 18 can controller (can) user?s manual u18743ee1v2um00 caution the values in table 18-27 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 12 1 7 2 2 1000 001 83.3 12 1 9 1 1 1001 000 91.7 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.0 10 1 5 2 2 0110 001 80.0 10 1 7 1 1 0111 000 90.0 9 1 2 3 3 0100 010 66.7 9 1 4 2 2 0101 001 77.8 9 1 6 1 1 0110 000 88.9 8 1 1 3 3 0011 010 62.5 8 1 3 2 2 0100 001 75.0 8 1 5 1 1 0101 000 87.5 7 a 1 2 2 2 0011 001 71.4 7 a 1 4 1 1 0100 000 85.7 6 a 1 1 2 2 0010 001 66.7 6 a 1 3 1 1 0011 000 83.3 5 a 1 2 1 1 0010 000 80.0 4 a 1 1 1 1 0001 000 75.0 a) setting with a dbt value of 7 or less is valid only when the value of the cnbrp register is other than 00 h . table 18-27 settable bit rate combinations (3/3) valid bit rate setting cnbtr register setting value sampling point (unit %) dbt length sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0]
633 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.15.2 representative examples of baud rate settings table 18-28 and table 18-29 show representative examples of baud rate settings. table 18-28 representative examples of baud rate settings (f canmod = 8 mhz) (1/2) set baud rate value (unit: kbps) division ratio of cnbrp register cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit: %) length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] 100010000000081133001101062.5 100010000000081322010000175.0 100010000000081511010100087.5 500100000000161177011111056.3 500100000000161366100010162.5 500100000000161555100110068.8 500100000000161744101001175.0 500100000000161933101101081.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 50020000000181133001101062.5 50020000000181322010000175.0 50020000000181511010100087.5 250200000001161177011111056.3 250200000001161366100010162.5 250200000001161555100110068.8 250200000001161744101001175.0 250200000001161933101101081.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 25040000001181322010000175.0 25040000001181511010100087.5 125400000011161177011111056.3 125400000011161366100010162.5 125400000011161555100110068.8 125400000011161744101001175.0 125400000011161933101101081.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 12580000011181322010000175.0 12580000011181511010100087.5 100400000011201766110010170.0 100400000011201955110110075.0 100500000100161744101001175.0 100500000100161933101101081.3
634 chapter 18 can controller (can) user?s manual u18743ee1v2um00 caution the values in table 18-28 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 100800000111101333010101070.0 100800000111101522011000180.0 100100000100181322010000175.0 100100000100181511010100087.5 83.3400000011241788111011166.7 83.3400000011241977111111070.8 83.3600000101161555100110068.8 83.3600000101161744101001175.0 83.3600000101161933101101081.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3800000111121533011101075.0 83.3800000111121722100000183.3 83.3120000101181322010000175.0 83.3120000101181511010100087.5 33.31000001001241788111011166.7 33.31000001001241977111111070.8 33.31200001011201766110010170.0 33.31200001011201955110110075.0 33.31500001110161744101001175.0 33.31500001110161933101101081.3 33.31600001111151644100101173.3 33.31600001111151833101001080.0 33.32000010011121533011101075.0 33.32000010011121722100000183.3 33.32400010111101333010101070.0 33.32400010111101522011000180.0 33.3300001110181322010000175.0 33.3300001110181511010100087.5 table 18-28 representative examples of baud rate settings (f canmod = 8 mhz) (2/2) set baud rate value (unit: kbps) division ratio of cnbrp register cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit: %) length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0]
635 can controller (can) chapter 18 user?s manual u18743ee1v2um00 table 18-29 representative examples of baud rate settings (f canmod = 16 mhz) (1/2) set baud rate value (unit: kbps) division ratio of cnbrp register cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit: %) length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0] 1000100000000161177011111056.3 1000100000000161366100010162.5 1000100000000161555100110068.8 1000100000000161744101001175.0 1000100000000161933101101081.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 100020000000181322010000175.0 100020000000181511010100087.5 500200000001161177011111056.3 500200000001161366100010162.5 500200000001161555100110068.8 500200000001161744101001175.0 500200000001161933101101081.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 50040000001181322010000175.0 50040000001181511010100087.5 250400000011161366100010162.5 250400000011161555100110068.8 250400000011161744101001175.0 250400000011161933101101081.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 25080000011181322010000175.0 25080000011181511010100087.5 125800000111161366100010162.5 125800000111161744101001175.0 125800000111161933101101081.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125160000111181322010000175.0 125160000111181511010100087.5 100800000111201955110110075.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 1001000001001161744101001175.0 1001000001001161933101101081.3 1001600001111101333010101070.0 1001600001111101522011000180.0 100200001001181322010000175.0
636 chapter 18 can controller (can) user?s manual u18743ee1v2um00 caution the values in table 18-29 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 83.3800000111241788111011166.7 83.3800000111241977111111070.8 83.31200001011161744101001175.0 83.31200001011161933101101081.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.31600001111121533011101075.0 83.31600001111121722100000183.3 83.3240001011181322010000175.0 83.3240001011181511010100087.5 33.33000011101241788111011166.7 33.33000011101241977111111070.8 33.32400010111201955110110075.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.33000011101161744101001175.0 33.33000011101161933101101081.3 33.33200011111151833101001080.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.33700100100131633100001076.9 33.33700100100131822100100184.6 33.34000100111121533011101075.0 33.34000100111121722100000183.3 33.34800101111101333010101070.0 33.34800101111101522011000180.0 33.3600011101181322010000175.0 33.3600011101181511010100087.5 table 18-29 representative examples of baud rate settings (f canmod = 16 mhz) (2/2) set baud rate value (unit: kbps) division ratio of cnbrp register cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit: %) length of dbt sync segment prop segment phase segment1 phase segment2 tseg1 [3:0] tseg2 [2:0]
637 can controller (can) chapter 18 user?s manual u18743ee1v2um00 18.16 operation of can controller the processing procedure for showing in this chapter is recommended processing procedure to operate can controller. develop the program referring to recommended processing procedure in this chapter. figure 18-35 initialization start set cngmcs register. set cnbrp register, cnbtr register. set cnie register. set cnmask register. initialize message buffers. set cnctrl register (set opmode bit). end set cngmctrl register (set gom bit = 1) o pmode: normal operation mode, normal operation mode with ab t, receive-only mode, single-shot mode, self-test mode
638 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-36 re-initialization caution after setting the can module to the initialization mode, avoid setting the module to another operation mode immediately after. if it is necessary to immediately set the module to another operation mode, be sure to access registers other than the cnctrl and cngmctrl registers (e.g., set a message buffer). s tart s et cnbrp register, cnbtr register s et cnie register s et cnma s k register s et cnctrl register ( s et opmode) end clear opmode init mode? no yes s et ccerc bit yes no initialize message buffers cnerc and cninfo register clear? s tart s et cnbrp register, cnbtr register s et cnie register s et cnma s k register s et cnctrl register ( s et opmode) end clear opmode init mode? no s et ccerc bit yes no initialize message buffers cnerc and cninfo register clear? opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode
639 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-37 message buffer initialization caution 1. before a message buffer is initialized, the rdy bit must be cleared. 2. make the following settings for message buffers not used by the application.  clear the rdy, trq, and dn bits of the cnmctrlm register to 0.  clear the ma0 bit of the cnmconfm register to 0. s tart s et cnmconfm register end rdy = 1? no yes clear rdy bit rdy = 0? s et cnmidhm register, cnmidlm register transmit message buffer? clear cnmdatam register s et cnmctrlm register s et rdy bit s et cnmdlcm register no no yes yes s tart s et cnmconfm register end rdy = 1? no yes clear rdy bit rdy = 0? s et cnmidhm register, cnmidlm register transmit message buffer? clear cnmdatam register s et cnmctrlm register s et rdy bit s et cnmdlcm register no no yes yes
640 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-38 shows the processing for a receive message buffer (mt[2:0] bits of cnmconfm register = 001 b to 101 b ). figure 18-38 message buffer redefinition s tart s et message buffers end rdy = 1? no yes clear rdy bit rdy = 0? no clear valid bit s et rdy bit yes yes no wait for 4 can data bits note2 r s tat = 0 or valid = 1? note1 note1: confirm that a message is being received because rdy bit must be set after a message is completely received. note2: avoid message buffer redefinition during store operation of message reception by waiting additional 4 can data bits.
641 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-39 shows the processing for a transmit message buffer during transmission (mt[2:0] bits of cnmconfm register = 000 b ). figure 18-39 message buffer redefinition during transmission s tart end rdy = 0? no yes data frame or remote frame? s et rdy bit s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers remote frame data frame transmit abort process clear rdy bit transmit? s et trq bit yes wait for 1can data bits no s tart end rdy = 0? no yes data frame or remote frame? s et rdy bit s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers remote frame data frame transmit abort process clear rdy bit transmit? s et trq bit yes wait for 1can data bits no
642 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-40 shows the processing for a transmit message buffer (mt[2:0] bits of cnmconfm register = 000 b ). figure 18-40 message transmit processing caution 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. s tart end trq = 0? no yes clear rdy bit rdy = 0? data frame or remote frame? s et rdy bit yes no s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et trq bit remote frame data frame s tart end trq = 0? no yes clear rdy bit rdy = 0? data frame or remote frame? s et rdy bit yes no s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et trq bit remote frame data frame
643 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-41 shows the processing for a transmit message buffer (mt[2:0] bits of cnmconfm register = 000 b ) figure 18-41 abt message transmit processing note this processing (normal operation mode with abt) can only be applied to message buffers 0 to 7. for message buffers other than the abt message buffers, see figure 18-40 on page 642 . caution the abttrg bit should be set to 1 after the tstat bit is cleared to 0. checking the tstat bit and setting the abttrg bit to 1 must be processed consecutively. s tart s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers end abttrg = 0? no yes clear rdy bit rdy = 0? s et rdy bit yes no s et abttrg bit s et all abt transmit messages? t s tat = 0? yes no yes no s tart s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers end abttrg = 0? no yes clear rdy bit rdy = 0? s et rdy bit yes no s et abttrg bit s et all abt transmit messages? t s tat = 0? yes no yes no
644 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-42 transmission via interrupt (using cnlopt register) caution 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. note also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as tx history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing tx interrupts. s tart end clear rdy bit rdy = 0? data frame or remote frame? s et rdy bit yes no s et cnmdataxm register s et cnmdlcm register, clear rtr bit of cnmconfm register. s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm register. s et cnmidlm and cnmidhm registers s et trq bit remote frame data frame transmit completion interrupt processing read cnlopt register s tart end clear rdy bit rdy = 0? data frame or remote frame? s et rdy bit yes no s et cnmdataxm register s et cnmdlcm register, clear rtr bit of cnmconfm register. s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm register. s et cnmidlm and cnmidhm registers s et trq bit remote frame data frame transmit completion interrupt processing transmit completion interrupt processing read cnlopt register
645 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-43 transmission via interrupt (using cntgpt register) caution 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. note 1. also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as tx history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of s tart end tovf = 1? data frame or remote frame? s et rdy bit yes s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et trq bit remote frame data frame transmit completion interrupt processing read cntgpt register clear tovf bit clear rdy bit rdy = 0? thpm = 1? no yes no yes s tart end tovf = 1? data frame or remote frame? s et rdy bit no s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm register s et cnmidlm and cnmidhm registers s et trq bit remote frame data frame transmit completion interrupt processing transmit completion interrupt processing read cntgpt register clear tovf bit clear rdy bit rdy = 0? thpm = 1? no yes no yes
646 chapter 18 can controller (can) user?s manual u18743ee1v2um00 the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing tx interrupts. 2. if tovf was set once, the transmit history list is inconsistent. consider to scan all configured transmit buffers for completed transmissions. figure 18-44 transmission via software polling caution 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. s tart end tovf = 1? data frame or remote frame? s et rdy bit yes no s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register. s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm s et cnmidlm and cnmidhm registers s et trq bit remote frame data frame read cntgpt register clear tovf bit clear rdy bit rdy = 0? thpm = 1? no yes no yes cint s 0 = 1? no clear cint s 0 bit yes s tart end tovf = 1? data frame or remote frame? s et rdy bit yes no s et cnmdataxm register s et cnmdlcm register clear rtr bit of cnmconfm register. s et cnmidlm and cnmidhm registers s et cnmdlcm register s et rtr bit of cnmconfm s et cnmidlm and cnmidhm registers s et trq bit remote frame data frame read cntgpt register clear tovf bit clear rdy bit rdy = 0? thpm = 1? no yes no yes cint s 0 = 1? no clear cint s 0 bit yes
647 can controller (can) chapter 18 user?s manual u18743ee1v2um00 note 1. also check the mbon flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as tx history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. 2. if tovf was set once, the transmit history list is inconsistent. consider to scan all configured transmit buffers for completed transmissions. figure 18-45 transmission abort processing (except normal operation mode with abt) note there is a possibility of starting the transmission without being aborted even if trq bit is cleared, because the transmission request to protocol layer might already been accepted between 11 bits, total of interframe space (3 bits) and suspend transmission (8 bits). caution 1. clear the trq bit for aborting transmission request, not the rdy bit. 2. before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. do not execute any new transmission request including in the other message buffers while transmission abort processing is in progress. s tart read cnlopt register end no yes clear trq bit t s tat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits note transmission successful transmit abort request was successful yes s tart read cnlopt register end no yes clear trq bit t s tat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits note transmission successful transmission successful transmit abort request was successful transmit abort request was successful yes
648 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-46 transmission abort processing except for abt transmission (normal operation mode with abt) caution 1. clear the trq bit for aborting transmission request, not the rdy bit. 2. before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. do not execute any new transmission request including in the other message buffers while transmission abort processing is in progress. s tart read cnlopt register end no yes clear trq bit t s tat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits transmission successful transmit abort request was successful yes no abttrg = 0? clear abttrg bit yes s tart read cnlopt register end no yes clear trq bit t s tat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits transmission successful transmission successful transmit abort request was successful transmit abort request was successful yes no abttrg = 0? clear abttrg bit yes
649 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-47 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 18-47 transmission abort processing (normal operation mode with abt) caution 1. do not set any transmission requests while abt transmission abort processing is in progress. 2. make a can sleep mode/can stop mode transition request after the abttrg bit is cleared (after abt mode is aborted) following the procedure shown in figure 18-47 or figure 18-48 . when clearing a transmission request in an area other than the abt area, follow the procedure shown in figure 18-45 on page 647 . s tart end no clear abttrg bit abttrg = 0? transmission start no clear trq bit of message buffer whose transmission was aborted transmit abort yes s et abtclr bit yes no t s tat = 0? yes s tart end no clear abttrg bit abttrg = 0? transmission start no clear trq bit of message buffer whose transmission was aborted transmit abort transmit abort yes s et abtclr bit yes no t s tat = 0? yes
650 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-48 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 18-48 abt transmission request abort processing (normal operation mode with abt) caution 1. do not set any transmission requests while abt transmission abort processing is in progress. 2. make a can sleep mode/can stop mode request after the abttrg bit is cleared (after abt mode is stopped) following the procedure shown in figure 18-47 or figure 18-48 . when clearing a transmission request in an area other than the abt area, follow the procedure shown in figure 18-45 on page 647 . s tart end no clear abttrg bit abttrg = 0? transmission start pointer clear? no transmit abort yes s et abtclr bit yes clear trq bit of message buffer undergoing transmission s tart end no clear abttrg bit abttrg = 0? transmission start pointer clear? no transmit abort transmit abort yes s et abtclr bit yes clear trq bit of message buffer undergoing transmission
651 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-49 reception via interrupt (using cnlipt register) note also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing rx interrupts. s tart end no read cnmdataxm, cnmdlcm, cnmidlm, and cnmidhm registers dn = 0 and muc = 0 read cnlipt register yes generation of receive completion interrupt clear dn bit note s tart end no read cnmdataxm, cnmdlcm, cnmidlm, and cnmidhm registers dn = 0 and muc = 0 read cnlipt register yes generation of receive completion interrupt clear dn bit note note check the muc and dn bits using one read access.
652 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-50 reception via interrupt (using cnrgpt register) note 1. also check the mbon flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. it is recommended to cancel any sleep mode requests, before processing rx interrupts. 2. if rovf was set once, the receive history list is inconsistent. consider to scan all configured receive buffers for receptions. note check the muc and dn bits using one read access. s tart clear rovf bit no rovf = 1? read cnrgpt register yes generation of receive completion interrupt clear dn bit read cnmdataxm, cnmdlcm, cnmidlm, cnmidhm registers dn = 0 and muc = 0 note rhpm = 1? end yes yes no correct data is read illegal data is read no s tart clear rovf bit no rovf = 1? read cnrgpt register yes generation of receive completion interrupt clear dn bit read cnmdataxm, cnmdlcm, cnmidlm, cnmidhm registers dn = 0 and muc = 0 note dn = 0 and muc = 0 note rhpm = 1? end yes yes no correct data is read illegal data is read no
653 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-51 reception via software polling note 1. also check the mbon flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed. if mbon is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after mbon is set again. 2. if rovf was set once, the receive history list is inconsistent. consider to scan all configured receive buffers for receptions. s tart cint s 1 = 1? yes no clear cint s 1 bit clear rovf bit no rovf = 1? read cnrgpt register yes clear dn bit read cnmdataxm, cnmdlcm, cnmidlm, cnmidhm registers end yes yes no correct data is read illegal data is read s tart cint s 1 = 1? yes no clear cint s 1 bit clear rovf bit rovf = 1? read cnrgpt register clear dn bit read cnmdataxm, cnmdlcm, cnmidlm, cnmidhm registers dn = 0 and muc = 0 note rhpm = 1? end yes no correct data is read illegal data is read no note check the muc and dn bits using one read access.
654 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-52 setting can sleep mode/stop mode caution to abort transmission before making a request for the can sleep mode, perform processing according to figure 18-45 on page 647 and figure 18-47 on page 649 . s tart (when p s mode[1:0] = 00b) p s mode0 = 1? s et p s mode0 bit can sleep mode end yes no s et p s mode1 bit p s mode1 = 1? can stop mode request can sleep mode again? clear opmode yes no yes no access to registers other than the cnctrl and cngmctrl registers init mode? yes no clear cint s 5 bit s et cnctrl register (set opmode) s tart (when p s mode[1:0] = 00b) p s mode0 = 1? s et p s mode0 bit can sleep mode can sleep mode end yes no s et p s mode1 bit p s mode1 = 1? can stop mode can stop mode request can sleep mode again? no yes no clear cint s 5 bit
655 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-53 clear can sleep/stop mode s tart end releasing can sleep mode by user clear p s mode0 bit can stop mode clear p s mode1 bit can sleep mode clear cint s 5 bit clear p s mode0 bit releasing can sleep mode by can bus activity dominant edge on can detected end clear p s mode0 bit
656 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-54 bus-off recovery (except normal operation mode with abt) caution when the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequence again in the bus-off recovery sequence, reception error counter is cleared. therefore it is necessary to detect 11 consecutive recessive-level bits 128 times on the bus again. s tart forced recovery from bus off? end boff = 1? yes no s et ccerc bit s et cnctrl register ( s et opmode) yes no clear all trq bits note access to registers other than cnctrl and cngmctrl registers s et cnctrl register (clear opmode) s et cnctrl register ( s et opmode) wait for recovery from bus off note: clear all trq bits when re-initialization of message buffer is executed by clearing rdy bit before bus-off recovery sequence is started. opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode
657 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-55 bus-off recovery (normal operation mode with abt) caution when the transmission from the initialization mode to any operation modes is requested to execute bus-off recovery sequence again in the bus-off recovery sequence, reception error counter is cleared. therefore it is necessary to detect 11 consecutive recessive-level bits 128 times on the bus again. note: clear all trq bits when re-initialization of message buffer is executed by clearing rdy bit before bus-off recovery sequence is started. opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode s tart forced recovery from bus off? end boff = 1? yes no s et ccerc bit s et cnctrl register ( s et opmode) yes no clear all trq bits note clear abttrg bit access to registers other than cnctrl and cngmctrl registers s et cnctrl register (clear opmode) s et cnctrl register ( s et opmode) wait for recovery from bus off s et cnctrl register ( s et opmode)
658 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-56 normal shutdown process s tart gom = 0? clear gom bit end yes no init mode s tart end s hutdown successful gom = 0, ef s d = 0
659 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-57 forced shutdown process caution do not read- or write-access any registers by software between setting the efsd bit and clearing the gom bit. s tart gom = 0? clear gom bit end yes no s et ef s d bit must be a subsequent write gom = 0? clear gom bit end s hutdown successful gom = 0, ef s d = 0
660 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-58 error handling s tart cint s 2 = 1? cint s 3 = 1? end yes no yes no error interrupt clear cint s 3 bit clear cint s 2 bit cint s 4 = 1? clear cint s 4 bit no yes cint s 3 = 1? check can module state (read cninfo register) check can protocol error state (read cnlec register)
661 can controller (can) chapter 18 user?s manual u18743ee1v2um00 figure 18-59 setting cpu stand-by (from can sleep mode) caution before the cpu is set in the cpu standby mode, please check if the can sleep mode has been reached. however, after check of the can sleep mode, until the cpu is set in the cpu standby mode, the can sleep mode may be cancelled by wakeup from can bus. start end set psmode0 bit. set psmode0 bit = 1 clear psmode0 bit = 0 ye s no cints5 bit = 1? psmode0 bit = 1? mbon bit = 0? no ye s ye s no clear cints5 bit. clear cints5 bit = 1 can sleep mode set cpu standby mode.
662 chapter 18 can controller (can) user?s manual u18743ee1v2um00 figure 18-60 setting cpu stand-by (from can stop mode) caution the can stop mode can only be released by writing 01 b to the psmode[1:0] bit of the cnctrl register and not by a change in the can bus state. start end set psmode0 bit. set psmode0 bit = 1 clear psmode0 bit = 0 psmode0 bit = 1? mbon bit = 0? ye s no psmode1 bit = 1? no ye s can stop mode ye s no set psmode1 bit. set psmode1 bit = 1 clear psmode1 bit = 0 clear cints5 bit. clear cints5 bit = 1 set cpu standby mode. can sleep mode
663 user?s manual u18743ee1v2um00 chapter 19 a/d converter (adc) the v850es/fx3-l microcontrollers have following instances of the a/d converter adc: throughout this chapter, the individual instances of adc are identified by ?n?, for example, adanm0 for the adan mode register 0. throughout this chapter, the individual channels of each adc instance are identified by ?m?, for example, adancrm for the conversion result register m of adan. 19.1 functions the a/d converter converts analog input signals into digital values. the a/d converter has the following features.  10-bit resolution  successive approximation method  the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot select mode ? one-shot scan mode  the following functions are provided as trigger modes. ? software trigger mode ? timer trigger mode ? hardware trigger mode ? external trigger mode  power-fail monitor function (conversion result compare function)  self diagnostic function  discharge function adc v850es/fe3-l v850es/ff3-l v850es/fg3-l instances 1 1 1 names ada0 ada0 ada0 channels 10 12 16
664 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 the block diagram of the a/d converter is shown below. figure 19-1 block diagram of a/d converter adanm0 adanm1 adanm2 adans sar adancr0 adancr1 adancrm av ref0 adanps bit av ss adance bit f xp1 v olt age comp arator controller sample & hold circuit ta p selector selector internal bus adtrg adanets0 bit adanets1 bit edge detection inttaa2cc0 inttaa2cc1 tqtadt0 ani0 ani1 anim { a dc0 intad adanpft adanpfm control circuit adanpfe bit adanpfc bit voltage comperator
665 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 19.2 configuration the a/d converter includes the following hardware. table 19-1 configuration of a/d converter (1) sar - successive approximation register the sar register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the comparison result starting from the most significant bit (msb). when the comparison result has been held down to the least significant bit (lsb) (i.e., when a/d conversion is complete), the contents of the sar register are transferred to the adancrm register. (2) a/d conversion result register n (adancrm), a/d conversion result register nh (adancrmh) the adancrm register is a 16-bit register that stores the a/d conversion result. adancrm consist of m registers and the a/d conversion result is stored in the 10 higher bits of the adancrm register corresponding to analog input. (the lower 6 bits are fixed to 0.) the adancrm register is read-only, in 16-bit units. when using only the higher 8 bits of the a/d conversion result, the adancrmh register is read-only, in 8-bit units. caution a write operation to the adanm0 and adans registers may cause the contents of the adancrm register to become undefined. after the conversion, read the conversion result before writing to the adanm0 and adans registers. correct conversion results may not be read if a sequence other than the above is used. (3) power-fail compare threshold value register (adanpft) the adanpft register sets a threshold value that is compared with the value of a/d conversion result register nh (adancrmh). the 8-bit data set to the adanpft register is compared with the higher 8 bits of the a/d conversion result register (adancrmh). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. item configuration analog inputs ani0 to anim registers successive approximation register (sar) a/d conversion result registers adancrm, adancrmh avref a/d conversion diagnostic registers adancrdd, adancrddh avss a/d conversion diagnostic registers adancrss, adancrssh adc power-fail compare mode register adanpfm adc power-fail compare threshold value register adanpft control registers a/d converter mode registers 0 to 2 (adanm0 to adanm2) a/d converter channel specification register 0 (adans)
666 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (4) sample & hold circuit the sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (5) voltage comparator the voltage comparator compares a voltage value that has been sampled and held with the voltage value of the series resistor string. (6) series resistor string this series resistor string is connected between av ref and av ss and generates a voltage for comparison with the analog input signal. (7) aninm pins these are analog input pins for the m a/d converter channels and are used to input analog signals to be converted into digital signals. pins other than the one selected as the analog input by the adans register can be used as input port pins. caution 1. make sure that the voltages input to the aninm pins do not exceed the rated values. in particular if a voltage of av ref or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. 2. the analog input pins aninm function also as input port pins. if any of aninmm is selected and a/d converted, do not execute an input instruction to this ports during conversion. if executed, the conversion resolution may be degraded. (8) av ref pin this is the pin used to input the reference voltage of the a/d converter. av ref also delivers the a/d converter's analog supply voltage av dd . av ref has to be connected to v dd even if the a/d converter is not used. the signals input to the aninmm pins are converted to digital signals based on the voltage applied between the av ref and av ss pins. (9) av ss pin this is the ground pin of the a/d converter. always make the potential at this pin the same as that at the v ss pin even when the a/d converter is not used.
667 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 19.3 adc registers the a/d converter is controlled by the following registers:  a/d converter mode registers 0, 1, 2 (adanm0, adanm1, adanm2)  a/d converter channel specification register 0 (adans)  power-fail compare mode register (adanpfm) the following registers are also used:  a/d conversion result register n (adancrm)  a/d conversion result register nh (adancrmh)  power-fail compare threshold value register (adanpft) (1) adanm0 - adc mode register 0 the adanm0 register is an 8-bit register that specifies the operation mode and controls conversion operations. this register can be read or written in 8-bit or 1-bit units. however, bit 0 is read- only. reset input clears this register to 00h. after reset: 00h r/w address: ada0m0 fffff200h 76543210 adanm0 adance adanps adanmd1 adanmd0 adanets1 adanets0 adantmd adanef adance a/d conversion control 0 stops conversion 1 starts conversion adanps a/d conversion control 0a/d power off 1a/d power on note: the a/d converter needs a stabilization time after a/d power on. only if the specified stabilization time after adanps = 1 (power on) is taken, the first conversion result is valid. adanmd1 adanmd0 specification of a/d conversion operation mode 0 0 continuous select mode 0 1 continuous scan mode 1 0 one-shot select mode 1 1 one-shot scan mode
668 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 caution 1. writing to adanef is ignored. 2. when not using the a/d converter, stop the operation by setting the adanps bit to 0 to reduce the current consumption. 3. during a/d conversion (adance bit = 1), the adanfr3 to adanfr0 bits of the adanm1 register cannot be changed. 4. access to the adanm0 register during sub-clock operation and when the main clock is stopped is prohibited. adanets1 adanets0 specification of external trigger (adtrg pin) input valid edge 0 0 no edge detection 0 1 falling edge detection 1 0 rising edge detection 1 1 detection of both rising and falling edges adantmd trigger mode specification 0 software trigger mode 1 external trigger mode/ timer trigger mode adanef a/d converter status display 0 a/d conversion stopped 1 a/d conversion in progress
669 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (2) adanm1 - adc mode register 1 the adanm1 register is an 8-bit register that controls the conversion time specification. this register can be read or written in 8-bit or 1-bit units. reset input clears this bit to 00h. caution 1. be sure to clear bits 4-7 to 0. 2. changing the adanfr3 to adanfr0 bits of the adanm1 register during conversion (adance0 bit = 1) is prohibited. for a/d conversion time settings, see table 19-2 . after reset: 00h r/w address: ada0m1 fffff201h 76543210 adanm10000adanfr3adanfr2adanfr1adanfr0 table 19-2 conversion, sampling, discharge time settings adanfr3-0 a/d conversion time adandisc=1 (discharge function) a/d sampling time 3 2 1 0 0000 32/f xp1 4/f xp1 17/f xp1 0001 64/f xp1 8/f xp1 34/f xp1 0010 96/f xp1 12/f xp1 51/f xp1 0011 128/f xp1 16/f xp1 68/f xp1 0100 160/f xp1 20/f xp1 85/f xp1 0101 192/f xp1 24/f xp1 102/f xp1 0110 224/f xp1 28/f xp1 119/f xp1 0111 256/f xp1 32/f xp1 136/f xp1 1000 288/f xp1 36/f xp1 153/f xp1 1001 320/f xp1 40/f xp1 170/f xp1 1010 prohibited prohibited prohibited 1011 prohibited prohibited prohibited 1100 prohibited prohibited prohibited 1101 prohibited prohibited prohibited 1110 prohibited prohibited prohibited 1111 prohibited prohibited prohibited table 19-3 conversion time settings (1/2) adanfr3-0 a/d conversio n time f xp1 = 20 mhz f xp1 = 16 mhz f xp1 = 10 mhz f xp1 = 4mhz 3 2 1 0 0000 32/f xp1 prohibited prohibited 3.20 s 8.00 s
670 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 0001 64/f xp1 3.20 s 4.00 s 6.40 s 16.00 s 0010 96/f xp1 4.80 s 6.00 s 9.60 s prohibited 0011 128/f xp1 6.40 s 8.00 s 12.80 s prohibited 0100 160/f xp1 8.00 s 10.00 s 16.00 s prohibited 0101 192/f xp1 9.60 s 12.00 s prohibited prohibited 0110 224/f xp1 11.20 s 14.00 s prohibited prohibited 0111 256/f xp1 12.80 s 16.00 s prohibited prohibited 1000 288/f xp1 14.40 s prohibited prohibited prohibited 1001 320/f xp1 16.00 s prohibited prohibited prohibited 1010 352/f xp1 prohibited prohibited prohibited prohibited 1011 384/f xp1 prohibited prohibited prohibited prohibited 1100 416/f xp1 prohibited prohibited prohibited prohibited 1101 448/f xp1 prohibited prohibited prohibited prohibited 1110 480/f xp1 prohibited prohibited prohibited prohibited 1111 512/f xp1 prohibited prohibited prohibited prohibited table 19-3 conversion time settings (2/2)
671 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (3) adanm2 - adc mode register 2 the adanm2 register specifies the hardware trigger mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. note in the discharge function the avrefm (ass) voltage is sampled during 4 clocks (f xp1 ) after finishing a/d conversion. therefore, additional 2 clocks must be added to the a/d conversion time. caution be sure to clear bits 7, 6, 3, and 2 to 0. after reset: 00h r/w address: ad0m2 fffff203h 76543210 adanm2 0 0 adandiag adandisc 0 0 adantmd1 adantmd0 adandiag diagnostic function enable 0 diagnostic function disabled 1 diagnostic function enabled adandisc discharge function enable 0 discharge function disabled 1 discharge function enabled adantmd1 adantmd0 specification of trigger mode 0 0 adtrg external trigger mode 0 1 inttaa2cc0 timer trigger mode 0 1 0 inttaa2cc1 timer trigger mode 1 1 1 prohibited
672 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (4) adans - adc channel specification register the adans register specifies the pin that inputs the analog voltage to be converted into a digital signal. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: ada0s fffff202h 7654 3 2 1 0 adans 0 0 0 adans4 adans3 adans2 adans1 adans0 adans[4:0] analog input to convert adandiag = 0 (without diagnostic function) adandiag = 1 (with diagnostic function) 4 3 2 1 0 select mode scan mode select mode scan mode 00000 ani0 ani100 ani0 ani100 avref ani0 ani100 - avref - avss 00001 ani1 ani101 ani0, ani1 ani100, ani101 avss ani0, ani1 ani100, ani101 - avref - avss 00010 ani2 ani102 ani0 to ani2 ani100, ani102 prohibited ani0 to ani2 ani100, ani102 - avref - avss 00011 ani3 ani103 ani0 to ani3 ani100, ani103 prohibited ani0 to ani3 ani100, ani103 - avref - avss 00100 ani4 ani104 ani0 to ani4 ani100, ani104 prohibited ani0 to ani4 ani100, ani104 - avref - avss 00101 ani5 ani105 ani0 to ani5 ani100, ani105 prohibited ani0 to ani5 ani100, ani105 - avref - avss 00110 ani6 ani106 ani0 to ani6 ani100, ani106 prohibited ani0 to ani6 ani100, ani106 - avref - avss 00111 ani7 ani107 ani0 to ani7 ani100, ani107 prohibited ani0 to ani7 ani100, ani107 - avref - avss 01000 ani8 ani108 ani0 to ani8 ani100, ani108 prohibited ani0 to ani8 ani100, ani108 - avref - avss 01001 ani9 ani109 ani0 to ani9 ani100, ani109 prohibited ani0 to ani9 ani100, ani109 - avref - avss 01010 ani10 ani110 ani0 to ani10 ani100, ani110 prohibited ani0 to ani10 ani100, ani110 - avref - avss 01011 ani11 ani111 ani0 to ani11 ani100, ani111 prohibited ani0 to ani11 ani100, ani111 - avref - avss 01100 ani12 ani112 ani0 to ani12 ani100, ani112 prohibited ani0 to ani12 ani100, ani112 - avref - avss 01101 ani13 ani113 ani0 to ani13 ani100, ani113 prohibited ani0 to ani13 ani100, ani113 - avref - avss 01110 ani14 ani114 ani0 to ani14 ani100, ani114 prohibited ani0 to ani14 ani100, ani114 - avref - avss 01111 ani15 ani115 ani0 to ani15 ani100, ani115 prohibited ani0 to ani15 ani100, ani115 - avref - avss
673 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 10000 ani16 ani0 to ani16 prohibited ani0 to ani16 - avref- avss 10001 ani17 ani0 to ani17 prohibited ani0 to ani17 - avref- avss 10010 ani18 ani0 to ani18 prohibited ani0 to ani18 - avref- avss 10011 ani19 ani0 to ani19 prohibited ani0 to ani19 - avref- avss 10100 ani20 ani0 to ani20 prohibited ani0 to ani20 - avref- avss 10101 ani21 ani0 to ani21 prohibited ani0 to ani21 - avref- avss 10110 ani22 ani0 to ani22 prohibited ani0 to ani22 - avref- avss 10111 ani23 ani0 to ani23 prohibited ani0 to ani23 - avref- avss other than above setting prohibited a a) when the channel in which an analog input does not exist is set, a conversion result becomes undefined. adans[4:0] analog input to convert adandiag = 0 (without diagnostic function) adandiag = 1 (with diagnostic function) 4 3 2 1 0 select mode scan mode select mode scan mode
674 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (5) adancrm, adancrmh - adc conversion result registers the adancrm and adancrmh registers store the a/d conversion results. these registers are read-only, in 16-bit or 8-bit units. however, specify the adancrm register for 16-bit access and the adancrmh register for 8-bit access. the 10 bits of the conversion result are read from the higher 10 bits of the adancrm register, and 0 is read from the lower 6 bits. the higher 8 bits of the conversion result are read from the adancrmh register. caution when writing to the adanm0-adanm2, adans, adanpfm and the adanpft register the contents of the adancrm registers might become undefined. therefore, after the conversion operation ends read the conversion result before writing to any of the above registers. moreover, when external/timer trigger is used, the content of the adancrm register must be read before the following external/timer trigger is accepted. after reset: undefined r address: ada0cr0 fffff210h, ada0cr1 fffff212h, ada0cr2 fffff214h, ada0cr3 fffff216h, ada0cr4 fffff218h, ada0cr5 fffff21ah, ada0cr6 fffff21ch, ada0cr7 fffff21eh, ada0cr8 fffff220h, ada0cr9 fffff222h, ada0cr10 fffff224h, ada0cr11 fffff226h, ada0cr12 fffff228h, ada0cr13 fffff22ah, ada0cr14 fffff22ch, ada0cr15 fffff22eh, ada0cr16 fffff230h, ada0cr17 fffff232h, ada0cr18 fffff234h, ada0cr19 fffff236h, ada0cr20 fffff238h, ada0cr21 fffff23ah, ada0cr22 fffff23ch, ada0cr23 fffff23eh 1514131211109876543210 adancrmad9ad8ad7ad6ad5ad4ad3ad2ad1ad0000000 after reset: undefined r address: ada0cr0h fffff211h, ada0cr1h fffff213h, ada0cr2h fffff215h, ada0cr3h fffff217h, ada0cr4h fffff219h, ada0cr5h fffff21bh, ada0cr6h fffff21dh, ada0cr7h fffff21fh, ada0cr8h fffff221h, ada0cr9h fffff223h, ada0cr10h fffff225h, ada0cr11h fffff227h, ada0cr12h fffff229h, ada0cr13h fffff22bh, ada0cr14h fffff22dh, ada0cr15h fffff22fh, ada0cr16h fffff231h, ada0cr17h fffff233h, ada0cr18h fffff235h, ada0cr19h fffff237h, ada0cr20h fffff239h, ada0cr21h fffff23bh, ada0cr22h fffff23dh, ada0cr23h fffff23fh 7 6543210 adancrmh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2
675 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 the relationship between the analog voltage input to the analog input pins aninmm and the a/d conversion result (of a/d conversion result register n adancrm is as follows: or int( ): function that returns the integer of the value in ( ) v in : analog input voltage at ainn pin av ref :av ref0 pin voltage adancrm: value of a/d conversion result register n (adancrm) figure 19-2 shows the relationship between the analog input voltage and the a/d conversion results. figure 19-2 relationship between analog input voltage and a/d conversion results adncrm int v in av ref ----------------- - 1024 ? 0,5 + () = adancrm 0,5 ? () av ref 1024 ------------------ ? v in adancrm 0,5 + () av ref 1024 ----------------- - ? < 1,023 1,022 1,021 3 2 1 0 input voltage/av ref 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion result adancrm s ar ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h
676 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (6) adancrdd, adancrddh - avref a/d conversion diagnostic registers the adancrdd and adancrddh registers store the result of the avref conversion if the adc diagnostic function is enabled (adanm2.adandiag = 1). these registers are read-only, in 16-bit or 8-bit units. however, specify the adancrdd register for 16-bit access and the adancrddh register for 8-bit access. the 10 bits of the conversion result are read from the higher 10 bits of the adancrdd register, and 0 is read from the lower 6 bits. the higher 8 bits of the conversion result are read from the adancrddh register. caution since a/d conversion accuracy is influenced of use conditions, the result does not necessarily become all 1 (adancrdd = ffc0h) when converting avref. after reset: 00h r address: ada0crdd fffff20ch 1514131211109876543210 adancrddad9ad8ad7ad6ad5ad4ad3ad2ad1ad0000000 after reset: 00h r address: ada0crddh fffff20ch ada1crddh fffff24dh 7 6543210 adancrddh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2
677 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (7) adancrss, adancrssh - avss a/d conversion diagnostic registers the adancrss and adancrssh registers store the result of the avss conversion if the adc diagnostic function is enabled (adanm2.adandiag = 1). these registers are read-only, in 16-bit or 8-bit units. however, specify the adancrss register for 16-bit access and the adancrssh register for 8-bit access. the 10 bits of the conversion result are read from the higher 10 bits of the adancrss register, and 0 is read from the lower 6 bits. the higher 8 bits of the conversion result are read from the adancrssh register. caution since a/d conversion accuracy is influenced of use conditions, the result does not necessarily become all 0 (adancrss = 003fh) when converting avss. after reset: ffffh r address: ada0crss fffff20eh 1514131211109876543210 adancrssad9ad8ad7ad6ad5ad4ad3ad2ad1ad0111111 after reset: ffh r address: ada0crssh fffff20fh 7 6543210 adancrssh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2
678 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (8) adanpfm - adc power-fail compare mode register the adanpfm register is an 8-bit register that sets the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution 1. in the select mode, the 8-bit data set to the adanpft register is compared with the value of the adancrmh register specified by the adans register. if the result matches the condition specified by the adanpfc bit, the conversion result is stored in the adancrm register and the intad signal is generated. if it does not match, however, the interrupt signal is not generated. 2. in the scan mode, the 8-bit data set to the adanpft register is compared with the contents of the adancr0h register. if the result matches the condition specified by the adanpfc bit, the conversion result is stored in the adancr0 register and the intad signal is generated. if it does not match, however, the intad signal is not generated. regardless of the comparison result, the scan operation is continued and the conversion result is stored in the adancrm register until the scan operation is completed. however, the intad signal is not generated after the scan operation has been completed. after reset: 00h r/w address: ada0pfm fffff204h 76543210 adanpfm adanpfe adanpfc0 0 0 0 0 0 0 adanpfe power-fail compare enable/disable 0 power-fail compare disabled 1 power-fail compare enabled adanpfc power-fail compare mode 0 generates interrupt request intad if adancrmh adanpft 1 generates interrupt request intad if adancrmh < adanpft
679 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (9) adanpft - adc power-fail compare threshold value register the adanpft register sets the compare value in the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: ada0pft fffff205h 76543210 adanpft adanpft7 adanpft6 adanpft5 adanpft4 adanpft3 adanpft2 adanpft1 adanpft0
680 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 19.4 operation 19.4.1 basic operation 1. set the operation mode, trigger mode, and conversion time for executing a/d conversion by using the adanm0, adanm1, adanm2, and adans registers. set the adanps bit of the adanm0 register to supply power to the analog circuitry of the adc. do not enable ad conversion before the adc stabilization time is elapsed. for the stabilization time refer to the electrical target specification. when the adance bit of the adanm0 register is set, conversion is started in the software trigger mode and the a/d converter waits for a trigger in the external or timer trigger mode. 2. when a/d conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. 3. when the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and holds the input analog voltage until a/d conversion is complete. 4. set bit 9 of the successive approximation register (sar). the tap selector selects (1/2) av ref as the voltage tap of the series resistor string. 5. the voltage difference between the voltage of the series resistor string and the analog input voltage is compared by the voltage comparator. if the analog input voltage is higher than (1/2) av ref , the msb of the sar register remains set. if it is lower than (1/2) av ref , the msb is reset. 6. next, bit 8 of the sar register is automatically set and the next comparison is started. depending on the value of bit 9, to which a result has been already set, the voltage tap of the series resistor string is selected as follows: ?bit 9 = 1: (3/4) av ref ?bit 9 = 0: (1/4) av ref this voltage tap and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. analog input voltage voltage tap: bit 8 = 1 analog input voltage voltage tap: bit 8 = 0 7. this comparison is continued to bit 0 of the sar register. 8. when comparison of the 10 bits is complete, the valid digital result is stored in the sar register, which is then transferred to and stored in the adancrm register. at the same time, an a/d conversion end interrupt request signal (intad) is generated.
681 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 figure 19-3 a/d converter basic operation 19.4.2 trigger mode the timing of starting the conversion operation is specified by setting a trigger mode. the trigger mode includes a software trigger mode and hardware trigger modes. the hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. the adantmd bit of the adanm0 register is used to set the trigger mode. in timer trigger mode set adanm2.adantmd[1:0] = 01. (1) software trigger mode when the adance bit of the adanm0 register is set to 1, the signal of the analog input pin aninmm specified by the adans register is converted. when conversion is complete, the result is stored in the adancrm register. at the same time, the a/d conversion end interrupt request signal (intad) is generated. if the operation mode specified by the adanmd1 and adanmd0 bits of the adanm0 register is the continuous select/scan mode, the next conversion is started, unless the adance bit is cleared to 0 after completion of the first conversion. when conversion is started, the adanef bit is set to 1 (indicating that conversion is in progress). if the adanm0, adanm2, adans, adanpfm, or adanpft register is written during conversion, the conversion is aborted and started again from the beginning. s ar adancrm intad intad1 conversion time s ampling time s ampling a/d conversion undefined conversion result conversion result a/d converter operation
682 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (2) external trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani23) specified by the adans register is started when an external trigger is input (to the adtrg pin). which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the adanets1 and adanets0 bits of the adanm0 register. when the adance bit of the adanm0 register set to 1, the a/d converter waits for the trigger, and starts conversion after the external trigger has been input. when conversion is completed, the result of conversion is stored in the adancrm register. at the same time, the a/d conversion end interrupt request signal (intad) is generated, and the a/d converter waits for the trigger again. when conversion is started, the adanef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the adanef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. if the adanm0, adanm2, adans, adanpfm, or adanpft register is written during the conversion operation, the conversion is not aborted, and the a/d converter waits for the trigger again. (3) timer trigger mode in this mode, converting the signal of the analog input pin aninmm, specified by the adans register, is started by any of the timer output signals inttaa2cc0 or inttaa2cc1. the timer output signal is selected by the adantmd1 and adantmd0 bits of the adanm2 register, and conversion is started at the rising edge of the timer output signal. when the adance bit of the adanm0 register is set to 1, the a/d converter waits for a trigger, and starts conversion when the rising edge of the timer output signal is input. when conversion is completed, the result of the conversion is stored in the adancrm register. at the same time, the a/d conversion end interrupt request signal (intad) is generated, and the a/d converter waits for the trigger again. when conversion is started, the adanef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the adanef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. if the adanm0, adanm2, adans, adanpfm, or adanpft register is written during conversion, the conversion is stopped and the a/d converter waits for the trigger again.
683 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 19.4.3 operation modes four operation modes are available as the modes in which to set the aninmm pins: continuous select mode, continuous scan mode, one-shot select mode and one-shot scan mode.. the operation mode is selected by the adanmd1 and adanmd0 bits of the adanm0 register. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the adans register is continuously converted into a digital value. the conversion result is stored in the adancrm register corresponding to the analog input pin. in this mode, an analog input pin corresponds to an adancrm register on a one-to-one basis. each time a/d conversion is completed, the a/d conversion end interrupt request signal (intad) is generated. after completion of conversion, the next conversion is started, unless the adance bit of the adanm0 register is cleared to 0. figure 19-4 timing example of continuous select mode operation (ada0s = 01h) (2) continuous scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the adans register, and their values are converted into digital values. the result of each conversion is stored in the adancrm register corresponding to the analog input pin. when conversion of the analog input pin specified by the adans register is complete, the a/d conversion end interrupt request signal (intad) is generated, and a/d conversion is started again from the ani0 pin, unless the adance bit of the adanm0 register is cleared to 0. ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) ada0cr1 intad intad1 conversion start set ada0m0.ada0ce = 1 data 6 (ani1)
684 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 figure 19-5 timing example of continuous scan mode operation (ada0s register = 03h) a /d conversion data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 ( b ) b l o c k d i ag r a m a/d converter ada0crn registers analog input pin ani0 ani1 ani2 ani3 ani4 ani5 anim ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0crm . . . . . . . (a) timing example
685 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (3) one-shot select mode in this mode, the voltage on the analog input pin specified by the ada0s register is converted into a digital value only once. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin and an ada0crn register correspond on a one-to-one basis. when a/d conversion has been completed once, the intad signal is generated. the a/d conversion operation is stopped after it has been completed. figure 19-6 timing example of one-shot select mode operation (ada0s register = 01h)
686 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (4) one-shot scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the adans register, and their values are converted into digital values. the result of each conversion is stored in the adancrm register corresponding to the analog input pin. when conversion of the analog input pin specified by the adans register is complete, the a/d conversion end interrupt request signal (intad) is generated, and a/d conversion is stopped.(n = 0-23). figure 19-7 timing example of one-shot scan mode operation (ada0s register = 03h) ( a ) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) ada0crn intad conversion start set ada0ce bit = 1 transformation completion ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 anim ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 . . . . . . . ada0crm ( ani0) (ani1) ( ani2) data 1 data 2 data 3 data 2 (ani1) data 3 (ani2) data 1 (ani0)
687 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (5) diagnostic mode when activating the diagnostic mode (adadiag bit of adanm2 register is set) the voltage at the avref pin and the avss pin are sampled after conversion of the specified aninm range is finished. the resulting values can be found in the adancrdd, adancrddh, adancrss and adancrssh registers. since ad conversion accuracy is influenced of use conditions, the result does not necessarily become all 1 when converting avref. since ad conversion accuracy is influenced of use conditions, the result does not necessarily become all 0 when converting avss. (6) discharge mode when activating the discharge mode (adandisc bit of adanm2 register is set) the internal capacitors of the sample and hold circuit are discharged prior to every conversion. additional 4 clocks must therefore be added to every conversion.
688 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 19.4.4 power-fail compare mode the a/d conversion end interrupt request signal (intad) can be controlled as follows by the adanpfm and adanpft registers.  when the adanpfe bit = 0, the intad signal is generated each time conversion is completed (normal use of the a/d converter).  when the adanpfe bit = 1 and when the adanpfc bit = 0, the value of the adancrmh register is compared with the value of the adanpft register when conversion is completed, and the intad signal is generated only if adancr0h adanpft.  when the adanpfe bit = 1 and when the adanpfc bit = 1, the value of the adancrmh register is compared with the value of the adanpft register when conversion is completed, and the intad signal is generated only if adancr0h < adanpft. in the power-fail compare mode, four modes are available as modes in which to set the aninm pins: continuous select mode and continuous scan mode, one-shot select mode and one-shot scan mode. (1) continuous select mode in this mode, the result of converting the voltage of the analog input pin specified by the adans register is compared with the set value of the adanpft register. if the result of power-fail comparison matches the condition set by the adanpfc bit, the conversion result is stored in the adancrm register, and the intad signal is generated. if it does not match, the conversion result is stored in the adancrm register, and the intad signal is not generated. after completion of the first conversion, the next conversion is started, unless the adance bit of the adanm0 register is cleared to 0. figure 19-8 timing example of continuous select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 ( ani1) data 7 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 2 ( ani1) data 3 ( ani1) data 4 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start s et ada0ce bit = 1 ada0pft unmatch ada0pft unmatch ada0pft match ada0pft match ada0pft match conversion start s et ada0ce bit = 1
689 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (2) continuous scan mode in this mode, the results of converting the voltages of the analog input pins sequentially selected from the ani0 pin to the pin specified by the adans register are stored, and the set value of the adancr0h register of channel 0 is compared with the value of the adanpft register. if the result of power-fail comparison matches the condition set by the adanpfc bit of the adanpfm register, the conversion result is stored in the adancr0 register, and the intad signal is generated. if it does not match, the conversion result is stored in the adancr0 register, and the intad signal is not generated. after the result of the first conversion has been stored in the adancr0 register, the results of sequentially converting the voltages on the analog input pins up to the pin specified by the adans register are continuously stored. after completion of conversion, the next conversion is started from the ani0 pin again, unless the adance bit of the adanm0 register is cleared to 0.
690 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 figure 19-9 timing example of continuous scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a /d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) data 7 ( ani2) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ada0pft unmatch ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn registers analog input pin ani0 ani1 ani2 ani3 ani4 ani5 anim ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0crm . . . . . . .
691 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (3) one-shot select mode in this mode, the result of converting the voltage of the analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0crn register, and the intad signal is not generated. conversion is stopped after it has been completed. figure 19-10 timing example of one-shot select mode operation (when power-fail comparison is made: ada0s register = 01h)
692 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (4) one-shot scan mode in this mode, the results of converting the voltages of the analog input pins sequentially selected from the ani0 pin to the pin specified by the adans register are stored, and the set value of the adancr0h register of channel 0 is compared with the value of the adanpft register. if the result of power-fail comparison matches the condition set by the adanpfc bit of the adanpfm register, the conversion result is stored in the adancr0 register, and the intad signal is generated. if it does not match, the conversion result is stored in the adancr0 register, and the intad signal is not generated. after the result of the first conversion has been stored in the adancr0 register, the results of sequentially converting the voltages on the analog input pins up to the pin specified by the adans register are continuously stored. after completion of conversion, a/d conversion is stopped. the 1st conversion result after a/d conversion has been ignored, because it is not good.
693 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 figure 19-11 timing example of one-shot scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 conversion completion (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 anim ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0crm . . . . . . .
694 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 19.5 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consumption can be reduced by clearing the adance bit and the adanps bit of the adanm0 register to 0. (2) input range of aninm pins input the voltage within the specified range to the aninm pins. if a voltage equal to or higher than av ref or equal to or lower than av ss (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined and the conversion value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit resolution, the aninm pins must be effectively protected from noise. the influence of noise increases as the output impedance of the analog input source becomes higher. to lower the noise, connecting an external capacitor as shown in figure 19-12 is recommended. figure 19-12 processing of analog input pin (4) alternate i/o the analog input pins aninm function alternately as port pins. changing the digital input/output function (pmcn and pmn; n = 2, 7 or 12) or changing the level of one or more output ports (pnm; n = 2, 7 or 12; m = 0 up to 15) while ada0ce bit = 1 could degrade the conversion accuracy. for the output port the potential degradation increases with the driven total output current. also the conversion resolution may drop if the output current fluctuates due to the effect of the external circuit connected to the port pins. av ref v dd v ss av ss c = 100 to 1,000 pf ani0 to anin
695 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the adans register are changed. if the analog input pin is changed during a/d conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the adans register is rewritten. if the adif flag is read immediately after the adans register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, clear the adif flag before resuming conversion. figure 19-13 generation timing of a/d conversion end interrupt request (6) reading adancrm register when the adanm0 to adanm2 or adans register is written, the contents of the adancrm register may be undefined. read the conversion result after completion of conversion and before writing to the adanm0 to adanm2 and adans registers. the correct conversion result may not be read at a timing different from the above. adan s rewrite (anink conversion start) a/d conversion adancrm intadn adan s rewrite (aninl conversion start) anink anink aninl aninl anink anink aninl aninl adif is set, but aninl conversion does not end
696 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 19.6 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. for details refer to the electrical target specification (1) resolution the minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref ? 0)/100 = av ref /100 when the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics table does not include the quantization error.
697 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 figure 19-14 overall error (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. figure 19-15 quantization error ideal line overall error 1 ...... 1 0 ...... 0 0av ref analog input digital output quantization error 1 ...... 1 0 ...... 0 0av ref analog input digital output 1/2 l s b 1/2 l s b
698 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (4) zero-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 19-16 zero-scale error av ref analog input (l s b) digital output (lower 3 bits) ideal line 111 ? 10 1 2 3 100 011 010 001 000 zero-scale error
699 a/d converter (adc) chapter 19 user?s manual u18743ee1v2um00 (5) full-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1?110 to 0?111 (full scale - 3/2 lsb). figure 19-17 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a specific code is output. figure 19-18 differential linearity error av ref analog input (l s b) digital output (lower 3 bits) 111 av ref ? 3 0 av ref ? 2av ref ? 1 110 101 100 000 full-scale error ideal width of 1 l s b differential linearity error 1 ...... 1 0 ...... 0 av ref analog input digital output
700 chapter 19 a/d converter (adc) user?s manual u18743ee1v2um00 (7) integral linearity error this error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. it indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 19-19 integral linearity error (8) conversion time this is the time required to obtain a digital output after an analog input voltage has been assigned. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 19-20 sampling time 1 ...... 1 0 ...... 0 0av ref analog input digital output ideal line integral linearity error s ampling time conversion time
701 user?s manual u18743ee1v2um00 chapter 20 power supply scheme the microcontroller has general power supply pins for its core, internal memory and peripherals. these pins are connected to internal voltage regulators. the microcontroller also has dedicated power supply pins for certain i/o modules. these pins provide the power for the i/o operations. 20.1 overview the following table gives the naming convention of the pins: the following pins belong to the power supply scheme: note for electrical characteristics refer to the electrical target specification. table 20-1 naming convention of power supply pins dedicated function v dd or v ss cpu core, internal memory and peripherals  vdd: voltage drain drain  vss: voltage for substrate and source a a/d converter, low-voltage detector b, e standard i/o buffer table 20-2 power supply pins power supply pins v850es/fe3-l v850es/ff3-l v850es/fg3-l avref0 / avss a/d converter 0 / low-voltage detector vdd / vss cpu core (with voltage regulator) evdd / evss - numbered i/o port buffers a - alpha i/o port buffers a a) numbered ports: port groups 0 to 9 numbered i/o port buffers a bvdd / bvss - alpha i/o port buffers b b) alpha ports: port groups cm, cs, ct, dl
702 chapter 20 power supply scheme user?s manual u18743ee1v2um00 20.2 description following figures give an overview of the allocation of power supply pins on the chip. note the diagrams do not show the exact pin location. (1) v850es/fe3-l, v850es/ff3-l power supply pins assignment figure 20-1 v850es/fe3-l, v850es/ff3-l power supply pins assignment
703 power supply scheme chapter 20 user?s manual u18743ee1v2um00 (2) v850es/fg3-l power supply pins assignment figure 20-2 v850es/fg3-l ower supply pins assignment 20.3 voltage regulators the on-chip voltage regulators generate the voltages for the internal circuitry, refer to figure 20-1 , figure 20-2 . the regulators operate per default in all operation modes (normal operation, halt, idle1, idle2, stop, sub-clock, and during reset). note to stabilize the output voltage of the regulator, connect a capacitor to the regc pin. refer to the electrical target specification. internal circ uit main and sub oscillators evdd i/o buffer bvdd i/o buffer avref0 a/d converter regulator vdd regc flash memory evdd bidirectional level shifter bvdd
704 chapter 20 power supply scheme user?s manual u18743ee1v2um00
705 user?s manual u18743ee1v2um00 chapter 21 reset several reset functions are provided in order to initialize hardware and registers. 21.1 overview features summary an internal system reset sysres can be generated by the following sources:  external reset signal reset  power-on-clear (respoc)  watchdog timer 2 (reswdt2)  clock monitor (resclm)  low-voltage detector (reslvi) 21.1.1 general reset performance the following figure shows the signals involved in the reset function. figure 21-1 reset function signal diagram all resets are applied asynchronously. that means, resets are not synchronized to any internal clock. this ensures that the microcontroller can be kept in reset state even if all internal clocks fail to operate. re s lvi re s clm re s wdt2 re s f npb reset logic circuit s y s re s re s et re s f = 00 h re s poc lvirf clmrf wdt2 rf 0 000 0
706 chapter 21 reset user?s manual u18743ee1v2um00 (1) hardware status with each reset function the hardware is initialized. when the reset status is released, program execution is started. the following table describes the status of the clocks and on-chip modules during reset and after reset release. table 21-1 hardware status during and after reset item during reset after reset general clock supplies refer to ?start conditions? on page 184 on-chip peripheral functions watch timer wt operating on f xt watchdog timer wdt2 stopped starts operation based on f rl , after internal oscillator stable. all others stopped operable based on f rh , after internal oscillator stable. cpu initialized program execution starts based on f rh , after internal oscillator stable. i/o pins (port/alternative function pins) all pins are in input port mode a . see chapter ?pin functions? on page 31 for a description. a) the status of the n-wire debug interface pins drst (p05), ddi (p52), ddo (p53), dck (p54), dms (p55) after reset depends on the reset value of the ocdm register, and therefore on the reset source. see chapter ?pin functions? on page 31 for details.
707 reset chapter 21 user?s manual u18743ee1v2um00 (2) register status with each reset function the registers of the cpu, internal ram, and on-chip peripheral i/os are initialized. after a reset, make sure to set the registers to the values needed within your program. internal ram data becomes undefined after power-on reset, or if ram data access by the cpu and a reset input conflict (data is lost). addtionally the following resources are used by the internal firmware executed after a reset::  the first 150 bytes and the last 100 bytes of the available ram area are undefined.  program status word (psw) is undefined, but interrupts are disabled table 21-2 initial values of cpu and internal ram after reset on-chip hardware register name initial value after reset cpu program registers general-purpose register (r0) 0000 0000 h general-purpose registers (r1 to r31) undefined program counter (pc) reset vector programmed to the code flash memory extra area a system registers status save registers during interrupt (eipc, eipsw) undefined status save registers during non- maskable interrupt (nmi) (fepc, fepsw) undefined interrupt cause register (ecr) 0000 0000 h program status word (psw) 0000 0020 h status save registers during callt execution (ctpc, ctpsw) undefined status save registers during exception/ debug trap (dbpc, dbpsw) undefined callt base pointer (ctbp) undefined internal ram undefined peripherals macro internal registers the reset values of the various registers are given in the chapters of the peripheral functions a) after reset, the internal firmware is executed. when execution of the firmware is finished, it performs a pro- gram branch according to the user defined reset vector . the reset vector is stored in the extra flash area.
708 chapter 21 reset user?s manual u18743ee1v2um00 21.1.2 reset at power-on the power-on-clear circuit (poc) permanently compares the power supply voltage v dd with an internal reference voltage (v ip ). it ensures that the microcontroller only operates as long as the power supply exceeds a well- defined limit. when the power supply voltage falls below the internal reference voltage (v dd 709 reset chapter 21 user?s manual u18743ee1v2um00 figure 21-3 on page 709 outlines the start up of the cpu system after power- on-clear. figure 21-3 cpu system start up after power-on-clear pll output f pllo reset internal reset cpu system clock f vbclk 8 mhz internal oscillator f rh mainosc f x vdd stop stop stop mainosc start possible pll enable possible cpu system f rh operation f rh setup time analog delay (reset release)
710 chapter 21 reset user?s manual u18743ee1v2um00 21.1.3 external reset reset is performed when a low level signal is applied to the reset pin. the reset status is released when the signal applied to the reset pin changes from low to high. after the external reset is released, the resf register is cleared and the internal system reset signal sysres is generated. the reset pin incorporates a noise eliminator, which is applied to the reset signal reset . to prevent erroneous external reset due to noise, it uses an analog filter. even if no clock is active in the controller the external reset can keep the controller in reset state. the following figure shows the timing when an external reset is performed. it explains the effect of the noise eliminator. the noise eliminator uses the analog delay to prevent the generation of an external reset due to noise. the analog delay is caused by the analog input filter. the filter regards pulses up to a certain width as noise and suppresses them. for the minimum reset pulse width refer to the electrical target specification. figure 21-4 timing for external reset stop stop stop mainosc start possible pll enable possible cpu system f rh operation f rh setup time analog delay (reset release) analog delay (noise removal) analog delay (reset detection) analog delay (noise removal) pll output f pllo reset internal reset cpu system clock f vbclk 8 mhz internal oscillator f rh mainosc f x cpu system f pllo operation
711 reset chapter 21 user?s manual u18743ee1v2um00 21.1.4 reset by watchdog timer 2 the watchdog timer can be configured to generate a reset if the watchdog time overflows. after watchdog reset, the resf.wdt2rf bit is set. the system reset signal sysres is generated. after watchdog timer overflow, the reset status lasts for a specific time. then the reset status is automatically released. 21.1.5 reset by clock monitor the clock monitor generates a reset when the main oscillator fails. after a clock monitor reset, the corresponding bit resf.clmrf is set. the system reset signal sysres is generated. after a clock monitor reset, the reset status lasts for a specific time. then the reset status is automatically released. 21.1.6 reset by low-voltage detector the low-voltage detector can be configured to generate the reset reslvi if the voltage supply v dd falls below the reference voltage v lv i . reslvi sets the bit resf.lvirf and the system reset sysres is generated.
712 chapter 21 reset user?s manual u18743ee1v2um00 21.2 reset registers the reset functions are controlled and operated by means of the following registers: (1) resf - reset source flag register the 8-bit resf register contains information about which type of resets occurred since the last power-on-clear or external reset. the resf register is a special register that can be written only by specific sequences. each following reset condition sets the corresponding flag in the register. for example, if a power-on-clear reset is finished and then a watchdog timer reset occurs, the resf reads 0001 0000 b . access the register can be read/written in 8-bit units and 1-bit units. address ffff f888 h initial value power-on-clear reset and external reset sets this register to 00 h . note if clearing this register by writing and flag setting (occurrence of reset) conflict, flag setting takes precedence. table 21-3 reset function register overview register name shortcut address reset source flag register resf ffff f888 h 76543210 0 0 0 wdt2rf 0 0 clmrf lvirf r r r r/w r r r/w r/w table 21-4 resf register contents bit position bit name function 4 wdt2rf reset by watchdog timer 0: not generated. 1: generated. 1 clmrf reset by clock monitor 0: not generated. 1: generated. 0 lvirf reset by low-voltage detector 0: not generated. 1: generated.
713 user?s manual u18743ee1v2um00 chapter 22 low-voltage detector this chapter describes the low-voltage detector and the ram data rentention function. 22.1 functions the low-voltage detector (lvi) has the following functions.  compares the supply voltage (v dd ) with a reference voltage (v lv i ) and generates ? internal interrupt signals when v dd < v lv i or v dd > v lv i ? or internal reset signal when v dd < v lv i .  the level of the supply voltage to be detected can be changed by software (in two steps).  interrupt or reset signal can be selected by software.  can operate in stop mode.  operation can be stopped by software. if the low-voltage detector is used to generate a reset signal, bit 0 (lvirf) of the reset source flag register (resf) is set to 1 when the reset signal is generated. for details of resf, refer to ?reset? on page 705 . 22.2 configuration figure 22-1 shows the block diagram of the low-voltage detector.
714 chapter 22 low-voltage detector user?s manual u18743ee1v2um00 figure 22-1 block diagram of low-voltage detector 22.3 registers the low-voltage detector is controlled by the following registers.  low voltage detection register (lvim)  low voltage detection level selection register (lvis) (1) lvim - low voltage detection register this register is a special register and can be written only in a combination of specific sequences (refer to ?write protected registers? on page 155 ). the lvim register is used to enable or disable low voltage detection, and to set the operation mode of the low-voltage detector. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. lvis0 lvio n reference voltage source (v lvi ) v dd v dd internal bus n-ch low voltage detection level selection register (lvis) low voltage detection register (lvim) lvim d lvif intlvil intlvih internal reset signal r o t c e l e s low voltage detection level selector ? + after reset: 00h r/w address: fffff890h 76543210 lvimlvion00000lvimdlvif lv i on low voltage detection operation enable or disable 0 disable operation. 1 enable operation.
715 low-voltage detector chapter 22 user?s manual u18743ee1v2um00 caution 1. after setting the lvim.lvion bit to 1, wait for a specified time before checking the voltage using the lvim.lvif bit. the wait time is specified in the electrical target specification. 2. the lviif bit is valid only when the lvim.lvion = 1 and lvim.lvimd = 0. 3. the lvim.lvif bit is read-only. 4. be sure to clear bits 2 to 6 to 0. lv i md selection of operation mode of low voltage detection 0 generate interrupt request signal  intlvil when supply voltage v dd < reference voltage v lv i  intlvih when supply voltage v dd > reference voltage v lv i 1 generate internal reset signal lvires when supply voltage v dd < reference voltage v lv i lv i f low voltage detection flag 0 when  supply voltage v dd > reference voltage v lv i or  operation is disabled (lvim.lvion = 0) 1 supply voltage of power supply v dd < reference voltagev lv i
716 chapter 22 low-voltage detector user?s manual u18743ee1v2um00 (2) lvis - low voltage detection level selection register the lvis register is used to select the level of low voltage to be detected. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution 1. this register cannot be written until a reset request due to something other than low-voltage detection is generated after the lvim.lvion and lvim.lvimd bits are set to 1. 2. be sure to clear bits 7 to 1 to 0. after reset: 00h r/w address: fffff891h 76543210 lvis0000000lvis0 lv i s 0 detection level 0 4.0 v a a) refer to electrical target specification for the detailed specification. 1 3.7 v a
717 low-voltage detector chapter 22 user?s manual u18743ee1v2um00 (3) rams - internal ram data status register the rams register is a flag register that indicates that the supply voltage has dropped below a specific data retention voltage. if so, the contents of the ram may have changed and has to be considered as invalid. this register can be read or written in 8-bit or 1-bit units. writing to this register is protected by a special sequence of instructions. please refer to ?write protected registers? on page 155 for details. for the specification of the data rentention voltage, consult the electrical target specification. note this register is not influenced by any reset. refer to 22.4.4 on page 722 for further details concerning ram data retention. after reset: note r/w address: fffff892h 76543210 rams0000000ramf ramf internal ram data valid/invalid 0 supply voltage > data retention voltage, ram valid 1 supply voltage < data retention voltage, ram invalid
718 chapter 22 low-voltage detector user?s manual u18743ee1v2um00 (4) pemu1 - peripheral emulation register 1 when an in-circuit emulator is used, the operation of the ram retention flag (ramf bit: bit 0 of rams register) can be pseudo-controlled and emulated by manipulating this register on the debugger. this register can be read or written in 8-bit or 1-bit units. this register is valid only in the emulation mode. it is invalid in the normal mode. caution this bit is not automatically cleared. [usage] when an in-circuit emulator is used, pseudo emulation of ramf is realized by rewriting this register on the debugger. after reset: 00h r/w address: fffff9feh 76543 2 10 pemu100000 evaramin 00 evaramin pseudo specification of ram retention voltage detection signal 0 do not detect voltage lower than ram retention voltage. 1 detect voltage lower than ram retention voltage (set ramf flag). <1> cpu break (cpu operation stops.) <2> set the evaramin bit to 1 by using a register write command. by setting the evaramin bit to 1, the ramf bit is set to 1 on hardware (the internal ram data is invalid). <3> clear the evaramin bit to 0 by using a register write command again. unless this operation is performed (clearing the evaramin bit to 0), the ramf bit cannot be cleared to 0 by a cpu operation instruction. <4> run the cpu and resume emulation.
719 low-voltage detector chapter 22 user?s manual u18743ee1v2um00 22.4 operation depending on the setting of the lvimd bit, the interrupt signals (intlvil, intlvih) or an internal reset signal is generated. how to specify each operation is described below, together with timing charts. 22.4.1 reset generation from lvi (lvim.lvimd = 1) operation start 1. mask the interrupt of lvi. 2. select the voltage to be detected by using the lvis.lvis0 bit. 3. set the lvim.lvion bit to 1 (to enable operation). 4. insert sufficient wait time by software. see the electrical target specifica- tion for details. 5. by using the lvim.lvif bit, check if the supply voltage v dd > reference voltage v lv i . 6. set the lvim.lvimd bit to 1 (to generate an internal reset signal). caution if lvim.lvimd is set to 1, the contents of the lvim and lvis registers cannot be changed until a reset request other than lvi is generated.
720 chapter 22 low-voltage detector user?s manual u18743ee1v2um00 figure 22-2 operation timing of low-voltage detector (lvimd = 1) note during the period in which the supply voltage is the set low voltage or lower, the internal reset signal is retained (internal reset state). 22.4.2 interrupt generation from lvi (lvim.lvimd = 0) operation start 1. mask the interrupts of lvi. 2. select the voltage to be detected by using the lvis.lvis0 bit. 3. set the lvim.lvion bit to 1 (to enable operation). 4. insert sufficient wait time by software. see the electrical target specifica- tion for details. 5. by using the lvim.lvif bit, check if the supply voltage v dd > reference voltage v lv i . 6. clear the interrupt request flag of lvi. 7. unmask the interrupt of lvi. stop 1. mask the interrupt intlvih by setting lvihmk to 1. 2. clear the lvim.lvion bit to 0. 3. clear the interrupt request flag lvihif of intlvih lvim.lvion poc detection voltage (v poc ) lvi detection voltage (v lvi ) supply voltage (v dd ) time resf.lvirf d d : delay of analog circuitry d d d d respoc sysres reslvi d cleared by instruction
721 low-voltage detector chapter 22 user?s manual u18743ee1v2um00 figure 22-3 operation timing of low-voltage detector (lvim.lvimd = 0) note if vdd is fluctuating around the lvi detection level (vlvi), note that the judgment upon the intlvih or intlvil interrupt servicing may be incorrect. for example, if during intlvil interrupt servicing multiple intlvih/intlvil interrupts are generated due to the vdd fluctuation, it cannot be detected which interrupt was generated last. consequently, when intlvil interrupt servicing is performed at the last, even though vdd > vlvi, software detects vdd < vlvi by mistake. therefore when lvi detection interrupt servicing is performed, program the software code as to complete interrupt servicing before the next lvi detection is generated, at the same time as controlling the vdd, or monitoring the lvif flag. 22.4.3 disabling the lvi operation 1. mask the interrupt intlvih by setting lvihmk to 1. 2. disable the lvi operation by setting the lvim. lvon bit to 0. 3. clear the interrupt request flag lvihif of the intlvih register. intlvih intlvil lvim.lvion poc detection voltage (v poc ) lvi detection voltage (v lvi ) supply voltage (v dd ) time lvim.lvif respoc : delay of analog circuitry d d d d d d d sysres
722 chapter 22 low-voltage detector user?s manual u18743ee1v2um00 22.4.4 ram retention volt age detection operation the supply voltage and the data retention voltage are compared. when the supply voltage drops below the data retention voltage (including power on application), the rams.ramf bit is set. for the specification of the data retention voltage, consult the electrical target specification. the rams.ramf flag behaves as follows:  after power up the rams.ramf is set.  rams.ramf can only be reset by software.  rams.ramf remains 0 as long as the supply voltage exceeds the data retention voltage.  the rams.ramf flag is not influenced by any reset.  if the supply voltage drops below the power-on-clear reference voltage, but stays above the data retention voltage, a poc reset is applied, but rams.ramf remains 0. caution if an external reset is applied during a ram access of the cpu, parts of the ram content may have changed accidentally. such event does not set rams.ramf. figure 22-4 power-on-clear and ram data retention detection behaviour v dd poc detection voltage ram data detection voltage pocres rams.ramf power up clear by software ramf remains ?1? time
723 user?s manual u18743ee1v2um00 chapter 23 on-chip debug unit the microcontroller includes an on-chip debug unit. by connecting an n-wire emulator, on-chip debugging can be executed. 23.1 functional outline 23.1.1 debug functions (1) debug interface communication with the host machine is established by using the drst , dck, dms, ddi, and ddo signals via an on-chip debug emulator. the communication specifications of n-wire are used for the interface. (2) on-chip debug on-chip debugging can be executed by preparing wiring and a connector for on-chip debugging on the target system. an on-chip debug emulator is used to connect the host pc to the on-chip debug unit. (3) forced reset function the microcontroller can be forcibly reset. (4) break reset function the cpu can be started in the debug mode immediately after reset of the cpu is released. (5) forced break function execution of the user program can be forcibly aborted. (6) hardware break function two breakpoints for instruction and data access can be used. the instruction breakpoint can abort program execution at any address. the access breakpoint can abort program execution by data access to any address. (7) software break function up to four software breakpoints can be set in the internal code flash memory area. the number of software breakpoints that can be set in the ram area differs depending on the debugger to be used.
724 chapter 23 on-chip debug unit user?s manual u18743ee1v2um00 (8) debug monitor function a memory space for debugging that is different from the user memory space is used during debugging (background monitor mode). the user program can be executed starting from any address. while execution of the user program is aborted, the user resources (such as memory and i/o) can be read and written, and the user program can be downloaded. (9) mask function each of the following signals can be masked. that means these signals will not be effective during debugging. the correspondence between the maskable signals and on-chip debug emulator mask functions are shown below.  nmi0 mask function: nmi pin  nmi1 mask function: wdt2 interrupt  hold mask function: hldrq pin  reset mask function: reset pin, wdt2 reset, poc reset note , lvi reset, clock monitor reset  wait mask function: wait pin note available in products with the poc function (10) timer function the execution time of the user program can be measured. (11) peripheral macro operation/st op selection function during break depending on the debugger to be used, certain peripheral macros can be configured to continue or to stop operation upon a breakpoint hit.  functions that are always stopped during break ? watchdog timer 2 ? clock monitor  functions that can operate or be stopped during break (however, each function cannot be selected individually) ?all timers aa ?timer m ?watch timer  peripheral functions that continue operating during break (functions that cannot be stopped) ? peripheral functions other than above (12) function during power saving modes when the device is set into a power saving mode, debug operation is not possible. when exiting the power save mode, the on-chip debug unit continues operation. the n-wire interface is still accessible during power saving modes:  n-wire emulator can get status information from the on-chip debug unit.  stop mode can be released by the n-wire emulator.
725 on-chip debug unit chapter 23 user?s manual u18743ee1v2um00 (13) security function this microcontroller has a n-wire security function, that demands the user to input an id code upon start of the debugger. for further information concerning n-wire security, refer to ?data protection and security? on page 289 .
726 chapter 23 on-chip debug unit user?s manual u18743ee1v2um00 23.2 controlling the n-wire interface the n-wire interface pins drst , ddi, ddo, dck, dms are shared with port functions, see table 23-1. during debugging the respective device pins are forced into the n-wire interface mode and port functions are not available. note that n-wire debugging must be generally permitted by the security bit in the id code region (*0x0000 0079[bit7] = 1) of the code flash memory. an internal pull-down resistor - detachable by software - is provided at the drst pin to keep the n-wire interface in reset, if no debugger is connected. (1) ocdm - on-chip debug mode register the ocdm register is used to select the normal operation mode or on-chip debug mode. . writing to this register is protected by a special sequence of instructions. please refer to ?cpu system functions? on page 135 for details. access the register can be read or written in 8-bit and 1-bit units. address ffff f9fc h the reset value of ocdm.ocdm0 depends on the reset source. (2) power-on-clear respoc respoc (power-on-clear) reset sets ocdm.ocdm0 = 0, i.e. the pins are defined as port pins. the debugger can not communicate with the controller table 23-1 n-wire interface pins gpio n-wire function pin direction description p05 drst input n-wire rcu reset p52 ddi input n-wire debug data in p53 ddo output n-wire debug data out p54 dck input n-wire interface clock p55 dms input n-wire mode 76543210 bit name 0000000ocdm0 reset value00000000/1 a a) reset value depends on reset source (see below) ocdm0 0  pins used as port/alternative function pins  internal pull-down resistor detached from p05/drst 1  pins used as n-wire interface pins  internal pull-down resistor attached to p05/drst
727 on-chip debug unit chapter 23 user?s manual u18743ee1v2um00 and the n-wire debug circuit is disabled. the first cpu instructions after respoc can not be controlled by the debugger. the application software must set ocdm.ocdm0 = 1 in order to enable the n-wire interface and allow debugger access to the on-chip debug unit. during and after poc reset (ocdm.ocdm0 = 0) pins p05, p52?p55 are configured as input ports. (3) external reset external reset by the reset pin sets ocdm.ocdm0 = 1, i.e. the pins are defined as n-wire interface pins. if connected the debugger can communicate with the on-chip debug unit and take over cpu control. during and after reset the pins p05, p52?p55 are configured as follows: drst , ddi, dck, dms are inputs.  ddo is output, but in high impedance state as long as drst =0. (4) other resets resets from all other reset sources do not affect the pins p05, p52...p55. an internal pull-down resistor is provided for the pin p05/drst . during and after any reset the resistor is connected to p05/drst , ensuring that the n-wire interface is kept in reset state, if no debugger is connected. the internal pull-down resistor is connected by reset from any source and can be disconnected via ocdm.ocdm0. the drst signal depicts the n-wire interface reset signal. if drst = 0 the on-chip debug unit is kept in reset state and does not impact normal controller operation. drst is driven by the debugger, if one is connected. the debugger may start communication with the controller by setting drst =1. pin configuration in n-wire debug mode the configuration of the n-wire interface pins can not be changed by the pin configuration registers. the registers contents can be changed but will have no effect on the pin configuration.
728 chapter 23 on-chip debug unit user?s manual u18743ee1v2um00 23.3 n-wire enabling methods the current operation mode of the microcontroller is determined by ocdm.ocdm0 and drst : 23.3.1 starting normal operation after reset and respoc for ?normal operation? it has to be assured that the pins p05, p52?p55 are available as port pins after either reset event. therefore the software has to perform ocdm.ocdm0 = 0 to make the pins available as port pins after reset . note that after any external reset via the reset pin ocdm.ocdm0 is set to ?1? and the pins p05, p52?p55 are not available as application function pins until the software sets ocdm.ocdm0 = 0. figure 23-1 start without n-wire activation 23.3.2 starting debugger after reset and respoc the software has to set ocdm.ocdm0 = 1 for enabling the n-wire interface also upon a respoc event. afterwards the debugger may start to establish communication with the controller by setting the drst pin to high level and to take control over the cpu. on start of the debugger the entire controller is reset, i.e. all registers are set to their default states and the cpu's program counter is set to the reset vector 0000 0000 h . note after respoc the controller is operating without debugger control. thus all cpu instructions until the software performs ocdm.ocdm0 = 1 can not be debugged. to restart the user?s program from beginning under the debugger?s control apply an external reset after the debugger has started, as shown in table 23-2 normal operation and debug mode control drst ocdm.ocdm0 mode 0 x normal operation 1 0 1 on-chip debug power on respoc ocdm0 reset reset normal operation normal operation application software sets ocdm.ocdm0pc = 0 drst reset ?0? ?1?
729 on-chip debug unit chapter 23 user?s manual u18743ee1v2um00 figure 23-2 . this will cause the program to restart. however the status of the controller might not be the same as immediately after respoc, since the internal ram may have already been initialized, when the external reset is applied. figure 23-2 start with n-wire activation 23.3.3 n-wire activation by reset pin the n-wire interface can also be activated after power up by keeping reset active after respoc is released. by this ocdm.ocdm0 is set to ?1?, thus the n-wire interface is enabled. with this method the user's program does not need to perform ocdm.ocdm0 = 1. figure 23-3 n-wire activation by reset pin power on respoc ocdm0 reset normal operation debug application software sets ocdm.ocdm0 = 1 drst reset ?0? power on respoc ocdm0 reset debug normal operation debugger starts pc = 0 drst reset ?0? ?1? >= 2 s
730 chapter 23 on-chip debug unit user?s manual u18743ee1v2um00 23.4 connection to n-wire emulator to connect the n-wire emulator, a connector for emulator connection and a connection circuit must be mounted on the target system. as a connector example the kel connector is described in more detail. other connectors, like for instance mictor connector (product name: 2-767004-2, tyco electronics amp k.k.), are available as well. for the mechanical and electrical specification of these connectors refer to user?s manual of the emulator to be used. 23.4.1 kel connector kel connector product names:  8830e-026-170s (kel): straight type  8830e-026-170l (kel): right-angle type figure 23-4 connection to n-wire emulator (nec electronics ie-v850e1-cd-nw: n-wire card)
731 on-chip debug unit chapter 23 user?s manual u18743ee1v2um00 (1) pin configuration figure 23-5 shows the pin configuration of the connector for emulator connection (target system side), and table 23-3 on page 732 shows the pin functions. figure 23-5 pin configuration of connector for emulator connection (target system side) caution evaluate the dimensions of the connector when actually mounting the connector on the target board.
732 chapter 23 on-chip debug unit user?s manual u18743ee1v2um00 (2) pin functions the following table shows the pin functions of the connector for emulator connection (target system side). ?i/o? indicates the direction viewed from the device. caution 1. the connection of the pins not supported by the microcontroller is dependent upon the emulator to be used. 2. the pattern of the target board must satisfy the following conditions.  the pattern length must be 100 mm or less.  the clock signal must be shielded by gnd. table 23-3 pin functions of connector for emulator connection (target system side) pin no. pin name i/o pin function a1 (reserved 1) ? (connect to gnd) a2 (reserved 2) ? (connect to gnd) a3 (reserved 3) ? (connect to gnd) a4 (reserved 4) ? (connect to gnd) a5 (reserved 5) ? (connect to gnd) a6 (reserved 6) ? (connect to gnd) a7 ddi input data input for n-wire interface a8 dck input clock input for n-wire interface a9 dms input transfer mode select input for n-wire interface a10 ddo output data output for n-wire interface a11 drst input on-chip debug unit reset input a12 reset input reset input. (in a system that uses only poc reset and not pin reset, some emulators input an external reset signal as shown in figure 23-6 on page 733 to set the ocdm0 bit to 1.) a13 flmd0 input control signal for flash download (flash memory versions only) b1 gnd ? ? b2 gnd ? ? b3 gnd ? ? b4 gnd ? ? b5 gnd ? ? b6 gnd ? ? b7 gnd ? ? b8 gnd ? ? b9 gnd ? ? b10 gnd ? ? b11 (reserved 8) ? (connect to gnd) b12 (reserved 9) ? (connect to gnd) b13 v dd ? 5 v input (for monitoring power supply to target)
733 on-chip debug unit chapter 23 user?s manual u18743ee1v2um00 (3) example of recommended circuit an example of the recommended circuit of the connector for emulator connection (target system side) is shown below. figure 23-6 example of recommended emulator connection circuit note 1. the pattern length must be 100 mm or less. 2. shield the dck signal by enclosing it with gnd. 3. this pin is used to detect power to the target board. connect the voltage of the n-wire interface to this pin. 4. in a system that uses only poc reset and not pin reset, some emulators input an external reset signal as shown in figure 23-6 to set the ocdm.ocdm0 bit to 1. caution the n-wire emulator may not support a 5 v interface and may require a level shifter. refer to the user?s manual of the emulator to be used. v850 flmd0 (reserved 1) (reserved 2) (reserved 3) (reserved 4) (reserved 5) (reserved 6) ddi dck dms ddo drst flmd0 reset v dd note 3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd (reserved 8) (reserved 9) note 2 note 1 note 1 note 1 note 1 note 4 5 v 5 v a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a13 a12 b13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 ddi dck dms ddo drst kel connector 8830e-026-170s reset note 1
734 chapter 23 on-chip debug unit user?s manual u18743ee1v2um00 23.5 restrictions and cautions on on-chip debug function  do not mount a device that was used for debugging on a mass-produced product (this is because the code flash memory was rewritten during debugging and the number of rewrites of the code flash memory cannot be guaranteed).  if a reset signal (reset input from the target system or reset by an internal reset source) is input during run (program execution), the break function may malfunction.  even if reset is masked by using a mask function, the i/o buffer (port pin, etc.) is reset when a pin reset signal is input.  with a debugger that can set software breakpoints in the internal code flash memory, the breakpoints temporarily become invalid when pin reset or internal reset is effected. the breakpoints become valid again if a break such as a hardware break or forced break is executed. until then, no software break occurs. the reset signal input is masked during a break.  the poc reset operation cannot be emulated.  the on-chip debugging unit uses the exception vector address 60 h for software breakpoint (dbtrap, refer to ?interrupt controller (intc)? on page 221 ). thus the debugger takes over control when one of the following exceptions occur: ? debug trap (dbtrap) ? illegal op-code detection (ilgop) ? rom correction the debugger executes its own exception handler. therefore, the user's exception handler at address 60 h will not be executed.  when executing on-chip debugging, pin reset must be input to set the ocdm0 bit of the ocdm register to 1. for details, refer to 23.2?controlling the n-wire interface? on page 726.  when the break command is started in on-chip debug (ocd) mode and the application software accesses to the uartd/csib/can peripheral i/o registers, csib, uartd and can do not operate normally if on-chip debugging is restarted without executing reset. caution if the flash memory is programmed during a debug session and the options bytes have been changed, a target reset command has to be issued in order to make the new option byte settings effective.
735 user?s manual u18743ee1v2um00 chapter 24 differences fx3-l to fx3 the following table give a short overview of the main differences between the fx3-l series of devices and the fx3 series of devices. table 24-1 feature fx3-l fx3 operation speed 20 mhz 32mhz data flash not available 32kb dma not available 4 channels tab not available 1 channel (fe3, ff3) 2 channnels (fg3) can 1 channel 1 channel (fe3, ff3) 2 channels (fg3) sscg not available available
736 chapter 24 differences fx3-l to fx3 user?s manual u18743ee1v2um00
737 user?s manual u18743ee1v2um00 appendix a special function registers the following tables list all registers that are accessed via the npb (nec peripheral bus). the registers are called ?special function registers? (sfr). ta b l e a - 1 lists all can special function registers. the addresses are given as offsets to the programmable peripheral base address (refer to ?can module register and message buffer addresses? on page 553 . the tables list all registers and do not distinguish between the different derivatives. a.1 can registers the can registers are accessible via the programmable peripheral area. table a-1 can special function registers (1/2) address offset register name shortcut 1 8 16 32 0x000 can0 global control register c0gmctrl - - r/w - 0x002 can0 global clock selection register c0gmcs - r/w - - 0x006 can0 global automatic block transmission register c0gmabt - - r/w - 0x008 can0 global automatic block transmission delay register c0gmabtd -r/w- - 0x040 can0 module mask 1 register c0mask1l - - r/w - 0x042 c0mask1h - - r/w - 0x044 can0 module mask 2 register c0mask2l - - r/w - 0x046 c0mask2h - - r/w - 0x048 can0 module mask 3 register c0mask3l - - r/w - 0x04a c0mask3h - - r/w - 0x04c can0 module mask 4 register c0mask4l - - r/w - 0x04e c0mask4h - - r/w - 0x050 can0 module control register c0ctrl - - r/w - 0x052 can0 module last error code register c0lec - r/w - - 0x053 can0 module information register c0info - r - - 0x054 can0 module error counter register c0erc - - r - 0x056 can0 module interrupt enable register c0ie - - r/w - 0x058 can0 module interrupt status register c0ints - - r/w - 0x05a can0 module bit-rate prescaler register c0brp - r/w - - 0x05c can0 module bit-rate register c0btr - - r/w - 0x05e can0 module last in-pointer register c0lipt - r - - 0x060 can0 module receive history list register c0rgpt - - r/w - 0x062 can0 module last out-pointer register c0lopt - r - -
738 appendix a special function registers user?s manual u18743ee1v2um00 0x064 can0 module transmit history list register c0tgpt - - r/w - 0x066 can0 module time stamp register c0ts - - r/w - 0x100 to 0x4ef can0 message buffer registers, see table 18-20 on page 556 table a-1 can special function registers (2/2) address offset register name shortcut 1 8 16 32
739 special function registers appendix a user?s manual u18743ee1v2um00 a.2 other special function registers table a-2 other special function registers (1/9) address register name shortcut 1 8 16 32 0xfffff004 portdl pdl - - r/w - 0xfffff004 portdl low byte pdll r/w r/w - - 0xfffff005 portdl high byte pdlh r/w r/w - - 0xfffff008 portcs pcs r/w r/w - - 0xfffff00a portct pct r/w r/w - - 0xfffff00c portcm pcm r/w r/w - - 0xfffff024 portdl mode pmdl - - r/w - 0xfffff024 portdl mode low byte pmdll r/w r/w - - 0xfffff025 portdl mode high byte pmdlh r/w r/w - - 0xfffff028 portcs mode pmcs r/w r/w - - 0xfffff02a portct mode pmct r/w r/w - - 0xfffff02c portcm mode pmcm r/w r/w - - 0xfffff044 portdl mode control pmcdl - - r/w - 0xfffff044 portdl mode control low byte pmcdll r/w r/w - - 0xfffff045 portdl mode control high byte pmcdlh r/w r/w - - 0xfffff048 portcs mode control pmccs r/w r/w - - 0xfffff04a portct mode control pmcct r/w r/w - - 0xfffff04c portcm mode control pmccm r/w r/w - - 0xfffff064 peripheral i/o area select control register bpc - - r/w - 0xfffff06e system wait control register vswc r/w r/w - - 0xfffff100 interrupt mask control register 0 imr0 - - r/w - 0xfffff100 interrupt mask control register 0l imr0l r/w r/w - - 0xfffff101 interrupt mask control register 0h imr0h r/w r/w - - 0xfffff102 interrupt mask control register 1 imr1 - - r/w - 0xfffff102 interrupt mask control register 1l imr1l r/w r/w - - 0xfffff103 interrupt mask control register 1h imr1h r/w r/w - - 0xfffff104 interrupt mask control register 2 imr2 - - r/w - 0xfffff104 interrupt mask control register 2l imr2l r/w r/w - - 0xfffff105 interrupt mask control register 2h imr2h r/w r/w - - 0xfffff106 interrupt mask control register 3 imr3 - - r/w - 0xfffff106 interrupt mask control register 3l imr3l r/w r/w - - 0xfffff107 interrupt mask control register 3h imr3h r/w r/w - - 0xfffff108 interrupt mask control register 4 imr4 - - r/w - 0xfffff108 interrupt mask control register 4l imr4l r/w r/w - - 0xfffff109 interrupt mask control register 4h imr4h r/w r/w - - 0xfffff10a interrupt mask control register 5 imr5 - - r/w - 0xfffff10a interrupt mask control register 5l imr5l r/w r/w - - 0xfffff10b interrupt mask control register 5h imr5h r/w r/w - - 0xfffff10c interrupt mask control register 6 imr6 - - r/w -
740 appendix a special function registers user?s manual u18743ee1v2um00 0xfffff10c interrupt mask control register 6l imr6l r/w r/w - - 0xfffff10d interrupt mask control register 6h imr6h r/w r/w - - 0xfffff10e interrupt mask control register 7 imr7 - - r/w - 0xfffff10e interrupt mask control register 7l imr7l r/w r/w - - 0xfffff110 interrupt control register lvilic r/w r/w - - 0xfffff112 interrupt control register lvihic r/w r/w - - 0xfffff114 interrupt control register pic0 r/w r/w - - 0xfffff116 interrupt control register pic1 r/w r/w - - 0xfffff118 interrupt control register pic2 r/w r/w - - 0xfffff11a interrupt control register pic3 r/w r/w - - 0xfffff11c interrupt control register pic4 r/w r/w - - 0xfffff11e interrupt control register pic5 r/w r/w - - 0xfffff120 interrupt control register pic6 r/w r/w - - 0xfffff122 interrupt control register pic7 r/w r/w - - 0xfffff12e interrupt control register taa0ovic r/w r/w - - 0xfffff130 interrupt control register taa0ccic0 r/w r/w - - 0xfffff132 interrupt control register taa0ccic1 r/w r/w - - 0xfffff134 interrupt control register taa1ovic r/w r/w - - 0xfffff136 interrupt control register taa1ccic0 r/w r/w - - 0xfffff138 interrupt control register taa1ccic1 r/w r/w - - 0xfffff13a interrupt control register taa2ovic r/w r/w - - 0xfffff13c interrupt control register taa2ccic0 r/w r/w - - 0xfffff13e interrupt control register taa2ccic1 r/w r/w - - 0xfffff140 interrupt control register taa3ovic r/w r/w - - 0xfffff142 interrupt control register taa3ccic0 r/w r/w - - 0xfffff144 interrupt control register taa3ccic1 r/w r/w - - 0xfffff146 interrupt control register taa4ovic r/w r/w - - 0xfffff148 interrupt control register taa4ccic0 r/w r/w - - 0xfffff14a interrupt control register taa4ccic1 r/w r/w - - 0xfffff14c interrupt control register tm0eqic0 r/w r/w - - 0xfffff14e interrupt control register cb0ric r/w r/w - - 0xfffff150 interrupt control register cb0tic r/w r/w - - 0xfffff152 interrupt control register cb1ric r/w r/w - - 0xfffff154 interrupt control register cb1tic r/w r/w - - 0xfffff156 interrupt control register ud0sic r/w r/w - - 0xfffff158 interrupt control register ud0ric r/w r/w - - 0xfffff15a interrupt control register ud0tic r/w r/w - - 0xfffff15c interrupt control register ud1sic r/w r/w - - 0xfffff15e interrupt control register ud1ric r/w r/w - - 0xfffff160 interrupt control register ud1tic r/w r/w - - 0xfffff162 interrupt control register iic0ic r/w r/w - - table a-2 other special function registers (2/9) address register name shortcut 1 8 16 32
741 special function registers appendix a user?s manual u18743ee1v2um00 0xfffff164 interrupt control register adic r/w r/w - - 0xfffff166 interrupt control register c0erric r/w r/w - - 0xfffff168 interrupt control register c0wupic r/w r/w - - 0xfffff16a interrupt control register c0recic r/w r/w - - 0xfffff16c interrupt control register c0trxic r/w r/w - - 0xfffff176 interrupt control register kric r/w r/w - - 0xfffff178 interrupt control register wtiic r/w r/w - - 0xfffff17a interrupt control register wtic r/w r/w - - 0xfffff17e interrupt control register flic r/w r/w - - 0xfffff180 interrupt control register pic8 r/w r/w - - 0xfffff182 interrupt control register pic9 r/w r/w - - 0xfffff184 interrupt control register pic10 r/w r/w - - 0xfffff190 interrupt control register ud2sic r/w r/w - - 0xfffff192 interrupt control register ud2ric r/w r/w - - 0xfffff194 interrupt control register ud2tic r/w r/w - - 0xfffff1fa in-service priority register ispr r r - - 0xfffff1fc command register prcmd - w - - 0xfffff1fe power save control register psc r/w r/w - - 0xfffff200 adc0 mode register 0 ada0m0 r/w r/w - - 0xfffff201 adc0 mode register 1 ada0m1 r/w r/w - - 0xfffff202 adc0 channel specification register ada0s r/w r/w - - 0xfffff203 adc0 mode register 2 ada0m2 r/w r/w - - 0xfffff204 adc0 power fail comparison mode register ada0pfm r/w r/w - - 0xfffff205 adc0 power fail comparison threshold value register ada0pft r/w r/w - - 0xfffff20c adc0 conversion result register dd ada0crdd - - r - 0xfffff20d adc0 conversion result register ddh ada0crddh - r - - 0xfffff20e adc0 conversion result register ss ada0crss - - r - 0xfffff20f adc0 conversion result register ssh ada0crssh - r - - 0xfffff210 adc0 conversion result register 0 ada0cr0 - - r - 0xfffff211 adc0 conversion result register 0h ada0cr0h - r - - 0xfffff212 adc0 conversion result register 1 ada0cr1 - - r - 0xfffff213 adc0 conversion result register 1h ada0cr1h - r - - 0xfffff214 adc0 conversion result register 2 ada0cr2 - - r - 0xfffff215 adc0 conversion result register 2h ada0cr2h - r - - 0xfffff216 adc0 conversion result register 3 ada0cr3 - - r - 0xfffff217 adc0 conversion result register 3h ada0cr3h - r - - 0xfffff218 adc0 conversion result register 4 ada0cr4 - - r - 0xfffff219 adc0 conversion result register 4h ada0cr4h - r - - 0xfffff21a adc0 conversion result register 5 ada0cr5 - - r - 0xfffff21b adc0 conversion result register 5h ada0cr5h - r - - 0xfffff21c adc0 conversion result register 6 ada0cr6 - - r - table a-2 other special function registers (3/9) address register name shortcut 1 8 16 32
742 appendix a special function registers user?s manual u18743ee1v2um00 0xfffff21d adc0 conversion result register 6h ada0cr6h - r - - 0xfffff21e adc0 conversion result register 7 ada0cr7 - - r - 0xfffff21f adc0 conversion result register 7h ada0cr7h - r - - 0xfffff220 adc0 conversion result register 8 ada0cr8 - - r - 0xfffff221 adc0 conversion result register 8h ada0cr8h - r - - 0xfffff222 adc0 conversion result register 9 ada0cr9 - - r - 0xfffff223 adc0 conversion result register 9h ada0cr9h - r - - 0xfffff224 adc0 conversion result register 10 ada0cr10 - - r - 0xfffff225 adc0 conversion result register 10h ada0cr10h - r - - 0xfffff226 adc0 conversion result register 11 ada0cr11 - - r - 0xfffff227 adc0 conversion result register 11h ada0cr11h - r - - 0xfffff228 adc0 conversion result register 12 ada0cr12 - - r - 0xfffff229 adc0 conversion result register 12h ada0cr12h - r - - 0xfffff22a adc0 conversion result register 13 ada0cr13 - - r - 0xfffff22b adc0 conversion result register 13h ada0cr13h - r - - 0xfffff22c adc0 conversion result register 14 ada0cr14 - - r - 0xfffff22d adc0 conversion result register 14h ada0cr14h - r - - 0xfffff22e adc0 conversion result register 15 ada0cr15 - - r - 0xfffff22f adc0 conversion result register 15h ada0cr15h - r - - 0xfffff300 key return mode register krm r/w r/w - - 0xfffff308 selector motion control register 0 selcnt0 r/w r/w - - 0xfffff30c selector motion control register 2 selcnt2 r/w r/w - - 0xfffff30e selector motion control register 3 selcnt3 r/w r/w - - 0xfffff318 noise elimination control register nfc r/w r/w - - 0xfffff340 ops0 clock selection register ocks0 r/w - - - 0xfffff400 port 0 p0 r/w r/w - - 0xfffff402 port 1 p1 r/w r/w - - 0xfffff406 port 3 p3 - - r/w - 0xfffff406 port 3l p3l r/w r/w - - 0xfffff407 port 3h p3h r/w r/w - - 0xfffff408 port 4 p4 r/w r/w - - 0xfffff40a port 5 p5 r/w r/w - - 0xfffff40e port 7l p7l r/w r/w - - 0xfffff40f port 7h p7h r/w r/w - - 0xfffff412 port 9 p9 - - r/w - 0xfffff412 port 9l p9l r/w r/w - - 0xfffff413 port 9h p9h r/w r/w - - 0xfffff420 port mode register 0 pm0 r/w r/w - - 0xfffff422 port mode register 1 pm1 r/w r/w - - 0xfffff426 port mode register 3 pm3 - - r/w - 0xfffff426 port mode register 3l pm3l r/w r/w - - table a-2 other special function registers (4/9) address register name shortcut 1 8 16 32
743 special function registers appendix a user?s manual u18743ee1v2um00 0xfffff427 port mode register3h pm3h r/w r/w - - 0xfffff428 port mode register4 pm4 r/w r/w - - 0xfffff42a port mode register5 pm5 r/w r/w - - 0xfffff42e port mode register7l pm7l r/w r/w - - 0xfffff42f port mode register7h pm7h r/w r/w - - 0xfffff432 port mode register9 pm9 - - r/w - 0xfffff432 port mode register9l pm9l r/w r/w - - 0xfffff433 port mode register9h pm9h r/w r/w - - 0xfffff440 port mode control register0 pmc0 r/w r/w - - 0xfffff442 port mode control register1 pmc1 r/w r/w - - 0xfffff446 port mode control register3 pmc3 - - r/w - 0xfffff446 port mode control register3l pmc3l r/w r/w - - 0xfffff447 port mode control register3h pmc3h r/w r/w - - 0xfffff448 port mode control register4 pmc4 r/w r/w - - 0xfffff44a port mode control register5 pmc5 r/w r/w - - 0xfffff44c port mode control register6l pmc6l r/w r/w - - 0xfffff44d port mode control register6h pmc6h r/w r/w - - 0xfffff44e port mode control register7l pmc7l r/w r/w - - 0xfffff44f port mode control register7h pmc7h r/w r/w - - 0xfffff452 port mode control register9 pmc9 - - r/w - 0xfffff452 port mode control register9l pmc9l r/w r/w - - 0xfffff453 port mode control register9h pmc9h r/w r/w - - 0xfffff460 port function control register0 pfc0 r/w r/w - - 0xfffff466 port function control register3l pfc3l r/w r/w - - 0xfffff468 port function control register4 pfc4 r/w r/w - - 0xfffff46a port function control register5 pfc5 r/w r/w - - 0xfffff472 port function control register9 pfc9 - - r/w - 0xfffff472 port function control register9l pfc9l r/w r/w - - 0xfffff473 port function control register9h pfc9h r/w r/w - - 0xfffff590 taa0 control register 0 taa0ctl0 r/w r/w - - 0xfffff591 taa0 control register 1 taa0ctl1 r/w r/w - - 0xfffff592 taa0 i/o control register 0 taa0ioc0 r/w r/w - - 0xfffff593 taa0 i/o control register 1 taa0ioc1 r/w r/w - - 0xfffff594 taa0 i/o control register 2 taa0ioc2 r/w r/w - - 0xfffff595 taa0 option register 0 taa0opt0 r/w r/w - - 0xfffff596 taa0 capture/compare register 0 taa0ccr0 - - r/w - 0xfffff598 taa0 capture/compare register 1 taa0ccr1 - - r/w - 0xfffff59a taa0 counter read buffer register taa0cnt - - r - 0xfffff59c taa0 i/o control register 4 taa0ioc4 r/w r/w - - 0xfffff5a0 taa1 control register 0 taa1ctl0 r/w r/w - - 0xfffff5a1 taa1 control register 1 taa1ctl1 r/w r/w - - table a-2 other special function registers (5/9) address register name shortcut 1 8 16 32
744 appendix a special function registers user?s manual u18743ee1v2um00 0xfffff5a2 taa1 i/o control register 0 taa1ioc0 r/w r/w - - 0xfffff5a3 taa1 i/o control register 1 taa1ioc1 r/w r/w - - 0xfffff5a4 taa1 i/o control register 2 taa1ioc2 r/w r/w - - 0xfffff5a5 taa1 option register 0 taa1opt0 r/w r/w - - 0xfffff5a6 taa1 capture/compare register 0 taa1ccr0 - - r/w - 0xfffff5a8 taa1 capture/compare register 1 taa1ccr1 - - r/w - 0xfffff5aa taa1 counter read buffer register taa1cnt - - r - 0xfffff5ac taa1 i/o control register 4 taa1ioc4 r/w r/w - - 0xfffff5ad taa1 option register 1 taa1opt1 r/w r/w - - 0xfffff5b0 taa2 control register 0 taa2ctl0 r/w r/w - - 0xfffff5b1 taa2 control register 1 taa2ctl1 r/w r/w - - 0xfffff5b2 taa2 i/o control register 0 taa2ioc0 r/w r/w - - 0xfffff5b3 taa2 i/o control register 1 taa2ioc1 r/w r/w - - 0xfffff5b4 taa2 i/o control register 2 taa2ioc2 r/w r/w - - 0xfffff5b5 taa2 option register 0 taa2opt0 r/w r/w - - 0xfffff5b6 taa2 capture/compare register 0 taa2ccr0 - - r/w - 0xfffff5b8 taa2 capture/compare register 1 taa2ccr1 - - r/w - 0xfffff5ba taa2 counter read buffer register taa2cnt - - r - 0xfffff5bc taa2 i/o control register 4 taa2ioc4 r/w r/w - - 0xfffff5c0 taa3 control register 0 taa3ctl0 r/w r/w - - 0xfffff5c1 taa3 control register 1 taa3ctl1 r/w r/w - - 0xfffff5c2 taa3 i/o control register 0 taa3ioc0 r/w r/w - - 0xfffff5c3 taa3 i/o control register 1 taa3ioc1 r/w r/w - - 0xfffff5c4 taa3 i/o control register 2 taa3ioc2 r/w r/w - - 0xfffff5c5 taa3 option register 0 taa3opt0 r/w r/w - - 0xfffff5c6 taa3 capture/compare register 0 taa3ccr0 - - r/w - 0xfffff5c8 taa3 capture/compare register 1 taa3ccr1 - - r/w - 0xfffff5ca taa3 counter read buffer register taa3cnt - - r - 0xfffff5cc taa3 i/o control register 4 taa3ioc4 r/w r/w - - 0xfffff5cd taa3 option register 1 taa3opt1 r/w r/w - - 0xfffff5d0 taa4 control register 0 taa4ctl0 r/w r/w - - 0xfffff5d1 taa4 control register 1 taa4ctl1 r/w r/w - - 0xfffff5d2 taa4 i/o control register 0 taa4ioc0 r/w r/w - - 0xfffff5d3 taa4 i/o control register 1 taa4ioc1 r/w r/w - - 0xfffff5d4 taa4 i/o control register 2 taa4ioc2 r/w r/w - - 0xfffff5d5 taa4 option register 0 taa4opt0 r/w r/w - - 0xfffff5d6 taa4 capture/compare register 0 taa4ccr0 - - r/w - 0xfffff5d8 taa4 capture/compare register 1 taa4ccr1 - - r/w - 0xfffff5da taa4 counter read buffer register taa4cnt - - r - 0xfffff5dc taa4 i/o control register 4 taa4ioc4 r/w r/w - - 0xfffff680 watch timer operation mode register wtm r/w r/w - - table a-2 other special function registers (6/9) address register name shortcut 1 8 16 32
745 special function registers appendix a user?s manual u18743ee1v2um00 0xfffff690 tmm0 timer control register0 tm0ctl0 r/w r/w - - 0xfffff694 tmm0 compare register 0 tm0cmp0 - - r/w - 0xfffff6c0 oscillation stabilization time select register osts - r/w - - 0xfffff6c1 pll lockup time specification register plls - r/w - - 0xfffff6c2 oscillation stabilization timer status register ostc r r - - 0xfffff6d0 watchdog timer mode register 2 wdtm2 r/w r/w - - 0xfffff6d1 watchdog timer enable register wdte r/w r/w - - 0xfffff700 port 0 function control enhancing register pfce0 r/w r/w - - 0xfffff706 port 3 function control enhancing register l pfce3l r/w r/w - - 0xfffff708 port 4 function control enhancing register pfce4 r/w r/w - - 0xfffff70a port 5 function control enhancing register l pfce5 r/w r/w - - 0xfffff712 port 9 function control enhancing register pfce9 - - r/w - 0xfffff712 port 9 function control enhancing register l pfce9l r/w r/w - - 0xfffff713 port 9 function control enhancing register h pfce9h r/w r/w - - 0xfffff802 system register sys r/w r/w - - 0xfffff80c internal oscillator mode register rcm r/w r/w - - 0xfffff820 power save mode register psmr r/w r/w - - 0xfffff824 lock register lockr r r - - 0xfffff828 processor clock control register pcc r/w r/w - - 0xfffff82c pll control register pllctl r/w r/w - - 0xfffff82e cpu operating clock status register ccls r r - - 0xfffff82f programmable clock mode register pclm r/w r/w - - 0xfffff860 system clock mode register mcm r/w r/w - - 0xfffff870 clock monitor mode register clm r/w r/w - - 0xfffff888 reset factor flag register resf r/w r/w - - 0xfffff890 low voltage detection register lvim r/w r/w - - 0xfffff891 low voltage detection level selection register lvis - r/w - - 0xfffff892 ram data status register rams r/w r/w - - 0xfffff8b0 brg0 prescaler mode register prsm0 - r/w - - 0xfffff8b1 brg0 prescaler compare register prscm0 - r/w - - 0xfffff9fc on-chip debug mode register ocdm r/w r/w - - 0xfffff9fe peripheral emulation register 1 pemu1 r/w r/w - - 0xfffffa00 uartd0 control register 0 ud0ctl0 r/w r/w - - 0xfffffa01 uartd0 control register 1 ud0ctl1 - r/w - - 0xfffffa02 uartd0 control register 2 ud0ctl2 - r/w - - 0xfffffa03 uartd0 option control register 0 ud0opt0 r/w r/w - - 0xfffffa04 uartd0 status register ud0str r/w r/w - - 0xfffffa05 uartd0 option control register 1 ud0opt1 - r/w - - 0xfffffa06 uartd0 receive data register ud0rx - r - - 0xfffffa07 uartd0 transmit data register ud0tx - r/w - - 0xfffffa10 uartd1 control register 0 ud1ctl0 r/w r/w - - table a-2 other special function registers (7/9) address register name shortcut 1 8 16 32
746 appendix a special function registers user?s manual u18743ee1v2um00 0xfffffa11 uartd1 control register 1 ud1ctl1 - r/w - - 0xfffffa12 uartd1 control register 2 ud1ctl2 - r/w - - 0xfffffa13 uartd1 option control register 0 ud1opt0 r/w r/w - - 0xfffffa14 uartd1 status register ud1str r/w r/w - - 0xfffffa15 uartd1 option control register 1 ud1opt1 - r/w - - 0xfffffa16 uartd1 receive data register ud1rx - r - - 0xfffffa17 uartd1 transmit data register ud1tx - r/w - - 0xfffffa20 uartd2 control register 0 ud2ctl0 r/w r/w - - 0xfffffa21 uartd2 control register 1 ud2ctl1 - r/w - - 0xfffffa22 uartd2 control register 2 ud2ctl2 - r/w - - 0xfffffa23 uartd2 option control register 0 ud2opt0 r/w r/w - - 0xfffffa24 uartd2 status register ud2str r/w r/w - - 0xfffffa25 uartd2 option control register 1 ud2opt1 - r/w - - 0xfffffa26 uartd2 receive data register ud2rx - r - - 0xfffffa27 uartd2 transmit data register ud2tx - r/w - - 0xfffffc00 external interrupt falling edge specification register 0 intf0 r/w r/w - - 0xfffffc02 external interrupt falling edge specification register 1 intf1 r/w r/w - - 0xfffffc06 external interrupt falling edge specification register 3 intf3 - - r/w - 0xfffffc06 external interrupt falling edge specification register 3l intf3l r/w r/w - - 0xfffffc07 external interrupt falling edge specification register 3h intf3h r/w r/w - - 0xfffffc08 external interrupt falling edge specification register 4 intf4 r/w r/w - - 0xfffffc0c external interrupt falling edge specification register 6 intf6 - - r/w - 0xfffffc0c external interrupt falling edge specification register 6l intf6l r/w r/w - - 0xfffffc0d external interrupt falling edge specification register 6h intf6h r/w r/w - - 0xfffffc10 external interrupt falling edge specification register 8 intf8 r/w r/w - - 0xfffffc13 external interrupt falling edge specification register 9h intf9h r/w r/w - - 0xfffffc20 external interrupt rising edge specification register 0 intr0 r/w r/w - - 0xfffffc22 external interrupt rising edge specification register 1 intr1 r/w r/w - - 0xfffffc26 external interrupt rising edge specification register 3 intr3 - - r/w - 0xfffffc26 external interrupt rising edge specification register 3l intr3l r/w r/w - - 0xfffffc27 external interrupt rising edge sp ecification register 3h intr3h r/w r/w - - 0xfffffc28 external interrupt rising edge specification register 4 intr4 r/w r/w - - 0xfffffc2c external interrupt rising edge specification register 6 intr6 - - r/w - 0xfffffc2c external interrupt rising edge specification register 6l intr6l r/w r/w - - 0xfffffc2d external interrupt rising edge sp ecification register 6h intr6h r/w r/w - - 0xfffffc30 external interrupt rising edge specification register 8 intr8 r/w r/w - - 0xfffffc33 external interrupt rising edge sp ecification register 9h intr9h r/w r/w - - 0xfffffc40 pull-up resistor option register 0 pu0 r/w r/w - - 0xfffffc42 pull-up resistor option register 1 pu1 r/w r/w - - 0xfffffc46 pull-up resistor option register 3 pu3 - - r/w - 0xfffffc46 pull-up resistor option register 3l pu3l r/w r/w - - table a-2 other special function registers (8/9) address register name shortcut 1 8 16 32
747 special function registers appendix a user?s manual u18743ee1v2um00 0xfffffc47 pull-up resistor option register 3h pu3h r/w r/w - - 0xfffffc48 pull-up resistor option register 4 pu4 r/w r/w - - 0xfffffc4a pull-up resistor option register 5 pu5 r/w r/w - - 0xfffffc4c pull-up resistor option register 6 pu6 - - r/w - 0xfffffc52 pull-up resistor option register 9 pu9 - - r/w - 0xfffffc52 pull-up resistor option register 9l pu9l r/w r/w - - 0xfffffc53 pull-up resistor option register 9h pu9h r/w r/w - - 0xfffffc73 port 9 function control register h pf9h r/w r/w - - 0xfffffd00 csib0 control register 0 cb0ctl0 r/w r/w - - 0xfffffd01 csib0 control register 1 cb0ctl1 r/w r/w - - 0xfffffd02 csib0 control register 2 cb0ctl2 r/w r/w - - 0xfffffd03 csib0 status register cb0str r/w r/w - - 0xfffffd04 csib0 receive da ta register cb0rx - - r - 0xfffffd04 csib0 receive data register l cb0rxl - r - - 0xfffffd06 csib0 transmit data register cb0tx - - r/w - 0xfffffd06 csib0 transmit data register l cb0txl - r/w - - 0xfffffd10 csib1 control register 0 cb1ctl0 r/w r/w - - 0xfffffd11 csib1 control register 1 cb1ctl1 r/w r/w - - 0xfffffd12 csib1 control register 2 cb1ctl2 - r/w - - 0xfffffd13 csib1 status register cb1str r/w r/w - - 0xfffffd14 csib1 receive da ta register cb1rx - - r - 0xfffffd14 csib1 receive data register l cb1rxl - r - - 0xfffffd16 csib1 transmit data register cb1tx - - r/w - 0xfffffd16 csib1 transmit data register l cb1txl - r/w - - 0xfffffd80 iic0 shift register iic0 - r/w - - 0xfffffd82 iic0 control register iicc0 r/w r/w - - 0xfffffd83 iic0 slave address register sva0 - r/w - - 0xfffffd84 iic0 clock selection register iiccl0 r/w r/w - - 0xfffffd85 iic0 function expansion register iicx0 r/w r/w - - 0xfffffd86 iic0 state register iics0 r/w r/w - - 0xfffffd8a iic0 flag register iicf0 r/w r/w - - table a-2 other special function registers (9/9) address register name shortcut 1 8 16 32
748 appendix a special function registers user?s manual u18743ee1v2um00
749 user?s manual u18743ee1v2um00 appendix b registers access times this chapter provides formulas to calculate the access time to registers, which are accessed via the peripheral i/o areas. all accesses to the peripheral i/o areas are passed over to the npb bus via the vsb - npb bus bridge bbr. read and write access times to registers via the npb depend on the register, the system clock vbclk and the setting of the vswc register. the cpu operation during an access to a register via the npb depends also on the kind of peripheral i/o area:  fixed peripheral i/o area during a read or write access the cpu operation stops until the access via the npb is completed.  programmable peripheral i/o area during a read access the cpu operation stops until the read access via the npb is completed. during a write access the cpu operation continues operation, provided any preceded npb access is already finished. if a preceded npb access is still ongoing the cpu stops until this access is finished and the npb is cleared. the following formulas are given to calculate the access times t a , when the cpu reads from or writes to special function registers via the npb bus. the access time depends  on the cpu system clock frequency f vbclk  on the setting of the internal peripheral function wait control register vswc, which determines the address set up wait suwl = vswc.suwl and data wait vswl = vswc.vswl (refer to ?vswc - internal peripheral function wait control register? on page 302 for the correct values for a certain cpu system clock vbclk)  for some registers on the clock frequency applied to the module note ?ru[...]? in the formulas mean ?round up? the calculated value of the term in squared brackets. all formulas calculate the maximum access time. cpu access for calculating the access times for cpu accesses 1 vblck period time 1/ f vbclk has to be added to the results of the formulas. b.1 timer aa register taanccrm access r
750 appendix b registers access times user?s manual u18743ee1v2um00 formula  i f ta a n c t l 0 . ta a n c e = 0 :  i f ta a n c t l 0 . ta a n c e = 1 : access w formula  i f ta a n c t l 0 . ta a n c e = 0 :  i f ta a n c t l 0 . ta a n c e = 1 : ? continuous write ? single write register taanioc4 access r formula access w formula  i f ta a n c t l 0 . ta a n c e = 0 :  i f ta a n c t l 0 . ta a n c e = 1 : ? continuous write ? single write t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl 2 vswl ? 5 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ 1 f vbclk ------------------ ? = t a suwl vswl 3 ru 5f vbclk ? 2vswl + () f taa ? ------------------------------------------------ 1 + 2 vswl + () ? +++ ?? ?? ?? 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ru 5f vbclk ? 2vswl + () f taa ? ------------------------------------------------ 1 + 2 vswl + () ? +++ ?? ?? ?? 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? =
751 registers access times appendix b user?s manual u18743ee1v2um00 register taancnt access r formula  i f ta a n c t l 0 . ta a n c e = 0 :  i f ta a n c t l 0 . ta a n c e = 1 : access w formula register all other access r/w formula f ta a the taan input clock can be selected from  selcnt2.selcnt2n = 0: f ta a =f xp1  selcnt2.selcnt2n = 1: f ta a =f xp2 b.2 timer m register all access r/w formula t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl 2 vswl ? 5 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? =
752 appendix b registers access times user?s manual u18743ee1v2um00 b.3 watchdog timer 2 register wdtm2 access w formula  if watchdog timer operating:  if watchdog timer stopped: access r formula register all other access r/w formula b.4 a/d converter register ada0m0, ada0crm, ada0crmh, ada0crdd, ada0crddh, ada0crdss, ada0crssh access r formula access w formula register all other access r/w formula t a suwl 4 vswl ? 9 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ru 2f vbclk ? 2vswl + () f xp1 ? ------------------------------------------------ 1 + 2vswl + () ? +++ ?? ?? ?? 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? =
753 registers access times appendix b user?s manual u18743ee1v2um00 b.5 i 2 c bus register iicsn access r formula register all other access r/w formula b.6 asynchronous serial interface (uartd) register all access r/w formula b.7 clocked serial interface (csib) register all access r/w formula t a suwl 3 vswl ? 7 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? =
754 appendix b registers access times user?s manual u18743ee1v2um00 b.8 can controller register cnmdata[7:0]m access r formula access 8-bit write formula access 16-bit write formula register cnrgpt, cntgpt, cnlipt, cnlopt access r formula access w formula register all other access r/w formula f can refer to ?clock generator? on page 159 for f can selection control. b.9 all other registers register all access r/w formula t a suwl vswl 3 ru 4 f vbclk f can ------------------ 1 + ? 2vswl + () ----------------------------------- - 2 vswl + () ? +++ ?? ?? ?? ?? ?? 1 f vbclk ------------------ ? = t a suwl vswl 3 ru 5 f vbclk f can ------------------ 1 + ? 2vswl + () ----------------------------------- - 2 vswl + () ? +++ ?? ?? ?? ?? ?? 1 f vbclk ------------------ ? = t a suwl vswl 3 ru 3 f vbclk f can ------------------ 1 + ? 2vswl + () ----------------------------------- - 2 vswl + () ? +++ ?? ?? ?? ?? ?? 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? = t a suwl vswl 3 ru 4 f vbclk f can ------------------ 1 + ? 2vswl + () ----------------------------------- - 2 vswl + () ? +++ ?? ?? ?? ?? ?? 1 f vbclk ------------------ ? = t a suwl vswl 3 ru 2 f vbclk f can ------------------ 1 + ? 2vswl + () ----------------------------------- - 2 vswl + () ? +++ ?? ?? ?? ?? ?? 1 f vbclk ------------------ ? = t a suwl vswl 3 ++ () 1 f vbclk ------------------ ? =
755 user?s manual u18743ee1v2um00 revision history the following revision list shows all functional changes compared to the manual version u18743ee1v1um00 (published in april 2008). version date document number description 1.0 august 2007 u18743ee1v0um00 initial release 1.1 april 2008 u18743ee1v1um00 update 1.2 june 2008 u18743ee1v2um00 update chapter page description 7 265 corrected number of writable bytes in flash memory. 9 295 added chapter ?bus control unit? 24 735 added sscg to fx3-l vs fx3 difference list
756 user?s manual u18743ee1v2um00
757 user?s manual u18743ee1v2um00 index a a/d converter 663 basic operation 680 cautions 694 configuration 665 control registers 667 how to read a/d converter characteristics table 696 operation mode 683 power-fail compare mode 688 trigger mode 681 adancrdd 676 adancrddh 676 adancrm 674 adancrmh 674 adancrss 677 adancrssh 677 adanm0 667 adanm1 669 adanm2 671 adanpfm 678 adanpft 679 adans 672 adc (a/d converter) 663 adc channel specification register (adans) 672 adc mode register 0 (adanm0) 667 adc mode register 1 (adanm1) 669 adc mode register 2 (adanm2) 671 adc power-fail compare mode register (adanpfm) 678 adc power-fail compare threshold value register (adanpft) 679 adc result registers (adancrm) 674 adc result registers h (adamcrmh) 674 address space cpu 147 data space 149 images 148 physical 147 program space 149 adic 237 analog filtered inputs 126 asynchronous serial interface see uartd avref a/d conversion diagnostic registers (adancrdd) 676 avref a/d conversion diagnostic registers (adancrddh) 676 avss a/d conversion diagnostic registers (adancrss) 677 avss a/d conversion diagnostic registers (adancrssh) 677 b baud rate generator uartd 419 bcu (bus control unit) 295 bcu registers 301 boundary operation conditions 299 bpc 301 buffer diagrams 47 bus and memory control registers 301 bus control 295 bus properties 299 bus access 299 endian format 299 c c0erric 237 c0recic 237 c0trxic 237 c0wupic 237 callt base pointer (ctbp) 145 can (controller area network) 527 can controller 527 baud rate settings 629 bit set/clear function 560 configuration 530 connection with target system 552 control registers 562 diagnosis functions 624 functions 541 initialization 598 internal registers 553 interrupt function 623 message reception 602 message transmission 610 operation 637 overview of functions 529 power saving modes 618 register access type 555 register bit configuration 557 special operational modes 624 time stamp function 628 transition from initialization mode to opera- tion mode 600 can protocol 531 cann global automatic block transmission control register (cngmabt) 565
758 index user?s manual u18743ee1v2um00 cann global automatic block transmission delay register (cngmabtd) 567 cann global clock selection register (cngmcs) 564 cann global control register (cngmctrl) 562 cann message configuration register m (cnmconfm) 592 cann message control register m (cnmctrlm) 595 cann message data byte register (cnmdataxm) 589 cann message data length register m (cnmdlcm) 591 cann message id register m (cnmidlm, cnmidhm) 594 cann module bit rate prescaler register (cnbrp) 580 cann module bit rate register (cnbtr) 581 cann module control register (cnctrl) 570 cann module error counter register (cnerc) 576 cann module information register (cninfo) 575 cann module interrupt enable register (cnie) 577 cann module interrupt status register (cnints) 579 cann module last error information register (cnlec) 574 cann module last in-pointer register (cnlipt) 582 cann module last out-pointer register (cnlopt) 584 cann module mask control register (cnmaskal, cnmaskah) 568 cann module receive history list register (cnrgpt) 583 cann module time stamp register (cnts) 587 cann module transmit history list register (cntgpt) 585 cb0ric 237 cb0tic 237 cb1ric 237 cb1tic 237 cbnctl0 430 cbnctl1 432 cbnctl2 433 cbnrx 429 cbnstr 435 cbntx 429 ccls 168 clkout function 215 clock generator 159 general registers 168 operation 191 pll related registers 178 registers 166 start conditions 165 clock monitor 163 control registers 184 operation 217 clock operation control settings 191 clock signals summary 163 clocked serial interface see csib clocks cpu 161 for peripherals 162 in power save modes 211 special clocks 162 cnbrp 580 cnbtr 581 cnctrl 570 cnerc 576 cngmabt 565 cngmabtd 567 cngmcs 564 cngmctrl 562 cnie 577 cninfo 575 cnints 579 cnlec 574 cnlipt 582 cnlopt 584 cnmaskah 568 cnmaskal 568 cnmconfm 592 cnmctrlm 595 cnmdataxm 589 cnmdlcm 591 cnmidhm 594 cnmidlm 594 cnrgpt 583 cntgpt 585 cnts 587 command register (prcmd) 157 cpu address space 147 clocks 161 memory 151 operation modes 146 register set 137 write protected registers 155
759 index user?s manual u18743ee1v2um00 cpu operation clock status register (ccls) 168 csib configuration 428 control registers 430 operation 436 operation flow 449 output pins 448 csib (clocked serial interface) 427 csib transmit data register (cbntx) 429 csibn control register 0 (cbnctl0) 430 csibn control register 1 (cbnctl1) 432 csibn control register 2 (cbnctl2) 433 csibn receive data register (cbnrx) 429 csibn status register (cbnstr) 435 ctbp 145 ctpc 140 ctpsw 143 d data address space recommended use 154 data space 149 dbpc 140 dbpsw 143 debug function (on-chip) 723 code protection 289 restrictions and cautions 734 debug trap 251 differences fx3-l to fx3 735 digital noise filter control register (nfc) 128 digitally filtered inputs 127 e eccdic 237 ecr 144 eipc 140 eipsw 143 element pointer 138 exception status flag (ep) 249 exception trap 249 external interrupt falling edge specification regis- ter (intfm) 244 external interrupt rising edge specification register (intrm) 244 external reset 710 f fepc 140 fepsw 143 fixed peripheral i/o area 152, 296 flash area 151 flash memory 259 self-programming 277 flash programmer communication mode 267 pin connection 269 flash programming mode 146 flic 237 fplli 161 fpllo 161 g general purpose registers (r0 to r31) 138 global pointer 138 h halt mode 197 i i 2 c bus 457 acknowledge signal 483 address match detection method 507 arbitration 509 bus mode functions 480 cautions 511 communication operations 512 configuration 458 control registers 462 definitions and control methods 481 error detection 507 extension code 508 interrupt request signal (intiicn) generation timing and wait control 506 interrupt request signals (intiicn) 488 interrupt request signals (intiicn) 488 pin configuration 457 pin functions 480 stop condition 485 timing of data communication 519 transfer direction specification 483 wait signal 486 wakeup function 510 idle pins recommended connection 131 idle1 mode 199 idle2 mode 201 iic clock select registers (iiccln) 472 iic control registers (iiccn) 463 iic division clock select registers (ocksn) 474 iic flag registers (iicfn) 470 iic function expansion registers (iicxn) 473
760 index user?s manual u18743ee1v2um00 iic shift registers (iicn) 479 iic status registers (iicsn) 467 iic0ic 237 iiccln 472 iiccn 463 iicfn 470 iicn 479 iicsn 467 iicxn 473 images in address space 148 imrn 240 in-service priority register (ispr) 242 intc (interrupt controller) 221 internal flash area 151 internal oscillator 160 internal oscillator mode register (rcm) 177 internal peripheral function wait control register (vswc) 302 internal ram area 151 internal ram data status register (rams) 717 interrupt maskable 230 non-maskable 224 processing (multiple interrupts) 252 response time 254 interrupt control registers 237 interrupt controller 221 debug trap 251 edge detection configuration 244 exception trap 249 periods in which interrupts are not acknowledged 255 software exception 247 interrupt mask registers imrn 240 interrupt/exception source register (ecr) 144 intfm 244 intrm 244 ispr 242 k key interrupt function 257 cautions 258 control register 258 key return mode register (krm) 258 kric 237 krm 258 l link pointer 138 lockr 178 low voltage detection level selection register (lvis) 716 low voltage detection register (lvim) 714 low voltage detector 713 configuration 713 operation 719 registers 714 lvihic 237 lvilic 237 lvim 714 lvis 716 m main oscillator 160 main system clock mode register (mcm) 169 maskable interrupt control registers (xxicn) 237 maskable interrupt status flag (id) 243 maskable interrupts 230 mcm 169 memory areas 151 modified usage of taanctl0 during taa operation. 314 n nfc 128 noise elimination pin input 126 non-maskable interrupts 224 normal operation mode 146 n-wire code protection 289 connection to emulator 730 controlling the interface 726 emulator 723 enabling methods 728 security function 725 o ocdm 42, 726 ocksn 474 on-chip debug mode register (ocdm) 42, 726 open drain configuration 46 operation modes flash programming mode 146 normal operation mode 146 option bytes 188 oscillation stabilization time select register (osts) 171 oscillation stabilization timer status register (ostc) 170 oscillators
761 index user?s manual u18743ee1v2um00 internal oscillator 160 main oscillator 160 sub oscillator 160 ostc 170 osts 171 p package pins assignment 132 pc 140 pc saving registers 140 pcc 173 pclm 176 pemu1 718 peripheral area selection control register (bpc) 301 peripheral clocks 162 peripheral emulation register 1 (pemu1) 718 peripheral i/o area 296 fixed 152, 296 programmable 153, 297 pfcen 41 pfcn 40 pfn 46 phase locked loop (pll) 161 physical address space 147 pic0 237 pic1 237 pic10 237 pic2 237 pic3 237 pic4 237 pic5 237 pic6 237 pic7 237 pic8 237 pic9 237 pin functions 31 after reset/power save modes 130 list 104 unused pins 131 pll 161 control 215 pll control register (pllctl) 179 pll lock status register (lockr) 178 pll lockup time specification register (plls) 180 pllctl 179 plls 180 pmcn 38 pmn 39 pn 43 poc (power-on clear) 708 port function control expansion register (pfcen) 41 port function control register (pfcn) 40 port function register (pfn) 46 port groups 32 configuration 51 configuration registers 36 list 100 port mode control register (pmcn) 38 port mode register (pmn) 39 port pull-up resistor option register (pun) 45 port register (pn) 43 power save control register (psc) 181 power save mode control register (psmr) 182 power save modes activation 213 description 196 overview 164 power supply scheme 701 description 702 voltage regulators 703 power-on clear reset 708 ppa (programmable peripheral i/o area) 297 prcmd 157 prdselh - product selection code register high 288 prescaler3 216 prescaler3 compare register (prscm0) 183 prescaler3 control registers 183 prescaler3 mode register (prsm0) 183 processor clock control register (pcc) 173 program counter (pc) 140 program space 149 program status word (psw) 141 programmable clock mode register (pclm) 176 programmable peripheral i/o area 153, 297 prscm0 183 prsm0 183 psc 181 psmr 182 psw 141 psw saving registers 143 pun 45 r ram area 151 rams 717 rcm 177 regid (system register number) 139
762 index user?s manual u18743ee1v2um00 reset 705 at power-on 708 by clock monitor 711 by watchdog timer 711 external reset 710 hardware status after reset 706 register status after reset 707 registers 712 reset source flag register (resstat) 712 resstat 712 s saturated operation instructions 142 selcnt0 185, 312 selcnt2 186 selcnt3 187, 313 selcntx 185, 312 selector control register 0 312 selector control register 0 (selcnt0) 185 selector control register 2 (selcnt2) 186 selector control register 3 313 selector control register 3 (selcnt3) 187 selector control registers (selcntx) 185, 312 sfr (special function register) 737 slave address registers (svan) 479 software exception 247 special clocks 162 special function registers (list) 737 stack pointer 138 stand-by control 163 registers 181 stop mode 204 sub idle mode 208 sub oscillator 160 subclock mode 207 svan 479 sys 157 system register (sys) 157 system register set 139 t taa capture/compare register 0 (taanccr0) 309 taa capture/compare register 1 (taanccr1) 310 taa control register 0 (taanctl0) 314 taa counter read buffer register (taancnt) 311 taa dedicated i/o control register 0 (taanioc0) 318 taa dedicated i/o control register 1 (taanioc1) 319 taa i/o control register 2 (taanioc2) 321 taa i/o control register 4 (taanioc4) 323 taa option register 0 (taanopt0) 324 taa option register 1 (taanopt1) 325 taa timer control register 1 (taanctl1) 316 taa0ccic0 237 taa0ccic1 237 taa0ovic 237 taa1ccic0 237 taa1ccic1 237 taa1ovic 237 taa2ccic0 237 taa2ccic1 237 taa2ovic 237 taa3ccic0 237 taa3ccic1 237 taa3ovic 237 taa4ccic0 237 taa4ccic1 237 taa4ovic 237 taanccr0 309 taanccr1 310 taancnt 311 taanctl0 314 taanctl1 316 taanioc0 318 taanioc1 319 taanioc2 321 taanioc4 323 taanopt0 324 taanopt1 325 text pointer 138 timer m 371 configuration 371 operation 374 registers 372 timer m0 compare register 0 (tm0cmp0) 372 timer m0 control register 0 (tm0ctl0) 373 tm0cmp0 372 tm0ctl0 373 tm0eqic0 237 u uartd cautions 426 dedicated baud rate generator 419 interrupt request signals 403 operation 404 uartdn control register 0 (udnctl0) 395 uartdn control register 1 (udnctl1) 420
763 index user?s manual u18743ee1v2um00 uartdn control register 2 (udnctl2) 421 uartdn option control register 0 (udnopt0) 397 uartdn option control register 1 (udnopt1) 399 uartdn receive data register (udnrx) 402 uartdn receive shift register 393 uartdn status register (udnstr) 400 uartdn transmit data register (udntx) 402 uartdn transmit shift register 394 ud0ric 237 ud0sic 237 ud0tic 237 ud1ric 237 ud1sic 237 ud1tic 237 ud2ric 237 ud2sic 237 ud2tic 237 udnctl0 395 udnctl1 420 udnctl2 421 udnopt0 397 udnopt1 399 udnrx 402 udnstr 400 udntx 402 v vswc 302 w watch dog timer clock 215 watch timer functions configuration 380 control registers 381 operation 382 watch timer functions 379 watch timer operation mode register (wtm) 381 watchdog timer 2 385 configuration 386 control registers 387 watchdog timer 2 mode register (wdtm2) 387 watchdog timer enable register (wdte) 389 wdte 389 wdtm2 387 write protected registers 155 wtic 237 wtiic 237 wtm 381 z zero register 138
764 user?s manual u18743ee1v2um00


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