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1 ? fn8149.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. preliminary x80010, x80011, x80012, x80013 penta-power sequence controller with hot swap and system management the x80010, x80011, x80012, x80013 contain three major functions: a power sequencing controller, a hotswap controller, and systems management support. the power sequencer controller time sequences up to five dc/dc modules. the device allows various dc/dc power sequencing configurations, either parallel or relay modes. the power good, enable, and voltage good signals provide for flexible dc/dc timing configurations. each voltage enable signal has a built-in delay while additional delay can be added with simple external passive components. the hot swap controller allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. the x80010 family of devices offers a modular, power distribution approa ch by providing flexibility to solve the hotswap and power sequencing issues for insertion, operations, and ex traction. hardshort detection and retry with delay, noise filtering, insertion overcurrent bypass, and gate current selection are some of the integrated features of the devic e. during insertion, the gate of an external power mosfet is clamped low to suppress contact bounce. the undervoltage/overvoltage circuits and the power on reset circuitry suppress the gate turn on until the mechanical bounce has ended. the x80010 turns on the gate with a user set slew rate to limit the inrush current and incorporates an electronic circuit breaker set by a sense resistor. after the load is successfully charged, the pwrgd signal is asserted; indicating that the device is ready to power sequence the dc/dc power bricks. systems management function provides a reset signal indicating that the power good and all the voltage good signals are active. the reset signal is asserted after a wait state delay. this signal is used to coordinate the hotswap and dc/dc module latencies during power up to avoid "power hang up". in addition, the cpu host can initiate soft insertion or dc voltage module re-sequencing. features ? integrates three major functions - power sequencing - hot swap controller - system management functions ? penta-power sequencing - sequence up to 5 dc/dc converters. - four independent voltage enable pins - four time delay circuits - soft power sequencing - mrc pin restarts sequence without power cycling. ? hot swap controller - programmable overvoltage and undervoltage protection - undervoltage lockout for battery/redundant supplies - electronic circuit breaker - overcurrent detection and gate shut-off - overcurrent limit during insertion - hardshort retry with retry failure flag - selectable gate current using igq pins (10, 70, 150a) - mrh pin controls board insertion/extraction. - typically operates from -30v to -80v. tolerates transients to -200v (limited by external components) ? system management - reset output, with delay, holds off host until all supplies are good - host control of reinsertion with mrh input - host control of resequencing using mrc input ? available packages - 32-lead quad no-lead frame (qfn) applications ? -48v hot swap power backplane/distribution central office, ethernet for voip ? card insertion detection ? power sequencing dc/dc/power bricks ? ip phone applications ? databus power interfacing ? custom industrial power backplanes ? distributed power systems data sheet january 13, 2005
2 fn8149.0 january 13, 2005 pinout typical application v1good mrc na1 v3good v2good en4 en3 en1 reset na1 v4good drain pwrgd sense v uv/ov i gq0 v ee gate v dd far batt-on mrh i gq1 na2 1 2 3 4 5 6 7 91011 12 13 14 18 19 20 21 22 23 24 26 27 28 29 30 31 32 na2 en2 817 na1 v ee 15 25 v rgo 16 na1 nc nc qfn package (top view) (7mm x 7mm) ordering information order number ov (v) uv1 (v) uv2 (v) t nf (us) v oc (mv) v oci (mv) over current retry retry delay (ms) i gate (a) t delay (ms) t por (ms) temp range (c) part mark x80010q32i 74.9 42.4 33.2 5 50 150 always 100 50 100 100 -40 to 85 80010i x80011q32i 68.0 42.4 33.2 5 50 150 always 100 50 100 100 -40 to 85 80011i X80012Q32I 74.9 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 to 85 80012i x80013q32i 68.0 42.4 33.2 5 50 150 5 retries 100 50 100 100 -40 to 85 80013i v dd x80010, x80011, v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 rtn v1good v2good v3good dc/dc module 1 on /off dc/dc module 2 on /off dc/dc module 3 on /off dc/dc module 4 on /off pwrgd en1 en2 en3 4.7v 12v v1 v2 v3 v4 100 0.1uf back- plane 100k 4.7k 3.3n x80012, x80013 x80010, x80011, x80012, x80013
3 fn8149.0 january 13, 2005 absolute maximum ratings recommended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . . ?65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c voltage on given pin (hot side functions): v ov/uv pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee sense pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mv + v ee v ee pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -80v drain pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48v + v ee pwrgd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v + v ee gate pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd + v ee far pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v + v ee mrh pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee batt_on pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee voltage on given pin (cold side functions): eni pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v vigood pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee mrc pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee igq1 and igq0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee v dd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14v + v ee d.c. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300c temperature range (industrial) . . . . . . . . . . . . . . . . . . -40c to 85c supply voltage (v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical specifications (standard settings) over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min typ max unit dc characteristics v dd supply operating range 10 12 14 v i dd supply current 2.5 5 ma v rgo regulated 5v output i rgo = 10a 4.5 6.0 i rgo v rgo current output 50 a i gate gate pin current gate drive on, v gate = v ee , v sense = v ee (sourcing) 46.2 52.5 58.8 a v gate - v ee = 3v v sense -v ee = 0.1v (sinking) 9ma v gate external gate drive (slew rate control) i gate = 50a v dd -1 v dd v v pga power good threshold (pwrgd high to low) referenced to v ee v uv1 < v uv/ov < v ov 0.9 1 1.1 v v ihb voltage input high (batt_on) v ee + 4 v ee + 5 v v ilb voltage input low (batt_on) v ee + 2 v i li input leakage current (mrh, mrc) v il = gnd to v cc 10 a i lo output leakage current (v1good , v2good , v3good , v4good , reset ) all eni = v rgo for i = 1 to 4 10 a v il (3) input low voltage (mrh , mrc, igq0, igq1) -0.5 + v ee (v ee + 5) x 0.3 v v ih (3) input high voltage (mrh , mrc, igq0, igq1) (v ee + 5) x 0.7 (v ee + 5) + 0.5 v x80010, x80011, x80012, x80013
4 fn8149.0 january 13, 2005 v ol output low voltage (reset, reset , v1good , v2good , v3good , v4good, far , pwrgd ) i ol = 4.0ma (v ee + 2.7 to v ee + 5.5v) i ol = 2.0ma (v ee + 2.7 to v ee + 3.6v) v ee + 0.4 v c out (1) output capacitance (reset , v1good , v2good , v3good , v4good , far ) v out = 0v 8 pf c in (1) input capacitance (mrh , mrc) v in = 0v 6 pf v oc over-current threshold v oc = v sense - v ee 45 50 55 mv v oci over-current threshold (insertion) v oc = v sense - v ee pwrgd = high initial power up condition 135 150 165 mv v ovr overvoltage threshold (rising) x80010, x80012 x80011, x80013 referenced to v ee 3.85 3.49 3.90 3.54 3.95 3.59 v v ovh overvoltage hysteresis referenced to v ee 12 18 24 mv v uv1h undervoltage 1 hysteresis referenced to v ee batt-on = v ee 12 18 24 mv v uv1f undervoltage 1 threshold (falling) 2.16 2.21 2.26 v v uv2h undervoltage 2 hysteresis referenced to v ee batt-on = v rgo 12 18 24 mv v uv2f undervoltage 2 threshold (falling) 1.68 1.73 1.78 v v drainf drain sense voltage threshold (falling) referenced to v ee 0.9 1 1.1 v v drainr drain sense voltage threshold (rising) referenced to v ee 1.2 1.3 1.4 v v trip1 en1 trip point voltage referenced to v ee 2.25 2.5 2.75 v v trip2 en2 trip point voltage referenced to v ee 2.25 2.5 2.75 v v trip3 en3 trip point voltage referenced to v ee 2.25 2.5 2.75 v v trip4 en4 trip point voltage referenced to v ee 2.25 2.5 2.75 v ac characteristics t foc sense high to gate low 1.5 2.5 3.5 s t fuv under voltage conditions to gate low 0.5 1.0 1.5 s t fov overvoltage conditions to gate low 1.0 1.5 2 s t vfr overvoltage/undervoltage failure recovery time to gate =1v. v dd does not drop below 3v, no other failure conditions. 1.2 1.6 2 s t batt_on delay batt_on valid 100 ns t mrc minimum time high for reset valid on the mrc pin 5 s t mrh minimum time high for reset valid on the mrh pin 5 s t mrce delay from mrc enable to pwrgd high no load 1.0 1.6 s t mrcd delay from mrc disable to pwrgd low gate is on, no load 200 400 s t mrhe delay from mrh enable to gate pin low i gate = 60a, no load 1.0 1.6 2.4 s t mrhd delay from mrh disable to gate reaching 1v i gate = 60a, no load 1.8 2.6 s electrical specifications (standard settings) over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min typ max unit x80010, x80011, x80012, x80013
5 fn8149.0 january 13, 2005 equivalent a.c. out put load circuit t reset _e delay from pwrgd or vigood to reset valid low 1 s t qc delay from igq1 and igq0 to valid gate pin current 1 s t sc_retry delay between retries 85 100 115 ms t nf noise filter for overcurrent 4.5 5 5.5 s t dpor device delay before gate assertion 45 50 55 ms t spor delay after pwrgd and all vigood signals are active before reset assertion 85 100 115 ms t delay1 power sequencing time delay t i d1 = 0; t i d0 = 0 85 100 115 ms t delay2 t delay3 t delay4 t to vigood turn off time 50 ns t pdhlpg (1) delay from drain good to pwrgd low gate = v dd 1 s t pdlhpg (1) delay from drain fail to pwrgd high gate = v dd 1 s t pghlpg (1) delay from gate good to pwrgd low drain = v ee 1 s t pglhpg (1) delay from gate fail to pwrgd high drain = v ee 1 s note: 1. this parameter is based on characterization data. electrical specifications (standard settings) over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min typ max unit a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load 4.6k ? reset 30pf v1good , 5v 4.6k ? 30pf v2good , v3good , v4good far 5v pwrgd x80010, x80011, x80012, x80013
6 fn8149.0 january 13, 2005 sense v uv/ov v ov v uv v dd v th mrh gate v oc v oci t vfr t fov t fuv t dpor t vfr 1v 1v figure 1. overvoltage/undervoltage gate timing sense v dd v th gate v oc v oci t dpor t sc_retry t foc t foc always retry v uv < v uv/ov < v ov t sc_retry mrh = high figure 2. overcurrent gate timing eni t to vigood v tripi t delayi i = 1, 2, 3, 4 initial power-up t to v dd enable dc/dc supply figure 3. vigood timings x80010, x80011, x80012, x80013
7 fn8149.0 january 13, 2005 t mrhd gate t mrhe mrh t mrh 1v figure 4. manual reset (hot side) mrh t mrcd pwrgd mrc t mrce t mrc figure 5. manual reset (cold side) mrc pwrgd t delay1 v1good t delay2 v2good t delay3 v3good t delay4 v4good t spor reset t reset _e pwrgd or v drain t glhpg t ghlpg v gate t dlhpg t dhlpg eni any eni low to high (1st occurance) figure 6. reset timings x80010, x80011, x80012, x80013
8 fn8149.0 january 13, 2005 typical performance characteristics figure 7. over current threshold vs temperature figure 8. undervoltage 2 threshold vs temperature figure 9. overvoltage threshold vs temperature figure 10. eni threshold vs temperature figure 11. undervoltage 1 threshold vs temperature figure 12. i gate (source) vs temperature 46.000 47.000 48.000 49.000 50.000 51.000 52.000 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature inrush current limit (mv) 1.690 1.700 1.710 1.720 1.730 1.740 1.750 1.760 1.770 1.780 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling under voltage 2 threshold (v) 3.85 3.86 3.87 3.88 3.89 3.90 3.91 3.92 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling ov threshold (v) 2.475 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature eni threshold (v) 2.190 2.200 2.210 2.220 2.230 2.240 2.250 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling under voltage 1 threshold (v) 0 40 80 120 160 200 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature 150a 70a 50a 10a gate current (a) x80010, x80011, x80012, x80013
9 fn8149.0 january 13, 2005 figure 13. i gate (sink) vs temperature figure 14. t foc vs temperature figure 15. t fuv vs temperature figure 16. t delayi vs temperature figure 17. t fov vs temperature typical performance characteristics (continued) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature gate current - sink (ma) 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t oc (s) 0.500 0.550 0.600 0.650 0.700 0.750 0.800 -55-40-25-10 5 203550658095110125 temperature tuv1 tuv2 t uv (s) 0.90 0.92 0.94 0.96 0.98 1.00 1.02 -55 -35 -15 5 25 45 65 85 temperature t delay (normalized) 1.0 1.1 1.1 1.2 1.2 1.3 1.3 1.4 1.4 -55-40-25-10 5 203550658095110125 temperature t ov (s) x80010, x80011, x80012, x80013
10 fn8149.0 january 13, 2005 figure 18. over current threshold vs temperature figure 19. undervoltage 2 threshold vs temperature figure 20. overvoltage threshold vs temperature figure 21. eni threshold vs temperature figure 22. undervoltage 1 threshold vs temperature figure 23. i gate (source) vs temperature typical performance characteristics (continued) 46.000 47.000 48.000 49.000 50.000 51.000 52.000 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature inrush current limit (mv) 1.690 1.700 1.710 1.720 1.730 1.740 1.750 1.760 1.770 1.780 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling under voltage 2 threshold (v) 3.85 3.86 3.87 3.88 3.89 3.90 3.91 3.92 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling ov threshold (v) 2.475 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature eni threshold (v) 2.190 2.200 2.210 2.220 2.230 2.240 2.250 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling under voltage 1 threshold (v) 0 40 80 120 160 200 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature 150a 70a 50a 10a gate current (a) x80010, x80011, x80012, x80013
11 fn8149.0 january 13, 2005 figure 24. i gate (sink) vs temperature figure 25. t foc vs temperature figure 26. t fuv vs temperature figure 27. t delayi vs temperature figure 28. t fov vs temperature typical performance characteristics (continued) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature gate current - sink (ma) 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t oc (s) 0.500 0.550 0.600 0.650 0.700 0.750 0.800 -55-40-25-10 5 203550658095110125 temperature tuv1 tuv2 t uv (s) 0.90 0.92 0.94 0.96 0.98 1.00 1.02 -55 -35 -15 5 25 45 65 85 temperature t delay (normalized) 1.0 1.1 1.1 1.2 1.2 1.3 1.3 1.4 1.4 -55-40-25-10 5 203550658095110125 temperature t ov (s) x80010, x80011, x80012, x80013
12 fn8149.0 january 13, 2005 sense v ee gate igq1 igq0 drain batt-on mrc mrh reset v dd far pwrgd power good logic slew rate selection 5v reg. v rgo v ee v ee v ee v ov ref v uv1 ref v uv2 ref v uv/ov 2:1 mux v ee gate control v dd 1v ref v rgo v oc ref 38r 3r reset logic and delay v ee over current logic, hard short relay, retry logic status and delay por sequence and timing control logic 50a en1 en2 en3 en4 v4good v3good v2good v1good v ee v ee divider 4 reset osc 0.1s 0.5s 1s 5s select 4 delay1 delay2 delay3 delay4 delay circuit repeated 4 times v rgo figure 29. block diagram x80010, x80011, x80012, x80013
13 fn8149.0 january 13, 2005 pin configuration v1good mrc na1 v3good v2good en4 en3 en1 reset na1 v4good drain pwrgd sense v uv/ov i gq0 v ee gate v dd far batt-on mrh i gq1 na2 1 2 3 4 5 6 7 91011 12 13 14 18 19 20 21 22 23 24 26 27 28 29 30 31 32 x80010, x80011, x80012, x80013 32-lead qfn quad package na2 en2 817 na1 v ee 15 25 v rgo 16 na1 nc nc (7mm x 7mm) pin descriptions pin name description 1v rgo regulated 5v output. used to pull-up user programmable inputs igq0, igq1, batt-on (if needed). 2na1 not available. do not connect to this pin. 3 v4good v4 voltage good output. this open drain output goes low when en4 is less than v trip4 and goes high when en4 is greater than v trip4 . there is a user selectable delay circuitry on this pin. 4en4 v4 voltage enable input. fourth voltage enable pin. if unused connect to v rgo . 5 v3good v3 voltage good output (active low). this open drain output goes low when en3 is less than v trip3 and goes high when en3 is greater than v trip3 . there is a user selectable delay circuitry on this pin. 6en3 v3 voltage enable input. third voltage enable pin. if unused connect to v rgo . 7 v2good v2 voltage good output (active low). this open drain output goes low when en2 is less than v trip2 and goes high when en2 is greater than v trip2 . there is a user selectable delay circuitry on this pin. 8en2 v2 voltage enable input. second voltage enable pin. if unused connect to v rgo . 9v dd positive supply voltage input. 10 v ee negative supply voltage input. 11 v uv/ov analog undervoltage and overvoltage input. turns off the external n-channel mo sfet when there is an undervoltage or overvoltage condition. 12 sense circuit breaker sense input . this input pin detects the overcurrent condition. 13 gate gate drive output. gate drive output for the external n-channel mosfet. 14 drain drain . drain sense input of the external n-channel mosfet. 15 na1 not available. do not connect to this pin. 16 na1 not available. do not connect to this pin. 17 na2 not available. connect to v rgo . 18 na2 not available. connect to v rgo . 19 en1 v1 voltage enable input. first voltage enable pin. if unused connect to v rgo . 20 v1good v1 voltage good output (active low). this open drain output goes low when en1 is less than v trip1 and goes high when en1 is greater than v trip1 . there is a user selectable delay circuitry on this pin. x80010, x80011, x80012, x80013
14 fn8149.0 january 13, 2005 functional description hot circuit insertion when circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board?s power module or dc/dc converter can draw huge transient currents as they charge up (see figure 30). this transient current can cause permanent damage to the board?s components and cause transients on the system power supply. the x80010 is designed to turn on a board?s supply voltage in a controlled manner (see figure 31), allowing the board to be safely inserted or removed from a live backplane. the device also provides undervoltage, overvoltage and overcurrent protection while keeping the power module (dc/dc converter) off until the backplane input voltage is stable and within tolerance. overvoltage and undervoltage shutdown the x80010 provides overvoltage and undervoltage protection circuits. when an overvoltage (v ov ) or undervoltage (v uv1 and v uv2 ) condition is detected, the gate pin immediately pulls low. the undervoltage threshold v uv1 applies to the normal operation with a mains supply. the undervoltage threshold v uv2 assumes the system is powered by a battery. when using a battery backup, the 21 reset reset output. this open drain pin is an active low out put. this pin will be active until pwrgd goes active and the power sequencing is complete. this pin will be released after a programmable delay. 22 na1 not available. do not connect to this pin. 23 mrc manual reset input cold-side. pulling the mrc pin high initiates a system si de reset. the mrc signal must be held high for 5 s. it has an internal pulldown resistor. (>10m ? typical) 24 nc no connect. no internal connections. 25 v ee negative supply voltage input. 26 nc no connect. no internal connections. 27 far failure after re-try (far ) output signal. failure after re-try (far ) is asserted after a number of retries. used for overcurrent and hardshort detection. 28 batt-on battery on input . this input signals that the battery backup (or seconda ry supply) is supplying power to the backplane. it has an internal pulldown resistor. (>10m ? typical) 29 pwrgd power good output. this output pin enables a power module. 30 igq1 gate current quick select bit 1 input. this pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an exter nal fet. it has an internal pulldown resistor. (>10m ? typical) 31 igq0 gate current quick select bit 0 input. this pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an exter nal fet. it has an internal pulldown resistor. (>10m ? typical) 32 mrh manual reset input hot-side. pulling the mrh pin low initiates a gate pin re set (gate pin pulled low). the mrh signal must be held low for 5 s (minimum). pin descriptions (continued) pin name description v dd x80010 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 return 100k -48v dc/dc converter dc/dc converter i inrush x80011 0.1f 100 4.7k 3.3n x80012 x80013 figure 30. typical -48v hotswap application circuit figure 31. typical inrush with gate slew rate control x80010, x80011, x80012, x80013
15 fn8149.0 january 13, 2005 batt-on pin is pulled to v rgo . the default thresholds have been set so the external resistance values in figure 30 provide an overvoltage thres hold of 74.9v (x80010/x80012) or 68v (x80011/x80013), a main undervoltage threshold of 43v and a battery undervoltage threshold of 33.8v. as shown in figure 34, this circuit block contains comparators and voltage references to monitor for a single overvoltage and dual undervoltage trip points. the overvoltage and undervoltage trip points as shown in table 1. a resistor divider connected between the plus and minus input voltages and the v uv/ov pin (see figure 32) determines the overvoltage and undervoltage shutdown voltages and the operating voltage range. using the thresholds in table and the equations of figure 32 the desired operating voltage can be determined. figure 33 shows the resistance values for various operating voltages (x80010 and x80012). battery back up operations an external signal, batt_on is provided to switch the undervoltage trip point. the batt_on signal is a logic high if v ihb > v ee + 4v and is a logic low if v ilb < v ee + 2v. the time from a batt_on input change to a valid new undervoltage threshold is 100ns. see electrical specifications for more details. note: the v uv/ov pin must be limited to less than v ee + 5.5v in worst case conditions. values for r1 and r2 must be chosen such that this condition is met. intersil recommends r1 = 182k ? and r2 = 10k ? to conform to factory settings. table 1. overvoltage/undervoltage default thresholds threshold symbol description falling rising max/min voltage 1 lockout voltage 2 v ov overvoltage (x80010/12) 3.87v 3.9v 74.3 74.9 v ov overvoltage (x80011/13) 3.51v 3.54v 67.4 68 v uv1 undervoltage 1 2.21v 2.24v 43.0 42.4 v uv2 undervoltage 2 1.73v 1.76v 33.8 33.2 notes: 1: max/min voltage is the maximum and minimum operat- ing voltage assuming the recommended v uv/ov resis- tor divider. 2: lockout voltage is the voltage where the x8001x turns off the fet. r1 r2 v p v uv/ov v n voltage divider: or: v uv ov ? v s r2 r1 r2 + ---------------------- ?? ?? = v s v uv ov ? r1 r2 + r2 ---------------------- ?? ?? = v s figure 32. overvoltage undervoltage divider table 2. selecting between undervoltage trip points pin description trip point selection batt_on undervoltage trip point selection pin if batt_on = 0, v uv1 trip point is selected; if batt_on = 1, v uv2 trip point is selected. v uv1 and v uv2 are undervoltage thresholds. batt-on = v ee v ov v uv1 v uv2 operating voltage batt-on = v rgo 100 90 80 70 60 50 40 30 20 10 0 150 158 166 175 182 190 198 206 214 222 operating voltage (v) r1 in k ? (for r2=10k) figure 33. operating voltage vs resistor ratio voltage voltage 2:1 mux voltage -48v v uv/ov batt_on r1 r2 v uv1 v uv2 to gate to gate + - + - + - v ov reference reference reference control control 10k 182k figure 34. overvoltage undervoltage for primary and battery backup x80010, x80011, x80012, x80013
16 fn8149.0 january 13, 2005 overcurrent protection (circuit breaker function) the x80010 over-current circuit provides the following functions: - over-current shut-down of the power fet and external power good indicators. - noise filtering of the current monitor input. - relaxed over-current limits for initial board insertion. - over-current recove ry retry operation. a sense resistor, placed in the supply path between v ee and sense (see figure 30) generates a voltage internal to the x80010. when this voltage exceeds 50mv an over current condition exists and an internal ?circuit breaker? trips, turning off the gate drive to the external fet. the actual over- current level is dependent on th e value of the current sense resistor. for example a 20m ? sense resistor sets the over- current level to 2.5a. intersil?s x80010 provides a safety mechanism during insertion of the board into the back plane. during insertion of the board into the backplane large currents may be induced. in order to prevent prematur e shut down, the overcurrent detect circuit of the x80010 allo ws up to 3 times the standard overcurrent setting during insertion. after the pwrgd signal is asserted, the x80010 switches back to the normal overcurrent setting. the over-current threshold voltage during insertion is 150mv. after the power fet turns off due to an over-current condition, a retry circuit turns the fet back on after a delay of 100ms. if the over-current condition remains, the fet again turns off. for the x80010 and x80012, this sequence repeats indefinitely until the over-current condition is released. for the x80011 and x80013, the x80010 retries five times, then, sets an output signal, far , to indicate a failure after retry. over-current shut-down as shown in figure 35, this circuit block contains a resistor divider, a comparator, a noise filter and a voltage reference to monitor for over-c urrent conditions. the overcurrent voltage threshold (v oc ) is 50mv. this can be factory set, by special or der, to any setting between 30mv and 100mv. v oc is the voltage between the sense and v ee pins and across the r sense resistor. if the selected sense resistor is 20mw, then 50mv corresponds to an overcurrent of 2.5a. if an over-current condition is detected, the gate is turned off and all power good indicators go inactive. overcurrent noise filter the x80010 has a noise (low pass) filter built into the over- current comparator. the comparator will thus require the current spikes to exceed the overcurrent limit for more than 5s. overcurrent du ring insertion insertion is defined as the firs t plug-in of the board to the backplane. in this case, the x 80010 is initially fully powered off prior to the hot plug connection to the mains supply. this condition is different from a si tuation where the mains supply has temporarily failed resulting in a partial recycle of the power. this second condition will be referred to as a power cycle. during insertion, the board can experience high levels of current for short periods of time as power supply capacitors charge up on the power bus. to prevent the over-current sensor from turning off the fet inadvertently, the x80010 has the ability to allow more current to flow through the powerfet and the sense resistor for a short period of time until the fet turns on and the pwrgd signal goes active. in the x80010, 150mv is allow ed across sense resistor the during insertion (10a assuming a 20m ? resistor). this provides a mechanism to reduce insertion issues associated with huge current surges. overcurrent/ gate short-circuit retry logic retry voltage 5s noise 38r 3r + ? -48v overcurrent event r sense reference delay control bl ock filtering figure 35. overcurrent detection/short circuit protection x80010, x80011, x80012, x80013
17 fn8149.0 january 13, 2005 hardshort protection - fet turn-on retry in the event on an over-current or hard short condition, the x80010 includes a retry circuit. this circuit waits for 100ms, then attempts to again turn on the fet. if the fault condition still exists, the fet turns off and the sequence repeats. for the x80010 and x80012, this pr ocess continues indefinitely until the overcurrent condition does not exist. for the x80011 and x80013, this process repeats five times, only then will keep the fet off and set the far pin active. after far is asserted, it can be cleared using the master reset pin, mrh (upon mrh assertion the far output is cleared) or cycling the power on v dd . if an overcurrent condition does not occur on any retry, the gate pin proceeds to open at the user defined slew rate. gate drive output slew rate (inrush current) control the gate output drives an external n-channel fet. the gate pin goes high when no overcurrent, undervoltage or overvoltage conditions exist. the x80010 provides an i gate current of 50a to provide on-chip slew rate control to mi nimize inrush current. this i gate current limits the inrush current and provides the best charge time for a given load, while avoiding overcurrent conditions. for applications that require different ramp rates during insertion and start-up and operations modes, the x80010 provides two external pins, igq1 and igq0, that allow the user to switch to different gate currents on-the-fly by selecting one of four pre-selected i gate currents. when igq0 and igq1 are left unconnected, the gate current is 50a. the other three settings are 10a, 70a and 150a (see figure 36). typically, the delay from igq1 and igq0 selection to a change in the gate pin current is less than 1 s. slew rate (gate) control as shown in figure 37, this circuit block contains a current source (i gate ) that drives the 50a current into the gate pin. this current provides a controlled slew rate for the fet. for applications that require different ramp rates during insertion and operation or for applications where a different gate current is desired, the x80010 provides two external pins, igq1 and igq0, that allo w the system to switch to a different gate current with pre-selected options. the igq1 and igq0 pins can be used to select from one of four set values. typically, the delay from ig q1 and igq0 selection to a change in the gate pin current is less than 1 s. gate capacitor, filtering and feedback in figure 37, the fet control circuit includes an fet feedback capacitor c 2 , which provides compensation for the fet during turn on. the capacitor value depends on the load, the fet gate current, and the maximum desired inrush current. the value of c2 can be selected with the following formula. where: i gate = fet gate current i inrush = maximum desired inrush current c load = dc/dc bulk capacitance inrush current overcurrent i gate i gate = 150a 70a 50a 10a t1 time, ms t2 t3 t4 t5 figure 36. selecting i gate current for slew rate control on the gate pin igq1 pin igq0 pin contents 0 0 defaults to gate current 50 a 0 1 gate current is 10 a 1 0 gate current is 70 a 1 1 gate current is 150 a sense v ee r sense load v dd =12v slew selection gate 10a i inrush drain 100k gate current igq1 igq0 -48v control registers 150a logic rate quick select logic 100* 100nf* * optional components see section ?gate capacitor, filtering and feedback? 22k 3.3nf c2 r2 50a 70a figure 37. slew rate (inrush current) control c2 i gate c load i inrush ------------------------------------------- = x80010, x80011, x80012, x80013
18 fn8149.0 january 13, 2005 with the x80010, there is some control of the gate current with the igq pins, so one selection of c2 can cover a wide range of possible loading conditions. typical values for c2 range from 2.2 to 4.7nf. when power is applie d to the system, the fet tries to turn on due to its internal gate to drain capacitance (cgd) and the feedback capacitor c2 (see figure 37.) the x80010 device, when powered, pulls the gate out put low to prevent the gate voltage from rising and keep the fet from turning on. however, unless v dd powers up very quickly, there will be a brief period of time during initial application of power when the x80010 circuits cannot hold the gate low. the use of an external capacitor (c1) prevents this. capacitors c1 and c2 form a voltage divider to prevent the gate voltage from rising above the fet turn on threshold before the x80010 can hold the gate low. use the following formula for choosing c1. where: v1 = maximum input voltage, v2 = fet threshold voltage, c1 = gate capacitor, c2 = feedback capacitor. in a system where v dd rises very fast, a smaller value of c1 may suffice as the x80010 will control voltage at the gate before the voltage can rise to the fet turn on threshold. the circuit of figure 37 assumes that the input voltage can rise to 80v before the x80010 sees operational voltage on v dd . if c1 is used then the series re sistor r1 will be required to prevent high frequency oscillations. drain sense and power good indicator the x80010 provides a drain sense and power good indicator circuit. the pwrgd signal asserts low when there is no overvoltage, no u ndervoltage, and no overcurrent condition, the gate voltage exceeds vdd-1v, and the voltage at the drain pin is less v ee +v drain . as shown in figure 38, this circuit block contains a drain sense voltage trip point ( ? v drain ) and a gate voltage trip point ( ? v gate ), two comparators, and internal voltage references. these provide both a drain sense and a gate sense circuit to determine the whether the fet has turned on as requested. if so, the power good indicator (pwrgd ) goes active. the drain sense circuit checks the drain pin. if the voltage on this pin is greater that 1v above v ee , then a fault condition exists. the gate sense circuit checks the gate pin. if the voltage on this pin is less than v ee - 1v, then a fault condition exists. the pwrgd signal asserts (logic low) only when all of the below conditions are true: - there is no overvoltage or no undervoltage condition, (i.e. undervoltage < v ee < overvoltage.) - there is no overcurrent condition (i.e. v ee - v sense < v oc .) - the fet is turned on (i.e. v drain < v ee + 1v and v gate > v dd - 1v). power on/system reset and delay application of power to the x80010 activates a power on reset circuit that pulls the reset pin active. this signal, if used, provides several benefits. - it prevents the system microprocessor from starting to operate with insufficient voltage. - it prevents the processor from operating prior to stabilization of the oscillator. - it allows time for an fpga to download its configuration prior to initialization of the circuit. the por/reset circuit is acti vated when all voltages are within specified ranges and the following time-out conditions are met: pwrgd and v1good , v2good , v3good, and v4good . the por/reset circuit will then wait 100ms and assert the reset pin. c1 v1 v2 ? v2 --------------------- c 2 = (factory programmable) sense v ee r sense load gate drain 100k -48v pwrgd + ? 1v v ee control/status registers power good logic ? v drain + ? vdd-1v ? v gate figure 38. drain sense and power good indicator x80010, x80011, x80012, x80013
19 fn8149.0 january 13, 2005 quad voltage monitoring x80010 monitors 4 voltage enable inputs. when the eni (i=1-4) input is detected to be below the input threshold, the output vigood (i = 1 to 4) goes active low. the vigood signal is asserted after a delay of 100ms. the vigood signal remains active until eni rises above threshold. once the pwrgd signal is asserted, the power sequencing of the dc/dc module s can commence. reset goes active 100ms after all vigood (i=1 to 4) outputs are asserted (see figure 39). as shown in figure 40, this circuit block contains four separate voltage enable pins, a time delay circuit, and an output driver. control registers reset logic spor mrc v dd drain sense & power good logic enable logic t spor delay reset pwrgd vigood i = 1 to 4 p v ee figure 39. power on/system reset and delay en1 en2 en3 en4 v4good v3good v2good v1good v ee divider 4 reset osc 0.1s 0.5s 1s 5s select 4 delay1 delay2 delay3 delay4 delay circuit repeated 4 times v rgo control register figure 40. voltage monitors and vgood outputs x80010, x80011, x80012, x80013
20 fn8149.0 january 13, 2005 manual reset (hot side and cold side) the manual reset option allows a hardware reset of either the gate control or the pwrgd indicator. these can be used to recover the system in the event of an abnormal operating condition.the x80010 has two manual reset pins: mrh (manual reset hot side) and mrc (manual reset cold side). the mrh signal is used as a manual reset for the gate pin. this pin is used to initiate soft reinsert. when mrh is pulled low the gate pin will be pulled low. it also clears the far signal. when the mrh pin goes high, it removes the override signal and the gate will turn on based on the selected gate control mechanism. the mrc signal is used as a manual reset for the pwrgd signal. this pin is used to initiate a soft restart. when the mrc is pulled high, the pwrgd signal is pulled high. when mrc pin goes low, the pwrgd pin goes operational. it will go low if all constraints on the gate are within limits. flexible power sequencing of multiple power supplies the x80010 provides several circuits such as multiple voltage enable pins, programmable delays, and a power good signals can be used to set up flexible power sequencing schemes for downstream dc/dc supplies. below are examples of parallel and relay sequencing. 1. power up of dc/dc supplies in parallel sequencing using programmable delays on power good (see figure 41 and figure 42). several dc/dc power supplies and their respective power up start times can be controlled using the x80010 such that each of the dc/dc power supplies will start up following the issue of the pwrgd signal. the pwrgd signal is fed into the eni inputs to the x80010. when pwrgd is valid, the internal voltage enable circuits issue vigood signals after a time delay. the vigood signals control the on /off pins of the dc/dc supplies. each dc/dc converter is instructed to turn on 100ms after the pwrgd goes active. however, each vigood delay can be increased with the use of external r-c circuits. table 3. manual reset of the hot side (gate signal) mrh gate pin requirements 1 operational when mrh is high the manual reset (hot) function is disabled 0offmrh must be held low minimum of 5 s table 4. manual reset of the cold side (pwrgd signal) mrc pwrgd requirements 1 high mrc must be held high minimum of 5 s 0 operational when mrc is low the mrc function is disabled x80010, x80011, x80012, x80013
21 fn8149.0 january 13, 2005 v dd v3good en3 v2good en2 v1good en1 pwrgd x80010, x80011, v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% on /off c3 0.1f 100v c4 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 reset c v cc1 3.3v gnd on /off c6 0.1f 100v c7 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 fpga v cc1 2.5v gnd on /off c9 0.1f 100v c10 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 asic v cc1 1.8v gnd r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 c5 100f 16v c8 100f 16v c11 100f 16v + + + v4good en4 on /off c12 0.1f 100v c13 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.2v gnd c14 100f 16v + reset opto coupler pwrgd reset ? v cc2 v cc2 v cc2 mrh mrc return opto coupler 0.1f 100 4.7k 3.3n 100k figure 41. typical application of hotswa p and dc/dc parallel power sequencing x80013, x80014 x80010, x80011, x80012, x80013
22 fn8149.0 january 13, 2005 1. power up of dc/dc supplies via relay sequencing using power good and voltage monitors (see figure 43 and figure 44). several dc/dc power supplies and their respective power up start times can be controlled using the x80010 such that each of the dc/dc power supplies will start in a relay sequencing fashion. the 1st dc/dc supply will power up when pwrgd is low after a 100ms delay. subsequent dc/dc supplies will power up after the prior supply has reached its operating voltage. one way to do this is by using an external cpu supervisor (for example the intersil x40430) to monitor the dc/dc output. when the dc/dc voltage is good, the supervisor output signals the x80010 en1 input to sequence the next supply. an opto-coupler is recommended in this connection for isolation. this configur ation ensures that each subsequent dc/dc supply will power up after the preceding dc/dc supply voltage output is valid. en1 t delay1 v1gdo power supply #1 turns on power supply v2gdo 100ms v3gdo #1 output t delay2 t delay3 power supply #2 output power supply #3 output t delay4 v4gdo (from pwrgd ) (3.3v) (2.5v) (1.8v) reset main fet turns on en2 en3 power supply #4 output (1.2v) en4 power supply #2 turns on 100ms power supply #3 turns on 100ms power supply #4 turns on 100ms 100ms t spor all vigood=low (from pwrgd ) (from pwrgd ) (from pwrgd ) figure 42. parallel sequencing of dc/dc supplies. (timing) x80010, x80011, x80012, x80013
23 fn8149.0 january 13, 2005 v dd v3good en3 v2good en2 v1good en1 pwrgd x80010, x80011, v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% 100 on /off c3 0.1f 100v c4 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 3.3v gnd on /off c6 0.1f 100v c7 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 2.5v gnd on /off c9 0.1f 100v c10 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.8v gnd r4 182k 1% r6 10k 1% q1 irfr120 c5 100f 16v c8 100f 16v c11 100f 16v + + + v4good en4 on /off c12 0.1f 100v c13 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.2v gnd c14 100f 16v + reset opto coupler reset x40430 opto coupler vmon<1:3> vfail<1:3> pwrgd reset c v cc1 fpga v cc1 asic v cc1 v cc2 v cc2 v cc2 mrh mrc r5 30k 1% return opto coupler 0.1f 4.7k 3.3n 100k figure 43. typical application of hotswap and dc/dc relay sequencing x80012, x80013 x80010, x80011, x80012, x80013
24 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8149.0 january 13, 2005 en2 in t delay1 v1gdo power supply #1 turns on power supply v2mon threshold power supply #3 turns on v2gdo 100ms v3gdo #1 output 100ms t delay2 power supply #2 turns on v3mon threshold 100ms t delay3 power supply #2 output v4mon power supply #3 output threshold t delay4 v4gdo (from pwrgd ) (3.3v) (2.5v) (1.8v) t reset reset 100ms 100ms fet turns on en2 en3 power supply #4 output (1.2v) en4 power supply #4 turns on figure 44. relay sequencing of dc/dc supplies. (timing) x80010, x80011, x80012, x80013
25 fn8149.0 january 13, 2005 packaging information 0.009 (0.23) 0.015 (0.38) 0.185 (4.70) 0.271 (6.90) 0.279 (7.10) 0.014 (0.35) 0.029 (0.75) (4.70) 0.185 (4.70) 0.027 (0.70) 0.031 (0.80) 0.000 (0.00) 0.030 (0.76) 0.007 (0.19) 0.009 (0.25) 0.000 (0.00) 0.002 (0.05) 0.271 (6.90) 0.279 (7.10) 0.271 (6.90) 0.279 (7.10) pin 1 indent 32-lead very very thin quad flat no lead package 7mm x 7mm body with 0.65mm lead pitch x80010, x80011, x80012, x80013

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