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revision date: mar. 15 , 2006 16 h8/36049 group hardware manual renesas 16-bit single-chip microcomputer h8 family/h8/300h tiny series h8/36049f hd64f36049, hd64f36049g, h8/36049 hd64336049, hd64336049g, h8/36048 hd64336048, hd64336048g, h8/36047 hd64336047, hd64336047g rev.3.00 rej09b0060-0300
rev. 3.00 mar. 15, 2006 page ii of xxxii
rev. 3.00 mar. 15, 2006 page iii of xxxii 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev. 3.00 mar. 15, 2006 page iv of xxxii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed.
rev. 3.00 mar. 15, 2006 page v of xxxii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index
rev. 3.00 mar. 15, 2006 page vi of xxxii preface the h8/36049 group comprises single-chip microcomputers made up of the high-speed h8/300h cpu as their cores, and the peri pheral functions required to configure a system. the h8/300h cpu has an instruction set that is compatible with the h8/300 cpu. target users: this manual was written for users who will be using the h8/36049 group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to expl ain the hardware functions and electrical characteristics of th e h8/36049 group to the target users. refer to the h8/300h series software ma nual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the h8/300h series software manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 22, list of registers. example: register name: the following notatio n is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. number notation: binary is b'xxxx, hexadecimal is h'xxxx, and decimal is xxxx. signal notation: an overbar is added to a low-active signal: xxxx
rev. 3.00 mar. 15, 2006 page vii of xxxii notes: when using an on-chip emulator (e7 or e8) for h8/36049 group program development and debugging, the following restrictions must be noted. 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 2. pins p85, p86, and p87 cannot be used. 3. area h'fff780 to h'fffb7f must on no account be accessed. 4. when the e7 or e8 is used, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7 or e8, the address break control registers must not be accessed. 5. when the e7 or e8 is used, nmi is an input/output pin (open-drain in output mode), p85 and p87 are input pins, and p86 is an output pin. 6. in on-board programming mode by boot mode, channel 1 (p21/rxd and p22/txd) for sci3 is used. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ h8/36049 group manuals: document title document no. h8/36049 group hardware manual this manual h8/300h series software manual rej09b0213 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0058 h8s, h8/300 series simulator/debugger user's manual rej10b0211 h8s, h8/300 series high-performance embedded workshop 3 tutorial rej10b0024 h8s, h8/300 series high-performance embe dded workshop 3 user's manual rej10b0026
rev. 3.00 mar. 15, 2006 page viii of xxxii application notes: document title document no. h8s, h8/300 series c/c++ compiler package application note rej05b0464 single power supply f-ztat tm on-board programming rej05b0520
rev. 3.00 mar. 15, 2006 page ix of xxxii contents section 1 overview................................................................................................1 1.1 features....................................................................................................................... .......... 1 1.2 internal bloc k diagram......................................................................................................... 3 1.3 pin arrangement ................................................................................................................ ... 4 1.4 pin functions .................................................................................................................. ...... 5 section 2 cpu........................................................................................................9 2.1 address space and memory map ....................................................................................... 10 2.2 register conf iguratio n........................................................................................................ 1 1 2.2.1 general registers................................................................................................ 12 2.2.2 program counter (pc) ........................................................................................ 13 2.2.3 condition-code re gister (ccr)......................................................................... 13 2.3 data formats................................................................................................................... .... 15 2.3.1 general register data formats ........................................................................... 15 2.3.2 memory data formats ........................................................................................ 17 2.4 instruction set ................................................................................................................ ..... 18 2.4.1 list of instructions cl assified by function ......................................................... 18 2.4.2 basic instructio n formats ................................................................................... 27 2.5 addressing modes and effec tive address ca lculation....................................................... 28 2.5.1 addressing modes .............................................................................................. 28 2.5.2 effective address calculation ............................................................................ 31 2.6 basic bus cycle ................................................................................................................ .. 33 2.6.1 access to on-chip me mory (ram, rom)........................................................ 33 2.6.2 on-chip peripheral modules .............................................................................. 34 2.7 cpu states ..................................................................................................................... ..... 35 2.8 usage notes .................................................................................................................... .... 36 2.8.1 notes on data acce ss to empty areas ............................................................... 36 2.8.2 eepmov instru ction.......................................................................................... 36 2.8.3 bit manipulation instruction............................................................................... 37 section 3 exception handling .............................................................................43 3.1 exception sources and vector address .............................................................................. 44 3.2 register de scriptions.......................................................................................................... 46 3.2.1 interrupt edge select register 1 (iegr1) .......................................................... 47 3.2.2 interrupt edge select register 2 (iegr2) .......................................................... 48 3.2.3 interrupt enable regi ster 1 (ienr1) .................................................................. 49
rev. 3.00 mar. 15, 2006 page x of xxxii 3.2.4 interrupt enable regi ster 2 (ienr2) .................................................................. 50 3.2.5 interrupt flag register 1 (irr1)......................................................................... 50 3.2.6 interrupt flag register 2 (irr2)......................................................................... 52 3.2.7 wakeup interrupt flag register (iwpr) ............................................................ 53 3.3 reset exceptio n handling .................................................................................................. 54 3.4 interrupt exception handling ............................................................................................. 55 3.4.1 external interrupts .............................................................................................. 55 3.4.2 internal interrupts ............................................................................................... 57 3.4.3 interrupt handling sequence .............................................................................. 57 3.4.4 interrupt response time..................................................................................... 59 3.5 usage notes .................................................................................................................... .... 61 3.5.1 interrupts after reset........................................................................................... 61 3.5.2 notes on stack area use .................................................................................... 61 3.5.3 notes on rewriting port mode registers ........................................................... 61 section 4 address break ..................................................................................... 63 4.1 register de scriptions.......................................................................................................... 64 4.1.1 address break control register (a brkcr) ..................................................... 64 4.1.2 address break status register (a brksr) ........................................................ 66 4.1.3 break address registers e, h, l (bare, barh, barl) ................................ 66 4.1.4 break data registers h, l (bdrh, bdrl)....................................................... 66 4.2 operation ...................................................................................................................... ...... 67 section 5 clock pulse generators ....................................................................... 69 5.1 system clock generator ..................................................................................................... 70 5.1.1 connecting crysta l resona tor ............................................................................ 70 5.1.2 connecting cerami c resonator .......................................................................... 71 5.1.3 external clock input me thod.............................................................................. 71 5.2 subclock generator ............................................................................................................ 7 2 5.2.1 connecting 32.768-khz cr ystal resonator ........................................................ 72 5.2.2 pin connection when no t using s ubclock.......................................................... 73 5.3 prescalers ..................................................................................................................... ....... 73 5.3.1 prescaler s .......................................................................................................... 73 5.3.2 prescaler w......................................................................................................... 73 5.4 usage notes .................................................................................................................... .... 74 5.4.1 notes on resonators ........................................................................................... 74 5.4.2 notes on board design ....................................................................................... 74
rev. 3.00 mar. 15, 2006 page xi of xxxii section 6 power-down modes ............................................................................75 6.1 register de scriptions.......................................................................................................... 75 6.1.1 system control regi ster 1 (syscr1) ................................................................ 76 6.1.2 system control regi ster 2 (syscr2) ................................................................ 77 6.1.3 module standby control register 1 (mstcr1) ................................................ 79 6.1.4 module standby control register 2 (mstcr2) ................................................ 80 6.2 mode transitions and states of lsi.................................................................................... 81 6.2.1 sleep mode ......................................................................................................... 84 6.2.2 standby mode ..................................................................................................... 84 6.2.3 subsleep mode.................................................................................................... 85 6.2.4 subactive mode .................................................................................................. 85 6.3 operating frequency in active mode................................................................................. 86 6.4 direct tr ansition .............................................................................................................. ... 86 6.4.1 direct transition from active mode to suba ctive mode.................................... 86 6.4.2 direct transition from subac tive mode to ac tive mode.................................... 87 6.5 module standby function................................................................................................... 87 section 7 rom ....................................................................................................89 7.1 block confi guratio n ........................................................................................................... 9 0 7.2 register de scriptions.......................................................................................................... 91 7.2.1 flash memory control re gister 1 (flmcr1).................................................... 91 7.2.2 flash memory control re gister 2 (flmcr2).................................................... 92 7.2.3 erase block register 1 (ebr1) .......................................................................... 93 7.2.4 flash memory power contro l register (flpwcr) ........................................... 94 7.2.5 flash memory enable register (fenr) ............................................................. 94 7.3 on-board progra mming modes.......................................................................................... 95 7.3.1 boot mode .......................................................................................................... 95 7.3.2 programming/erasing in user program mode.................................................... 98 7.4 flash memory progra mming/erasing............................................................................... 100 7.4.1 program/progra m-verify .................................................................................. 100 7.4.2 erase/erase- verify............................................................................................ 103 7.4.3 interrupt handling when progra mming/erasing flash memory....................... 103 7.5 program/erase pr otection ................................................................................................. 105 7.5.1 hardware protection ......................................................................................... 105 7.5.2 software protection........................................................................................... 105 7.5.3 error protection................................................................................................. 105 7.6 programmer mode ............................................................................................................ 106 7.7 power-down states fo r flash memory............................................................................. 106
rev. 3.00 mar. 15, 2006 page xii of xxxii section 8 ram .................................................................................................. 109 section 9 i/o ports............................................................................................. 111 9.1 port 1......................................................................................................................... ........ 111 9.1.1 port mode regist er 1 (pmr1) .......................................................................... 112 9.1.2 port control regist er 1 (pcr1) ........................................................................ 113 9.1.3 port data regist er 1 (pdr1) ............................................................................ 113 9.1.4 port pull-up control re gister 1 (pucr1)........................................................ 114 9.1.5 pin functions .................................................................................................... 114 9.2 port 2......................................................................................................................... ........ 116 9.2.1 port control regist er 2 (pcr2) ........................................................................ 117 9.2.2 port data regist er 2 (pdr2) ............................................................................ 117 9.2.3 port mode regist er 3 (pmr3) .......................................................................... 118 9.2.4 pin functions .................................................................................................... 118 9.3 port 3......................................................................................................................... ........ 120 9.3.1 port control regist er 3 (pcr3) ........................................................................ 120 9.3.2 port data regist er 3 (pdr3) ............................................................................ 121 9.3.3 pin functions .................................................................................................... 121 9.4 port 5......................................................................................................................... ........ 123 9.4.1 port mode regist er 5 (pmr5) .......................................................................... 124 9.4.2 port control regist er 5 (pcr5) ........................................................................ 125 9.4.3 port data regist er 5 (pdr5) ............................................................................ 125 9.4.4 port pull-up control re gister 5 (pucr5)........................................................ 126 9.4.5 pin functions .................................................................................................... 126 9.5 port 6......................................................................................................................... ........ 129 9.5.1 port control regist er 6 (pcr6) ........................................................................ 129 9.5.2 port data regist er 6 (pdr6) ............................................................................ 130 9.5.3 pin functions .................................................................................................... 130 9.6 port 7......................................................................................................................... ........ 134 9.6.1 port control regist er 7 (pcr7) ........................................................................ 134 9.6.2 port data regist er 7 (pdr7) ............................................................................ 135 9.6.3 pin functions .................................................................................................... 135 9.7 port 8......................................................................................................................... ........ 137 9.7.1 port control regist er 8 (pcr8) ........................................................................ 138 9.7.2 port data regist er 8 (pdr8) ............................................................................ 138 9.7.3 pin functions .................................................................................................... 139 9.8 port 9......................................................................................................................... ........ 141 9.8.1 port control regist er 9 (pcr9) ........................................................................ 142 9.8.2 port data regist er 9 (pdr9) ............................................................................ 142 9.8.3 pin functions .................................................................................................... 143
rev. 3.00 mar. 15, 2006 page xiii of xxxii 9.9 port b ......................................................................................................................... ....... 145 9.9.1 port data regist er b (pdrb) ........................................................................... 145 section 10 realtime clock (rtc) .....................................................................147 10.1 features....................................................................................................................... ...... 147 10.2 input/output pin ............................................................................................................... 148 10.3 register desc riptions........................................................................................................ 14 8 10.3.1 second data register/free running c ounter data register (rsecdr) ......... 149 10.3.2 minute data regist er (rmindr)..................................................................... 150 10.3.3 hour data regist er (rhrdr) .......................................................................... 151 10.3.4 day-of-week data regi ster (rwkdr) ........................................................... 152 10.3.5 rtc control register 1 (rtccr1).................................................................. 153 10.3.6 rtc control register 2 (rtccr2).................................................................. 155 10.3.7 clock source select re gister (rt ccsr) ......................................................... 156 10.4 operation ...................................................................................................................... .... 157 10.4.1 initial settings of regist ers after po wer-on ..................................................... 157 10.4.2 initial setting pr ocedure ................................................................................... 157 10.4.3 data reading pr ocedure ................................................................................... 158 10.5 interrupt sources.............................................................................................................. .159 section 11 timer b1 ..........................................................................................161 11.1 features....................................................................................................................... ...... 161 11.2 input/output pin ............................................................................................................... 161 11.3 register desc riptions........................................................................................................ 16 2 11.3.1 timer mode register b1 (tmb1) .................................................................... 162 11.3.2 timer counter b1 (tcb1)................................................................................ 163 11.3.3 timer load register b1 (tlb1) ...................................................................... 163 11.4 operation ...................................................................................................................... .... 163 11.4.1 interval timer operation .................................................................................. 163 11.4.2 auto-reload timer operation .......................................................................... 164 11.4.3 event counter op eration .................................................................................. 164 11.5 timer b1 operating modes .............................................................................................. 164 section 12 timer v............................................................................................165 12.1 features....................................................................................................................... ...... 165 12.2 input/output pins.............................................................................................................. 167 12.3 register desc riptions........................................................................................................ 16 7 12.3.1 timer counter v (tcntv) .............................................................................. 167 12.3.2 time constant registers a, b (tcora, tcorb) .......................................... 168 12.3.3 timer control regist er v0 (tcrv0) ............................................................... 169
rev. 3.00 mar. 15, 2006 page xiv of xxxii 12.3.4 timer control/status regi ster v (tcsrv) ...................................................... 170 12.3.5 timer control regist er v1 (tcrv1) ............................................................... 172 12.4 operation ...................................................................................................................... .... 173 12.4.1 timer v operation............................................................................................ 173 12.5 timer v applicati on examples ........................................................................................ 176 12.5.1 pulse output with arbi trary duty cycle........................................................... 176 12.5.2 pulse output with arbitrary pulse wi dth and delay from trgv input .......... 177 12.6 usage notes .................................................................................................................... .. 178 section 13 timer w........................................................................................... 181 13.1 features....................................................................................................................... ...... 181 13.2 input/output pins.............................................................................................................. 184 13.3 register desc riptions........................................................................................................ 18 4 13.3.1 timer mode regist er w (tmrw) ................................................................... 185 13.3.2 timer control regist er w (tcrw) ................................................................. 186 13.3.3 timer interrupt enable re gister w (tierw) .................................................. 187 13.3.4 timer status regist er w (tsrw) .................................................................... 188 13.3.5 timer i/o control regi ster 0 (tio r0) ............................................................. 189 13.3.6 timer i/o control regi ster 1 (tio r1) ............................................................. 191 13.3.7 timer counter (tcnt)..................................................................................... 192 13.3.8 general registers a to d (gra to grd)......................................................... 193 13.4 operation ...................................................................................................................... .... 194 13.4.1 normal operation ............................................................................................. 194 13.4.2 pwm opera tion................................................................................................ 199 13.5 operation timing.............................................................................................................. 2 04 13.5.1 tcnt count timing ........................................................................................ 204 13.5.2 output compar e timing ................................................................................... 205 13.5.3 input capture timing........................................................................................ 206 13.5.4 timing of counter clearin g by compare match .............................................. 206 13.5.5 buffer operatio n timing .................................................................................. 207 13.5.6 timing of imfa to imfd flag setting at comp are match ............................. 208 13.5.7 timing of imfa to imfd se tting at input capture ......................................... 209 13.5.8 timing of status flag clearing......................................................................... 209 13.6 usage notes .................................................................................................................... .. 210 section 14 timer z............................................................................................ 213 14.1 features....................................................................................................................... ...... 213 14.2 input/output pins.............................................................................................................. 218 14.3 register desc riptions........................................................................................................ 21 9 14.3.1 timer start regist er (tstr) ............................................................................ 220
rev. 3.00 mar. 15, 2006 page xv of xxxii 14.3.2 timer mode regist er (tmdr) ......................................................................... 221 14.3.3 timer pwm mode regi ster (tpmr) ............................................................... 222 14.3.4 timer function control register (t fcr)......................................................... 223 14.3.5 timer output master enab le register (toer) ................................................ 225 14.3.6 timer output control register (t ocr) ........................................................... 227 14.3.7 timer counter (tcnt)..................................................................................... 228 14.3.8 general registers a, b, c, and d (gra, grb, grc, and grd).................... 228 14.3.9 timer control regi ster (t cr).......................................................................... 229 14.3.10 timer i/o control register (tiora and tiorc)............................................ 230 14.3.11 timer status regi ster (tsr)............................................................................. 232 14.3.12 timer interrupt enable register (tier) ........................................................... 234 14.3.13 pwm mode output level cont rol register (pocr) ....................................... 235 14.3.14 interface with cpu ........................................................................................... 236 14.4 operation ...................................................................................................................... .... 237 14.4.1 counter operation............................................................................................. 237 14.4.2 waveform output by compare ma tch.............................................................. 241 14.4.3 input capture function ..................................................................................... 244 14.4.4 synchronous op eration..................................................................................... 247 14.4.5 pwm mode ...................................................................................................... 248 14.4.6 reset synchronou s pwm mode ....................................................................... 254 14.4.7 complementary pwm mode............................................................................ 258 14.4.8 buffer operation ............................................................................................... 268 14.4.9 timer z output timing .................................................................................... 276 14.5 interrupts..................................................................................................................... ...... 278 14.5.1 status flag se t timing...................................................................................... 278 14.5.2 status flag clear ing timi ng ............................................................................. 280 14.6 usage notes .................................................................................................................... .. 281 section 15 watchdog timer ..............................................................................289 15.1 features....................................................................................................................... ...... 289 15.2 register desc riptions........................................................................................................ 29 0 15.2.1 timer control/status regi ster wd (tcsrwd)............................................... 290 15.2.2 timer counter wd (tcwd)............................................................................ 292 15.2.3 timer mode register wd (tmwd) ................................................................ 292 15.3 operation ...................................................................................................................... .... 293 section 16 14-bit pwm.....................................................................................295 16.1 features....................................................................................................................... ...... 295 16.2 input/output pin ............................................................................................................... 295 16.3 register desc riptions........................................................................................................ 29 6
rev. 3.00 mar. 15, 2006 page xvi of xxxii 16.3.1 pwm control regist er (pwcr) ...................................................................... 296 16.3.2 pwm data registers u, l (pwdru, pwdrl) .............................................. 297 16.4 operation ...................................................................................................................... .... 297 section 17 serial communication interface 3 (sci3)....................................... 299 17.1 features....................................................................................................................... ...... 299 17.2 input/output pins.............................................................................................................. 303 17.3 register desc riptions........................................................................................................ 30 3 17.3.1 receive shift regi ster (rsr) ........................................................................... 303 17.3.2 receive data regi ster (rdr)........................................................................... 303 17.3.3 transmit shift regi ster (tsr) .......................................................................... 304 17.3.4 transmit data regi ster (tdr).......................................................................... 304 17.3.5 serial mode regi ster (smr) ............................................................................ 304 17.3.6 serial control regi ster 3 (scr3) ..................................................................... 306 17.3.7 serial status regi ster (ssr) ............................................................................. 307 17.3.8 bit rate regist er (brr) ................................................................................... 309 17.4 operation in asynch ronous mode .................................................................................... 318 17.4.1 clock................................................................................................................. 318 17.4.2 sci3 initiali zation............................................................................................. 319 17.4.3 data transmission ............................................................................................ 320 17.4.4 serial data reception ....................................................................................... 322 17.5 operation in clocked synchronous mode ........................................................................ 326 17.5.1 clock................................................................................................................. 326 17.5.2 sci3 initiali zation............................................................................................. 326 17.5.3 serial data tr ansmission .................................................................................. 327 17.5.4 serial data reception (clock ed synchronous mode) ...................................... 329 17.5.5 simultaneous serial data tran smission and reception.................................... 331 17.6 multiprocessor communi cation func tion ........................................................................ 332 17.6.1 multiprocessor serial da ta transmission ......................................................... 334 17.6.2 multiprocessor serial data reception .............................................................. 335 17.7 interrupt reques ts............................................................................................................. 338 17.8 usage notes .................................................................................................................... .. 339 17.8.1 break detection an d processing ....................................................................... 339 17.8.2 mark state and br eak sending ......................................................................... 339 17.8.3 receive error flags and transmit operations (clocked synchronous mode only).................................................................. 339 17.8.4 receive data sampling timing and reception margin in asynchronous mode ................................................................................................................. 340
rev. 3.00 mar. 15, 2006 page xvii of xxxii section 18 i 2 c bus interface 2 (iic2) ................................................................341 18.1 features....................................................................................................................... ...... 341 18.2 input/output pins.............................................................................................................. 343 18.3 register desc riptions........................................................................................................ 34 4 18.3.1 i 2 c bus control regist er 1 (iccr1 )................................................................. 344 18.3.2 i 2 c bus control regist er 2 (iccr2 )................................................................. 347 18.3.3 i 2 c bus mode regist er (icmr)........................................................................ 348 18.3.4 i 2 c bus interrupt enable register (i cier) ....................................................... 350 18.3.5 i 2 c bus status regi ster (icsr)......................................................................... 352 18.3.6 slave address regi ster (sar).......................................................................... 355 18.3.7 i 2 c bus transmit data re gister (icdrt)......................................................... 356 18.3.8 i 2 c bus receive data re gister (icd rr).......................................................... 356 18.3.9 i 2 c bus shift regist er (icdrs)........................................................................ 356 18.4 operation ...................................................................................................................... .... 357 18.4.1 i 2 c bus format.................................................................................................. 357 18.4.2 master transmit operation ............................................................................... 358 18.4.3 master receive operatio n................................................................................. 360 18.4.4 slave transmit op eration ................................................................................. 362 18.4.5 slave receive op eration................................................................................... 364 18.4.6 clocked synchronous serial format................................................................. 366 18.4.7 noise canceller................................................................................................. 368 18.4.8 example of use................................................................................................. 369 18.5 interrupts..................................................................................................................... ...... 373 18.6 bit synchronous circuit.................................................................................................... 374 18.7 usage notes .................................................................................................................... .. 375 18.7.1 issue (retransmission) of start/stop co nditions .............................................. 375 18.7.2 wait setting in i 2 c bus mode regist er (icmr) ............................................ 375 section 19 a/d converter..................................................................................377 19.1 features....................................................................................................................... ...... 377 19.2 input/output pins.............................................................................................................. 379 19.3 register desc riptions........................................................................................................ 38 0 19.3.1 a/d data registers a to d (addra to addrd) .......................................... 380 19.3.2 a/d control/status regi ster (adcsr) ............................................................ 381 19.3.3 a/d control regist er (adcr) ......................................................................... 382 19.4 operation ...................................................................................................................... .... 384 19.4.1 single mode...................................................................................................... 384 19.4.2 scan mode ........................................................................................................ 384 19.4.3 input sampling and a/d conversion time ...................................................... 385
rev. 3.00 mar. 15, 2006 page xviii of xxxii 19.4.4 external trigger input timi ng.......................................................................... 386 19.5 a/d conversion accura cy definitions ............................................................................. 387 19.6 usage notes .................................................................................................................... .. 390 19.6.1 permissible signal s ource impedance .............................................................. 390 19.6.2 influences on abso lute accuracy ..................................................................... 390 section 20 power-on reset and lo w-voltage detection circuits (optional) ........................................................................................ 391 20.1 features....................................................................................................................... ...... 391 20.2 register desc riptions........................................................................................................ 39 3 20.2.1 low-voltage-detection contro l register (lvdcr)........................................ 393 20.2.2 low-voltage-detection status register (lvdsr)........................................... 395 20.3 operation ...................................................................................................................... .... 396 20.3.1 power-on reset circuit .................................................................................... 396 20.3.2 low-voltage detec tion circuit......................................................................... 397 section 21 power supply circuit ...................................................................... 401 21.1 when using internal power su pply step-down circuit .................................................. 401 21.2 when not using internal power supply step-dow n circuit ........................................... 402 section 22 list of registers............................................................................... 403 22.1 register addresses (a ddress order)................................................................................. 404 22.2 register bits .................................................................................................................. ... 411 22.3 register states in ea ch operating mode .......................................................................... 417 section 23 electrical characteristics ................................................................. 423 23.1 absolute maximum ratings ............................................................................................. 423 23.2 electrical characteristics (f-ztat tm version)................................................................. 423 23.2.1 power supply voltage an d operating ranges .................................................. 423 23.2.2 dc character istics ............................................................................................ 426 23.2.3 ac character istics ............................................................................................ 433 23.2.4 a/d converter char acteristic s.......................................................................... 437 23.2.5 watchdog timer ch aracteristic s....................................................................... 438 23.2.6 flash memory char acteristi cs .......................................................................... 439 23.2.7 power-supply-voltage detection circ uit characteristics (optional) ............... 441 23.2.8 power-on reset circuit char acteristics (op tional).......................................... 442 23.3 electrical characteristics (masked rom version)........................................................... 442 23.3.1 power supply voltage an d operating ranges .................................................. 442 23.3.2 dc character istics ............................................................................................ 445 23.3.3 ac character istics ............................................................................................ 452
rev. 3.00 mar. 15, 2006 page xix of xxxii 23.3.4 a/d converter char acteristic s .......................................................................... 456 23.3.5 watchdog timer ch aracteristic s....................................................................... 457 23.3.6 power-supply-voltage detection circ uit characteristics (optional) ............... 458 23.3.7 power-on reset circuit char acteristics (opt ional) .......................................... 459 23.4 operation timing.............................................................................................................. 4 59 23.5 output load condition ..................................................................................................... 461 appendix..............................................................................................................463 a. instruction set ................................................................................................................ ... 463 a.1 instruction list...................................................................................................... 463 a.2 operation code map............................................................................................. 478 a.3 number of execu tion stat es ................................................................................. 481 a.4 combinations of instructions and addressing modes .......................................... 492 b. i/o ports...................................................................................................................... ...... 493 b.1 i/o port block diagrams ...................................................................................... 493 b.2 port states in each operating mode ..................................................................... 511 c. product code lineup ........................................................................................................ 512 d. package dime nsions ......................................................................................................... 513 main revisions and additions in this edition .....................................................515 index ....................................................................................................................521
rev. 3.00 mar. 15, 2006 page xx of xxxii
rev. 3.00 mar. 15, 2006 page xxi of xxxii figures section 1 overview figure 1.1 internal block diagram ............................................................................................ ..... 3 figure 1.2 pin arrangements (fp-80a)......................................................................................... .4 section 2 cpu figure 2.1 memory map........................................................................................................ ....... 10 figure 2.2 cpu regi sters ..................................................................................................... ........ 11 figure 2.3 usage of general registers ........................................................................................ .12 figure 2.4 relationship between stack pointer an d stack area ................................................... 13 figure 2.5 general regi ster data formats (1).............................................................................. 15 figure 2.5 general regi ster data formats (2).............................................................................. 16 figure 2.6 memo ry data formats............................................................................................... .. 17 figure 2.7 inst ruction formats............................................................................................... ....... 27 figure 2.8 branch address specifi cation in memory indirect mode ........................................... 30 figure 2.9 on-chip memory acces s cycle.................................................................................. 33 figure 2.10 on-chip peripheral mo dule access cycle (3 -state access)..................................... 34 figure 2.11 cp u operation states............................................................................................. ... 35 figure 2.12 state tran siti ons ................................................................................................ ........ 36 figure 2.13 example of timer configuration with two registers allocated to same address...................................................................................................................... 37 section 3 exception handling figure 3.1 reset se quence.................................................................................................... ........ 56 figure 3.2 stack status after exceptio n handling ........................................................................ 58 figure 3.3 interrupt sequence................................................................................................ ....... 60 figure 3.4 port mode regi ster setting and interrupt reques t flag clearing procedure .............. 62 section 4 address break figure 4.1 block diag ram of address break................................................................................ 63 figure 4.2 address break inte rrupt operation example (1)......................................................... 67 figure 4.2 address break inte rrupt operation example (2)......................................................... 68 section 5 clock pulse generators figure 5.1 block diagram of clock pulse generators.................................................................. 69 figure 5.2 block diagram of system clock generator ................................................................ 70 figure 5.3 typical connect ion to crystal resonator.................................................................... 70 figure 5.4 equivalent circ uit of crystal resonator...................................................................... 70 figure 5.5 typical connect ion to ceramic resonator.................................................................. 71 figure 5.6 example of external clock input ................................................................................ 71
rev. 3.00 mar. 15, 2006 page xxii of xxxii figure 5.7 block diagram of subclock generator ....................................................................... 72 figure 5.8 typical connection to 32.768-khz crysta l resonator................................................ 72 figure 5.9 equivalent circuit of 32.768-khz crys tal resona tor.................................................. 72 figure 5.10 pin connectio n when not using subclock ................................................................ 73 figure 5.11 example of incorrect board design ........................................................................... 74 section 6 power-down modes figure 6.1 mode transition diagram ........................................................................................... 81 section 7 rom figure 7.1 block config uration of flash memory ....................................................................... 90 figure 7.2 programming/erasing flowch art example in user program mode............................ 99 figure 7.3 program/prog ram-verify fl owchart ......................................................................... 101 figure 7.4 erase/eras e-verify flowchart ................................................................................... 104 section 9 i/o ports figure 9.1 port 1 pin config uration.......................................................................................... .. 111 figure 9.2 port 2 pin config uration.......................................................................................... .. 116 figure 9.3 port 3 pin config uration.......................................................................................... .. 120 figure 9.4 port 5 pin config uration.......................................................................................... .. 123 figure 9.5 port 6 pin config uration.......................................................................................... .. 129 figure 9.6 port 7 pin config uration.......................................................................................... .. 134 figure 9.7 port 8 pin config uration.......................................................................................... .. 137 figure 9.8 port 9 pin config uration.......................................................................................... .. 141 figure 9.9 port b pin config uration.......................................................................................... .145 section 10 realtime clock (rtc) figure 10.1 bloc k diagram of rtc ........................................................................................... 14 7 figure 10.2 definition of time expr ession ................................................................................ 154 figure 10.3 initia l setting procedure........................................................................................ .. 157 figure 10.4 example: readin g of inaccurate time data............................................................ 158 section 11 timer b1 figure 11.1 block di agram of timer b1.................................................................................... 161 section 12 timer v figure 12.1 block di agram of timer v ..................................................................................... 166 figure 12.2 increment timi ng with intern al clock .................................................................... 174 figure 12.3 increment timi ng with extern al clock................................................................... 174 figure 12.4 ovf set timing ................................................................................................... ... 174 figure 12.5 cmfa an d cmfb set timing................................................................................ 175 figure 12.6 tmov output timing ............................................................................................ 175 figure 12.7 clear timi ng by compare match............................................................................ 175
rev. 3.00 mar. 15, 2006 page xxiii of xxxii figure 12.8 clear ti ming by tmriv input ............................................................................... 176 figure 12.9 pulse output example ............................................................................................. 176 figure 12.10 example of pulse outp ut synchronized to trgv input....................................... 177 figure 12.11 contention betw een tcntv write and clear ...................................................... 178 figure 12.12 contention between tcora write and co mpare match ..................................... 179 figure 12.13 internal clock sw itching and tcntv operation ................................................. 179 section 13 timer w figure 13.1 block di agram of timer w..................................................................................... 183 figure 13.2 free-runnin g counter operation ............................................................................ 194 figure 13.3 periodic counter operation..................................................................................... 19 5 figure 13.4 0 and 1 output example (toa = 0, tob = 1)........................................................ 195 figure 13.5 toggle output example (toa = 0, tob = 1) ........................................................ 196 figure 13.6 toggle output example (toa = 0, tob = 1) ........................................................ 196 figure 13.7 input capt ure operating example........................................................................... 197 figure 13.8 buffer operatio n example (input capture)............................................................. 198 figure 13.9 pwm mo de example (1) ........................................................................................ 199 figure 13.10 pwm m ode example (2) ...................................................................................... 200 figure 13.11 buffer operatio n example (outpu t compare) ...................................................... 201 figure 13.12 pwm mode example (tob = 0, toc = 0, tod = 0: initial output values ar e set to 0) ....................... 202 figure 13.13 pwm mode example (tob = 1, toc = 1,and tod = 1: initia l output values are set to 1) ................. 203 figure 13.14 count timing fo r internal cloc k source ............................................................... 204 figure 13.15 count timing fo r external cloc k source.............................................................. 204 figure 13.16 output co mpare output timing ........................................................................... 205 figure 13.17 input capt ure input signa l timing........................................................................ 206 figure 13.18 timing of counte r clearing by comp are matc h................................................... 206 figure 13.19 buffer operat ion timing (compa re match).......................................................... 207 figure 13.20 buffer operat ion timing (input capture) ............................................................. 207 figure 13.21 timing of imfa to im fd flag setting at compare match .................................. 208 figure 13.22 timing of imfa to im fd flag setting at input capture...................................... 209 figure 13.23 timing of stat us flag clearing by cpu................................................................ 209 figure 13.24 contention betw een tcnt write and clear ......................................................... 210 figure 13.25 internal clock sw itching and tcnt operation.................................................... 211 figure 13.26 when compare match and bit manipulation instruction to tcrw occur at the same timing ......................................................................................................... 212 section 14 timer z figure 14.1 time r z block di agram .......................................................................................... 21 5 figure 14.2 timer z (cha nnel 0) block diagram ...................................................................... 216
rev. 3.00 mar. 15, 2006 page xxiv of xxxii figure 14.3 timer z (cha nnel 1) block diagram ...................................................................... 217 figure 14.4 example of outputs in reset synchronous pwm mode and complementary pwm mode............................................................................................................. 224 figure 14.5 accessing operation of 16-bit re gister (between cpu and tcnt (16 bits))........ 236 figure 14.6 accessing operation of 8-bit re gister (between cpu and tstr (8 bits)) ............ 236 figure 14.7 example of counte r operation setting procedure .................................................. 237 figure 14.8 free-runnin g counter operation ............................................................................ 238 figure 14.9 periodic counter operation..................................................................................... 23 9 figure 14.10 count timing at internal clock operation............................................................ 239 figure 14.11 count timing at external clock operation (both edges detected)...................... 240 figure 14.12 example of setting procedure for waveform output by compare match............ 241 figure 14.13 example of 0 ou tput/1 output operation ............................................................. 242 figure 14.14 example of toggle output op eration ................................................................... 243 figure 14.15 output compare timing ....................................................................................... 243 figure 14.16 example of input ca pture operation setti ng procedure ....................................... 244 figure 14.17 example of input capture op eration .................................................................... 245 figure 14.18 input ca pture signal timing................................................................................. 246 figure 14.19 example of synchro nous operation settin g procedure ........................................ 247 figure 14.20 example of synchronous op eration...................................................................... 248 figure 14.21 example of pw m mode setting pr ocedure .......................................................... 249 figure 14.22 example of pwm mode opera tion (1) ................................................................. 250 figure 14.23 example of pwm mode opera tion (2) ................................................................. 251 figure 14.24 example of pwm mode opera tion (3) ................................................................. 252 figure 14.25 example of pwm mode opera tion (4) ................................................................. 253 figure 14.26 example of reset sync hronous pwm mode setting procedure........................... 255 figure 14.27 example of reset synchronous pwm mode operation (ols0 = ols1 = 1) ...... 256 figure 14.28 example of reset synchronous pwm mode operation (ols0 = ols1 = 0) ...... 257 figure 14.29 example of compleme ntary pwm mode setti ng procedure................................ 259 figure 14.30 canceling procedur e of complementary pwm mode.......................................... 260 figure 14.31 example of compleme ntary pwm mode op eration (1) ...................................... 261 figure 14.32 (1) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 = 0) (2)................................................................ 263 figure 14.32 (2) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 0) (3)................................................................ 264 figure 14.33 timi ng of overshooting ........................................................................................ 26 5 figure 14.34 timing of undershoo ting ...................................................................................... 265 figure 14.35 compare ma tch buffer operation......................................................................... 268 figure 14.36 input capt ure buffer op eration............................................................................. 269 figure 14.37 example of buffe r operation setting procedure................................................... 269
rev. 3.00 mar. 15, 2006 page xxv of xxxii figure 14.38 example of buffer operation (1) (buffer operation for output compare register).................................................. 270 figure 14.39 example of compare ma tch timing for buffer operation ................................... 271 figure 14.40 example of buffer operation (2) (buffer operation for inpu t capture regi ster) ...................................................... 272 figure 14.41 input capture timing of buffer operation............................................................ 273 figure 14.42 buff er operation (3) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1) ............ 274 figure 14.43 buff er operation (4) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1) ............ 275 figure 14.44 example of output disabl e timing of timer z by writing to toer .................. 276 figure 14.45 example of output disable timing of timer z by ex ternal trigger.................... 277 figure 14.46 example of output invers e timing of timer z by writing to tfcr ................... 277 figure 14.47 example of output invers e timing of timer z by writing to pocr................... 278 figure 14.48 imf flag set timi ng when compare match occurs ............................................ 279 figure 14.49 imf flag set timing at input capture .................................................................. 279 figure 14.50 ovf flag set timing ............................................................................................ 2 80 figure 14.51 status flag clearing timing.................................................................................. 280 figure 14.52 contention between tc nt write and clear operations....................................... 281 figure 14.53 contention between tcnt write and increment operations ............................... 281 figure 14.54 contention between gr write and comp are match ............................................. 282 figure 14.55 contention between tcnt write an d overfl ow................................................... 283 figure 14.56 contention between gr read and inpu t capture.................................................. 284 figure 14.57 contention between count clearing and increment operations by input capture .................................................................................................................. 285 figure 14.58 contention between gr write and inpu t capture................................................. 286 figure 14.59 when compare match and bit manipulation instruction to tocr occur at the same timing ......................................................................................................... 287 section 15 watchdog timer figure 15.1 block diagra m of watchdog timer ........................................................................ 289 figure 15.2 watchdog ti mer operation example...................................................................... 293 section 16 14-bit pwm figure 16.1 block di agram of 14-b it pwm .............................................................................. 295 figure 16.2 waveform output by 14 -bit pwm ......................................................................... 298 section 17 serial commu nication interface 3 (sci3) figure 17.1 bloc k diagram of sci3 ........................................................................................... 3 02 figure 17.2 data format in asynchronous co mmunication ...................................................... 318 figure 17.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-b it data, parity, two stop bits) ............. 318
rev. 3.00 mar. 15, 2006 page xxvi of xxxii figure 17.4 sample sci3 initialization fl owchart ..................................................................... 319 figure 17.5 example of sci3 transmission in asynchronous mode (8-bit data, parity, one stop bit) ........................................................................... 320 figure 17.6 sample serial transmissi on data flowchart (asynchronous mode)...................... 321 figure 17.7 example of sci3 reception in asynchronous mode (8-bit data, parity, one stop bit) ........................................................................... 322 figure 17.8 sample serial reception da ta flowchart (asynchronous mode) (1) ..................... 324 figure 17.8 sample serial reception da ta flowchart (asynchronous mode) (2) ..................... 325 figure 17.9 data format in cl ocked synchronous communication .......................................... 326 figure 17.10 example of sci3 transm ission in clocked sy nchronous mode .......................... 327 figure 17.11 sample serial transmission flowchart (clocked sy nchronous mode) ................ 328 figure 17.12 example of sci3 recep tion in clocked sync hronous mode................................ 329 figure 17.13 sample serial reception fl owchart (clocked sync hronous mo de)...................... 330 figure 17.14 sample flowchart of simultaneous serial transmit and receive operations (clocked synchronous mode)............................................................................... 331 figure 17.15 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving st ation a) .......................................... 333 figure 17.16 sample multiprocessor serial transmissi on flowchart ........................................ 334 figure 17.17 sample multiprocessor serial reception fl owchart (1)........................................ 335 figure 17.17 sample multiprocessor serial reception fl owchart (2)........................................ 336 figure 17.18 example of sci3 reception using multip rocessor format (example with 8-bit data, multipro cessor bit, one stop bit).............................. 337 figure 17.19 receive data sampli ng timing in asynchronous mode ...................................... 340 section 18 i 2 c bus interface 2 (iic2) figure 18.1 block diagram of i 2 c bus interf ace 2..................................................................... 342 figure 18.2 external circu it connections of i/o pins ................................................................ 343 figure 18.3 i 2 c bus form ats ...................................................................................................... 357 figure 18.4 i 2 c bus timi ng........................................................................................................ 357 figure 18.5 master transmit mode operation timing (1)......................................................... 359 figure 18.6 master transmit mode operation timing (2)......................................................... 359 figure 18.7 master receive mode operation timing (1) .......................................................... 361 figure 18.8 master receive mode operation timing (2) .......................................................... 362 figure 18.9 slave transmit mode operation timing (1) ........................................................... 363 figure 18.10 slave transmit mode operation timing (2) ......................................................... 364 figure 18.11 slave receive mode operation timing (1)........................................................... 365 figure 18.12 slave receive mode operation timing (2)........................................................... 365 figure 18.13 clocked synchron ous serial transfer format....................................................... 366 figure 18.14 transmit mode operatio n timing......................................................................... 367 figure 18.15 receive mo de operation timing .......................................................................... 368 figure 18.16 block diagra m of noise ca nceller........................................................................ 368
rev. 3.00 mar. 15, 2006 page xxvii of xxxii figure 18.17 sample flowchar t for master tr ansmit mode....................................................... 369 figure 18.18 sample flowchar t for master r eceive mode ........................................................ 370 figure 18.19 sample flowchar t for slave tran smit mode......................................................... 371 figure 18.20 sample flowch art for slave r eceive mode .......................................................... 372 figure 18.21 timing of b it synchronous circuit ....................................................................... 374 section 19 a/d converter figure 19.1 block diag ram of a/d c onverter ........................................................................... 378 figure 19.2 a/d conversion timing .......................................................................................... 38 5 figure 19.3 external trigger input timing ................................................................................ 386 figure 19.4 a/d conversion accuracy definitions (1) .............................................................. 388 figure 19.4 a/d conversion accuracy definitions (2) .............................................................. 389 figure 19.5 analog i nput circuit ex ample................................................................................. 390 section 20 power-on reset and lo w-voltage detection circuits (optional) figure 20.1 block diagram of power-on reset circuit and low-voltage detection circuit...................................................................................................................... 39 2 figure 20.2 operational timi ng of power-on rese t circuit...................................................... 396 figure 20.3 operational timing of lvdr circuit ..................................................................... 398 figure 20.4 operational timing of lvdi circuit....................................................................... 399 figure 20.5 timing for operation/releas e of low-voltage det ection circ uit .......................... 400 section 21 power supply circuit figure 21.1 power supply connection when internal step-down circuit is used .................... 401 figure 21.2 power supply connection when internal step-down circuit is not used ............. 402 section 23 electrical characteristics figure 23.1 system clock input timing..................................................................................... 459 figure 23.2 res low width timing.......................................................................................... 459 figure 23.3 input timing..................................................................................................... ....... 460 figure 23.4 i 2 c bus interface inpu t/output ti ming ................................................................... 460 figure 23.5 sck3 input clock timing....................................................................................... 460 figure 23.6 sci input/output timi ng in clocked synchronous mode ...................................... 461 figure 23.7 outp ut load circuit.............................................................................................. ... 461 appendix figure b.1 port 1 block diagra m (p17) ..................................................................................... 493 figure b.2 port 1 bloc k diagram (p14, p16) ............................................................................. 494 figure b.3 port 1 block diagra m (p15) ..................................................................................... 495 figure b.4 port 1 block diagra m (p12) ..................................................................................... 495 figure b.5 port 1 block diagra m (p11) ..................................................................................... 496 figure b.6 port 1 block diagra m (p10) ..................................................................................... 497 figure b.7 port 2 bloc k diagram (p24, p23) ............................................................................. 497
rev. 3.00 mar. 15, 2006 page xxviii of xxxii figure b.8 port 2 block diagra m (p22) ..................................................................................... 498 figure b.9 port 2 block diagra m (p21) ..................................................................................... 498 figure b.10 port 2 block diagram (p20) ................................................................................... 499 figure b.11 port 3 bloc k diagram (p37 to p30) ........................................................................ 499 figure b.12 port 5 bl ock diagram (p57, p56) ........................................................................... 500 figure b.13 port 5 block diagram (p55) ................................................................................... 501 figure b.14 port 5 bloc k diagram (p54 to p50) ........................................................................ 502 figure b.15 port 6 bloc k diagram (p67 to p60) ........................................................................ 503 figure b.16 port 7 block diagram (p77) ................................................................................... 503 figure b.17 port 7 block diagram (p76) ................................................................................... 504 figure b.18 port 7 block diagram (p75) ................................................................................... 504 figure b.19 port 7 block diagram (p74) ................................................................................... 505 figure b.20 port 7 block diagram (p72) ................................................................................... 506 figure b.21 port 7 block diagram (p71) ................................................................................... 506 figure b.22 port 7 block diagram (p70) ................................................................................... 507 figure b.23 port 8 bloc k diagram (p87 to p85) ........................................................................ 507 figure b.24 port 8 bloc k diagram (p84 to p81) ........................................................................ 508 figure b.25 port8 block diagram (p80) .................................................................................... 508 figure b.26 port 9 bloc k diagram (p97 to p93) ........................................................................ 509 figure b.27 port 9 block diagram (p92) ................................................................................... 509 figure b.28 port 9 block diagram (p91) ................................................................................... 510 figure b.29 port 9 block diagram (p90) ................................................................................... 510 figure b.30 port b bloc k diagram (pb7 to pb0) ...................................................................... 511 figure d.1 fp-80a package dimensions ................................................................................... 513
rev. 3.00 mar. 15, 2006 page xxix of xxxii tables section 1 overview table 1.1 pin functions ............................................................................................................ 5 section 2 cpu table 2.1 operation notation ................................................................................................. 18 table 2.2 data transfer instructions....................................................................................... 19 table 2.3 arithmetic operations instructions (1) ................................................................... 20 table 2.3 arithmetic operations instructions (2) ................................................................... 21 table 2.4 logic operations instructions................................................................................. 22 table 2.5 shift instru ctions..................................................................................................... 22 table 2.6 bit manipulation inst ructions (1)............................................................................ 23 table 2.6 bit manipulation inst ructions (2)............................................................................ 24 table 2.7 branch instructions ................................................................................................. 25 table 2.8 system control instructions.................................................................................... 26 table 2.9 block data transfer instructions ............................................................................ 26 table 2.10 addressing modes .................................................................................................. 28 table 2.11 absolute address access ranges ........................................................................... 29 table 2.12 effective address ca lculation (1)........................................................................... 31 table 2.12 effective address ca lculation (2)........................................................................... 32 section 3 exception handling table 3.1 exception sources and vector address .................................................................. 44 table 3.2 interrupt wa it states ............................................................................................... 59 section 4 address break table 4.1 access and data bus used ..................................................................................... 65 section 5 clock pulse generators table 5.1 crystal resonato r parameters ................................................................................. 71 section 6 power-down modes table 6.1 operating frequency and waiting time................................................................. 77 table 6.2 transition mode after sleep instruction execution and transition mode due to interrupt .................................................................................................................. 82 table 6.3 internal state in ea ch operating mode................................................................... 83 section 7 rom table 7.1 setting programming modes .................................................................................. 95 table 7.2 boot mode operation ............................................................................................. 97
rev. 3.00 mar. 15, 2006 page xxx of xxxii table 7.3 system clock frequencies for which automa tic adjustment of lsi bit rate is possible................................................................................................................... 98 table 7.4 reprogram data com putation table .................................................................... 102 table 7.5 additional-program data computation table ...................................................... 102 table 7.6 programming time ............................................................................................... 102 table 7.7 flash memory oper ating states............................................................................ 107 section 10 realtime clock (rtc) table 10.1 pin configuration.................................................................................................. 148 table 10.2 interrupt sources................................................................................................... 159 section 11 timer b1 table 11.1 pin configuration.................................................................................................. 161 table 11.2 timer b1 operating modes .................................................................................. 164 section 12 timer v table 12.1 pin configuration.................................................................................................. 167 table 12.2 clock signals to input to tc ntv and counting conditions ............................... 170 section 13 timer w table 13.1 timer w functions ............................................................................................... 182 table 13.2 pin configuration.................................................................................................. 184 section 14 timer z table 14.1 timer z functions ................................................................................................ 214 table 14.2 pin configuration.................................................................................................. 218 table 14.3 initial output level of ftiob0 pin...................................................................... 249 table 14.4 output pins in reset sy nchronous pwm mode................................................... 254 table 14.5 register settings in reset synchronous pw m mode........................................... 254 table 14.6 output pins in complementary pwm mode........................................................ 258 table 14.7 register settings in comp lementary pw m mode................................................ 258 table 14.8 register combinations in buffer operation ......................................................... 268 section 16 14-bit pwm table 16.1 pin configuration.................................................................................................. 295 section 17 serial commu nication interface 3 (sci3) table 17.1 channel config uration.......................................................................................... 300 table 17.2 pin configuration.................................................................................................. 303 table 17.3 examples of brr settings for various b it rates (asynchronous mode) (1) ...... 310 table 17.3 examples of brr settings for various b it rates (asynchronous mode) (2) ...... 312 table 17.3 examples of brr settings for various b it rates (asynchronous mode) (3) ...... 314 table 17.4 maximum bit rate for each fre quency (asynchronous mode) .......................... 315
rev. 3.00 mar. 15, 2006 page xxxi of xxxii table 17.5 examples of brr settings for various bit rates (clocked synchronous mode) (1) .......................................................................................................................... 316 table 17.5 examples of brr settings for various bit rates (clocked synchronous mode) (2) .......................................................................................................................... 317 table 17.6 ssr status flags and recei ve data ha ndling ...................................................... 323 table 17.7 sci3 interrupt requests........................................................................................ 338 section 18 i 2 c bus interface 2 (iic2) table 18.1 pin configuration.................................................................................................. 343 table 18.2 transfer rate ........................................................................................................ 346 table 18.3 interrupt re quests ................................................................................................. 373 table 18.4 time for monitoring scl..................................................................................... 374 section 19 a/d converter table 19.1 pin configuration.................................................................................................. 379 table 19.2 analog input channels and corr esponding addr registers .............................. 380 table 19.3 a/d conversion time (single mode)................................................................... 386 section 20 power-on reset and lo w-voltage detection circuits (optional) table 20.1 lvdcr settings and se lect func tions................................................................. 394 section 23 electrical characteristic table 23.1 absolute maximum ratings ................................................................................. 423 table 23.2 dc characteris tics (1)........................................................................................... 426 table 23.2 dc characteris tics (2)........................................................................................... 432 table 23.3 ac character istics ................................................................................................ 433 table 23.4 i 2 c bus interface timing ...................................................................................... 435 table 23.5 serial communication inte rface (sci) timing..................................................... 436 table 23.6 a/d converter char acteristic s .............................................................................. 437 table 23.7 watchdog timer ch aracteristic s........................................................................... 438 table 23.8 flash memory char acteristic s .............................................................................. 439 table 23.9 power-supply-voltage detecti on circuit charact eristics..................................... 441 table 23.10 power-on reset circu it characteris tics............................................................ 442 table 23.11 dc characteris tics (1)....................................................................................... 445 table 23.11 dc characteris tics (2)....................................................................................... 451 table 23.12 ac character istics ............................................................................................ 452 table 23.13 i 2 c bus interface timing .................................................................................. 454 table 23.14 serial communication inte rface (sci) timing................................................. 455 table 23.15 a/d converter char acteristic s .......................................................................... 456 table 23.16 watchdog timer ch aracteristic s....................................................................... 457 table 23.17 power-supply-voltage detecti on circuit charact eristics................................. 458 table 23.18 power-on reset circu it characteris tics............................................................ 459
rev. 3.00 mar. 15, 2006 page xxxii of xxxii appendix table a.1 instruction set....................................................................................................... 465 table a.2 operation code map (1) ....................................................................................... 478 table a.2 operation code map (2) ....................................................................................... 479 table a.2 operation code map (3) ....................................................................................... 480 table a.3 number of cycles in each instruction.................................................................. 482 table a.4 number of cycles in each instruction.................................................................. 483 table a.5 combinations of instructions and addressing modes .......................................... 492
section 1 overview rev. 3.00 mar. 15, 2006 page 1 of 526 rej09b0060-0300 section 1 overview 1.1 features ? ? ? flash memory version (f-ztat tm version) h8/36049f hd64f36049 hd64f36049g 96 kbytes 4 kbytes masked rom version h8/36049 hd64336049 hd64336049g 96 kbytes 3 kbytes h8/36048 hd64336048 hd64336048g 80 kbytes 3 kbytes h8/36047 hd64336047 hd64336047g 64 kbytes 3 kbytes note: f-ztat tm is a trademark of renesas technology corp.
section 1 overview rev. 3.00 mar. 15, 2006 page 2 of 526 rej09b0060-0300 ? ? ? ? ? qfp-80 fp-80a 14.0 14.0 mm 0.65 mm
section 1 overview rev. 3.00 mar. 15, 2006 page 3 of 526 rej09b0060-0300 1.2 internal block diagram p17/ irq3 /trgv p16/ irq2 p15/ irq1 /tmib1 p14/ irq0 p12 p11/pwm p10/tmow p57/scl p56/sda p55/ wkp5 / adtrg p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 pb7/an7 pb6/an6 pb5/an5 pb4/an4 pb3/an3 pb2/an2 pb1/an1 pb0/an0 v cl v cc v ss v ss res test nmi av cc av ss p24 p23 p22/txd p21/rxd p20/sck3 p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci osc1 osc2 x1 x2 port 1 port 2 port 9 cpu h8/300h rom ram data bus (lower) data bus (upper) rtc 14-bit pwm timer z sci3 iic2 sci3_2 timer v watchdog timer sci3_3 a/d converter por and lvd (option) port 8 p67/ftiod1 p66/ftioc1 p65/ftiob1 p64/ftioa1 p63/ftiod0 p62/ftioc0 p61/ftiob0 p60/ftioa0 p77 p76/tmov p75/tmciv p74/tmriv p72/txd_2 p71/rxd_2 p70/sck3_2 port 7 p97 p96 p95 p94 p93 p92/txd_3 p91/rxd_3 p90/sck3_3 port 5 p37 p36 p35 p34 p33 p32 p31 p31 port 3 subclock generator system clock generator port b timer w timer b1 port 6 address bus figure 1.1 internal block diagram
section 1 overview rev. 3.00 mar. 15, 2006 page 4 of 526 rej09b0060-0300 1.3 pin arrangement pb6/an6 pb7/an7 avcc x2 x1 v cl res test vss osc2 osc1 vcc nmi p87 p86 p85 p37 p36 p35 p34 1 2 3 4 5 6 7 8 9 1011121314151617181920 48 47 46 45 44 43 42 41 56 55 54 53 60 59 58 57 52 51 50 49 p91/rxd_3 p90/sck3_3 p12 p11/pwm p10/tmow p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci vss p67/ftiod1 p66/ftioc1 p65/ftiob1 p64/ftioa1 p63/ftiod0 p62/ftioc0 p61/ftiob0 p60/ftioa0 p20/sck3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p92/txd_3 p93 p94 p95 p96 p97 p70/sck3_2 p71/rxd_2 p72/txd_2 p74/tmriv p75/tmciv p76/tmov p77 avss pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 p21/rxd p22/txd p23 p24 p50/ wkp0 p51/ wkp1 p52/ wkp2 p53/ wkp3 p54/ wkp4 p55/ wkp5 / adtr g p56/sda p57/scl p17/ irq3 /trgv p16/ irq2 p15/ irq1 /tmib1 p14/ irq0 p30 p31 p32 p33 h8/36049 group top view figure 1.2 pin arrangements (fp-80a)
section 1 overview rev. 3.00 mar. 15, 2006 page 5 of 526 rej09b0060-0300 1.4 pin functions table 1.1 pin functions pin no. type symbol fp-80a i/o functions power supply pins vcc 12 input power supply pin. connect this pin to the system power supply. vss 9, 50 input ground pin. ensure to connect all pins to the system power supply (0 v). avcc 3 input analog power suppl y pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. avss 74 input analog ground pin for the a/d converter. connect this pin to t he system power supply (0 v). v cl 6 input internal step-down power supply pin. connect a capacitor of around 0.1 f between this pin and the vss pin for stabilization. clock pins osc1 11 input osc2 10 output these pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. see section 5, clock pulse generators, for a typical connection. x1 5 input x2 4 output these pins connect with a 32.768 khz crystal resonator for the subclock. see section 5, clock pulse generators, for a typical connection. system control res 7 input reset pin. the pull-up resistor (typ.150 k ? ) is incorporated. when driven low, the chip is reset. test 8 input test pin. connect this pin to vss. nmi 13 input non-maskable inte rrupt request input pin. be sure to pull-up by a pull-up resistor. external interrupt pins irq0 to irq3 25 to 28 input external interrupt request input pins. can select the rising or falling edge. wkp0 to wkp5 36 to 31 input external interrupt request input pins. can select the rising or falling edge. rtc tmow 56 output this is an output pin for divided clocks. timer b1 tmib1 26 input external event input pin.
section 1 overview rev. 3.00 mar. 15, 2006 page 6 of 526 rej09b0060-0300 pin no. type symbol fp-80a i/o functions timer v tmov 72 output this is an output pin for waveforms generated by the output compare function. tmciv 71 input external event input pin. tmriv 70 input counter reset input pin. trgv 28 input count start trigger input pin. timer z ftioa0 42 i/o output co mpare output/in put capture input/external clock input pin ftiob0 43 i/o output compare out put/input capture input/pwm output pin ftioc0 44 i/o output compare out put/input capture input/pwm synchronous output pin (at a reset or in complementary pwm mode) ftiod0 45 i/o output compare out put/input capture input/pwm output pin ftioa1 46 i/o output compare out put/input capture input/pwm output pin (at a reset or in complementary pwm mode) ftiob1 to ftiod1 47 to 49 i/o output compare out put/input capture input/pwm output pin timer w ftci 51 input external event input pin ftioa to ftiod 52 to 55 i/o output compare out put/input capture input/pwm output pin 14-bit pwm pwm 57 output 14-bit pwm square wave output pin i 2 c bus interface 2 (iic2) sda 30 i/o iic data i/o pin. can directly drive a bus by nmos open-drain output. when using this pin, external pull-up resistor is required. scl 29 i/o iic clock i/o pin. can directly drive a bus by nmos open-drain output. when using this pin, external pull-up resistor is required.
section 1 overview rev. 3.00 mar. 15, 2006 page 7 of 526 rej09b0060-0300 pin no. type symbol fp-80a i/o functions txd txd_2 txd_3 39 69 61 output transmit data output pin rxd rxd_2 rxd_3 40 68 60 input receive data input pin serial com- munication interface 3 (sci3) sck3 sck3_2 sck3_3 41 67 59 i/o clock i/o pin a/d converter an7 to an0 2, 1, 80 to 75 input analog input pin adtrg 31 input conversion start trigger input pin i/o ports pb7 to pb0 2, 1, 80 to 75 input 8-bit input port p17 to p14, p12 to p10 28 to 25, 58 to 56 i/o 7-bit i/o port p24 to p20 37 to 41 i/o 5-bit i/o port p37 to p30 17 to 24 i/o 8-bit i/o port p57 to p50 29 to 36 i/o 8-bit i/o port p67 to p60 49 to 42 i/o 8-bit i/o port p77 to p74, p72 to p70 73 to 70, 69 to 67 i/o 7-bit i/o port p87 to p80 14 to 16, 55 to 51 i/o 8-bit i/o port p97 to p90 66 to 59 i/o 8-bit i/o port
section 1 overview rev. 3.00 mar. 15, 2006 page 8 of 526 rej09b0060-0300
section 2 cpu rev. 3.00 mar. 15, 2006 page 9 of 526 rej09b0060-0300 section 2 cpu this lsi has an h8/300h cpu with an internal 32-bit architecture that is upward-compatible with the h8/300cpu, and supports only advanced mode, which has a 16-mbyte address space. ? ? ? ? + ? ?
section 2 cpu rev. 3.00 mar. 15, 2006 page 10 of 526 rej09b0060-0300 ? 2.1 address space and memory map the address space of this lsi is 16 mbytes, which include s the program area and data area. figure 2.1 shows the memory map. interrupt vector interrupt vector on-chip rom (96 kbytes) on-chip rom (96 kbytes) not used (1-kbyte work area for flash memory programming) internal i/o register hd64f36049 hd64f36049g (flash memory version) internal i/o register not used on-chip ram (1 kbyte) internal i/o register on-chip ram (1 kbyte) internal i/o register on-chip ram (2 kbytes) (1-kbyte user area) on-chip ram (2 kbytes) interrupt vector on-chip rom (80 kbytes) not used hd64336048 hd64336048g (masked rom version) internal i/o register not used on-chip ram (2 kbytes) interrupt vector on-chip rom (64 kbytes) not used h'000000 h'00008b h'00008c h'00ffff h'ffff7f h'ffff80 h'fffb80 h'fff77f h'fff600 h'ffefff h'ffe800 h'ffffff h'000000 h'00008b h'00008c h'013fff h'ffff7f h'ffff80 h'fffb80 h'fff77f h'fff600 h'ffefff h'ffe800 h'ffffff h'000000 h'00008b h'00008c h'017fff h'ffff7f h'ffff80 h'fffb80 h'fff77f h'fff600 h'ffefff h'ffe800 h'ffffff h'000000 h'00008b h'00008c h'017fff h'ffff7f h'ffff80 h'fffb80 h'fffb7f h'fff77f h'fff780 h'fff600 h'ffefff h'ffe800 h'ffffff hd64336047 hd64336047g (masked rom version) internal i/o register not used not used not used on-chip ram (2 kbytes) hd64336049 hd64336049g (masked rom version) not used not used not used on-chip ram (1 kbyte) internal i/o register on-chip ram (2 kbytes) internal i/o register figure 2.1 memory map
section 2 cpu rev. 3.00 mar. 15, 2006 page 11 of 526 rej09b0060-0300 2.2 register configuration the h8/300h cpu has the internal registers shown in figure 2.2. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), and an 8-bit condition-code register (ccr). pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp: pc: ccr: i: ui: stack pointer program counter condition-code register interrupt mask bit user bit half-carry flag user bit negative flag zero flag overflow flag carry flag er0 er1 er2 er3 er4 er5 er6 er7 iuihunzvc ccr 76543210 h: u: n: z: v: c: general registers (ern) control registers (cr) [legend] (sp) figure 2.2 cpu registers
section 2 cpu rev. 3.00 mar. 15, 2006 page 12 of 526 rej09b0060-0300 2.2.1 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally identical and can be used as both address register s and data registers. when a general register is used as a data register, it can be accessed as a 32-b it, 16-bit, or 8-bit regist er. figure 2.3 illustrates the usage of the general registers. when the genera l registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. the usage of each register can be selected independently. address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.3 usage of general registers general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.4 shows the relationship between the stack pointer and the stack area.
section 2 cpu rev. 3.00 mar. 15, 2006 page 13 of 526 rej09b0060-0300 sp (er7) empty area stack area figure 2.4 relationship between stack pointer and stack area 2.2.2 program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0). the pc is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v ), and carry (c) flags. the i bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. some instructions leave flag bits unchanged. op erations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. for the action of each instruction on the flag bits, see appendix a. 1, instruction list.
section 2 cpu rev. 3.00 mar. 15, 2006 page 14 of 526 rej09b0060-0300 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an exception-handling sequence. 6 ui undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is execut ed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h fl ag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructi ons, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions.
section 2 cpu rev. 3.00 mar. 15, 2006 page 15 of 526 rej09b0060-0300 2.3 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.3.1 general register data formats figure 2.5 shows the data formats in general registers. 7 0 7 0 msb lsb msb lsb 70 4 3 don't care don't care don't care 7 0 4 3 70 don't care 65432 71 0 7 0 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type general register data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.5 general register data formats (1)
section 2 cpu rev. 3.00 mar. 15, 2006 page 16 of 526 rej09b0060-0300 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb ern: en: rn: rnh: rnl: msb: lsb: general register er general register e general register r general register rh general register rl most significant bit least significant bit data type data format general register word data word data rn en longword data [legend] ern figure 2.5 general register data formats (2)
section 2 cpu rev. 3.00 mar. 15, 2006 page 17 of 526 rej09b0060-0300 2.3.2 memory data formats figure 2.6 shows the data formats in memory. the h8/300h cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd addr ess, an address error does not occur, however the least significant bit of the address is re garded as 0, so access begins the preceding address. this also applies to instruction fetches. when er7 (sp) is used as an address register to access the stack area, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.6 memory data formats
section 2 cpu rev. 3.00 mar. 15, 2006 page 18 of 526 rej09b0060-0300 2.4 instruction set 2.4.1 list of instructions classified by function the h8/300h cpu has 62 instructions. tables 2.2 to 2.9 summarize the instructions in each functional category. the notation used in tables 2.2 to 2.9 is defined below. table 2.1 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ~ not (logical complement)
section 2 cpu rev. 3.00 mar. 15, 2006 page 19 of 526 rej09b0060-0300 symbol description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers/address register (er0 to er7). table 2.2 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd cannot be used in this lsi. movtpe b rs (eas) cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is id entical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 mar. 15, 2006 page 20 of 526 rej09b0060-0300 table 2.3 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on da ta in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general re gister by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd (decimal adjust) rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 mar. 15, 2006 page 21 of 526 rej09b0060-0300 table 2.3 arithmetic operations instructions (2) instruction size * function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general regist er with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arith metic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 mar. 15, 2006 page 22 of 526 rej09b0060-0300 table 2.4 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ~ (rd) (rd) takes the one's complement (logical complement) of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.5 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl rotr b/w/l rd (rotate) rd rotates general register contents. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 3.00 mar. 15, 2006 page 23 of 526 rej09b0060-0300 table 2.6 bit manipulation instructions (1) instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immedi ate data or the lower three bits of a general register. bnot b ~ ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. btst b ~ ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. t he bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ~ ( of ) c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ~ ( of ) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 3.00 mar. 15, 2006 page 24 of 526 rej09b0060-0300 table 2.6 bit manipulation instructions (2) instruction size * function bxor bixor b b c ( of ) c xors the carry flag with a specified bi t in a general register or memory operand and stores the result in the carry flag. c ~ ( of ) c xors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ~ ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ~ c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 3.00 mar. 15, 2006 page 25 of 526 rej09b0060-0300 table 2.7 branch instructions instruction size function bcc * ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine note: * bcc is the general name for conditional branch instructions.
section 2 cpu rev. 3.00 mar. 15, 2006 page 26 of 526 rej09b0060-0300 table 2.8 system control instructions instruction size * function trapa ? starts trap-instruct ion excepti on handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr moves the source operand contents to t he ccr. the ccr size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfe r to memory, data is written by word access. andc b ccr #imm ccr logically ands the ccr with immediate data. orc b ccr #imm ccr logically ors the ccr with immediate data. xorc b ccr #imm ccr logically xors the ccr with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte w: word table 2.9 block data transfer instructions instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l?1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4?1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction be gins as soon as the transfer is completed.
section 2 cpu rev. 3.00 mar. 15, 2006 page 27 of 526 rej09b0060-0300 2.4.2 basic instruction formats h8/300h cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op), a register field (r), an eff ective address extension (e a), and a condition field (cc). figure 2.7 shows examples of instruction formats. ? ? ? ? op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm rn rm op ea(disp) op cc ea(disp) bra d:8 (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.7 instruction formats
section 2 cpu rev. 3.00 mar. 15, 2006 page 28 of 526 rej09b0060-0300 2.5 addressing modes and effective address calculation 2.5.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.10. each instruction uses a subset of these addressing modes. addressing modes that can be used differ depending on the instruction. for details, refer to appendix a.4, combinations of instructions and addressing modes. arithmetic and logic instructions can use the regi ster direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.10 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displa cement @(d:16,ern)/@(d:24,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx: 8/#xx:16/#xx:32 7 program-counter relati ve @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 register direct?rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. register indirect?@ern the register field of the instruction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand on memory.
section 2 cpu rev. 3.00 mar. 15, 2006 page 29 of 526 rej09b0060-0300 register indirect with displacemen t?@(d:16, ern) or @(d:24, ern) a 16-bit or 24-bit displacement cont ained in the instruction is adde d to an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. a 16-bit displacemen t is sign-extended when added. register indirect with post-incremen t or pre-decrement?@ern+ or @-ern ? + ? absolute address?@aa:8, @aa:16, @aa:24 the instruction code contains the absolute addr ess of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 8 bits are a sign ex tension. a 24-bit absolute address can access the entire address space. the access ranges of absolute addr esses for the group of this lsi are those shown in table 2.11. table 2.11 absolute address access ranges absolute address access range 8 bits (@aa:8) h'ffff00 to h'ffffff 16 bits (@aa:16) h'000000 to h'007fff h'ff8000 to h'ffffff 24 bits (@aa:24) h'000000 to h'ffffff
section 2 cpu rev. 3.00 mar. 15, 2006 page 30 of 526 rej09b0060-0300 immediate?#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bsr instruction. an 8-bi t or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number. memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memo ry operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byt e of the memory operand is ignored, generating a 24-bit branch address. figure 2.8 shows how to specify branch address for in memory indirect mode. the upper bits of the absolute ad dress are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff). note that the first part of the address range is also the exception vector area. specified by @aa:8 branch address dummy figure 2.8 branch a ddress specification in memory indirect mode
section 2 cpu rev. 3.00 mar. 15, 2006 page 31 of 526 rej09b0060-0300 2.5.2 effective address calculation table 2.12 indicates how effectiv e addresses are calculated in each addressing mode. in this lsi, a 24-bit effective address is generated. table 2.12 effective ad dress calculation (1) no 1 r o p 31 0 23 2 3 registe r indirect with dis placement @(d: 16,ern) or @(d: 24,ern) 4 r o p disp r op rm op rn 3 1 0 0 r o p 2 3 0 31 0 dis p 31 0 31 0 23 0 23 0 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand is general register contents. the value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
section 2 cpu rev. 3.00 mar. 15, 2006 page 32 of 526 rej09b0060-0300 table 2.12 effective ad dress calculation (2) no 5 op 23 0 abs @aa:8 7 h'ffff op 23 0 @aa:16 @aa:2 4 abs 15 16 23 0 op abs 6 op imm #xx:8/#xx:16/#xx:32 8 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 7 program-co unter re lativ e @(d :8,pc) @(d :16 ,pc) memo ry indirect @@aa :8 23 0 dis p 0 23 0 disp op 23 op 8 abs 23 0 abs h' 0000 7 8 0 15 23 0 1 5 h'00 16 [legend] r, rm,rn op disp imm abs : register field : operation field : displacement : immediate data : absolute address pc contents sign extension memory contents
section 2 cpu rev. 3.00 mar. 15, 2006 page 33 of 526 rej09b0060-0300 2.6 basic bus cycle cpu operation is synchronized by a system clock ( 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states . the data bus width is 16 bits, allowing access in byte or word size. figure 2.9 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) or sub figure 2.9 on-chip memory access cycle
section 2 cpu rev. 3.00 mar. 15, 2006 page 34 of 526 rej09b0060-0300 2.6.2 on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits or 16 bits depending on the register. for details on the data bus width and number of accessing states of each register, refer to s ection 22, list of registers. regi sters with 16-bit data bus width can be accessed by word size only. registers with 8-bit data bus width can be accessed by byte or word size. when a register with 8-bit data bus width is accessed by word size, access is completed in two cycles. in two-state access, the operation timing is the sa me as that for on-chip memory. figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data or sub figure 2.10 on-chip peripheral mo dule access cycle (3-state access)
section 2 cpu rev. 3.00 mar. 15, 2006 page 35 of 526 rej09b0060-0300 2.7 cpu states there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active mode and subactive mode. for the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. these states are shown in figure 2.11. figure 2.12 sh ows the state transitions. for details on program execution state and program halt state, refer to section 6, power-down modes. for details on exception processing, refer to section 3, exception handling. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode subactive mode sleep mode subsleep mode power-down modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized standby mode figure 2.11 cpu operation states
section 2 cpu rev. 3.00 mar. 15, 2006 page 36 of 526 rej09b0060-0300 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs interrupt source exception- handling complete reset occurs figure 2.12 state transitions 2.8 usage notes 2.8.1 notes on data access to empty areas the address space of this lsi includes empty areas in additi on to the rom, ram, and on-chip i/o registers areas available to the user. when da ta is transferred from cpu to empty areas, the transferred data will be lost. this action may al so cause the cpu to malfunction. when data is transferred from an empty ar ea to cpu, the contents of the data cannot be guaranteed. 2.8.2 eepmov instruction eepmov is a block-transfer instru ction and transfers th e byte size of data indicated by r4 or r4l, which starts from the address indicated by er5, to the address indicated by er6. set r4 or r4l and er6 so that the end address of the destination address (value of er6 + +
section 2 cpu rev. 3.00 mar. 15, 2006 page 37 of 526 rej09b0060-0300 2.8.3 bit manipulation instruction the bset, bclr, bnot, bst, and bist instructions read data from the specified address in byte units, manipulate the data of the target bit, an d write data to the same address again in byte units. special care is required wh en using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, becau se this may rewrite data of a bit other than the bit to be manipulated. bit manipulation for two registers assigned to the same address example 1: bit manipulation for the timer load register and timer counter (applicable for timer b1 in the h8/36049 group.) figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. when a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. data is read in byte units. 2. the cpu sets or resets the bit to be manipulated with the bit-manipulation instruction. 3. the written data is written again in byte units to the timer load register. the timer is counting, so the value read is not n ecessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. read write count clock timer counter timer load register reload internal data bus figure 2.13 example of timer configuration with two registers allocated to same address
section 2 cpu rev. 3.00 mar. 15, 2006 page 38 of 526 rej09b0060-0300 example 2: the bset instructio n is executed for port 5. p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins and output low-level signals. an example to output a high-level signal at p50 with a bset instruction is shown below. ? input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bset #0, @pdr5 the bset instruction is executed for port 5. ? input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 0 1 0 0 0 0 0 1
section 2 cpu rev. 3.00 mar. 15, 2006 page 39 of 526 rej09b0060-0300 ? ? mov.b #80, r0l mov.b r0l, @ram0 mov.b r0l, @pdr5 the pdr5 value (h'80) is written to a work area in memory (ram0) as well as to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 1 0 0 0 0 0 0 0 ? bset #0, @ram0 the bset instruction is executed designating the pdr5 work area (ram0).
section 2 cpu rev. 3.00 mar. 15, 2006 page 40 of 526 rej09b0060-0300 ? mov.b @ram0, r0l mov.b r0l, @pdr5 the work area (ram0) value is written to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 1 ram0 1 0 0 0 0 0 0 1 bit manipulation in a register containing a write-only bit example 3: bclr instruction executed de signating port 5 control register pcr5 p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins that output low-level signals. an example of setting the p50 pin as an input pin by the bclr instruction is shown below. it is assumed that a high-level signal will be input to this input pin. ? input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ? bclr #0, @pcr5 the bclr instruction is executed for pcr5.
section 2 cpu rev. 3.00 mar. 15, 2006 page 41 of 526 rej09b0060-0300 ? input/output output output output output output ou tput output input pin state low level high level low level low level low level low level low level high level pcr5 1 1 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ? ? mov.b #3f, r0l mov.b r0l, @ram0 mov.b r0l, @pcr5 the pcr5 value (h'3f) is written to a work area in memory (ram0) as well as to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 1
section 2 cpu rev. 3.00 mar. 15, 2006 page 42 of 526 rej09b0060-0300 ? bclr #0, @ram0 the bclr instructions executed for the pcr5 work area (ram0). ? mov.b @ram0, r0l mov.b r0l, @pcr5 the work area (ram0) value is written to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 0
section 3 exception handling rev. 3.00 mar. 15, 2006 page 43 of 526 rej09b0060-0300 section 3 exception handling exception handling may be caused by a reset, a trap instruction (trapa), or interrupts. ? res pin. the chip is also reset when the watchdog timer overflows, and exception handling starts. exception handling is the same as exception handling by the res pin. ? ?
section 3 exception handling rev. 3.00 mar. 15, 2006 page 44 of 526 rej09b0060-0300 3.1 exception sources and vector address table 3.1 shows the vector addresses and priority of each exception handling. when more than one interrupt is requested, handling is performed from the interrupt with the highest priority. table 3.1 exception sou rces and vector address relative module exception sources vector number vector address priority res pin watchdog timer reset 0 h'000000 to h'000003 high ? reserved for system use 1 to 6 h'000004 to h'00001b external interrupt pin nmi 7 h'00001c to h'00001f cpu trap instruction #0 8 h'000020 to h'000023 trap instruction #1 9 h'000024 to h'000027 trap instruction #2 10 h'000028 to h'00002b trap instruction #3 11 h'00002c to h'00002f address break break conditions satisfied 12 h'000030 to h'000033 cpu direct transition by executing the sleep instruction 13 h'000034 to h'000037 external interrupt pin irq0 low-voltage detection interrupt * 14 h'000038 to h'00003b irq1 15 h'00003c to h'00003f irq2 16 h'000040 to h'000043 irq3 17 h'000044 to h'000047 wkp 18 h'000048 to h'00004b low
section 3 exception handling rev. 3.00 mar. 15, 2006 page 45 of 526 rej09b0060-0300 relative module exception sources vector number vector address priority rtc overflow 19 h'00004c to h'00004f high ? reserved for system use 20 h'000050 to h'000053 timer w input capture a/compare match a input capture b/compare match b input capture c/compare match c input capture d/compare match d overflow 21 h'000054 to h'000057 timer v compare match a compare match b overflow 22 h'000058 to h'00005b sci3 receive data full transmit data empty transmit end receive error 23 h'00005c to h'00005f iic2 transmit data empty transmit end receive data full arbitration lost/overrun error nack detection stop conditions detected 24 h'000060 to h'000063 a/d converter a/d conversion end 25 h'000064 to h'000067 timer z0 compare match/input capture a0 to d0 overflow 26 h'000068 to h'00006b timer z1 compare match/input capture a1 to d1 overflow underflow 27 h'00006c to h'00006f timer b1 overflow 29 h'000074 to h'000077 ? reserved for system use 30, 31 h'000078 to h'00007f sci3_2 receive data full transmit data empty transmit end receive error 32 h'000080 to h'000083 low
section 3 exception handling rev. 3.00 mar. 15, 2006 page 46 of 526 rej09b0060-0300 relative module exception sources vector number vector address priority ? reserved for system use 33 h'000084 to h'000087 high sci3_3 receive data full transmit data empty transmit end receive error 34 h'000088 to h'00008b low note: * a low-voltage detection interrupt is enabled only in the product with an on-chip power- on reset and low-voltage detection circuit. 3.2 register descriptions interrupts are controlled by the following registers. ? ? ? ? ? ? ?
section 3 exception handling rev. 3.00 mar. 15, 2006 page 47 of 526 rej09b0060-0300 3.2.1 interrupt edge se lect register 1 (iegr1) iegr1 selects the direction of an edge that generates interrupt requests of pins nmi and irq3 to irq0 . bit bit name initial value r/w description 7 nmieg 0 r/w nmi edge select 0: falling edge of nmi pin input is detected 1: rising edge of nmi pin input is detected 6 5 4 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. 3 ieg3 0 r/w irq3 edge select 0: falling edge of irq3 pin input is detected 1: rising edge of irq3 pin input is detected 2 ieg2 0 r/w irq2 edge select 0: falling edge of irq2 pin input is detected 1: rising edge of irq2 pin input is detected 1 ieg1 0 r/w irq1 edge select 0: falling edge of irq1 pin input is detected 1: rising edge of irq1 pin input is detected 0 ieg0 0 r/w irq0 edge select 0: falling edge of irq0 pin input is detected 1: rising edge of irq0 pin input is detected
section 3 exception handling rev. 3.00 mar. 15, 2006 page 48 of 526 rej09b0060-0300 3.2.2 interrupt edge se lect register 2 (iegr2) iegr2 selects the direction of an edge that generates interrupt requests of the pins adtrg and wkp5 to wkp0 . bit bit name initial value r/w description 7 6 ? ? 1 1 ? ? reserved these bits are always read as 1. 5 wpeg5 0 r/w wkp5 edge select 0: falling edge of wkp5 ( adtrg ) pin input is detected 1: rising edge of wkp5 ( adtrg ) pin input is detected 4 wpeg4 0 r/w wkp4 edge select 0: falling edge of wkp4 pin input is detected 1: rising edge of wkp4 pin input is detected 3 wpeg3 0 r/w wkp3 edge select 0: falling edge of wkp3 pin input is detected 1: rising edge of wkp3 pin input is detected 2 wpeg2 0 r/w wkp2 edge select 0: falling edge of wkp2 pin input is detected 1: rising edge of wkp2 pin input is detected 1 wpeg1 0 r/w wkp1edge select 0: falling edge of wkp1 pin input is detected 1: rising edge of wkp1 pin input is detected 0 wpeg0 0 r/w wkp0 edge select 0: falling edge of wkp0 pin input is detected 1: rising edge of wkp0 pin input is detected
section 3 exception handling rev. 3.00 mar. 15, 2006 page 49 of 526 rej09b0060-0300 3.2.3 interrupt enable register 1 (ienr1) ienr1 enables direct transition interrupts, rt c interrupts, and external pin interrupts. bit bit name initial value r/w description 7 iendt 0 r/w direct transfer interrupt enable when this bit is set to 1, direct transition interrupt requests are enabled. 6 ienta 0 r/w rtc interrupt enable when this bit is set to 1, rtc interrupt requests are enabled. 5 ienwp 0 r/w wakeup interrupt enable this bit is an enable bit, which is common to the pins wkp5 to wkp0 . when the bit is set to 1, interrupt requests are enabled. 4 ? 1 ? reserved this bit is always read as 1. 3 ien3 0 r/w irq3 interrupt enable when this bit is set to 1, interrupt requests of the irq3 pin are enabled. 2 ien2 0 r/w irq2 interrupt enable when this bit is set to 1, interrupt requests of the irq2 pin are enabled. 1 ien1 0 r/w irq1 interrupt enable when this bit is set to 1, interrupt requests of the irq1 pin are enabled. 0 ien0 0 r/w irq0 interrupt enable when this bit is set to 1, interrupt requests of the irq0 pin are enabled. when disabling interrupts by clearing bits in an in terrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a resu lt a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.
section 3 exception handling rev. 3.00 mar. 15, 2006 page 50 of 526 rej09b0060-0300 3.2.4 interrupt enable register 2 (ienr2) ienr2 enables, timer b1 overflow interrupts. bit bit name initial value r/w description 7 6 ? ? 0 0 ? ? reserved these bits are always read as 0. 5 ientb1 0 r/w timer b1 interrupt enable when this bit is set to 1, timer b1 overflow interrupt requests are enabled. 4 3 2 1 0 ? ? ? ? ? 1 1 1 1 1 ? ? ? ? ? reserved these bits are always read as 1. when disabling interrupts by clearing bits in an in terrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a resu lt a conflict arises between the clear instruction and an interrupt request, exception handling fo r the interrupt will be executed after the clear instruction has been executed. 3.2.5 interrupt flag register 1 (irr1) irr1 is a status flag register for direct transition interrupts, rtc interrupts, and irq3 to irq0 interrupt requests. bit bit name initial value r/w description 7 irrdt 0 r/w direct transfer interrupt request flag [setting condition] when a direct transfer is made by executing a sleep instruction while dton in syscr2 is set to 1. [clearing condition] when irrdt is cleared by writing 0
section 3 exception handling rev. 3.00 mar. 15, 2006 page 51 of 526 rej09b0060-0300 bit bit name initial value r/w description 6 irrta ? r/w rtc interrupt request flag [setting condition] when the rtc counter value overflows [clearing condition] when irrta is cleared by writing 0 5 4 ? ? 1 1 ? ? reserved these bits are always read as 1. 3 irri3 0 r/w irq3 interrupt request flag [setting condition] when irq3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri3 is cleared by writing 0 2 irri2 0 r/w irq2 interrupt request flag [setting condition] when irq2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri2 is cleared by writing 0 1 irri1 0 r/w irq1 interrupt request flag [setting condition] when irq1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri1 is cleared by writing 0 0 irrl0 0 r/w irq0 interrupt request flag [setting condition] when irq0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri0 is cleared by writing 0
section 3 exception handling rev. 3.00 mar. 15, 2006 page 52 of 526 rej09b0060-0300 3.2.6 interrupt flag register 2 (irr2) irr2 is a status flag register for timer b1 overflow interrupts. bit bit name initial value r/w description 7 6 ? ? 0 0 ? ? reserved these bits are always read as 0. 5 irrtb1 0 r/w timer b1 interrupt request flag [setting condition] when the timer b1 counter value overflows [clearing condition] when irrtb1 is cleared by writing 0 4 3 2 1 0 ? ? ? ? ? 1 1 1 1 1 ? ? ? ? ? reserved these bits are always read as 1.
section 3 exception handling rev. 3.00 mar. 15, 2006 page 53 of 526 rej09b0060-0300 3.2.7 wakeup interrupt flag register (iwpr) iwpr is a status flag register for wkp5 to wkp0 interrupt requests. bit bit name initial value r/w description 7 6 ? ? 1 1 ? ? reserved these bits are always read as 1. 5 iwpf5 0 r/w wkp5 interrupt request flag [setting condition] when wkp5 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf5 is cleared by writing 0. 4 iwpf4 0 r/w wkp4 interrupt request flag [setting condition] when wkp4 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf4 is cleared by writing 0. 3 iwpf3 0 r/w wkp3 interrupt request flag [setting condition] when wkp3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf3 is cleared by writing 0. 2 iwpf2 0 r/w wkp2 interrupt request flag [setting condition] when wkp2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf2 is cleared by writing 0. 1 iwpf1 0 r/w wkp1 interrupt request flag [setting condition] when wkp1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf1 is cleared by writing 0. \
section 3 exception handling rev. 3.00 mar. 15, 2006 page 54 of 526 rej09b0060-0300 bit bit name initial value r/w description 0 iwpf0 0 r/w wkp0 interrupt request flag [setting condition] when wkp0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf0 is cleared by writing 0. 3.3 reset exception handling when the res pin goes low, all processing halts and this lsi enters the reset. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized by the reset. to ensure that this lsi is reset at power-up, hold the res pin low until the clock pulse generator output stabilizes. to reset the chip during operation, hold the res pin low for at least 10 system clock cycles. when the res pin goes high after bei ng held low for the necessary time, this lsi starts reset exception handling. the reset exception handling sequence is shown in figure 3.1. however, for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer to section 20, power-on reset and low-voltage detection circuits (optional). the reset exception handling sequence is as follows: 1. set the i bit in the condition code register (ccr) to 1. 2. the cpu generates a reset exception handling vector address (from h'0000 to h'0001), the data in that address is sent to the program counter (pc) as the start address, and program execution starts from that address.
section 3 exception handling rev. 3.00 mar. 15, 2006 page 55 of 526 rej09b0060-0300 3.4 interrupt exception handling 3.4.1 external interrupts as the external interrupts, there are nmi, ir q3 to irq0, and wkp5 to wkp0 interrupts. nmi interrupt : nmi interrupt is requested by input signal edge to pin nmi . this interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit nmieg in iegr1. nmi is the highest-priority interrupt, and can always be accepted without depending on the i bit value in ccr. irq3 to irq0 interrupts: irq3 to irq0 interrupts are requested by input signals to pins irq3 to irq0 . these four interrupts are given different vector addresses, and are detected indi vidually by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg3 to ieg0 in iegr1. when pins irq3 to irq0 are designated for interrupt input in pmr1 and the designated signal edge is input, the corresponding bit in irr1 is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bits ien3 to ien0 in ienr1.
section 3 exception handling rev. 3.00 mar. 15, 2006 page 56 of 526 rej09b0060-0300 wkp5 to wkp0 interrupts : wkp5 to wkp0 interrupts are requested by input signals to pins wkp 5 to wkp 0. these six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits wpeg5 to wpeg0 in iegr2. when pins wkp5 to wkp0 are designated for interrupt input in pmr5 and the designated signal edge is input, the corresponding bit in iwpr is se t to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bit ienwp in ienr1. vector fetch internal address bus internal read signal internal write signal internal data bus (16 bits) res internal processing prefetch of first program instruction (1), (3) address of reset vector: (1) = h'000000, (3) = h'000002 (2), (4) start address (contents of reset vector) (5) start address (6) first instruction of program (1) (3) (5) (2) (4) (6) figure 3.1 reset sequence
section 3 exception handling rev. 3.00 mar. 15, 2006 page 57 of 526 rej09b0060-0300 3.4.2 internal interrupts each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. for rtc interrupt requests and direct transfer interrupt requests generated by execution of a sleep instruction, this function is included in irr1, irr2, ienr1, and ienr2. when an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 interrupt handling sequence interrupts are controlled by an interrupt controller. interrupt operation is described as follows. 1. if an interrupt occurs while the nmi or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. when multiple interrupt requests are generated, the interrupt controller requests to the cpu for the interrupt handling with the highest priority at that time according to table 3.1. other interrupt requests are held pending. 3. the cpu accepts the nmi and address break wi thout depending on the i bit value. other interrupt requests are accepted, if the i bit is clear ed to 0 in ccr; if the i bit is set to 1, the interrupt request is held pending. 4. if the cpu accepts the interrupt after proces sing of the current instruction is completed, interrupt exception handling will begin. first, both pc and ccr are pushed onto the stack. the stack status at this time is shown in figure 3. 2. the pc value pushed onto the stack is the address of the first instruction to be exec uted upon return from interrupt handling. 5. then, the i bit in ccr is set to 1, masking further interrupts excluding the nmi and address break. upon return from interrupt handling, the values of i bit and other bits in ccr will be restored and returned to the values prior to the start of interrupt exception handling. 6. next, the cpu generates the vector addres s corresponding to th e accepted interrupt, and transfers the address to pc as a start address of the interr upt handling-routine. then a program starts executing from the address indicated in pc.
section 3 exception handling rev. 3.00 mar. 15, 2006 page 58 of 526 rej09b0060-0300 figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram. pc and ccr saved to stack sp (er7) sp ? 1 sp ? 2 sp ? 3 sp ? 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (er7) even address prior to start of interrupt exception handling after completion of interrupt exception handling [legend] pce: pch: pcl: ccr: sp: bits 23 to 16 of program counter (pc) bits 15 to 8 of program counter (pc) bits 7 to 0 of program counter (pc) condition code register stack pointer notes: ccr pce pch pcl 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word length, starting from an even-numbered address. figure 3.2 stack status after exception handling
section 3 exception handling rev. 3.00 mar. 15, 2006 page 59 of 526 rej09b0060-0300 3.4.4 interrupt response time table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. table 3.2 interrupt wait states item states total interrupt priority determination 2 * 1 19 to 41 waiting time for completion of executing instruction * 2 1 to 23 saving of pc and ccr to stack 4 vector fetch 4 instruction fetch 4 internal processing 4 notes: 1. in case of internal interrupts, the number of states is 1. 2. not including eepmov instruction.
section 3 exception handling rev. 3.00 mar. 15, 2006 page 60 of 526 rej09b0060-0300 internal address bus internal read signal internal write signal internal data bus interrupt request signal (14) (12) (10) (6) (4) high (2) (1) (5) (7) (9) (11) (13) instruction prefetch of interrupt handling routine internal processing vector fetch stack instruction prefetch internal processing interrupt level decision and wait for end of instruction interrupt accepted (3) (1) (2), (4) (3) (5) (7) instruction prefetch address (not executed; return address, same as pc contents) instruction code (not executed) instruction prefetch address (not executed) sp ? 2 sp ? 4 pc and ccr saved to stack vector address starting address of interrupt handling routine (contents of vector address) starting address of interrupt handling routine; (13) = (10), (12) first instruction of interrupt handling routine (6), (8) (9), (11) (10), (12) (13) (14) (8) figure 3.3 interrupt sequence
section 3 exception handling rev. 3.00 mar. 15, 2006 page 61 of 526 rej09b0060-0300 3.5 usage notes 3.5.1 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a re set. since the first instruction of a program is always executed immediatel y after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx: 32, sp). 3.5.2 notes on stack area use when word data is accessed, the l east significant bit of the address is regarded as 0. access to the stack always takes place in word si ze, so the stack pointer (sp: er7) should never indicate an odd address. use push rn (mov.w rn, @?sp) or po p rn (mov.w @sp+, rn) to save or restore register values. 3.5.3 notes on rewriting port mode registers when a port mode register is rewritten to switc h the functions of external interrupt pins, irq3 to irq0 , and wkp5 to wkp0 , the interrupt request flag may be set to 1. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at l east one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
section 3 exception handling rev. 3.00 mar. 15, 2006 page 62 of 526 rej09b0060-0300 ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0. interrupt mask cleared clear interrupt request flag to 0 ccr i bit 0 figure 3.4 port mode register setting and interrupt request flag clearing procedure
section 4 address break rev. 3.00 mar. 15, 2006 page 63 of 526 rej09b0060-0300 section 4 address break the address break simplifies on-board program debu gging. it requests an address break interrupt when the set break condition is satisfied. the interrupt request is not affected by the i bit of ccr. break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific ad dress. with the addres s break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. figure 4.1 shows a block diagram of the address break. barh bare barl bdrh bdrl abrkcr abrksr internal address bus comparator interrupt generation control circuit internal data bus comparator interrupt [legend] bare, barh, barl: bdrh, bdrl: abrkcr: abrksr: break address register break data register address break control register address break status register figure 4.1 block diagram of address break
section 4 address break rev. 3.00 mar. 15, 2006 page 64 of 526 rej09b0060-0300 4.1 register descriptions the address break has th e following registers. ? ? ? ? 4.1.1 address break control register (abrkcr) abrkcr sets address break conditions. bit bit name initial value r/w description 7 rtinte 1 r/w rte interrupt enable when this bit is 0, the interrupt immediately after executing rte is masked and then one instruction must be executed. when this bit is 1, the interrupt is not masked. 6 5 csel1 csel0 0 0 r/w r/w condition select 1 and 0 these bits set address break conditions. 00: instruction execution cycle 01: cpu data read cycle 10: cpu data write cycle 11: cpu data read/write cycle 4 3 2 acmp2 acmp1 acmp0 0 0 0 r/w r/w r/w address compare 2 to 0 these bits set the comparison condition between the address set in bar and the internal address bus. 000: compares 24-bit addresses 001: compares upper 20-bit addresses 010: compares upper 16-bit addresses 011: compares upper 12-bit addresses 1xx: reserved
section 4 address break rev. 3.00 mar. 15, 2006 page 65 of 526 rej09b0060-0300 bit bit name initial value r/w description 1 0 dcmp1 dcmp0 0 0 r/w r/w data compare 1 and 0 these bits set the comparison condition between the data set in bdr and the internal data bus. 00: no data comparison 01: compares lower 8-bit data between bdrl and data bus 10: compares upper 8-bit data between bdrh and data bus 11: compares 16-bit data between bdr and data bus [legend] x: don't care. when an address break is set in the data read cy cle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. table 4.1 shows the access and data bus used. when an i/o register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. for details on da ta widths of each regi ster, see section 22.1, register addresses (address order). table 4.1 access and data bus used word access byte access even address odd address even address odd address rom space upper 8 bits lower 8 bits upper 8 bits upper 8 bits ram space upper 8 bits lower 8 bits upper 8 bits upper 8 bits i/o register with 8-bit data bus width upper 8 bits upper 8 bits upper 8 bits upper 8 bits i/o register with 16-bit data bus width upper 8 bits lower 8 bits ? ?
section 4 address break rev. 3.00 mar. 15, 2006 page 66 of 526 rej09b0060-0300 4.1.2 address break status register (abrksr) abrksr consists of the address break interrupt flag and the address break interrupt enable bit. bit bit name initial value r/w description 7 abif 0 r/w address break interrupt flag [setting condition] when the condition set in abrkcr is satisfied [clearing condition] when 0 is written after abif=1 is read 6 abie 0 r/w address break interrupt enable when this bit is 1, an address break interrupt request is enabled. 5 to 0 ? all 1 ? reserved these bits are always read as 1. 4.1.3 break address registers e, h, l (bare, barh, barl) bar (bare, barh, barl) is a 24-bit readable/writable register that sets the address for generating an address break interrupt. the initial va lue of this register is h'ffffff. when setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. 4.1.4 break data registers h, l (bdrh, bdrl) bdr (bdrh, bdrl) is a 16-bit readable/writable register that sets the data for generating an address break interrupt. bdrh is compared with the upper 8-bit data bus. bdrl is compared with the lower 8-bit data bus. when memory or regist ers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. therefore, comparison data must be set in bdrh for byte access. fo r word access, the data bus used depends on the address. see section 4.1.1, address break control register (abrkcr), for details. the initial value of this register is undefined.
section 4 address break rev. 3.00 mar. 15, 2006 page 67 of 526 rej09b0060-0300 4.2 operation when the abie bit in abrksr is set to 1, if the abif bit in abrksr is set to 1 by the combination of the address set in bar, the data set in bdr, and the conditions set in abrkcr, the address break function generates an interrupt re quest to the cpu. when the interrupt request is accepted, interrupt exception handling starts after the instruction be ing executed ends. the address break interrupt is not masked because of the i bit in ccr of the cpu. figures 4.2 (1) to (2) show the operation examples of the address break interrupt setting. nop instruc- tion prefetch register setting abrkcr = h'80 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 0258 address bus interrupt request 025a 025c 025e sp-2 sp-4 nop instruc- tion prefetch mov instruc- tion 1 prefetch mov instruc- tion 2 prefetch internal processing stack save interrupt acceptance underline indicates the address to be stacked. when the address break is specified in instruction execution cycle figure 4.2 address break in terrupt operation example (1)
section 4 address break rev. 3.00 mar. 15, 2006 page 68 of 526 rej09b0060-0300 mov instruc- tion 1 prefetch register setting abrkcr = h'a0 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 025c address bus interrupt request 025e 0260 025a 0262 0264 sp-2 mov instruc- tion 2 prefetch nop instruc- tion prefetch mov instruc- tion execution next instru- ction prefetch internal processing stack save nop instruc- tion prefetch interrupt acceptance underline indicates the address to be stacked. when the address break is specified in the data read cycle figure 4.2 address break in terrupt operation example (2)
section 5 clock pulse generators rev. 3.00 mar. 15, 2006 page 69 of 526 rej09b0060-0300 section 5 clock pulse generators clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock puls e generator. the system clock pulse generator consists of a system clock oscillator, a duty co rrection circuit, and system clock divider. the subclock pulse generator consists of a subclock oscillator and a subclock divider. figure 5.1 shows a block diagram of the clock pulse generators. system clock oscillator subclock oscillator subclock divider duty correction circuit system clock divider prescaler s (13 bits) prescaler w (5 bits) osc 1 osc 2 x 1 x 2 system clock pulse generator osc (f osc ) osc (f osc ) w (f w ) w /2 w /4 sub /2 to /8192 w /8 osc /8 osc osc /16 osc /32 osc /64 w /8 to w /128 subclock pulse generator figure 5.1 block diagram of clock pulse generators the basic clock signals that drive the cpu and on-chip peripheral modules are
section 5 clock pulse generators rev. 3.00 mar. 15, 2006 page 70 of 526 rej09b0060-0300 5.1 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. figure 5.2 shows a block diagram of the system clock generator. lpm lpm: low-power mode (standby mode, subactive mode, subsleep mode) 2 1 osc osc figure 5.2 block diagram of system clock generator 5.1.1 connecting crystal resonator figure 5.3 shows a typical method of connecting a crystal resonator. an at-cut parallel-resonance crystal resonator should be used. figure 5.4 shows the equivalent circuit of a crystal resonator. a resonator having the characteristics given in table 5.1 should be used. 1 2 c 1 c 2 osc osc c = c = 10 to 22pf 12 figure 5.3 typical connect ion to crystal resonator c s c 0 r s osc 1 osc 2 l s figure 5.4 equivalent circuit of crystal resonator
section 5 clock pulse generators rev. 3.00 mar. 15, 2006 page 71 of 526 rej09b0060-0300 table 5.1 crystal resonator parameters frequency (mhz) 2 4 8 10 16 20 r s (max.) 500 ? 120 ? 80 ? 60 ? 50 ? 40 ? c 0 (max.) 7 pf 7 pf 7 pf 7 pf 7 pf 7 pf 5.1.2 connecting ceramic resonator figure 5.5 shows a typical method of connecting a ceramic resonator. osc 1 osc 2 c 1 c 2 c 1 = 5 to 30pf c 2 = 5 to 30pf figure 5.5 typical connect ion to cerami c resonator 5.1.3 external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 5.6 shows a typical connection. the duty cycle of the external clock sign al must be 45 to 55%. osc 1 external clock input osc 2 open figure 5.6 example of external clock input
section 5 clock pulse generators rev. 3.00 mar. 15, 2006 page 72 of 526 rej09b0060-0300 5.2 subclock generator figure 5.7 shows a block diagram of the subclock generator. note: resistance is a reference value. 2 1 x 8 m ? x figure 5.7 block diagram of subclock generator 5.2.1 connecting 32.768-khz crystal resonator clock pulses can be supplied to the subclock divider by connecting a 32.768-khz crystal resonator, as shown in figure 5.8. figure 5.9 shows the equivalent circuit of the 32.768-khz crystal resonator. x x c 1 c 2 1 2 c = c = 15 pf (typ.) 12 figure 5.8 typical connection to 32.768-khz crystal resonator x 1 x 2 l s c s c o c o = 1.5 pf (typ.) r s = 14 k ? (typ.) fw = 32.768 khz r s note: constants are reference values. figure 5.9 equivalent circuit of 32.768-khz crystal resonator
section 5 clock pulse generators rev. 3.00 mar. 15, 2006 page 73 of 526 rej09b0060-0300 5.2.2 pin connection when not using subclock when the subclock is not used, connect pin x 1 to v cl or v ss and leave pin x 2 open, as shown in figure 5.10. x 1 v cl or v ss x 2 open figure 5.10 pin connection when not using subclock 5.3 prescalers 5.3.1 prescaler s prescaler s is a 13-bit counter using the system clock ( 5.3.2 prescaler w prescaler w is a 5-bit counter using a 32.768 khz signal divided by 4 (
section 5 clock pulse generators rev. 3.00 mar. 15, 2006 page 74 of 526 rej09b0060-0300 5.4 usage notes 5.4.1 notes on resonators resonator characteristics are closely related to boar d design and should be carefully evaluated by the user, referring to the examples shown in this section. resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the resonator element manufacturer. design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.4.2 notes on board design when using a crystal resonator (ceramic resonator) , place the resonator and its load capacitors as close as possible to the osc 1 and osc 2 pins. other signal lines should be routed away from the resonator circuit to prevent induc tion from interfering with correct oscillation (see figure 5.11). osc 1 osc 2 c 1 c2 signal a signal b avoid figure 5.11 example of incorrect board design
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 75 of 526 rej09b0060-0300 section 6 power-down modes this lsi has five modes of operation after a reset. these include a normal active mode and four power-down modes, in which power consumption is significantly reduced. the module standby function reduces power consumption by selectively halting on-chip module functions. ? ? ? ? ? ? 6.1 register descriptions the registers related to power-down modes are listed below. for details on the serial mode control register (sci3_3 module standby), see section 17, serial communicatio n interface 3 (sci3). ? ? ? ? ?
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 76 of 526 rej09b0060-0300 6.1.1 system control register 1 (syscr1) syscr1 controls the power-down modes, as well as syscr2. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit selects the mode to transit after the execution of the sleep instruction. 0: enters sleep mode or subsleep mode. 1: enters standby mode. for details, see table 6.2. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or subsleep mode to active mode or sleep mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. the relationship between t he specified value and the number of wait states is shown in table 6.1. when an external clock is to be used, the minimum value (sts2 = sts1 = sts0 =1) is recommended. 3 nesel 0 r/w noise eliminat ion sampling frequency select the subclock pulse generat or generates the watch clock signal ( w ) and the system clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 20 mhz, clear nesel to 0. 0: sampling rate is osc /16 1: sampling rate is osc /4 2 1 0 ? ? ? 0 0 0 ? ? ? reserved these bits are always read as 0.
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 77 of 526 rej09b0060-0300 table 6.1 operating frequency and waiting time bit name operating frequency sts2 sts1 sts0 waiting time 20 mhz 16 mhz 10 mhz 8 mhz 4 mhz 2 mhz 1 mhz 0.5 mhz 0 0 0 8,192 states 0.4 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 0.8 1.0 1.6 2.0 4.1 8.2 16.4 32.8 1 0 32,768 states 1.6 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 3.3 4.1 6.6 8.2 16.4 32.8 65.5 131.1 1 0 0 131,072 states 6.6 8.2 13.1 16.4 32.8 65.5 131.1 262.1 1 1,024 states 0.05 0.06 0.10 0.13 0.26 0.51 1.02 2.05 1 0 128 states 0.00 0.00 0.01 0.02 0.03 0.06 0.13 0.26 1 16 states 0.00 0.00 0.00 0.00 0.00 0.01 0.02 0.03 note: time unit is ms. 6.1.2 system control register 2 (syscr2) syscr2 controls the power-down modes, as well as syscr1. bit bit name initial value r/w description 7 6 5 smsel lson dton 0 0 0 r/w r/w r/w sleep mode selection low speed on flag direct transfer on flag these bits select the mode to enter after the execution of a sleep instruction, as well as bit ssby of syscr1. for details, see table 6.2. 4 3 2 ma2 ma1 ma0 0 0 0 r/w r/w r/w active mode clock select 2 to 0 these bits select the operating clock frequency in active and sleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 0xx: osc 100: osc /8 101: osc /16 110: osc /32 111: osc /64
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 78 of 526 rej09b0060-0300 bit bit name initial value r/w description 1 0 sa1 sa0 0 0 r/w r/w subactive mode clock select 1 and 0 these bits select the operating clock frequency in subactive and subsleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 00: w /8 01: w /4 1x: w /2 [legend] x: don't care.
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 79 of 526 rej09b0060-0300 6.1.3 module standby control register 1 (mstcr1) mstcr1 allows the on-chip peripheral module s to enter a standby state in module units. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 mstiic 0 r/w iic2 module standby iic2 enters standby mode when this bit is set to 1 5 msts3 0 r/w sci3 module standby sci3 enters standby mode when this bit is set to 1 4 mstad 0 r/w a/d converter module standby a/d converter enters standby mode when this bit is set to 1 3 mstwd 0 r/w watchdog timer module standby watchdog timer enters standby mode when this bit is set to 1.when the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit 2 msttw 0 r/w timer w module standby timer w enters standby mode when this bit is set to 1 1 msttv 0 r/w timer v module standby timer v enters standby mode when this bit is set to 1 0 mstta 0 r/w rtc module standby rtc enters standby mode when this bit is set to 1
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 80 of 526 rej09b0060-0300 6.1.4 module standby control register 2 (mstcr2) mstcr2 allows the on-chip peripheral modules to enter a standby state in module units. bit bit name initial value r/w description 7 msts3_2 0 r/w sci3_2 module standby sci3_2 enters standby mode when this bit is set to1 6 5 ? ? 0 0 ? ? reserved these bits are always read as 0. 4 msttb1 0 r/w timer b1 module standby timer b1 enters standby mode when this bit is set to1 3 2 ? ? 0 0 ? ? reserved these bits are always read as 0. 1 msttz 0 r/w timer z module standby timer z enters standby mode when this bit is set to1 0 mstpwm 0 r/w pwm module standby pwm enters standby mode when this bit is set to1
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 81 of 526 rej09b0060-0300 6.2 mode transitions and states of lsi figure 6.1 shows the possible transitions among these operating modes. a transition is made from the program execution state to the program halt state by executing a sleep instruction. interrupts allow for returning from the program halt state to the program execution stat e. a direct transition between active mode and subactive mode, which ar e both program execution states, can be made without halting the program. the operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. res input enables transitions from a mode to the reset state. table 6.2 shows the transition conditions of each mode after the sleep instruction is executed and a mode to return by an interrupt. table 6.3 shows the in ternal states of the lsi in each mode. reset state standby mode active mode sleep mode subsleep mode subactive mode program halt state program execution state program halt state sleep instruction sleep instruction interrupt direct transition interrupt direct transition interrupt notes: 1. to make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. details on the mode transition conditions are given in table 6.2. sleep instruction direct transition interrupt direct transition interrupt interrupt sleep instruction interrupt interrupt sleep instruction interrupt sleep instruction figure 6.1 mode transition diagram
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 82 of 526 rej09b0060-0300 table 6.2 transition mode after sleep inst ruction execution and transition mode due to interrupt dton ssby smsel lson transition mode after sleep instruction execution transition mode due to interrupt 0 0 0 0 sleep mode active mode 1 subactive mode 1 0 subsleep mode active mode 1 subactive mode 1 x x standby mode active mode 1 x 0 * 0 active mode (direct transition) ? x x 1 subactive mode (direct transition) ? [legend] x: don't care. * when a state transition is performed while sm sel is 1, timer v, sci3, sci3_2, sci3_3, and the a/d converter are reset, and all registers are set to their initial values. to use these functions after entering active mode, reset the registers.
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 83 of 526 rej09b0060-0300 table 6.3 internal state in each operating mode function active mode sleep mode subactive mode subsleep mode standby mode system clock oscillator functioning functioning halted halted halted subclock oscillator functioning functi oning functioning functioning functioning instructions functioning halted functioning halted halted cpu operations registers functioning retained functioning retained retained ram functioning retained f unctioning retained retained io ports functioning retained functioning retained register contents are retained, but output is the high- impedance state. irq3 to irq0 functioning functioni ng functioning functioning functioning external interrupts wkp5 to wkp0 functioning functioning functi oning functioning functioning rtc functioning functioni ng functioning if the timekeeping time-base function is selected, and retained if not selected peripheral functions timer v functioning functioning reset reset reset watchdog timer functioning functioning retained (functioning if the internal oscillator is selected as a count clock * ) sci3, sci3_2, sci3_3 functioning functioning reset reset reset iic2 functioning functioning retained * retained retained timer b1 functioning functioning retained * retained retained timer z functioning functioning retained * retained retained timer w functioning functioni ng retained (the counter is incremented by a subclock if the internal clock is selected as a count clock *) retained a/d converter functioning functioning reset reset reset note: * registers can be read or written in subactive mode.
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 84 of 526 rej09b0060-0300 6.2.1 sleep mode in sleep mode, cpu operation is halted but the on-chip peripheral modules function at the clock frequency set by the ma2, ma1, and ma0 bits in syscr2. cpu register contents are retained. when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit of the co ndition code register (ccr) is set to 1 or the requested interrupt is disabled in the interrupt enable register. after sleep mode is cleared, a transition is made to active mode when the lson b it in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 6.2.2 standby mode in standby mode, the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. however, as long as the rated voltage is supplied, the contents of cpu registers, on- chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be retained as long as the voltage set by the ram data retention voltage is provided. the i/o ports go to the high-impedance state. standby mode is cleared by an in terrupt. when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, and interrupt exception handling starts. standby mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system cloc k pulse generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high.
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 85 of 526 rej09b0060-0300 6.2.3 subsleep mode in subsleep mode, operation of the cpu and on-chip peripheral modules other than rtc is halted. as long as a required voltage is applied, the contents of cpu registers, the on-chip ram, and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. subsleep mode is cleared by an in terrupt. when an interrupt is requ ested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the in terrupt enable register. after subsleep mode is cleared, a transition is made to active mode when th e lson bit in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. after the time set in bits sts2 to sts0 in syscr1 has elapsed, a transition is made to active mode. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire ch ip as soon as the system clock puls e generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 6.2.4 subactive mode the operating frequency of subactive mode is selected from res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire ch ip as soon as the system clock puls e generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high.
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 86 of 526 rej09b0060-0300 6.3 operating frequency in active mode operation in active mode is clocked at the frequency designated by the ma2, ma1, and ma0 bits in syscr2. the operating frequency changes to the set frequency after sleep instruction execution. 6.4 direct transition the cpu can execute programs in two modes: activ e and subactive modes. a direct transition is a transition between these two modes without stoppi ng program execution. a direct transition can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. the direct transition also enables operating frequency modi fication in active or subactive mode. after the mode transition, direct transition interrupt exception handling starts. if the direct transition interrupt is disabled in in terrupt enable register 1, a transition is made instead to sleep or subsleep mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep or subsleep mode will be en tered, and the resulting mode cannot be cleared by means of an interrupt. 6.4.1 direct transition from ac tive mode to subactive mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). direct transition time = {(number of sleep instruction execution states) + (number of internal processing states)} direct transition time = (2 + 1) tosc + 16 8 tw = 3 tosc + 128 tw (when the cpu operating clock of osc w /8 is selected) [legend] tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock (
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 87 of 526 rej09b0060-0300 6.4.2 direct transition from su bactive mode to active mode the time from the start of sleep instruction execu tion to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). direct transition time = {(number of sleep inst ruction execution states) + (number of internal processing states)} : direct transition time = (2 + 1) 8 tw + (8192 + 16) tosc = 24 tw + 8208 tosc (when the cpu operating clock of w /8 osc and a waiting time of 8192 states are selected) [legend] tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( 6.5 module standby function the module-standby function can be set to any peri pheral module. in the mo dule standby state, the clock supply to modules stops to enter the power-down mode. setting a bit in mstcr1, mstcr2, or smcr that corresponds to each modul e to 1 enables each on-chip peripheral module to enter the module standby state and the module standby state is can celed by clearing the bit to 0.
section 6 power-down modes rev. 3.00 mar. 15, 2006 page 88 of 526 rej09b0060-0300
section 7 rom rev. 3.00 mar. 15, 2006 page 89 of 526 rej09b0060-0300 section 7 rom the features of the 96-kbyte flash memory bu ilt into the flash memory (f-ztat) version are summarized below. ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 7 rom rev. 3.00 mar. 15, 2006 page 90 of 526 rej09b0060-0300 7.1 block configuration figure 7.1 shows the block configuration of flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresse s. the 96-kbyte flash memory is divided into 1 kbyte erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 1 kbyte erase unit: 28 kbytes erase unit: 16 kbytes erase unit: 16 kbytes erase unit: 32 kbytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes h'000000 h'000001 h'000002 h'00007f h'0003ff h'00047f h'00087f h'000c7f h'00107f h'007fff h'00807f h'00bfff h'0007ff h'000bff h'000fff h'00c07f h'00ffff h'01007f h'017fff h'000400 h'000401 h'000402 h'000780 h'000781 h'000782 h'000800 h'000801 h'000802 h'000b80 h'000b81 h'000b82 h'000f80 h'000f81 h'000f82 h'007f80 h'007f81 h'007f82 h'00bf80 h'00bf81 h'00bf82 h'00ff80 h'00ff81 h'00ff82 h'017f80 h'017f81 h'017f82 h'000c00 h'000c01 h'000c02 h'001000 h'001001 h'001002 h'008000 h'008001 h'008002 h'00c000 h'00c001 h'00c002 h'010000 h'010001 h'010002 h'000380 h'000381 h'000382 figure 7.1 block configuration of flash memory
section 7 rom rev. 3.00 mar. 15, 2006 page 91 of 526 rej09b0060-0300 7.2 register descriptions the flash memory has th e following registers. ? ? ? ? ? 7.2.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 7.4, flash memory programming/erasing. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e bit to 1 in flmcr1. 4 psu 0 r/w program setup when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p bit in flmcr1. 3 ev 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled.
section 7 rom rev. 3.00 mar. 15, 2006 page 92 of 526 rej09b0060-0300 bit bit name initial value r/w description 2 pv 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program- verify mode is cancelled. 1 e 0 r/w erase when this bit is set to 1 while swe=1 and esu=1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p 0 r/w program when this bit is set to 1 while swe=1 and psu=1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. 7.2.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displa ys the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. see section 7.5.3, error protection, for details. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 7 rom rev. 3.00 mar. 15, 2006 page 93 of 526 rej09b0060-0300 7.2.3 erase block register 1 (ebr1) ebr1 specifies the flash memory erase area block. ebr1 is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. bit bit name initial value r/w description 7 eb7 0 r/w when this bit is set to 1, 32 kbytes of h'010000 to h'017fff will be erased. 6 eb6 0 r/w when this bit is set to 1, 16 kbytes of h'00c000 to h'00ffff will be erased. 5 eb5 0 r/w when this bit is set to 1, 16 kbytes of h'008000 to h'00bfff will be erased. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'001000 to h'007fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'000c00 to h'000fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'000800 to h'000bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'000400 to h'0007ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'000000 to h'0003ff will be erased.
section 7 rom rev. 3.00 mar. 15, 2006 page 94 of 526 rej09b0060-0300 7.2.4 flash memory power control register (flpwcr) flpwcr enables or disables a transition to th e flash memory power-down mode when the lsi switches to subactive mode. there are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retain ed and flash memory can be read. bit bit name initial value r/w description 7 pdwnd 0 r/w power-down disable when this bit is 0 and a transition is made to subactive mode, the flash memory ent ers the power-down mode. when this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 ? all 0 ? reserved these bits are always read as 0. 7.2.5 flash memory enable register (fenr) bit 7 (flshe) in fenr enables or disables the cpu access to the flash memo ry control registers, flmcr1, flmcr2, ebr1, and flpwcr. bit bit name initial value r/w description 7 flshe 0 r/w flash memory control register enable flash memory control registers can be accessed when this bit is set to 1. flash memory control registers cannot be accessed when this bit is set to 0. 6 ? 0 r/w reserved this bit can be read from or written to, but should not be set to 1. 5 to 0 ? all 0 ? reserved these bits are always read as 0.
section 7 rom rev. 3.00 mar. 15, 2006 page 95 of 526 rej09b0060-0300 7.3 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the test pin settings, nmi pin settings, and input level of each port, as shown in table 7.1. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci3. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 7.1 setting programming modes test nmi p85 pb0 pb1 pb2 lsi state after reset end 0 1 x x x x user mode 0 0 1 x x x boot mode 1 x x 0 0 0 programmer mode [legend] x : don't care. 7.3.1 boot mode table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 7.4, flash memory programming/erasing. 2. sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity.
section 7 rom rev. 3.00 mar. 15, 2006 page 96 of 526 rej09b0060-0300 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initia te boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi w ithin the ranges listed in table 7.3. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'fff780 to h'fffeef is the area to which the programmi ng control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control pr ogram, the chip terminat es transfer operations by sci3 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming co ntrol program can still use it for transfer of program data or verify data with the host. the txd pin is high (pcr22 = 1, p22 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointe r (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the test pin and nmi pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and nmi pin input levels in boot mode.
section 7 rom rev. 3.00 mar. 15, 2006 page 97 of 526 rej09b0060-0300 table 7.2 boot mode operation communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. h'55 reception h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception upper bytes, lower bytes echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation measures low-level period of receive data h'00. calculates bit rate and sets brr in sci3. transmits data h'00 to host as adjustment end indication. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of number of bytes of programming control program flash memory erase
section 7 rom rev. 3.00 mar. 15, 2006 page 98 of 526 rej09b0060-0300 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system cloc k frequency range of lsi 19,200 bps 16 to 20 mhz 9,600 bps 8 to 16 mhz 4,800 bps 4 to 16 mhz 2,400 bps 2 to 16 mhz 7.3.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 7.2 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 7.4, flash memory programming/erasing.
section 7 rom rev. 3.00 mar. 15, 2006 page 99 of 526 rej09b0060-0300 ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 7.2 programming/erasing flowchart example in user program mode
section 7 rom rev. 3.00 mar. 15, 2006 page 100 of 526 rej09b0060-0300 7.4 flash memory programming/erasing a software method using the cpu is employed to program and erase fl ash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4. 1, program/program-veri fy and sect ion 7.4.2, erase/erase-verify, respectively. 7.4.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start addres s in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. table 7.6 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in words or in longwords from the address to which a dummy write was performed.
section 7 rom rev. 3.00 mar. 15, 2006 page 101 of 526 rej09b0060-0300 8. the maximum number of repetitions of the pr ogram/program-verify sequence of the same bit is 1,000. start end of programming note: * the rts instruction must not be used during the following 1. and 2. periods. 1. a period between 128-byte data programming to flash memory and the p bit clearing 2. a period between dummy writing of h'ff to a verify address and verify data reading set swe bit in flmcr1 write pulse application subroutine wait 1 s apply write pulse * set psu bit in flmcr1 wdt enable disable wdt wait 50 s set p bit in flmcr1 wait (wait time=programming time) clear p bit in flmcr1 wait 5 s clear psu bit in flmcr1 wait 5 s n= 1 m= 0 no no no yes yes yes yes wait 4 s wait 2 s wait 2 s apply write pulse set pv bit in flmcr1 set block start address as verify address h'ff dummy write to verify address read verify data verify data = write data? reprogram data computation additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 m= 0 ? increment address programming failure no clear swe bit in flmcr1 wait 100 s no yes n 6? no yes n 6 ? wait 100 s n 1000 ? n n + 1 write 128-byte data in ram reprogram data area consecutively to flash memory store 128-byte program data in program data area and reprogram data area apply write pulse sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory * figure 7.3 program/program-verify flowchart
section 7 rom rev. 3.00 mar. 15, 2006 page 102 of 526 rej09b0060-0300 table 7.4 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 1 0 1 ? 1 1 1 remains in erased state table 7.5 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 7.6 programming time n (number of writes) programming time in additional programming comments 1 to 6 30 10 7 to 1,000 200 ? note: time shown in s.
section 7 rom rev. 3.00 mar. 15, 2006 page 103 of 526 rej09b0060-0300 7.4.2 erase/erase-verify when erasing flash memory, the erase/erase-veri fy flowchart shown in figure 7.4 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr1). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to prog ram runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower two bits are b'00. verify data can be read in lo ngwords from the address to which a dummy write was performed. 6. if the read data is not erased successfully, se t erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 interrupt handli ng when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
section 7 rom rev. 3.00 mar. 15, 2006 page 104 of 526 rej09b0060-0300 erase start set ebr1 enable wdt wait 1 s wait 100 s swe bit 1 n 1 esu bit 1 e bit 1 wait 10 ms e bit 0 wait 10 s esu bit 10 10 s disable wdt read verify data increment address verify data + all 1s ? last address of block ? all erase block erased ? set block start address as verify address h'ff dummy write to verify address wait 20 s wait 2 s ev bit 1 wait 100 s end of erasing note: * the rts instruction must not be used during a period between dummy writing of h'ff to a verify address and verify data reading. swe bit 0 wait 4 s ev bit 0 n 100 ? wait 100 s erase failure swe bit 0 wait 4 s ev bit 0 n n + 1 ye s no ye s ye s ye s ye s no no no * figure 7.4 erase/erase-verify flowchart
section 7 rom rev. 3.00 mar. 15, 2006 page 105 of 526 rej09b0060-0300 7.5 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) ar e initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stab ilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristic s section. 7.5.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h'00, erase protection is set for all blocks. 7.5.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the prog ram/erase operation is forcibly ab orted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are de tected during programming/eras ing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? ? ?
section 7 rom rev. 3.00 mar. 15, 2006 page 106 of 526 rej09b0060-0300 the flmcr1, flmcr2, and ebr1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurr ed. program mode or erase mode cannot be re- entered by re-setting the p or e bit. however, pv and ev bit settings are retained, and a transition can be made to verify mode. error protection can be cleared only by a power-on reset. 7.6 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memo ry. use a prom programmer that supports the mcu device type with the on-chip renesas technology 128-kbyte flash memory. 7.7 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? ? ?
section 7 rom rev. 3.00 mar. 15, 2006 page 107 of 526 rej09b0060-0300 table 7.7 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode standby mode standby mode standby mode
section 7 rom rev. 3.00 mar. 15, 2006 page 108 of 526 rej09b0060-0300
section 8 ram rev. 3.00 mar. 15, 2006 page 109 of 526 rej09b0060-0300 section 8 ram this lsi has an on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling two-state access by the cpu to both byte data and word data. product classification ram size ram address flash memory version (f-ztat tm version) h8/36049f 4 kbytes h'ffe800 to h'ffefff, h'fff780 to h'ffff7f * masked rom version h8/36049 3 kbytes h'ffe800 to h'ffefff, h'fffb80 to h'ffff7f h8/36048 3 kbytes h'ffe800 to h'ffefff, h'fffb80 to h'ffff7f h8/36047 3 kbytes h'ffe800 to h'ffefff, h'fffb80 to h'ffff7f note: * when the e7 or e8 is used, area h 'fff780 to h'fffb7f must not be accessed.
section 8 ram rev. 3.00 mar. 15, 2006 page 110 of 526 rej09b0060-0300
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 111 of 526 rej09b0060-0300 section 9 i/o ports the group of this lsi has fifty-nine general i/o ports and eight general input-only ports. thirteen ports are large current ports, which can drive 20 ma (@v ol = 1.5 v) when a low level signal is output. any of these ports can become an input port immediately after a reset. they can also be used as i/o pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. the registers for selecting these functions can be divided into two types: those included in i/o ports and those included in each on- chip peripheral module. general i/ o ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. for functions in each port, see appendix b.1, i/o port block diagrams. for the execution of bit- manipulation instructions to the port control register and port data register, see section 2.8.3, bit manipulation instruction. 9.1 port 1 port 1 is a general i/o port also functioning as irq interrupt input pins, an rtc output pin, a 14- bit pwm output pin, a timer b1 input pin, and a timer v input pin. figure 9.1 shows its pin configuration. p17/ irq3 /trgv p16/ irq2 p15/ irq1 /tmib1 p14/ irq0 p12 p11/pwm p10/tmow port 1 figure 9.1 port 1 pin configuration port 1 has the following registers. ? ? ? ?
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 112 of 526 rej09b0060-0300 9.1.1 port mode register 1 (pmr1) pmr1 switches the functions of pins in port 1 and port 2. bit bit name initial value r/w description 7 irq3 0 r/w selects the function of pin p17/ irq3 /trgv. 0: general i/o port 1: irq3 /trgv input pin 6 irq2 0 r/w selects the function of pin p16/ irq2 . 0: general i/o port 1: irq2 input pin 5 irq1 0 r/w selects the function of pin p15/ irq1 /tmib1. 0: general i/o port 1: irq1 /tmib1 input pin 4 irq0 0 r/w selects the function of pin p14/ irq0 . 0: general i/o port 1: irq0 input pin 3 txd2 0 r/w selects the function of pin p72/txd_2. 0: general i/o port 1: txd_2 output pin 2 pwm 0 r/w selects the function of pin p11/pwm. 0: general i/o port 1: pwm output pin 1 txd 0 r/w selects the function of pin p22/txd. 0: general i/o port 1: txd output pin 0 tmow 0 r/w selects the function of pin p10/tmow. 0: general i/o port 1: tmow output pin
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 113 of 526 rej09b0060-0300 9.1.2 port control register 1 (pcr1) pcr1 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 0 0 0 0 ? 0 0 0 w w w w ? w w w when the corresponding pin is designated in pmr1 as a general i/o pin, setting a pcr1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bit 3 is a reserved bit. 9.1.3 port data register 1 (pdr1) pdr1 is a general i/o port data register of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17 p16 p15 p14 ? p12 p11 p10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w pdr1 stores output data for port 1 pins. if pdr1 is read while pcr1 bi ts are set to 1, the values stored in pdr1 are read. if pdr1 is read while pcr1 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr1. bit 3 is a reserved bit. this bit is always read as 1.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 114 of 526 rej09b0060-0300 9.1.4 port pull-up control register 1 (pucr1) pucr1 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w only bits for which pcr1 is cleared are valid. the pull- up moss of p17 to p14 and p12 to p10 pins enter the on-state when these bits are set to 1, while they enter the off-state when these bi ts are cleared to 0. bit 3 is a reserved bit. this bit is always read as 1. 9.1.5 pin functions the correspondence between the register specification and the port functions is shown below. ? irq3 /trgv pin register pmr1 pcr1 bit name irq3 pcr17 pin function setting value 0 0 p17 input pin 1 p17 output pin 1 x irq3 input/trgv input pin [legend] x: don't care. ? irq2 pin register pmr1 pcr1 bit name irq2 pcr16 pin function setting value 0 0 p16 input pin 1 p16 output pin 1 x irq2 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 115 of 526 rej09b0060-0300 ? irq1 /tmib1 pin register pmr1 pcr1 bit name irq1 pcr15 pin function setting value 0 0 p15 input pin 1 p15 output pin 1 x irq1 input/tmib1 input pin [legend] x: don't care. ? irq0 pin register pmr1 pcr1 bit name irq0 pcr14 pin function setting value 0 0 p14 input pin 1 p14 output pin 1 x irq0 input pin [legend] x: don't care. ? register pcr1 bit name pcr12 pin function 0 p12 input pin setting value 1 p12 output pin ? register pmr1 pcr1 bit name pwm pcr11 pin function setting value 0 0 p11 input pin 1 p11 output pin 1 x pwm output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 116 of 526 rej09b0060-0300 ? register pmr1 pcr1 bit name tmow pcr10 pin function setting value 0 0 p10 input pin 1 p10 output pin 1 x tmow output pin [legend] x: don't care. 9.2 port 2 port 2 is a general i/o port also functioning as sci3 i/o pins. each pin of the port 2 is shown in figure 9.2. the register settings of pmr1 and sci3 have priority for functions of the pins for both uses. p22/txd p21/rxd p20/sck3 p23 p24 port 2 figure 9.2 port 2 pin configuration port 2 has the following registers. ? ? ?
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 117 of 526 rej09b0060-0300 9.2.1 port control register 2 (pcr2) pcr2 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 2. bit bit name initial value r/w description 7 6 5 ? ? ? ? ? ? ? ? ? reserved 4 3 2 1 0 pcr24 pcr23 pcr22 pcr21 pcr20 0 0 0 0 0 w w w w w when each of the port 2 pins p24 to p20 functions as a general i/o port, setting a pcr2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.2.2 port data register 2 (pdr2) pdr2 is a general i/o port data register of port 2. bit bit name initial value r/w description 7 6 5 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. 4 3 2 1 0 p24 p23 p22 p21 p20 0 0 0 0 0 r/w r/w r/w r/w r/w pdr2 stores output data for port 2 pins. if pdr2 is read while pcr2 bi ts are set to 1, the values stored in pdr2 are read. if pdr2 is read while pcr2 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr2.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 118 of 526 rej09b0060-0300 9.2.3 port mode register 3 (pmr3) pmr3 selects the cmos output or nmos open-drain output for port 2. bit bit name initial value r/w description 7 6 5 ? ? ? 0 0 0 ? ? ? reserved these bits are always read as 0. 4 3 pof24 pof23 0 0 r/w r/w when the bit is set to 1, the corresponding pin is cut off by pmos and it functions as the nmos open-drain output. when cleared to 0, the pin functions as the cmos output. 2 1 0 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. 9.2.4 pin functions the correspondence between the register specification and the port functions is shown below. ? register pcr2 bit name pcr24 pin function setting value 0 p24 input pin 1 p24 output pin ? register pcr2 bit name pcr23 pin function setting value 0 p23 input pin 1 p23 output pin
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 119 of 526 rej09b0060-0300 ? register pmr1 pcr2 bit name txd pcr22 pin function setting value 0 0 p22 input pin 1 p22 output pin 1 x txd output pin [legend] x: don't care. ? register scr3 pcr2 bit name re pcr21 pin function setting value 0 0 p21 input pin 1 p21 output pin 1 x rxd input pin [legend] x: don't care. ? register scr3 smr pcr2 bit name cke1 cke0 com pcr20 pin function setting value 0 0 0 0 p20 input pin 1 p20 output pin 0 0 1 x sck3 output pin 0 1 x x sck3 output pin 1 x x x sck3 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 120 of 526 rej09b0060-0300 9.3 port 3 port 3 is a general i/o port. each pin of the port 3 is shown in figure 9.3. p35 p36 p37 p30 p34 p33 p32 p31 port 3 figure 9.3 port 3 pin configuration port 3 has the following registers. ? ? 9.3.1 port control register 3 (pcr3) pcr3 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 3. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 pcr30 0 0 0 0 0 0 0 0 w w w w w w w w setting a pcr3 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 121 of 526 rej09b0060-0300 9.3.2 port data register 3 (pdr3) pdr3 is a general i/o port data register of port 3. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p37 p36 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr3 stores output data for port 3 pins. if pdr3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read. if pdr3 is read while pcr3 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr3. 9.3.3 pin functions the correspondence between the register specification and the port functions is shown below. ? register pcr3 bit name pcr37 pin function setting value 0 p37 input pin 1 p37 output pin ? register pcr3 bit name pcr36 pin function setting value 0 p36 input pin 1 p36 output pin
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 122 of 526 rej09b0060-0300 ? register pcr3 bit name pcr35 pin function setting value 0 p35 input pin 1 p35 output pin ? register pcr3 bit name pcr34 pin function setting value 0 p34 input pin 1 p34 output pin ? register pcr3 bit name pcr33 pin function setting value 0 p33 input pin 1 p33 output pin ? register pcr3 bit name pcr32 pin function setting value 0 p32 input pin 1 p32 output pin ? register pcr3 bit name pcr31 pin function setting value 0 p31 input pin 1 p31 output pin
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 123 of 526 rej09b0060-0300 ? register pcr3 bit name pcr30 pin function setting value 0 p30 input pin 1 p30 output pin 9.4 port 5 port 5 is a general i/o port also functioning as an i 2 c bus interface i/o pin, an a/d trigger input pin, and a wakeup interrupt input pin. each pin of the port 5 is shown in figure 9.4. the register setting of the i 2 c bus interface has priority for functions of the pins p57/scl and p56/sda. since the output buffer for pins p56 and p57 has the nmos push-pull structure, it differs from an output buffer with the cmos structure in the high-level output characteristics (see section 23, electrical characteristics). p55/ wkp5 / adtr g p56/sda p57/scl p50/ wkp0 p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 port 5 figure 9.4 port 5 pin configuration port 5 has the following registers. ? ? ? ?
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 124 of 526 rej09b0060-0300 9.4.1 port mode register 5 (pmr5) pmr5 switches the functions of pins in port 5. bit bit name initial value r/w description 7 6 pof57 pof56 0 0 r/w r/w when the bit is set to 1, the corresponding pin is cut off by pmos and it functions as the nmos open-drain output. when cleared to 0, the pin functions as the cmos output. 5 wkp5 0 r/w selects the function of pin p55/ wkp5 / adtrg . 0: general i/o port 1: wkp5 / adtrg input pin 4 wkp4 0 r/w selects the function of pin p54/ wkp4 . 0: general i/o port 1: wkp4 input pin 3 wkp3 0 r/w selects the function of pin p53/ wkp3 . 0: general i/o port 1: wkp3 input pin 2 wkp2 0 r/w selects the function of pin p52/ wkp2 . 0: general i/o port 1: wkp2 input pin 1 wkp1 0 r/w selects the function of pin p51/ wkp1 . 0: general i/o port 1: wkp1 input pin 0 wkp0 0 r/w selects the function of pin p50/ wkp0 . 0: general i/o port 1: wkp0 input pin
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 125 of 526 rej09b0060-0300 9.4.2 port control register 5 (pcr5) pcr5 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 5 pins p57 to p50 functions as a general i/o port, setting a pcr5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.4.3 port data register 5 (pdr5) pdr5 is a general i/o port data register of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57 p56 p55 p54 p53 p52 p51 p50 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr5 stores output data for port 5 pins. if pdr5 is read while pcr5 bi ts are set to 1, the values stored in pdr5 are read. if pdr5 is read while pcr5 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr5.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 126 of 526 rej09b0060-0300 9.4.4 port pull-up control register 5 (pucr5) pucr5 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 ? ? 0 0 ? ? reserved these bits are always read as 0. 5 4 3 2 1 0 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w only bits for which pcr5 is cleared are valid. the pull- up moss of the correspondin g pins enter the on-state when these bits are set to 1, while they enter the off- state when these bits are cleared to 0. 9.4.5 pin functions the correspondence between the register specification and the port functions is shown below. ? register iccr pcr5 bit name ice pcr57 pin function setting value 0 0 p57 input pin 1 p57 output pin 1 x scl i/o pin [legend] x: don't care. scl performs the nmos open-drain output, that enables a direct bus drive.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 127 of 526 rej09b0060-0300 ? register iccr pcr5 bit name ice pcr56 pin function setting value 0 0 p56 input pin 1 p56 output pin 1 x sda i/o pin [legend] x: don't care. sda performs the nmos open-drain output, that enables a direct bus drive. ? wkp5 / adtrg pin register pmr5 pcr5 bit name wkp5 pcr55 pin function setting value 0 0 p55 input pin 1 p55 output pin 1 x wkp5 / adtrg input pin [legend] x: don't care. ? wkp4 pin register pmr5 pcr5 bit name wkp4 pcr54 pin function setting value 0 0 p54 input pin 1 p54 output pin 1 x wkp4 input pin [legend] x: don't care. ? wkp3 pin register pmr5 pcr5 bit name wkp3 pcr53 pin function setting value 0 0 p53 input pin 1 p53 output pin 1 x wkp3 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 128 of 526 rej09b0060-0300 ? wkp2 pin register pmr5 pcr5 bit name wkp2 pcr52 pin function setting value 0 0 p52 input pin 1 p52 output pin 1 x wkp2 input pin [legend] x: don't care. ? wkp1 pin register pmr5 pcr5 bit name wkp1 pcr51 pin function setting value 0 0 p51 input pin 1 p51 output pin 1 x wkp1 input pin [legend] x: don't care. ? wkp0 pin register pmr5 pcr5 bit name wkp0 pcr50 pin function setting value 0 0 p50 input pin 1 p50 output pin 1 x wkp0 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 129 of 526 rej09b0060-0300 9.5 port 6 port 6 is a general i/o port also functioning as a timer z i/o pin. each pin of the port 6 is shown in figure 9.5. the register setting of the timer z has priority for functions of the pins for both uses. p65/ftiob1 p66/ftioc1 p67/ftiod1 p60/ftioa0 p64/ftioa1 p63/ftiod0 p62/ftioc0 p61/ftiob0 port 6 figure 9.5 port 6 pin configuration port 6 has the following registers. ? ? 9.5.1 port control register 6 (pcr6) pcr6 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 6. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 6 pins p67 to p60 functions as a general i/o port, setting a pcr6 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 130 of 526 rej09b0060-0300 9.5.2 port data register 6 (pdr6) pdr6 is a general i/o port data register of port 6. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p67 p66 p65 p64 p63 p62 p61 p60 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr6 stores output data for port 6 pins. if pdr6 is read while pcr6 bits are set to 1, the values stored in pdr6 are read. if pdr6 is read while pcr6 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr6. 9.5.3 pin functions the correspondence between the register specification and the port functions is shown below. ? register toer tfcr tpmr tiorc1 pcr6 bit name ed1 cmd1, cmd0 pwmd1 iod2 to iod0 pcr67 pin function setting value 1 00 0 000 or 1xx 0 p67 input/ftiod1 input pin 1 p67 output pin 0 00 0 001 or 01x x ftiod1 output pin 1 xxx other than 00 x xxx [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 131 of 526 rej09b0060-0300 ? register toer tfcr tpmr tiorc1 pcr6 bit name ec1 cmd1, cmd0 pwmc1 ioc2 to ioc0 pcr66 pin function setting value 1 00 0 000 or 1xx 0 p66 input/ftioc1 input pin 1 p66 output pin 0 00 0 001 or 01x x ftioc1 output pin 1 xxx other than 00 x xxx [legend] x: don't care. ? register toer tfcr tpmr tiora1 pcr6 bit name eb1 cmd1, cmd0 pwmb1 iob2 to iob0 pcr65 pin function setting value 1 00 0 000 or 1xx 0 p65 input/ftiob1 input pin 1 p65 output pin 0 00 0 001 or 01x x ftiob1 output pin 1 xxx other than 00 x xxx [legend] x: don't care. ? register toer tfcr tiora1 pcr6 bit name ea1 cmd1, cmd0 ioa2 to ioa0 pcr64 pin function setting value 1 xx 000 or 1xx 0 p64 input/ftioa1 input pin 1 p64 output pin 0 00 001 or 01x x ftioa1 output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 132 of 526 rej09b0060-0300 ? register toer tfcr tpmr tiorc0 pcr6 bit name ed0 cmd1, cmd0 pwmd0 iod2 to iod0 pcr63 pin function setting value 1 00 0 000 or 1xx 0 p63 input/ftiod0 input pin 1 p63 output pin 0 00 0 001 or 01x x ftiod0 output pin 1 xxx other than 00 x xxx [legend] x: don't care. ? register toer tfcr tpmr tiorc0 pcr6 bit name ec0 cmd1, cmd0 pwmc0 ioc2 to ioc0 pcr62 pin function setting value 1 00 0 000 or 1xx 0 p62 input/ftioc0 input pin 1 p62 output pin 0 00 0 001 or 01x x ftioc0 output pin 1 xxx other than 00 x xxx [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 133 of 526 rej09b0060-0300 ? register toer tfcr tpmr tiora0 pcr6 bit name eb0 cmd1, cmd0 pwmb0 iob2 to iob0 pcr61 pin function setting value 1 00 0 000 or 1xx 0 p61 input/ftiob0 input pin 1 p61 output pin 0 00 0 001 or 01x x ftiob0 output pin 1 xxx other than 00 x xxx [legend] x: don't care. ? register toer tfcr tfcr tiora0 pcr6 bit name ea0 cmd1, cmd0 stclk ioa2 to ioa0 pcr60 pin function setting 1 xx x 000 or 0 p60 input/ftioa0 input pin value 1xx 1 p60 output pin 0 00 0 001 or 01x x ftioa0 output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 134 of 526 rej09b0060-0300 9.6 port 7 port 7 is a general i/o port also functioning as a timer v i/o pin and sci3_2 i/o pin. each pin of the port 7 is shown in figure 9.6. the register settings of the timer v and sci3_2 have priority for functions of the pins for both uses. p76/tmov p77 p75/tmciv p74/tmriv p72/txd_2 p71/rxd_2 p70/sck3_2 port 7 figure 9.6 port 7 pin configuration port 7 has the following registers. ? ? 9.6.1 port control register 7 (pcr7) pcr7 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 7. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr77 pcr76 pcr75 pcr74 ? pcr72 pcr71 pcr70 0 0 0 0 ? 0 0 0 w w w w ? w w w when each of the port 7 pins p77 to p74 and p72 to p70 functions as a general i/o port, setting a pcr7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bit 3 is a reserved bit.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 135 of 526 rej09b0060-0300 9.6.2 port data register 7 (pdr7) pdr7 is a general i/o port data register of port 7. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p77 p76 p75 p74 ? p72 p71 p70 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w pdr7 stores output data for port 7 pins. if pdr7 is read while pcr7 bits are set to 1, the values stored in pdr7 are read. if pdr7 is read while pcr7 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr7. bit 3 is a reserved bit. this bit is always read as 1. 9.6.3 pin functions the correspondence between the register specification and the port functions is shown below. ? register pcr7 bit name pcr77 pin function setting value 0 p77 input pin 1 p77 output pin ? register tcsrv pcr7 bit name os3 to os0 pcr76 pin function setting value 0000 0 p76 input pin 1 p76 output pin other than above x tmov output pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 136 of 526 rej09b0060-0300 ? register pcr7 bit name pcr75 pin function setting value 0 p75 input/tmciv input pin 1 p75 output/tmciv input pin ? register pcr7 bit name pcr74 pin function setting value 0 p74 input/tmriv input pin 1 p74 output/tmriv input pin ? register pmr1 pcr7 bit name txd2 pcr72 pin function setting value 0 0 p72 input pin 1 p72 output pin 1 x txd_2 output pin [legend] x: don't care. ? register scr3_2 pcr7 bit name re pcr71 pin function setting value 0 0 p71 input pin 1 p71 output pin 1 x rxd_2 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 137 of 526 rej09b0060-0300 ? register scr3_2 smr_2 pcr7 bit name cke1 cke0 com pcr70 pin function setting value 0 0 0 0 p70 input pin 1 p70 output pin 0 0 1 x sck3_2 output pin 0 1 x x sck3_2 output pin 1 x x x sck3_2 input pin [legend] x: don't care. 9.7 port 8 port 8 is a general i/o port also functioning as a timer w i/o pin. each pin of the port 8 is shown in figure 9.7. the register setting of the timer w has priority for functions of the pins p84/ftiod, p83/ftioc, p82/ftiob, and p81/ftioa. the p80/ftci pin also functions as a timer w input port that is connected to the timer w regardless of the register setting of port 8. p85 p86 p87 p80/ftci p84/ftiod p83/ftioc p82/ftiob p81/ftioa port 8 figure 9.7 port 8 pin configuration port 8 has the following registers. ? ?
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 138 of 526 rej09b0060-0300 9.7.1 port control register 8 (pcr8) pcr8 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 8. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 8 pins p87 to p80 functions as a general i/o port, setting a pcr8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.7.2 port data register 8 (pdr8) pdr8 is a general i/o port data register of port 8. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p87 p86 p85 p84 p83 p82 p81 p80 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr8 stores output data for port 8 pins. if pdr8 is read while pcr8 bi ts are set to 1, the values stored in pdr8 are read. if pdr8 is read while pcr8 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr8.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 139 of 526 rej09b0060-0300 9.7.3 pin functions the correspondence between the register specification and the port functions is shown below. ? register pcr8 bit name pcr87 pin function setting value 0 p87 input pin 1 p87 output pin ? register pcr8 bit name pcr86 pin function setting value 0 p86 input pin 1 p86 output pin ? register pcr8 bit name pcr85 pin function setting value 0 p85 input pin 1 p85 output pin ? register tmrw tior1 pcr8 bit name pwmd iod2 iod1 iod0 pcr84 pin function setting value 0 0 0 0 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin 0 0 1 x ftiod output pin 0 1 x x ftiod output pin 1 x x 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin 1 x x x x pwm output [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 140 of 526 rej09b0060-0300 ? register tmrw tior1 pcr8 bit name pwmc ioc2 ioc1 ioc0 pcr83 pin function setting value 0 0 0 0 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin 0 0 1 x ftioc output pin 0 1 x x ftioc output pin 1 x x 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin 1 x x x x pwm output [legend] x: don't care. ? register tmrw tior0 pcr8 bit name pwmb iob2 iob1 iob0 pcr82 pin function setting value 0 0 0 0 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin 0 0 1 x ftiob output pin 0 1 x x ftiob output pin 1 x x 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin 1 x x x x pwm output [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 141 of 526 rej09b0060-0300 ? register tior0 pcr8 bit name ioa2 ioa1 ioa0 pcr81 pin function setting value 0 0 0 0 p81 input/ftioa input pin 1 p81 output/ftioa input pin 0 0 1 x ftioa output pin 0 1 x x ftioa output pin 1 x x 0 p81 input/ftioa input pin 1 p81 output/ftioa input pin [legend] x: don't care. ? register pcr8 bit name pcr80 pin function setting value 0 p80 input/ftci input pin 1 p80 output/ftci input pin 9.8 port 9 port 9 is a general i/o port also functioning as an sci3_3 i/o pin. each pin of the port 9 is shown in figure 9.8. the register setting of the sci3_3 has priority for functions of the pins for both uses. p95 p96 p97 p90/sck3_3 p94 p93 p92/txd_3 p91/rxd_3 port 9 figure 9.8 port 9 pin configuration
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 142 of 526 rej09b0060-0300 port 9 has the following registers. ? ? 9.8.1 port control register 9 (pcr9) pcr9 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 9. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr97 pcr96 pcr95 pcr94 pcr93 pcr92 pcr91 pcr90 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 9 pins p97 to p90 functions as a general i/o port, setting a pcr9 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.8.2 port data register 9 (pdr9) pdr9 is a general i/o port data register of port 9. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p97 p96 p95 p94 p93 p92 p91 p90 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr9 stores output data for port 9 pins. if pdr9 is read while pcr9 bits are set to 1, the values stored in pdr9 are read. if pdr9 is read while pcr9 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr9.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 143 of 526 rej09b0060-0300 9.8.3 pin functions the correspondence between the register specification and the port functions is shown below. ? register pcr9 bit name pcr97 pin function setting value 0 p97 input pin 1 p97 output pin ? register pcr9 bit name pcr96 pin function setting value 0 p96 input pin 1 p96 output pin ? register pcr9 bit name pcr95 pin function setting value 0 p95 input pin 1 p95 output pin ? register pcr9 bit name pcr94 pin function setting value 0 p94 input pin 1 p94 output pin ? register pcr9 bit name pcr93 pin function setting value 0 p93 input pin 1 p93 output pin
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 144 of 526 rej09b0060-0300 ? register smcr3 pcr9 bit name txd_3 pcr92 pin function setting value 0 0 p92 input pin 1 p92 output pin 1 x txd_3 output pin [legend] x: don't care. ? register scr3_3 pcr9 bit name re pcr91 pin function setting value 0 0 p91 input pin 1 p91 output pin 1 x rxd_3 input pin [legend] x: don't care. ? register scr3_3 smr3_3 pcr9 bit name cke1 cke0 com pcr90 pin function setting value 0 0 0 0 p90 input pin 1 p90 output pin 0 0 1 x sck3_3 output pin 0 1 x x sck3_3 output pin 1 x x x sck3_3 input pin [legend] x: don't care.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 145 of 526 rej09b0060-0300 9.9 port b port b is an input port also functioning as an a/d converter analog input pin. each pin of the port b is shown in figure 9.9. pb5/an5 pb6/an6 pb7/an7 pb0/an0 pb4/an4 pb3/an3 pb2/an2 pb1/an1 port b figure 9.9 port b pin configuration port b has the following register. ? 9.9.1 port data register b (pdrb) pdrb is a general input-only port data register of port b. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 ? ? ? ? ? ? ? ? r r r r r r r r the input value of each pin is read by reading this register. however, if a port b pin is designated as an analog input channel by adcsr of a/d converter, 0 is read.
section 9 i/o ports rev. 3.00 mar. 15, 2006 page 146 of 526 rej09b0060-0300
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 147 of 526 rej09b0060-0300 section 10 realtime clock (rtc) the realtime clock (rtc) is a timer used to count time ranging from a second to a week. figure 10.1 shows the block diagram of the rtc. 10.1 features ? ? ? ? ? ? ? pss 32-khz oscillator circuit rtccsr rsecdr rmindr rwkdr clock count control circuit interrupt control circuit interrupt rtccr1 rhrdr rtccr2 internal data bus 1/4 tmow [legend] rtccsr: rsecdr: rmindr: rhrdr: rwkdr: rtccr1: rtccr2: pss: clock source select register second date register/free running counter data register minute date register hour date register day-of-week date register rtc control register 1 rtc control register 2 prescaler s figure 10.1 block diagram of rtc
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 148 of 526 rej09b0060-0300 10.2 input/output pin table 10.1 shows the rtc input/output pin. table 10.1 pin configuration name abbreviation i/o function clock output tmow output rtc divided clock output 10.3 register descriptions the rtc has the following registers. ? ? ? ? ? ? ?
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 149 of 526 rej09b0060-0300 10.3.1 second data register/free runn ing counter data register (rsecdr) rsecdr counts the bcd-coded second value. the setti ng range is decimal 00 to 59. it is an 8-bit read register used as a counter, when it operates as a free running counter. for more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, data reading procedure. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 sc12 sc11 sc10 ? ? ? r/w r/w r/w counting ten's position of seconds counts on 0 to 5 for 60-second counting. 3 2 1 0 sc03 sc02 sc01 sc00 ? ? ? ? r/w r/w r/w r/w counting one's position of seconds counts on 0 to 9 once per second. when a carry is generated, 1 is added to the ten's position.
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 150 of 526 rej09b0060-0300 10.3.2 minute data register (rmindr) rmindr counts the bcd-coded minute value on the carry generated once per minute by the rsecdr counting. the setting range is decimal 00 to 59. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 mn12 mn11 mn10 ? ? ? r/w r/w r/w counting ten's position of minutes counts on 0 to 5 for 60-minute counting. 3 2 1 0 mn03 mn02 mn01 mn00 ? ? ? ? r/w r/w r/w r/w counting one's position of minutes counts on 0 to 9 once per minute. when a carry is generated, 1 is added to the ten's position.
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 151 of 526 rej09b0060-0300 10.3.3 hour data register (rhrdr) rhrdr counts the bcd-coded hour value on the carry generated once per hour by rmindr. the setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in rtccr1. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 ? 0 ? reserved this bit is always read as 0. 5 4 hr11 hr10 ? ? r/w r/w counting ten's position of hours counts on 0 to 2 for ten's position of hours. 3 2 1 0 hr03 hr02 hr01 hr00 ? ? ? ? r/w r/w r/w r/w counting one's position of hours counts on 0 to 9 once per hour. when a carry is generated, 1 is added to the ten's position.
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 152 of 526 rej09b0060-0300 10.3.4 day-of-week data register (rwkdr) rwkdr counts the bcd-coded day-of-week value on the carry generated once per day by rhrdr. the setting range is decimal 0 to 6 using bits wk2 to wk0. bit bit name initial value r/w description 7 bsy ? r rtc busy this bit is set to 1 when the rtc is updating (operating) the values of second, minute, hour, and day-of-week data registers. when this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 ? ? ? ? 0 0 0 0 ? ? ? ? reserved these bits are always read as 0. 2 1 0 wk2 wk1 wk0 ? ? ? r/w r/w r/w day-of-week counting day-of-week is indicated with a binary code 000: sunday 001: monday 010: tuesday 011: wednesday 100: thursday 101: friday 110: saturday 111: reserved (setting prohibited)
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 153 of 526 rej09b0060-0300 10.3.5 rtc control register 1 (rtccr1) rtccr1 controls start/stop and reset of the clock timer. for the definition of time expression, see figure 10.2. bit bit name initial value r/w description 7 run ? r/w rtc operation start 0: stops rtc operation 1: starts rtc operation 6 12/24 ? r/w operating mode 0: rtc operates in 12-hour mode. rhrdr counts on 0 to 11. 1: rtc operates in 24-hour mode. rhrdr counts on 0 to 23. 5 pm ? r/w a.m./p.m. 0: indicates a.m. when rtc is in the 12-hour mode. 1: indicates p.m. when rtc is in the 12-hour mode. 4 rst 0 r/w reset 0: normal operation 1: resets registers and control circuits except rtccsr and this bit. clear this bit to 0 after having been set to 1. 3 int ? r/w interrupt generation timing 0: generates a second, minute, hour, or day-of-week periodic interrupt during rtc busy period. 1: generates a second, minute, hour, or day-of-week periodic interrupt immediately after completing rtc busy period. 2 1 0 ? ? ? 0 0 0 ? ? ? reserved these bits are always read as 0.
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 154 of 526 rej09b0060-0300 24-hour count 01234567891011121314151617 12-hour count 0 pm 24-hour count 12-hour count pm 0 (morning) 1 (afternoon) noon 123456789101101234 5 18 19 20 21 22 23 0 6 1 (afternoon) 0 7 8 9 10 11 0 figure 10.2 definition of time expression
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 155 of 526 rej09b0060-0300 10.3.6 rtc control register 2 (rtccr2) rtccr2 controls rtc periodic interrupts of week s, days, hours, minutes, and seconds. enabling interrupts of weeks, days, hours, minutes, and seconds sets the irrta flag to 1 in the interrupt flag register 1 (irr1) when an interrupt occurs. it also controls an overflow interrupt of a free running counter when rtc operat es as a free running counter. bit bit name initial value r/w description 7 6 ? ? 0 0 ? ? reserved these bits are always read as 0. 5 foie ? r/w free running counter overflow interrupt enable 0: disables an overflow interrupt 1: enables an overflow interrupt 4 wkie ? r/w week periodic interrupt enable 0: disables a week periodic interrupt 1: enables a week periodic interrupt 3 dyie ? r/w day periodic interrupt enable 0: disables a day periodic interrupt 1: enables a day periodic interrupt 2 hrie ? r/w hour periodic interrupt enable 0: disables an hour periodic interrupt 1: enables an hour periodic interrupt 1 mnie ? r/w minute periodic interrupt enable 0: disables a minute periodic interrupt 1: enables a minute periodic interrupt 0 seie ? r/w second peri odic interrupt enable 0: disables a second periodic interrupt 1: enables a second periodic interrupt
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 156 of 526 rej09b0060-0300 10.3.7 clock source sel ect register (rtccsr) rtccsr selects clock source. a free running counter controls start/stop of counter operation by the run bit in rtccr1. when a clock other than 32.768 khz is selected, the rtc is disabled and operates as an 8-b it free running counter. when the rtc operates as an 8-bit free running counter, rsecdr enables counter values to be read. an interrupt can be generated by setting 1 to the foie bit in rtccr2 and enabling an overflow interrupt of the free running counter. a clock in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 5 rcs6 rcs5 0 0 r/w r/w clock output selection selects a clock output from the tmow pin when setting tmow in pmr1 to 1. 00: /4 01: /8 10: /16 11: /32 4 ? 0 ? reserved this bit is always read as 0. 3 2 1 0 rcs3 rcs2 rcs1 rcs0 1 0 0 0 r/w r/w r/w r/w clock source selection 0000: /8 ?????????????????? free running counter operation 0001: /32 ???????????????? free running counter operation 0010: /128 ?????????????? free running counter operation 0011: /256 ?????????????? free running counter operation 0100: /512 ?????????????? free running counter operation 0101: /2048 ???????????? free running counter operation 0110: /4096 ???????????? free running counter operation 0111: /8192 ???????????? free running counter operation 1xxx: 32.768 khz ??? rtc operation [legend] x: don't care
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 157 of 526 rej09b0060-0300 10.4 operation 10.4.1 initial settings of registers after power-on the rtc registers that store s econd, minute, hour, and day-of week data are not reset by a res input. therefore, all registers must be set to th eir initial values after power-on. once the register setting are made, the rtc provides an accurate time as long as power is supplied regardless of a res input. 10.4.2 initial setting procedure figure 10.3 shows the procedure for the initial se tting of the rtc. to set the rtc again, also follow this procedure. rtc operation is stopped. rtc registers and clock count controller are reset. clock output and clock source are selected and second, minute, hour, day-of-week,operating mode, and a.m/p.m are set. rtc operation is started. run in rtccr1=0 rst in rtccr1=1 rst in rtccr1=0 set rtccsr, rsecdr, rmindr,rhrdr, rwkdr,12/24 in rtccr1, and pm run in rtccr1=1 figure 10.3 initia l setting procedure
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 158 of 526 rej09b0060-0300 10.4.3 data reading procedure when the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be corr ect, and so the time data must be read again. figure 10.4 shows an example in which correct data is not obtained. in this exampl e, since only rsecdr is read after data update, about 1-minute inconsistency occurs. to avoid reading in this timing, the following processing must be performed. 1. check the setting of the bsy bit, and when the bsy bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. when about 62.5 ms is passed after the bsy bit is set to 1, the registers are updated, and the bsy bit is cleared to 0. 2. making use of interrupts, read from the second, minute, hour, and day-of week registers after the irrta flag in irr1 is set to 1 and the bsy bit is confirmed to be 0. 3. read from the second, minute, hour, and day-of week registers twice in a row, and if there is no change in the read data, the read data is used. before update rwkdr = h'03, rhddr = h'13, rmindr = h'46, rsecdr = h'59 bsy bit = 0 (1) day-of-week data register read h'03 (2) hour data register read h'13 (3) minute data register read h'46 bsy bit -> 1 (under data update) after update rwkdr = h'03, rhddr = h'13, rmindr = h'47, rsecdr = h'00 bsy bit -> 0 (4) second data register read h'00 processing flow figure 10.4 example: readin g of inaccurate time data
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 159 of 526 rej09b0060-0300 10.5 interrupt sources there are five kinds of rtc interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. when using an interrupt, initiate the rtc last af ter other registers are set. do not set multiple interrupt enable bits in rtccr2 simultaneously to 1. when an interrupt request of the rtc occurs, the irrta flag in irr1 is set to 1. when clearing the flag, write 0. table 10.2 interrupt sources interrupt name interrupt s ource interrupt enable bit overflow interrupt occurs when the free running counter is overflown. foie week periodic interrupt occurs every week when the day-of-week date register value becomes 0. wkie day periodic interrupt occurs every day when the day-of-week date register is counted. dyie hour periodic interrupt occurs every hour when the hour date register is counted. hrie minute periodic interrupt occurs every minute when the minute date register is counted. mnie second periodic interrupt occurs every second when the second date register is counted. scie
section 10 realtime clock (rtc) rev. 3.00 mar. 15, 2006 page 160 of 526 rej09b0060-0300
section 11 timer b1 rev. 3.00 mar. 15, 2006 page 161 of 526 rej09b0060-0300 section 11 timer b1 timer b1 is an 8-bit timer that increments each time a clock pulse is input. this timer has two operating modes, interval and auto reload. figure 11.1 shows a block diagram of timer b1. 11.1 features ? ? [legend] tmb1: tmib1 tcb1: timer mode register b1 timer counter b1 tlb1: irrtb1: timer load register b1 timer b1 interrupt request flag pss: tmib1: prescaler s timer b1 event input internal data bus tcb1 tmb1 pss tlb1 irrtb1 figure 11.1 block diagram of timer b1 11.2 input/output pin table 11.1 shows the timer b1 pin configuration. table 11.1 pin configuration name abbreviation i/o function timer b1 event input tmib1 input event input to tcb1
section 11 timer b1 rev. 3.00 mar. 15, 2006 page 162 of 526 rej09b0060-0300 11.3 register descriptions the timer b1 has the following registers. ? ? ? 11.3.1 timer mode register b1 (tmb1) tmb1 selects the auto-reload function and input clock. bit bit name initial value r/w description 7 tmb17 0 r/w auto-reload function select 0: interval timer function selected 1: auto-reload function selected 6 5 4 3 ? ? ? ? 1 1 1 1 ? ? ? ? reserved these bits are always read as 1. 2 1 0 tmb12 tmb11 tmb10 0 0 0 r/w r/w r/w clock select 000: internal clock: /8192 001: internal clock: /2048 010: internal clock: /512 011: internal clock: /256 100: internal clock: /64 101: internal clock: /16 110: internal clock: /4 111: external event (tmib1): rising or falling edge * note: * the edge of the external event signal is selected by bit ieg1 in the interrupt edge select register 1 (iegr1 ). see section 3.2.1, interrupt edge select register 1 (iegr1), for details. before setting tmb12 to tmb10 to 1, irq1 in the port mode register 1 (pmr1) should be set to 1.
section 11 timer b1 rev. 3.00 mar. 15, 2006 page 163 of 526 rej09b0060-0300 11.3.2 timer coun ter b1 (tcb1) tcb1 is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tmb12 to tmb10 in tmb1. tcb1 values can be read by the cpu at any time. when tcb1 overflows from h'ff to h'00 or to the value set in tlb1, the irrtb1 flag in irr2 is set to 1. tcb1 is allocated to the same address as tlb1. tcb1 is initialized to h'00. 11.3.3 timer load register b1 (tlb1) tlb1 is an 8-bit write-only register for setting the reload value of tcb1. when a reload value is set in tlb1, the same value is loaded into tcb1 as well, and tcb1 starts counting up from that value. when tcb1 overflows during operation in auto-reload mode, the tlb1 value is loaded into tcb1. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. tlb1 is allocated to the same address as tcb1. tlb1 is initialized to h'00. 11.4 operation 11.4.1 interval timer operation when bit tmb17 in tmb1 is cleared to 0, timer b1 functions as an 8-bit interval timer. upon reset, tcb1 is cleared to h'00 and bit tmb17 is cleared to 0, so up-counting and interval timing resume immediately. the operating clock of timer b1 is selected from seven internal clock signals output by prescaler s, or an external clock input at pin tmb1. the selection is made by bits tmb12 to tmb10 in tmb1. after the count value in tmb1 r eaches h'ff, the next clock sign al input causes timer b1 to overflow, setting flag irrtb1 in irr2 to 1. if ientb1 in ienr2 is 1, an interrupt is requested to the cpu. at overflow, tcb1 returns to h'00 and starts counting up again. during interval timer operation (tmb17 = 0), when a value is set in tlb1, the same value is set in tcb1.
section 11 timer b1 rev. 3.00 mar. 15, 2006 page 164 of 526 rej09b0060-0300 11.4.2 auto-reloa d timer operation setting bit tmb17 in tmb1 to 1 causes timer b1 to function as an 8-bit auto-reload timer. when a reload value is set in tlb1, the same value is loaded into tcb1, becoming the value from which tcb1 starts its count. after the count value in tcb1 reaches h'ff, the next clock signal input causes timer b1 to overflow. the tlb1 value is then loaded into tcb1, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb1 value. the clock sources and interrupts in auto-reload mo de are the same as in interval mode. in auto- reload mode (tmb17 = 1), when a new value is set in tlb1, the tlb1 value is also loaded into tcb1. 11.4.3 event counter operation timer b1 can operate as an event counter in which tmib1 is set to an event input pin. external event counting is selected by setting bits tmb12 to tmb10 in tmb1 to 1. tcb1 counts up at rising or falling edge of an external event signal input at pin tmb1. when timer b1 is used to count external event input, bit irq1 in pmr1 should be set to 1 and ien1 in ienr1 should be cleared to 0 to disable irq1 interrupt requests. 11.5 timer b1 operating modes table 11.2 shows the timer b1 operating modes. table 11.2 timer b1 operating modes operating mode reset active sleep subactive subsleep standby interval reset functions functions halted halted halted tcb1 auto-reload reset functions functions halted halted halted tmb1 reset functions retained retained retained retained
section 12 timer v rev. 3.00 mar. 15, 2006 page 165 of 526 rej09b0060-0300 section 12 timer v timer v is an 8-bit timer based on an 8-bit counter. timer v counts external events. compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. counting can be initiated by a trigger input at the trgv pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. figure 12.1 shows a block diagram of timer v. 12.1 features ? ? ? ? ?
section 12 timer v rev. 3.00 mar. 15, 2006 page 166 of 526 rej09b0060-0300 trgv tmciv tmriv tmov trigger control clock select clear control output control pss tcrv1 tcorb comparator tcntv comparator tcora tcrv0 interrupt request control tcsrv cmia cmib ovi internal data bus tcora: tcorb: tcntv: tcsrv: tcrv0: [legend] time constant register a time constant register b timer counter v timer control/status register v timer control register v0 tcrv1: pss: cmia: cmib: ovi: timer control register v1 prescaler s compare-match interrupt a compare-match interrupt b overflow interupt figure 12.1 block diagram of timer v
section 12 timer v rev. 3.00 mar. 15, 2006 page 167 of 526 rej09b0060-0300 12.2 input/output pins table 12.1 shows the timer v pin configuration. table 12.1 pin configuration name abbreviation i/o function timer v output tmov output timer v waveform output timer v clock input tmciv input clock input to tcntv timer v reset input tmriv input external input to reset tcntv trigger input trgv input trigger input to initiate counting 12.3 register descriptions time v has the following registers. ? ? ? ? ? ? 12.3.1 timer counter v (tcntv) tcntv is an 8-bit up-counter. the clock source is selected by bits cks2 to cks0 in timer control register v0 (tcrv0). the tcntv value can be read and written by the cpu at any time. tcntv can be cleared by an external reset in put signal, or by compare match a or b. the clearing signal is selected by bits cclr1 and cclr0 in tcrv0. when tcntv overflows, ovf is set to 1 in timer control/status register v (tcsrv). tcntv is initialized to h'00.
section 12 timer v rev. 3.00 mar. 15, 2006 page 168 of 526 rej09b0060-0300 12.3.2 time constant regi sters a, b (t cora, tcorb) tcora and tcorb have the same function. tcora and tcorb are 8-bit read able/writable registers. tcora and tcntv are compared at all times. when the tcora and tcntv contents match, cmfa is set to 1 in tcsrv. if cmiea is also se t to 1 in tcrv0, a cpu interrupt is requested. note that they must not be compared duri ng the t3 state of a tcora write cycle. timer output from the tmov pin can be controlled by the identifying signal (compare match a) and the settings of bits os3 to os0 in tcsrv. tcora and tcorb are initialized to h'ff.
section 12 timer v rev. 3.00 mar. 15, 2006 page 169 of 526 rej09b0060-0300 12.3.3 timer control register v0 (tcrv0) tcrv0 selects the input clock signals of tcntv, specifies the clearing conditions of tcntv, and controls each interrupt request. bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b when this bit is set to 1, interrupt request from the cmfb bit in tcsrv is enabled. 6 cmiea 0 r/w compare match interrupt enable a when this bit is set to 1, interrupt request from the cmfa bit in tcsrv is enabled. 5 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, interrupt request from the ovf bit in tcsrv is enabled. 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 these bits specify the clear ing conditions of tcntv. 00: clearing is disabled 01: cleared by compare match a 10: cleared by compare match b 11: cleared on the rising edge of the tmriv pin. the operation of tcntv after clearing depends on trge in tcrv1. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select clock signals to input to tcntv and the counting condition in combination with icks0 in tcrv1. refer to table 12.2.
section 12 timer v rev. 3.00 mar. 15, 2006 page 170 of 526 rej09b0060-0300 table 12.2 clock signals to input to tcntv and counting conditions tcrv0 tcrv1 bit 2 bit 1 bit 0 bit 0 cks2 cks1 cks0 icks0 description 0 0 0 ? clock input prohibited 1 0 internal clock: counts on /4, falling edge 1 internal clock: counts on /8, falling edge 1 0 0 internal clock: counts on /16, falling edge 1 internal clock: counts on /32, falling edge 1 0 internal clock: counts on /64, falling edge 1 internal clock: counts on /128, falling edge 1 0 0 ? clock input prohibited 1 ? external clock: counts on rising edge 1 0 ? external clock: counts on falling edge 1 ? external clock: counts on rising and falling edge 12.3.4 timer control/st atus register v (tcsrv) tcsrv indicates the status flag and controls outputs by using a compare match. bit bit name initial value r/w description 7 cmfb 0 r/w compare match flag b setting condition: when the tcntv value matches the tcorb value clearing condition: after reading cmfb = 1, cleared by writing 0 to cmfb 6 cmfa 0 r/w compare match flag a setting condition: when the tcntv value matches the tcora value clearing condition: after reading cmfa = 1, cleared by writing 0 to cmfa
section 12 timer v rev. 3.00 mar. 15, 2006 page 171 of 526 rej09b0060-0300 bit bit name initial value r/w description 5 ovf 0 r/w timer overflow flag setting condition: when tcntv overflows from h'ff to h'00 clearing condition: after reading ovf = 1, cleared by writing 0 to ovf 4 ? 1 ? reserved this bit is always read as 1. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits select an output method for the tomv pin by the compare match of tcorb and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits select an output method for the tomv pin by the compare match of tcora and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles os3 and os2 select the output level for compare match b. os1 and os0 select the output level for compare match a. the two output levels can be controlled independently. after a reset, the timer output is 0 until the first compare match.
section 12 timer v rev. 3.00 mar. 15, 2006 page 172 of 526 rej09b0060-0300 12.3.5 timer control register v1 (tcrv1) tcrv1 selects the edge at the trgv pin, enab les trgv input, and sel ects the clock input to tcntv. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 3 tveg1 tveg0 0 0 r/w r/w trgv input edge select these bits select the trgv input edge. 00: trgv trigger input is prohibited 01: rising edge is selected 10: falling edge is selected 11: rising and falling edges are both selected 2 trge 0 r/w tcnt starts countin g up by the input of the edge which is selected by tveg1 and tveg0. 0: disables starting counting- up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1: enables starting counting- up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1 ? 1 ? reserved this bit is always read as 1. 0 icks0 0 r/w internal clock select 0 this bit selects clock sign als to input to tcntv in combination with cks2 to cks0 in tcrv0. refer to table 12.2.
section 12 timer v rev. 3.00 mar. 15, 2006 page 173 of 526 rej09b0060-0300 12.4 operation 12.4.1 timer v operation 1. according to table 12.2, six internal/external clock signals output by prescaler s can be selected as the timer v operating clock signals . when the operating cl ock signal is selected, tcntv starts counting-up. figure 12.2 shows the count timing with an internal clock signal selected, and figure 12.3 shows the count timing with both edges of an external clock signal selected. 2. when tcntv overflows (changes from h'ff to h'00), the overflow flag (ovf) in tcrv0 will be set. the timing at this time is shown in fi gure 12.4. an interrupt request is sent to the cpu when ovie in tcrv0 is 1. 3. tcntv is constantly compared with tcora and tcorb. compare match flag a or b (cmfa or cmfb) is set to 1 when tcntv ma tches tcora or tcorb, respectively. the compare-match signal is generated in the last state in which the values match. figure 12.5 shows the timing. an interrupt request is ge nerated for the cpu when cmiea or cmieb in tcrv0 is 1. 4. when a compare match a or b is generated, the tmov responds with the output value selected by bits os3 to os0 in tcsrv. figure 12.6 shows the timing when the output is toggled by compare match a. 5. when cclr1 or cclr0 in tcrv0 is 01 or 10, tcntv can be cleared by the corresponding compare match. figure 12.7 shows the timing. 6. when cclr1 or cclr0 in tcrv0 is 11, tcnt v can be cleared by the rising edge of the input of tmriv pin. a tmriv input pulse-width of at least 1.5 system clocks is necessary. figure 12.8 shows the timing. 7. when a counter-clearing source is generated with trge in tcrv1 set to 1, the counting-up is halted as soon as tcntv is cleared. tcntv re sumes counting-up when the edge selected by tveg1 or tveg0 in tcrv1 is input from the tgrv pin.
section 12 timer v rev. 3.00 mar. 15, 2006 page 174 of 526 rej09b0060-0300 n ? 1 n + 1 n internal clock tcntv input clock tcntv figure 12.2 increment timi ng with internal clock n ? 1 n + 1 n tmciv (external clock input pin) tcntv input clock tcntv figure 12.3 increment timing with external clock h'ff h'00 tcntv overflow signal ovf figure 12.4 ovf set timing
section 12 timer v rev. 3.00 mar. 15, 2006 page 175 of 526 rej09b0060-0300 n n n+1 tcntv tcora or tcorb compare match signal cmfa or cmfb figure 12.5 cmfa and cmfb set timing compare match a signal timer v output pin figure 12.6 tmov output timing n h'00 compare match a signal tcntv figure 12.7 clear ti ming by compare match
section 12 timer v rev. 3.00 mar. 15, 2006 page 176 of 526 rej09b0060-0300 n ? 1 n h'00 compare match a signal timer v output pin tcntv figure 12.8 clear ti ming by tmriv input 12.5 timer v application examples 12.5.1 pulse output with arbitrary duty cycle figure 12.9 shows an example of output of pulses with an arbitrary duty cycle. 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcora. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 4. with these settings, a waveform is output without further software intervention, with a period determined by tcora and a pulse width determined by tcorb. counter cleared time tcntv value h'ff tcora tcorb h'00 tmov figure 12.9 pulse output example
section 12 timer v rev. 3.00 mar. 15, 2006 page 177 of 526 rej09b0060-0300 12.5.2 pulse output with arbitrary pulse width and delay from trgv input the trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the trgv input, as shown in figure 12.10. to set up this output: 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcorb. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits tveg1 and tveg0 in tcrv1 and set trge to select the falling edge of the trgv input. 4. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 5. with these settings, a pulse waveform will be output without further software intervention, with a delay determined by tcora from the trgv input, and a pulse width determined by (tcorb ? tcora). counter cleared h'ff tcora tcorb h'00 trgv tmov compare match a compare match b clears tcntv and halts count-up compare match b clears tcntv and halts count-up compare match a tcntv value time figure 12.10 example of pulse ou tput synchronized to trgv input
section 12 timer v rev. 3.00 mar. 15, 2006 page 178 of 526 rej09b0060-0300 12.6 usage notes the following types of contention or operation can occur in timer v operation. 1. writing to registers is performed in the t3 state of a tcntv write cycle. if a tcntv clear signal is generated in the t3 state of a tcntv write cycle, as shown in figure 12.11, clearing takes precedence and the write to the counter is not carried out. if counting-up is generated in the t3 state of a tcntv write cycle, writing takes precedence. 2. if a compare match is generated in the t3 st ate of a tcora or tcorb write cycle, the write to tcora or tcorb takes precedence and the compare match signal is inhibited. figure 12.12 shows the timing. 3. if compare matches a and b occur simultaneous ly, any conflict between the output selections for compare match a and compare match b is re solved by the following priority: toggle output > > address tcntv address tcntv write cycle by cpu internal write signal counter clear signal tcntv n h'00 t 1 t 2 t 3 figure 12.11 contention between tcntv write and clear
section 12 timer v rev. 3.00 mar. 15, 2006 page 179 of 526 rej09b0060-0300 address tcora address internal write signal tcntv tcora n n n+1 m tcora write data inhibited t 1 t 2 t 3 tcora write cycle by cpu compare match signal figure 12.12 contention betwee n tcora write and compare match clock before switching clock after switching count clock tcntv n n+1 n+2 write to cks1 and cks0 figure 12.13 internal clock switching and tcntv operation
section 12 timer v rev. 3.00 mar. 15, 2006 page 180 of 526 rej09b0060-0300
section 13 timer w rev. 3.00 mar. 15, 2006 page 181 of 526 rej09b0060-0300 section 13 timer w the timer w is a 16-bit timer having output co mpare and input capture functions. timer w can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. thus, it can be applied to various systems. 13.1 features ? ? ? ? ? ?
section 13 timer w rev. 3.00 mar. 15, 2006 page 182 of 526 rej09b0060-0300 table 13.1 summarizes the timer w functions, and figure 13.1 shows a block diagram of timer w. table 13.1 timer w functions input/output pins item counter ftioa ftiob ftioc ftiod count clock internal clocks: , /2, /4, /8 external clock: ftci general registers (output compare/input capture registers) period specified in gra gra grb grc (buffer register for gra in buffer mode) grd (buffer register for grb in buffer mode) counter clearing function gra compare match gra compare match ? ? ? initial output value setting function ? yes yes yes yes buffer function ? yes yes ? ? compare 0 ? yes yes yes yes match output 1 ? yes yes yes yes toggle ? yes yes yes yes input capture function ? yes yes yes yes pwm mode ? ? yes yes yes interrupt sources overflow compare match/input capture compare match/input capture compare match/input capture compare match/input capture
section 13 timer w rev. 3.00 mar. 15, 2006 page 183 of 526 rej09b0060-0300 internal clock: external clock: ftci ftioa ftiob ftioc ftiod irrtw control logic clock selector comparator tcnt internal data bus bus interface [legend] tmrw: tcrw: tierw: tsrw: tior: tcnt: gra: grb: grc: grd: timer mode register w (8 bits) timer control register w (8 bits) timer interrupt enable register w (8 bits) timer status register w (8 bits) timer i/o control register (8 bits) timer counter (16 bits) general register a (input capture/output compare register: 16 bits) general register b (input capture/output compare register: 16 bits) general register c (input capture/output compare register: 16 bits) general register d (input capture/output compare register: 16 bits) gra grb grc grd tmrw tcrw tierw tsrw tior /2 /4 /8 figure 13.1 block diagram of timer w
section 13 timer w rev. 3.00 mar. 15, 2006 page 184 of 526 rej09b0060-0300 13.2 input/output pins table 13.2 summarizes the timer w pins. table 13.2 pin configuration name abbreviation input/output function external clock input ftci input external clock input pin input capture/output compare a ftioa input/output output pi n for gra output compare or input pin for gra input capture input capture/output compare b ftiob input/output output pi n for grb output compare, input pin for grb input capture, or pwm output pin in pwm mode input capture/output compare c ftioc input/output output pi n for grc output compare, input pin for grc input capture, or pwm output pin in pwm mode input capture/output compare d ftiod input/output output pi n for grd output compare, input pin for grd input capture, or pwm output pin in pwm mode 13.3 register descriptions the timer w has the following registers. ? ? ? ? ? ? ? ? ? ? ?
section 13 timer w rev. 3.00 mar. 15, 2006 page 185 of 526 rej09b0060-0300 13.3.1 timer mode register w (tmrw) tmrw selects the general register functions and the timer output mode. bit bit name initial value r/w description 7 cts 0 r/w counter start the counter operation is halted when this bit is 0; while it can be performed when this bit is 1. 6 ? 1 ? reserved this bit is always read as 1. 5 bufeb 0 r/w buffer operation b selects the grd function. 0: grd operates as an input capture/output compare register 1: grd operates as the buffer register for grb 4 bufea 0 r/w buffer operation a selects the grc function. 0: grc operates as an input capture/output compare register 1: grc operates as the buffer register for gra 3 ? 1 ? reserved this bit is always read as 1. 2 pwmd 0 r/w pwm mode d selects the output mode of the ftiod pin. 0: ftiod operates normally (output compare output) 1: pwm output 1 pwmc 0 r/w pwm mode c selects the output mode of the ftioc pin. 0: ftioc operates normally (output compare output) 1: pwm output 0 pwmb 0 r/w pwm mode b selects the output mode of the ftiob pin. 0: ftiob operates normally (output compare output) 1: pwm output
section 13 timer w rev. 3.00 mar. 15, 2006 page 186 of 526 rej09b0060-0300 13.3.2 timer control register w (tcrw) tcrw selects the timer counter clock source, sel ects a clearing condition, and specifies the timer initial output levels. bit bit name initial value r/w description 7 cclr 0 r/w counter clear the tcnt value is cleared by compare match a when this bit is 1. when it is 0, tcnt operates as a free- running counter. 6 5 4 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select the tcnt clock source. 000: internal clock: counts on 001: internal clock: counts on /2 010: internal clock: counts on /4 011: internal clock: counts on /8 1xx: counts on rising edges of the external event (ftci) when the internal clock source ( ) is selected, subclock sources are counted in subactive and subsleep modes. 3 tod 0 r/w timer output level setting d sets the output value of t he ftiod pin until the first compare match d is generated. 0: initial output value is 0 * 1: initial output value is 1 * 2 toc 0 r/w timer output level setting c sets the output value of t he ftioc pin until the first compare match c is generated. 0: initial output value is 0 * 1: initial output value is 1 * 1 tob 0 r/w timer output level setting b sets the output value of t he ftiob pin until the first compare match b is generated. 0: initial output value is 0 * 1: initial output value is 1 *
section 13 timer w rev. 3.00 mar. 15, 2006 page 187 of 526 rej09b0060-0300 bit bit name initial value r/w description 0 toa 0 r/w timer output level setting a sets the output value of t he ftioa pin until the first compare match a is generated. 0: initial output value is 0 * 1: initial output value is 1 * [legend] x: don't care. note: * the change of the setting is immediat ely reflected in the output value. 13.3.3 timer interrupt en able register w (tierw) tierw controls the timer w interrupt request. bit bit name initial value r/w description 7 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, fovi interrupt requested by ovf flag in tsrw is enabled. 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 imied 0 r/w input capture/com pare match interrupt enable d when this bit is set to 1, imid interrupt requested by imfd flag in tsrw is enabled. 2 imiec 0 r/w input capture/com pare match interrupt enable c when this bit is set to 1, imic interrupt requested by imfc flag in tsrw is enabled. 1 imieb 0 r/w input capture/com pare match interrupt enable b when this bit is set to 1, imib interrupt requested by imfb flag in tsrw is enabled. 0 imiea 0 r/w input capture/com pare match interrupt enable a when this bit is set to 1, imia interrupt requested by imfa flag in tsrw is enabled.
section 13 timer w rev. 3.00 mar. 15, 2006 page 188 of 526 rej09b0060-0300 13.3.4 timer status register w (tsrw) tsrw shows the status of interrupt requests. bit bit name initial value r/w description 7 ovf 0 r/w timer overflow flag [setting condition] ? when tcnt overflows from h'ffff to h'0000 [clearing condition] ? read ovf when ovf=1, then write 0 in ovf 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3 imfd 0 r/w input capt ure/compare match flag d [setting conditions] ? tcnt=grd when grd functions as an output compare register ? the tcnt value is transferred to grd by an input capture signal when grd functions as an input capture register [clearing condition] ? read imfd when imfd=1, then write 0 in imfd 2 imfc 0 r/w input capt ure/compare match flag c [setting conditions] ? tcnt=grc when grc functions as an output compare register ? the tcnt value is transferred to grc by an input capture signal when grc functions as an input capture register [clearing condition] ? read imfc when imfc=1, then write 0 in imfc
section 13 timer w rev. 3.00 mar. 15, 2006 page 189 of 526 rej09b0060-0300 bit bit name initial value r/w description 1 imfb 0 r/w input capt ure/compare match flag b [setting conditions] ? tcnt=grb when grb functions as an output compare register ? the tcnt value is transferred to grb by an input capture signal when grb functions as an input capture register [clearing condition] ? read imfb when imfb=1, then write 0 in imfb 0 imfa 0 r/w input capt ure/compare match flag a [setting conditions] ? tcnt=gra when gra functions as an output compare register ? the tcnt value is transferred to gra by an input capture signal when gra functions as an input capture register [clearing condition] ? read imfa when imfa=1, then write 0 in imfa 13.3.5 timer i/o control register 0 (tior0) tior0 selects the functions of gra and grb, and specifies the functions of the ftioa and ftiob pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iob2 0 r/w i/o control b2 selects the grb function. 0: grb functions as an output compare register 1: grb functions as an input capture register
section 13 timer w rev. 3.00 mar. 15, 2006 page 190 of 526 rej09b0060-0300 bit bit name initial value r/w description 5 4 iob1 iob0 0 0 r/w r/w i/o control b1 and b0 when iob2 = 0, 00: no output at compare match 01: 0 output to the ftiob pin at grb compare match 10: 1 output to the ftiob pin at grb compare match 11: output toggles to the ftiob pin at grb compare match when iob2 = 1, 00: input capture at risi ng edge at the ftiob pin 01: input capture at fallin g edge at the ftiob pin 1x: input capture at rising edge and falling edge at the ftiob pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioa2 0 r/w i/o control a2 selects the gra function. 0: gra functions as an output compare register 1: gra functions as an input capture register 1 0 ioa1 ioa0 0 0 r/w r/w i/o control a1 and a0 when ioa2 = 0, 00: no output at compare match 01: 0 output to the ftioa pin at gra compare match 10: 1 output to the ftioa pin at gra compare match 11: output toggles to the ftioa pin at gra compare match when ioa2 = 1, 00: input capture at risi ng edge of the ftioa pin 01: input capture at fallin g edge of the ftioa pin 1x: input capture at rising edge and falling edge of the ftioa pin [legend] x: don't care.
section 13 timer w rev. 3.00 mar. 15, 2006 page 191 of 526 rej09b0060-0300 13.3.6 timer i/o control register 1 (tior1) tior1 selects the functions of grc and grd, and specifies the functions of the ftioc and ftiod pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iod2 0 r/w i/o control d2 selects the grd function. 0: grd functions as an output compare register 1: grd functions as an input capture register 5 4 iod1 iod0 0 0 r/w r/w i/o control d1 and d0 when iod2 = 0, 00: no output at compare match 01: 0 output to the ftiod pin at grd compare match 10: 1 output to the ftiod pin at grd compare match 11: output toggles to the ftiod pin at grd compare match when iod2 = 1, 00: input capture at rising edge at the ftiod pin 01: input capture at falling edge at the ftiod pin 1x: input capture at rising edge and falling edge at the ftiod pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioc2 0 r/w i/o control c2 selects the grc function. 0: grc functions as an output compare register 1: grc functions as an input capture register
section 13 timer w rev. 3.00 mar. 15, 2006 page 192 of 526 rej09b0060-0300 bit bit name initial value r/w description 1 0 ioc1 ioc0 0 0 r/w r/w i/o control c1 and c0 when ioc2 = 0, 00: no output at compare match 01: 0 output to the ftioc pin at grc compare match 10: 1 output to the ftioc pin at grc compare match 11: output toggles to the ftioc pin at grc compare match when ioc2 = 1, 00: input capture to grc at rising edge of the ftioc pin 01: input capture to grc at falling edge of the ftioc pin 1x: input capture to grc at rising edge and falling edge of the ftioc pin [legend] x: don't care. 13.3.7 timer counter (tcnt) tcnt is a 16-bit readable/writable up-counter. th e clock source is selected by bits cks2 to cks0 in tcrw. tcnt can be cleared to h'0000 through a compare match with gra by setting the cclr bit in tcrw to 1. when tcnt overflows (changes from h'ffff to h'0000), the ovf flag in tsrw is set to 1. if the ovie bit in tier w is set to 1 at this time, an interrupt request is generated. tcnt must always be read or writte n in 16-bit units; 8-bit access is not allowed. tcnt is initialized to h'0000.
section 13 timer w rev. 3.00 mar. 15, 2006 page 193 of 526 rej09b0060-0300 13.3.8 general registers a to d (gra to grd) each general register is a 16-bit readable/writable register that can function as either an output- compare register or an input-capture register. the function is selected by settings in tior0 and tior1. when a general register is used as an output-compare register, its value is constantly compared with the tcnt value. when the two values match (a compare match), the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. an interrupt request is generated at this time, when imiea, imieb, imiec, or imied is set to 1. compare match output can be selected in tior. when a general register is used as an input-captu re register, an external input-capture signal is detected and the current tcnt value is stored in the general register. the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. if the corresponding interrupt-enable bit (imiea, imieb, imiec, or imied) in tsrw is set to 1 at this time, an interrupt request is generated. the edge of the input-cap ture signal is selected in tior. grc and grd can be used as buffer registers of gra and grb, respectively, by setting bufea and bufeb in tmrw. for example, when gra is set as an output-compare register and grc is set as the buffer register for gra, the value in the buffer register grc is sent to gra whenever compare match a is generated. when gra is set as an input-capture register and grc is set as the buffer register for gra, the value in tcnt is transferred to gra and the valu e in gra is transferred to the buffer register grc whenever an input capture is generated. gra to grd must be written or read in 16-bit units; 8-bit access is not a llowed. gra to grd are initialized to h'ffff.
section 13 timer w rev. 3.00 mar. 15, 2006 page 194 of 526 rej09b0060-0300 13.4 operation the timer w has the following operation modes: ? ? 13.4.1 normal operation tcnt performs free-running or periodic counting operations. after a reset, tcnt is set as a free- running counter. when the cst bit in tmrw is se t to 1, tcnt starts incrementing the count. when the count overflows from h'ffff to h'0000, the ovf flag in tsrw is set to 1. if the ovie in tierw is set to 1, an interrupt request is ge nerated. figure 13.2 shows free-running counting. tcnt value h'ffff h'0000 cst bit ovf time flag cleared by software figure 13.2 free-running counter operation
section 13 timer w rev. 3.00 mar. 15, 2006 page 195 of 526 rej09b0060-0300 periodic counting operation can be performed when gra is set as an output compare register and bit cclr in tcrw is set to 1. when the count matches gra, tcnt is cleared to h' 0000, the imfa flag in tsrw is set to 1. if the corresponding imiea bit in tierw is set to 1, an interrupt request is generated. tcnt continues counting from h'0000. figure 13.3 shows periodic counting. tcnt value gra h'0000 cst bit imfa time flag cleared by software figure 13.3 periodic counter operation by setting a general register as an output comp are register, compare matc h a, b, c, or d can cause the output at the ftioa, ftiob, ftioc, or ftiod pin to output 0, output 1, or toggle. figure 13.4 shows an example of 0 and 1 output when tcnt operates as a free-running counter, 1 output is selected for compare match a, and 0 output is selected for compare match b. when signal is already at the selected output level, the signal level does not ch ange at compare match. tcnt value h'ffff h'0000 ftioa ftiob time gra grb no change no change no change no change figure 13.4 0 and 1 output example (toa = 0, tob = 1)
section 13 timer w rev. 3.00 mar. 15, 2006 page 196 of 526 rej09b0060-0300 figure 13.5 shows an example of toggle output when tcnt operates as a free-running counter, and toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output figure 13.5 toggle output example (toa = 0, tob = 1) figure 13.6 shows another example of toggle output when tcnt operates as a periodic counter, cleared by compare matc h a. toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time grb gra toggle output toggle output counter cleared by compare match with gra figure 13.6 toggle output example (toa = 0, tob = 1)
section 13 timer w rev. 3.00 mar. 15, 2006 page 197 of 526 rej09b0060-0300 by setting a general register as an input-capture register, the tcnt value can be captured into a general register (gra, grb, grc, or grd) when a signal level changes at an input-capture pin (ftioa, ftiob, ftioc, or ftiod) . capture can take place on the rising edge, fa lling edge, or both edges. by using the input-capture function, the pulse width and periods can be measured. figure 13.7 shows an example of input capture when both edges of ftioa and the falling edge of ftiob are selected as capture edges. tc nt operates as a free-running counter. tcnt value h'ffff h'1000 h'0000 ftioa gra time h'aa55 h'55aa h'f000 h'1000 h'f000 h'55aa grb h'aa55 ftiob figure 13.7 input capture operating example
section 13 timer w rev. 3.00 mar. 15, 2006 page 198 of 526 rej09b0060-0300 figure 13.8 shows an example of buffer operation when the gra is set as an input-capture register and grc is set as the bu ffer register for gra. tcnt op erates as a free-running counter, and ftioa captures both rising and falling edge of the input signal. due to the buffer operation, the gra value is transferred to grc by input-cap ture a and the tcnt value is stored in gra. tcnt value h'da91 h'0245 h'0000 grc time h'0245 ftioa gra h'5480 h'0245 h'ffff h'5480 h'5480 h'da91 figure 13.8 buffer operation example (input capture)
section 13 timer w rev. 3.00 mar. 15, 2006 page 199 of 526 rej09b0060-0300 13.4.2 pwm operation in pwm mode, pwm waveforms are generated by using gra as the cycle register and grb, grc, and grd as duty registers. pwm waveforms are output from the ftiob, ftioc, and ftiod pins. up to three-phase pwm waveforms can be output. in pwm mode, a general register functions as an output compare register automatically. the out put level of each pin depends on the corresponding timer output level set bit (tob, to c, tod) in tcrw. when tob is 1, the ftiob output goes to 1 at compare match a and to 0 at compare match b. when tob is 0, the ftiob output goes to 0 at compare match a and to 1 at compare match b. thus the compare match output level settings in tior0 and tior1 are ignored for the output pin set to pwm mode. if the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. figure 13.9 shows an example of operation in pwm mode. the output signals go to 1 and tcnt is cleared at compare match a, and the output signals go to 0 at compare match b, c, and d (tob, toc, and tod = 1). tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 13.9 pwm mode example (1)
section 13 timer w rev. 3.00 mar. 15, 2006 page 200 of 526 rej09b0060-0300 figure 13.10 shows another example of operation in pwm mode. the output signals go to 0 and tcnt is cleared at compare match a, and the output signals go to 1 at compare match b, c, and d (tob, toc, and tod = 0). tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 13.10 pwm mode example (2)
section 13 timer w rev. 3.00 mar. 15, 2006 page 201 of 526 rej09b0060-0300 figure 13.11 shows an example of buffer opera tion when the ftiob pin is set to pwm mode and grd is set as the buffer register for grb. tc nt is cleared by compare match a, and ftiob outputs 1 at compare match b and 0 at compare match a. due to the buffer operation, the ftiob output level changes and the value of buffer register grd is transferred to grb whenever compare match b occurs. this proc edure is repeated every time compare match b occurs. tcnt value gra h'0000 grd time grb h'0200 h'0520 ftiob h'0200 h'0450 h'0520 h'0450 grb h'0450 h'0520 h'0200 figure 13.11 buffer operatio n example (output compare)
section 13 timer w rev. 3.00 mar. 15, 2006 page 202 of 526 rej09b0060-0300 figures 13.12 and 13.13 show examples of the output of pwm waveforms with duty cycles of 0% and 100%. tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 0% write to grb figure 13.12 pwm mode example (tob = 0, toc = 0, tod = 0: initial output values are set to 0)
section 13 timer w rev. 3.00 mar. 15, 2006 page 203 of 526 rej09b0060-0300 tcnt value gra h'0000 ftiob time grb duty 100% write to grb tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 100% write to grb write to grb write to grb figure 13.13 pwm mode example (tob = 1, toc = 1,and tod = 1: initial output values are set to 1)
section 13 timer w rev. 3.00 mar. 15, 2006 page 204 of 526 rej09b0060-0300 13.5 operation timing 13.5.1 tcnt count timing figure 13.14 shows the tcnt count timing when the internal clock source is selected. figure 13.15 shows the timing when the ex ternal clock source is selected. the pulse width of the external clock signal must be at least two system clock ( tcnt tcnt input clock internal clock n n+1 n+2 rising edge figure 13.14 count timing for internal clock source tcnt tcnt input clock external clock n n+1 n+2 rising edge rising edge figure 13.15 count timing for external clock source
section 13 timer w rev. 3.00 mar. 15, 2006 page 205 of 526 rej09b0060-0300 13.5.2 output compare timing the compare match signal is generated in the last state in which tcnt and the general register match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the compare match output pin (ftioa, ftiob, ftioc, or ftiod). when tcnt matches a general register, the compare match signal is generated only after the next counter clock pulse is input. figure 13.16 shows the output compare timing. gra to grd tcnt tcnt input clock n n n+1 compare match signal ftioa to ftiod figure 13.16 output compare output timing
section 13 timer w rev. 3.00 mar. 15, 2006 page 206 of 526 rej09b0060-0300 13.5.3 input ca pture timing input capture on the rising edge, falling edge, or both edges can be selected through settings in tior0 and tior1. figure 13.17 shows the timing when the falling edge is selected. the pulse width of the input capture signal mu st be at least two system clock ( tcnt input capture input n?1 n n+1 n+2 n gra to grd input capture signal figure 13.17 input capture input signal timing 13.5.4 timing of counter clearing by compare match figure 13.18 shows the timing when the counter is cleared by compare match a. when the gra value is n, the counter counts from 0 to n, and its cycle is n + 1. tcnt compare match signal gra n n h'0000 figure 13.18 timing of count er clearing by compare match
section 13 timer w rev. 3.00 mar. 15, 2006 page 207 of 526 rej09b0060-0300 13.5.5 buffer operation timing figures 13.19 and 13.20 show the buffer operation timing. grc, grd compare match signal tcnt gra, grb n n+1 m m figure 13.19 buffer operat ion timing (compare match) gra, grb tcnt input capture signal grc, grd n m m n+1 n nn+1 figure 13.20 buffer operation timing (input capture)
section 13 timer w rev. 3.00 mar. 15, 2006 page 208 of 526 rej09b0060-0300 13.5.6 timing of imfa to imfd flag setting at compare match if a general register (gra, grb, grc, or grd) is used as an output compare register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when tcnt matches the general register. the compare match signal is generated in the last state in which the values match (when tcnt changes from the matching value to the next value). therefore, when tcnt matches a general register, the compare match signal is generated only after the next tcnt clock pulse is input. figure 13.21 shows the timing of the im fa to imfd flag setting at compare match. gra to grd tcnt tcnt input clock n n n+1 compare match signal imfa to imfd irrtw figure 13.21 timing of imfa to imfd flag setting at compare match
section 13 timer w rev. 3.00 mar. 15, 2006 page 209 of 526 rej09b0060-0300 13.5.7 timing of imfa to im fd setting at input capture if a general register (gra, grb, grc, or grd) is used as an input capture register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when an input capture occurs. figure 13.22 shows the timing of the imfa to imfd flag setting at input capture. gra to grd tcnt input capture signal n n imfa to imfd irrtw figure 13.22 timing of imfa to imfd flag setting at input capture 13.5.8 timing of st atus flag clearing when the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 13.23 shows th e status flag clearing timing. imfa to imfd write signal address tsrw address irrtw tsrw write cycle t 1 t 2 figure 13.23 timing of status flag clearing by cpu
section 13 timer w rev. 3.00 mar. 15, 2006 page 210 of 526 rej09b0060-0300 13.6 usage notes the following types of contention or operation can occur in timer w operation. 1. the pulse width of the input clock signal and the input capture signal must be at least two system clock ( counter clear signal write signal address tcnt address tcnt tcnt write cycle t 1 t 2 n h'0000 figure 13.24 contention between tcnt write and clear
section 13 timer w rev. 3.00 mar. 15, 2006 page 211 of 526 rej09b0060-0300 tcnt previous clock n n+1 n+2 n+3 new clock count clock the change in signal level at clock switching is assumed to be a rising edge, and tcnt increments the count. figure 13.25 internal clock switching and tcnt operation
section 13 timer w rev. 3.00 mar. 15, 2006 page 212 of 526 rej09b0060-0300 5. the toa to tod bits in tcrw decide the value of the ftio pin, which is output until the first compare match occurs. once a compare matc h occurs and this comp are match changes the values of ftioa to ftiod output, the values of the ftioa to ftiod pin output and the values read from the toa to tod bits may differ. moreover, when the writing to tcrw and the generation of the compare match a to d occur at the same timing, the writing to tcrw has the priority. thus, output change due to the compare match is not reflected to the ftioa to ftiod pins. therefore, when bit manipulation instruction is used to write to tcrw, the values of the ftioa to ftiod pin output may result in an unexpected result. when tcrw is to be written to while compare match is opera ting, stop the counter once before accessing to tcrw, read the port 8 state to reflect the valu es of ftioa to ftiod output, to toa to tod, and then restart the counter. figure 13.26 sh ows an example when the compare match and the bit manipulation instruction to tcrw occur at the same timing. compare match signal b ftiob pin tcrw write signal set value bit tcrw 000 00110 765 43210 cclr cks2 cks1 cks0 tod toc tob toa expected output remains high because the 1 writing to tob has priority tocr has been set to h'06. compare match b and compare match c are used. the ftiob pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match b. when bclr#2, @tocr is executed to clear the toc bit (the ftioc0 signal is low) and compare match b occurs at the same timing as shown below, the h'02 writing to tocr has priority and compare match b does not drive the ftiob signal low; the ftiob signal remains high. bclr#2, @tcrw (1) tcrw read operation: read h'06 (2) modify operation: modify h'06 to h'02 (3) write operation to tocr: write h'02 figure 13.26 when compa re match and bit manipulation instruction to tcrw occur at the same timing
section 14 timer z rev. 3.00 mar. 15, 2006 page 213 of 526 rej09b0060-0300 section 14 timer z the timer z has a 16-bit timer with two channels. figures 14.1, 14.2, and 14.3 show the block diagrams of entire timer z, its channel 0, and its channel 1, respectively. for details on the timer z functions, see table 14.1. 14.1 features ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 14 timer z rev. 3.00 mar. 15, 2006 page 214 of 526 rej09b0060-0300 ? ? table 14.1 timer z functions item channel 0 channel 1 count clock internal clocks: , /2, /4, /8 external clock: ftioa0 (tclk) general registers (output compare/input capture registers) gra_0, grb_0, grc_0, grd_0 gra_1, grb_1, grc_1, grd_1 buffer register grc_0, grd_0 grc_1, grd_1 i/o pins ftioa0, ftiob0, ftioc0, ftiod0 ftioa1, ftiob1, ftioc1, ftiod1 counter clearing function com pare match/input capture of gra_0, grb_0, grc_0, or grd_0 compare match/input capture of gra_1, grb_1, grc_1, or grd_1 0 output yes yes 1 output yes yes compare match output output yes yes input capture function yes yes synchronous operation yes yes pwm mode yes yes reset synchronous pwm mode yes yes complementary pwm mode yes yes buffer function yes yes interrupt sources compare match/input capture a0 to d0 overflow compare match/input capture a1 to d1 overflow underflow
section 14 timer z rev. 3.00 mar. 15, 2006 page 215 of 526 rej09b0060-0300 itmz0 ftioa0 itmz1 adtrg channel 0 timer channel 1 timer module data bus ftiob0 ftioc0 ftiod0 ftioa1 ftiob1 ftioc1 ftiod1 tstr: [legend] tmdr: tfcr: toer: tocr: adtrg : itmz0: itmz1: timer start register (8 bits) timer mode register (8 bits) tpmr: timer pwm mode register (8 bits) timer function control register (8 bits) timer output master enable register (8 bits) timer output control register (8 bits) a/d conversion start trigger output signal channel 0 interrupt channel 1 interrupt toer tocr tpmr tfcr tstr tmdr control logic , /2, /4, /8 figure 14.1 timer z block diagram
section 14 timer z rev. 3.00 mar. 15, 2006 page 216 of 526 rej09b0060-0300 itmz0 ftiod0 ftioc0 ftiob0 ftioa0 tcnt_0 gra_0 grb_0 grc_0 grd_0 tcr_0 tiora_0 tsr_0 tiorc_0 tier_0 pocr_0 tcnt_0 : gra_0, grb_0: grc_0, grd_0 : tcr_0: tiora_0: tier_0: tsr_0: itmz0: timer counter_0 (16 bits) general registers a_0, b_0, c_0, and d_0 (input capture/output compare registers: 16 bits 4) timer control register_0 (8 bits) timer i/o control register a_0 (8 bits) tiorc_0: timer i/o control register c_0 (8 bits) timer interrupt enable register_0 (8 bits) pocr_0: pwm mode output level control register_0 (8 bits) timer status register_0 (8 bits) channel 0 interrupt [legend] , /2, /4, /8 clock select control logic module data bus comparator figure 14.2 timer z (channel 0) block diagram
section 14 timer z rev. 3.00 mar. 15, 2006 page 217 of 526 rej09b0060-0300 itmz1 ftiod1 ftioc1 ftiob1 ftioa1 tcnt_1 gra_1 grb_1 grc_1 grd_1 tcr_1 tiora_1 tsr_1 tiorc_1 tier_1 pocr_1 tcnt_1: gra_1, grb_1: grc_1, grd_1: tcr_1: tiora_1: tier_1: tsr_1: itmz1: timer counter_1 (16 bits) general registers a_1, b_1, c_1, and d_1 (input capture/output compare registers: 16 bits 4) timer control register_1 (8 bits) timer i/o control register a_1 (8 bits) tiorc_1: timer i/o control register c_1 (8 bits) timer interrupt enable register_1 (8 bits) pocr_1: pwm mode output level control register_1 (8 bits) timer status register_1 (8 bits) channel 1 interrupt [legend] , /2, /4, /8 clock select control logic module data bus comparator figure 14.3 timer z (channel 1) block diagram
section 14 timer z rev. 3.00 mar. 15, 2006 page 218 of 526 rej09b0060-0300 14.2 input/output pins table 14.2 summarizes the timer z pins. table 14.2 pin configuration name abbreviation input/output function input capture/output compare a0 ftioa0 input/output gra_0 output compare output, gra_0 input capture input, or external clock input (tclk) input capture/output compare b0 ftiob0 input/output grb_0 output compare output, grb_0 input capture input, or pwm output input capture/output compare c0 ftioc0 input/output grc_0 ou tput compare output, grc_0 input capture input, or pwm synchronous output (in reset synchronous pwm and complementary pwm modes) input capture/output compare d0 ftiod0 input/output grd_0 ou tput compare output, grd_0 input capture input, or pwm output input capture/output compare a1 ftioa1 input/output gra_1 output compare output, gra_1 input capture input, or pwm output (in reset synchronous pwm and complementary pwm modes) input capture/output compare b1 ftiob1 input/output grb_1 output compare output, grb_1 input capture input, or pwm output input capture/output compare c1 ftioc1 input/output grc_1 ou tput compare output, grc_1 input capture input, or pwm output input capture/output compare d1 ftiod1 input/output grd_1 ou tput compare output, grd_1 input capture input, or pwm output
section 14 timer z rev. 3.00 mar. 15, 2006 page 219 of 526 rej09b0060-0300 14.3 register descriptions the timer z has the following registers. common ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 14 timer z rev. 3.00 mar. 15, 2006 page 220 of 526 rej09b0060-0300 ? ? 14.3.1 timer start register (tstr) tstr selects the operation/stop for the tcnt counter. bit bit name initial value r/w description 7 to 2 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 1 str1 0 r/w channel 1 counter start 0: tcnt_1 halts counting 1: tcnt_1 starts counting 0 str0 0 r/w channel 0 counter start 0: tcnt_0 halts counting 1: tcnt_0 starts counting
section 14 timer z rev. 3.00 mar. 15, 2006 page 221 of 526 rej09b0060-0300 14.3.2 timer mode register (tmdr) tmdr selects buffer operation setti ngs and synchronized operation. bit bit name initial value r/w description 7 bfd1 0 r/w buffer operation d1 0: grd_1 operates normally 1: grb_1 and grd_1 are used together for buffer operation 6 bfc1 0 r/w buffer operation c1 0: grc_1 operates normally 1: gra_1 and grd_1 are used together for buffer operation 5 bfd0 0 r/w buffer operation d0 0: grd_0 operates normally 1: grb_0 and grd_0 are used together for buffer operation 4 bfc0 0 r/w buffer operation c0 0: grc_0 operates normally 1: gra_0 and grc_0 are used together for buffer operation 3 to 1 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 0 sync 0 r/w timer synchronization 0: tcnt_1 and tcnt_0 operat e as a different timer 1: tcnt_1 and tcnt_0 are synchronized tcnt_1 and tcnt_0 can be pre-set or cleared synchronously
section 14 timer z rev. 3.00 mar. 15, 2006 page 222 of 526 rej09b0060-0300 14.3.3 timer pwm mode register (tpmr) tpmr sets the pin to enter pwm mode. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 6 pwmd1 0 r/w pwm mode d1 0: ftiod1 operates normally 1: ftiod1 operates in pwm mode 5 pwmc1 0 r/w pwm mode c1 0: ftioc1 operates normally 1: ftioc1 operates in pwm mode 4 pwmb1 0 r/w pwm mode b1 0: ftiob1 operates normally 1: ftiob1 operates in pwm mode 3 ? 1 ? reserved this bit is always read as 1, and cannot be modified. 2 pwmd0 0 r/w pwm mode d0 0: ftiod0 operates normally 1: ftiod0 operates in pwm mode 1 pwmc0 0 r/w pwm mode c0 0: ftioc0 operates normally 1: ftioc0 operates in pwm mode 0 pwmb0 0 r/w pwm mode b0 0: ftiob0 operates normally 1: ftiob0 operates in pwm mode
section 14 timer z rev. 3.00 mar. 15, 2006 page 223 of 526 rej09b0060-0300 14.3.4 timer function control register (tfcr) tfcr selects the settings and output levels for each operating mode. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 stclk 0 r/w external clock input select 0: external clock input is disabled 1: external clock input is enabled 5 adeg 0 r/w a/d trigger edge select a/d module should be set to start an a/d conversion by the external trigger 0: a/d trigger at the crest in complementary pwm mode 1: a/d trigger at the trough in complementary pwm mode 4 adtrg 0 r/w external trigger disable 0: a/d trigger for pwm cycles is disabled in complementary pwm mode 1: a/d trigger for pwm cycles is enabled in complementary pwm mode 3 ols1 0 r/w output level select 1 selects the counter-phase output levels in reset synchronous pwm mode or complementary pwm mode. 0: initial output is high and the active level is low. 1: initial output is low and the active level is high. 2 ols0 0 r/w output level select 0 selects the normal-phase output levels in reset synchronous pwm mode or complementary pwm mode. 0: initial output is high and the active level is low. 1: initial output is low and the active level is high. figure 14.4 shows an example of outputs in reset synchronous pwm mode and complementary pwm mode when ols1 = 0 and ols0 = 0.
section 14 timer z rev. 3.00 mar. 15, 2006 page 224 of 526 rej09b0060-0300 bit bit name initial value r/w description 1 0 cmd1 cmd0 0 0 r/w r/w combination mode 1 and 0 00: channel 0 and channel 1 operate normally 01: channel 0 and channel 1 are used together to operate in reset synchronous pwm mode 10: channel 0 and channel 1 are used together to operate in complementary pwm mode (transferred at the trough) 11: channel 0 and channel 1 are used together to operate in complementary pwm mode (transferred at the crest) note: when reset synchronous pwm mode or complementary pwm mode is selected by these bits, this setting has the priority to the settings for pwm mode by each bit in tpmr. stop tcnt_0 and tcnt_1 before making settings for reset synchronous pwm mode or complementary pwm mode. tcnt_0 normal phase counter phase normal phase counter phase active level active level active level active level complementary pwm mode note: write h'00 to tocr to start initial outputs after stopping the counter. reset synchronous pwm mode initial output initial output tcnt_1 figure 14.4 example of outputs in reset synchronous pwm mode and complementary pwm mode
section 14 timer z rev. 3.00 mar. 15, 2006 page 225 of 526 rej09b0060-0300 14.3.5 timer output master enable register (toer) toer enables/disables the outputs for channel 0 and channel 1. when wkp4 is selected for inputs, if a low level signal is input to wkp4 , the bits in toer are set to 1 to disable the output for timer z. bit bit name initial value r/w description 7 ed1 1 r/w master enable d1 0: ftiod1 pin output is enabled according to the tpmr, tfcr, and tiorc_1 settings 1: ftiod1 pin output is disabled regardless of the tpmr, tfcr, and tiorc_1 settings (ftiod1 pin is operated as an i/o port). 6 ec1 1 r/w master enable c1 0: ftioc1 pin output is enabled according to the tpmr, tfcr, and tiorc_1 settings 1: ftioc1 pin output is disabled regardless of the tpmr, tfcr, and tiorc_1 settings (ftioc1 pin is operated as an i/o port). 5 eb1 1 r/w master enable b1 0: ftiob1 pin output is enabled according to the tpmr, tfcr, and tiora_1 settings 1: ftiob1 pin output is disabled regardless of the tpmr, tfcr, and tiora_1 settings (ftiob1 pin is operated as an i/o port). 4 ea1 1 r/w master enable a1 0: ftioa1 pin output is enabled according to the tpmr, tfcr, and tiora_1 settings 1: ftioa1 pin output is disabled regardless of the tpmr, tfcr, and tiora_1 settings (ftioa1 pin is operated as an i/o port). 3 ed0 1 r/w master enable d0 0: ftiod0 pin output is enabled according to the tpmr, tfcr, and tiorc_0 settings 1: ftiod0 pin output is disabled regardless of the tpmr, tfcr, and tiorc_0 settings (ftiod0 pin is operated as an i/o port).
section 14 timer z rev. 3.00 mar. 15, 2006 page 226 of 526 rej09b0060-0300 bit bit name initial value r/w description 2 ec0 1 r/w master enable c0 0: ftioc0 pin output is enabled according to the tpmr, tfcr, and tiorc_0 settings 1: ftioc0 pin output is disabled regardless of the tpmr, tfcr, and tiorc_0 settings (ftioc0 pin is operated as an i/o port). 1 eb0 1 r/w master enable b0 0: ftiob0 pin output is enabled according to the tpmr, tfcr, and tiora_0 settings 1: ftiob0 pin output is disabled regardless of the tpmr, tfcr, and tiora_0 settings (ftiob0 pin is operated as an i/o port). 0 ea0 1 r/w master enable a0 0: ftioa0 pin output is enabled according to the tpmr, tfcr, and tiora_0 settings 1: ftioa0 pin output is disabled regardless of the tpmr, tfcr, and tiora_0 settings (ftioa0 pin is operated as an i/o port).
section 14 timer z rev. 3.00 mar. 15, 2006 page 227 of 526 rej09b0060-0300 14.3.6 timer output co ntrol register (tocr) tocr selects the initial outputs before the first oc currence of a compare ma tch. note that bits ols1 and ols0 in tfcr set these initial outputs in reset synchronous pwm mode and complementary pwm mode. bit bit name initial value r/w description 7 tod1 0 r/w output level select d1 0: 0 output at the ftiod1 pin * 1: 1 output at the ftiod1 pin * 6 toc1 0 r/w output level select c1 0: 0 output at the ftioc1 pin * 1: 1 output at the ftioc1 pin * 5 tob1 0 r/w output level select b1 0: 0 output at the ftiob1 pin * 1: 1 output at the ftiob1 pin * 4 toa1 0 r/w output level select a1 0: 0 output at the ftioa1 pin * 1: 1 output at the ftioa1 pin * 3 tod0 0 r/w output level select d0 0: 0 output at the ftiod0 pin * 1: 1 output at the ftiod0 pin * 2 toc0 0 r/w output level select c0 0: 0 output at the ftioc0 pin * 1: 1 output at the ftioc0 pin * 1 tob0 0 r/w output level select b0 0: 0 output at the ftiob0 pin * 1: 1 output at the ftiob0 pin * 0 toa0 0 r/w output level select a0 0: 0 output at the ftioa0 pin * 1: 1 output at the ftioa0 pin * note: * the change of the setting is immediatel y reflected in the output value.
section 14 timer z rev. 3.00 mar. 15, 2006 page 228 of 526 rej09b0060-0300 14.3.7 timer counter (tcnt) the timer z has two tcnt counters (tcnt_0 and tcnt_1), one for each channel. the tcnt counters are 16-bit readable/writable registers that increment/decrement according to input clocks. input clocks can be selected by bits tpsc2 to tpsc0 in tcr. tcnt0 and tcnt 1 increment/decrement in complementary pwm mode, while they only increm ent in other modes. the tcnt counters are initialized to h'0000 by compare matches with corresponding gra, grb, grc, or grd, or input captures to gra, grb, grc, or grd (counter clearing function). when the tcnt counters overflow, an ov f flag in tsr for the corresponding channel is set to 1. when tcnt_1 underflows, an udf flag in tsr is set to 1. the tcnt counters cannot be accessed in 8- bit units; they must always be accessed as a 16 -bit unit. tcnt is in itialized to h'0000. 14.3.8 general registers a, b, c, and d (gra, grb, grc, and grd) gr are 16-bit registers. timer z has eight genera l registers (gr), four for each channel. the gr registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. functions can be switched by tiora and tiorc. the values in gr and tcnt are constantly compared with each ot her when the gr registers are used as output compare register s. when the both values match, the imfa to imfd flags in tsr are set to 1. compare match outputs ca n be selected by tiora and tiorc. when the gr registers are used as input capture re gisters, the tcnt value is stored after detecting external signals. at this point, imfa to imfd flags in the correspond ing tsr are set to 1. detection edges for input capture signals can be selected by tiora and tiorc. when pwm mode, complementary pwm mode, or reset synchronous pwm mode is selected, the values in tiora and tiorc are ignored. upon rese t, the gr registers are set as output compare registers (no output) and initialized to h'ffff. the gr registers ca nnot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
section 14 timer z rev. 3.00 mar. 15, 2006 page 229 of 526 rej09b0060-0300 14.3.9 timer control register (tcr) the tcr registers select a tcnt counter clock, an edge when an external clock is selected, and counter clearing sources. timer z has a total of two tcr registers, one for each channel. bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 2 to 0 000: disables tcnt clearing 001: clears tcnt by gra compare match/input capture * 1 010: clears tcnt by grb compare match/input capture * 1 011: synchronization clear; clears tcnt in synchronous with counter clearing of the other channel's timer * 2 100: disables tcnt clearing 101: clears tcnt by grc compare match/input capture * 1 110: clears tcnt by grd compare match/input capture * 1 111: synchronization clear; clears tcnt in synchronous with counter clearing of the other channel's timer * 2 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 1 and 0 00: count at rising edge 01: count at falling edge 1x: count at both edges 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 2 to 0 000: internal clock: count by 001: internal clock: count by /2 010: internal clock: count by /4 011: internal clock: count by /8 1xx: external clock: count by ftioa0 (tclk) pin input notes: 1. when gr functions as an output compar e register, tcnt is cleared by compare match. when gr functions as input capture, tcnt is cleared by input capture. 2. synchronous operation is set by tmdr. 3. x: don't care
section 14 timer z rev. 3.00 mar. 15, 2006 page 230 of 526 rej09b0060-0300 14.3.10 timer i/o control register (tiora and tiorc) the tior registers control the general registers (gr). timer z has four tior registers (tiora_0, tiora_1, tiorc_0, and tiorc_1), two for each cha nnel. in pwm mode including complementary pwm mode and reset synchronous pwm mode, the settings of tior are invalid. tiora: tiora selects whether gra or grb is used as an output compare re gister or an input capture register. when an output compare register is selected, the output setting is selected. when an input capture register is selected, an input e dge of an input capture signal is selected. tiora also selects the function of ftioa or ftiob pin. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 iob2 iob1 iob0 0 0 0 r/w r/w r/w i/o control b2 to b0 grb is an output compare register: 000: disables pin output by compare match 001: 0 output by grb compare match 010: 1 output by grb compare match 011: toggle output by grb compare match grb is an input capture register: 100: input capture to grb at the rising edge 101: input capture to grb at the falling edge 11x: input capture to grb at both rising and falling edges 3 ? 1 ? reserved this bit is always read as 1. 2 1 0 ioa2 ioa1 ioa0 0 0 0 r/w r/w r/w i/o control a2 to a0 gra is an output compare register: 000: disables pin output by compare match 001: 0 output by gra compare match 010: 1 output by gra compare match 011: toggle output by gra compare match gra is an input capture register: 100: input capture to gra at the rising edge 101: input capture to gra at the falling edge 11x: input capture to gra at both rising and falling edges [legend] x: don't care
section 14 timer z rev. 3.00 mar. 15, 2006 page 231 of 526 rej09b0060-0300 tiorc: tiorc selects whether grc or grd is used as an output compare register or an input capture register. when an output compare register is selected, the output setting is selected. when an input capture register is selected, an input e dge of an input capture signal is selected. tiorc also selects the function of ftioc or ftiod pin. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 iod2 iod1 iod0 0 0 0 r/w r/w r/w i/o control d2 to d0 grd is an output compare register: 000: disables pin output by compare match 001: 0 output by grd compare match 010: 1 output by grd compare match 011: toggle output by grd compare match grd is an input capture register: 100: input capture to g rd at the rising edge 101: input capture to grd at the falling edge 11x: input capture to grd at both rising and falling edges 3 ? 1 ? reserved this bit is always read as 1. 2 1 0 ioc2 ioc1 ioc0 0 0 0 r/w r/w r/w i/o control c2 to c0 grc is an output compare register: 000: disables pin output by compare match 001: 0 output by grc compare match 010: 1 output by grc compare match 011: toggle output by grc compare match grc is an input capture register: 100: input capture to g rc at the rising edge 101: input capture to grc at the falling edge 11x: input capture to grc at both rising and falling edges [legend] x: don't care
section 14 timer z rev. 3.00 mar. 15, 2006 page 232 of 526 rej09b0060-0300 14.3.11 timer status register (tsr) tsr indicates generation of an overflow/underflow of tcnt and a compare match/input capture of gra, grb, grc, and grd. these flags are interrupt sources. if an interrupt is enabled by a corresponding bit in tier, tsr requests an interr upt for the cpu. timer z has two tsr registers, one for each channel. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. 5 udf * 0 r/w underflow flag [setting condition] ? when tcnt_1 underflows [clearing condition] ? when 0 is written to udf after reading udf = 1 4 ovf 0 r/w overflow flag [setting condition] ? when the tcnt value underflows [clearing condition] ? when 0 is written to ovf after reading ovf = 1 3 imfd 0 r/w input capt ure/compare match flag d [setting conditions] ? when tcnt = grd and grd is functioning as output compare register ? when tcnt value is transf erred to grd by input capture signal and grd is functioning as input capture register [clearing condition] ? when 0 is written to imfd after reading imfd = 1
section 14 timer z rev. 3.00 mar. 15, 2006 page 233 of 526 rej09b0060-0300 bit bit name initial value r/w description 2 imfc 0 r/w input capt ure/compare match flag c [setting conditions] ? when tcnt = grc and grc is functioning as output compare register ? when tcnt value is transf erred to grc by input capture signal and grc is functioning as input capture register [clearing condition] ? when 0 is written to imfc after reading imfc = 1 1 imfb 0 r/w input capt ure/compare match flag b [setting conditions] ? when tcnt = grb and grb is functioning as output compare register ? when tcnt value is transferred to grb by input capture signal and grb is functioning as input capture register [clearing condition] ? when 0 is written to imfb after reading imfb = 1 0 imfa 0 r/w input capt ure/compare match flag a [setting conditions] ? when tcnt = gra and gra is functioning as output compare register ? when tcnt value is transferred to gra by input capture signal and gra is functioning as input capture register [clearing condition] ? when 0 is written to imfa after reading imfa = 1 note: bit 5 is not the udf flag in tsr_0. it is a reserved bit. it is always read as 1.
section 14 timer z rev. 3.00 mar. 15, 2006 page 234 of 526 rej09b0060-0300 14.3.12 timer interrupt enable register (tier) tier enables or disables interrupt requests for overflow or gr compare match/input capture. timer z has two tier registers, one for each channel. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 ovie 0 r/w overflow interrupt enable 0: interrupt requests (ovi) by ovf or udf flag are disabled 1: interrupt requests (ovi) by ovf or udf flag are enabled 3 imied 0 r/w input capture/com pare match interrupt enable d 0: interrupt requests (imid) by imfd flag are disabled 1: interrupt requests (imid) by imfd flag are enabled 2 imiec 0 r/w input capture/com pare match interrupt enable c 0: interrupt requests (imic) by imfc flag are disabled 1: interrupt requests (imic) by imfc flag are enabled 1 imieb 0 r/w input capture/com pare match interrupt enable b 0: interrupt requests (imib) by imfb flag are disabled 1: interrupt requests (imib) by imfb flag are enabled 0 imiea 0 r/w input capture/com pare match interrupt enable a 0: interrupt requests (imia) by imfa flag are disabled 1: interrupt requests (imia) by imfa flag are enabled
section 14 timer z rev. 3.00 mar. 15, 2006 page 235 of 526 rej09b0060-0300 14.3.13 pwm mode output level control register (pocr) pocr control the active level in pwm mode. ti mer z has two pocr registers, one for each channel. bit bit name initial value r/w description 7 to 3 ? all 1 ? reserved these bits are always read as 1. 2 pold 0 r/w pwm mode output level control d 0: the output level of ftiod is low-active 1: the output level of ftiod is high-active 1 polc 0 r/w pwm mode output level control c 0: the output level of ftioc is low-active 1: the output level of ftioc is high-active 0 polb 0 r/w pwm mode output level control b 0: the output level of ftiob is low-active 1: the output level of ftiob is high-active
section 14 timer z rev. 3.00 mar. 15, 2006 page 236 of 526 rej09b0060-0300 14.3.14 interface with cpu 1. 16-bit register tcnt and gr are 16-bit registers. reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the cpu is 16-bit width. these registers must always be accessed in a 16-bit unit. figure 14.5 shows an example of accessing th e 16-bit registers. h internal data bus bus interface module data bus c p u l tcntl tcnth figure 14.5 accessing opera tion of 16-bit register (between cpu and tcnt (16 bits)) 2. 8-bit register registers other than tcnt and gr are 8-bit regi sters that are connected internally with the cpu in an 8-bit width. figure 14.6 shows an example of accessing the 8-bit registers. tstr h internal data bus bus interface module data bus c p u l figure 14.6 accessing opera tion of 8-bit register (between cpu and tstr (8 bits))
section 14 timer z rev. 3.00 mar. 15, 2006 page 237 of 526 rej09b0060-0300 14.4 operation 14.4.1 counter operation when one of bits str0 and str1 in tstr is set to 1, the tcnt counter for the corresponding channel begins counting. tcnt can operate as a free-running counter, periodic counter, for example. figure 14.7 shows an example of the counter operation setting procedure. [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [2] for periodic counter operation, select the tcnt clearing source with bits cclr2 to cclr0 in tcr. [3] designate the general register selected in [2] as an output compare register by means of tior. [4] set the periodic counter cycle in the general register selected in [2]. [5] set the str bit in tstr to 1 to start the counter operation. operation selection periodic counter free-running counter [1] select counter clock [2] select counter clearing source [3] select output compare register [5] start count operation [4] set period figure 14.7 example of coun ter operation setting procedure
section 14 timer z rev. 3.00 mar. 15, 2006 page 238 of 526 rej09b0060-0300 1. free-running count operation and periodic count operation immediately after a reset, the tcnt counters for channels 0 and 1 are all designated as free- running counters. when the relevant bit in tstr is set to 1, the corresponding tcnt counter starts an increment operation as a free-running counter. when tcnt overflows, the ovf flag in tsr is set to 1. if the value of the ovie bit in the corresponding tier is 1 at this point, timer z requests an interrupt. after overflow, tcnt starts an increment operation again from h'0000. figure 14.8 illustrates free-running counter operation. h'ffff tcnt value time h'0000 str0, str1 ovf figure 14.8 free-running counter operation when compare match is selected as the tcnt cl earing source, the tcnt co unter for the relevant channel performs periodic count operation. the gr registers for setting the period are designated as output compare registers, and counter clearing by compare match is sel ected by means of bits cclr1 and cclr0 in tcr. after the settings ha ve been made, tcnt starts an increment operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in gr, the imfa, imfb, imfc, or imfd flag in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding imiea, imieb, imiec, or imied bit in tier is 1 at this point, the timer z requests an interrupt. after a comp are match, tcnt starts an increment operation again from h'0000.
section 14 timer z rev. 3.00 mar. 15, 2006 page 239 of 526 rej09b0060-0300 figure 14.9 illustrates periodic counter operation. h'0000 time counter cleared by gr compare match str gr value tcnt value imf figure 14.9 periodic counter operation 2. tcnt count timing a. internal clock operation a system clock ( tcnt tcnt input internal clock n-1 n n+1 figure 14.10 count timing at internal clock operation
section 14 timer z rev. 3.00 mar. 15, 2006 page 240 of 526 rej09b0060-0300 b. external clock operation an external clock input pin (tclk) can be se lected by bits tpsc2 to tpsc0 in tcr, and a detection edge can be selected by bits ckeg 1 and ckeg0. to detect an external clock, the rising edge, falling edge, or both edges can be selected. the pulse width of the external clock needs two or more system clocks. note that an external clock does not operate correctly with the lower pulse width. figure 14.11 illustrates the detection timing of the rising and falling edges. tcnt external clock input pin tcnt input n-1 n n+1 figure 14.11 count timing at external clock operation (both edges detected)
section 14 timer z rev. 3.00 mar. 15, 2006 page 241 of 526 rej09b0060-0300 14.4.2 waveform output by compare match timer z can perform 0, 1, or toggle output from the corresponding ftioa, ftiob, ftioc, or ftiod output pin using compare match a, b, c, or d. figure 14.12 shows an example of the setting procedure for waveform output by compare match. [1] select 0 output, 1 output, or toggle output as a compare much output, by means of tior. the initial values set in tocr are output unit the first compare match occurs. [2] set the timing for compare match generation in gra/grb/grc/grd. [3] enable or disable the timer output by toer. [4] set the str bit in tstr to 1 to start the tcnt count operation. [1] output selection select waveform output mode [2] set output timing [3] enable waveform output [4] start count operation figure 14.12 example of setting procedu re for waveform output by compare match
section 14 timer z rev. 3.00 mar. 15, 2006 page 242 of 526 rej09b0060-0300 1. examples of waveform output operation figure 14.13 shows an example of 0 output/1 output. in this example, tcnt has been designated as a free-running counter, and settings have been made such that 0 is output by compare match a, and 1 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. h'ffff h'0000 ftiob time no change no change no change no change tcnt value ftioa figure 14.13 example of 0 output/1 output operation figure 14.14 shows an example of toggle output. in this example, tcnt has b een designated as a periodic co unter (with counter clearing on compare match b), and settings have been made such that the output is toggled by both compare match a and compare match b.
section 14 timer z rev. 3.00 mar. 15, 2006 page 243 of 526 rej09b0060-0300 grb gra h'0000 ftiob toggle output toggle output time tcnt value ftioa figure 14.14 example of toggle output operation 2. output compare timing the compare match signal is generated in the last state in which tcnt and gr match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the compare match output pin (ftioa, ftiob, ftioc, or ftiod). when tcnt matches gr, the compare match signal is generated only after the next tcnt input clock pulse is input. figure 14.15 shows an example of the output compare timing. tcnt ftioa to ftiod compare match signal tcnt input gr n n n+1 figure 14.15 out put compare timing
section 14 timer z rev. 3.00 mar. 15, 2006 page 244 of 526 rej09b0060-0300 14.4.3 input ca pture function the tcnt value can be transferred to gr on detection of the input edge of the input capture/output compare pin (ftioa, ftiob, ftioc, or ftiod). rising edge, falling edge, or both edges can be selected as the detected edge. when the input capture fu nction is used, the pulse width or period can be measured. figure 14.16 shows an example of the i nput capture operati on setting procedure. [1] designate gr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input edge of the input capture signal. [2] set the str bit in tstr to 1 to start the tcnt counter operation. [1] input selection select input edge of input capture [2] start counter operation figure 14.16 example of input ca pture operation setting procedure
section 14 timer z rev. 3.00 mar. 15, 2006 page 245 of 526 rej09b0060-0300 1. example of input capture operation figure 14.17 shows an example of input capture operation. in this example, both rising and falling edge s have been selected as the ftioa pin input capture input edge, the falling edge has been se lected as the ftiob pin input capture input edge, and counter clearing by grb input capture has been designated for tcnt. ftioa tcnt value counter cleared by ftiob input (falling edge) time ftiob gra h'0005 h'0005 h'0000 h'0160 h'0160 grb h'0180 h'0180 figure 14.17 example of input capture operation
section 14 timer z rev. 3.00 mar. 15, 2006 page 246 of 526 rej09b0060-0300 2. input capture signal timing input capture on the rising edge, falling edge, or both edges can be selected through settings in tior. figure 14.18 shows the timing when the risi ng edge is selected. the pulse width of the input capture signal must be at least two system clock ( tcnt input capture signal input capture input gr n n figure 14.18 input capture signal timing
section 14 timer z rev. 3.00 mar. 15, 2006 page 247 of 526 rej09b0060-0300 14.4.4 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables gr to be increased w ith respect to a single time base. figure 14.19 shows an example of the synchronous operation setting procedure. no yes synchronous operation selection clearing source generation channel? set synchronous operation select counter clearing source synchronous presetting set tcnt synchronous clearing [1] [2] [3] select counter clearing source [4] start counter operation [5] start counter operation [5] [1] set the sync bits in tmdr to 1. [2] when a value is written to either of the tcnt counters, the same value is simultaneously written to the other tcnt counter. [3] set bits cclr1 and cclr0 in tcr to specify counter clearing by compare match/input capture. [4] set bits cclr1 and cclr0 in tcr to designate synchronous clearing for the counter clearing source. [5] set the str bit in tstr to 1 to start the count operation. figure 14.19 example of synchronous operation setting procedure
section 14 timer z rev. 3.00 mar. 15, 2006 page 248 of 526 rej09b0060-0300 figure 14.20 shows an example of synchronous operation. in this example, synchronous operation has been selected, ftiob0 and ftiob1 have been designated for pwm mode, gra_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. in addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. two-phase pwm waveforms are output from pins ftiob0 and ftiob1. at this time, synchronous presetting and synchronous operation by gra_0 compare match are performed by tcnt counters. for details on pwm mode, see section 14.4.5, pwm mode. gra_0 time synchronous clearing by gra_0 compare match tcnt values gra_1 grb_0 grb_1 h'0000 ftiob0 ftiob1 figure 14.20 example of synchronous operation 14.4.5 pwm mode in pwm mode, pwm waveforms are output from the ftiob, ftioc, and ftiod output pins with gra as a cycle register and grb, grc, and grd as duty registers. the initial output level of the corresponding pin depends on the setting values of tocr and pocr. table 14.3 shows an example of the initial output level of the ftiob0 pin. the output level is determined by the polb to pold bits corresponding to pocr. when polb is 0, the ftiob output pin is set to 0 by compare match b and set to 1 by compare match a. when polb is 1, the ftiob output pin is set to 1 by compare match b and cleared to 0 by compare match a. in pwm mode, maximum 6-phase pwm outputs are possible.
section 14 timer z rev. 3.00 mar. 15, 2006 page 249 of 526 rej09b0060-0300 figure 14.21 shows an example of the pwm mode setting procedure. table 14.3 initial output level of ftiob0 pin tob0 polb initial output level 0 0 1 0 1 0 1 0 0 1 1 1 [1] select the counter clock with bits tpsc2 to tosc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [2] use bits cclr1 and cclr0 in tcr to select the counter clearing source. [3] select the pwm mode with bits pwmb0 to pwmd0 and pwmb1 to pwmd1 in tpmr. [4] set the initial output value with bits tob0 to tod0 and tob1 to tod1 in tocr. [5] set the output level with bits polb to pold in pocr. [6] set the cycle in gra, and set the duty in the other gr. [7] enable or disable the timer output by toer. [8] set the str bit in tstr to 1 and start the counter operation. [1] [2] [3] [4] [5] [6] [7] pwm mode select counter clock select counter clearing source set pwm mode set initial output level select output level set gr enable waveform output [8] start counter operation figure 14.21 example of pwm mode setting procedure
section 14 timer z rev. 3.00 mar. 15, 2006 page 250 of 526 rej09b0060-0300 figure 14.22 shows an example of operation in pwm mode. the output signals go to 1 and tcnt is reset at compare match a, and the output signals go to 0 at compare match b, c, and d (tob, toc, and tod = 0, polb, polc, and pold = 0). gra tcnt value time counter cleared by gra compare match grb grc grd h'0000 ftioc ftiod ftiob figure 14.22 example of pwm mode operation (1)
section 14 timer z rev. 3.00 mar. 15, 2006 page 251 of 526 rej09b0060-0300 figure 14.23 shows another example of operation in pwm mode. the output signals go to 0 and tcnt is reset at compare match a, and the output signals go to 1 at compare match b, c, and d (tob, toc, and tod = 0, polb, polc, and pold = 1). gra grb grc grd h'0000 ftioc ftiod ftiob counter cleared by gra compare match time tcnt value figure 14.23 example of pwm mode operation (2) figures 14.24 (when tob, toc, and tod = 0, polb, polc, and pold = 0) and 14.25 (when tob, toc, and tod = 0, polb, polc, and pold = 1) show examples of the output of pwm waveforms with duty cycles of 0% and 100% in pwm mode.
section 14 timer z rev. 3.00 mar. 15, 2006 page 252 of 526 rej09b0060-0300 gra tcnt value 0% duty 0% duty time time time grb rewritten tcnt value grb rewritten grb rewritten grb rewritten tcnt value grb rewritten grb rewritten grb rewritten when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. grb rewritten 100% duty 100% duty grb h'0000 ftiob gra grb h'0000 ftiob gra grb h'0000 ftiob figure 14.24 example of pwm mode operation (3)
section 14 timer z rev. 3.00 mar. 15, 2006 page 253 of 526 rej09b0060-0300 gra grb h'0000 ftiob gra grb h'0000 ftiob gra grb h'0000 ftiob tcnt value 0% duty time grb rewritten grb rewritten time tcnt value grb rewritten grb rewritten grb rewritten 100% duty 0% duty time tcnt value grb rewritten grb rewritten grb rewritten 100% duty when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. when cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. figure 14.25 example of pwm mode operation (4)
section 14 timer z rev. 3.00 mar. 15, 2006 page 254 of 526 rej09b0060-0300 14.4.6 reset synchronous pwm mode three normal- and counter-phase pwm waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. in reset synchronous pwm mode, the ftiob0 to ftiod0 and ftioa1 to ftiod1 pins become pwm-output pins automatically. tcnt_0 performs an increment operation. tables 14.4 and 14.5 show the pwm-output pins used and the register settings, respectively. figure 14.26 shows the example of reset synchronous pwm mode setting procedure. table 14.4 output pins in reset synchronous pwm mode channel pin name input/output pin function 0 ftioc0 output toggle output in synchronous with pwm cycle 0 ftiob0 output pwm output 1 0 ftiod0 output pwm output 1 (counter-phase waveform of pwm output 1) 1 ftioa1 output pwm output 2 1 ftioc1 output pwm output 2 (counter-phase waveform of pwm output 2) 1 ftiob1 output pwm output 3 1 ftiod1 output pwm output 3 (counter-phase waveform of pwm output 3) table 14.5 register settings in reset synchronous pwm mode register description tcnt_0 initial setting of h'0000 tcnt_1 not used (independently operates) gra_0 sets counter cycle of tcnt_0 grb_0 set a changing point of the pwm wa veform output from pins ftiob0 and ftiod0. gra_1 set a changing point of the pwm wa veform output from pins ftioa1 and ftioc1. grb_1 set a changing point of the pwm wa veform output from pins ftiob1 and ftiod1.
section 14 timer z rev. 3.00 mar. 15, 2006 page 255 of 526 rej09b0060-0300 [1] clear bit str0 in tstr to 0 and stop the counter operation of tcnt_0. set reset synchronous pwm mode after tcnt_0 stops. [2] select the counter clock with bits tpsc2 to tosc0 in tcr. when an external clock is selected, select the external clock edge with bits ckeg1 and ckeg0 in tcr. [3] use bits cclr1 and cclr0 in tcr to select counter clearing source gra_0. [4] select the reset synchronous pwm mode with bits cmd1 and cmd0 in tfcr. ftiob0 to ftiod0 and ftioa1 to ftiod1 become pwm output pins automatically. [5] set h'00 to tocr. [6] set tcnt_0 as h'0000. tcnt1 does not need to be set. [7] gra_0 is a cycle register. set a cycle for gra_0. set the changing point timing of the pwm output waveform for grb_0, gra_1, and grb_1. [8] enable or disable the timer output by toer. [9] set the str bit in tstr to 1 and start the counter operation. [1] reset synchronous pwm mode [2] stop counter operation [3] select counter clock [4] select counter clearing source [5] set reset synchronous pwm mode [6] initialize the output pin [7] set tcnt [8] set gr [9] start counter operation enable waveform output figure 14.26 example of reset sync hronous pwm mode setting procedure
section 14 timer z rev. 3.00 mar. 15, 2006 page 256 of 526 rej09b0060-0300 figures 14.27 and 14.28 show examples of operation in reset synchronous pwm mode. gra_0 tcnt value counter cleared by gra compare match time grb_0 gra_1 grb_1 h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 figure 14.27 example of reset synchronous pwm mode operation (ols0 = ols1 = 1)
section 14 timer z rev. 3.00 mar. 15, 2006 page 257 of 526 rej09b0060-0300 gra_0 grb_0 gra_1 grb_1 h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 tcnt value counter cleared by gra compare match time figure 14.28 example of reset synchronous pwm mode operation (ols0 = ols1 = 0) in reset synchronous pwm mode, tcnt_0 and tcnt_1 perform increment and independent operations, respectively. however, gra_1 and grb_1 are separated from tcnt_1. when a compare match occurs between tcnt_0 and gra_ 0, a counter is cleared and an increment operation is restarted from h'0000. the pwm pin outputs 0 or 1 whenever a compare match between grb_0, gra_1, grb_1 and tcnt_0 or counter clearing occur. for details on operations when reset synchronous pwm mode and buffer operation are simultaneously set, see section 14.4.8, buffer operation.
section 14 timer z rev. 3.00 mar. 15, 2006 page 258 of 526 rej09b0060-0300 14.4.7 complementary pwm mode three pwm waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. in complementary pwm mode, the ftiob0 to ftiod0 and ftioa1 to ftiod1 pins become pwm-output pins automatically. tcnt_0 and tcnt_1 perform an increment or decrement operation. tables 14.6 and 14.7 show the output pins and register settings in complementary pwm mode, respectively. figure 14.29 shows the example of complementary pwm mode setting procedure. table 14.6 output pins in complementary pwm mode channel pin name input/output pin function 0 ftioc0 output toggle output in synchronous with pwm cycle 0 ftiob0 output pwm output 1 0 ftiod0 output pwm output 1 (counter-phase waveform non- overlapped with pwm output 1) 1 ftioa1 output pwm output 2 1 ftioc1 output pwm output 2 (counter-phase waveform non- overlapped with pwm output 2) 1 ftiob1 output pwm output 3 1 ftiod1 output pwm output 3 (counter-phase waveform non- overlapped with pwm output 3) table 14.7 register settings in complementary pwm mode register description tcnt_0 initial setting of non-overlapped periods (non-overlapped periods are differences with tcnt_1) tcnt_1 initial setting of h'0000 gra_0 sets (upper limit value ? 1) of tcnt_0 grb_0 set a changing point of the pwm wa veform output from pins ftiob0 and ftiod0. gra_1 set a changing point of the pwm wa veform output from pins ftioa1 and ftioc1. grb_1 set a changing point of the pwm wa veform output from pins ftiob1 and ftiod1.
section 14 timer z rev. 3.00 mar. 15, 2006 page 259 of 526 rej09b0060-0300 [1] clear bits str0 and str1 in tstr to 0, and stop the counter operation of tcnt_0. stop tcnt_0 and tcnt_1 and set complementary pwm mode. [2] write h'00 to tocr. [3] use bits tpsc2 to tpsc0 in tcr to select the same counter clock for channels 0 and 1. when an external clock is selected, select the edge of the external clock by bits ckeg1 and ckeg0 in tcr. do not use bits cclr1 and cclr0 in tcr to clear the counter. [4] use bits cmd1 and cmd0 in tfcr to set complementary pwm mode. ftiob0 to ftiod0 and ftioa1 to ftiod1 automatically become pwm output pins. [5] set h'00 to tocr. [6] tcnt_1 must be h'0000. set a non-overlapped period to tcnt_0. [7] gra_0 is a cycle register. set the cycle to gra_0. set the timing to change the pwm output waveform to grb_0, gra_1, and grb_1. note that the timing must be set within the range of compare match carried out for tcnt_0 and tcnt_1. for gr settings, see 3. setting gr value in complementary pwm mode in section 14.4.7, complementary pwm mode. [8] use toer to enable or disable the timer output. [9] set the str0 and str1 bits in tstr to 1 to start the count operation. [1] complementary pwm mode stop counter operation note: to re-enter complementary pwm mode, first, enter a mode other than the complementary pwm mode. after that, repeat the setting procedures from step [1]. for settings of waveform outputs with a duty cycle of 0% and 100%, see the settings shown in 2. examples of complementary pwm mode operation and 3. setting gr value in complementary pwm mode in section 14.4.7, complementary pwm mode. [2] initialize output pin [3] select counter clock [4] set complementary pwm mode [5] initialize output pin [6] set tcnt [7] set gr [8] enable waveform output [9] start counter operation figure 14.29 example of complementary pwm mode setting procedure
section 14 timer z rev. 3.00 mar. 15, 2006 page 260 of 526 rej09b0060-0300 1. canceling procedure of complementary pwm mode: figure 14.30 shows the complementary pwm mode canceling procedure. [1] clear bit cmd1 in tfcr to 0, and set channels 0 and 1 to normal operation. [2] after setting channels 0 and 1 to normal operation, clear bits str0 and str1 in tstr to 0 and stop tcnt0 and tcnt1. [1] [2] complementary pwm mode stop counter operation cancel complementary pwm mode figure 14.30 canceling procedure of complementary pwm mode
section 14 timer z rev. 3.00 mar. 15, 2006 page 261 of 526 rej09b0060-0300 2. examples of complementary pwm mode operation: figure 14.31 shows an example of complementary pwm mode operation. in complementary pwm mode, tcnt_0 and tcnt_1 perform an increment or decr ement operation. when tcnt_0 and gra_0 are compared and their contents match, the counter is decremented, and when tcnt_1 underflows, the counter is incremented. in gra_0, gra_1, and grb_1, compare match is carried out in the order of tcnt_0 gra_0 grb_0 gra_1 grb_1 tcnt values tcnt_0 and gra_0 are compared and their contents match time h'0000 ftioa1 ftiob1 ftiob0 ftioc1 ftiod1 ftioc0 ftiod0 figure 14.31 example of complementary pwm mode operation (1)
section 14 timer z rev. 3.00 mar. 15, 2006 page 262 of 526 rej09b0060-0300 figure 14.32 (1) and (2) show examples of pwm waveform output with 0% duty and 100% duty in complementary pwm mode (for one phase). ? tpsc2 = tpsc1 = tpsc0 = 0 set grb_0 to h'0000 or a value equal to or more than gra_0. the waveform with a duty cycle of 0% and 100% can be output. when buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. for details on buffer operation, see section 14.4.8, buffer operation. ? other than tpsc2 = tpsc1 = tpsc0 = 0 set grb_0 to satisfy the following expression: gra_0 + 1 < grb_0 < h'ffff. the waveform with a duty cycle of 0% and 100% can be output. for details on 0%- and 100%-duty cycle waveform output, see 3. c., outputting a wa veform with a duty cycle of 0% and 100% in section 14.4.7, complementary pwm mode.
section 14 timer z rev. 3.00 mar. 15, 2006 page 263 of 526 rej09b0060-0300 gra0 h'0000 ftiob0 ftiod0 gra0 (b) when duty is 100% 100% duty tcnt values tcnt values time time 0% duty (a) when duty is 0% grb0 h'0000 ftiob0 ftiod0 grb0 figure 14.32 (1) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 = 0) (2)
section 14 timer z rev. 3.00 mar. 15, 2006 page 264 of 526 rej09b0060-0300 gra0 h'0000 ftiob0 ftiod0 gra0 (b) when duty is 100% 100% duty tcnt values tcnt values time time 0% duty (a) when duty is 0% grb0 h'0000 ftiob0 ftiod0 grb0 figure 14.32 (2) example of complementary pwm mode operation (tpsc2 = tpsc1 = tpsc0 0) (3)
section 14 timer z rev. 3.00 mar. 15, 2006 page 265 of 526 rej09b0060-0300 in complementary pwm mode, when the counter switches from up-counter to down-counter or vice versa, tcnt_0 and tcnt_1 overshoots or undershoots, respectivel y. in this case, the conditions to set the imfa flag in channel 0 and the udf flag in channel 1 differ from usual settings. also, the transfer conditio ns in buffer operation differ from usual settings. such timings are shown in figures 14.33 and 14.34. gr buffer transfer signal set to 1 flag is not set transferred to buffer not transferred to buffer n+1 gra_0 tcnt n n-1 n-1 n n imfa figure 14.33 timing of overshooting h'ffff h'0001 h'0001 h'0000 h'0000 gr udf tcnt buffer transfer signal set to 1 flag is not set transferred to buffer not transferred to buffer figure 14.34 timing of undershooting
section 14 timer z rev. 3.00 mar. 15, 2006 page 266 of 526 rej09b0060-0300 when the counter is incremented or decremented, th e imfa flag of channel 0 is set to 1, and when the register is underflowed, the udf flag of channel 0 is set to 1. after buffer operation has been designated for br, br is transfer red to gr when the counter is incremented by compare match a0 or when tcnt_1 is underflowed. if the ? ? ? ? ? ? ?
section 14 timer z rev. 3.00 mar. 15, 2006 page 267 of 526 rej09b0060-0300 ? ? ? ? ? ? ? ? ?
section 14 timer z rev. 3.00 mar. 15, 2006 page 268 of 526 rej09b0060-0300 d. buffer operation is used and other than tpsc2 = tpsc1 = tpsc0 = 0 write a value which satisfies gra_0 + 1 < gr < h'ffff to the buffer register. a waveform with a duty cycle of 0% can be output. however, a waveform with a duty cycle of 100% cannot be output using the buffer operation. also, the buffer operation cannot be used to change duty cycles while a waveform wi th a duty cycle of 100% is being output. for details on buffer operation, see section 14.4.8, buffer operation. 14.4.8 buffer operation buffer operation differs depending on whether gr has been designated for an input capture register or an output compare register, or in reset synchronous pwm mode or complementary pwm mode. table 14.8 shows the register combin ations used in buffer operation. table 14.8 register combinations in buffer operation general register buffer register gra grc grb grd 1. when gr is an output compare register when a compare match occurs, the value in the bu ffer register of the corresponding channel is transferred to the general register. this operation is illustrated in figure 14.35. buffer register comparator tcnt general register compare match signal figure 14.35 compare match buffer operation
section 14 timer z rev. 3.00 mar. 15, 2006 page 269 of 526 rej09b0060-0300 2. when gr is an input capture register when an input capture occurs, the value in tcnt is transferred to the general register and the value previously stored in the general register is transferred to the buffer register. this operation is illustrated in figure 14.36. tcnt buffer register general register input capture signal figure 14.36 input capture buffer operation 3. complementary pwm mode when the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general regi ster. here, the value of the buffer register is transferred to the general register in the following timing: a. when tcnt_0 and gra_0 are co mpared and their contents match b. when tcnt_1 underflows 4. reset synchronous pwm mode the value of the buffer register is transferred from compare match a0 to the general register. 5. example of buffer operation setting procedure figure 14.37 shows an example of the buffer operation setting procedure. [1] designate gr as an input capture register or output compare register by means of tior. [2] designate gr for buffer operation with bits bfd1, bfc1, bfd0, or bfc0 in tmdr. [3] set the str bit in tstr to 1 to start the count operation of tcnt. [1] [2] [3] select gr function set buffer operation start count operation buffer operation figure 14.37 example of buffe r operation setting procedure
section 14 timer z rev. 3.00 mar. 15, 2006 page 270 of 526 rej09b0060-0300 6. examples of buffer operation figure 14.38 shows an operation example in which gra has been designated as an output compare register, and buffer operation has been designated for gra and grc. this is an example of tcnt operating as a periodic counter cleared by compare match b. pins ftioa and ftiob are set for toggle output by compare match a and b. as buffer operation has been set, when compare match a occurs, the ftioa pin performs toggle outputs and the value in buffer register is simultaneously transferred to the general register. this operation is repeated each time that compare match a occurs. the timing to transfer data is shown in figure 14.39. grb tcnt value counter is cleared by gbr compare match time compare match a h'0250 h'0200 h'0100 h'0000 ftiob ftioa h'0200 h'0250 h'0200 h'0200 h'0100 h'0200 grc h'0100 gra figure 14.38 example of buffer operation (1) (buffer operation for ou tput compare register)
section 14 timer z rev. 3.00 mar. 15, 2006 page 271 of 526 rej09b0060-0300 gra n n tcnt compare match signal buffer transfer signal n n+1 grc n figure 14.39 example of compare match timing for buffer operation figure 14.40 shows an operation example in which gra has been designated as an input capture register, and buffer operation has been designated for gra and grc. counter clearing by input capture b has been se t for tcnt, and falling edges have been selected as the fiocb pin input capture input edge. and both rising and falling edges have been selected as the fioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in gra upon the occurrence of input capture a, the value previously stored in gra is simultaneously transferred to grc. the transfer timing is shown in figure 14.41.
section 14 timer z rev. 3.00 mar. 15, 2006 page 272 of 526 rej09b0060-0300 h'0180 h'0160 h'0005 h'0000 ftiob ftioa h'0160 h'0005 h'0005 gra h'0160 grc h'0180 grb tcnt value counter is cleared by the input capture b time input capture a figure 14.40 example of buffer operation (2) (buffer operation for i nput capture register)
section 14 timer z rev. 3.00 mar. 15, 2006 page 273 of 526 rej09b0060-0300 tcnt ftio pin input capture signal n n n+1 n+1 gra m n n n grc m m n m figure 14.41 input capture timing of buffer operation
section 14 timer z rev. 3.00 mar. 15, 2006 page 274 of 526 rej09b0060-0300 figures 14.42 and 14.43 show the operation examples when buffer operation has been designated for grb_0 and grd_0 in complementary pw m mode. these are examples when a pwm waveform of 0% duty is created by using the buffer operation and performing grd_0 gra_0 h'0000 h'0999 ftiob0 ftiod0 tcnt_0 tcnt values time grb_0 (when restored, data will be transferred to the saved location regardless of the cmd1 and cmd0 values) tcnt_1 h'0999 h'0999 h'0999 h'0999 h'1fff h'0999 grd_0 h'1fff grb_0 figure 14.42 buffer operation (3) (buffer operation in complementar y pwm mode cmd1 = cmd0 = 1)
section 14 timer z rev. 3.00 mar. 15, 2006 page 275 of 526 rej09b0060-0300 gra_0 h'0000 h'0999 ftioc0 ftiod0 tcnt values grb_0 (when restored, data will be transferred to the saved location regardless of the cmd1 and cmd0 values) time tcnt_0 tcnt_1 grb_0 h'0999 h'0999 h'0999 h'0000 h'0999 h'0000 grd_0 grb_0 figure 14.43 buffer operation (4) (buffer operation in complementary pwm mode cmd1 = cmd0 = 1)
section 14 timer z rev. 3.00 mar. 15, 2006 page 276 of 526 rej09b0060-0300 14.4.9 timer z output timing the outputs of channels 0 and 1 can be disabled or inverted by the settings of toer and tocr and the external level. 1. output disable/enable timing of timer z by toer: setting the master enable bit in toer to 1 disables the output of timer z. by setting the pcr and pdr of the corresponding i/o port beforehand, any value can be output. figure 14.44 shows the timing to enable or disable the output of timer z by toer. t 1 t 2 toer address bus toer address timer z output pin timer z output i/o port i/o port timer output figure 14.44 example of ou tput disable timing of timer z by writing to toer
section 14 timer z rev. 3.00 mar. 15, 2006 page 277 of 526 rej09b0060-0300 2. output disable timing of timer z by external trigger: when p54/ wkp4 is set as a wkp4 input pin, and low level is input to wkp4 , the master enable bit in toer is set to 1 and the output of timer z will be disabled. wkp4 toer timer z output pin timer z output i/o port timer z output i/o port n h'ff figure 14.45 example of output disable timing of timer z by external trigger 3. output inverse timing by tfcr: the output level can be inverted by inverting the ols1 and ols0 bits in tfcr in reset synchronous pwm mode or complementary pwm mode. figure 14.46 shows the timing. t 1 t 2 tfcr inverted timer z output pin address bus toer address figure 14.46 example of ou tput inverse timing of ti mer z by writing to tfcr
section 14 timer z rev. 3.00 mar. 15, 2006 page 278 of 526 rej09b0060-0300 4. output inverse timing by pocr: the output level can be inverted by inverting the pold, polc, and polb bits in pocr in pwm mode. figure 14.47 shows the timing. t 1 t 2 tfcr address bus pocr address timer z output pin inverted figure 14.47 example of output inverse timing of timer z by writing to pocr 14.5 interrupts there are three kinds of timer z interrupt sources; input capture/compare match, overflow, and underflow. an interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 14.5.1 status fl ag set timing 1. imf flag set timing: the imf flag is set to 1 by the compare match signal that is generated when the gr matches with the tc nt. the compare match signal is generated at the last state of matching (timing to update the counter va lue when the gr and tcnt match). therefore, when the tcnt and gr matches, the compare match signal will not be generated until the tcnt input clock is generated. figure 14.48 shows the timing to set the imf flag.
section 14 timer z rev. 3.00 mar. 15, 2006 page 279 of 526 rej09b0060-0300 imf itmz tcnt tcnt input clock compare match signal n n+1 gr n figure 14.48 imf flag set timi ng when compare match occurs 2. imf flag set timing at input capture: when an input capture signal is generated, the imf flag is set to 1 and the value of tcnt is simultane ously transferred to corresponding gr. figure 14.49 shows the timing. imf input capture signal tcnt n gr n itmz figure 14.49 imf flag set timing at input capture
section 14 timer z rev. 3.00 mar. 15, 2006 page 280 of 526 rej09b0060-0300 3. overflow flag (ovf) set timing: the overflow flag is set to 1 when the tcnt overflows. figure 14.50 shows the timing. ovf tcnt overflow signal h'0000 h'ffff itmz figure 14.50 ovf flag set timing 14.5.2 status flag clearing timing the status flag can be cleared by writing 0 after reading 1 from the cpu. figure 14.51 shows the timing in this case. address tsr address wtsr (internal write signal) imf, ovf itmz figure 14.51 status flag clearing timing
section 14 timer z rev. 3.00 mar. 15, 2006 page 281 of 526 rej09b0060-0300 14.6 usage notes 1. contention between tcnt write and clear operat ions: if a counter clear signal is generated in the t 2 state of a tcnt write cycle, tcnt clearin g has priority and the tcnt write is not performed. figure 14.52 shows the timing in this case. t 1 t 2 tcnt tcnt write cycle tcnt address wtcnt (internal write signal) clearing has priority. counter clear signal n h'0000 figure 14.52 contention betwee n tcnt write and clear operations 2. contention between tcnt write and incremen t operations: if increm entation is done in t 2 state of a tcnt write cycle, tcnt writing has priority. figure 14.53 shows the timing in this case. t 1 t 2 tcnt tcnt write cycle tcnt address wtcnt (internal write signal) tcnt input clock tcnt write data n m figure 14.53 contention between tc nt write and increment operations
section 14 timer z rev. 3.00 mar. 15, 2006 page 282 of 526 rej09b0060-0300 3. contention between gr write and compare matc h: if a compare match occurs in the t 2 state of a gr write cycle, gr write has priority and the compare match signal is disabled. figure 14.54 shows the timing in this case. t 1 t 2 gr n m tcnt gr write cycle gr address wgr (internal write signal) gr write data compare match signal disabled n n+1 figure 14.54 contention between gr write and compare match
section 14 timer z rev. 3.00 mar. 15, 2006 page 283 of 526 rej09b0060-0300 4. contention between tcnt write and overflow/underflow: if overflow/underflow occurs in the t 2 state of a tcnt write cycle, tcnt write ha s priority without an increment operation. at this time, the ovf flag is set to 1. figure 14.55 shows the timing in this case. t 1 t 2 tcnt h'ffff m ovf tcnt address wtcnt (internal write signal) tcnt input clock overflow signal tcnt write data tcnt write cycle figure 14.55 contention be tween tcnt write and overflow
section 14 timer z rev. 3.00 mar. 15, 2006 page 284 of 526 rej09b0060-0300 5. contention between gr read and input capture: if an input capture signal is generated in the t 1 state of a gr read cycle, the data that is read will be transferre d before input capture transfer. figure 14.56 shows the timing in this case. t 1 t 2 gr gr read cycle gr address internal read signal input capture signal internal data bus x x m figure 14.56 contention between gr read and input capture
section 14 timer z rev. 3.00 mar. 15, 2006 page 285 of 526 rej09b0060-0300 6. contention between count clearing and incremen t operations by input capture: if an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. the tcnt contents before clearing counter are transferred to gr. figu re 14.57 shows the timing in this case. tcnt input capture signal counter clear signal tcnt input clock clearing has priority. n h'0000 gr n figure 14.57 contention between co unt clearing and increment operations by input capture
section 14 timer z rev. 3.00 mar. 15, 2006 page 286 of 526 rej09b0060-0300 7. contention between gr write and input capture: if an input capture signal is generated in the t 2 state of a gr write cycle, the input capture op eration has priority and the write to gr is not performed. figure 14.58 shows the timing in this case. t 1 t 2 tcnt n gr write cycle gr address input capture signal wgr (internal write signal) address bus gr write data gr m figure 14.58 contention between gr write and input capture 8. notes on setting reset synchronous pwm mode/complementary pwm mode: when bits cmd1 and cmd0 in tfcr are set, note the following: a. write bits cmd1 and cmd0 while tcnt_1 and tcnt_0 are halted. b. changing the settings of reset synchronous pwm mode to complementary pwm mode or vice versa is disabled. set reset synchronous pwm mode or complementary pwm mode after the normal operation (bits cmd1 and cm d0 are cleared to 0) has been set. 9. notes on writing to the toa0 to tod0 bits and the toa1 to tod1 bits in tocr: the toa0 to tod0 bits and the toa1 to tod1 bits in tocr decide the value of the ftio pin, which is output until the first compare match occurs. once a compare match occurs and this compare match changes the values of ftioa0 to ftiod0 and ftioa1 to ftiod1 output, the values of the ftioa0 to ftiod0 and ftioa1 to ftiod1 pin output and the values read from the toa0 to tod0 and toa1 to tod1 bits may differ. moreover, when the writing to tocr and the generation of the compare match a0 to d0 and a1 to d1 occur at the same timing, the writing to tocr has the priority. thus, output change due to the compare match is not reflected to the ftioa0 to ftio d0 and ftioa1 to ftiod1 pins. therefore, when bit manipulation instruction is used to write to tocr, the values of the ftioa0 to ftiod0 and ftioa1 to ftiod1 pin output may result in an unexpected result. when tocr is to be written to while compare match is oper ating, stop the counter once before accessing to
section 14 timer z rev. 3.00 mar. 15, 2006 page 287 of 526 rej09b0060-0300 tocr, read the port 6 state to reflect the va lues of ftioa0 to ftiod0 and ftioa1 to ftiod1 output, to toa0 to tod0 and toa1 to tod1, and then restart the counter. figure 14.59 shows an example when the compare match and the bit manipulation instruction to tocr occur at the same timing. compare match signal b0 ftiob0 pin tocr write signal set value bit tocr 000 00110 765 43210 tod1 toc1 tob1 toa1 tod0 toc0 tob0 toa0 expected output remains high because the 1 writing to tob has priority tocr has been set to h'06. compare match b0 and compare match c0 are used. the ftiob0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match b0. when bclr#2, @tocr is executed to clear the toc0 bit (the ftioc0 signal is low) and compare match b0 occurs at the same timing as shown below, the h'02 writing to tocr has priority and compare match b0 does not drive the ftiob0 signal low; the ftiob0 signal remains high. bclr#2, @tocr (1) tocr read operation: read h'06 (2) modify operation: modify h'06 to h'02 (3) write operation to tocr: write h'02 figure 14.59 when compa re match and bit manipulation instruction to tocr occur at the same timing
section 14 timer z rev. 3.00 mar. 15, 2006 page 288 of 526 rej09b0060-0300
section 15 watchdog timer rev. 3.00 mar. 15, 2006 page 289 of 526 rej09b0060-0300 section 15 watchdog timer the watchdog timer is an 8-bit timer that can gene rate an internal reset signal for this lsi if a system crash prevents the cpu from writing to th e timer counter, thus allowing it to overflow. the block diagram of the watchdog timer is shown in figure 15.1. internal reset signal pss tcwd tmwd tcsrwd internal data bus [legend] tcsrwd: tcwd: pss: tmwd: timer control/status register wd timer counter wd prescaler s timer mode register wd internal oscillator clk figure 15.1 block diagram of watchdog timer 15.1 features ? ?
section 15 watchdog timer rev. 3.00 mar. 15, 2006 page 290 of 526 rej09b0060-0300 15.2 register descriptions the watchdog timer has the following registers. ? ? ? 15.2.1 timer control/stat us register wd (tcsrwd) tcsrwd performs the tcsrwd and tcwd writ e control. tcsrwd also controls the watchdog timer operation and indicates the operatin g state. tcsrwd must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. bit bit name initial value r/w description 7 b6wi 1 r/w bit 6 write inhibit the tcwe bit can be written only when the write value of the b6wi bit is 0. this bit is always read as 1. 6 tcwe 0 r/w timer counter wd write enable tcwd can be written when the tcwe bit is set to 1. when writing data to this bit, the value for bit 7 must be 0. 5 b4wi 1 r/w bit 4 write inhibit the tcsrwe bit can be written only when the write value of the b4wi bit is 0. this bit is always read as 1. 4 tcsrwe 0 r/w timer control/status register wd write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the value for bit 5 must be 0. 3 b2wi 1 r/w bit 2 write inhibit this bit can be written to the wdon bit only when the write value of the b2wi bit is 0. this bit is always read as 1.
section 15 watchdog timer rev. 3.00 mar. 15, 2006 page 291 of 526 rej09b0060-0300 bit bit name initial value r/w description 2 wdon 0 r/w watchdog timer on tcwd starts counting up when wdon is set to 1 and halts when wdon is cleared to 0. [setting condition] when 1 is written to the wdon bit while writing 0 to the b2wi bit when the tcsrwe bit=1 [clearing conditions] ? reset by res pin ? when 0 is written to the wdon bit while writing 0 to the b2wi when the tcsrwe bit=1 1 b0wi 1 r/w bit 0 write inhibit this bit can be written to the wrst bit only when the write value of the b0wi bit is 0. this bit is always read as 1. 0 wrst 0 r/w watchdog timer reset [setting condition] when tcwd overflows and an internal reset signal is generated [clearing conditions] ? reset by res pin ? when 0 is written to the wrst bit while writing 0 to the b0wi bit when the tcsrwe bit=1
section 15 watchdog timer rev. 3.00 mar. 15, 2006 page 292 of 526 rej09b0060-0300 15.2.2 timer coun ter wd (tcwd) tcwd is an 8-bit readable/writable up-counter. when tcwd overflows from h'ff to h'00, the internal reset signal is generated and the wrst bit in tcsrwd is set to 1. tcwd is initialized to h'00. 15.2.3 timer mode register wd (tmwd) tmwd selects the input clock. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 2 1 0 cks3 cks2 cks1 cks0 1 1 1 1 r/w r/w r/w r/w clock select 3 to 0 select the clock to be input to tcwd. 1000: internal clock: counts on /64 1001: internal clock: counts on /128 1010: internal clock: counts on /256 1011: internal clock: counts on /512 1100: internal clock: counts on /1024 1101: internal clock: counts on /2048 1110: internal clock: counts on /4096 1111: internal clock: counts on /8192 0xxx: internal oscillator for the internal oscillator overflow periods, see section 23, electrical characteristics. [legend] x: don't care.
section 15 watchdog timer rev. 3.00 mar. 15, 2006 page 293 of 526 rej09b0060-0300 15.3 operation the watchdog timer is provided with an 8-bit counter. if 1 is written to wdon while writing 0 to b2wi when the tcsrwe bit in tcsrwd is set to 1, tcwd begins counting up. (to operate the watchdog timer, two write accesses to tcsrwd are required.) when a clock pulse is input after the tcwd count value has reached h'ff, the wa tchdog timer overflows and an internal reset signal is generated. the internal reset signal is output for a period of 256 example: with 30ms overflow period when = 4 mhz 4 10 6 30 10 ?3 = 14.6 8192 tcwd overflow h'ff h'00 internal reset signal h'f1 tcwd count value h'f1 written to tcwd h'f1 written to tcwd reset generated start 256 osc clock cycles therefore, 256 ? 15 = 241 (h'f1) is set in tcw. figure 15.2 watchdog timer operation example
section 15 watchdog timer rev. 3.00 mar. 15, 2006 page 294 of 526 rej09b0060-0300
section 16 14-bit pwm rev. 3.00 mar. 15, 2006 page 295 of 526 rej09b0060-0300 section 16 14-bit pwm the 14-bit pwm is a pulse division type pwm that can be used for electronic tuner control, etc. figure 16.1 shows a block diagram of the 14-bit pwm. 16.1 features ? ? pwcr: pwm control register [legend] internal data bus pwdrl: pwm data register l pwdru: pwm data register u pwm: pwm output pin pwcr pwdrl pwdru pwm pwm waveform generator /4 /2 figure 16.1 block diagram of 14-bit pwm 16.2 input/output pin table 16.1 shows the 14-bit pwm pin configuration. table 16.1 pin configuration name abbreviation i/o function 14-bit pwm square-wave output pwm out put 14-bit pwm square-wave output pin
section 16 14-bit pwm rev. 3.00 mar. 15, 2006 page 296 of 526 rej09b0060-0300 16.3 register descriptions the 14-bit pwm has the following registers. ? ? ? 16.3.1 pwm control register (pwcr) pwcr selects the conversion period. bit bit name initial value r/w description 7 6 5 4 3 2 1 ? ? ? ? ? ? ? 1 1 1 1 1 1 1 ? ? ? ? ? ? ? reserved these bits are always read as 1, and cannot be modified. 0 pwcr0 0 r/w clock select 0: the input clock is /2 (t = 2/ ) ? the conversion period is 16384/ , with a minimum modulation width of 1/ 1: the input clock is /4 (t = 4/ ) ? the conversion period is 32768/ , with a minimum modulation width of 2/ [legend] t : period of pwm clock input
section 16 14-bit pwm rev. 3.00 mar. 15, 2006 page 297 of 526 rej09b0060-0300 16.3.2 pwm data registers u, l (pwdru, pwdrl) pwdru and pwdrl indicate high level width in one pwm waveform cycle. pwdru and pwdrl are 14-bit write-only registers, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. when read, all bits are always read as 1. both pwdru and pwdrl are accessibl e only in bytes. note that th e operation is not guaranteed if word access is performed. when 14-bit data is written in pwdru and pwdrl, the contents are latched in the pwm waveform generator and the pwm waveform generation data is updated. when writing the 14-bit data, the order is as follows: pwdrl to pwdru. pwdru and pwdrl are initialized to h'c000. 16.4 operation when using the 14-bit pwm, set the registers in this sequence: 1. set the pwm bit in the port mode register 1 (pmr1) to set the p11/pwm pin to function as a pwm output pin. 2. set the pwcr0 bit in pwcr to select a conversion period of either. 3. set the output waveform data in pwdru and pw drl. be sure to write byte data first to pwdrl and then to pwdru. when the data is written in pwdru, the contents of these registers are latched in the pwm waveform generator, and the pwm waveform generation data is updated in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 16.2. the total high-level width during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be expressed as follows: t h = (data value in pwdru and pwdrl + 64) t /2 where t t h = 64 t /2 = 32 t
section 16 14-bit pwm rev. 3.00 mar. 15, 2006 page 298 of 526 rej09b0060-0300 t h64 t h63 t h3 t h2 t h1 t h = t h1 + t h2 + t h3 + ... + t h64 t f1 = t f2 = t f3 = ... = t f64 t f1 t f2 t f63 t f64 conversion period figure 16.2 waveform output by 14-bit pwm
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 299 of 526 rej09b0060-0300 section 17 serial communi cation interface 3 (sci3) this lsi includes a serial communication interface 3 (sci3), which has independent three channels. the sci3 can handle both asynchronous and clocked synchronous serial communication. in asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronou s communication interface adapter (acia). a function is also provided for serial commun ication between processors (multiprocessor communication function). table 17.1 shows the sci3 channel configuration and figure 17.1 shows a block diagram of the sci3. since basic pin functions are identical for each of the three channels (sci3, sci3_2, and sci3_3), separate explanations are not given in this section. 17.1 features ? ? ? ? ? ? ? ? ? ? ?
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 300 of 526 rej09b0060-0300 clocked synchronous mode ? ? table 17.1 channel configuration channel abbreviation pin register register address noise canceller smr h'ffffa8 brr h'ffffa9 scr3 h'ffffaa tdr h'ffffab ssr h'ffffac rdr h'ffffad rsr ? channel 1 sci3 * 2 sck3 rxd txd tsr ? none smr_2 h'fff740 brr_2 h'fff741 scr3_2 h'fff742 tdr_2 h'fff743 ssr_2 h'fff744 rdr_2 h'fff745 rsr_2 ? channel 2 sci3_2 sck3_2 rxd_2 txd_2 tsr_2 ? none smr_3 h'fff600 brr_3 h'fff601 scr3_3 h'fff602 tdr_3 h'fff603 ssr_3 h'fff604 rdr_3 h'fff605 rsr_3 ? tsr_3 ? channel 3 sci3_3 sck3_3 rxd_3 txd_3 smcr_3 * 1 h'fff608 yes
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 301 of 526 rej09b0060-0300 note: 1. in addition to basic functions common to sci3 and sci3_2, sci3_3 has the serial mode control register (smcr). smcr controls taking noise from the rxd_3 input signal, p92/txd_3 pin function, and sci3_3 module standby function. 2. the channel 1 of the sci3 is used in on-board programming mode by boot mode. ? bit bit name initial value r/w description 7 to 3 ? all 1 ? reserved these bits are always read as 1. 2 nfen_3 0 r/w noise cancel function select when com in smr is cleared to 0 and this bit is set to 1, noise in the rxd_3 input signal is taken. 1 txd_3 0 r/w txd_3 pin select selects p92/txd_3 pin function. 0: general input pin is selected 1: txd_3 output pin is selected 0 msts3_3 0 r/w sci3_3 module standby when this bit is set to 1, sci3_3 enters in the standby state. ?
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 302 of 526 rej09b0060-0300 rxd_3 input signal internal rxd_3 signal in figure 17.1 sampling clock sampling clock internal basic clock interval c latch q d c latch q d c latch q d match detector scmr3 (nfef_3) block diagram of noise canceller clock txd rxd sck3 tsr rsr tdr ssr scr3 smr brr rdr transmit/receive control circuit internal data bus [legend] rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter interrupt request (tei, txi, rxi, eri) internal clock ( /64, /16, /4, ) external clock brc baud rate generator figure 17.1 block diagram of sci3
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 303 of 526 rej09b0060-0300 17.2 input/output pins table 17.2 shows the sci3 pin configuration. table 17.2 pin configuration pin name abbreviation i/o function sci3 clock sck3 i/o sc i3 clock input/output sci3 receive data input rxd i nput sci3 receive data input sci3 transmit data output txd output sci3 transmit data output 17.3 register descriptions the sci3 has the following registers for each channel. ? ? ? ? ? ? ? ? ? 17.3.1 receive shi ft register (rsr) rsr is a shift register that is us ed to receive serial data input fr om the rxd pin and convert it into parallel data. when one frame of data has been r eceived, it is transferre d to rdr automatically. rsr cannot be directly accessed by the cpu. 17.3.2 receive data register (rdr) rdr is an 8-bit register that stores received data. when the sci3 has receiv ed one frame of serial data, it transfers the received serial data from rsr to rdr, where it is stored. after this, rsr is receive-enabled. as rsr and rdr function as a d ouble buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 304 of 526 rej09b0060-0300 17.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci3 first transfers transmit data fr om tdr to tsr automatically, then sends the data that starts from the lsb to the txd pin . tsr cannot be directly accessed by the cpu. 17.3.4 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sc i3 detects that tsr is empty, it transfers the tr ansmit data written in tdr to tsr an d starts transmission. the double- buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during transm ission of one-frame data, the sci3 transfers the written data to tsr to continue transmission. to achieve reliable serial transmission, write transmit data to tdr only once after confirming th at the tdre bit in ssr is set to 1. tdr is initialized to h'ff. 17.3.5 serial mode register (smr) smr is used to set the sci3's serial transfer format and select the baud rate generator clock source. bit bit name initial value r/w description 7 com 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 pm 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 305 of 526 rej09b0060-0300 bit bit name initial value r/w description 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits for reception, only the first stop bit is checked, regardless of the value in the bit. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and pm bit settings are invalid in multiprocessor mode. in clocked synchronous mode, clear this bit to 0. 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 17.3.8, bit rate register (brr). n is the decimal repres entation of the value of n in brr (see section 17.3.8, bit rate register (brr)).
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 306 of 526 rej09b0060-0300 17.3.6 serial control register 3 (scr3) scr3 is a register that enables or disables sci3 transfer operations and interrupt requests, and is also used to select the transfer clock source. for details on inte rrupt requests, see section 17.7, interrupt requests. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit s set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and oer status flags in ssr is disabled. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, see se ction 17.6, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, tei interrupt request is enabled.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 307 of 526 rej09b0060-0300 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source. ? asynchronous mode 00: on-chip baud rate generator 01: on-chip baud rate generator outputs a clock of the same frequency as the bit rate from the sck3 pin. 10: external clock inputs a clock with a frequency 16 times the bit rate from the sck3 pin. 11:reserved ? clocked synchronous mode 00: on-chip clock (sck3 pin functions as clock output) 01:reserved 10: external clock (sck3 pin functions as clock input) 11:reserved 17.3.7 serial status register (ssr) ssr is a register containing status flags of the sci3 and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? when the te bit in scr3 is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 308 of 526 rej09b0060-0300 bit bit name initial value r/w description 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when data is read from rdr 5 oer 0 r/w overrun error [setting condition] ? when an overrun error occurs in reception [clearing condition] ? when 0 is written to oer after reading oer = 1 4 fer 0 r/w framing error [setting condition] ? when a framing error occurs in reception [clearing condition] ? when 0 is written to fer after reading fer = 1 3 per 0 r/w parity error [setting condition] ? when a parity error is detected during reception [clearing condition] ? when 0 is written to per after reading per = 1 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr3 is 0 ? when tdre = 1 at transmission of the last bit of a 1-frame serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 309 of 526 rej09b0060-0300 bit bit name initial value r/w description 1 mpbr 0 r multiprocessor bit receive mpbr stores the multiprocessor bit in the receive character data. when the re bit in scr3 is cleared to 0, its state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit character data. 17.3.8 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. the initial value of brr is h'ff. table 17.3 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in asynchronous mode. table 17.4 show s the maximum bit rate for each frequency in asynchronous mode. the values shown in both ta bles 17.3 and 17.4 are values in active (high- speed) mode. table 17.5 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in clocked synchronous mode. the values shown in table 17.5 are values in active (high-speed) mode. the n setting in brr and error for other operating frequencies and bit rates can be obtained by the following formulas: [asynchronous mode] n = 64 2 2n?1 b 10 6 ? 1 error (%) = ? 1 100 ? ? ? ? ? ? 10 6 (n + 1) b 64 2 2n?1 [clocked synchronous mode] n = 8 2 2n?1 b 10 6 ? 1 [legend] b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: csk1 and csk0 settings in smr (0 n 3)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 310 of 526 rej09b0060-0300 table 17.3 examples of brr settings for various bit rates (asynchronous mode) (1) operating frequency (mhz) 2 2.097152 2.4576 3 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 0 19 ?2.34 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 0 9 ?2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 ?2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 ?18.62 0 1 ?14.67 0 1 0.00 ? ? ?
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 311 of 526 rej09b0060-0300 operating frequency (mhz) 3.6864 4 4.9152 5 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 ?6.99 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 [legend] ? : a setting is available but error occurs
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 312 of 526 rej09b0060-0300 table 17.3 examples of brr settings for various bit rates (asynchronous mode) (2) operating frequency (mhz) 6 6.144 7.3728 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.00 0 95 0.00 4800 0 38 0.16 0 39 0.00 0 47 0.00 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 31250 0 5 0.00 0 5 2.40 0 6 5.33 38400 0 4 ?2.34 0 4 0.00 0 5 0.00
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 313 of 526 rej09b0060-0300 operating frequency (mhz) 8 9.8304 10 12 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 141 0.03 2 174 ?0.26 2 177 ?0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 ?1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 ?2.34 31250 0 7 0.00 0 9 ?1.70 0 9 0.00 0 11 0.00 38400 0 6 -6.99 0 7 0.00 0 7 1.73 0 9 ?2.34 [legend] ? : a setting is availabl e but error occurs.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 314 of 526 rej09b0060-0300 table 17.3 examples of brr settings for various bit rates (asynchronous mode) (3) operating frequency (mhz) 12.888 14 14.7456 16 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 217 0.08 2 248 ?0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 ?0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 ?0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 ?1.70 0 15 0.00 38400 0 9 0.00 ? ? ? 0 11 0.00 0 12 0.16
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 315 of 526 rej09b0060-0300 operating frequency (mhz) 18 20 bit rate (bit/s) n n error (%) n n error (%) 110 3 79 ?0.12 3 88 ?0.25 150 2 233 0.16 3 64 0.16 300 2 116 0.16 2 129 0.16 600 1 233 0.16 2 64 0.16 1200 1 116 0.16 1 129 0.16 2400 0 233 0.16 1 64 0.16 4800 0 116 0.16 0 129 0.16 9600 0 58 ?0.96 0 64 0.16 19200 0 28 1.02 0 32 ?1.36 31250 0 17 0.00 0 19 0.00 38400 0 14 ?2.34 0 15 1.73 [legend] ?: a setting is available but error occurs. table 17.4 maximum bit rate for ea ch frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 8 250000 0 0 2.097152 65536 0 0 9.8304 307200 0 0 2.4576 76800 0 0 10 312500 0 0 3 93750 0 0 12 375000 0 0 3.6864 115200 0 0 12.288 384000 0 0 4 125000 0 0 14 437500 0 0 4.9152 153600 0 0 14.7456 460800 0 0 5 156250 0 0 16 500000 0 0 6 187500 0 0 17.2032 537600 0 0 6.144 192000 0 0 18 562500 0 0 7.3728 230400 0 0 20 625000 0 0
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 316 of 526 rej09b0060-0300 table 17.5 examples of brr settings for various bi t rates (clocked synchronous mode) (1) operating frequency (mhz) 2 4 8 10 16 bit rate (bit/s) n n n n n n n n n n 110 3 70 ? ? ? ? ? ? 250 2 124 2 249 3 124 ? ? 3 249 500 1 249 2 124 2 249 ? ? 3 124 1k 1 124 1 249 2 124 ? ? 2 249 2.5k 0 199 1 99 1 199 1 249 2 99 5k 0 99 0 199 1 99 1 124 1 199 10k 0 49 0 99 0 199 0 249 1 99 25k 0 19 0 39 0 79 0 99 0 159 50k 0 9 0 19 0 39 0 49 0 79 100k 0 4 0 9 0 19 0 24 0 39 250k 0 1 0 3 0 7 0 9 0 15 500k 0 0 * 0 1 0 3 0 4 0 7 1m 0 0 * 0 1 ? ? 0 3 2m 0 0 * ? ? 0 1 2.5m 0 0 * ? ? 4m 0 0 * [legend] blank: no setting is available. ?: a setting is available but error occurs. * : continuous transfer is not possible.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 317 of 526 rej09b0060-0300 table 17.5 examples of brr settings for various bi t rates (clocked synchronous mode) (2) operating frequency (mhz) 18 20 bit rate (bit/s) n n n n 110 ? ? ? ? 250 ? ? ? ? 500 3 140 3 155 1k 3 69 3 77 2.5k 2 112 2 124 5k 1 224 1 249 10k 1 112 1 124 25k 0 179 0 199 50k 0 89 0 99 100k 0 44 0 49 250k 0 17 0 19 500k 0 8 0 9 1m 0 4 0 4 2m ? ? ? ? 2.5m ? ? 0 1 4m ? ? ? ? [legend] blank: no setting is available. ?: a setting is available but error occurs. * : continuous transfer is not possible.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 318 of 526 rej09b0060-0300 17.4 operation in asynchronous mode figure 17.2 shows the general format for asynchronous serial communication. one character (or frame) consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). inside the sci3, the tran smitter and receiver are independent units, enabling full-dupl ex. both the transmitter and th e receiver also have a double- buffered structure, so data can be read or wr itten during transmission or reception, enabling continuous data transfer. lsb start bit msb mark state stop bit transmit/receive data 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 17.2 data format in asynchronous communication 17.4.1 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck3 pin can be selected as the sci3's serial clock, according to the setting of the com bit in smr and the cke0 and cke1 bits in scr3. when an external clock is input at the sck3 pin, the clock frequency should be 16 times the bit rate used. when the sci3 is operated on an internal clock, the clock can be output from the sck3 pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 17.3. 0 1 character (frame) d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 clock serial data figure 17.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-bit data, parity, two stop bits)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 319 of 526 rej09b0060-0300 17.4.2 sci3 initialization before transmitting and receiving data, you should first clear the te and re bits in scr3 to 0, then initialize the sci3 as described below. wh en the operating mode, or transfer format, is changed for example, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and oer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait start initialization set data transfer format in smr [1] set cke1 and cke0 bits in scr3 no yes set value in brr clear te and re bits in scr3 to 0 [2] [3] set te and re bits in scr3 to 1, and set rie, tie, teie, and mpie bits. for transmit (te=1), also set the txd bit in pmr1. [4] 1-bit interval elapsed? [1] set the clock selection in scr3. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock output is selected in asynchronous mode, clock is output immediately after cke1 and cke0 settings are made. when the clock output is selected at reception in clocked synchronous mode, clock is output immediately after cke1, cke0, and re are set to 1. [2] set the data transfer format in smr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr3 to 1. re settings enable the rxd pin to be used. for transmission, set the txd bit in pmr1 to 1 to enable the txd output pin to be used. also set the rie, tie, teie, and mpie bits, depending on whether interrupts are required. in asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. figure 17.4 sample sci3 initialization flowchart
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 320 of 526 rej09b0060-0300 17.4.3 data transmission figure 17.5 shows an example of operation for transmission in asynchronous mode. in transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr. if the flag is cleared to 0, th e sci3 recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at th is time, a txi interrupt request is generated. continuous transmission is possible because the txi interrupt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. the sci3 checks the tdre flag at the timing for sending the stop bit. 4. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 5. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the tei e bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 6. figure 17.6 shows a sample flowchart for transmission in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1d0d1d70/11 1 1 0d0d1 d70/1 serial data tdre tend lsi operation txi interrupt request generated tdre flag cleared to 0 user processing data written to tdr txi interrupt request generated tei interrupt request generated figure 17.5 example of sci3 transmission in asynchronous mode (8-bit data, parity, one stop bit)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 321 of 526 rej09b0060-0300 no no no no yes start transmission read tdre flag in ssr [1] [2] [3] tdre = 1 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [2] to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [3] to output a break in serial transmission, after setting pcr to 1 and pdr to 0, clear txd in pmr1 to 0, then clear the te bit in scr3 to 0. yes write transmit data to tdr all data transmitted? yes read tend flag in ssr clear te bit in scr3 to 0 clear pdr to 0 and set pcr to 1 tend = 1 yes break output? figure 17.6 sample serial transmission data flowchart (asynchronous mode)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 322 of 526 rej09b0060-0300 17.4.4 serial data reception figure 17.7 shows an example of operation for reception in asynchronous mode. in serial reception, the sci3 operat es as described below. 1. the sci3 monitors the communication line. if a start bit is detected, the sci3 performs internal synchronization, receives receive data in rsr, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible because the rxi inte rrupt routine r eads the receive data transferred to rdr before reception of the next receive data has been completed. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1d0d1d70/11 01 0d0d1 d70/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 stop bit detected eri request in response to framing error figure 17.7 example of sci3 reception in asynchronous mode (8-bit data, parity, one stop bit)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 323 of 526 rej09b0060-0300 table 17.6 shows the states of th e ssr status flags and receive da ta handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 17.8 shows a sample flow chart for serial data reception. table 17.6 ssr status flag s and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the stat e it had before data reception.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 324 of 526 rej09b0060-0300 yes yes yes no no no start reception [1] read rdrf flag in ssr read receive data in rdr clear re bit in scr3 to 0 [2] [3] read oer, per, and fer flags in ssr error processing (continued on next page) [4] oer+per+fer = 1 rdrf = 1 all data received? [1] read the oer, per, and fer flags in ssr to identify the error. if a receive error occurs, performs the appropriate error processing. [2] read ssr and check that rdrf = 1, then read the receive data in rdr. the rdrf flag is cleared automatically. [3] to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag and read rdr. the rdrf flag is cleared automatically. [4] if a receive error occurs, read the oer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. (a) figure 17.8 sample serial reception data flowchart (asynchronous mode) (1)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 325 of 526 rej09b0060-0300 (a) error processing parity error processing yes no clear oer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing oer = 1 fer = 1 break? per = 1 [4] figure 17.8 sample serial reception data flowchart (asynchronous mode) (2)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 326 of 526 rej09b0060-0300 17.5 operation in clocked synchronous mode figure 17.9 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received synchronous with clock pulses. a single character in the transmit data co nsists of the 8-bit data starti ng from the lsb. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next. in clocked synchronous mo de, the sci3 receives data in synchronous with the rising edge of the synchronization clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci3, the transmitter and receiver are independent units, enabling full- duplex communication thro ugh the use of a common clock. bo th the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling conti nuous data transfer. don't care don't care one unit of transfer data (character or frame) 8-bit bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 17.9 data format in clocked synchronous communication 17.5.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck3 pin can be selected, according to the setting of the com bit in smr and cke0 and cke1 bits in scr3. when the sci3 is operated on an internal clock, the synchronization clock is output from the sck3 pin. eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 17.5.2 sci3 initialization before transmitting and receiving data, the sci3 sh ould be initialized as described in a sample flowchart in figure 17.4.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 327 of 526 rej09b0060-0300 17.5.3 serial data transmission figure 17.10 shows an example of sci3 operation for transmission in clocked synchronous mode. in serial transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr, and if the flag is 0, the sci3 recognizes that data has been written to tdr, and transf ers the data from tdr to tsr. 2. the sci3 sets the tdre flag to 1 and starts tr ansmission. if the tie bit in scr3 is set to 1 at this time, a transmit data empty interrupt (txi) is generated. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. serial data is transmitted sequentially from the lsb (bit 0), from the txd pin. 4. the sci3 checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 7. the sck3 pin is fixed high at the end of transmission. figure 17.11 shows a sample flow chart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a r eceive error flag (oer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi interrupt request generated data written to tdr tdre flag cleared to 0 txi interrupt request generated tei interrupt request generated figure 17.10 example of sci3 transmission in clocked synchronous mode
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 328 of 526 rej09b0060-0300 no yes start transmission read tdre flag in ssr [1] write transmit data to tdr no yes no yes read tend flag in ssr [2] clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0 and clocks are output to start the data transmission. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. figure 17.11 sample serial transmission flowchart (clocked synchronous mode)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 329 of 526 rej09b0060-0300 17.5.4 serial data reception (clocked synchronous mode) figure 17.12 shows an example of sci3 operation for reception in clocked synchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. 2. the sci3 stores the receive data in rsr. 3. if an overrun error occurs (when reception of the next data is completed while the rdrf flag in ssr is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated, re ceive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 4. if reception is comple ted successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. serial clock serial data 1 frame 1 frame bit 0 bit 7 bit 7 bit 0 bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi interrupt request generated rdr data read rdrf flag cleared to 0 rxi interrupt request generated eri interrupt request generated by overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 17.12 example of sci3 reception in clocked synchronous mode
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 330 of 526 rej09b0060-0300 reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 17.13 shows a sample flow chart for serial data reception. yes no start reception [1] [4] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 error processing (continued below) read receive data in rdr yes no oer = 1 rdrf = 1 all data received? read oer flag in ssr error processing overrun error processing clear oer flag in ssr to 0 [4] [1] read the oer flag in ssr to determine if there is an error. if an overrun error has occurred, execute overrun error processing. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial reception, before the msb (bit 7) of the current frame is received, reading the rdrf flag and reading rdr should be finished. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. reception cannot be resumed if the oer flag is set to 1. figure 17.13 sample serial reception flowchart (clocked synchronous mode)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 331 of 526 rej09b0060-0300 17.5.5 simultaneous serial data transmission and reception figure 17.14 shows a samp le flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to si multaneous transmit and receive mode, after checking that the sci3 has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 wi th a single instruction. to switch from receive mode to simultaneous transmit and receive mode , after checking that the sci3 has finished reception, clear re to 0. then after checking th at the rdrf and receive error flags (oer, fer, and per) are cleared to 0, simultaneously se t te and re to 1 with a single instruction. yes no start transmission/reception [3] error processing [4] yes no [1] read tdre flag in ssr write transmit data to tdr read oer flag in ssr read rdrf flag in ssr no yes tdre = 1 oer = 1 rdrf = 1 read receive data in rdr clear te and re bits in scr to 0 all data received? no yes [2] [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. transmission/reception cannot be resumed if the oer flag is set to 1. for overrun error processing, see figure 17.13. figure 17.14 sample flowchart of simultaneo us serial transmit and receive operations (clocked synchronous mode)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 332 of 526 rej09b0060-0300 17.6 multiprocessor communication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor commun ication is performed, each receiving st ation is addressed by a unique id code. the serial communication cy cle consists of two component cy cles; an id transmission cycle that specifies the receiving station, and a data transmission cycl e. the multiprocessor bit is used to differentiate between the id tr ansmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 17.15 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with wh ich it wants to perform serial co mmunication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bit is received, the r eceiving station compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose ids do not match continue to skip data until data w ith a 1 multiprocessor b it is again received. the sci3 uses the mpie bit in scr3 to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer, to 1, are inhibited until data with a 1 multi processor bit is received. on reception of a receive character w ith a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor form at is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 333 of 526 rej09b0060-0300 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa [legend] mpb: multiprocessor bit figure 17.15 example of in ter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 334 of 526 rej09b0060-0300 17.6.1 multiprocessor seri al data transmission figure 17.16 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci3 operations are the same as those in asynchronous mode. no yes start transmission read tdre flag in ssr [1] set mpbt bit in ssr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? write transmit data to tdr [1] read ssr and check that the tdre flag is set to 1, set the mpbt bit in ssr to 0 or 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [3] to output a break in serial transmission, set the port pcr to 1, clear pdr to 0, then clear the te bit in scr3 to 0. figure 17.16 sample multiprocessor serial tr ansmission flowchart
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 335 of 526 rej09b0060-0300 17.6.2 multiprocessor s erial data reception figure 17.17 shows a sample flowchart for multipro cessor serial data reception. if the mpie bit in scr3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the r eceive data is transferred to rd r. an rxi interrupt request is generated at this time. all other sci3 operations are the same as those in asynchronous mode. figure 17.18 shows an example of sci3 oper ation for multiprocesso r format reception. yes no start reception no yes [4] clear re bit in scr3 to 0 error processing (continued on next page) [5] yes no fer+oer = 1 rdrf = 1 all data received? set mpie bit in scr3 to 1 [1] [2] read oer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes [a] this station's id? read oer and fer flags in ssr yes no read rdrf flag in ssr no yes fer+oer = 1 read receive data in rdr rdrf = 1 [1] set the mpie bit in scr3 to 1. [2] read oer and fer in ssr to check for errors. receive error processing is performed in cases where a receive error occurs. [3] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station?s id. if the data is not this station?s id, set the mpie bit to 1 again. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] read ssr and check that the rdrf flag is set to 1, then read the data in rdr. [5] if a receive error occurs, read the oer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. figure 17.17 sample multiprocessor serial reception flowchart (1)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 336 of 526 rej09b0060-0300 error processing yes no clear oer, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing oer = 1 fer = 1 break? [5] [a] figure 17.17 sample multiprocessor serial reception flowchart (2)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 337 of 526 rej09b0060-0300 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request is not generated, and rdr retains its state rdr data read when data is not this station's id, mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request rdrf flag cleared to 0 rdr data read when data is this station's id, reception is continued rdr data read mpie set to 1 again figure 17.18 example of sci3 r eception using multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit)
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 338 of 526 rej09b0060-0300 17.7 interrupt requests sci3 creates the following six interrupt requests: transmission end, transm it data empty, receive data full, and receive errors (ove rrun error, framing error, and pa rity error). table 17.7 shows the interrupt sources. table 17.7 sci3 interrupt requests interrupt requests abbreviation interrupt sources receive data full rxi setting rdrf in ssr transmit data empty txi setting tdre in ssr transmission end tei setting tend in ssr receive error eri setting oer, fer, and per in ssr the initial value of the tdre flag in ssr is 1. thus, when the tie bit in scr3 is set to 1 before transferring the transmit data to tdr, a txi interr upt request is generated even if the transmit data is not ready. the initial value of the tend flag in ssr is 1. thus, when the teie bit in scr3 is set to 1 before transferring the transmit data to tdr, a tei interrupt request is generated even if the transmit data has not been sent. it is possib le to make use of the most of these interrupt requests efficiently by transferring the transmit da ta to tdr in the interrupt routine. to prevent the generation of these interrupt requests (txi an d tei), set the enable bits (tie and teie) that correspond to these in terrupt requests to 1, after transf erring the transmit data to tdr.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 339 of 526 rej09b0060-0300 17.8 usage notes 17.8.1 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, setting the fer flag, and possibly the per flag. note that as the sci3 continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 17.8.2 mark state and break sending when te is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by pcr and pdr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both pcr and pdr to 1. as te is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set pcr to 1 and clear pdr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. 17.8.3 receive error flags and transmit op erations (clocked synchronous mode only) transmission cannot be started when a receive error flag (oer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flag s to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0.
section 17 serial communication interface 3 (sci3) rev. 3.00 mar. 15, 2006 page 340 of 526 rej09b0060-0300 17.8.4 receive data sampling timing and recept ion margin in asynchronous mode in asynchronous mode, the sci3 operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 17 .19. thus, the reception margin in asynchronous mode is given by formula (1) below. m = (0.5 ? ) ? ? (l ? 0.5) f 100(%) ? ? ? ? ? ? 1 2n d ? 0.5 n ... formula (1) [legend] n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute va lue of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 17.19 receive data sampling timing in asynchronous mode
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 341 of 526 rej09b0060-0300 section 18 i 2 c bus interface 2 (iic2) the i 2 c bus interface 2 conforms to and pr ovides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register co nfiguration that controls the i 2 c bus differs partly from the philips configuration, however. figure 18.1 shows a block diagram of the i 2 c bus interface 2. figure 18.2 shows an example of i/o pin connections to external circuits. 18.1 features ? ? ? ? ? ? ? ? ?
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 342 of 526 rej09b0060-0300 scl iccr1 transfer clock generation circuit address comparator interrupt generator interrupt request bus state decision circuit arbitration decision circuit noise canceler noise canceler output control output control transmission/ reception control circuit iccr2 icmr icsr icier icdrr icdrs icdrt i 2 c bus control register 1 i 2 c bus control register 2 i 2 c bus mode register i 2 c bus status register i 2 c bus interrupt enable register i 2 c bus transmit data register i 2 c bus receive data register i 2 c bus shift register slave address register [legend] iccr1: iccr2: icmr: icsr: icier: icdrt: icdrr: icdrs: sar: sar sda internal data bus figure 18.1 block diagram of i 2 c bus interface 2
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 343 of 526 rej09b0060-0300 vcc vcc scl in scl out scl sda in sda out sda scl (master) (slave 1) (slave 2) sda scl in scl out scl sda in sda out sda scl in scl out scl sda in sda out sda figure 18.2 external circu it connections of i/o pins 18.2 input/output pins table 18.1 summarizes the input/output pins used by the i 2 c bus interface 2. table 18.1 pin configuration name abbreviation i/o function serial clock scl i/o iic se rial clock input/output serial data sda i/o iic serial data input/output
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 344 of 526 rej09b0060-0300 18.3 register descriptions the i 2 c bus interface 2 has the following registers. ? ? ? ? ? ? ? ? ? 18.3.1 i 2 c bus control register 1 (iccr1) iccr1 enables or disables the i 2 c bus interface 2, controls transm ission or reception, and selects master or slave mode, transmission or reception , and transfer clock frequ ency in master mode. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is halted. (scl and sda pins are set to port function.) 1: this bit is enabled for transfer operations. (scl and sda pins are bus drive state.) 6 rcvd 0 r/w reception disable this bit enables or disables the next operation when trs is 0 and icdrr is read. 0: enables next reception 1: disables next reception
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 345 of 526 rej09b0060-0300 bit bit name initial value r/w description 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. modification of the trs bit should be made between transfer frames. after data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to sar and the eighth bit is 1, trs is automatically set to 1. if an overrun error occurs in master mode with the clock synchronous serial format, mst is cleared to 0 and slave receive mode is entered. operating modes are described below according to mst and trs combination. when clocked synchronous serial format is selected and mst is 1, clock is output. 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w transfer clock select 3 to 0 these bits should be set according to the necessary transfer rate (see table 18.2) in master mode. in slave mode, these bits are used fo r reservation of the setup time in transmit mode. the time is 10 t cyc when cks3 = 0 and 20 t cyc when cks3 = 1.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 346 of 526 rej09b0060-0300 table 18.2 transfer rate bit 3 bit 2 bit 1 bit 0 transfer rate cks3 cks2 cks1 cks0 clock =5 mhz =8 mhz =10 mhz =16 mhz =20 mhz 0 /28 179 khz 286 khz 357 khz 571 khz 714 khz 0 1 /40 125 khz 200 khz 250 khz 400 khz 500 khz 0 /48 104 khz 167 khz 208 khz 333 khz 417 khz 0 1 1 /64 78.1 khz 125 khz 156 khz 250 khz 313 khz 0 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 0 1 /100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 0 /112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 0 1 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 0 /56 89.3 khz 143 khz 179 khz 286 khz 357 khz 0 1 /80 62.5 khz 100 khz 125 khz 200 khz 250 khz 0 /96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 0 1 1 /128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 0 /160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 0 1 /200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 0 /224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 1 1 1 /256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 347 of 526 rej09b0060-0300 18.3.2 i 2 c bus control register 2 (iccr2) iccr2 issues start/stop conditions, manipulates the sda pin, monitors the scl pin, and controls reset in the control part of the i 2 c bus interface 2. bit bit name initial value r/w description 7 bbsy 0 r/w bus busy this bit enables to confirm whether the i 2 c bus is occupied or released and to issue start/stop conditions in master mode. with the clocked synchronous serial format, this bit has no meaning. with the i 2 c bus format, this bit is set to 1 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. this bit is cleared to 0 when the sda level changes from low to high under the condition of scl = high, assuming that the stop condition has been issued. write 1 to bbsy and 0 to scp to issue a start condition. follow this procedure when also re-transmitting a start condition. write 0 in bbsy and 0 in scp to issue a stop condition. to issue start/stop conditions , use the mov instruction. 6 scp 1 w start/stop issue condition disable the scp bit controls the iss ue of start/stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. 5 sdao 1 r/w sda output value control this bit is used with sdaop when modifying output level of sda. this bit should not be manipulated during transfer. 0: when reading, sda pin outputs low. when writing, sda pin is changed to output low. 1: when reading, sda pin outputs high. when writing, sda pin is changed to output hi-z (outputs high by external pull-up resistance).
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 348 of 526 rej09b0060-0300 bit bit name initial value r/w description 4 sdaop 1 r/w sdao write protect this bit controls change of output level of the sda pin by modifying the sdao bit. to change the output level, clear sdao and sdaop to 0 or set sdao to 1 and clear sdaop to 0 by the mov instruction. this bit is always read as 1. 3 sclo 1 r this bit monitors sc l output level. when sclo is 1, scl pin outputs high. when sclo is 0, scl pin outputs low. 2 ? 1 ? reserved this bit is always read as 1. 1 iicrst 0 r/w iic control part reset this bit resets the control part except for i 2 c registers. if this bit is set to 1 when hang-up occurs because of communication failure during i 2 c operation, i 2 c control part can be reset without setting ports and initializing registers. 0 ? 1 ? reserved this bit is always read as 1. 18.3.3 i 2 c bus mode register (icmr) icmr selects whether the msb or lsb is transferre d first, performs master mode wait control, and selects the tran sfer bit count. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 349 of 526 rej09b0060-0300 bit bit name initial value r/w description 6 wait 0 r/w wait insertion bit in master mode with the i 2 c bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. when wait is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the setting of this bit is invalid in slave mode with the i 2 c bus format or with the clocked synchronous serial format. 5 4 ? ? 1 1 ? ? reserved these bits are always read as 1. 3 bcwp 1 r/w bc write protect this bit controls the bc2 to bc0 modifications. when modifying bc2 to bc0, this bit should be cleared to 0 and use the mov instruction. in clock synchronous serial mode, bc should not be modified. 0: when writing, values of bc2 to bc0 are set. 1: when reading, 1 is always read. when writing, settings of bc2 to bc0 are invalid. 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. when read, the remaining number of transfer bits is indicated. with the i 2 c bus format, the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl pin is low. the value returns to 000 at the end of a data transfer, including the acknowledge bit. with the clock synchronous serial format, these bits should not be modified. i 2 c bus format clock synchronous serial format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bits 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 350 of 526 rej09b0060-0300 18.3.4 i 2 c bus interrupt enable register (icier) icier enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms ackn owledge bits to be received. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when the tdre bit in icsr is set to 1, this bit enables or disables the transmit data empty interrupt (txi). 0: transmit data empty interrupt request (txi) is disabled. 1: transmit data empty interrupt request (txi) is enabled. 6 teie 0 r/w transmit end interrupt enable this bit enables or disables the transmit end interrupt (tei) at the rising of the ni nth clock while the tdre bit in icsr is 1. tei can be canceled by clearing the tend bit or the teie bit to 0. 0: transmit end interrupt request (tei) is disabled. 1: transmit end interrupt request (tei) is enabled. 5 rie 0 r/w receive interrupt enable this bit enables or disables the receive data full interrupt request (rxi) and the overrun error interrupt request (eri) with the clocked synchronous format, when a receive data is transferred from icdrs to icdrr and the rdrf bit in icsr is set to 1. rxi can be canceled by clearing the rdrf or rie bit to 0. 0: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clocked synchronous format are disabled. 1: receive data full interrupt request (rxi) and overrun error interrupt request (eri) with the clocked synchronous format are enabled.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 351 of 526 rej09b0060-0300 bit bit name initial value r/w description 4 nakie 0 r/w nack receive interrupt enable this bit enables or disables the nack receive interrupt request (naki) and the overrun error (setting of the ove bit in icsr) interrupt request (eri) with the clocked synchronous format, when the nackf and al bits in icsr are set to 1. naki can be canceled by clearing the nackf, ove, or nakie bit to 0. 0: nack receive interrupt request (naki) is disabled. 1: nack receive interrupt request (naki) is enabled. 3 stie 0 r/w stop condition detection interrupt enable 0: stop condition detection interrupt request (stpi) is disabled. 1: stop condition detection interrupt request (stpi) is enabled. 2 acke 0 r/w acknowledge bit judgement select 0: the value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: if the receive acknowledge bit is 1, continuous transfer is halted. 1 ackbr 0 r receive acknowledge in transmit mode, this bit stores the acknowledge data that are returned by the receive device. this bit cannot be modified. 0: receive acknowledge = 0 1: receive acknowledge = 1 0 ackbt 0 r/w transmit acknowledge in receive mode, this bit spec ifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 352 of 526 rej09b0060-0300 18.3.5 i 2 c bus status register (icsr) icsr performs confirmation of interrupt request flags and status. bit bit name initial value r/w description 7 tdre 0 r/w transmit data register empty [setting conditions] ? when data is transferred from icdrt to icdrs and icdrt becomes empty ? when trs is set ? when a start condition (including re-transfer) has been issued ? when transmit mode is entered from receive mode in slave mode [clearing conditions] ? when 0 is written in tdre after reading tdre = 1 ? when data is written to icdrt with an instruction 6 tend 0 r/w transmit end [setting conditions] ? when the ninth clock of scl rises with the i 2 c bus format while the tdre flag is 1 ? when the final bit of transmit frame is sent with the clock synchronous serial format [clearing conditions] ? when 0 is written in tend after reading tend = 1 ? when data is written to icdrt with an instruction 5 rdrf 0 r/w receive data register full [setting condition] ? when a receive data is transferred from icdrs to icdrr [clearing conditions] ? when 0 is written in rdrf after reading rdrf = 1 ? when icdrr is read with an instruction
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 353 of 526 rej09b0060-0300 bit bit name initial value r/w description 4 nackf 0 r/w no acknowledge detection flag [setting condition] ? when no acknowledge is detected from the receive device in transmission while the acke bit in icier is 1 [clearing condition] ? when 0 is written in nackf after reading nackf = 1 3 stop 0 r/w stop condition detection flag [setting conditions] ? in master mode, when a stop condition is detected after frame transfer ? in slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in sar [clearing condition] ? when 0 is written in stop after reading stop = 1
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 354 of 526 rej09b0060-0300 bit bit name initial value r/w description 2 al/ove 0 r/w arbitration lost flag/overrun error flag this flag indicates that arbitration was lost in master mode with the i 2 c bus format and that the final bit has been received while rdrf = 1 with the clocked synchronous format. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? when the sda pin outputs high in master mode while a start condition is detected ? when the final bit is received with the clocked synchronous format while rdrf = 1 [clearing condition] ? when 0 is written in al/ove after reading al/ove=1 1 aas 0 r/w slave addr ess recognition flag in slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar. [setting conditions] ? when the slave address is detected in slave receive mode ? when the general call address is detected in slave receive mode. [clearing condition] ? when 0 is written in aas after reading aas=1
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 355 of 526 rej09b0060-0300 bit bit name initial value r/w description 0 adz 0 r/w general call address recognition flag this bit is valid in i 2 c bus format slave receive mode. [setting condition] ? when the general call address is detected in slave receive mode [clearing condition] ? when 0 is written in adz after reading adz=1 18.3.6 slave address register (sar) sar selects the communica tion format and sets the slave address. when the chip is in slave mode with the i 2 c bus format, if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the ch ip operates as the slave device. bit bit name initial value r/w description 7 to 1 sva6 to sva0 all 0 r/w slave address 6 to 0 these bits set a unique address in bits sva6 to sva0, differing form the addresses of other slave devices connected to the i 2 c bus. 0 fs 0 r/w format select 0: i 2 c bus format is selected. 1: clocked synchronous seri al format is selected.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 356 of 526 rej09b0060-0300 18.3.7 i 2 c bus transmit data register (icdrt) icdrt is an 8-bit readable/writable register that stores the transmit data. when icdrt detects the space in the shift register (icdrs), it transfers th e transmit data which is written in icdrt to icdrs and starts transferring data. if the next transfer data is written to icdrt during transferring data of icdrs, conti nuous transfer is possible. if the mls bit of icmr is set to 1 and when the data is written to icdrt, the msb/ls b inverted data is read. the initial value of icdrt is h'ff. 18.3.8 i 2 c bus receive data register (icdrr) icdrr is an 8-bit register that stores the receiv e data. when data of one byte is received, icdrr transfers the receive data from icdrs to icdrr and the next data can be received. icdrr is a receive-only register, therefore the cpu cannot write to this register . the initial value of icdrr is h'ff. 18.3.9 i 2 c bus shift register (icdrs) icdrs is a register that is used to transfer/receive data. in transm ission, data is transferred from icdrt to icdrs and the data is sent from the sda pin. in reception, data is transferred from icdrs to icdrr after data of one byte is received. this register cannot be read directly from the cpu.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 357 of 526 rej09b0060-0300 18.4 operation the i 2 c bus interface can communicate either in i 2 c bus mode or clocked synchronous serial mode by setting fs in sar. 18.4.1 i 2 c bus format figure 18.3 shows the i 2 c bus formats. figure 18.4 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits. s sla r/ w a data a a/ a p 1111 n 7 1 m (a) i 2 c bus format (fs = 0) (b) i 2 c bus format (start condition retransmission, fs = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 111n1 7 1 m1 s sla r/ w a data a/ a p 111n2 7 1 m2 11 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 18.3 i 2 c bus formats sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a figure 18.4 i 2 c bus timing
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 358 of 526 rej09b0060-0300 [legend] s: start condition. the master device drives sda from high to low while scl is high. sla: slave address r/w: indicates the direction of data transfer: from the slave dev ice to the master device when r/w is 1, or from the master device to the slave device when r/w is 0. a: acknowledge. the receive device drives sda to low. data: transfer data p: stop condition. the master device drives sda from low to high while scl is high. 18.4.2 master transmit operation in master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for master transmit mode operation timing, see figures 18.5 and 18.6. the transmission procedure and operations in master transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. read the bbsy flag in iccr2 to confirm that the bus is free. set the mst and trs bits in iccr1 to select master transmit mode. then , write 1 to bbsy and 0 to scp using mov instruction. (start condition issued) this generates the start condition. 3. after confirming that tdre in icsr has been set, write the transmit data (the first byte data show the slave address and r/ w ) to icdrt. at this time, tdre is automatically cleared to 0, and data is transferred from icdrt to icdrs. tdre is set again. 4. when transmission of one byte data is comple ted while tdre is 1, tend in icsr is set to 1 at the rise of the 9th transmit clock pulse. read the ackbr bit in icier, and confirm that the slave device has been selected. then, write second byte data to icdrt. when ackbr is 1, the slave device has not been acknowledged, so issue the stop condition. to issue the stop condition, write 0 to bbsy and scp using mov instruction. scl is fixed low until the transmit data is prepared or the stop condition is issued. 5. the transmit data after the second byte is written to icdrt every time tdre is set. 6. write the number of bytes to be transmitted to icdrt. wait until tend is set (the end of last byte data transmission) while tdre is 1, or wait for nack (nackf in icsr = 1) from the receive device while acke in icier is 1. then , issue the stop condition to clear tend or nackf. 7. when the stop bit in icsr is set to 1, the operation returns to the slave receive mode.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 359 of 526 rej09b0060-0300 tdre scl (master output) sda (master output) sda (slave output) tend [5] write data to icdrt (third byte) icdrt icdrs [2] instruction of start condition issuance [3] write data to icdrt (first byte) [4] write data to icdrt (second byte) user processing 1 bit 7 slave address address + r/ w data 1 data 1 data 2 address + r/ w bit 6 bit 7 bit 6 bit 5bit 4bit 3bit 2bit 1bit 0 212 3456789 a r/ w figure 18.5 master transmit mode operation timing (1) tdre [6] issue stop condition. clear tend. [7] set slave receive mode tend icdrt icdrs 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 data n data n bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [5] write data to icdrt user processing figure 18.6 master transmit mode operation timing (2)
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 360 of 526 rej09b0060-0300 18.4.3 master receive operation in master receive mode, the master device outputs th e receive clock, receives data from the slave device, and returns an acknowledge signal. for ma ster receive mode operation timing, see figures 18.7 and 18.8. the reception procedure and operatio ns in master receive mode are shown below. 1. clear the tend bit in icsr to 0, then clear the trs bit in iccr1 to 0 to switch from master transmit mode to master receive mode . then, clear the tdre bit to 0. 2. when icdrr is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. the master device outputs the level specified by ackbt in icier to sda, at the 9th receive clock pulse. 3. after the reception of first frame data is complete d, the rdrf bit in icst is set to 1 at the rise of 9th receive clock pulse. at this time, the r eceive data is read by reading icdrr, and rdrf is cleared to 0. 4. the continuous reception is performed by reading icdrr every time rdrf is set. if 8th receive clock pulse falls after reading icdrr by the other processing while rdrf is 1, scl is fixed low until icdrr is read. 5. if next frame is the last receive data, set th e rcvd bit in iccr1 to 1 before reading icdrr. this enables the issuance of the stop condition after the next reception. 6. when the rdrf bit is set to 1 at rise of th e 9th receive clock pulse, issue the stage condition. 7. when the stop bit in icsr is set to 1, read icdrr. then clear the rcvd bit to 0. 8. the operation returns to the slave receive mode.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 361 of 526 rej09b0060-0300 tdre tend icdrs icdrr [1] clear tdre after clearing tend and trs [2] read icdrr (dummy read) [3] read icdrr 1 a 21 3456789 9 a trs rdrf scl (master output) sda (master output) sda (slave output) bit 7 master transmit mode master receive mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing data 1 data 1 figure 18.7 master receive mode operation timing (1)
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 362 of 526 rej09b0060-0300 rdrf rcvd icdrs icdrr data n-1 data n data n data n-1 [5] read icdrr after setting rcvd [6] issue stop condition [7] read icdrr, and clear rcvd [8] set slave receive mode 1 9 23456789 aa/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing figure 18.8 master receive mode operation timing (2) 18.4.4 slave transmit operation in slave transmit mode, the slave device outputs th e transmit data, while the master device outputs the receive clock and returns an acknowledge sign al. for slave transmit mode operation timing, see figures 18.9 and 18.10. the transmission procedure and operations in slave transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ac kbt in icier to sda, at the rise of the 9th clock pulse. at this time, if the 8th bit data (r/ w ) is 1, the trs and icsr bits in iccr1 are set to 1, and the mode changes to slave transmit mode automatically. the continuous transmission is performed by writing transmit data to icdrt every time tdre is set. 3. if tdre is set after writing last transmit data to icdrt, wait until tend in icsr is set to 1, with tdre = 1. when tend is set, clear tend. 4. clear trs for the end processing, and read icdrr (dummy read). scl is free. 5. clear tdre.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 363 of 526 rej09b0060-0300 tdre tend icdrs icdrr 1 a 21 3456789 9 a trs icdrt scl (master output) slave receive mode slave transmit mode sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 data 1 data 1 data 2 data 3 data 2 bit 6bit 5bit 4bit 3bit 2bit 1bit 0 [2] write data to icdrt (data 1) [2] write data to icdrt (data 2) [2] write data to icdrt (data 3) user processing figure 18.9 slave transmit mode operation timing (1)
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 364 of 526 rej09b0060-0300 tdre data n tend icdrs icdrr 1 9 23456789 trs icdrt a scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 slave transmit mode slave receive mode bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a [3] clear tend [5] clear tdre [4] read icdrr (dummy read) after clearing trs user processing figure 18.10 slave transmit mode operation timing (2) 18.4.5 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for slave receive mode operation timing, see figures 18.11 and 18.12. the reception procedure and operations in slav e receive mode are described below. 1. set the ice bit in iccr1 to 1. set the mls and wait bits in icmr and the cks3 to cks0 bits in iccr1 to 1. (initial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ac kbt in icier to sda, at the rise of the 9th clock pulse. at the same time, rdrf in icsr is set to read icdrr (d ummy read). (since the read data show the slave address and r/ w , it is not used.) 3. read icdrr every time rdrf is set. if 8th r eceive clock pulse falls while rdrf is 1, scl is fixed low until icdrr is read. the change of the acknowledge before reading icdrr, to be returned to the master device, is re flected to the next transmit frame.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 365 of 526 rej09b0060-0300 4. the last byte data is read by reading icdrr. icdrs icdrr 12 1 345678 9 9 a a rdrf data 1 data 2 data 1 scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] read icdrr (dummy read) [2] read icdrr user processing figure 18.11 slave receive mode operation timing (1) icdrs icdrr 12345678 9 9 a a rdrf scl (master output) sda (master output) sda (slave output) scl (slave output) user processing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data 1 [3] set ackbt [3] read icdrr [4] read icdrr data 2 data 1 figure 18.12 slave receive mode operation timing (2)
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 366 of 526 rej09b0060-0300 18.4.6 clocked synchronous serial format this module can be operated with the clocked synchronous serial format, by setting the fs bit in sar to 1. when the mst bit in iccr1 is 1, the transfer clock output from scl is selected. when mst is 0, the external clock input is selected. data transfer format figure 18.13 shows the clocked synchronous serial transfer format. the transfer data is output from the rise to the fa ll of the scl clock, and the data at the rising edge of the scl clock is guaranteed. the mls bit in icmr sets the order of data transfer, in either the msb first or lsb first. the output level of sda can be changed during the transfer wait, by the sdao bit in iccr2. sda bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 scl figure 18.13 clocked synchronous serial transfer format transmit operation in transmit mode, transmit data is output from sda, in synchronization with the fall of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for transmit mode operation timing, see figure 18.14. the transmission proced ure and operations in transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. set the trs bit in iccr1 to select the transmit mode. then, tdre in icsr is set. 3. confirm that tdre has been set. then, write the transmit data to icdrt. the data is transferred from icdrt to icdrs, and td re is set automatically. the continuous transmission is performed by writing data to icdrt every time tdre is set. when changing from transmit mode to receive mode, clear trs while tdre is 1.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 367 of 526 rej09b0060-0300 12 781 78 1 scl trs bit 0 data 1 data 1 data 2 data 3 data 2 data 3 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 sda (output) tdre icdrt icdrs user processing [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [3] write data to icdrt [2] set trs figure 18.14 transmit mode operation timing receive operation in receive mode, data is latched at the rise of the transfer clock. the transfer clock is output when mst in iccr1 is 1, and is input when mst is 0. for receive mode operation timing, see figure 18.15. the reception procedure and operatio ns in receive mode are described below. 1. set the ice bit in iccr1 to 1. set the mst and cks3 to cks0 bits in iccr1 to 1. (initial setting) 2. when the transfer clock is output, set mst to 1 to start outputting the receive clock. 3. when the receive operation is completed, da ta is transferred from icdrs to icdrr and rdrf in icsr is set. when mst = 1, the ne xt byte can be received, so the clock is continually output. the continuous reception is performed by reading icdrr every time rdrf is set. when the 8th clock is risen wh ile rdrf is 1, the overrun is detected and al/ove in icsr is set. at this time, the pr evious reception data is retained in icdrr. 4. to stop receiving when mst = 1, set rcvd in iccr1 to 1, then read icdrr. then, scl is fixed high after receiving the next byte data.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 368 of 526 rej09b0060-0300 12 781 7812 scl mst trs rdrf icdrs icdrr sda (input) bit 0 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 bit 1 user processing data 1 data 1 data 2 data 2 data 3 [2] set mst (when outputting the clock) [3] read icdrr [3] read icdrr figure 18.15 receive mode operation timing 18.4.7 noise canceller the logic levels at the scl and sda pins are routed through noise cancellers before being latched internally. figure 18.16 shows a block diagram of the noise canceller circuit. the noise canceller consists of two cascaded la tches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. c q d march detector internal scl or sda signal scl or sda input signal sampling clock sampling clock system clock period latch latch c q d figure 18.16 block diag ram of noise canceller
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 369 of 526 rej09b0060-0300 18.4.8 example of use flowcharts in respective modes that use the i 2 c bus interface are shown in figures 18.17 to 18.20. bbsy=0 ? no tend=1 ? no yes start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] initialize set mst and trs in iccr1 to 1. write 1 to bbsy and 0 to scp. write transmit data in icdrt write 0 to bbsy and scp set mst to 1 and trs to 0 in iccr1 read bbsy in iccr2 read tend in icsr read ackbr in icier mater receive mode yes ackbr=0 ? write transmit data in icdrt read tdre in icsr read tend in icsr clear tend in icsr read stop in icsr clear tdre in icsr end write transmit data in icdrt transmit mode? no yes tdre=1 ? last byte? stop=1 ? no no no no no yes yes tend=1 ? yes yes yes [1] test the status of the scl and sda lines. [2] set master transmit mode. [3] issue the start candition. [4] set the first byte (slave address + r/ w ) of transmit data. [5] wait for 1 byte to be transmitted. [6] test the acknowledge transferred from the specified slave device. [7] set the second and subsequent bytes (except for the final byte) of transmit data. [8] wait for icdrt empty. [9] set the last byte of transmit data. [10] wait for last byte to be transmitted. [11] clear the tend flag. [12] clear the stop flag. [13] issue the stop condition. [14] wait for the creation of stop condition. [15] set slave receive mode. clear tdre. [12] clear stop in icsr figure 18.17 sample flowch art for master transmit mode
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 370 of 526 rej09b0060-0300 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? mater receive mode clear tend in icsr clear trs in iccr1 to 0 clear tdre in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 set rcvd in iccr1 to 1 read icdrr read rdrf in icsr write 0 to bbsy and scp read stop in icsr read icdrr clear rcvd in iccr1 to 0 clear mst in iccr1 to 0 note: do not activate an interrupt during the execution of steps [1] to [3]. end no yes stop=1 ? no yes [1] clear tend, select master receive mode, and then clear tdre. * [2] set acknowledge to the transmit device. * [3] dummy-read icddr. * [4] wait for 1 byte to be received [5] check whether it is the (last receive - 1). [6] read the receive data last. [7] set acknowledge of the final byte. disable continuous reception (rcvd = 1). [8] read the (final byte - 1) of receive data. [9] wait for the last byte to be receive. [10] clear the stop flag. [11] issue the stop condition. [12] wait for the creation of stop condition. [13] read the last byte of receive data. [14] clear rcvd. [15] set slave receive mode. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] clear stop in icsr. [10] [14] [15] supplementary explanation: when one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. the step [8] is dummy-read in icdrr. figure 18.18 sample flowch art for master receive mode
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 371 of 526 rej09b0060-0300 tdre=1 ? yes yes no slave transmit mode clear aas in icsr write transmit data in icdrt read tdre in icsr last byte? write transmit data in icdrt read tend in icsr clear tend in icsr clear trs in iccr1 to 0 dummy read icdrr clear tdre in icsr end [1] clear the aas flag. [2] set transmit data for icdrt (except for the last data). [3] wait for icdrt empty. [4] set the last byte of transmit data. [5] wait for the last byte to be transmitted. [6] clear the tend flag . [7] set slave receive mode. [8] dummy-read icdrr to release the scl line. [9] clear the tdre flag. no no yes tend=1 ? [1] [2] [3] [4] [5] [6] [7] [8] [9] figure 18.19 sample flowchart for slave transmit mode
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 372 of 526 rej09b0060-0300 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? slave receive mode clear aas in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 read icdrr read rdrf in icsr read icdrr end no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] clear the aas flag. [2] set acknowledge to the transmit device. [3] dummy-read icdrr. [4] wait for 1 byte to be received. [5] check whether it is the (last receive - 1). [6] read the receive data. [7] set acknowledge of the last byte. [8] read the (last byte - 1) of receive data. [9] wait the last byte to be received. [10] read for the last byte of receive data. supplementary explanation: when one byte is received, steps [2] to [6] are skipped after step [1], before jumping to step [7]. the step [8] is dummy-read in icdrr. figure 18.20 sample flowch art for slave receive mode
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 373 of 526 rej09b0060-0300 18.5 interrupts there are six interrupt requ ests in this module; transmit data em pty, transmit end, receive data full, nack receive, stop recogn ition, and arbitration lost/overrun error. table 18.3 shows the contents of each interrupt request. table 18.3 interrupt requests interrupt request abbreviation interrupt condition i 2 c mode clocked synchronous mode transmit data empty txi (tdre=1) ? (tie=1) { { transmit end tei (tend=1) ? (teie=1) { { receive data full rxi (rdrf=1) ? (rie=1) { { stop recognition stpi (stop=1) ? (stie=1) { nack receive { arbitration lost/overrun error naki {(nackf=1)+(al=1)} ? (nakie=1) { { when interrupt conditions described in table 18.3 are 1 and the i bit in ccr is 0, the cpu executes an interrupt exception pr ocessing. interrupt sources should be cleared in the exception processing. tdre and tend are automatically cl eared to 0 by writing the transmit data to icdrt. rdrf are automatically cl eared to 0 by readin g icdrr. tdre is set to 1 again at the same time when transmit data is written to icdrt. when tdre is cleared to 0, then an excessive data of one byte may be transmitted.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 374 of 526 rej09b0060-0300 18.6 bit synchronous circuit in master mode, this module has a possibility that high level period may be short in the two states described below. ? ? scl v ih scl monitor timing reference clock internal scl figure 18.21 timing of bit synchronous circuit table 18.4 time for monitoring scl cks3 cks2 time for monitoring scl 0 7.5 tcyc 0 1 19.5 tcyc 0 17.5 tcyc 1 1 41.5 tcyc
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 375 of 526 rej09b0060-0300 18.7 usage notes 18.7.1 issue (retransmission) of start/stop conditions in master mode, when the start/stop conditions ar e issued (retransmitted) at the specific timing under the following condition 1 or 2, such cond itions may not be output successfully. to avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. check the sclo bit in the i 2 c control register 2 (iicr2) to confirm the fall of the ninth clock. 1. when the rising of scl falls behind the time specified in section 18.6, bit synchronous circuit, by the load of the scl bus (l oad capacitance or pull-up resistance) 2. when the bit synchronous circuit is activated by extending the low period of eighth and ninth clocks, that is driven by the slave device 18.7.2 wait setting in i 2 c bus mode register (icmr) if the wait bit is set to 1, and the scl signal is dr iven low for two or more transfer clocks by the slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. to avoid this, set the wait bit in icmr to 0.
section 18 i 2 c bus interface 2 (iic2) rev. 3.00 mar. 15, 2006 page 376 of 526 rej09b0060-0300
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 377 of 526 rej09b0060-0300 section 19 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to eight analog input channels to be selected. the block diagram of the a/d converter is shown in figure 19.1. 19.1 features ? ? ? ? ? ? ? ?
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 378 of 526 rej09b0060-0300 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt bus interface successive approximations register analog multiplexer a d c s r a d c r a d d r d a d d r c a d d r b a d d r a a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d [legend] adcr: adcsr: addra: addrb: addrc: addrd: adtrg /4 /8 av cc an0 an1 an2 an3 an4 an5 an6 an7 figure 19.1 block di agram of a/d converter
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 379 of 526 rej09b0060-0300 19.2 input/output pins table 19.1 summarizes the input pins used by th e a/d converter. the 8 analog input pins are divided into two groups; analog input pins 0 to 3 (an0 to an3) comprising group 0, analog input pins 4 to 7 (an4 to an7) comprising group 1. the avcc pin is the power supply pin for the analog block in the a/d converter. table 19.1 pin configuration pin name abbreviation i/o function analog power supply pin av cc input analog block power supply analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 380 of 526 rej09b0060-0300 19.3 register descriptions the a/d converter has the following registers. ? ? ? ? ? ? 19.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which stor e a conversion result for each analog input channel, are shown in table 19.2. the converted 10-bit data is stored in bits 15 to 6. the lower 6 bits are always read as 0. the data bus width between the cpu and the a/d converter is 8 bits. the upper byte can be read directly from the cpu, however the lower byte should be read via a temporary register. the temporary register cont ents are transferred from the addr when the upper byte data is read. therefore, byte access to addr shou ld be done by reading the upp er byte first then the lower one. word access is also possible. addr is initialized to h'0000. table 19.2 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register to be stored results of a/d conversion an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 381 of 526 rej09b0060-0300 19.3.2 a/d control/status register (adcsr) adcsr consists of the control bits and conversion end status bits of the a/d converter. bit bit name initial value r/w description 7 adf 0 r/w a/d end flag [setting conditions] ? when a/d conversion ends in single mode ? when a/d conversion ends once on all the channels selected in scan mode [clearing condition] when 0 is written after reading adf = 1 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt request (adi) is enabled by adf when this bit is set to 1 5 adst 0 r/w a/d start setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. 0: single mode 1: scan mode 3 cks 0 r/w clock select selects the a/d conversions time. 0: conversion time = 134 states (max.) 1: conversion time = 70 states (max.) clear the adst bit to 0 before switching the conversion time.
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 382 of 526 rej09b0060-0300 bit bit name initial value r/w description 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w channel select 2 to 0 select analog input channels. when scan = 0 when scan = 1 000: an0 000: an0 001: an1 001: an0 and an1 010: an2 010: an0 to an2 011: an3 011: an0 to an3 100: an4 100: an4 101: an5 101: an4 and an5 110: an6 110: an4 to an6 111: an7 111: an4 to an7 19.3.3 a/d control register (adcr) adcr enables a/d conversion started by an external trigger signal.
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 383 of 526 rej09b0060-0300 bit bit name initial value r/w description 7 trge 0 r/w trigger enable a/d conversion is started at the falling edge and the rising edge of the external trigger signal ( adtrg ) when this bit is set to 1. the selection between the falling edge and rising edge of the external trigger pin ( adtrg ) conforms to the wpeg5 bit in the interrupt edge select register 2 (iegr2) 6 to 4 ? all 1 ? reserved these bits are always read as 1. 3, 2 ? all 0 r/w reserved although these bits are readable/writable, these bits should not be set to 1. 1 ? 1 ? reserved this bit is always read as 1. 0 ? 0 r/w reserved although this bit is readable/ writable, this bit should not be set to 1.
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 384 of 526 rej09b0060-0300 19.4 operation the a/d converter operates by successive appr oximation with 10-bit resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent in correct operation, first clear th e bit adst in adcsr to 0. the adst bit can be set at the same time as the opera ting mode or analog input channel is changed. 19.4.1 single mode in single mode, a/d conversion is performed once for the analog input of the specified single channel as follows: 1. a/d conversion is started when the adst bit in adcsr is set to 1, according to software or external trigger input. 2. when a/d conversion is completed, the result is transferred to the corresponding a/d data register of the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state. 19.4.2 scan mode in scan mode, a/d conversion is performed sequentially for the analog input of the specified channels (four channels maximum) as follows: 1. when the adst bit in adcsr is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0, an4 when ch2 = 1). 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt requested is generated. a/d conversion starts again on the firs t channel in the group. 4. the adst bit is not automatica lly cleared to 0. step s [2] and [3] are repeated as long as the adst bit remains set to 1. when the adst b it is cleared to 0, a/ d conversion stops.
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 385 of 526 rej09b0060-0300 19.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 19.2 shows the a/d conversion timing. table 19.3 shows the a/d conversion time. as indicated in figure 19.2, th e a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the wr ite access to adcsr. th e total conversion time therefore varies within the ranges indicated in table 19.3. in scan mode, the values given in table 19.3 apply to the first conversion time. in the second and subsequent conversions, the conversion time is 128 states (fixed) when cks = 0 and 66 states (fixed) when cks = 1. (1) (2) address write signal input sampling timing adf [legend] (1): (2): t d : t spl : t conv : adcsr write cycle adcsr address a/d conversion start delay time input sampling time a/d conversion time t conv t spl t d figure 19.2 a/d conversion timing
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 386 of 526 rej09b0060-0300 table 19.3 a/d conversio n time (single mode) cks = 0 cks = 1 item symbol min. typ. max. min. typ. max. a/d conversion start delay time t d 6 ? 9 4 ? 5 input sampling time t spl ? 31 ? ? 15 ? a/d conversion time t conv 131 ? 134 69 ? 70 note: all values represent the number of states. 19.4.4 external tr igger input timing a/d conversion can also be started by an external trigger input. when the trge bit in adcr is set to 1, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg input pin sets the adst bit in adcsr to 1, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 19.3 shows the timing. adtrg internal trigger signal adst a/d conversion figure 19.3 external trigger input timing
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 387 of 526 rej09b0060-0300 19.5 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? ? ? ? ? ?
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 388 of 526 rej09b0060-0300 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 3 8 4 8 5 8 figure 19.4 a/d conversio n accuracy definitions (1)
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 389 of 526 rej09b0060-0300 fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 19.4 a/d conversio n accuracy definitions (2)
section 19 a/d converter rev. 3.00 mar. 15, 2006 page 390 of 526 rej09b0060-0300 19.6 usage notes 19.6.1 permissible si gnal source impedance this lsi's analog input is designed such that conv ersion accuracy is guarant eed for an input signal for which the signal source impedance is 5 k ? ? ? 19.6.2 influences on absolute accuracy adding capacitance results in coupling with gn d, and therefore noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. 20 pf 10 k ? c in = 15 pf sensor output impedance up to 5 k ? this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 19.5 analog input circuit example
section 20 power-on reset and low-v oltage detection ci rcuits (optional) rev. 3.00 mar. 15, 2006 page 391 of 526 rej09b0060-0300 section 20 power-on reset and low-voltage detection circuits (optional) this lsi can include a power-on re set circuit and low-voltage detect ion circuit as optional circuits. the low-voltage detection circuit consists of two circuits: lvdi (interrupt by low voltage detect) and lvdr (reset by low voltage detect) circuits. this circuit is used to prevent abnormal opera tion (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operat ion. thus, system stability can be improved. if the power supply voltage falls more, the reset state is automatically entered. if the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. figure 20.1 is a block diagram of the power-on re set circuit and the low-vo ltage detection circuit. 20.1 features ? ?
section 20 power-on reset and low-v oltage detection ci rcuits (optional) rev. 3.00 mar. 15, 2006 page 392 of 526 rej09b0060-0300 c res pss: lvdcr: lvdsr: lvdres : lvdint : vreset: vint: prescaler s low-voltage-detection control register low-voltage-detection status register low-voltage-detection reset signal low-voltage-detection interrupt signal reset detection voltage power-supply fall/rise detection voltage [legend] res ck r pss r s q ovf vreset vcc vint lvdres lvdcr lvdsr lvdint reference voltage generator noise canceler noise canceler interrupt control circuit internal reset signal power-on reset circuit low-voltage detection circuit internal data bus ladder resistor + ? + ? interrupt request figure 20.1 block diagram of power-on reset circuit and low-voltage detection circuit
section 20 power-on reset and low-voltage detection circuits (optional) rev. 3.00 mar. 15, 2006 page 393 of 526 rej09b0060-0300 20.2 register descriptions the low-voltage detection circuit has the following registers. ? ? 20.2.1 low-voltage-detection control register (lvdcr) lvdcr is used to enable or disable the low-voltage detection circuit, set the detection levels for the lvdr function, enable or disable the lvdr function, and enable or disable generation of an interrupt when the power-supply voltage rises above or falls below the respective levels. table 20.1 shows the relationship between the lvdcr settings and select functions. lvdcr should be set according to table 20.1. bit bit name initial value r/w description 7 lvde 0 * r/w lvd enable 0: the low-voltage detection circuit is not used (in standby mode) 1: the low-voltage detection circuit is used 6 to 4 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 3 lvdsel 0 * r/w lvdr detection level select 0: reset detection voltage is 2.3 v (typ.) 1: reset detection voltage is 3.6 v (typ.) when the falling or rising voltage detection interrupt is used, reset detection voltage of 2.3 v (typ.) should be used. when only a reset detection interrupt is used, reset detection voltage of 3.6 v (typ.) should be used. 2 lvdre 0 * r/w lvdr enable 0: disables the lvdr function 1: enables the lvdr function
section 20 power-on reset and low-v oltage detection ci rcuits (optional) rev. 3.00 mar. 15, 2006 page 394 of 526 rej09b0060-0300 bit bit name initial value r/w description 1 lvdde 0 r/w voltage-fall-interrupt enable 0: interrupt on the power-supply voltage falling below the selected detection level disabled 1: interrupt on the power-supply voltage falling below the selected detection level enabled 0 lvdue 0 r/w voltage-rise-interrupt enable 0: interrupt on the power-supply voltage rising above the selected detection level disabled 1: interrupt on the power-supply voltage rising above the selected detection level enabled note: * not initialized by lvdr but initialized by a power-on reset or wdt reset. table 20.1 lvdcr setting s and select functions lvdcr settings select functions lvde lvdsel lvdre lvdde lvdue power-on reset lvdr low-voltage- detection falling interrupt low-voltage- detection rising interrupt 0 * * * * o ? ? ? 1 1 1 0 0 o o ? ? 1 0 0 1 0 o ? o ? 1 0 0 1 1 o ? o o 1 0 1 1 1 o o o o [legend] * means invalid.
section 20 power-on reset and low-voltage detection circuits (optional) rev. 3.00 mar. 15, 2006 page 395 of 526 rej09b0060-0300 20.2.2 low-voltage-detection status register (lvdsr) lvdsr indicates whether the power-supply voltage falls below or rises above the respective specified values. bit bit name initial value r/w description 7 to 2 ? all 1 ? reserved these bits are always read as 1, and cannot be modified. 1 lvddf 0 * r/w lvd power-supply voltage fall flag [setting condition] when the power-supply voltage falls below vint (d) (typ. = 3.7 v) [clearing condition] writing 0 to this bit after reading it as 1 0 lvduf 0 * r/w lvd power-supply voltage rise flag [setting condition] when the power supply voltage falls below vint (d) while the lvdue bit in lvdcr is set to 1, then rises above vint (u) (typ. = 4.0 v) before falling below vreset1 (typ. = 2.3 v) [clearing condition] writing 0 to this bit after reading it as 1 note: * initialized by lvdr.
section 20 power-on reset and low-v oltage detection ci rcuits (optional) rev. 3.00 mar. 15, 2006 page 396 of 526 rej09b0060-0300 20.3 operation 20.3.1 power-on reset circuit figure 20.2 shows the timing of the operation of the power-on reset circuit. as the power-supply voltage rises, the capacitor which is externally c onnected to the res pin is gradually charged via the on-chip pull-up resistor (typ. 150 k ? res pin is transmitted within the chip, the prescaler s and the entire chip are in their reset states. when the level on the res pin reaches the specified value, the pr escaler s is released from its re set state and it starts counting. the ovf signal is generated to release the intern al reset signal after the prescaler s has counted 131,072 clock ( res pin. to achieve stable operation of this lsi, the power supply needs to rise to its full level and settles within the specified time. the maximum time required for the power supply to rise and settle after power has been supplied (t pwon ) is determined by the oscillation frequency (f osc ) and capacitance which is connected to res pin (c res ). if t pwon means the time requ ired to reach 90 % t pwon (ms) 90 c res ( f) + 162/f osc (mhz) (t pwon 3000 ms, c res 0.22 f, and f osc = 10 in 2-mhz to 10-mhz operation) note that the power supply voltage (vcc) must fall below vpor = 100 mv and rise after charge on the res pin is removed. to remove charge on the res pin, it is recommended that the diode should be placed near vcc. if the power supply vo ltage (vcc) rises from the point above vpor, a power-on reset may not occur. res vcc pss-reset signal internal reset signal vss vss ovf 131,072 cycles pss counter starts reset released t pwon vpor figure 20.2 operational timi ng of power-on reset circuit
section 20 power-on reset and low-voltage detection circuits (optional) rev. 3.00 mar. 15, 2006 page 397 of 526 rej09b0060-0300 20.3.2 low-voltage detection circuit use this circuit in the system in which the power supply voltage vcc is between 4.5 and 5.5 v. if so, the contents described in the section of electrical characteristics are guaranteed. lvdr (reset by low voltage detect) circuit: figure 20.3 shows the timing of the lvdr function. the lvdr enters the module-standby state after a power-on reset is canceled. to operate the lvdr, set the lvde bit in lvdcr to 1, wait for 50 lvdres signal to 0, and resets the prescaler s. the low-voltage detection reset state remains in place until a power-on reset is generated. when the power-supply voltage rises above the vreset voltage again, the prescaler s starts counting. it counts 131,072 clock (
section 20 power-on reset and low-v oltage detection ci rcuits (optional) rev. 3.00 mar. 15, 2006 page 398 of 526 rej09b0060-0300 lvdres vcc vreset vss v lvdrmin ovf pss-reset signal internal reset signal 131,072 cycles pss counter starts reset released figure 20.3 operational timing of lvdr circuit lvdi (interrupt by low voltage detect) circuit: figure 20.4 shows the timing of lvdi functions. the lvdi enters the module-standby state after a power-on reset is canceled. to operate the lvdi, set the lvde bit in lvdcr to 1, wait for 50 lvdint signal to 0 and the lvddf bit in lvdsr is set to 1. if the lvdde bit is 1 at this time, an irq0 interrupt request is simultaneously generated. in this case, the necessary data must be saved in the external eeprom, etc, and a transition must be made to standby mode or subsleep mode. until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. when the power-supply voltage does not fall below vreset1 (typ. = 2.3 v) voltage but rises above vint (u) (typ. = 4.0 v) voltage, the lvdi sets the lvdint signal to 1. if the lvdue bit is 1 at this time, the lvduf bit in lvdsr is set to 1 an d an irq0 interrupt request is simultaneously generated.
section 20 power-on reset and low-voltage detection circuits (optional) rev. 3.00 mar. 15, 2006 page 399 of 526 rej09b0060-0300 if the power supply voltage (vcc) falls below vreset1 (typ. = 2.3 v) voltage, the lvdr function is performed. lvdint vcc vint (d) vint (u) vss lvddf lvdue lvduf irq0 interrupt generated irq0 interrupt generated lvdde vreset1 figure 20.4 operational timing of lvdi circuit procedures for clearing settin gs when using lvdr and lvdi: to operate or release the low-vo ltage detection circuit normally, follow the procedure described below. figure 20.5 shows the timing for the operation and release of the low-voltage detection circuit. 1. to operate the lo w-voltage detection circuit, set the lvde bit in lvdcr to 1. 2. wait for 50
section 20 power-on reset and low-v oltage detection ci rcuits (optional) rev. 3.00 mar. 15, 2006 page 400 of 526 rej09b0060-0300 lvdre lvdde lvdue t lvdon lvde figure 20.5 timing for operation/rel ease of low-voltage detection circuit
section 21 power supply circuit rev. 3.00 mar. 15, 2006 page 401 of 526 rej09b0060-0300 section 21 power supply circuit this lsi incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 3.0 v or above can be held down to virtually the same low level as when used at approxim ately 3.0 v. if the external power supply is 3.0 v or below, the internal voltage will be practically the same as th e external voltage. it is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit. 21.1 when using internal power supply step-down circuit connect the external po wer supply to the v cc pin, and connect a capacita nce of approximately 0.1 f between v cl and v ss , as shown in figure 21.1. the internal step-down circuit is made effective simply by adding this external circuit. in the ex ternal circuit interface, th e external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. the a/d converter analog power supply is not affected by the internal step-down circuit. v cl v ss internal logic step-down circuit internal power supply stabilization capacitance (approx. 0.1 f) v cc v cc = 3.0 to 5.5 v figure 21.1 power supply connection when internal step-down circuit is used
section 21 power supply circuit rev. 3.00 mar. 15, 2006 page 402 of 526 rej09b0060-0300 21.2 when not using internal power supply step-down circuit when the internal power supply step-down circuit is not used, connect the external power supply to the v cl pin and v cc pin, as shown in figure 21.2. the external power supply is then input directly to the internal power supply. the permissible range for the power supply voltage is 3.0 v to 3.6 v. operation cannot be guaranteed if a voltage outside this range (less than 3.0 v or more than 3.6 v) is input. v cl v ss internal logic step-down circuit internal power supply v cc v cc = 3.0 to 3.6 v figure 21.2 power supply connection when internal step-down circuit is not used
section 22 list of registers rev. 3.00 mar. 15, 2006 page 403 of 526 rej09b0060-0300 section 22 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? ? ? ? ? ? ? ? ? ? ? ? ?
section 22 list of registers rev. 3.00 mar. 15, 2006 page 404 of 526 rej09b0060-0300 22.1 register addresses (address order) the data-bus width column indicates the numb er of bits. the access-st ate column shows the number of states of the speci fied basic clock that is requ ired for access to the register. note: access to undefined or reserved addresse s is prohibited. correct operation of the access itself or later operations is not guaran teed when such a register is accessed. register name abbre- viation bit no. address module name data bus width access state ? ? ? h'fff000 to h'fff5ff ? ? ? serial mode register_3 smr_3 8 h'fff600 sci3_3 8 3 bit rate register_3 brr_3 8 h'fff601 sci3_3 8 3 serial control register 3 _3 scr3_3 8 h'fff602 sci3_3 8 3 transmit data register_3 tdr_3 8 h'fff603 sci3_3 8 3 serial status register_3 ssr_3 8 h'fff604 sci3_3 8 3 receive data register_3 rdr_3 8 h'fff605 sci3_3 8 3 ? ? ? h'fff606, h'fff607 ? ? ? serial mode control register smcr_3 8 h'fff608 sci3_3 8 3 ? ? ? h'fff609 to h'fff6ff ? ? ? timer control register_0 tcr_0 8 h'fff700 timer z0 8 2 timer i/o control register a_0 tiora_0 8 h'fff701 timer z0 8 2 timer i/o control register c_0 tiorc_0 8 h'fff702 timer z0 8 2 timer status register_0 tsr_0 8 h'fff703 timer z0 8 2 timer interrupt enable register _0 tier_0 8 h'fff704 timer z0 8 2 pwm mode output level control register_0 pocr_0 8 h'fff705 timer z0 8 2 timer counter_0 tcnt_0 16 h'fff706 timer z0 16 2 general register a_0 gra_0 16 h'fff708 timer z0 16 2 general register b_0 grb_0 16 h'fff70a timer z0 16 2 general register c_0 grc_0 16 h'fff70c timer z0 16 2 general register d_0 grd_0 16 h'fff70e timer z0 16 2
section 22 list of registers rev. 3.00 mar. 15, 2006 page 405 of 526 rej09b0060-0300 register name abbre- viation bit no. address module name data bus width access state timer control register_1 tcr_1 8 h'fff710 timer z1 8 2 timer i/o control register a_1 tiora_1 8 h'fff711 timer z1 8 2 timer i/o control register c_1 tiorc_1 8 h'fff712 timer z1 8 2 timer status register_1 tsr_1 8 h'fff713 timer z1 8 2 timer interrupt enable register_1 tier_1 8 h'fff714 timer z1 8 2 pwm mode output level control register_1 pocr_1 8 h'fff715 timer z1 8 2 timer counter_1 tcnt_1 16 h'fff716 timer z1 16 2 general register a_1 gra_1 16 h'fff718 timer z1 16 2 general register b_1 grb_1 16 h'fff71a timer z1 16 2 general register c_1 grc_1 16 h'fff71c timer z1 16 2 general register d_1 grd_1 16 h'fff71e timer z1 16 2 timer start register tstr 8 h'fff720 timer z common 8 2 timer mode register tmdr 8 h'fff721 timer z common 8 2 timer pwm mode register tpmr 8 h'fff722 timer z common 8 2 timer function control register tfcr 8 h'fff723 timer z common 8 2 timer output master enable register toer 8 h'fff724 timer z common 8 2 timer output control regist er tocr 8 h'fff725 timer z common 8 2 ? ? ? h'fff726, h'fff727 ? ? ? second data register/free running counter data register rsecdr 8 h'fff728 rtc 8 2 minute data register rmindr 8 h'fff729 rtc 8 2 hour data register rhrdr 8 h'fff72a rtc 8 2 day-of-week data register rwkdr 8 h'fff72b rtc 8 2 rtc control register 1 rtccr1 8 h'fff72c rtc 8 2
section 22 list of registers rev. 3.00 mar. 15, 2006 page 406 of 526 rej09b0060-0300 register name abbre- viation bit no. address module name data bus width access state rtc control register 2 rtccr2 8 h'fff72d rtc 8 2 ? ? ? h'fff72e ? ? ? clock source select register rtccsr 8 h'fff72f rtc 8 2 low-voltage-detection control register lvdcr 8 h'fff730 lvdc * 1 8 2 low-voltage-detection status register lvdsr 8 h'fff731 lvdc * 1 8 2 ? ? ? h'fff732 to h'fff73f ? ? ? serial mode register_2 smr_2 8 h'fff740 sci3_2 8 3 bit rate register_2 brr_2 8 h'fff741 sci3_2 8 3 serial control register 3 _2 scr3_2 8 h'fff742 sci3_2 8 3 transmit data register_2 tdr_2 8 h'fff743 sci3_2 8 3 serial status register_2 ssr_2 8 h'fff744 sci3_2 8 3 receive data register_2 rdr_2 8 h'fff745 sci3_2 8 3 ? ? ? h'fff746, h'fff747 ? ? ? i 2 c bus control register 1 iccr1 8 h'fff748 iic2 8 2 i 2 c bus control register 2 iccr2 8 h'fff749 iic2 8 2 i 2 c bus mode register icmr 8 h'fff74a iic2 8 2 i 2 c bus interrupt enable register icier 8 h'fff74b iic2 8 2 i 2 c bus status register icsr 8 h'fff74c iic2 8 2 slave address register sar 8 h'fff74d iic2 8 2 i 2 c bus transmit data register icdrt 8 h'fff74e iic2 8 2 i 2 c bus receive data register icdrr 8 h'fff74f iic2 8 2 ? ? ? h'fff750 to h'fff75f ? ? ? timer mode register b1 tmb1 8 h'fff760 timer b1 8 2 timer counter b1 tcb1 8 h'fff761 timer b1 8 2 timer load register b1 tlb1 8 h'fff761 timer b1 8 2 ? ? ? h'fff762 to h'ffff7f ? ? ?
section 22 list of registers rev. 3.00 mar. 15, 2006 page 407 of 526 rej09b0060-0300 register name abbre- viation bit no. address module name data bus width access state timer mode register w tmrw 8 h'ffff80 timer w 8 2 timer control register w tcrw 8 h'ffff81 timer w 8 2 timer interrupt enable register w tierw 8 h'ffff82 timer w 8 2 timer status register w tsrw 8 h'ffff83 timer w 8 2 timer i/o control register 0 tior0 8 h'ffff84 timer w 8 2 timer i/o control register 1 tior1 8 h'ffff85 timer w 8 2 timer counter tcnt 16 h'ffff86 timer w 16 2 general register a gra 16 h'ffff88 timer w 16 2 general register b grb 16 h'ffff8a timer w 16 2 general register c grc 16 h'ffff8c timer w 16 2 general register d grd 16 h'ffff8e timer w 16 2 flash memory control register 1 flmcr1 8 h'ffff90 rom 8 2 flash memory control register 2 flmcr2 8 h'ffff91 rom 8 2 flash memory power control register flpwcr 8 h'ffff92 rom 8 2 erase block register 1 ebr1 8 h'ffff93 rom 8 2 ? ? ? h'ffff94 to h'ffff9a ? ? ? flash memory enable regist er fenr 8 h'ffff9b rom 8 2 ? ? ? h'ffff9c to h'ffff9f ? ? ? timer control register v0 tcrv0 8 h'ffffa0 timer v 8 3 timer control/status register v tcsrv 8 h'ffffa1 timer v 8 3 time constant register a tcora 8 h'ffffa2 timer v 8 3 time constant register b tcorb 8 h'ffffa3 timer v 8 3 timer counter v tcntv 8 h'ffffa4 timer v 8 3 timer control register v1 tcrv1 8 h'ffffa5 timer v 8 3 ? ? ? h'ffffa6, h'ffffa7 ? ? ? serial mode register smr 8 h'ffffa8 sci3 8 3 bit rate register brr 8 h'ffffa9 sci3 8 3
section 22 list of registers rev. 3.00 mar. 15, 2006 page 408 of 526 rej09b0060-0300 register name abbre- viation bit no. address module name data bus width access state serial control register 3 scr3 8 h'ffffaa sci3 8 3 transmit data register tdr 8 h'ffffab sci3 8 3 serial status register ssr 8 h'ffffac sci3 8 3 receive data register rdr 8 h'ffffad sci3 8 3 ? ? ? h'ffffae, h'ffffaf ? ? ? a/d data register a addra 16 h'ffffb0 a/d converter 8 3 a/d data register b addrb 16 h'ffffb2 a/d converter 8 3 a/d data register c addrc 16 h'ffffb4 a/d converter 8 3 a/d data register d addrd 16 h'ffffb6 a/d converter 8 3 a/d control/status register adcsr 8 h'ffffb8 a/d converter 8 3 a/d control register adcr 8 h'ffffb9 a/d converter 8 3 ? ? ? h'ffffba, h'ffffbb ? ? ? pwm data register l pwdrl 8 h'ffffbc 14-bit pwm 8 2 pwm data register u pwdru 8 h'ffffbd 14-bit pwm 8 2 pwm control register pwcr 8 h'ffffbe 14-bit pwm 8 2 ? ? ? h'ffffbf ? ? ? timer control/status regist er wd tcsrwd 8 h'ffffc0 wdt * 2 8 2 timer counter wd tcwd 8 h'ffffc1 wdt * 2 8 2 timer mode register wd tmwd 8 h'ffffc2 wdt * 2 8 2 ? ? ? h'ffffc3 ? ? ? ? ? ? h'ffffc4 to h'ffffc7 ? ? ?
section 22 list of registers rev. 3.00 mar. 15, 2006 page 409 of 526 rej09b0060-0300 register name abbre- viation bit no. address module name data bus width access state address break control regist er abrkcr 8 h'ffffc8 address break 8 2 address break status regist er abrksr 8 h'ffffc9 address break 8 2 break address register h barh 8 h'ffffca address break 8 2 break address register l barl 8 h'ffffcb address break 8 2 break data register h bdrh 8 h'ffffcc address break 8 2 break data register l bdrl 8 h'ffffcd address break 8 2 ? ? ? h'ffffce ? ? ? break address register e bare 8 h'ffffcf address break 8 2 port pull-up control register 1 pucr1 8 h'ffffd0 i/o port 8 2 port pull-up control register 5 pucr5 8 h'ffffd1 i/o port 8 2 ? ? ? h'ffffd2, h'ffffd3 ? ? ? port data register 1 pdr1 8 h'ffffd4 i/o port 8 2 port data register 2 pdr2 8 h'ffffd5 i/o port 8 2 port data register 3 pdr3 8 h'ffffd6 i/o port 8 2 ? ? ? h'ffffd7 ? ? ? port data register 5 pdr5 8 h'ffffd8 i/o port 8 2 port data register 6 pdr6 8 h'ffffd9 i/o port 8 2 port data register 7 pdr7 8 h'ffffda i/o port 8 2 port data register 8 pdr8 8 h'ffffdb i/o port 8 2 port data register 9 pdr9 8 h'ffffdc i/o port 8 2 port data register b pdrb 8 h'ffffdd i/o port 8 2 ? ? ? h'ffffde, h'ffffdf ? ? ? port mode register 1 pmr1 8 h'ffffe0 i/o port 8 2 port mode register 5 pmr5 8 h'ffffe1 i/o port 8 2
section 22 list of registers rev. 3.00 mar. 15, 2006 page 410 of 526 rej09b0060-0300 register name abbre- viation bit no. address module name data bus width access state port mode register 3 pmr3 8 h'ffffe2 i/o port 8 2 ? ? ? h'ffffe3 ? ? ? port control register 1 pcr1 8 h'ffffe4 i/o port 8 2 port control register 2 pcr2 8 h'ffffe5 i/o port 8 2 port control register 3 pcr3 8 h'ffffe6 i/o port 8 2 ? ? ? h'ffffe7 ? ? ? port control register 5 pcr5 8 h'ffffe8 i/o port 8 2 port control register 6 pcr6 8 h'ffffe9 i/o port 8 2 port control register 7 pcr7 8 h'ffffea i/o port 8 2 port control register 8 pcr8 8 h'ffffeb i/o port 8 2 port control register 9 pcr9 8 h'ffffec i/o port 8 2 ? ? ? h'ffffed to h'ffffef ? ? ? system control register 1 syscr1 8 h'fffff0 power- down 8 2 system control register 2 syscr2 8 h'fffff1 power- down 8 2 interrupt edge select register 1 iegr1 8 h'fffff2 interrupt 8 2 interrupt edge select register 2 iegr2 8 h'fffff3 interrupt 8 2 interrupt enable register 1 ie nr1 8 h'fffff4 interrupt 8 2 interrupt enable register 2 ie nr2 8 h'fffff5 interrupt 8 2 interrupt flag register 1 irr1 8 h'fffff6 interrupt 8 2 interrupt flag register 2 irr2 8 h'fffff7 interrupt 8 2 wakeup interrupt flag register iwpr 8 h'fffff8 interrupt 8 2 module standby control register 1 mstcr1 8 h'fffff9 power- down 8 2 module standby control register 2 mstcr2 8 h'fffffa power- down 8 2 ? ? ? h'fffffb to h'ffffff ? ? ? notes: 1. lvdc: low-voltage det ection circuits (optional) 2. wdt: watchdog timer
section 22 list of registers rev. 3.00 mar. 15, 2006 page 411 of 526 rej09b0060-0300 22.2 register bits the addresses and bit names of the registers in the on-chip peripheral modules are listed below. the 16-bit register is indicated in two rows, 8 bits for each row. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name smr_3 com chr pe pm stop mp cks1 cks0 sci3_3 brr_3 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3_3 tie rie te re mpie teie cke1 cke0 tdr_3 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr_3 tdre rdrf oer fer per tend mpbr mpbt rdr_3 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 smcr_3 ? ? ? ? ? nfen_3 txd_3 msts3_3 tcr_0 cclr2 cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 timer z0 tiora_0 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tiorc_0 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0 tsr_0 ? ? ? ovf imfd imfc imfb imfa tier_0 ? ? ? ovie imied imiec imieb imiea pocr_0 ? ? ? ? ? pold polc polb tcnt_0 tcnt0h7 tcnt0h6 tcnt0h5 tcnt0h 4 tcnt0h3 tcnt0h2 tcnt0h1 tcnt0h0 tcnt0l7 tcnt0l6 tcnt0l5 tcnt0l4 t cnt0l3 tcnt0l2 tcnt0l1 tcnt0l0 gra_0 gra0h7 gra0h6 gra0h5 gra0h4 gra0h3 gra0h2 gra0h1 gra0h0 gra0l7 gra0l6 gra0l5 gra0l4 gra0l3 gra0l2 gra0l1 gra0l0 grb_0 grb0h7 grb0h6 grb0h5 grb0h4 grb0h3 grb0h2 grb0h1 grb0h0 grb0l7 grb0l6 grb0l5 grb0l4 grb0l3 grb0l2 grb0l1 grb0l0 grc_0 grc0h7 grc0h6 g rc0h5 grc0h4 grc0h3 gr c0h2 grc0h1 grc0h0 grc0l7 grc0l6 grc0l5 grc0l4 grc0l3 grc0l2 grc0l1 grc0l0 grd_0 grd0h7 grd0h6 g rd0h5 grd0h4 grd0h3 gr d0h2 grd0h1 grd0h0 grd0l7 grd0l6 grd0l5 grd0l4 grd0l3 grd0l2 grd0l1 grd0l0 tcr_1 cclr2 cclr1 cclr0 ckeg1 c keg0 tpsc2 tpsc1 tpsc0 timer z1 tiora_1 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tiorc_1 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0
section 22 list of registers rev. 3.00 mar. 15, 2006 page 412 of 526 rej09b0060-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name tsr_1 ? ? udf ovf imfd imfc imfb imfa timer z1 tier_1 ? ? ? ovie imied imiec imieb imiea pocr_1 ? ? ? ? ? pold polc polb tcnt_1 tcnt1h7 tcnt1h6 tcnt1h5 tcnt1h 4 tcnt1h3 tcnt1h2 tcnt1h1 tcnt1h0 tcnt1l7 tcnt1l6 tcnt1l5 tcnt1l4 tcnt1l3 tcnt1l2 tcnt1l1 tcnt1l0 gra_1 gra1h7 gra1h6 gra1h5 gra1h4 gra1h3 gra1h2 gra1h1 gra1h0 gra1l7 gra1l6 gra1l5 gra1l4 gra1l3 gra1l2 gra1l1 gra1l0 grb_1 grb1h7 grb1h6 grb1h5 grb1h4 grb1h3 grb1h2 grb1h1 grb1h0 grb1l7 grb1l6 grb1l5 grb1l4 grb1l3 grb1l2 grb1l1 grb1l0 grc_1 grc1h7 grc1h6 grc1h5 grc1h4 grc1h3 grc1h2 grc1h1 grc1h0 grc1l7 grc1l6 grc1l5 grc1l4 grc1l3 grc1l2 grc1l1 grc1l0 grd_1 grd1h7 grd1h6 grd1h5 grd1h4 grd1h3 grd1h2 grd1h1 grd1h0 grd1l7 grd1l6 grd1l5 grd1l4 grd1l3 grd1l2 grd1l1 grd1l0 tstr ? ? ? ? ? ? str1 str0 tmdr bfd1 bfc1 bfd0 bfc0 ? ? ? sync timer z common tpmr ? pwmd1 pwmc1 pwmb 1 ? pwmd0 pwmc0 pwmb0 tfcr ? stclk adeg adtrg ols1 ols0 cmd1 cmd0 toer ed1 ec1 eb1 ea1 ed0 ec0 eb0 ea0 tocr tod1 toc1 tob1 toa1 tod0 toc0 tob0 toa0 rsecdr bsy sc12 sc11 sc10 sc03 sc02 sc01 sc00 rtc rmindr bsy mn12 mn11 mn10 mn03 mn02 mn01 mn00 rhrdr bsy ? hr11 hr10 hr03 hr02 hr01 hr00 rwkdr bsy ? ? ? ? wk2 wk1 wk0 rtccr1 run 12/24 pm rst int ? ? ? rtccr2 ? ? foie wkie dyie hrie mnie seie rtccsr ? rcs6 rcs5 ? rcs3 rcs2 rcs1 rcs0 lvdcr lvde ? ? ? lvdsel lvdre lvdde lvdue lvdsr ? ? ? ? ? ? lvddf lvduf lvdc (optional) * 1
section 22 list of registers rev. 3.00 mar. 15, 2006 page 413 of 526 rej09b0060-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name smr_2 com chr pe pm stop mp cks1 cks0 sci3_2 brr_2 brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3_2 tie rie te re mpie teie cke1 cke0 tdr_2 tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr_2 tdre rdrf oer fer per tend mpbr mpbt rdr_2 rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 iccr1 ice rcvd mst trs c ks3 cks2 cks1 cks0 iic2 iccr2 bbsy scp sdao sdaop sclo ? iicrst ? icmr mls wait ? ? bcwp bc2 bc1 bc0 icier tie teie rie nakie stie acke ackbr ackbt icsr tdre tend rdrf nackf stop al/ove aas adz sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs icdrt icdrt7 icdrt6 icdrt5 icdrt4 icdrt3 icdrt2 icdrt1 icdrt0 icdrr icdrr7 icdrr6 icdrr5 icdrr4 icdrr3 icdrr2 icdrr1 icdrr0 tmb1 tmb17 ? ? ? ? tmb12 tmb11 tmb10 timer b1 tcb1 tcb17 tcb16 tcb15 tcb 14 tcb13 tcb12 tcb11 tcb10 tlb1 tlb17 tlb16 tlb15 tlb14 tlb13 tlb12 tlb11 tlb10 tmrw cts ? bufeb bufea ? pwmd pwmc pwmb timer w tcrw cclr cks2 cks1 cks0 tod toc tob toa tierw ovie ? ? ? imied imiec imieb imiea tsrw ovf ? ? ? imfd imfc imfb imfa tior0 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tior1 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0 tcnt tcnt15 tcnt14 tcnt13 tcnt 12 tcnt11 tcnt10 tcnt9 tcnt8 tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 gra gra15 gra14 gra13 gra12 gra11 gra10 gra9 gra8 gra7 gra6 gra5 gra4 gra3 gra2 gra1 gra0 grb grb15 grb14 grb13 grb12 grb11 grb10 grb9 grb8 grb7 grb6 grb5 grb4 grb3 grb2 grb1 grb0 grc grc15 grc14 grc13 grc12 grc11 grc10 grc9 grc8 grc7 grc6 grc5 grc4 grc3 grc2 grc1 grc0
section 22 list of registers rev. 3.00 mar. 15, 2006 page 414 of 526 rej09b0060-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name grd grd15 grd14 grd13 grd12 g rd11 grd10 grd9 grd8 timer w grd7 grd6 grd5 grd4 grd3 grd2 grd1 grd0 flmcr1 ? swe esu psu ev pv e p rom flmcr2 fler ? ? ? ? ? ? ? flpwcr pdwnd ? ? ? ? ? ? ? ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 fenr flshe ? ? ? ? ? ? ? tcrv0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 timer v tcsrv cmfb cfma ovf ? os3 os2 os1 os0 tcora tcora7 tcora6 tcora5 tcora4 tcora3 tcora2 tcora1 tcora0 tcorb tcorb7 tcorb6 tcorb5 tcorb4 tcorb3 tcorb2 tcorb1 tcorb0 tcntv tcntv7 tcntv6 tcntv5 tcntv4 tcntv3 tcntv2 tcntv1 tcntv0 tcrv1 ? ? ? tveg1 tveg0 trge ? icks0 smr com chr pe pm stop mp cks1 cks0 sci3 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3 tie rie te re mpie teie cke1 cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf oer fer per tend mpbr mpbt rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 addra ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter ad1 ad0 ? ? ? ? ? ? addrb ad9 ad8 ad7 ad 6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrc ad9 ad8 ad7 ad 6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrd ad9 ad8 ad7 ad 6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? adcsr adf adie adst scan cks ch2 ch1 ch0 adcr trge ? ? ? ? ? ? ?
section 22 list of registers rev. 3.00 mar. 15, 2006 page 415 of 526 rej09b0060-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name pwdrl pwdrl7 pwdrl6 pwdr l5 pwdrl4 pwdrl3 pwdrl2 pw drl1 pwdrl0 14-bit pwm pwdru ? ? pwdru5 pwdru4 pwdru3 pwdru2 pwdru1 pwdru0 pwcr ? ? ? ? ? ? ? pwcr0 tcsrwd b6wi tcwe b4wi tcsrwe b2wi wdon b0wi wrst wdt * 2 tcwd tcwd7 tcwd6 tcwd5 tcwd 4 tcwd3 tcwd2 tcwd1 tcwd0 tmwd ? ? ? ? cks3 cks2 cks1 cks0 abrkcr rtinte csel1 csel0 ac mp2 acmp1 acmp0 dcmp1 dcmp0 abrksr abif abie ? ? ? ? ? ? address break barh barh7 barh6 barh5 barh4 barh3 barh2 barh1 barh0 barl barl7 barl6 barl5 barl4 barl3 barl2 barl1 barl0 bdrh bdrh7 bdrh6 bdrh5 bdrh4 bdrh3 bdrh2 bdrh1 bdrh0 bdrl bdrl7 bdrl6 bdrl5 bdr l4 bdrl3 bdrl2 bdrl1 bdrl0 bare bare7 bare6 bare5 bare4 bare3 bare2 bare1 bare0 pucr1 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 i/o port pucr5 ? ? pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 pdr1 p17 p16 p15 p14 ? p12 p11 p10 pdr2 ? ? ? p24 p23 p22 p21 p20 pdr3 p37 p36 p35 p34 p33 p32 p31 p30 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 pdr6 p67 p66 p65 p64 p63 p62 p61 p60 pdr7 p77 p76 p75 p74 ? p72 p71 p70 pdr8 p87 p86 p85 p84 p83 p82 p81 p80 pdr9 p97 p96 p95 p94 p93 p92 p91 p90 pdrb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pmr1 irq3 irq2 irq1 irq0 txd2 pwm txd tmow pmr5 pof57 pof56 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 pmr3 ? ? ? pof24 pof23 ? ? ? pcr1 pcr17 pcr16 pcr15 p cr14 ? pcr12 pcr11 pcr10 pcr2 ? ? ? pcr24 pcr23 pcr22 pcr21 pcr20 pcr3 pcr37 pcr36 pcr35 pcr 34 pcr33 pcr32 pcr31 pcr30 pcr5 pcr57 pcr56 pcr55 pcr 54 pcr53 pcr52 pcr51 pcr50
section 22 list of registers rev. 3.00 mar. 15, 2006 page 416 of 526 rej09b0060-0300 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name pcr6 pcr67 pcr66 pcr65 pcr64 p cr63 pcr62 pcr61 pcr60 i/o port pcr7 pcr77 pcr76 pcr75 p cr74 ? pcr72 pcr71 pcr70 pcr8 pcr87 pcr86 pcr85 pcr 84 pcr83 pcr82 pcr81 pcr80 pcr9 pcr97 pcr96 pcr95 pcr 94 pcr93 pcr92 pcr91 pcr90 syscr1 ssby sts2 sts1 sts0 nesel ? ? ? power-down syscr2 smsel lson dton ma2 ma1 ma0 sa1 sa0 iegr1 nmieg ? ? ? ieg3 ieg2 ieg1 ieg0 interrupt iegr2 ? ? wpeg5 wpeg4 w peg3 wpeg2 wpeg1 wpeg0 ienr1 iendt ienta ienwp ? ien3 ien2 ien1 ien0 ienr2 ? ? ientb1 ? ? ? ? ? irr1 irrdt irrta ? ? irri3 irri2 irri1 irri0 irr2 ? ? irrtb1 ? ? ? ? ? iwpr ? ? iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 mstcr1 ? mstiic msts3 mstad ms twd msttw msttv mstta power-down mstcr2 msts3_2 ? ? msttb1 ? ? msttz mstpwm notes: 1. lvdc: low-voltage det ection circuits (optional) 2. wdt: watchdog timer
section 22 list of registers rev. 3.00 mar. 15, 2006 page 417 of 526 rej09b0060-0300 22.3 register states in each operating mode register name reset active sleep subactive subsleep standby module smr_3 initialized ? ? initialized initialized initialized sci3_3 brr_3 initialized ? ? initialized initialized initialized scr3_3 initialized ? ? initialized initialized initialized tdr_3 initialized ? ? initialized initialized initialized ssr_3 initialized ? ? initialized initialized initialized rdr_3 initialized ? ? initialized initialized initialized smcr_3 initialized ? ? ? ? ? tcr_0 initialized ? ? ? ? ? timer z0 tiora_0 initialized ? ? ? ? ? tiorc_0 initialized ? ? ? ? ? tsr_0 initialized ? ? ? ? ? tier_0 initialized ? ? ? ? ? pocr_0 initialized ? ? ? ? ? tcnt_0 initialized ? ? ? ? ? gra_0 initialized ? ? ? ? ? grb_0 initialized ? ? ? ? ? grc_0 initialized ? ? ? ? ? grd_0 initialized ? ? ? ? ? tcr_1 initialized ? ? ? ? ? timer z1 tiora_1 initialized ? ? ? ? ? tiorc_1 initialized ? ? ? ? ? tsr_1 initialized ? ? ? ? ? tier_1 initialized ? ? ? ? ? pocr_1 initialized ? ? ? ? ? tcnt_1 initialized ? ? ? ? ? gra_1 initialized ? ? ? ? ? grb_1 initialized ? ? ? ? ? grc_1 initialized ? ? ? ? ? grd_1 initialized ? ? ? ? ?
section 22 list of registers rev. 3.00 mar. 15, 2006 page 418 of 526 rej09b0060-0300 register name reset active sleep subactive subsleep standby module tstr initialized ? ? ? ? ? tmdr initialized ? ? ? ? ? timer z common tpmr initialized ? ? ? ? ? tfcr initialized ? ? ? ? ? toer initialized ? ? ? ? ? tocr initialized ? ? ? ? ? rsecdr initialized ? ? ? ? ? rtc rmindr initialized ? ? ? ? ? rhrdr initialized ? ? ? ? ? rwkdr ? ? ? ? ? ? rtccr1 ? ? ? ? ? ? rtccr2 ? ? ? ? ? ? rtccsr initialized ? ? ? ? ? lvdcr initialized ? ? ? ? ? lvdsr initialized ? ? ? ? ? lvdc (optional) * 1 smr_2 initialized ? ? initialized initialized initialized sci3_2 brr_2 initialized ? ? initialized initialized initialized scr3_2 initialized ? ? initialized initialized initialized tdr_2 initialized ? ? initialized initialized initialized ssr_2 initialized ? ? initialized initialized initialized rdr_2 initialized ? ? initialized initialized initialized iccr1 initialized ? ? ? ? ? iic2 iccr2 initialized ? ? ? ? ? icmr initialized ? ? ? ? ? icier initialized ? ? ? ? ? icsr initialized ? ? ? ? ? sar initialized ? ? ? ? ? icdrt initialized ? ? ? ? ? icdrr initialized ? ? ? ? ? tmb1 initialized ? ? ? ? ? tcb1 initialized ? ? ? ? ? timer b1 tlb1 initialized ? ? ? ? ?
section 22 list of registers rev. 3.00 mar. 15, 2006 page 419 of 526 rej09b0060-0300 register name reset active sleep subactive subsleep standby module tmrw initialized ? ? ? ? ? timer w tcrw initialized ? ? ? ? ? tierw initialized ? ? ? ? ? tsrw initialized ? ? ? ? ? tior0 initialized ? ? ? ? ? tior1 initialized ? ? ? ? ? tcnt initialized ? ? ? ? ? gra initialized ? ? ? ? ? grb initialized ? ? ? ? ? grc initialized ? ? ? ? ? grd initialized ? ? ? ? ? flmcr1 initialized ? ? initialized initialized initialized rom flmcr2 initialized ? ? ? ? ? flpwcr initialized ? ? ? ? ? ebr1 initialized ? ? initialized initialized initialized fenr initialized ? ? ? ? ? tcrv0 initialized ? ? initialized initialized initialized timer v tcsrv initialized ? ? initialized initialized initialized tcora initialized ? ? initialized initialized initialized tcorb initialized ? ? initialized initialized initialized tcntv initialized ? ? initia lized initialized initialized tcrv1 initialized ? ? initialized initialized initialized smr initialized ? ? initialized initialized initialized sci3 brr initialized ? ? initialized initialized initialized scr3 initialized ? ? initialized initialized initialized tdr initialized ? ? initialized initialized initialized ssr initialized ? ? initialized initialized initialized rdr initialized ? ? initialized initialized initialized addra initialized ? ? initialized in itialized initialized a/d converter addrb initialized ? ? initialized initialized initialized addrc initialized ? ? initialized initialized initialized
section 22 list of registers rev. 3.00 mar. 15, 2006 page 420 of 526 rej09b0060-0300 register name reset active sleep subactive subsleep standby module addrd initialized ? ? initialized init ialized initialized a/d converter adcsr initialized ? ? initialized initialized initialized adcr initialized ? ? initialized initialized initialized pwdrl initialized ? ? ? ? ? 14-bit pwm pwdru initialized ? ? ? ? ? pwcr initialized ? ? ? ? ? tcsrwd initialized ? ? ? ? ? wdt * 2 tcwd initialized ? ? ? ? ? tmwd initialized ? ? ? ? ? abrkcr initialized ? ? ? ? ? abrksr initialized ? ? ? ? ? address break barh initialized ? ? ? ? ? barl initialized ? ? ? ? ? bdrh initialized ? ? ? ? ? bdrl initialized ? ? ? ? ? bare initialized ? ? ? ? ? pucr1 initialized ? ? ? ? ? i/o port pucr5 initialized ? ? ? ? ? pdr1 initialized ? ? ? ? ? pdr2 initialized ? ? ? ? ? pdr3 initialized ? ? ? ? ? pdr5 initialized ? ? ? ? ? pdr6 initialized ? ? ? ? ? pdr7 initialized ? ? ? ? ? pdr8 initialized ? ? ? ? ? pdr9 initialized ? ? ? ? ? pdrb initialized ? ? ? ? ? pmr1 initialized ? ? ? ? ? pmr5 initialized ? ? ? ? ? pmr3 initialized ? ? ? ? ? pcr1 initialized ? ? ? ? ?
section 22 list of registers rev. 3.00 mar. 15, 2006 page 421 of 526 rej09b0060-0300 register name reset active sleep subactive subsleep standby module pcr2 initialized ? ? ? ? ? i/o port pcr3 initialized ? ? ? ? ? pcr5 initialized ? ? ? ? ? pcr6 initialized ? ? ? ? ? pcr7 initialized ? ? ? ? ? pcr8 initialized ? ? ? ? ? pcr9 initialized ? ? ? ? ? syscr1 initialized ? ? ? ? ? power-down syscr2 initialized ? ? ? ? ? iegr1 initialized ? ? ? ? ? interrupt iegr2 initialized ? ? ? ? ? ienr1 initialized ? ? ? ? ? ienr2 initialized ? ? ? ? ? irr1 initialized ? ? ? ? ? irr2 initialized ? ? ? ? ? iwpr initialized ? ? ? ? ? mstcr1 initialized ? ? ? ? ? power-down mstcr2 initialized ? ? ? ? ? notes: ? is not initialized 1. lvdc: low-voltage detection circuits (optional) 2. wdt: watchdog timer
section 22 list of registers rev. 3.00 mar. 15, 2006 page 422 of 526 rej09b0060-0300
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 423 of 526 rej09b0060-0300 section 23 electrical characteristics 23.1 absolute maximum ratings table 23.1 absolute maximum ratings item symbol value unit notes power supply voltage v cc ?0.3 to +7.0 v * analog power supply voltage av cc ?0.3 to +7.0 v input voltage ports other than ports b and x1 v in ?0.3 to v cc +0.3 v port b ?0.3 to av cc +0.3 v x1 ?0.3 to 4.3 v operating temperature t opr ?20 to +75 c storage temperature t stg ?55 to +125 c note: * permanent damage may result if maximu m ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 23.2 electrical characteristics (f-ztat? version) 23.2.1 power supply voltage and operating ranges power supply voltage and os cillation frequency range 10.0 2.0 20.0 3.0 4.0 5.5 v cc (v) osc (mhz) 32.768 3.0 4.0 5.5 v cc (v) w (khz) av cc = 3.0 to 5.5 v active mode sleep mode av cc = 3.0 to 5.5 v all operating modes
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 424 of 526 rej09b0060-0300 power supply voltage and op erating frequency range 10.0 1.0 20.0 3.0 4.0 5.5 v cc (v) (mhz) 16.384 3.0 4.0 5.5 v cc (v) sub (khz) 8.192 4.096 1250 78.125 2500 3.0 4.0 5.5 v cc (v) (khz) av cc = 3.0 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 0 ) av cc = 3.0 to 5.5 v subactive mode subsleep mode av cc = 3.0 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 1 ) analog power supply voltage and a/d converter accuracy guarantee range 10.0 2.0 20.0 3.0 4.0 5.5 av cc (v) (mhz) v cc = 3.0 to 5.5 v active mode sleep mode
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 425 of 526 rej09b0060-0300 range of power supply voltage and oscillat ion frequency when low-voltage detection circuit is used operation guarantee range operation guarantee range except a/d conversion accuracy 20.0 16.0 2.0 3.0 4.5 5.5 vcc(v) osc (mhz)
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 426 of 526 rej09b0060-0300 23.2.2 dc characteristics table 23.2 dc characteristics (1) v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg ,tmriv, v cc = 4.0 to 5.5 v v cc 0.8 ? v cc + 0.3 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, sck3, sck3_2, sck3_3, trgv, ftci, tmib1 v cc 0.9 ? v cc + 0.3 rxd, rxd_2, rxd_3, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc = 4.0 to 5.5 v v cc 0.7 ? v cc + 0.3 v p50 to p57, p60 to p67, p70 to p72, p74 to p77, p80 to p87, p90 to p97 v cc 0.8 ? v cc + 0.3 pb 0 to pb 7 v cc = 4.0 to 5.5 v v cc 0.7 ? av cc + 0.3 v v cc 0.8 ? av cc + 0.3 osc1 v cc = 4.0 to 5.5 v v cc ? 0.5 ? v cc + 0.3 v v cc ? 0.3 ? v cc + 0.3 note: connect the test pin to vss.
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 427 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmriv, v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.2 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, sck3, sck3_2, sck3_3, trgv, ftci, tmib1 ?0.3 ? v cc 0.1 rxd, rxd_2, rxd_3, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.3 v p50 to p57, p60 to p67, p70 to p72, p74 to p77, p80 to p87, p90 to p97 ?0.3 ? v cc 0.2 pb0 to pb7 v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.3 v ?0.3 ? v cc 0.2 osc1 v cc = 4.0 to 5.5 v ?0.3 ? 0.5 v ?0.3 ? 0.3
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 428 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes output high voltage v oh p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc = 4.0 to 5.5 v ?i oh = 1.5 ma v cc ? 1.0 ? ? v p50 to p55, p60 to p67, p70 to p72, p74 to p77, p80 to p87, p90 to p97 ?i oh = 0.1 ma v cc ? 0.5 ? ? p56, p57 4.0 v v cc 5.5 v ?i oh = 0.1 ma v cc ? 2.5 ? ? v 3.0 v v cc < 4.0 v ?i oh = 0.1 ma v cc ? 2.0 ? ? output low voltage v ol p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc = 4.0 to 5.5 v i ol = 1.6 ma ? ? 0.6 v p50 to p57, p70 to p72, p74 to p77, p85 to p87, p90 to p97 i ol = 0.4 ma ? ? 0.4 p60 to p67, p80 to p84 v cc = 4.0 to 5.5 v i ol = 20.0 ma ? ? 1.5 v v cc = 4.0 to 5.5 v i ol = 10.0 ma ? ? 1.0 v cc = 4.0 to 5.5 v i ol = 1.6 ma ? ? 0.4 i ol = 0.4 ma ? ? 0.4 scl, sda v cc = 4.0 to 5.5 v i ol = 6.0 ma ? ? 0.6 i ol = 3.0 ma ? ? 0.4
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 429 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes | i il | osc1, res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, rxd, sck3, rxd_2, sck3_2, rxd_3, sck3_3, scl, sda, tmib1, ftci v in = 0.5 v or higher (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p24, p30 to p37, p50 to p57, p60 to p67, p70 to p72, p74 to p77, p80 to p87, p90 to p97 v in = 0.5 v or higher (v cc ? 0.5 v) ? ? 1.0 a pb 0 to pb 7 v in = 0.5 v or higher (av cc ? 0.5 v) ? ? 1.0 a ?i p p10 to p12, p14 to p17, v cc = 5.0 v, v in = 0.0 v 50.0 ? 300.0 a pull-up mos current p50 to p55 v cc = 3.0 v, v in = 0.0 v ? 60.0 ? reference value pull-up mos resistance r res res ? 150 ? k ? input capaci- tance c in all input pins except power supply pins f = 1 mhz, v in = 0.0 v, t a = 25c ? ? 15.0 pf
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 430 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes i ope1 v cc active mode 1 v cc = 5.0 v, f osc = 20 mhz ? 25.0 36.0 ma * active mode supply current active mode 1 v cc = 3.0 v, f osc = 10 mhz ? 11.0 ? * reference value i ope2 v cc active mode 2 v cc = 5.0 v, f osc = 20 mhz ? 2.3 3.6 ma * active mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.3 ? * reference value i sleep1 v cc sleep mode 1 v cc = 5.0 v, f osc = 20 mhz ? 18.0 23.0 ma * sleep mode supply current sleep mode 1 v cc = 3.0 v, f osc = 10 mhz ? 8.0 ? * reference value i sleep2 v cc sleep mode 2 v cc = 5.0 v, f osc = 20 mhz ? 2.1 3.1 ma * sleep mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.2 ? * reference value i sub v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 35.0 70.0 a * subactive mode supply current v cc = 3.0 v 32-khz crystal resonator ( sub = w /8) ? 25.0 ? * reference value subsleep mode supply current i subsp v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 25.0 50.0 a *
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 431 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes standby mode supply current i stby v cc 32-khz crystal resonator not used ? ? 5.0 a * ram data retaining voltage v ram v cc 2.0 ? ? v note: * pin states during supply current measurement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc main clock: ceramic or crystal resonator active mode 2 operates ( osc /64) subclock: pin x1 = v ss sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc /64) subactive mode v cc operates v cc main clock: ceramic or crystal resonator subsleep mode v cc only timers operate v cc subclock: crystal resonator standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator subclock: pin x 1 = v ss
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 432 of 526 rej09b0060-0300 table 23.2 dc characteristics (2) v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values item symbol pins test condition min. typ. max. unit allowable output low current (per pin) i ol output pins except port 6, p80 to p84, scl, and sda v cc = 4.0 to 5.5 v ? ? 2.0 ma port 6, p80 to p84 ? ? 20.0 output pins except port 6, p80 to p84, scl, and sda ? ? 0.5 port 6, p80 to p84 ? ? 10.0 scl, sda ? ? 6.0 allowable output low current (total) i ol output pins except port 6, p80 to p84, scl, and sda v cc = 4.0 to 5.5 v ? ? 40.0 ma port 6, p80 to p84, scl, and sda ? ? 80.0 output pins except port 6, p80 to p84, scl, and sda ? ? 20.0 port 6, p80 to p84, scl, and sda ? ? 40.0 ? ?i oh ? all output pins v cc = 4.0 to 5.5 v ? ? 2.0 ma allowable output high current (per pin) ? ? 0.2 ? ? i oh ? all output pins v cc = 4.0 to 5.5 v ? ? 30.0 ma allowable output high current (total) ? ? 8.0
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 433 of 526 rej09b0060-0300 23.2.3 ac characteristics table 23.3 ac characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values reference item symbol pins test condition min. typ. max. unit figure f osc osc1, osc2 v cc = 4.0 to 5.5 v 2.0 ? 20.0 mhz * 1 system clock oscillation frequency 2.0 ? 10.0 t cyc 1 ? 64 t osc * 2 system clock ( ) cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * 2 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time t rcx x1, x2 ? ? 2.0 s t cph osc1 v cc = 4.0 to 5.5 v 20.0 ? ? ns external clock high width 40.0 ? ? figure 23.1 t cpl osc1 v cc = 4.0 to 5.5 v 20.0 ? ? ns external clock low width 40.0 ? ? t cpr osc1 v cc = 4.0 to 5.5 v ? ? 10.0 ns external clock rise time ? ? 15.0 t cpf osc1 v cc = 4.0 to 5.5 v ? ? 10.0 ns external clock fall time ? ? 15.0
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 434 of 526 rej09b0060-0300 applicable values reference item symbol pins test condition min. typ. max. unit figure res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 23.2 in active mode and sleep mode operation 200 ? ? ns input pin high width t ih nmi , tmbi1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, ftci 2 ? ? t cyc t subcyc figure 23.3 input pin low width t il nmi , tmbi1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, ftci 2 ? ? t cyc t subcyc notes: 1. when an external clock is input, the minimum system clock oscillation frequency is 1.0 mhz. 2. determined by the ma2, ma1, ma0, sa1, and sa0 bits in the system control register 2 (syscr2).
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 435 of 526 rej09b0060-0300 table 23.4 i 2 c bus interface timing v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. test values reference item symbol condition min. typ. max. unit figure scl input cycle time t scl 12t cyc + 600 ? ? ns scl input high width t sclh 3t cyc + 300 ? ? ns figure 23.4 scl input low width t scll 5t cyc + 300 ? ? ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns retransmission start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc +20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf v cc = 4.0 to 5.5 v ? ? 250 ns ? ? 300
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 436 of 526 rej09b0060-0300 table 23.5 serial communicati on interface (sci) timing v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values reference item symbol pins test condition min. typ. max. unit figure asynchro- nous t scyc sck3 4 ? ? t cyc figure 23.5 input clockcycle clocked synchro- nous 6 ? ? input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc t txd txd v cc = 4.0 to 5.5 v ? ? 1 t cyc transmit data delay time (clocked synchronous) ? ? 1 figure 23.6 t rxs rxd v cc = 4.0 to 5.5 v 50.0 ? ? ns receive data setup time (clocked synchronous) 100.0 ? ? t rxh rxd v cc = 4.0 to 5.5 v 50.0 ? ? ns receive data hold time (clocked synchronous) 100.0 ? ?
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 437 of 526 rej09b0060-0300 23.2.4 a/d converter characteristics table 23.6 a/d convert er characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable test values item symbol pins condition min. typ. max. unit notes analog power supply voltage av cc av cc 3.0 v cc 5.5 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 5.0 v f osc = 20 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf allowable signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.0 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb conversion time (single mode) av cc = 4.0 to 5.5 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 438 of 526 rej09b0060-0300 applicable test values item symbol pins condition min. typ. max. unit notes conversion time (single mode) av cc = 4.0 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep m odes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 23.2.5 watchdog timer characteristics table 23.7 watchdog ti mer characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable test values item symbol pins condition min. typ. max. unit notes internal oscillator overflow time t ovf 0.2 0.4 ? s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 439 of 526 rej09b0060-0300 23.2.6 flash memory characteristics table 23.8 flash memory characteristics v cc = 3.0 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. test values item symbol condition min. typ. max. unit programming time (per 128 bytes) * 1 * 2 * 4 t p ? 7 ? ms erase time (per block) * 1 * 3 * 6 t e ? 100 ? ms reprogramming count n wec 1000 10000 ? times programming wait time after swe bit setting * 1 x 1 ? ? s wait time after psu bit setting * 1 y 50 ? ? s wait time after p bit setting * 1 * 4 z1 1 n 6 28 30 32 s z2 7 n 1000 198 200 202 s z3 additional- programming 8 10 12 s wait time after p bit clear * 1 5 ? ? s wait time after psu bit clear * 1 5 ? ? s wait time after pv bit setting * 1 4 ? ? s wait time after dummy write * 1 2 ? ? s wait time after pv bit clear * 1 2 ? ? s wait time after swe bit clear * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 440 of 526 rej09b0060-0300 test values item symbol condition min. typ. max. unit erasing wait time after swe bit setting * 1 x 1 ? ? s wait time after esu bit setting * 1 y 100 ? ? s wait time after e bit setting * 1 * 6 z 10 ? 100 ms wait time after e bit clear * 1 10 ? ? s wait time after esu bit clear * 1 10 ? ? s wait time after ev bit setting * 1 20 ? ? s wait time after dummy write * 1 2 ? ? s wait time after ev bit clear * 1 4 ? ? s wait time after swe bit clear * 1 100 ? ? s maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. make the time se ttings in accordance with the program/erase algorithms. 2. the programming time for 128 bytes. (indica tes the total time for which the p bit in the flash memory control register 1 (flmcr1) is set. the program-verify time is not included.) 3. the time required to erase one block. (indi cates the time for which the e bit in the flash memory control register 1 (flmcr1) is set. the erase-verify time is not included.) 4. maximum programming time (t p (max.)) = wait time after p bit setting (z) maximum programming count (n) 5. set the maximum programming count (n) acco rding to the actual se t values of z1, z2, and z3, so that it does not exceed the maximum programming time (t p (max.)). the wait time after p bit setting (z1, z2) should be cha nged as follows according to the value of the programming count (n). programming count (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. maximum erase time (t e (max.)) = wait time after e bit setting (z) maximum erase count (n) 7. set the maximum erase count (n) according to the actual set value of (z), so that it does not exceed the maximum erase time (t e (max.)).
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 441 of 526 rej09b0060-0300 23.2.7 power-supply-voltage detection circuit characteristics (optional) table 23.9 power-supply-voltage de tection circuit characteristics v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min. typ. max. unit power-supply falling detection voltage vint (d) lvdsel = 0 3.3 3.7 ? v power-supply rising detection voltage vint (u) lvdsel = 0 ? 4.0 4.5 v reset detection voltage 1 * 1 vreset1 lvdsel = 0 ? 2.3 2.7 v reset detection voltage 2 * 2 vreset2 lvdsel = 1 3.0 3.6 4.2 v lower-limit voltage of lvdr operation * 3 v lvdrmin ? 1.0 ? ? v lvd stabilization time t lvdon ? 50 ? ? s supply current in standby mode i stby lvde = 1, vcc = 5.0 v, when a 32- khz crystal resonator is not used ? ? 350 a notes: 1. this voltage should be used when t he falling and rising voltage detection function is used. 2. select the low-voltage reset 2 when on ly the low-voltage detection reset is used. 3. when the power-supply voltage (vcc) falls below v lvdrmin = 1.0 v and then rises, a reset may not occur. therefore suffi cient evaluation is required.
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 442 of 526 rej09b0060-0300 23.2.8 power-on reset circuit characteristics (optional) table 23.10 power-on rese t circuit characteristics v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min. typ. max. unit pull-up resistance of res pin r res 100 150 ? k ? power-on reset start voltage * v por ? ? ? 100 mv note: * the power-supply voltage (vcc) must fall below vpor = 100 mv and then rise after charge of the res pin is removed completely. in order to remove charge of the res pin, it is recommended that the diode be placed in the vcc side. if the power-supply voltage (vcc) rises from the point over 100 mv, a power-on reset may not occur. 23.3 electrical characterist ics (masked rom version) 23.3.1 power supply voltage and operating ranges power supply voltage and os cillation frequency range 10.0 2.0 20.0 2.7 4.0 5.5 v cc (v) osc (mhz) 32.768 2.7 4.0 5.5 v cc (v) w (khz) av cc = 2.7 to 5.5 v active mode sleep mode av cc = 2.7 to 5.5 v all operating modes
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 443 of 526 rej09b0060-0300 power supply voltage and op erating frequency range 10.0 1.0 20.0 2.7 4.0 5.5 v cc (v) (mhz) 16.384 2.7 4.0 5.5 v cc (v) sub (khz) 8.192 4.096 1250 78.125 2500 2.7 4.0 5.5 v cc (v) (khz) av cc = 2.7 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 0) av cc = 2.7 to 5.5 v subactive mode subsleep mode av cc = 2.7 to 5.5 v active mode sleep mode (when ma2 in syscr2 = 1) analog power supply voltage and a/d converter accuracy guarantee range 10.0 2.0 20.0 3.0 4.0 5.5 av cc (v) (mhz) v cc = 2.7 to 5.5 v active mode sleep mode
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 444 of 526 rej09b0060-0300 range of power supply voltage and oscillat ion frequency when low-voltage detection circuit is used operation guarantee range operation guarantee range except a/d conversion accuracy 20.0 16.0 2.0 3.0 4.5 5.5 vcc(v) osc (mhz)
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 445 of 526 rej09b0060-0300 23.3.2 dc characteristics table 23.11 dc characteristics (1) v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol applicable pins test condition min. typ. max. unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg ,tmriv, v cc = 4.0 to 5.5 v v cc 0.8 ? v cc + 0.3 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, sck3, sck3_2, sck3_3, trgv, ftci, tmib1 v cc 0.9 ? v cc + 0.3 rxd, rxd_2, rxd_3, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37 v cc = 4.0 to 5.5 v v cc 0.7 ? v cc + 0.3 v p50 to p57, p60 to p67, p70 to p72, p74 to p77, p80 to p87, p90 to p97 v cc 0.8 ? v cc + 0.3 pb 0 to pb 7 v cc = 4.0 to 5.5 v v cc 0.7 ? av cc + 0.3 v v cc 0.8 ? av cc + 0.3 osc1 v cc = 4.0 to 5.5 v v cc ? 0.5 ? v cc + 0.3 v v cc ? 0.3 ? v cc + 0.3 note: connect the test pin to vss.
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 446 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg ,tmriv, v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.2 v tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, sck3, sck3_2, sck3_3, trgv, ftci, tmib1 ?0.3 ? v cc 0.1 rxd, rxd_2, rxd_3, scl, sda, p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.3 v p50 to p57, p60 to p67,. p70 to p72, p74 to p77, p80 to p87, p90 to p97 ?0.3 ? v cc 0.2 pb0 to pb7 v cc = 4.0 to 5.5 v ?0.3 ? v cc 0.3 v ?0.3 ? v cc 0.2 osc1 v cc = 4.0 to 5.5 v ?0.3 ? 0.5 v ?0.3 ? 0.3
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 447 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes output high voltage v oh p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc = 4.0 to 5.5 v ?i oh = 1.5 ma v cc ? 1.0 ? ? v p50 to p55, p60 to p67, p70 to p72, p74 to p76, p80 to p87, p90 to p97 ?i oh = 0.1 ma v cc ? 0.5 ? ? p56, p57 4.0 v v cc 5.5 v ?i oh = 0.1 ma v cc ? 2.5 ? ? v 2.0 v v cc < 4.0 v ?i oh = 0.1 ma v cc ? 2.0 ? ? output low voltage v ol p10 to p12, p14 to p17, p20 to p24, p30 to p37, v cc = 4.0 to 5.5 v i ol = 1.6 ma ? ? 0.6 v p50 to p57, p70 to p72, p74 to p77, p85 to p87, p90 to p97 i ol = 0.4 ma ? ? 0.4 p60 to p67, p80 to p84 v cc = 4.0 to 5.5 v i ol = 20.0 ma ? ? 1.5 v v cc = 4.0 to 5.5 v i ol = 10.0 ma ? ? 1.0 v cc = 4.0 to 5.5 v i ol = 1.6 ma ? ? 0.4 i ol = 0.4 ma ? ? 0.4 scl, sda v cc = 4.0 to 5.5 v i ol = 6.0 ma ? ? 0.6 v i ol = 3.0 ma ? ? 0.4
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 448 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes input/ output leakage current | i il | osc1, res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, rxd, sck3, rxd_2, sck3_2, rxd_3, sck3_3, scl, sda, tmib1, ftci v in = 0.5 v or higher (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p24, p30 to p37, p50 to p57, p60 to p67, p70 to p72, p74 to p77, p80 to p87, p90 to p97 v in = 0.5 v or higher (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v or higher (av cc ? 0.5 v) ? ? 1.0 a pull-up mos current ?i p p10 to p12, p14 to p17, v cc = 5.0 v, v in = 0.0 v 50.0 ? 300.0 a p50 to p55 v cc = 3.0 v, v in = 0.0 v ? 60.0 ? reference value pull-up mos resistance r res res ? 150 ? k ? input capaci- tance c in all input pins except power supply pins f = 1 mhz, v in = 0.0 v, t a = 25c ? ? 15.0 pf
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 449 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes i ope1 v cc active mode 1 v cc = 5.0 v, f osc = 20 mhz ? 25.0 36.0 ma * active mode supply current active mode 1 v cc = 3.0 v, f osc = 10 mhz ? 11.0 ? * reference value i ope2 v cc active mode 2 v cc = 5.0 v, f osc = 20 mhz ? 2.3 3.6 ma * active mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.3 ? * reference value i sleep1 v cc sleep mode 1 v cc = 5.0 v, f osc = 20 mhz ? 18.0 23.0 ma * sleep mode supply current sleep mode 1 v cc = 3.0 v, f osc = 10 mhz ? 8.0 ? * reference value i sleep2 v cc sleep mode 2 v cc = 5.0 v, f osc = 20 mhz ? 2.1 3.1 ma * sleep mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.2 ? * reference value i sub v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 35.0 70.0 a * subactive mode supply current v cc = 3.0 v 32-khz crystal resonator ( sub = w /8) ? 25.0 ? * reference value subsleep mode supply current i subsp v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 25.0 50.0 a *
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 450 of 526 rej09b0060-0300 values item symbol applicable pins test condition min. typ. max. unit notes standby mode supply current i stby v cc 32-khz crystal resonator not used ? ? 5.0 a ram data retaining voltage v ram v cc 2.0 ? ? v note: * pin states during supply current measurement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc main clock: ceramic or crystal resonator active mode 2 operates ( osc /64) subclock: pin x1 = v ss sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc /64) subactive mode v cc operates v cc main clock: ceramic or crystal resonator subsleep mode v cc only timers operate v cc subclock: crystal resonator standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator subclock: pin x1 = v ss
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 451 of 526 rej09b0060-0300 table 23.11 dc characteristics (2) v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values item symbol pins test condition min. typ. max. unit allowable output low current (per pin) i ol output pins except port 6, p80 to p84, scl, and sda v cc = 4.0 to 5.5 v ? ? 2.0 ma port 6, p80 to p84 ? ? 20.0 output pins except port 6, p80 to p84, scl, and sda ? ? 0.5 port 6, p80 to p84 ? ? 10.0 scl, sda ? ? 6.0 allowable output low current (total) i ol output pins except port 6, p80 to p84, scl, and sda v cc = 4.0 to 5.5 v ? ? 40.0 ma port 6, p80 to p84, scl, and sda ? ? 80.0 output pins except port 6, p80 to p84, scl, and sda ? ? 20.0 port 6, p80 to p84, scl, and sda ? ? 40.0 allowable output high ? ?i oh ? all output pins v cc = 4.0 to 5.5 v ? ? 2.0 ma current (per pin) ? ? 0.2 allowable output high ? ? i oh ? all output pins v cc = 4.0 to 5.5 v ? ? 30.0 ma current (total) ? ? 8.0
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 452 of 526 rej09b0060-0300 23.3.3 ac characteristics table 23.12 ac characteristics v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values reference item symbol pins test condition min. typ. max. unit figure system clock oscillation f osc osc1, osc2 v cc = 4.0 to 5.5 v 2.0 ? 20.0 mhz * 1 frequency 2.0 ? 10.0 system clock ( ) t cyc 1 ? 64 t osc * 2 cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * 2 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time t rcx x1, x2 ? ? 2.0 s external clock t cph osc1 v cc = 4.0 to 5.5 v 205.0 ? ? ns figure 23.1 high width 40.0 ? ? external clock t cpl osc1 v cc = 4.0 to 5.5 v 20.0 ? ? ns low width 40.0 ? ? external clock t cpr osc1 v cc = 4.0 to 5.5 v ? ? 10.0 ns rise time ? ? 15.0 external clock t cpf osc1 v cc = 4.0 to 5.5 v ? ? 10.0 ns fall time ? ? 15.0
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 453 of 526 rej09b0060-0300 applicable values reference item symbol pins test condition min. typ. max. unit figure res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 23.2 in active mode and sleep mode operation 200 ? ? ns input pin high width t ih nmi , tmbi1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, ftci 2 ? ? t cyc t subcyc figure 23.3 input pin low width t il nmi , tmbi1, irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftioa0 to ftiod0, ftioa1 to ftiod1, ftioa to ftiod, ftci 2 ? ? t cyc t subcyc notes: 1. when an external clock is input, the minimum system clock oscillation frequency is 1.0 mhz. 2. determined by the ma2, ma1, ma0, sa1, and sa0 bits in the system control register 2 (syscr2).
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 454 of 526 rej09b0060-0300 table 23.13 i 2 c bus interface timing v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. test values reference item symbol condition min. typ. max. unit figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 23.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns retransmission start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc +20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf v cc = 4.0 to 5.5 v ? ? 250 ns ? ? 300
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 455 of 526 rej09b0060-0300 table 23.14 serial communicati on interface (sci) timing v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable values reference item symbol pins test condition min. typ. max. unit figure asynchro- nous t scyc sck3 4 ? ? t cyc figure 23.5 input clock cycle clocked synchronous 6 ? ? input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc t txd txd v cc = 4.0 to 5.5 v ? ? 1 t cyc figure 23.6 transmit data delay time (clocked synchronous) ? ? 1 t rxs rxd v cc = 4.0 to 5.5 v 50.0 ? ? ns receive data setup time (clocked synchronous) 100.0 ? ? t rxh rxd v cc = 4.0 to 5.5 v 50.0 ? ? ns receive data hold time (clocked synchronous) 100.0 ? ?
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 456 of 526 rej09b0060-0300 23.3.4 a/d converter characteristics table 23.15 a/d converter characteristics v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable test values item symbol pins condition min. typ. max. unit notes analog power supply voltage av cc av cc 2.7 v cc 5.5 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 5.0 v f osc = 20 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf allowable signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 2.7 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb conversion time (single mode) av cc = 4.0 to 5.5 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 457 of 526 rej09b0060-0300 applicable test values item symbol pins condition min. typ. max. unit notes conversion time (single mode) av cc = 4.0 to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep m odes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 23.3.5 watchdog timer characteristics table 23.16 watchdog timer characteristics v cc = 2.7 to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. applicable test values item symbol pins condition min. typ. max. unit notes internal oscillator overflow time t ovf 0.2 0.4 ? s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 458 of 526 rej09b0060-0300 23.3.6 power-supply-voltage detection circuit characteristics (optional) table 23.17 power-supply-voltage de tection circuit characteristics v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min. typ. max. unit power-supply falling detection voltage vint (d) lvdsel = 0 3.3 3.7 ? v power-supply rising detection voltage vint (u) lvdsel = 0 ? 4.0 4.5 v reset detection voltage 1 * 1 vreset1 lvdsel = 0 ? 2.3 2.7 v reset detection voltage 2 * 2 vreset2 lvdsel = 1 3.0 3.6 4.2 v lower-limit voltage of lvdr operation * 3 v lvdrmin ? 1.0 ? ? v lvd stabilization time t lvdon ? 50 ? ? s supply current in standby mode i stby lvde = 1, vcc = 5.0 v, when a 32- khz crystal resonator is not used ? ? 350 a notes: 1. this voltage should be used when t he falling and rising voltage detection function is used. 2. select the low-voltage reset 2 when on ly the low-voltage detection reset is used. 3. when the power-supply voltage (vcc) falls below v lvdrmin = 1.0 v and then rises, a reset may not occur. therefore suffi cient evaluation is required.
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 459 of 526 rej09b0060-0300 23.3.7 power-on reset circuit characteristics (optional) table 23.18 power-on rese t circuit characteristics v ss = 0.0 v, t a = ?20 to +75c, unless otherwise indicated. values item symbol test condition min. typ. max. unit pull-up resistance of res pin r res 100 150 ? k ? power-on reset start voltage * v por ? ? ? 100 mv note: * the power-supply voltage (vcc) must fall below vpor = 100 mv and then rise after charge of the res pin is removed completely. in order to remove charge of the res pin, it is recommended that the diode be placed in the vcc side. if the power-supply voltage (vcc) rises from the point over 100 mv, a power-on reset may not occur. 23.4 operation timing t osc v ih v il t cph t cpl t cpr osc1 t cpf figure 23.1 system clock input timing t rel v il res t rel v il v cc 0.7 v cc osc1 figure 23.2 res low width timing
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 460 of 526 rej09b0060-0300 v ih v il t il nmi , irq0 to irq3 , wkp0 to wkp5 , adtrg , ftioa to ftiod, ftioa0 to ftiod0, ftioa1 to ftiod1, tmciv, tmriv, trgv, ftci, tmib1 t ih figure 23.3 input timing scl v ih v il t stah t buf p * s * t sf t scl t sdah t sclh t scll sda sr * t stas t sp t stos t sdas p * note: * s, p, and sr represent the following: s: start condition p: stop condition sr: retransmission start condition figure 23.4 i 2 c bus interface input/output timing t scyc t sckw sck3 figure 23.5 sck3 input clock timing
section 23 electrical characteristics rev. 3.00 mar. 15, 2006 page 461 of 526 rej09b0060-0300 t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * v ol * sck3 txd (transmit data) rxd (receive data) note: * output timing reference levels output high: output low: load conditions are shown in figure 23.7. v = 2.0 v v = 0.8 v oh ol figure 23.6 sci input/output ti ming in clocked synchronous mode 23.5 output load condition v cc 2.4 k ? 12 k ? 30 pf lsi output pin figure 23.7 output load circuit
section 23 electric al characteristics rev. 3.00 mar. 15, 2006 page 462 of 526 rej09b0060-0300
appendix rev. 3.00 mar. 15, 2006 page 463 of 526 rej09b0060-0300 appendix a. instruction set a.1 instruction list condition code symbol description rd general destination register rs general source register rn general register erd general destination register (address register or 32-bit register) ers general source register (addr ess register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides ? subtraction of the op erand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides
appendix rev. 3.00 mar. 15, 2006 page 464 of 526 rej09b0060-0300 symbol description logical exclusive or of the operands on both sides not (logical complement) ( ), < > contents of operand condition code notation (cont) symbol description ? changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 ? not affected by execution of the instruction ? varies depending on conditions, described in notes note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7).
appendix rev. 3.00 mar. 15, 2006 page 465 of 526 rej09b0060-0300 table a.1 instruction set 1. data transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) operation #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32?1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) b b b b b b b b b b b b b b b b w w w w w w w w w w w 2 4 2 2 2 2 2 2 4 8 4 8 4 8 4 8 2 2 2 2 4 6 2 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov
appendix rev. 3.00 mar. 15, 2006 page 466 of 526 rej09b0060-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 operation erd32?2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 erd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32?4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp sp?2 sp rn16 @sp sp?4 sp ern32 @sp cannot be used in this lsi cannot be used in this lsi w w w l l l l l l l l l l l l l l w l w l b b 6 2 4 4 6 10 6 10 2 4 4 4 6 6 8 6 8 4 4 2 4 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used in this lsi cannot be used in this lsi mov pop push movfpe movtpe
appendix rev. 3.00 mar. 15, 2006 page 467 of 526 rej09b0060-0300 2. arithmetic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd operation rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8?rs8 rd8 rd16?#xx:16 rd16 rd16?rs16 rd16 erd32?#xx:32 erd32 erd32?ers32 erd32 rd8?#xx:8?c rd8 rd8?rs8?c rd8 erd32?1 erd32 erd32?2 erd32 erd32?4 erd32 rd8?1 rd8 rd16?1 rd16 rd16?2 rd16 b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w 2 4 6 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? ? ? ? * (1) (1) (2) (2) ? ? ? ? ? ? 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (3) (3) ? ? ? (3) (3) ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? add addx adds inc daa sub subx subs dec
appendix rev. 3.00 mar. 15, 2006 page 468 of 526 rej09b0060-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd operation erd32?1 erd32 erd32?2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsigned multiplication) rd16 rs16 erd32 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) rd16 rs16 erd32 (signed multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (signed division) rd8?#xx:8 rd8?rs8 rd16?#xx:16 rd16?rs16 erd32?#xx:32 erd32?ers32 l l b b w b w b w b w b b w w l l 2 4 6 2 2 2 2 2 4 4 2 2 4 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 14 22 16 24 14 22 16 24 2 2 4 2 4 2 normal advanced ? ? ? ? ? * ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (7) (7) (7) (7) ? ? (6) (6) (8) (8) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dec das mulxu mulxs divxu divxs cmp
appendix rev. 3.00 mar. 15, 2006 page 469 of 526 rej09b0060-0300 mnemonic operation operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd 0?rd8 rd8 0?rd16 rd16 0?erd32 erd32 0 ( of rd16) 0 ( of erd32) ( of rd16) ( of rd16) ( of erd32) ( of erd32) b w l w l w l 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? neg extu exts
appendix rev. 3.00 mar. 15, 2006 page 470 of 526 rej09b0060-0300 3. logic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd operation rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 ? #xx:8 rd8 rd8 ? rs8 rd8 rd16 ? #xx:16 rd16 rd16 ? rs16 rd16 erd32 ? #xx:32 erd32 erd32 ? ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ~ rd8 rd8 ~ rd16 rd16 ~ rd32 rd32 b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? and or xor not
appendix rev. 3.00 mar. 15, 2006 page 471 of 526 rej09b0060-0300 4. shift instructions mnemonic operand size no. of states * 1 condition code ihnzvc shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 operation msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb c msb lsb c msb lsb c msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? shal shar shll shlr rotxl rotxr rotl rotr
appendix rev. 3.00 mar. 15, 2006 page 472 of 526 rej09b0060-0300 5. bit-manipulation instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd operation (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ~ (#xx:3 of rd8) (#xx:3 of @erd) ~ (#xx:3 of @erd) (#xx:3 of @aa:8) ~ (#xx:3 of @aa:8) (rn8 of rd8) ~ (rn8 of rd8) (rn8 of @erd) ~ (rn8 of @erd) (rn8 of @aa:8) ~ (rn8 of @aa:8) ~ (#xx:3 of rd8) z ~ (#xx:3 of @erd) z ~ (#xx:3 of @aa:8) z ~ (rn8 of @rd8) z ~ (rn8 of @erd) z ~ (rn8 of @aa:8) z (#xx:3 of rd8) c b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bset bclr bnot btst bld
appendix rev. 3.00 mar. 15, 2006 page 473 of 526 rej09b0060-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 operation (#xx:3 of @erd) c (#xx:3 of @aa:8) c ~(#xx:3 of rd8) c ~ (#xx:3 of @erd) c ~(#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) ~ c (#xx:3 of rd8) ~ c (#xx:3 of @erd24) ~ c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ~ (#xx:3 of rd8) c c ~ (#xx:3 of @erd24) c c ~ (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ~ (#xx:3 of rd8) c c ~ (#xx:3 of @erd24) c c ~ (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ~(#xx:3 of rd8) c c ~(#xx:3 of @erd24) c c ~ (#xx:3 of @aa:8) c b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bld bild bist bst band biand bor bior bxor bixor
appendix rev. 3.00 mar. 15, 2006 page 474 of 526 rej09b0060-0300 6. branching instructions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size no. of states * 1 condition code ihnzvc bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 normal advanced addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 operation always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 if condition is true then pc pc+d else next; branch condition bcc
appendix rev. 3.00 mar. 15, 2006 page 475 of 526 rej09b0060-0300 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts operation pc ern pc aa:24 pc @aa:8 pc @?sp pc pc+d:8 pc @?sp pc pc+d:16 pc @?sp pc ern pc @?sp pc aa:24 pc @?sp pc @aa:8 pc @sp+ ? ? ? ? ? ? ? ? ? 2 2 4 4 2 4 2 2 2 ? ? ? ? ? ? ? ? ? 4 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 6 8 6 8 8 8 10 8 10 8 10 12 10 jmp bsr jsr rts
appendix rev. 3.00 mar. 15, 2006 page 476 of 526 rej09b0060-0300 7. system control instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop operation pc @?sp ccr @?sp pc ccr @sp+ pc @sp+ transition to power- down state #xx:8 ccr rs8 ccr @ers ccr @(d:16, ers) ccr @(d:24, ers) ccr @ers ccr ers32+2 ers32 @aa:16 ccr @aa:24 ccr ccr rd8 ccr @erd ccr @(d:16, erd) ccr @(d:24, erd) erd32?2 erd32 ccr @erd ccr @aa:16 ccr @aa:24 ccr #xx:8 ccr ccr #xx:8 ccr ccr #xx:8 ccr pc pc+2 ? ? ? b b w w w w w w b w w w w w w b b b ? 2 2 2 2 2 2 4 4 6 10 6 10 4 4 6 8 6 8 2 2 1 ? ? ? ? ? ? ? ? ? 10 2 2 2 6 8 12 8 8 10 2 6 8 12 8 8 10 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 14 16 trapa rte sleep ldc stc andc orc xorc nop
appendix rev. 3.00 mar. 15, 2006 page 477 of 526 rej09b0060-0300 8. block transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? eepmov. b eepmov. w operation if r4l 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l?1 r4l until r4l=0 else next if r4 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4?1 r4 until r4=0 else next ? ? 4 4 ? ? 8+ 4n * 2 normal advanced ? ? ? ? ? ? ? ? ? ?8+ 4n * 2 eepmov notes: 1. the number of states in cases wher e the instruction code and its operands are located in on-chip memory is shown here. for ot her cases, see appendix a.3, number of execution states. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for executi on of an instruction t hat transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0.
appendix rev. 3.00 mar. 15, 2006 page 478 of 526 rej09b0060-0300 a.2 operation code map table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc beq trapa bld bild bst bist bvc mov bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) bvs blt bge bsr table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (2) table a.2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp mov.b
appendix rev. 3.00 mar. 15, 2006 page 479 of 526 rej09b0060-0300 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a.2 (3) table a.2 (3) table a.2 (3) add mov sub cmp bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl sub adds shll shlr rotxl rotxr not shal shar rotl rotr neg
appendix rev. 3.00 mar. 15, 2006 page 480 of 526 rej09b0060-0300 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divxs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc
appendix rev. 3.00 mar. 15, 2006 page 481 of 526 rej09b0060-0300 a.3 number of execution states the status of execution for each instruction of the h8/300h cpu and the method of calculating the number of states required for instructio n execution are shown belo w. table a.4 shows the number of cycles of each type occurring in each instruction, such as in struction fetch and data read/write. table a.3 shows the number of states required for each cycle. the total number of states required for execution of an instruction can be calculated by the following expression: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chi p rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8
appendix rev. 3.00 mar. 15, 2006 page 482 of 526 rej09b0060-0300 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip me mory on-chip peripheral module instruction fetch s i 2 ? branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m ? internal operation s n 1 note: * depends on which on-chip peripheral module is accessed. see section 22.1, register addresses (address order).
appendix rev. 3.00 mar. 15, 2006 page 483 of 526 rej09b0060-0300 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 2 2 2 2 2 2 2 2 2 2 2 2 2
appendix rev. 3.00 mar. 15, 2006 page 484 of 526 rej09b0060-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc blt d:8 bgt d:8 ble d:8 bra d:16(bt d:16) brn d:16(bf d:16) bhi d:16 bls d:16 bcc d:16(bhs d:16) bcs d:16(blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1
appendix rev. 3.00 mar. 15, 2006 page 485 of 526 rej09b0060-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bior bior #xx:8, rd bior #xx:8, @erd bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 bsr d:16 2 2 1 1 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2
appendix rev. 3.00 mar. 15, 2006 page 486 of 526 rej09b0060-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 divxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n+2 * 1 2n+2 * 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1
appendix rev. 3.00 mar. 15, 2006 page 487 of 526 rej09b0060-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern jmp @aa:24 jmp @@aa:8 2 2 2 1 2 2 jsr jsr @ern jsr @aa:24 jsr @@aa:8 2 2 2 1 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc@ers, ccr ldc@(d:16, ers), ccr ldc@(d:24,ers), ccr ldc@ers+, ccr ldc@aa:16, ccr ldc@aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @-erd mov.b rs, @aa:8 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2
appendix rev. 3.00 mar. 15, 2006 page 488 of 526 rej09b0060-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16,ers), rd mov.w @(d:24,ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16,erd) mov.w rs, @(d:24,erd) 2 3 2 1 1 2 4 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 2 mov mov.w rs, @-erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16,ers), erd mov.l @(d:24,ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers,@erd mov.l ers, @(d:16,erd) mov.l ers, @(d:24,erd) mov.l ers, @-erd mov.l ers, @aa:16 mov.l ers, @aa:24 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 movfpe movfpe @aa:16, rd * 2 2 1 movtpe movtpe rs,@aa:16 * 2 2 1
appendix rev. 3.00 mar. 15, 2006 page 489 of 526 rej09b0060-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1
appendix rev. 3.00 mar. 15, 2006 page 490 of 526 rej09b0060-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16,erd) stc ccr, @(d:24,erd) stc ccr,@-erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1
appendix rev. 3.00 mar. 15, 2006 page 491 of 526 rej09b0060-0300 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n subx subx #xx:8, rd subx. rs, rd 1 1 trapa trapa #xx:2 2 1 2 4 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: 1. n: specified value in r4l and r4. the source and destination operands are accessed n+1 times respectively. 2. cannot be used in this lsi.
appendix rev. 3.00 mar. 15, 2006 page 492 of 526 rej09b0060-0300 a.4 combinations of instructions and addressing modes table a.5 combinations of instructions and addressing modes addressing mode mov pop, push movfpe, movtpe add, cmp sub addx, subx adds, subs inc, dec daa, das mulxu, mulxs, divxu, divxs neg extu, exts and, or, xor not bcc, bsr jmp, jsr rts trapa rte sleep ldc stc andc, orc, xorc nop data transfer instructions arithmetic operations logical operations shift operations bit manipulations branching instructions system control instructions block data transfer instructions bwl ? ? bwl wl b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? b ? ? #xx rn @ern @(d:16.ern) @(d:24.ern) @ern+/@ern @aa:8 @aa:16 @aa:24 @(d:8.pc) @(d:16.pc) @@aa:8 ? bwl ? ? bwl bwl b l bwl b bw bwl wl bwl bwl bwl b ? ? ? ? ? ? b b ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? b ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw functions instructions
appendix rev. 3.00 mar. 15, 2006 page 493 of 526 rej09b0060-0300 b. i/o ports b.1 i/o port block diagrams res goes low in a reset, and sby goes low at reset and in standby mode. pdr pucr pmr pcr sby res pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register irq trgv internal data bus pull-up mos [legend] figure b.1 port 1 block diagram (p17)
appendix rev. 3.00 mar. 15, 2006 page 494 of 526 rej09b0060-0300 pdr pucr pmr pcr sby res irq internal data bus pull-up mos pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register [legend] figure b.2 port 1 block diagram (p14, p16)
appendix rev. 3.00 mar. 15, 2006 page 495 of 526 rej09b0060-0300 pdr pucr pmr pcr sby res internal data bus pull-up mos irq tmib1 pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register [legend] figure b.3 port 1 block diagram (p15) pucr: pdr: pcr: port pull-up control register port data register port control register [legend] pdr pucr pcr sby res internal data bus pull-up mos figure b.4 port 1 block diagram (p12)
appendix rev. 3.00 mar. 15, 2006 page 496 of 526 rej09b0060-0300 pdr pucr pmr pcr sby res pwm 14-bit pwm internal data bus pull-up mos pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register [legend] figure b.5 port 1 block diagram (p11)
appendix rev. 3.00 mar. 15, 2006 page 497 of 526 rej09b0060-0300 pdr pucr pmr pcr sby res internal data bus pull-up mos tmow rtc pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register [legend] figure b.6 port 1 block diagram (p10) pdr pmr pcr sby internal data bus pucr: pdr: pcr: port pull-up control register port data register port control register [legend] figure b.7 port 2 block diagram (p24, p23)
appendix rev. 3.00 mar. 15, 2006 page 498 of 526 rej09b0060-0300 pdr pmr pcr sby txd sci3 internal data bus pmr: pdr: pcr: port mode register port data register port control register [legend] figure b.8 port 2 block diagram (p22) pdr pcr sby re internal data bus rxd sci3 pdr: pcr: port data register port control register [legend] figure b.9 port 2 block diagram (p21)
appendix rev. 3.00 mar. 15, 2006 page 499 of 526 rej09b0060-0300 pdr pcr sby sckie internal data bus scki sci3 sckoe scko pdr: pcr: port data register port control register [legend] figure b.10 port 2 block diagram (p20) pdr pcr sby internal data bus pdr: pcr: port data register port control register [legend] figure b.11 port 3 block diagram (p37 to p30)
appendix rev. 3.00 mar. 15, 2006 page 500 of 526 rej09b0060-0300 pdr pmr pcr sby ice sdao/sclo sdai/scli iic2 internal data bus pmr: pdr: pcr: port mode register port data register port control register [legend] figure b.12 port 5 block diagram (p57, p56)
appendix rev. 3.00 mar. 15, 2006 page 501 of 526 rej09b0060-0300 pdr pucr pmr pcr sby res adtrg wkp5 internal data bus pull-up mos pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register [legend] figure b.13 port 5 block diagram (p55)
appendix rev. 3.00 mar. 15, 2006 page 502 of 526 rej09b0060-0300 pdr pucr pmr pcr sby res wkp internal data bus pull-up mos pucr: pmr: pdr: pcr: port pull-up control register port mode register port data register port control register [legend] figure b.14 port 5 block diagram (p54 to p50)
appendix rev. 3.00 mar. 15, 2006 page 503 of 526 rej09b0060-0300 pdr pcr sby ftioa to ftiod output control signals a to d timer z internal data bus pdr: pcr: port data register port control register [legend] figure b.15 port 6 block diagram (p67 to p60) pdr pcr sby internal data bus pdr: pcr: port data register port control register [legend] figure b.16 port 7 block diagram (p77)
appendix rev. 3.00 mar. 15, 2006 page 504 of 526 rej09b0060-0300 pdr pcr sby os3 os2 os1 os0 tmov internal data bus timer v pdr: pcr: port data register port control register [legend] figure b.17 port 7 block diagram (p76) pdr pcr sby tmciv internal data bus timer v pdr: pcr: port data register port control register [legend] figure b.18 port 7 block diagram (p75)
appendix rev. 3.00 mar. 15, 2006 page 505 of 526 rej09b0060-0300 pdr pcr sby tmriv internal data bus timer v pdr: pcr: port data register port control register [legend] figure b.19 port 7 block diagram (p74)
appendix rev. 3.00 mar. 15, 2006 page 506 of 526 rej09b0060-0300 pdr pmr pcr sby internal data bus txd sci3_2 pmr: pdr: pcr: port mode register port data register port control register [legend] figure b.20 port 7 block diagram (p72) pdr pcr sby re rxd sci3_2 internal data bus pdr: pcr: port data register port control register [legend] figure b.21 port 7 block diagram (p71)
appendix rev. 3.00 mar. 15, 2006 page 507 of 526 rej09b0060-0300 pdr pcr sby sckie scki sci3_2 sckoe scko internal data bus pdr: pcr: port data register port control register [legend] figure b.22 port 7 block diagram (p70) pdr pcr sby internal data bus pdr: pcr: port data register port control register [legend] figure b.23 port 8 block diagram (p87 to p85)
appendix rev. 3.00 mar. 15, 2006 page 508 of 526 rej09b0060-0300 pdr pcr sby ftioa to ftiod output control signals a to d timer w internal data bus pdr: pcr: port data register port control register [legend] figure b.24 port 8 block diagram (p84 to p81) pdr pcr sby internal data bus timer w ftci pdr: pcr: port data register port control register [legend] figure b.25 port8 block diagram (p80)
appendix rev. 3.00 mar. 15, 2006 page 509 of 526 rej09b0060-0300 pdr pcr internal data bus pdr: pcr: port data register port control register [legend] figure b.26 port 9 block diagram (p97 to p93) pdr smcr pcr sby internal data bus txd sci3_3 smcr: pdr: pcr: serial module control register port data register port control register [legend] figure b.27 port 9 block diagram (p92)
appendix rev. 3.00 mar. 15, 2006 page 510 of 526 rej09b0060-0300 pdr pcr sby re rxd sci3_3 internal data bus pdr: pcr: port data register port control register [legend] figure b.28 port 9 block diagram (p91) pdr pcr sby sckie scki sci3_3 sckoe scko internal data bus pdr: pcr: port data register port control register [legend] figure b.29 port 9 block diagram (p90)
appendix rev. 3.00 mar. 15, 2006 page 511 of 526 rej09b0060-0300 dec a/d converter internal data bus v in ch3 to ch0 figure b.30 port b block diagram (pb7 to pb0) b.2 port states in each operating mode port reset sleep subsleep standby subactive active p17 to p14, p12 to p10 high impedance retained retained high impedance * functioning functioning p24 to p20 high impedance retained retained high impedance functioning functioning p37 to p30 high impedance retained retained high impedance functioning functioning p57 to p50 high impedance retained retained high impedance * functioning functioning p67 to p60 high impedance retained retained high impedance functioning functioning p76 to p74, p72 to p70 high impedance retained retained high impedance functioning functioning p87 to p80 high impedance retained retained high impedance functioning functioning p97 to p90 high impedance retained retained high impedance functioning functioning pb7 to pb0 high impedance high impedance high impedance high impedance high impedance high impedance note: * high level output when the pul l-up mos is in on state.
appendix rev. 3.00 mar. 15, 2006 page 512 of 526 rej09b0060-0300 c. product code lineup product classification product code model marking package (package code) h8/36049 flash memory version product with por & lvdc hd64f36049gh hd64f36049gh standard product HD64F36049H HD64F36049H masked rom version product with por & lvdc hd64336049gh hd64336049( *** )gh standard product hd64336049h hd64336049( *** )h h8/36048 masked rom version product with por & lvdc hd64336048gh hd64336048( *** )gh standard product hd64336048h hd64336048( *** )h h8/36047 masked rom version product with por & lvdc hd64336047gh hd64336047( *** )gh standard product hd64336047h hd64336047( *** )h qfp-80 (fp-80a) [legend] ( *** ): rom code por & lvdc: power-on reset and low-voltage detection circuits
appendix rev. 3.00 mar. 15, 2006 page 513 of 526 rej09b0060-0300 d. package dimensions the package dimensions that are shown in the renesas semiconductor packages data book have priority. package code jedec jeita mass (reference value) fp-80a ? conforms 1.2 g * dimension including the plating thickness base material dimension 60 0? ? 8? 0.10 0.12 m 17.2 0.3 41 61 80 1 20 40 21 17.2 0.3 * 0.32 0.08 0.65 3.05 max 1.6 0.8 0.3 14 2.70 * 0.17 0.05 0.10 +0.15 ?0.10 0.83 0.30 0.06 0.15 0.04 unit: mm figure d.1 fp-80a package dimensions
appendix rev. 3.00 mar. 15, 2006 page 514 of 526 rej09b0060-0300
rev. 3.00 mar. 15, 2006 page 515 of 526 rej09b0060-0300 main revisions and add itions in this edition item page revision (see manual for details) preface notes vii added when using an on-chip emulator (e7 or e8) for h8/36049 group program development and debugging, the following restrictions must be noted. 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 2. pins p85, p86, and p87 cannot be used. 3. area h'fff780 to h'fffb7f must on no account be accessed. 4. when the e7 or e8 is used, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7 or e8, the address break control registers must not be accessed. 5. when the e7 or e8 is used, nmi is an input/output pin (open-drain in output mode), p85 and p87 are input pins, and p86 is an output pin. amended bit bit name description 3 nesel noise elim ination sampling frequency select ?. this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 20 mhz, clear nesel to 0. 6.1.1 system control register 1 (syscr1) 76
rev. 3.00 mar. 15, 2006 page 516 of 526 rej09b0060-0300 item page revision (see manual for details) 6.4.1 direct transition from active mode to subactive mode 86 amended example : direct transition time = (2 + 1) tosc + 16 8 tw = 3 tosc + 128 tw (when the cpu operating clock of osc w /8 is selected) 6.4.2 direct transition from subactive mode to active mode 87 amended example : direct transition time = (2 + 1) 8 tw + (8192 + 16) tosc = 24 tw + 8208 tosc (when the cpu operating clock of w /8 osc and a waiting time of 8192 states are selected) section 8 ram 109 added note: * when the e7 or e8 is used, area h'fff780 to h'fffb7f must not be accessed. amended register tmrw bit name pwmd 9.7.3 pin functions ? p84/ftiod pin 139 amended register tmrw bit name pwmc 9.7.3 pin functions ? p83/ftioc pin 140 amended register tmrw bit name pwmb 9.7.3 pin functions ? p82/ftiob pin 140
rev. 3.00 mar. 15, 2006 page 517 of 526 rej09b0060-0300 item page revision (see manual for details) amended bit bit name description 0 sync timer synchronization 0: tcnt_1 and tcnt_0 operate as a different timer 1: tcnt_1 and tcnt_0 are synchronized tcnt_1 and tcnt_0 can be pre-set or cleared synchronously 14.3.2 timer mode register (tmdr) 221 14.3.7 timer counter (tcnt) 228 ?.the tcnt counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. tcnt is initialized to h'0000. figure 14.17 example of input capture operation 245 amended counter cleared by ftiob input (falling edge) time 14.4.4 synchronous operation 248 added figure 14.20 shows an example of synchronous operation. in this example, ?. set for the channel 1 counter clearing source. in addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. two-phase pwm waveforms are?.
rev. 3.00 mar. 15, 2006 page 518 of 526 rej09b0060-0300 item page revision (see manual for details) figure 14.44 example of output disable timing of timer z by writing to toer 276 amended t 1 t 2 toer address bus toer address timer z output pin timer z output i/o port i/o port timer output figure 14.45 example of output disable timing of timer z by external trigger 277 amended wkp4 toer timer z output pin timer z output i/o port n h'ff amended bit bit name description 4 tcsrwe timer control/status register wd write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the value for bit 5 must be 0. 15.2.1 timer control/status register wd (tcsrwd 290
rev. 3.00 mar. 15, 2006 page 519 of 526 rej09b0060-0300 item page revision (see manual for details) amended bit bit name description 3 stop stop condition detection flag [setting conditions] ? in master mode, when a stop condition is detected after frame transfer ? in slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in sar 18.3.5 i 2 c bus status register (icsr) 353 18.7 usage note 375 added 19.3.1 a/d data registers a to d (addra to addrd) 380 amended ?. the temporary register contents are transferred from the addr when the upper byte data is read. therefore, byte access to addr should be done by reading the upper byte first then the lower one. word access is also possible. addr is initialized to h'0000. figure 20.1 block diagram of power-on reset circuit and low- voltage detection circuit 392 amended res c res amended mode res pin internal state active mode 1 operates active mode 2 v cc operates ( osc /64) sleep mode 1 only timers operate sleep mode 2 v cc only timers operate ( osc /64) table 23.2 dc characteristics (1) table 23.11 dc characteristics (1) 431, 450
rev. 3.00 mar. 15, 2006 page 520 of 526 rej09b0060-0300 item page revision (see manual for details) figure 23.4 i 2 c bus interface input/output timing 460 deleted scl v ih v il t stah t buf p * s * t sf t sr t scl t sclh t scll sda table a.1 instruction set 2. arithmetic instructions 467 amended mnemonic operand size no. of states * 1 condition code ihnzvc daa rd b ? * * 2 normal advanced ? ? ? daa
rev. 3.00 mar. 15, 2006 page 521 of 526 rej09b0060-0300 index numerics 14-bit pwm ............................................ 295 a a/d converter ......................................... 377 absolute address....................................... 29 acknowledge .......................................... 358 address break ........................................... 63 addressing modes..................................... 28 arithmetic operations instructions............ 20 asynchronous mode ............................... 318 auto-reload timer operation ................... 164 b bit manipulation instructions.................... 23 bit rate .................................................... 309 bit synchronous circuit ........................... 374 block data transfer instructions ................ 26 boot mode ................................................ 95 boot program............................................ 95 branch instructions ................................... 25 break....................................................... 339 buffer operation...................................... 268 c clock pulse generators.............................. 69 clock synchronous serial format ............ 366 clocked synchronous mode.................... 326 combinations of instructions and addressing modes.................................... 492 complementary pwm mode .................. 258 condition fi eld.......................................... 27 condition-code register (ccr)................. 13 cpu ............................................................ 9 d data reading procedure ........................... 158 data transfer instructions .......................... 19 e effective address....................................... 31 effective address extension....................... 27 erase/erase-verify ................................... 103 erasing units ............................................. 90 error protection....................................... 105 event counter operation .......................... 164 exception handling ................................... 43 f flash memory ........................................... 89 framing error .......................................... 322 g general registers ....................................... 12 h hardware protection................................ 105 i i/o port block diagrams .......................... 493 i/o ports .................................................. 111 i 2 c bus format ........................................ 357 i 2 c bus interface 2 (iic2)........................ 341 immediate ................................................. 30 initial setting procedure .......................... 157 input capture function ............................. 244 instruction list ......................................... 463
rev. 3.00 mar. 15, 2006 page 522 of of 526 rej09b0060-0300 instruction set ........................................... 18 internal interrupts ..................................... 57 internal power supply step-down circuit...................................................... 401 interrupt mask bit (i)................................. 13 interrupt response tme .............................. 59 interval timer operation .......................... 163 irq3 to irq0 interrupts ........................... 55 l large current ports...................................... 2 logic operations instructions.................... 22 low-voltage detec tion circuit .................. 391 lvdi ...................................................... 398 lvdi (interrupt by low voltage detect) circuit...................................................... 398 lvdr ..................................................... 397 lvdr (reset by low voltage detect) circuit...................................................... 397 m mark state ............................................... 339 memory indirect ....................................... 30 memory map ............................................ 10 module standby function .......................... 87 multiprocessor communication function................................................... 332 n nmi interrupt............................................ 55 noise canceler ........................................ 368 noise canceller ....................................... 301 number of execution states .................... 481 o on-board programming modes ................. 95 operation code map ................................ 478 operation field .......................................... 27 overrun error .......................................... 322 p package ....................................................... 2 package dimensions................................ 513 parity error .............................................. 322 pin arrangement .......................................... 4 power-down modes................................... 75 power-down st ates .................................. 106 power-on reset......................................... 391 power-on reset circuit ............................. 396 prescaler s ................................................ 73 prescaler w ............................................... 73 product code lineup ................................ 512 program counter (pc) ............................... 13 program/progra m-verify ......................... 100 program-counter relative .......................... 30 programmer mode................................... 106 programming units.................................... 90 programming/erasing in user program mode ......................................................... 98 pwm mode............................................. 248 pwm operation....................................... 199 r realtime cloc k (rtc) ............................. 147 register addresses................................... 404 register bits ............................................ 411 register direct ........................................... 28 register field............................................. 27 register indirect........................................ 28
rev. 3.00 mar. 15, 2006 page 523 of 526 rej09b0060-0300 register indirect w ith displacement.......... 29 register indirect w ith post-increment....... 29 register indirect with pre-decrement........ 29 register settings...................................... 297 register states in each operating mode ....................................................... 417 registers abrkcr................ 64, 66, 409, 415, 420 abrksr ...................... 66, 409, 415, 420 adcr ......................... 382, 408, 414, 420 adcsr....................... 381, 408, 414, 420 addra ...................... 380, 408, 414, 419 addrb ...................... 380, 408, 414, 419 addrc ...................... 380, 408, 414, 419 addrd ...................... 380, 408, 414, 420 bare ........................... 66, 409, 415, 420 barh ........................... 66, 409, 415, 420 barl ........................... 66, 409, 415, 420 bdrh ........................... 66, 409, 415, 420 bdrl ........................... 66, 409, 415, 420 brr ............................ 309, 407, 414, 419 ebr1 ............................ 93, 407, 414, 419 fenr............................ 94, 407, 414, 419 flmcr1....................... 91, 407, 414, 419 flmcr2....................... 92, 407, 414, 419 flpwcr ...................... 94, 407, 414, 419 gra........................... 193, 228, 404, 407, .................................... 411, 413, 417, 419 grb........................... 193, 228, 404, 407, .................................... 411, 413, 417, 419 grc........................... 193, 228, 404, 407, .................................... 411, 413, 417, 419 grd........................... 193, 228, 404, 407, .................................... 411, 414, 417, 419 iccr1......................... 344, 406, 413, 418 iccr2......................... 347, 406, 413, 418 icdrr........................ 356, 406, 413, 418 icdrs ................................................ 356 icdrt ........................ 356, 406, 413, 418 icier.......................... 350, 406, 413, 418 icmr .......................... 348, 406, 413, 418 icsr.................... 352, 406, 413, 418, 518 iegr1 ........................... 47, 410, 416, 421 iegr2 ........................... 48, 410, 416, 421 ienr1 ........................... 49, 410, 416, 421 ienr2 ........................... 50, 410, 416, 421 irr1.............................. 50, 410, 416, 421 irr2.............................. 52, 410, 416, 421 iwpr ............................ 53, 410, 416, 421 lvdcr....................... 393, 406, 412, 418 lvdsr ....................... 395, 406, 412, 418 mstcr1....................... 79, 410, 416, 421 mstcr2....................... 80, 410, 416, 421 pcr1........................... 113, 410, 415, 420 pcr2........................... 117, 410, 415, 421 pcr3........................... 120, 410, 415, 421 pcr5........................... 125, 410, 415, 421 pcr6........................... 129, 410, 416, 421 pcr7........................... 134, 410, 416, 421 pcr8........................... 138, 410, 416, 421 pcr9........................... 142, 410, 416, 421 pdr1........................... 113, 409, 415, 420 pdr2........................... 117, 409, 415, 420 pdr3........................... 121, 409, 415, 420 pdr5........................... 125, 409, 415, 420 pdr6........................... 130, 409, 415, 420 pdr7........................... 135, 409, 415, 420 pdr8........................... 138, 409, 415, 420 pdr9........................... 142, 409, 415, 420 pdrb .......................... 145, 409, 415, 420 pmr1 .......................... 112, 409, 415, 420 pmr3 .......................... 118, 410, 415, 420 pmr5 .......................... 124, 409, 415, 420 pocr .......................... 235, 404, 411, 417 pucr1 ........................ 114, 409, 415, 420 pucr5 ........................ 126, 409, 415, 420 pwcr ......................... 296, 408, 415, 420 pwdrl ...................... 297, 408, 415, 420 pwdru ...................... 297, 408, 415, 420 rdr ............................ 303, 408, 414, 419
rev. 3.00 mar. 15, 2006 page 524 of of 526 rej09b0060-0300 rhrdr .......................151, 405, 412, 418 rmindr .....................150, 405, 412, 418 rsecdr......................149, 405, 412, 418 rsr .................................................... 303 rtccr1 ......................153, 405, 412, 418 rtccr2 ......................155, 406, 412, 418 rtccsr......................156, 406, 412, 418 rwkdr ......................152, 405, 412, 418 sar .............................355, 406, 413, 418 scr3 ...........................306, 408, 414, 419 smcr..........................301, 404, 411, 417 smr.............................304, 407, 414, 419 ssr..............................307, 408, 414, 419 syscr1 ........................76, 410, 416, 421 syscr2 ........................77, 410, 416, 421 tcb1 ...........................163, 406, 413, 418 tcnt..........................192, 228, 404, 407, .....................................411, 413, 417, 419 tcntv........................167, 407, 414, 419 tcora .......................168, 407, 414, 419 tcorb........................168, 407, 414, 419 tcr .............................229, 404, 411, 417 tcrv0 ........................169, 407, 414, 419 tcrv1 ........................172, 407, 414, 419 tcrw .........................186, 407, 413, 419 tcsrv ........................170, 407, 414, 419 tcsrwd ....................290, 408, 415, 420 tcwd .........................292, 408, 415, 420 tdr .............................304, 408, 414, 419 tfcr ...........................223, 405, 412, 418 tier ............................234, 404, 411, 417 tierw ........................187, 407, 413, 419 tior0..........................189, 407, 413, 419 tior1..........................191, 407, 413, 419 tiora.........................230, 404, 411, 417 tiorc .........................231, 404, 411, 417 tlb1 ...........................163, 406, 413, 418 tmb1 ..........................162, 406, 413, 418 tmdr .........................221, 405, 412, 418 tmrw.........................185, 407, 413, 419 tmwd........................ 292, 408, 415, 420 tocr.......................... 227, 405, 412, 418 toer.......................... 225, 405, 412, 418 tpmr ......................... 222, 405, 412, 418 tsr ............................. 232, 404, 411, 417 tsrw ......................... 188, 407, 413, 419 tstr........................... 220, 405, 412, 418 reset exception handling .......................... 54 reset synchronous pwm mode .............. 254 s sample-and-hold circuit.......................... 385 scan mode............................................... 384 serial communication interface 3 (sci3) ..................................................... 299 shift instructions ....................................... 22 single mode ............................................ 384 slave address .......................................... 358 sleep mode................................................ 84 software protection................................. 105 stack pointer (sp) ..................................... 12 stack status ............................................... 57 standby mode ........................................... 84 start cond ition......................................... 358 stop cond ition ......................................... 358 subactive mode......................................... 85 subclock generator ................................... 72 subsleep mode .......................................... 85 synchronous op eration............................ 247 system clock generator ............................. 70 system control instructions....................... 26 t timer b1................................................. 161 timer v................................................... 165 timer w.................................................. 181 timer z ................................................... 213 transfer rate............................................ 346
rev. 3.00 mar. 15, 2006 page 525 of 526 rej09b0060-0300 trap instruction......................................... 43 v vector address .......................................... 44 w watchdog timer....................................... 289 waveform output .................................... 298 waveform output by compare match...... 241 wkp5 to wkp0 interrupts ....................... 56
rev. 3.00 mar. 15, 2006 page 526 of of 526 rej09b0060-0300
renesas 16-bit single-chip microcomputer hardware manual h8/36049 group publication date: rev.1.00, aug. 28, 2003 rev.3.00, mar. 15, 2006 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2006. renesas technology corp., all rights reserved. printed in japan.
sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0

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