agilent hpfc-5000 tachyon fibre channel interface controller product brief description tachyon is a fundamental building block compatible with agilent technologies fibre channel solution which includes interface controllers, physical link modules, adapters, switches and disk drives. the tachyon architecture sup- ports both networking and mass storage connections to provide a low cost, high performance solution with low host overhead. specifications system clock frequency: 20 40 mhz backplane operation testability: full internal scan path ieee standard 1149.1 boundary scan packaging: 208-pin metal quad flat pack standards: intended to be compliant with ansi standards and fcsi/fca profile definitions inbound message queue inbound block mover inbound data host-based data structures backplane interface fcp assists sequence management outbound block mover outbound data high priority message channel outbound message channel scsi read/write channel scsi buffer manager scsi exchange manager inbound message channel scsi exchange state table inbound data manager inbound sequence manager acks acks ack fifo outbound frame fifo inbound data fifo outbound sequence manager inbound sfs and mfs buffer channels mfs buffer queue sfs buffer queue high-priority command queue outbound command queue transmit receive link os/crc generator os processor crc checker 20b/16b decoder 10b/20b de-mux elastic store/ smoothing buffer 16b/20b encoder loop/n_port state machine 20b/10b mux internal block diagram the internal block diagram in figure 1 below shows the high-level chip architecture for tachyon. figure 1.
features single chip fibre channel interface (no i/o processor required) supports 1062, 531 and 266 mbaud links supports 3 topologies direct connect, fabric and fibre channel arbitrated loop (fc-al) supports fibre channel class 1, 2 and 3 services supports up to 2 kbyte frame payload for all classes of service sequence segmentation/reassembly in hardware automatic ack frame generation and processing on-chip support of fcp for scsi initiators and targets supports up to 16384 concurrent scsi i/o transactions compliant with internet mib-ii network management direct interface to industry standard 10 and 20-bit gigabit link module (glm) hardware assists for tcp/udp/ip networking parity protection on internal data path eight internal dma channels full duplex internal architecture that allows tachyon to process inbound and outbound data simultaneously pin-out block diagram figure 2 below shows the pin-out block diagram for tachyon. figure 2. tachyon backplane interface scan test interface backplane tad [31..0] parity avcs_l type [2..0] ready_l prefetch_l retry_l error_l int_l reset_l tbr_l [1..0] tbg_l sclk par_id [1..0] rx [19..0] rbc com_det l_unuse lckref_l ewrap fault tx [19..0] tbc txclk_sel tdi tdo tck trst tms gigabit link module interface gigabit link module clock generator transmit receive system adapter card block diagram figure 3 below shows an example of a tachyon on a generic host bus adapter. figure 3. tachyon backplane interface gigabit link module clk www.semiconductor.agilent.com data subject to change. copyright ? 2001 agilent technologies, inc. obsoletes 5965-1215 april 25, 2001 5988-2605en
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