1 ps8318f 11/13/08 pi6c185-01 precision 1-5 clock buffer pin configuration 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1 234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901 2 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 block diagram features ? high-speed, low-noise non-inverting 1-5 buffer ? switching speed up to 140 mhz ? supports up to two sodimms ? low skew (<250ps) between any two output clocks ? i 2 c serial configuration interface ? multiple v dd , v ss pins for noise reduction ? 3.3v power supply voltage ? packaging (pb-free & green available): -16-pin tssop (l) - 16-pin qsop (q) description the pi6c185-01 is a high-speed low-noise 1-5 non-inverting buffer designed for sdram clock buffer applications. this buffer is intended to be used with the pi6c10x clock generator for intel architecture-based mobile systems. at power-up, all sdram outputs are enabled and active. the i 2 c serial control may be used to individually activate/deactivate any of the 5 output drivers. note: purchase of i 2 c components from pericom conveys a license to use them in an i 2 c system as defined by philips?. sdram4 sdram2 sdram1 sdram0 buf_in sdata sclock sdram3 i 2 c i/o 1 2 3 v ss 4 buf_in 5 sdram1 6 sdata 7 v ss 8 v dd v dd v ss v dd sdram2 v ss sclk 16 15 14 13 12 11 10 9 v dd sdram0 sdram3 sdram4 08-0298
2 ps8318f 11/13/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c185-01 precision 1-5 clock buffer pin description serial configuration map byte0: sdram active/inactive register (1 = enable, 0 = disable) note: inactive means outputs are held low and are disabled from switching i 2 c address assignment 6 a5a4a3a2 a1 a0 aw /r 1101001 0 ti b# ni pn oitpircsed 7ti b2 1) evitcani/evitca(3mards 6ti b1 1) evitcani/evitca(2mards 5ti b- ) 0otezilaitini(cn 4ti b- ) 0otezil aitini(cn 3ti b- ) 0otezilaitini(cn 2ti b- ) 0otezilaitini(cn 1ti b3 ) evitcani/evitca(1mards 0ti b2 ) evitcani/evitca(0mards byte1: sdram active/inactive register (1 = enable, 0 = disable) ti b# ni pn oitpircsed 7ti b- ) 0otezilaitini(cn 6ti b- ) 0otezilaitini(cn 5ti b- ) 0otezilaitini(cn 4ti b- ) 0otezilaitini(cn 3ti b- ) 0 otezilaitini(cn 2ti b- ) 0otezilaitini(cn 1ti b- ) 0otezilaitini(cn 0ti b5 1) evitcani/evitca(4mards ni pl angi se py ty t qn oitpircsed 51,21,11,3, 2] 4.0[mard si5 s tuptuokcolcdereffub 5n i_fu bi1 t upnireffubkcolc 7a tad so / i1 i rofatadlaires 2 pu-lluplanretni,ecafretnic 8k lc si1 i rofkcolclaires 2 pu-lluplanretni,ecafretnic 61,31,6, 1v dd rewo p4 y lppusrewopv3.3 41,01,9, 4v ss dnuor g4d nuorg 08-0298
3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ps8318f 11/13/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c185-01 precision 1-5 clock buffer lobmy sr etemara pn oitidnoctse t. ni m. py t. xa ms tinu i dd tnerrucylppu sz hm0=ni_fu b3 am i dd tnerrucylppu sz hm66.66=ni_fu b0 7 i dd tnerrucylppu sz hm0.001=ni_fu b0 21 i dd tnerrucylppu sz hm3.331=ni_fu b0 02 the i 2 c interface permits individual enable/disable of each clock output and test mode enable. the pi6c185-01 is a slave receiver device. it can not be read back. sub-addressing is not supported. all preceding bytes must be sent in order to change one of the control bytes. every bite put on the sdata line must be 8-bits long (msb first), followed by an acknowledge bit generated by the receiving device. during normal data transfers sdata changes only when sclk is low. exceptions: a high-to-low transition on sdata while sclk is high indicates a ?start? condition. a low-to-high transition on sdata while sclk is high is a ?stop? condition and indicates the end of a data transfer cycle. each data transfer is initiated with a start condition and ended with a stop condition. the first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (high = read from addressed device, low = write to addressed device). if the device?s own address is detected, pi6c185-01 generates an acknowledge by pulling sdata line low during ninth clock pulse, then accepts the fol lowing data bytes until another start or stop condition is detected. following ack nowledgement of the address byte (0d2h), two more bytes must be sent: 1. ?command code? byte, and 2. ?byte count? byte. although the data bits on these two bytes are ?don?t care,? they must be sent and acknowledged. 2-wire i 2 c control storage temperature ...................................... ?65c to +150c ambient temperature with power applied ....... ?40c to +85c 3.3v supply voltage to ground potential ........... ?0.5v to +4.6v dc input voltage .............................................. ?0.5v to +4.6v note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. supply current (v dd = +3.465v, c load = max.) maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) 08-0298
4 ps8318f 11/13/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c185-01 precision 1-5 clock buffer sdram clock buffer operating specification dc operating specifications (v dd = +3.3v 5%, t a = 0c - 70c) lobmy sr etemara pn oitidno c. ni m. py t. xa ms tinu i nimho tnerrucpu-llu pv tuo v0.2 =4 5? am i xamho tnerrucpu-llu pv tuo v531.3 =6 4? i nimlo tnerrucnwod-llu pv tuo v0.1 =4 5 i xamlo tnerrucnwod-llu pv tuo v4.0 =3 5 t hr mard sy lnomardsetaregdeesirtuptu ov 4.2-v4.0@%5v3. 35 . 14 sn/v t hf mard sy lnomardsetaregdellaftuptu ov 4.0-v4.2@%5v3. 35 . 14 lobmy sr etemara pn oitidno c. ni m. xa ms tinu egatlovtupni v hi egatlovhgihtupn iv dd 0. 2v dd 3.0+ v v li egatlovwoltupn iv ss 3.0 ?8 .0 i li tnerrucegakaeltupn iv <0 ni v< dd 5 -5 + a v dd %5v3.3= v ho egatlovhgihtuptu oi ho am1- =4 .2 v v lo egatlovwoltuptu oi lo am1 =4 .0 c ni ecnaticapacniptupn i5 fp c tuo ecnaticapacsniptuptu o6 l nip ecnatcudnini p7h n t a erutarepmettneibm aw olfriao n00 7c o ac timing symbol parameter 66 mhz 100 mhz 133 mhz units min. max. min. max. min. max. t dskp sdram clk period 15.0 15.5 10.0 10.5 7.5 8.0 n s t sdkh sdram clk high time 5.6 3.3 2.2 ns t sdkl sdram clk low time 5.3 3.1 2.0 ns t sdrise sdram clk rise time 1.5 4.0 1.5 4.0 1.4 4.0 v/ns t sdfall sdram clk fall time 1.5 4.0 1.5 4.0 1.4 4.0 v/ns t plh sdram buffer lh prop delay 1.0 5.5 1.0 5.0 1.0 5.0 ns t phl sdram buffer hl prop delay 1.0 5.5 1.0 5.0 1.0 5.0 ns dutycycle measured at 1.5v 45 55 45 55 45 55 % tsdskw sdram output to output skew 250 250 250 ps 08-0298
5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ps8318f 11/13/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c185-01 precision 1-5 clock buffer 1.5v 1.5v t phl t plh 1.5v 1.5v input waveform output waveform output buffer test point 2.4 1.5 0.4 tsdkh tsdkp 3.3v clocking interface (ttl) tsdkl t sdfall t sdrise test load figure 1. clock waveforms notes: 1. maximum rise/fall times are guaranteed at maximum specified load. 2. minimum rise/fall times are guaranteed at minimum specified load. 3. rise/fall times are specified with pure capacitive load as shown. testing is done with an additional 500 resistor in parallel. minimum and maximum expected capacitive loads design guidelines to reduce emi 1. place r s series resistors and ci capacitors as close as possible to the respective clock pins. typical value for ci is 10 pf. r s series resistor value can be increased to reduce emi provided that the rise and fall time are still within the specified values. 2. minimize the number of ?vias? of the clock traces. 3. route clock traces over a continuous ground plane or over a continuous power plane. avoid routing clock traces from plane to plane (refer to rule #2). 4. position clock signals away from signals that go to any cables or any external connectors. kcol cd aolni md aolxa ms tin us eton mard s0 20 3f pn oitacificepsmmidmards 08-0298
6 ps8318f 11/13/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c185-01 precision 1-5 clock buffer packaging mechanical: 16-pin tssop (l) figure 2. design guidelines sdram r 5 c l sdram dimm spec. 100/66 mhz clock from chipset s 1 description: 16-pin, 173-mil wide, tssop package code: l document control no. pd - 1310 revision: e date: 03/09/05 note: 1. package outline exclusive of mold flash and metal burr 2. controlling dimentions in millimeters 3. ref: jedec mo-153f/ab pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com .193 .201 .047 max. .002 .006 seating plane .0256 bsc .018 .030 .004 .008 .252 bsc 1 16 .169 .177 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 1.20 4.9 5.1 0.65 0.19 0.30 .007 .012 08-0298
7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ps8318f 11/13/08 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 pi6c185-01 precision 1-5 clock buffer pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com ordering information ordering code packaging code package description operating temperature pi6c185-01l l 16-pin tssop commercial PI6C185-01LE l pb-free & green, 16-pin tssop commercial pi6c185-01qe q pb-f ree & green, 16-pin qsop commercial pi6c185-01qie q pb-f ree & green, 16 -pin qsop industrial packaging mechanical: 16-pin qsop (q) notes: 1. thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 1 .189 .197 .053 .069 .004 .010 seating plane .025 bsc .007 .010 .228 .244 1 16 .150 .157 x.xx x.xx denotes dimensions in millimeters 0.635 4.80 5.00 1.35 1.75 5.79 6.19 0.101 0.254 .008 .012 0.203 0.305 3.81 3.99 0.178 0.254 0.38 .008 0.203 .015 x 45 ref detail a detail a .008 0.20 min. guage plane .010 0.254 .041 1.04 ref .016 .035 0.41 0.89 ? ? .008 .013 0.20 0.33 description: 3 l q 0 l o wide qsop package code: q document control no. 3 ' revision: g date: 11/07/07 note: 1) controlling dimensions in inches. 2) ref: - ( ' ( & 0 2 % $ % 3) dimensions do not include mold flash, protrusions or gate burrs pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 ? www.pericom.com 08-0298
|
