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spicoder tm ur5hcspi zero-power tm keyboard encoder & power management ic for h/pcs spicoder is a trademark of semtech corp. all other trademarks belong to their respective companies. copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 1 hid & system management products, h/pc ic family description features ? strongarm tm handheld pcs windows ce ? platforms web phones personal digital assistants (pdas) wearable computers internet appliance the spicoder tm ur5hcspi keyboard encoder and power management ic is designed specifically for handheld pcs (h/pcs). the off-the-shelf ur5hcspi will readily work with cpus designed for windows ce ? , saving oems significant development time and money as well as minimizing time-to-market for the new generations of handheld products. three main design features of the ur5hcspi make it the ideal companion for the new generation of windows ce ? -compatible, single-chip computers: low-power consumption; real estate-saving size; and special keyboard modes. ?quasi? zero-power tm consumption (less than 2a @ 3v), a must for h/pcs, provides the host system with both power management and i/o flexibility, with almost no battery drainage. finally, special keyboard modes and built-in power management features allow the spicoder tm to operate in harmony with the power management modes of windows ce ? , resulting in more user flexibility and longer battery life. the ur5hcspi also offers programmable features for wake-up keys and general purpose i/o pins. compatible with ?system-on silicon? cpus for h/pcs special keyboard and power management modes for h/pcs, including programmable ?wake-up? keys scans, debounces, and encodes an 8 x 12 matrix and controls discrete switches and led indicators custom versions available spi-compatible keyboard encoder and power management ic with other interfaces available compatible with windows ce ? keyboard specification zero-power tm ? typically consuming less than 2a, between 3-5v offers overall system power management capabilities 111 12 22 33 23 44 34 _pwr_ok nc0 osco osci vcc nc nc _reset _wku vx c7 _atn _ss sck mosi miso xsw sw0 c8 c9 c10/wuko c11/_lid nc led2 led1 led0 _iotest vss nc r7 r6 r5 r4 c6 c5 c4 c3 c2 c1 c0 r0 r1 r2 r3 qfp UR5HCSPI-FB c6 c7 vx nc _wku _reset vcc osci osco nc0 nc c5 c4 c3 c2 c1 c0 r0 r1 r2 r3 r4 _pwr_ok _atn _ss sck mosi miso xsw sw0 c8 c9 c10/wuko nc r5 r6 r7 vss nc _iotest led0/gio0 led1/c13 led2/c12 c11/_lid 40 1 6 7 12 17 18 23 28 29 34 39 ur5hcspi-fn plcc applications pin assignments
package options pitch in mm?s ta=-20 c to +85 c 44-pin, plastic plcc 1.27 mm ur5hcspi-xx-fn 44-pin, plastic qfp 0.8 mm ur5hcspi-xx-fb other materials type order number spicoder tm testing board asy5-spi-xxx note 1 : xx=optional customization, xxx= denotes revision number block diagram ordering code copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 2 keyboard scanner & keyboard state control r0-r8 spi communication channel c0-c11 keyboard matrix lid latch monitor wake-up keys only signal switch external to case switch system monitor input signals power management unit leds lid wuko xsw swo pwr_ok wkup iotest wku miso mosi sck ss atn ur5hcspi led0 led1 led2
functional description pin definitions copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 3 the ur5hcspi consists functionally of five major sections (see the functional diagram on page 2). these are the keyboard scanner and state control, the programmable i/o, the spi communication channel, the system monitor and the power management unit. all sections communicate with each other and operate concurrently. mnemonic plcc qfp type name and function vcc 44 38 power supply: 3-5v vss 22 17 i ground vx 4 43 i tie to vcc osci 43 37 i oscillator input osco 42 36 o oscillator output _reset 1 41 i reset: apply 0v to provide orderly start-up miso 34 29 o spi interface signals mosi 35 30 i sck 36 31 i _ss 37 32 i slave select: if not used tie to vss _iotest 24 18 o wake-up control signals _wku 2 42 i r0-r4 13-17 8-12 i row data inputs r5-r7 19-21 13-15 i port provides internal pull-up resistors c0-c5 12-7 7-2 o column select outputs: c6-c7 6-5 1,44 o c8-c9 31-30 26-25 o multi-function pins c10/wuko 29 24 i/o c10 & ? wake-up keys only ? imput c11/_lid 28 23 i/o c11 & lid latch detect input miscellaneous functions led2 27 21 i/o led2 output led1 26 20 i/o led1 output led0 25 19 i/o led0 output xsw 33 28 i external discrete switch swo 32 27 i discrete switch power management pins _atn 38 33 o cpu attention output _pwr_ok 39 34 i power ok input nc 3,18 39-40 no connects : these pins are unused 23,40 16,22 nc0 41 35 nc0 should be tied to vss or gnd note 1: an underscore before a pin mnemonic denotes an active low signal.
pin descriptions copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 4 vcc and vss vcc and vss are the power supply and ground pins. the ur5hcspi will operate from a 3-5 volt power supply. to prevent noise problems, provide bypass capacitors and place them as close as possible to the ic with the power supply. vx, where available, should be tied to vcc. osci and osco osci and osco provide the input and output connections for the on- chip oscillator. the oscillator can be driven by any of the following circuits: - crystal - ceramic resonator - external clock signal the frequency of the on-chip oscillator is 2 mhz. _reset a logic zero on the _reset pin will force the ur5hcspi into a known start-up state. the reset signal can be supplied by any of the following circuits: - rc - voltage monitor - master system reset mosi, miso, sck, _ss, _atn these five signals implement the spi interface. the device acts as a slave on the spi bus. the _ss (slave select) pin should be tied to ground if not used by the spi master. the _atn pin is asserted low each time the ur5hcspi has a packet ready for delivery. for a more detailed description, refer to the spi communication channel section on page 9. _iotest and _wku ? input output test ? and ? wake up ? pins control the stop mode exit of the device. the designer can connect any number of active low signals to these two pins through a 17k resistor, in order to force the device to exit the stop mode. a sample circuit is shown on page 15 of this document. all the signals are ? wire-anded. ? when any one of these signals is not active, it should be floating (i.e., these signals should be driven from ? open-collector ? or ? open-drain ? outputs). other configurations are possible; contact semtech. r0-r 7 the r0-r7 pins are connected to the rows of the scanned matrix. each pin provides an internal pull- up resistor, eliminating the need for external components. c0-c9 c0 to c9 are bi-directional pins connected to the columns of the scanned matrix. when a column is selected, the pin outputs an active low signal. when the column is de- selected, the pin turns into high- impedance. c10/wuko the c10/wuko pin acts alternatively as column scan output and as an input. as an input, the pin detects the ? wake-up keys only ? signal, typically provided by the host cpu to indicate that the user has turned the unit off. when the device detects an active high state on this pin, it feeds this information into the ? keyboard state control ? unit, in order to disable the keyboard and enable the programmed wake-up keys. c11/_lid the c11/_lid pin acts in a similar manner to the c10/wuko. this pin is typically connected to the lid latch through a 150k resistor, in order to detect physical closing of the device cover. when the pin detects an active low state in this input, it feeds this information into the ? keyboard state control ? unit, in order to disable keys inside the case and enable only switches located physically on the outer body of the h/pc unit. led0, led1 and led2 these three pins provide an active low drive for led indicators. the programming of these pins is explained in the leds section on page 8 of this document.
pin descriptions, (con ? t) the windows ce ? keyboard copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 5 xsw the xsw pin is dedicated to an external switch. this pin is handled differently than the rest of the switch matrix and is intended to be connected to a switch physically located on the outside of the unit. sw0 the sw0 pin is a dedicated input pin for a switch. pwr_ok the pwr_ok is an active low pin that monitors the battery status of the unit. when the ur5hcspi detects a transition from high to low on this pin, it will immediately enter the stop mode, turn the led off and remain in this state until the batteries of the unit are replaced and the signal is deasserted. the following illustration shows a typical implementation of a windows ce ? keyboard. windows ce ? does not support the following keyboard keys typically found on desktop and laptop keyboards: insert scroll lock pause num lock function keys (f1-f12) print screen if the keyboard implements the windows key, the following key combinations are supported in the windows ce ? environment: key combination result windows open start menu windows+k open keyboard tool windows+i open stylus tool windows+c open control panel windows+e explore the h/pc windows+r display the run dialog box windows+h open windows ce ? help ctrl+windows+a select all on desktop 1 ! esc 3 # 2 @ 5 % 4 $ 7 & 6 ^ 9 ( 8 * - _ 0 ) e w t r u y o i p q f d h g k j l s a v c n b m x z tab shift ctrl shift enter = + \ | ' " ; : . > , < / ? ` ~ ] } [ { power alt
? ghost ? keys keyboard scanner copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 6 in any scanned contact switch matrix, whenever three keys defining a rectangle on the switch matrix are pressed at the same time, a fourth key positioned on the fourth corner of the rectangle is sensed as being pressed. this is known as the ? ghost ? or ? phantom ? key problem. the encoder scans a keyboard organized as an 8 row by 12 column matrix for a maximum of 96 keys. smaller size matrixes can also be accommodated by simply leaving unused pins open. the ur5hcspi provides internal pull-ups for the row input pins. when active, the encoder selects one of the column lines (c0-c13) every 512 s and then reads the row data lines (r0-r7). a key closure is detected as a zero in the corresponding position of the matrix. a complete scan cycle for the entire keyboard takes approximately 9.2 ms. each key found pressed is debounced for a period of 20 ms. once the key is verified, the corresponding key code(s) are loaded into the transmit buffer of the spi communication channel. actual key presses ? ghost ? key figure 1 : ? ghost ? or ? phantom ? key problem although the problem cannot be totally eliminated without using external hardware, there are methods to neutralize its negative effects for most practical applications. keys that are intended to be used in combinations should be placed in the same row or column of the matrix, whenever possible. shift keys (shift, alt, ctrl, window) should not reside in the same row (or column) as any other keys. the ur5hcspi has built-in mechanisms to detect the presence of ? ghost ? keys. n-key rollover in this mode, the code(s) corresponding to each key press are transmitted to the host system as soon as that key is debounced, independent of the release of other keys. when a key is released, the corresponding break code is transmitted to the host system. there is no limitation to the number of keys that can be held pressed at the same time. however, two or more key closures, occurring within a time interval of less than 5ms, will set an error flag and will not be processed. this feature is to protect against the effects of accidental key presses.
send all keys send wake up keys only send no keys pwr_ok pwr_ok pwr_ok = 0 soft reset (pwr_ok =1) and (wuko=0) and (lid=1) and key press (pwr_ok =1) and key press and (wuko = 1) wuko =1 and key press send xsw key only (lid = 0) and (wuk0=0) and key press (lid = 1) and (wuko=0) and key press wuko=1 and key press pwr_ok (pwr_ok =1) and (lid = 0) and (wuko=0) and key press figure 2: the ur5hcspi implements four modes of keyboard and switch operation. keyboard states copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 7 these states of operation refer only to the keyboard functionality and, although they are related to power states, they are also independent of them. "send all keys" entry conditions: power on reset, soft reset, pwr_ok =1, {(lid=1) and (wuko=0)} exit conditions: pwr_ok = 0 -> "send no keys"(wuko=1) and (key press) -> "send wake-up keys only"(lid = 0) and (wuko=0) and (key press) -> "send xsw key only" description: this is the ur5hcspi ? s normal state of operation, accepting and transmitting every key press to the system. this state is entered after the power-on and is sustained while the unit is being used. ?send wake-up keys only? entry conditions : (wuko=1) and (key or switch press) exit conditions: soft reset -> ? send all keys ? pwr_ok = 0 -> ? send no keys ? description : this state is entered when the user turns the unit off. a signal line driven by the host will notify the ur5hcspi about this state transition. while in this state, the ur5hcspi will transmit only keys programmed to be wake-up keys to the system. it is not necessary for the ur5hcspi to detect this transition in real time, since it does not effect any operation besides buffering keystrokes. 3. stop mode time-out entry will be shortened to further conserve energy. 4. while in this state all interrupts are disabled. the ur5hcspi will exit this state on the next interrupt event that detects the pwr_ok line has been de-asserted. e ?send xsw key only" entry condition: (lid=0) and (wuko=0) and (key press) exit condition: (lid=1) and (wuko=0) and (key press) -> ? send all keys ? pwr_ok = 0 -> ? send no keys ? (wuko = 1) and (key press) -> ? send wake up keys only ? description: this state is entered upon closing the lid of the device. while in this state, the encoder will transmit only the xsw key, which is located outside the unit. this feature is designed to accommodate buttons on the outside of the box, such as a microphone button, that need to be used while the lid is closed. ?send no keys" entry conditions : pwr_ok transition from high to low exit conditions: (pwr_ok = 1) and (matrix key pressed or switch or _wkup) description: this state is entered when a pwr_ok signal is asserted (transition high to low), indicating a critically low level of battery voltage. the pwr_ok signal will cause an interrupt to the ur5hcspi, which guarantees that the transition is performed in real time. while in this state, the ur5hcspi will perform as follows: 1. the led will be turned off. nevertheless, its state is saved and will be restored after exiting the disabled state (change of batteries). 2. the ur5hcspi will enter the stop mode for maximum energy conservation.
key codes led modes copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 8 the ur5hcspi provides three led pins. there are three led modes: off, on, and blinking. the led can be individually set to one of these modes. in the blinking mode, both the on-interval and the off-interval can be individually set. additionally, a meta blink count and meta blink interval may be specified. this describes an interval of a different length which may be inserted after each specified number of blinks. all the intervals are based on a 1/16th of a second duration. when the led is on or blinking, the spicoder tm will not enter the stop mode unless the pwr_ok signal is asserted low. in this case, the device will save the status of the led and turn it off. the default led mode is off. the above timing chart describes the behavior of an led using these settings,1: led on; 0: led off. key codes range from 01h to 73h and are arranged as follows: make code = column_number * 8 + row_number + 1 break code = make code or 80h discrete switches transmit the following codes: xsw = 71h sw0 = 72h on on off on interval off interval 12 on off meta blink count 3 1 blinking cycle meta blink off on off on figure 3 : the behavior of an led using the settings 1: led on; 0: led off.
spi communication channel copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 9 spi data transfers can be performed at a maximum clock rate of 500 khz. when the ur5hcspi asserts the _atn signal to the host master, the data will have already been loaded into the data register waiting for the clocks from the master. the slave select (ss) line can be tied permanently to ground if the ur5hcspi is the only slave device in the spi network. one _atn signal is used per each byte transfer. if the host fails to provide clock signals for successive bytes in the data packet within 120 ms, the transmission will be aborted and a new session will be initiated by asserting a new atn signal. in this case, the whole packet will be re-transmitted. if the spi transmission fails 20 times consecutively, the synchronization between the master and slave may be lost. in this case, the ur5hcspi will enter the reset state. the ur5hcspi implements the spi communication protocol according to the following diagram: cpol = 0 ---------- sck line idles in low state cpha = 1 ---------- ss line is an output enable control figure 5: transmitting data waveforms: figure 6: receiving data waveforms figure 4: spi communication protocol when the host sends commands to the keyboard, the ur5hcspi requires that the minimum and maximum intervals between two successive bytes be 200 s and 5 ms respectively. sck (cpol=0) _ss data output (cpha=1) sample input ? msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb _atn signal
data/command buffer power management unit copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 10 the ur5hcspi implements a data buffer that contains the key code/command bytes waiting to be transmitted to the host. if the data buffer is full, the whole buffer will be cleared and an "initialize" command will be sent to the host. at the same time, the keyboard will be disabled until the "initialize" or "initialize complete" command from the host is received. the ur5hcspi supports two modes of operation. the following table lists the typical and maximum supply current (no dc loads) for each mode at 3.3 volts (+/- 10%). current typical max unit description run 1.5 1 3.0 ma entered only while data/commands are in process and if the leds are blinking stop 2.0 20 a entered after 125 ms of inactivity if leds islow power consumption of the keyboard sub-system will be determined primarily by the use of the leds. while the ur5hcspi is in the stop mode, an active low wake-up output from the master must be connected to the edge-sensitive _wku pin of the ur5hcspi. this signal will be used to wake up the ur5hcspi in order to receive data from the master host. the master host will have to wait a minimum of 5 ms prior to providing clocks to the ur5hcspi. the ur5hcspi will enter the stop mode after a 125 ms period of keypad and/or host communications inactivity, or anytime the pwr_ok line is asserted low by the host. note that while one or more keys are held pressed, the ur5hcspi will not enter the stop mode until every key is released. stop run - keyboard - switch - input transaction - system wake-up - after 125 ms of inactivity and leds are off after reset or 125 ms of inactivity while processing current task and/or led(s) are active figure 7: the power states of the ur5hcspi
communication protocol copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 11 there are eight commands that may be sent from the ur5hcspi to the host, and ten commands that may be sent from the host to the ur5hcspi. each command from ur5hcspi to the host is composed of a sequence of codes. all commands start with code (80h) and end with lrc code (see the description of the lrc calculation on page 12). command details are listed below. commands to the host - summary command name code description initialize request aoh sent to the host when the data buffer is full initialize complete a1h issued upon completion of the ? initialize ? command issued by the host heartbeat response a2h response to ? heartbeat request ? issued by the host identification response f2h response to ? identification request ? issued by the host led status report a3h response to ? led status request ? resend request a5h issued upon error during the reception of a packet initialize request 80h a0h 20h the ur5hcspi will send the initialize request command to the host when its data buffer is full. initialization complete 80h a1h 21h the ur5hcspi wil send the initialize complete report to the host when it finishes the initialization caused by initialize command from the host. heartbeat response 80h a2h 22h the ur5hcspi will send the heartbeat response to the host when it receives the heartbeat request command from the host. identification response 80h f2h 02h --- usar 08h --- rev 0.8a 00h . 7eh the ur5hcspi will send the identification response to the host when it receives the identification request command from the host. the lrc is calculated for the whole packet, including the command code and the command prefix. the lrc is calculated by first taking the bitwise exclusive or of all bytes from the message. if the most significant bit (msb) of the lrc is set, the lrc is modified by clearing the msb and changing the state of the next most significant bit. thus, the packet check byte will never consist of a valid lrc with the most significant bit set. lrc calculation commands to the host analytically
lrc calculation, (con ? t) commands from the ur5hcspi to the host, (con ? t) copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 12 led status report 80h a3h xxh led0 status:( 0=off; 1=on; 2=blinking; 3=no led mode ) xxh led1 status:( 0=off; 1=on; 2=blinking; 3=no led mode ) xxh led2 status:( 0=off; 1=on; 2=blinking; 3=no led mode) xxh the ur5hcspi will send the led status report to the host when it receives the led status request command from the host. resend request 80h a5h 25h the ur5hcspi will send this resend request command to the host when its command buffer is full, or if it detects either a parity error or an unknown command during a system command transmission. the following c language function is an example of an lrc calculation program. it accepts two arguments: a pointer to a buffer and a buffer length. its return value is the lrc value for the specified buffer. char calculate lrc (char buffer, size buffer) { char lrc; size_t index; /* * init the lrc using the first two message bytes. */ lrc = buffer [0] ^ buffer [1]; /* * update the lrc using the remainder of the buffer. */ for (index = 2; index < buffer; index ++) lrc ^ = buffer[index]; /* * if the msb is set then clear the msb and change the next most significant bit */ if (lrc & 0x80) lrc ^ = 0xc0; /* * return the lrc value for the buffer.*/}
commands from the host to the ur5hcspi copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 13 commands from the host - summary command name code description initialize aoh causes the ur5hcspi to enter the power-on state initialization complete a1h issued as a response to the ? initialize request ? heartbeat request a2h the ur5hcspi will respond with ? heartbeat response ? identification request f2h the ur5hcspi will respond with ? identification response ? led status request a3h the ur5hcspi will respond with ? led status response ? led modify a6h the ur5hcspi will change the led accordingly resend request a5h issued upon error during the reception of a packet input/output mode modify a7h the ur5hcspi will modify or report the status of the gio0 pin output data to i/o pin a8h the ur5hcspi will output a signal to the gio0 pin set wake-up keys a9h defines which keys are ? wake-up ? keys each command to ur5hcspi is composed of a sequence of codes. all commands start with code (1bh) and end with the lrc code (bitwise exclusive or of all bytes). initialize 1bh a0h 7bh when the ur5hcspi receives this command, it will clear all buffers and return to the power-on state. initialization complete 1bh a1h 7ah when the ur5hcspi receives this command, it will enable transmission of keyboard data. keyboard data transmission is disabled if the tx output buffer is full (32 bytes). note that if the transmit data buffer gets full the encoder will issue an "initialize request" to the host. heartbeat request 1bh a2h 79h when the ur5hcspi receives this command, it will reply with the heartbeat response report. identification request 1bh f2h 29h the ur5hcspi will reply to this command with the identification response report. commands from the host to the ur5hcspi analytically
commands from the host to the ur5hcspi, (con ? t) copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 14 led status request 1bh a3h 78h when ur5hcspi receives this command, it will reply with the led status report. led modify 1bh a6h xxh led number (0) xxh (0=led off; 1=led on; 2=led blinking) xxh time in 1/16ths of a second for led to be on xxh time in 1/16ths of a second for led to be off xxh number of blinks after which to apply meta blink interval xxh time in 1/16ths of a second for led to be off after blinks xxh when the ur5hcspi receives this command, it will change the led mode accordingly. set wake-up keys 1bh a9h xxh (r7 r6 r5 r4 r3 r2 r1 r0 bitmap: 0- enabled, 1-disabled) xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh the "set wake-up keys" command is used to disable specific keys from waking up the host. using this command, the host can set only a group of keys.
suggested schematic for the UR5HCSPI-FB copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 15 alternatively a 2mhz cmos signal can be tied directly to osc1 UR5HCSPI-FB tied to gnd if not used attention signal wake up signal row inputs column outputs to switch matrix power ok signal discrete switches slave s elect ceramic resonator circuit with built in capacitors alternatively an rc circuit or master reset signal can be used power ok signal telcom UR5HCSPI-FB v0.9 vcc vcc 1.5m 1.5m 15k UR5HCSPI-FB 7 6 5 4 8 2 1 44 26 25 24 37 36 38 3 41 29 30 31 32 33 17 35 42 18 23 34 19 20 21 27 28 9 10 11 12 13 14 15 43 c0 c1 c2 c3 r0 c5 c6 c7 c8 c9 c10/wuko osci osco vdd c4 reset miso mosi sck ss atn vss nc0 wku iotest c11/lid pwr_ok led0 led1 led2 sw0 xsw r1 r2 r3 r4 r5 r6 r7 vpp 1mohm 2mhz tc54c4302ecb vout vin gnd 150k 15k 15k sck mosi miso _wkup _atn pwr_ok _lid wuko (c) 2000, usar, a semtech co.
implementation notes for the ur5hcspi copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 16 the following notes pertain to the suggested schematic found on the previous page. the built-in oscillator on the ur5hcspi-06 requires the attachment of the 2.00 mhz ceramic resonators with built-in load capacitors.. you can use either an avx, part number pbrc-2.00 br; or a murata part number cstcc2.00mg ceramic resonator. it may also be possible to operate with the 2.00 mhz crystal, albeit with reduced performance. due to their high q, the crystal oscillator circuits start-up slowly. since the spicoder tm constantly switches the clock on and off, it is important that the ceramic resonator is used (it starts up much quicker than the crystal). resonators are also less expensive than crystals. also, if crystal is attached, two load capacitors (33pf to 47pf) should be added, a capacitor between each side of the crystal and ground. in both cases, using ceramic resonator with built-in load capacitors, or crystal with external load capacitors, a feedback resistor of 1 meg should be connected between oscin and oscout. troubleshoot the circuit by looking at the output pin of the oscillator. if the voltage is half-way between supply and ground (while the oscillator should be running) --- the problem is with the load caps / crystal. if the voltage is all the way at supply or ground (while the oscillator should be running) --- there are shorts on the pcb. note: when the oscillator is intentionally turned off, the voltage on the output pin of the oscillator is high (at the supply rail).
electrical specifications copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 17 absolute maximum ratings ratings symbol value unit supply voltage vdd -0.3 to +7.0 v input voltage vin vss -0.3 to vdd +0.3 v current drain per pin i 25 ma (not including vss or vdd) operating temperature ta t low to t high c ur5hcspi -40 to +85 storage temperature range tstg - -65 to +150 c thermal characteristics characteristic symbol value unit thermal resistance tja c per w plastic 60 plcc 70 dc electrical characteristics (vdd=3.3 vdc +/-10%, vss=0 vdc, temperature range=t low to t high unless otherwise noted) characteristic symbol min typ max unit output voltage (i load<10a) vol 0.1 v voh vdd ? 0.1 output high voltage (i load=0.8ma) voh vdd ? 0.8 v output low voltage (i load=1.6ma) vol: 0.4 v input high voltage vih 0.7xvdd vdd v input low voltage vil vss 0.2xvdd v user mode current ipp 5 10 ma data retention mode (0 to 70 c) vrm 2.0 v supply current (run) idd 1.53 3.0 ma (wait) 0.711 1.0 ma (stop) 2.0 20 a i/o ports hi-z leakage current iil +/-10 a input current iin +/- 1 a i/o port capacitance cio 8 12 pf control timing (vdd=3.3 vdc +/-10%, vss=0 vdc, temperature range=t low to t high unless otherwise noted) characteristic symbol min max unit frequency of operation fosc mhz crystal option 2.0 external clock option dc 2.0 cycle time tcyc 1000 ns crystal oscillator startup time toxov 100 ms stop recovery startup time tilch 100 ms reset pulse width trl 8 tcyc interrupt pulse width low tlih 250 ns interrupt pulse period tilil * tcyc osc1 pulse width toh, tol 200 ns *the minimum period tlil should not be less than the number of cycle times it takes to execute the interrupt service routine pl us 21 tcyc.
spicoder tm bill of materials copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 18 UR5HCSPI-FB quantity manufacturer part# description 3 generic 330 ohms 330 ohms resistor 3 generic led led used as led1. led2. led3 3 generic 15 k 15 k resistors 1 generic 150 k 150 k resistors 1 generic 1m 1m resistors 2 generic 1.5 k 1.5 k resistors 1 telcom tc54vc4302ecb713 ic volt detector cmos 4.3v sot23, for 5v operation tc54vc2702ecb713 ic volt detector cmos 2.7v sot23, for 3.3v operation 1 avx pbrc-2.00br 2.00mhzceramic resonator with built in capacitors, smt revised 7/14/99
copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 19 this page left intentionally blank
copyright semtech 1997-2001 doc5-spi-ds-117 www.semtech.com 20 for sales information and product literature, contact: hid & system mgmt division semtech corporation 568 broadway new york, ny 10012 hidinfo@semtech.com http://www.semtech.com 212 226 2042 telephone 212 226 3215 telefax semtech western regional sales 805-498-2111 telephone 805-498-3804 telefax semtech central regional sales 972-437-0380 telephone 972-437-0381 telefax semtech eastern regional sales 203-964-1766 telephone 203-964-1755 telefax semtech asia-pacific sales office +886-2-2748-3380 telephone +886-2-2748-3390 telefax semtech japan sales office +81-45-948-5925 telephone +81-45-948-5930 telefax semtech korea sales sales +82-2-527-4377 telephone +82-2-527-4376 telefax northern european sales office +44 (0)2380-769008 telephone +44 (0)2380-768612 telefax southern european sales office +33 (0)1 69-28-22-00 telephone +33 (0)1 69-28-12-98 telefax central european sales office +49 (0)8161 140 123 telephone +49 (0)8161 140 124 telefax copyright 2000-2001 semtech corporation. all rights reserved. zero-power, spicoder and self-power management are trademarks of semtech corporation. semtech is a registered trademark of semtech company. all other trademarks belong to their respective companies. intellectual property disclaimer this specification is provided "as is" with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. a license is hereby granted to reproduce and distribute this specification for internal use only. no other license, expressed or implied to any other intellectual property rights is granted or intended hereby. authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in this specification. authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights.

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