View MT18HTF12872DG-53EXX_3903881.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80e934a6 htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 1 ?2003 micron technology, inc. 512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary ? ddr2 sdram registered dimm mt18htf6472d ? 512mb mt18htf12872d ? 1gb (advance ? ) mt18htf25672d ? 2gb(advance ? ) for the latest data sheet, please refer to the micron web site: www.micron.com/moduleds features ? 240-pin, dual in-line memory module (dimm) fast data transfer rates: pc2-3200 or pc2-4300 utilizes 400 mt/s and 533 mt/s ddr sdram components 512mb (64 meg x 72), 1gb (128 meg x 72) 2gb (256 meg x 72) v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v v ddspd = +1.7v to +3.6v jedec standard 1.8v i/o (sstl_18-compatible) differential data strobe (dqs, dqs#) option four-bit prefetch architecture differential clock inputs (ck, ck#) commands entered on each rising ck edge dqs edge-aligned with data for reads dqs center-aligned with data for writes dll to align dq and dqs transitions with ck four or eight internal device banks for concurrent operation data mask (dm) for masking write data programmable cas# latency (cl): 3 and 4 posted cas# additive latency (al): 0, 1, 2, 3, and 4 write latency = read latency - 1 t ck programmable burst lengths: 4 or 8 read burst interrupt supported by another read write burst interrupt supported by another write adjustable data-output drive strength concurrent auto precharge option is supported auto refresh (cbr) and self refresh mode 7.8125s maximum average periodic refresh interval 64ms, 8,192-cycle refresh figure 1: 240-pin dimm (mo-206 r/c ?b?) off-chip driver (ocd) impedance calibration on-die termination (odt) serial presence detect (spd) with eeprom gold edge contacts note: 1. consult factory for availability of lead-free prod- ucts. 2. cl = cas (read) latency. options marking package 240-pin dimm (standard) g 240-pin dimm (lead-free) 1 y frequency/cas latency 2 3.75ns @ cl = 4 (ddr2-533) -53e 5.0ns @ cl = 3 (ddr2-400) -40e table 1: address table 512mb 1gb 2gb refresh count 8k 8k 8k row addressing 8k (a0?a12) 16k (a0?a13) 16k (a0?a13) device bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 8 (ba0, ba1, ba2) device configuration 256mb (32 meg x 8) 512mb (64 meg x 8) 1gb (128 meg x 8) column addressing 1k (a0?a9) 1k (a0?a9) 1k (a0?a9) module rank addressing 2 (s0#, s1#) 2 (s0#, s1#) 2 (s0#, s1#)
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 2 ?2003 micron technology. inc. note: 1. all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt18htf12872dg-40ec2 . 2. contact micron for product availability. table 1: key timing parameters speed grade data rate (mhz) t rcd (ns) t rp (ns) t rc (ns) cl = 3 cl = 4 -53e 400 533 15 15 60 -40e 400 400 15 15 60 table 2: part numbers and timing parameters part number 1 module density configuration module bandwidth memory clock/ data rate latency (cl - t rcd - t rp) mt18htf6472dg-40e__ 512mb 64 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18htf6472dy-40e__ 512mb 64 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18htf6472dg-53e__ 512mb 64 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt18htf6472dy-53e__ 512mb 64 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt18htf12872dg-40e__ 2 1gb 128 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18htf12872dy-40e__ 2 1gb 128 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18htf12872dg-53e__ 2 1gb 128 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt18htf12872dy-53e__ 2 1gb 128 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt18htf25672dg-40e__ 2 2gb 256 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18htf25672dy-40e__ 2 2gb 256 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18htf25672dg-53e__ 2 2gb 256 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt18htf25672dy-53e__ 2 2gb 256 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 3 ?2003 micron technology. inc. note: pin 196 is nc for 512mb, or a13 for 1gb and 2gb; pin 54 is nc for 512mb and 1gb, or ba2 for 2gb. figure 2: pin locations table 3: pin assignment (240-pin dimm front) pin symbol pin symbol pin symbol pin symbol 1v ref 31 dq19 61 a4 91 v ss 2v ss 32 v ss 62 v ddq 92 dqs5# 3dq033dq24 63 a2 93 dqs5 4dq134dq25 64 v dd 94 v ss 5v ss 35 v ss 65 v ss 95 dq42 6 dqs0# 36 dqs3# 66 v ss 96 dq43 7 dqs037dqs367 v dd 97 v ss 8v ss 38 v ss 68 nc 98 dq48 9 dq2 39 dq26 69 v dd 99 dq49 10 dq3 40 dq27 70 a10/ap 100 v ss 11 v ss 41 v ss 71 ba0 101 sa2 12 dq8 42 cb0 72 v ddq 102 nc 13 dq9 43 cb1 73 we# 103 v ss 14 v ss 44 v ss 74 cas# 104 dqs6# 15 dqs1# 45 dqs8# 75 v ddq 105 dqs6 16 dqs1 46 dqs8 76 s1# 106 v ss 17 v ss 47 v ss 77 0dt1 107 dq50 18 reset# 48 cb2 78 v ddq 108 dq51 19 nc 49 cb3 79 v ss 109 v ss 20 v ss 50 v ss 80 dq32 110 dq56 21 dq10 51 v ddq 81 dq33 111 dq57 22 dq11 52 cke0 82 v ss 112 v ss 23 v ss 53 v dd 83 dqs4# 113 dqs7# 24 dq16 54 ba2 84 dqs4 114 dqs7 25 dq17 55 nc 85 v ss 115 v ss 26 v ss 56 v ddq 86 dq34 116 dq58 27 dqs2# 57 a11 87 dq35 117 dq59 28 dqs2 58 a7 88 v ss 118 v ss 29 v ss 59 v dd 89 dq40 119 sda 30 dq18 60 a5 90 dq41 120 scl table 4: pin assignment (240-pin dimm back) pin symbol pin symbol pin symbol pin symbol 121 v ss 151 v ss 181 v ddq 211 dm5/dqs14 122 dq4 152 dq28 182 a3 212 nc/dqs14# 123 dq5 153 dq29 183 a1 213 v ss 124 v ss 154 v ss 184 v dd 214 dq46 125 dm0/dqs9 155 dm3/dqs12 185 ck0 215 dq47 126 nc/dqs9# 156 nc/dqs12# 186 ck0# 216 v ss 127 v ss 157 v ss 187 v dd 217 dq52 128 dq6 158 dq30 188 a0 218 dq53 129 dq7 159 dq31 189 v dd 219 v ss 130 v ss 160 v ss 190 ba1 220 rfu 131 dq12 161 cb4 191 v ddq 221 rfu 132 dq13 162 cb5 192 ras# 222 v ss 133 v ss 163 v ss 193 s0# 223 dm6/dqs15 134 dm1/dqs10 164 dm8/dqs17 194 v ddq 224 nc/dqs15# 135 nc/dqs10# 165 nc/dqs17# 195 odt0 225 v ss 136 v ss 166 v ss 196 nc/ a13 226 dq54 137 rfu 167 cb6 197 v dd 227 dq55 138 rfu 168 cb7 198 v ss 228 v ss 139 v ss 169 v ss 199 dq36 229 dq60 140 dq14 170 v ddq 200 dq37 230 dq61 141 dq15 171 cke1 201 v ss 231 v ss 142 v ss 172 v dd 202 dm4/dqs13 232 dm7/dqs16 143 dq20 173 nc 203 nc/dqs13# 233 nc/dqs16# 144 dq21 174 nc 204 v ss 234 v ss 145 v ss 175 v ddq 205 dq38 235 dq62 146 dm2/dqs11 176 a12 206 dq39 236 dq63 147 nc/dqs11# 177 a9 207 v ss 237 v ss 148 v ss 178 v dd 208 dq44 238 v ddspd 149 dq22 179 a8 209 dq45 239 sa0 150 dq23 180 a6 210 v ss 240 sa1 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u22 u21 u20 u19 u18 u17 u16 u15 u14 u13 pin 121 pin 184 pin 185 pin 240 pin 1 pin 64 pin 65 pin 120 indicates a v dd or v ddq pin indicates a v ss pin front view back view
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 4 ?2003 micron technology. inc. table 5: pin descriptions pin numbers may not correlate with symbols. refer to pin assignment tables on page 3 for more information pin numbers symbol type description 77, 195 odt0m odt1 input on-die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the following pins: dq, dqs, dqs#, and dm. the odt input will be ignored if disabled via the load mode command. 185, 186 ck0, ck0# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs/dqs#) is referenced to the crossings of ck and ck#. 52, 171 cke0, cke1 input clock enable: cke (registered high) activates and cke (registered low) deactivates clocking circuitry on the ddr2 sdram. the specific circuitry that is enabled/disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge power-down and self refresh operations (all device banks idle), or active power- down (row active in any device bank). cke is synchronous for power-down entry, power-down exit, output disable, and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (excluding ck, ck#, cke, and odt) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_18 input but will detect a lvcmos low level once v dd is applied during first power-up. after vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh operation v ref must be maintained to this input. 76, 193 s0#, s1# input chip select: s# enables (registered low) and disables (registered high) the command decoder. all commands are masked when s# is registered high. s# provides for external rank selection on systems with multiple ranks. s# is considered part of the command code. 73, 74, 192 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 54 (2gb) , 71, 190 ba0, ba1, ba2 (2gb) input bank address inputs: define to which device bank an active, read, write, or precharge command is being applied. ba0? ba2 define which mode register including mr, emr, emr(2), and emr(3) is loaded during the load mode command. 57, 58, 60, 61, 63, 70, 176, 177, 179, 180, 182, 183, 188, 196 (2gb) a0?a12 (512mb) a0-a13 (1gb, 2gb) input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/ write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device ba nk selected by ba0?ba2) or all device banks (a10 high). the address inputs also provide the op- code during a load mode command. 125, 134, 146, 155, 164, 202, 211, 223, 232 dm0?dm8 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins.
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 5 ?2003 micron technology. inc. 3, 4, 9, 10, 12, 13, 21, 22, 24, 25, 30, 31, 33, 34, 39, 40, 80, 81, 86, 87, 89, 90, 95, 96, 98, 99, 107, 108, 110, 111, 116, 117, 122, 123, 128, 129, 131, 132, 140, 141, 143, 144, 149, 150, 152, 153, 158, 159, 199, 200, 205, 206, 208, 209, 214, 215, 217, 218, 226, 227, 229, 230, 235, 236 dq0?dq63 i/o data input/output: bidirectional data bus. 6, 7, 15, 16, 27, 28, 36, 37, 45, 46, 83, 84, 92, 93, 104, 105, 113, 114, 125, 126, 134, 135, 146, 147, 155, 156, 164, 165, 202, 203, 211, 212, 223, 224, 232, 233 dqs0?dqs17, dqs0#?dqs17# i/o data strobe: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center aligned with write data. dqs# is only used when differential data strobe mode is enabled via the load mode command. if rdqs is disabled, dqs0?dqs17 become dm0?dm8 and dqs9#?dqs17# are not used. 42, 43, 48, 49, 161, 162, 167, 168 cb0?cb7 i/o check bits: ecc, 1-bit error detection and correction. 120 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 101, 239, 240 sa0?sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 119 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. 18 reset# input asynchronously forces all registered outputs low when reset# is low. this signal can be used during power up to ensure that cke is low and dqs are high-z. 53, 59, 64, 67, 69, 172, 178, 184, 187, 189, 197, v dd supply power supply: +1.8v 0.1v. 51, 56, 62, 72, 75, 78, 170, 175, 181, 191, 194, v dd q supply dq power supply: +1.8v 0.1v. isolated on the device for improved noise immunity. 1v ref supply sstl_18 reference voltage. 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97,100, 103, 106, 109,112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 v ss supply ground. 238 v ddspd supply serial eeprom positive power supply: +1.7v to +3.6v. 19, 42, 43, 48, 49, 54 (512mb, 1gb), 55, 68, 102, 161, 162, 167, 168, 196 (512mb), 173, 174, nc ? no connect: these pins should be left unconnected. 137, 138, 220, 221 rfu ? reserved for future use table 5: pin descriptions pin numbers may not correlate with symbols. refer to pin assignment tables on page 3 for more information pin numbers symbol type description
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 6 ?2003 micron technology. inc. figure 3: functional block diagram r e g i s t e r s s0# s1# ba0-ba1 (512mb, 1gb) ba0-ba2 (2gb) a0-a12 (512mb) a0-a13 (1gb, 2gb) ras# cas# we# cke0 cke1 odt0 odt1 reset# ck ck# rs0#: ddr2 sdrams rs1#: ddr2 sdrams rba0-rba1: ddr2 sdrams rba0-rba2: ddr2 sdrams ra0-ra12: ddr2 sdrams ra0-ra13: ddr2 sdrams rras#: ddr2 sdrams rcas#: ddr2 sdrams rwe#: ddr2 sdrams rcke0: ddr2 sdrams rcke1: ddr2 sdrams rodt0: ddr2 sdrams rodt1: ddr2 sdrams u6, u17 v ref v ss ddr2 sdrams ddr2 sdrams v dd ddr2 sdrams v ddspd serial pd v ddq ddr2 sdrams a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp pll ck0 ck0# 120 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 register x 2 reset# u8 u7 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm/ nu/ cs# dqs dqs# rdqs rdqs# u1 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u22 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm/ nu/ cs# dqs dqs# rdqs rdqs# u9 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u16 rs1# rs0# dqs0 dqs0# dm0/dqs9 nc/dqs9# dqs4 dqs4# dm4/dqs13 nc/dqs13# dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm/ nu/ cs# dqs dqs# rdqs rdqs# u2 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u21 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm/ nu/ cs# dqs dqs# rdqs rdqs# u10 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u15 dqs1 dqs1# dm1/dqs10 nc/dqs10# dqs5 dqs5# dm5/dqs14 nc/dqs14# dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm/ nu/ cs# dqs dqs# rdqs rdqs# u3 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u20 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm/ nu/ cs# dqs dqs# rdqs rdqs# u11 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u14 dqs2 dqs2# dm2/dqs11 nc/dqs11# dqs6 dqs6# dm6/dqs15 nc/dqs15# dq dq dq dq dq dq dq dq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm/ nu/ cs# dqs dqs# rdqs rdqs# u4 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u19 dq dq dq dq dq dq dq dq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm/ nu/ cs# dqs dqs# rdqs rdqs# u12 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u13 dqs3 dqs3# dm3/dqs12 nc/dqs12# dqs7 dqs7# dm7/dqs16 nc/dqs16# dq dq dq dq dq dq dq dq cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dm/ nu/ cs# dqs dqs# rdqs rdqs# u5 dq dq dq dq dq dq dq dq dm/ nu/ cs# dqs dqs# rdqs rdqs# u18 dqs8 dqs8# dm8/dqs17 nc/dqs17# mt47h32m8fp = ddr2 sdram used in 512mb module mt47h64m8fp = ddr2 sdram used in 1gb module mt47h128m8fp = ddr2 sdram used in 2gb module note: 1. unless otherwise noted, resistor values are 22 2. micron module part numbers are explained in the module part numbering guide at www.micron.com/numberguide.
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 7 ?2003 micron technology. inc. general description the mt18htf6472d, mt18htf12872d, and mt18htf25672d ddr2 sdram modules are high- speed, cmos, dynamic random-access 512mb, 1gb, and 2gb memory modules organized in x72 (ecc) configuration. ddr2 sdram modules use internally configured quad-bank (512mb, 1gb) or eight-bank (2gb) ddr2 sdram devices. ddr2 sdram modules use double data rate archi- tecture to achieve high-speed operation. the double data rate architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit-wide, one-clock- cycle data transfer at the internal dram core and four corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmit- ted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the mem- ory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to ddr2 sdram modules are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the device bank and the starting column location for the burst access. ddr2 sdram modules provide for programmable read or write burst lengths of four or eight locations. ddr2 sdram supports interrupting a burst read of eight with another read, or a burst write of eight with another write. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr2 sdrams allows for concurrent operation, thereby pro- viding high, effective bandwidth by hiding row pre- charge and activation time. a self refresh mode is provided, along with a power- saving power-down mode. all inputs are compatible with the jedec standard for sstl_18. all full drive-strength outputs are sstl_18-compatible. pll and register operation ddr2 sdram modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the ddr2 sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differential clock signals (ck, ck#) to the ddr2 sdram devices. the registers and pll mini- mize system and clock loading. registered mode will add one clock cycle to cl. serial presence-detect operation ddr2 sdram modules incorporate serial pres- ence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parame- ters. the remaining 128 bytes of storage are available for use by the customer. system read/write opera- tions between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresses. write protect (wp) is tied to ground on the module, permanently disabling hard- ware write protect. functional description ddr2 sdram modules use double data rate archi- tecture to achieve high-speed operation. the ddr2 architecture is essentially a 4 n -prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module consists of a sin- gle 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and four corresponding n -bit- wide, one-half-clock-cycle data transfers at the i/o pins.
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 8 ?2003 micron technology. inc. prior to normal operation, ddr2 sdram modules must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. initialization the following sequence is required for power-up and initialization and is shown in figure 4. the follow- ing sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. 1. apply power; if cke is maintained below 20 per- cent of v dd q, outputs remain disabled. to guar- antee odt is off, v ref must be valid and a low level must be applied to the odt pin (all other inputs may be undefined). at least one of the fol- lowing two sets of conditions (a or b) must be met: a .c ondition s et a v dd , v dd l and v dd q are driven from a sin- gle power converter output v tt is limited to 0.95v max v ref tracks v dd q/2. b .c ondition s et b apply v dd before or at the same time as v dd l. apply v dd l before or at the same time as v dd q. apply v dd q before or at the same time as v tt and v ref . 2. for a minimum of 200 s after stable power and clock (ck, ck#), apply nop or deselect com- mands and take cke high. 3. wait a minimum of 400ns, then issue a pre- charge all command. 4. issue an emr(2) command. (to issue an emr(2) command, provide low to ba0, and high to ba1.) 5. issue an emr(3) command. (to issue an emr(3) command, provide high to ba0 and ba1.) 6. issue an emr to enable dll. (to issue a dll enable command, provide low to ba1, a0 and provide high to ba0.) 7. issue a mode register set command for dll reset. 200 cycles of clock input is required to lock the dll. (to issue a dll reset command, provide high to a8 and provide low to ba0 and ba1.) 8. issue precharge all command. 9. issue two or more refresh commands. 10. issue a mode register set command with low to a8 to initialize device operation (i.e., to program operating parameters without resetting the dll). 11. at least 200 clocks after step 7, execute emr ocd adjust mode if desired. if ocd adjust mode is not desired, then emr ocd default command is required followed by emr ocd exit command.
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 9 ?2003 micron technology. inc. figure 4: ddr2 power-up and initialization note: 1. v tt is not applied directly to the device; however, t vtd should be greater than or equal to zero to avoid device latch-up. one of the following two conditions (a or b) must be met: a) v dd , v dd l, and v dd q are driven from a single power converter output. v tt may be 0.95v maximum during power up. v ref tracks v dd q/2. b) apply v dd before or at the same time as v dd l. apply v dd l before or at the same time as v dd q. apply v dd q before or at the same time as v tt and v ref . 2. either a nop or deselect command may be applied. 3. 200 cycles of clock (ck, ck#) are required before a read command can be issued. 4. two or more refresh commands are required. 5. emr ocd default command is required unless ocd adjust mode is used by the system; either command must be fol- lowed by an emr ocd exit command. 6. pre = precharge command, lm = load mode command, ref = refresh command, act = active command, ra = row address, ba = device bank address. 7. dqs represents dqs, dqs#, rdqs, rdqs#. 8. cke pin uses lvcmos input levels prior to state t0 . after state t0, cke pin uses sstl_18 input levels. 9. the lm command for emr(2) and emr(3) may be before or after lm command for mr (tf0) and emr (te0). address represents a0?a12, ba0?ba1 (512mb); a0?a13, ba0?ba1 (1gb); or a0?a13, ba0?ba2 (2gb). a10 should be high at states tb0 and tg0 to ensure a precharge (all device banks) command is issued. ( ) ( ) ( ) ( ) t vtd 1 cke rtt power-up: v dd and stable clock (ck, ck#) t = 200s (min) high-z dm dqs 7 high-z address 9 ck ck# t cl v tt 1 v ref v ddl v dd q command 6 nop 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) pre t0 ta0 ( ) ( ) ( ) ( ) ( ) ( ) don?t care ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t cl t ck v dd odt ( ) ( ) dq high-z t = 400ns (min) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) tb0 200 cycles of ck 3 emr with dll enable mr with dll reset t mrd t mrd t rp t rfc t rfc ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) code 9 lm pre lm ref 4 ( ) ( ) ( ) ( ) ref 4 lm 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) code 9 code 9 tg0 th0 ti0 tj0 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) mr w/o dll reset t mrd emr with ocd default 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) lm 5 lm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) tk0 tl0 tm0 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t mrd ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t mrd code 9 emr with ocd exit 5 ( ) ( ) ( ) ( ) code 9 te0 tf0 ( ) ( ) ( ) ( ) valid 3 valid normal operation emr(2) 9 emr(3) 9 t mrd t mrd ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) lm 9 lm 9 ( ) ( ) ( ) ( ) code 9 code 9 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) tc0 td0 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) lvcmos low level 8 sstl_18 low level 8 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 10 ?2003 micron technology. inc. mode register the mode register is used to define the specific mode of operation of the ddr2 sdram. this defini- tion includes the selection of a burst length, burst type, cas latency, operating mode, dll reset, write recov- ery, and power-down mode as shown in figure 5. con- tents of the mode register can be altered by re- executing the load mode (lm) command. if the user chooses to modify only a subset of the mr vari- ables, all variables (m0?m14) must be programmed when the load mode command is issued. the mode register is programmed via the ml com- mand (bits m14, m13 = 0, 0) and will retain the stored information until it is programmed again or the device loses power (except for bit m8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. the load mode command can only be issued (or reissued) when all device banks are in the precharged state. the controller must wait the specified time t mrd before initiating any subsequent operations such as an active command. violating either of these requirements will result in unspecified operation. burst length burst length is defined by bits m0?m3 as shown in figure 5. read and write accesses to the ddr2 sdram are burst-oriented, with the burst length being pro- grammable to either four or eight. the burst length determines the maximum number of column loca- tions that can be accessed for a given read or write command. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a2?a9 when the burst length is set to four and by a3?a9 when the burst length is set to eight. the remaining (least significant) address bits are used to select the starting location within the block. the pro- grammed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved. the burst type is selected via bit m3 as shown in figure 5. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in table 6. ddr2 sdram supports 4-bit burst and 8-bit burst modes only. for 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. operating mode the normal operating mode is selected by issuing a load mode command with bi t m7 set to zero, and all other bits set to the desired values as shown in figure 5. when bit m7 is ?1,? no other bits of the mode register are programmed. programming bit m7 to ?1? places the ddr2 sdram into a test mode that is only used by the manufacturer and should not be used. no operation or functionality is guaranteed if m7 bit is ?1.? figure 5: mode register (mr) definition note: 2gb mode registers tbd. burst length cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 14 dll tm wr mr burst length cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 *m13 (a13) is reserved for future use and must be programmed to '0'. burst length reserved reserved 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 0 1 burst type sequential interleaved m3 cas latency reserved reserved 2 3 4 5 reserved reserved m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 1 mode normal test m7 15 dll tm 0 1 dll reset no yes m8 write recovery reserved 2 3 4 5 6 reserved reserved m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 wr a13 mr 0 1 0 1 mode register definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m15 0 0 1 1 0 1 pd mode fast exit (normal) slow exit (low power) m12 m14 512mb address bus 1gb address bus
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 11 ?2003 micron technology. inc. dll reset dll reset is defined by bit m8 as shown in figure 5. programming bit m8 to ?1? will activate the dll reset function. bit m8 is self-clearing, meaning it returns back to a value of ?0? after the dll reset function has been issued. anytime the dll reset function is used, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be syn- chronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. write recovery write recovery time is defined by bits m9?m11 as shown in figure 5. write recovery values of 2, 3, 4, 5, or 6 may be used for programming bits m9?m11. the user is required to program the value of write recovery, which is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up a non-integer value to the next integer; wr [cycles] = t wr [ns] / t ck [ns]. reserved states should not be used as unknown operation or incompatibility with future versions may result. power-down mode active power-down (pd) mode is defined by bit m12 as shown in figure5. pd mode allows the user to determine the active power-down mode, which deter- mines performance vs. power savings. pd mode bit m12 does not apply to precharge power-down mode. when bit m12 = 0, standard active power-down mode or ?fast-exit? active power-down mode is enabled. the t xard parameter is used for ?fast-exit? active power-down exit timing. the dll is expected to be enabled and running during this mode. when bit m12 = 1, a lower power active power-down mode or ?slow-exit? active power-down mode is enabled. the t xards parameter is used for ?slow-exit? active power-down exit timing. the dll can be enabled, but ?frozen? during active power-down mode since the exit-to-read command timing is relaxed. the power difference expected between pd ?normal? and pd ?low-power? mode is defined in the i dd table. cas latency (cl) the cas latency (cl) is defined by bits m4?m6 as shown in figure 5. cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the cas latency can be set to 2, 3, 4, or 5 clocks. ddr2 sdram does not support any half clock latencies. reserved states should not be used as unknown opera- tion or incompatibility with future versions may result. ddr2 sdram also supports a feature called posted cas additive latency (al). this feature allows the read command to be issued prior to t rcd(min) by delaying the internal command to the ddr2 sdram by al clocks. the al feature is described in more detail in the extended mode register (emr) and operational sections. examples of cl = 3 and cl = 4 are shown in figure 6; both assume al = 0. if a read command is registered at clock edge n , and the cas latency is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes al = 0). extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, output drive strength, odt (r tt ), posted cas additive latency (al), off-chip driver impedance calibration (ocd), dqs# enable/disable, rdqs/rdqs# enable/disable, and output disable/enable. these functions are controlled via the bits shown in figure 7. the extended mode register is programmed via the load mode (lm) command and will retain the stored information until it is programmed again or the device loses power. reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. the extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd table 6: burst definition burst length starting column address (a2, a1, a0) order of accesses within a burst burst type = sequential burst type = interleaved 4 0 0 0 0,1,2,3 0,1,2,3 0 0 1 1,2,3,0 1,0,3,2 0 1 0 2,3,0,1 2,3,0,1 0 1 1 3,0,1,2 3,2,1,0 8 0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 0 0 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 0 1 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 0 1 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 1 0 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 1 1 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 1 1 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 12 ?2003 micron technology. inc. before initiating any subsequent operation. violating either of these requirements could result in unspeci- fied operation. dll enable/disable the dll may be enabled or disabled by program- ming bit e0 during the load mode command as shown in figure 7. the dll must be enabled for nor- mal operation. dll enable is required during power- up initialization and upon returning to normal opera- tion after having disabled the dll for the purpose of debugging or evaluation. enabling the dll should always be followed by resetting the dll using a load mode command. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled and reset upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. fail- ing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. output drive strength the output drive strength is defined by bit e1 as shown in figure 7. the normal drive strength for all outputs are specified to be sstl_18. programming bit e1 = 0 selects normal (100 percent) drive strength for all outputs. selecting a reduced drive strength option (bit e1 = 1) will reduce all outputs to approximately 60 percent of the sstl_18 drive strength. this option is intended for the support of the lighter load and/or point-to-point environments. dqs# enable/disable the dqs# enable function is defined by bit e10. when enabled (bit e10 = 0), dqs# is the complement of the differential data strobe pair dqs/dqs#. when disabled (bit e10 = 1), dqs is used in a single-ended mode and the dqs# pin is disabled. this function is also used to enable/disable rdqs#. if rdqs is enabled (e11 = 1) and dqs# is enabled (e10 = 0), then both dqs# and rdqs# will be enabled. figure 6: cas latency (cl) d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# cl = 3 (al = 0) read burst length = 4 posted cas# additive latency (al) = 0 shown with nominal t ac, t dqsck, and t dqsq t0 t1 t2 don?t care transitioning data nop nop nop d out n t3 t4 t5 nop nop t6 nop d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# cl = 4 (al = 0) read t0 t1 t2 nop nop nop d out n t3 t4 t5 nop nop t6 nop
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 13 ?2003 micron technology. inc. rdqs enable/disable the rdqs enable function is defined by bit e11 as shown in figure 7, extended mode register definition. when enabled (e11 = 1), rdqs is identical in function and timing to data strobe dqs during a read. during a write operation, rdqs is ignored by the ddr2 sdram. if rdqs is disabled, rdqs pins are used for data mask. figure 7: extended mode register definition note: 2gb extended mode register tbd. output enable/disable the output enable function is defined by bit e12 as shown in figure 7. when enabled (e12 = 0), all out- puts (dqs, dqs, dqs#, rdqs/rdqs#) function nor- mally. when disabled (e12 = 1), all ddr2 sdram outputs (dqs, dqs, dqs#) are disabled removing out- put buffer current. the output disable feature is intended to be used during i dd characterization of read current. on die termination (odt) odt effective resistance r tt ( eff) is defined by bits e2 and e6 of the emr as shown in figure 7. the odt feature is designed to improve signal integrity of the memory channel by allowing the ddr2 sdram con- troller to independently turn on/off odt for any or all devices. r tt effective resistance values of 75 and 150 are selectable and apply to each dq, dqs/dqs#, rdqs/rdqs# and dm signals. bits (e6, e2) determine what odt resistance is enabled by turning on/off ?sw1? or ?sw2?. the odt effective resistance value is selected by enabling switch ?sw1,? which enables all ?r1? values that are 150 each, enabling an effective resistance of 75 (r tt ( eff1) = ?r1? / 2). similarly, if ?sw2? is enabled, all ?r2? values that are 300 each, enable an effective odt resistance of 150 (r tt ( eff2) = ?r2?/2). reserved states should not be used, as unknown operation or incompatibility with future versions may result. the odt control pin is used to determine when r tt ( eff) is turned on and off, assuming odt has been enabled via bits e2 and e6 of the emr. the odt fea- ture and odt input pin are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge power-down modes of opera- tion. if self refresh operation is used, r tt ( eff) should always be disabled and the odt input pin is disabled by the ddr2 sdram. during power-up and initialization of the ddr2 sdram, odt should be dis- abled until the emr command is issued to enable the odt feature, at which point the odt pin will deter- mine the r tt ( eff) value. off-chip driver (ocd) impedance calibration the ddr2 sdram output off-chip (ocd) driver impedance calibration operation is defined by bits e7? e9. ocd is intended to allow the system to calibrate and match pull-up to pull-down impedance to 18 nominal. ocd is not intended to allow a wide range of impedance calibration outside of the 18 nominal driver impedance. dll posted cas# r tt out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 14 ocd program ods r tt dqs# rdqs emr dll posted cas# rtt out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * e13 (a13) is reserved for future use and must be programmed to '0'. 0 1 output drive strength 100% 60% e1 posted cas# additive latency (al) 0 1 2 3 4 reserved reserved reserved e3 0 1 0 1 0 1 0 1 e4 0 0 1 1 0 0 1 1 e5 0 0 0 0 1 1 1 1 0 1 dll enable enable (normal) disable (test/debug) e0 15 0 1 rdqs enable no yes e11 ocd program a13 ods rtt dqs# 0 1 dqs# enable enable disable e10 rdqs rtt (nominal) rtt disabled 75 ohm 150 ohm reserved e2 0 1 0 1 e6 0 0 1 1 ocd operation ocd calibration mode exit drive(1) pull-up drive(0) pull-down ocd enter adjust mode ocd calibration default e7 0 1 0 0 1 e8 0 0 1 0 1 e9 0 0 0 1 1 0 1 outputs enabled disabled e12 0 1 0 1 mode register definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e15 0 0 1 1 e14 emr 512mb address bus 1gb address bus
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 14 ?2003 micron technology. inc. posted cas additive latency (al) posted cas additive latency (al) is supported to make the command and data bus efficient for sustain- able bandwidths in ddr2 sdram. bits e3?e5 define the value of al as shown in figure 7. bits e3?e5 allow the user to program the ddr2 sdram with a cas# additive latency of 0, 1, 2, 3, or 4 clocks. reserved states should not be used as unknown operation or incom- patibility with future versions may result. in this operation, the ddr2 sdram allows a read or write command to be issued prior to t rcd (min) with the requirement that al t rcd(min). a typical application using this feature would set al = t rcd (min) - 1 x t ck. the read or write command is held for the time of the additive latency (al) before it is issued internally to the ddr2 sdram device. read latency (rl) is controlled by the sum of the posted cas additive latency (al) and cas latency (cl); rl = al + cl. write latency (wl) is equal to read latency minus one clock; wl = al + cl - 1 x t ck. an example of a read latency is shown in figure 8. an example of a write latency is shown in figure 9. figure 8: read latency figure 9: write latency d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# al = 2 active n burst length = 4 shown with nominal t ac, t dqsck, and t dqsq t0 t1 t2 don?t care transitioning data read n nop nop d out n t3 t4 t5 nop t6 nop t7 t8 nop nop cl = 3 rl = 5 cas# latency (cl) = 3 additive latency (al) = 2 read latency (rl) = al + cl = 5 t rcd (min) nop ck ck# command dq dqs, dqs# active n burst length = 4 t0 t1 t2 don?t care transitioning data nop nop t3 t4 t5 nop write n t6 nop d in n + 3 d in n + 2 d in n + 1 wl = al + cl - 1 = 4 t7 nop d in n cas# latency (cl) = 3 additive latency (al) = 2 write latency = al + cl -1 = 4 t rcd (min) nop al = 2 cl - 1 = 2
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 15 ?2003 micron technology. inc. extended mode register 2 (emr2) the extended mode register 2 (emr2) controls functions beyond those controlled by the mode regis- ter. currently all bits in emr2 are reserved as shown in figure 10. the emr2 is programmed via the load mode command and will retain the stored informa- tion until it is programmed again or the device loses power. reprogramming the extended mode register will not alter the contents of the memory array, pro- vided it is performed correctly. the extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent operation. violating either of these requirements could result in unspeci- fied operation. figure 10: extended mode register 2 (emr2) definition note: 2gb extended mode register tbd. extended mode register set 3 (emr3) the extended mode register 3 (emr3) controls functions beyond those controlled by the mode regis- ter. currently all bits in emr3 are reserved as shown in figure 11. the emr3 is programmed via the load mode command and will retain the stored informa- tion until it is programmed again or the device loses power. reprogramming the extended mode register will not alter the contents of the memory array, pro- vided it is performed correctly. the extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent operation. violating either of these requirements could result in unspeci- fied operation. figure 11: extended mode register 3 (emr3) definition note: 2gb extended mode register tbd. a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 * e12 (a12)?e0 (a0) are reserved for future use and must all be programmed to '0.' 14 emr(2) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * e13 (a13) - e0 (a0) are reserved for future use and must all be programmed to '0'. 15 a13 0 1 0 1 mode register definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m15 0 0 1 1 m14 emr2 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 512mb address bus 1gb address bus a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 * e12 (a12)?e0 (a0) are reserved for future use and must all be programmed to '0.' 14 emr(3) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * e13 (a13) - e0 (a0) are reserved for future use and must all be programmed to '0'. 15 a13 0 1 0 1 mode register definition mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m15 0 0 1 1 m14 emr3 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 512mb address bus 1gb address bus
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 16 ?2003 micron technology. inc. command truth tables ta b l e 7 , co m m an d s tr ut h ta b l e p rov i d e s a q u i c k reference of ddr2 sdram available commands. refer to the 256mb, 512mb, or 1gb ddr2 sdram compo- nent data sheet for more truth table definitions, including cke power-down modes and device bank- to-bank commands. note: 1. all ddr2 sdram commands are defined by states of cs#, ra s#, cas#, we#, and cke at the rising edge of the clock. 2. device bank addresses (ba) determine which device bank is to be operated upon. for emr, ba selects an extended mode register. 3. burst reads or writes at bl = 4 cannot be terminated or interrupted. see sections ?read interrupted by a read? and ?write interrupted by a write? for other restrictions and details. 4. the power down mode does not perform any refresh operati ons. the duration of power-down is therefore limited by the refresh requirements outlined in the ac parametric section. 5. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. see the odt section for details. 6. ?x? means ?h or l? (but a defined logic level). 7. self refresh exit is asynchronous. 8. ba2 valid for 2gb only; a13 valid for 1gb and 2gb only. table 7: commands truth table notes: 1, 5 function cke cs# ras# cas# we# ba2, ba1, ba0 8 a13? a11 8 a10 a9?a0 notes previous cycle current cycle mode register set h h llllba op code 2 refresh h h lllh x x x x 6 self refresh entry h l lllh x x x x self refresh exit l hxxxxxxxx 6, 7 lhhhxxxx single device bank precharge hhllhlbaxlx2, 6 all device banks precharge hhllhlxxhx6 device bank activate h h l l h h ba row address 6 write h h l h l l ba column address l column address 2, 3 write with auto precharge h h l h l l ba column address h column address 2, 3 read h h l h l h ba column address l column address 2, 3 read with auto precharge h h l h l h ba column address h column address 2, 3 no operation h xlhhhxxxx6 device deselect h xhxxxxxxx6 power-down entry h lhxxxxxxx4, 6 lhhhxxxx power-down exit l hhxxxxxxx4, 6 lhhhxxxx
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 17 ?2003 micron technology. inc. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. v dd and v dd q must track each other. v dd q must be less than or equal to v dd . 2. v ref is expected to equal v dd q/2 of the transmitting device and to track va riations in the dc level of the same. peak- to-peak noise (non-common mode) on v ref may not exceed 1percent of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref (dc). this measurement is to be taken at the nearest v ref bypass capacitor. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 4. v dd q tracks with v dd ; v dd l tracks with v dd . input electrical characteristics and operating conditions table 8: absolute maximum dc ratings symbol parameter min max units v dd v dd supply voltage relative to v ss -1.0 2.3 v v dd q v dd q supply voltage relative to v ss -0.5 2.3 v v dd l v dd l supply voltage relative to vss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 c t opr operating temperature (t opr ) 055c i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v; (all other pins not under test = 0v) command/address, ras#, cas#, we#, s#, cke, odt -5 5 a ck, ck# -10 10 dm -10 10 i oz output leakage current; 0v v out v dd q; dqs and odt are disabled dq, dqs -10 10 a table 9: recommended dc operating conditions all voltages referenced to v ss parameter symbol min nom max units notes supply voltage v dd 1.7 1.8 1.9 v 1 v dd l supply voltage v dd l 1.7 1.8 1.9 v 4 i/o supply voltage v dd q 1.7 1.8 1.9 v 4 i/o reference voltage v ref 0.49 x v dd q0.50 x v dd q0.51 x v dd qv 2 i/o termination voltage (system) v tt v ref - 40 v ref v ref + 40 mv 3 table 10: input dc logic levels all voltages referenced to v ss parameter symbol min max units notes input high (logic 1) voltage v ih ( dc )v ref + 125 v dd q + 300 mv input low (logic 0) voltage v il ( dc )-300 v ref - 125 mv
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 18 ?2003 micron technology. inc. i dd specifications and conditions i dd specifications are tested after the device is prop- erly initialized. 0c t opr +55c. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v dd l= +1.8v 0.1v, v ref =v dd q/2. input slew rate is specified by ac parametric test conditions. i dd parameters are specified with odt disabled. data bus consists of dq, dm, dqs, dqs#. i dd values must be met with all combinations of emr bits 10 and 11. definitions for i dd conditions: low is defined as v in v il (ac) (max) high is defined as v in v ih (ac) (min) stable is defined as inputs stable at a high or low level floating is defined as inputs at v ref = v dd q/2 switching is defined as inputs changing between high and low every other clock cycle (once per two clocks) for address and control sig- nals switching is defined as inputs changing between high and low every other data transfer (once per clock) for dq signals not including masks or strobes i dd 7 conditions ta b l e 1 3 , i dd 7: operating current, specifies detailed timing requirements for i dd 7. changes will be required if timing parameter changes are made to the specification. note: all device banks are being interleaved at minimum t rc (i dd ) without violating t rrd (i dd ) using a burst length of 4. con- trol and address bus inputs are stable during deselects. i out = 0ma. table 11: input ac logic levels all voltages referenced to v ss parameter symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref + 250 - mv input low (logic 0) voltage v il ( ac )? v ref - 250 mv ta bl e 1 2 : g e ne r a l i dd parameters i dd parameter -53e -40e units cl (i dd ) 43 t ck t rcd (i dd ) 15 15 ns t rc (i dd ) 60 60 ns t rrd (i dd ) 7.5 7.5 ns t ck (i dd ) 3.75 5 ns t ras min (i dd ) 45 45 ns t ras max (i dd ) 70,000 70,000 ns t rp (i dd ) 15 15 ns t rfc (i dd ) 512mb 75 75 ns 1gb 105 105 ns 2gb 127.5 127.5 ns ta bl e 1 3 : i dd 7: operating current all bank interleave read operation; legend: a = active; ra = read auto precharge; d = deselect speed grade idd7 timing patterns -53e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -40e a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 19 ?2003 micron technology. inc. ta bl e 1 4 : d dr 2 i dd specifications an d conditions ? 512mb notes: 1?5; notes appear on page 25. values shown for ddr2 sdram components only. parameter/condition symbol -53e -40e units operating one device bank active-precharge current; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid commands; address bus inputs are sw itching; data bus inputs are switching. i dd 0 a 765 707 ma operating one device bank active-read-precharge current; iout = 0ma; bl = 4, cl = cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i dd 4w. i dd 1 a 855 797 ma precharge power-down current ; all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. i dd 2p b 90 63 ma precharge quiet standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating. i dd 2q b 450 378 ma precharge standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching. i dd 2n b 540 450 ma active power-down current ; all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. fast pdn exit mr[12] = 0 i dd 3p b 342 270 ma slow pdn exit mr[12] = 1 162 126 ma active standby current ; all device banks open; t ck = t ck(i dd ), t ras = t ras max (i dd ), t rp = t rp(i dd ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 3n b 702 576 ma operating burst write current ; all device banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 4w a 1,485 1,157 ma operating burst read current ; all device banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are sw itching; data bus inputs are switching. i dd 4r a 1,305 1,022 ma burst refresh current ; t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, cs# is high between valid commands; other control and ad dress bus inputs are switching; data bus inputs are switching. i dd 5 b 3,060 2,970 ma self refresh current ; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. i dd 6 b 54 54 ma operating device bank interleave read current ; all device banks interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc(i dd ), t rrd = t rrd(i dd ), t rcd = t rcd(i dd ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching; see i dd 7 conditions for detail. i dd 7 a 2,205 2,102 ma note: a - value calculated as one module rank in this operating condition, and all other module ranks in i dd 2 p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 20 ?2003 micron technology. inc. ta bl e 1 5 : d dr 2 i dd specifications and conditions ? 1gb notes: 1?5; notes appear on page 25. values shown for ddr2 sdram components only. parameter/condition symbol -53e -40e units operating one device bank active-precharge current; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 0 a tbd tbd ma operating one device bank active-read-precharge current; iout = 0ma; bl = 4, cl = cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i dd 4w. i dd 1 a tbd tbd ma precharge power-down current ; all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. i dd 2p b tbd tbd ma precharge quiet standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating. i dd 2q b tbd tbd ma precharge standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching. i dd 2n b tbd tbd ma active power-down current ; all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. fast pdn exit mr[12] = 0 i dd 3p b tbd tbd ma slow pdn exit mr[12] = 1 tbd tbd ma active standby current ; all device banks open; t ck = t ck(i dd ), t ras = t ras max (i dd ), t rp = t rp(i dd ); cke is high, cs# is high between valid commands; ot her control and address bus inputs are switching; data bus inputs are switching. i dd 3n b tbd tbd ma operating burst write current ; all device banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 4w a tbd tbd ma operating burst read current ; all device banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 4r a tbd tbd ma burst refresh current ; t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 5 b tbd tbd ma self refresh current ; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. i dd 6 b tbd tbd ma operating device bank interleave read current ; all device banks interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc(i dd ), t rrd = t rrd(i dd ), t rcd = t rcd(i dd ); cke is high, cs# is high between valid commands; addre ss bus inputs are stable during deselects; data bus inputs are switching; see i dd 7 conditions for detail. i dd 7 a tbd tbd ma note: a - value calculated as one module rank in this operating condition, and all other module ranks in i dd 2 p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 21 ?2003 micron technology. inc. ta bl e 1 6 : d dr 2 i dd specifications and conditions ? 2gb notes: 1?5; notes appear on page 25; values shown for ddr2 sdram components only parameter/condition symbol -53e -40e units operating one device bank active-precharge current; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 0 a tbd tbd ma operating one device bank active-read-precharge current; iout = 0ma; bl = 4, cl = cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i dd 4w. i dd 1 a tbd tbd ma precharge power-down current ; all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. i dd 2p b tbd tbd ma precharge quiet standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating. i dd 2q b tbd tbd ma precharge standby current ; all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching. i dd 2n b tbd tbd ma active power-down current ; all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. fast pdn exit mr[12] = 0 i dd 3p b tbd tbd ma slow pdn exit mr[12] = 1 tbd tbd ma active standby current ; all device banks open; t ck = t ck(i dd ), t ras = t ras max (i dd ), t rp = t rp(i dd ); cke is high, cs# is high between valid commands; ot her control and address bus inputs are switching; data bus inputs are switching. i dd 3n b tbd tbd ma operating burst write current ; all device banks open, continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 4w a tbd tbd ma operating burst read current ; all device banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. i dd 4r a tbd tbd ma burst refresh current ; t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 5 b tbd tbd ma self refresh current ; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. i dd 6 b tbd tbd ma operating device bank interleave read current ; all device banks interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc(i dd ), t rrd = t rrd(i dd ), t rcd = t rcd(i dd ); cke is high, cs# is high between valid commands; addre ss bus inputs are stable during deselects; data bus inputs are switching; see i dd 7 conditions for detail. i dd 7 a tbd tbd ma note: a - value calculated as one module rank in this operating condition, and all other module ranks in i dd 2 p (cke low) mode. b - value calculated reflects all module ranks in this operating condition.
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 22 ?2003 micron technology. inc. table 17: capacitance parameters are sampled; v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f = 100 mhz, 0c t opr +55c, v out ( dc ) = v dd q/2, v out (peak to peak) = 0.1v; dm input is grouped with i/o pins, reflecting the fact that they are matched in loading parameter symbol min max units input capacitance: ck, ck# c i1 2.0 3.0 pf input capacitance: ba0?ba2, a0?a13 , ras#, cas#, we#, s#, cke, odt c i2 2.5 3.5 pf input/output capacitance: dq, dqs, dm c io 5.0 8.0 pf table 18: ac operating conditions notes: 1?5; notes appear on page 25; 0c t opr +55c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -53e -40e parameter symbol min max min max units notes clock clock cycle time cl = 4 t ck (4) 3,750 8,000 5,000 8,000 ps 16, 25 cl = 3 t ck (3) 5,000 8,000 ? ? ps 16, 25 ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 19 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 19 half clock period t hp min ( t ch, t cl) min ( t ch, t cl) ps 20 clock jitter t jit tbd tbd tbd tbd ps 18 data dq output access time from ck/ck# t ac -500 +500 -600 +600 ps data-out high-impedance window from ck/ ck# t hz t ac max t ac max ps 8, 9 data-out low-impedance window from ck/ ck# t lz t ac min t ac max t ac min t ac max ps 8, 10 dq and dm input setup time relative to dqs t ds 100 150 ps 7, 15, 22 dq and dm input hold time relative to dqs t dh 225 275 ps 7, 15, 22 dq and dm input pulse width (for each input) t dipw 0.35 0.35 t ck data hold skew factor t qhs 400 450 ps dq?dqs hold, dqs to first dq to go nonvalid, per access t qh t hp - t qhs t hp - t qhs ps 15, 17 data valid output window (dvw) t dvw t qh - t dqsq t qh - t dqsq ns 15, 17
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 23 ?2003 micron technology. inc. data strobe dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck -450 +450 -500 +500 ps dqs falling edge to ck rising ? setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising ? hold time t dsh 0.2 0.2 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq 300 350 ps 15, 17 dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 23 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck dqs write preamble setup time t wpres 00ps12, 13 dqs write preamble t wpre 0.25 0.25 t ck dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 11 write command to first dqs latching transition t dqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 t ck command and address address and control input pulse width for each input t ipw 0.6 0.6 t ck address and control input setup time t is 250 350 ps 6, 22 address and control input hold time t ih 375 475 ps 6, 22 cas# to cas# command delay t ccd 22 t ck active to active (same bank) command t rc 60 65 ns active bank a to active bank b command t rrd 7.5 7.5 ns 28 active to read or write delay t rcd 15 20 ns active to precharge command t ras 45 70,000 45 70,000 ns 21 internal read to precharge command delay t rtp 7.5 7.5 ns 24, 28 write recovery time t wr 15 15 ns 28 auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp ns 23 internal write to read command delay t wtr 7.5 10 ns 28 precharge command period t rp 15 20 ns load mode command cycle time t mrd 22 t ck ocd drive mode delay t oit 012012ns cke low to ck,ck# uncertainty t delay 4.375 4.375 5.83 5.83 ns 29 refresh refresh to refresh command interval 512mb t rfc 75 70,000 75 70,000 ns 14 1gb 105 105 2gb 127.5 127.5 average periodic refresh interval t refi 7.8 7.8 s 14 table 18: ac operating conditions (continued) notes: 1?5; notes appear on page 25; 0c t opr +55c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -53e -40e parameter symbol min max min max units notes
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 24 ?2003 micron technology. inc. self refresh exit self refresh to non-read command t xsnr t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 t ck exit self refresh timing reference t isxr 250 350 ps 6, 30 odt odt turn-on delay t aond 2222 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 t ac (min) t ac (max) + 1000 ps 26 odt turn-off delay t aofd 2.5 2.5 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps 27 odt turn-on (power-down mode) t aonpd t ac (min) + 2000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 33 t ck odt power-down exit latency t axpd 88 t ck power-down exit active power-down to read command, mr[bit12=0] t xard 22 t ck exit active power-down to read command, mr[bit12=1] t xards 6 - al 6 - al t ck exit precharge power-down to any non- read command. t xp 22 t ck exit precharge power-down to read command. t xprd 6 - al 6 - al t ck cke minimum high/low time t cke 33 t ck table 18: ac operating conditions (continued) notes: 1?5; notes appear on page 25; 0c t opr +55c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -53e -40e parameter symbol min max min max units notes
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 25 ?2003 micron technology. inc. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.0v in the test environment and parame- ter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1.0v/ns for signals in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are as defined in the sstl_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. command/address minimum input slew rate = 1.0v/ns and is referenced to the crosspoint of ck/ ck#. t is timing is referenced to vih(ac) for a rising signal and v il (ac) for a falling signal . tih timing is referenced to v ih (dc) for a rising signal and v il (dc) for a falling signal. derating values for com- mand/address input signal slew rates < 1.0v/ns are tbd. 7. data minimum input slew rate = 1.0v/ns and is referenced to the crosspoi nt of dqs/dqs# if dif- ferential strobe feature is enabled. tds timing is referenced to v ih (ac) for a rising signal and v il (ac) for a falling signal. t dh timing is referenced to v ih (dc) for a rising signal and v il (dc) for a falling signal. derating values for data input sig- nal slew rates < 1.0v/ns are tbd. 8. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving ( t hz) or begins driving ( t lz). 9. this maximum value is derived from the refer- enced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 10. t lz (min) will prevail over a t dqsck (min) + t rpre (max) condition. 11. the intent of the don?t care state after completion of the postamble is the dqs-driven signal should either be high, low or high-z and that any signal transition within the input switching region must follow valid input requirements. that is if dqs transitions high [above v ih dc (min)] then it must not transition low (below v ih dc) prior to t dqsh(min). 12. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 13. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low ) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 14. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. however, an refresh command must be asserted at least once every 70.3s or t rfc (max); issuing more than eight refresh commands back-to-back at t rfc (min) is not allowed. 15. each byte lane has a corresponding dqs. 16. ck and ck# input slew rate must be 1 v/ns ( 2 v/ns if measured differentially). 17. the data valid window is derived by achieving other specifications: t hp, ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct proportion to the clock duty cycle and a practicle data valid window can be derived. 18. t jit specification is currently tbd. 19. min( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch). for example, t cl and t ch are = 50 percent of the period, less the half period jitter [ t jit(hp)] of the clock source, and less the half period jitter due to cross talk [ t jit(cross talk)] into the clock traces. 20. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs. output (v out ) reference point 25 ? v tt = v dd q/2
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 26 ?2003 micron technology. inc. 21. reads and writes with auto precharge are allowed to be issued before t ras (min) is satisfied since t ras lockout feature is supported in ddr2 sdram. 22. v il /v ih ddr2 overshoot/undershoot. refer to 256mb, 512mb, or 1gb ddr2 sdram component data sheet for more detailed information. 23. t dal = (nwr) + ( t rp/ t ck): for each of the terms above, if not already an integer, round to the next highest integer. t ck refers to the application clock period; nwr refers to the t wr parameter stored in the mr[11,10,9]. example: for -53e at tck = 3.75 ns with t wr programmed to four clocks. t dal = 4 + (15 ns/3.75 ns) clocks = 4 +(4)clocks = 8 clocks. 24. this is a minimum requirement. minimum read to internal precharge timing is al + bl/2 pro- viding the t rtp and t ras (min) have been satis- fied. the ddr2 sdram will automatically delay the internal precharge command until t ras (min) has been satisfied. 25. operating frequency is only allowed to change during self refresh mode or precharge power- down mode. anytime the operating frequency is changed, not including jitter, the dll is required to be reset, followed by 200 clock cycles. 26. odt turn-on time t aon (min) is when the device leaves high impedance and odt resistance begins to turn on. odt turn-on time t aon (max) is when the odt resistance is fully on. both are measured from t aond. 27. odt turn-off time t aof (min) is when the device starts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high impedance. both are measured from t aofd. 28. this parameter has a two clock minimum require- ment at any t ck. 29. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition. 30. t isxr is equal to t is and is used for cke setup time during self refresh exit.
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 27 ?2003 micron technology. inc. note: 1. timing and switching specifications for the register listed above are critical for proper operation of the ddr2 sdram registered dimms. these are meant to be a subset of the parameters for the specific device used on the module. detailed information for this registe r is available in jedec standard jesd82. 2. this parameter is not necessarily production tested. 3. data inputs must be low a minimum time of t act (max), after reset# is taken high. 4. data and clock inputs must be held at valid levels (not floating) a minimum time of t inact (max), after reset# is taken low. table 19: register timing requirements and switching characteristics symbol parameter condition 0c t opr +55c v dd = +1.8v 0.1v units min max v oh i oh = -tbd ma tbd ? v v ol i ol = tbd ma ? tbd v i i all inputs v i = v dd or gnd ? 5 a i dd static standby reset# = gnd ? 100 a static operating reset# = v dd , v i = v ih (ac) or v il (ac), i 0 = 0 ? tbd ma i ddd dynamic operating ? clock only reset# = v dd , v i = v ih (ac) or v il (ac), i 0 = 0; ck and ck# switching 50% duty cycle tbd tbd a dynamic operating ? per each data input, 1:1 mode r eset# = v dd , v i = v ih (ac) or v il (ac), i 0 = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2, 50% duty cycle tbd tbd dynamic operating ? per each data input, 1:2 mode reset# = v dd , v i = v ih (ac) or v il (ac), i 0 = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2, 50% duty cycle tbd tbd c i data inputs v i = v ref 250mv 2.5 3.5 pf ck and ck# v icr = 0.9v, v id = 600mv 2 3 reset v i = v dd or gnd tbd tbd table 20: register electrical characteristics note: 1 register symbol parameter condition 0c t opr +55c v dd = +1.8v 0.1v units notes min max sstl (bit pattern by jesd82) f clock clock frequency ? 270 mhz t w pulse duration 1 ? ns t act differential inputs active time ?tbdns2, 3 t inact differential inputs inactive time ?tbdns2, 4 t su setup time data before ck high, ck# low 0.7 ? ns data before ck high, ck# low 0.5 ? ns odt, cke, and data before ck high, ck# low 0.5 ? t h hold time oke, cke, and data after ck high, ck# low 0.50 ? ns
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 28 ?2003 micron technology. inc. table 21: pll clock driver electrical characteristics total i dd = i dd q = i add = f ck x c pd x v dd q, solving for c pd = (i dd q + i add )/(f ck x v dd q) where f ck is the input frequency, v dd q is the power supply and cpd is the power dissipation capacitance symbol parameter test condition 0c t opr +55c v dd = +1.8v 0.1v units notes min nominal max v ik all inputs i i = -18 m a? ? -1.2v v oh high output voltage i oh = -100a v dd q/2 - 0.2 ? ? v i oh = -9ma 1.1 ? ? v v ol low output voltage i ol = 100a ? 0.1 a i ol = 9ma 0.6 v i odl output disabled low current oe = l, v odl = 100mv 100 ? ? a v od output differential voltage, the magnitude of the difference between the true and complimentary outputs 0.5 ? ? v i i ck, ck# v i = v dd q or gnd ? ? 250 a i ddld static supply current: i dd q + i add ck and ck# = l ? ? 500 a i dd dynamic supply current: i dd q + i add ck and ck# = 270 mhz, all outputs are open (not connected to a pcb) ??300ma1 c i ci and ck# v i = v dd q or gnd 2?3pf c i ( ) ci and ck# v i = v dd q or gnd v dd q/2 - 0.2 ? 0.25 pf
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 29 ?2003 micron technology. inc. note: 1. timing and switching specifications for the pll listed above are critical for proper operation of the ddr2 sdram registered dimms. these are meant to be a subset of th e parameters for the specific device used on the module. detailed information for this pll is available in jedec standard jesd82. 2. static phase offset does not include jitter. 3. period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 4. design target is 60ps, unless it is unachievable. 5. v ox spedified at the dram clock input, or the test load. 6. the output slew rate is determined from the ibis model: table 22: pll clock driver timing requ irements and switching characteristics note: 1 parameter symbol 0c t opr +55c v dd = 1.85v 0.1v units notes min nominal max output enable to any y/y# t en ??8ns output enable to any y/y# t dis ??8ns cycle to cycle jitter t jit cc -40 ? 40 ps static phase offset t -50 0 50 ps 2 dynamc phase offset t dyn -50 0 50 ps 2 output clock skew t sk o ??40ps period jitter t jit per -40 ? 40 ps 3, 4 half-period jitter t jit hper -75 ? 75 ps 3 input clock slew rate t ls i 1.0 2.5 4 v/ns output clock slew rate t ls o 1.5 2.5 3 v/ns 6 output differential-pair cross-voltage v ox v dd q/2 - 0.1 ? v dd q/2 + 0.1 v 5 ssc modulation frequency 30 ? 33 khz ssc clock input frequency deviation 0.0 ? -0.50 % pll loop bandwidth (-3db from unity gain) 2.0 ? ? mhz gnd v ddq cu877 v ck v ck
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 30 ?2003 micron technology. inc. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (fig- ure 12, data validity, and figure 13, definition of start and stop). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 14, acknowledge response from receiver). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 12: data validity figure 13: definition of start and stop figure 14: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 31 ?2003 micron technology. inc. figure 15: spd eeprom timing diagram table 23: eeprom device select code the most significant bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 sa2 sa1 sa0 rw protection register select code 0 1 1 0 sa2 sa1 sa0 rw table 24: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1? random address read 0v ih or v il 1 start, device select, rw = ?0?, address 1v ih or v il 1 restart, device select, rw = ?1? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0? page write 0v il 16 start, device select, rw = ?0? scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 32 ?2003 micron technology. inc. note: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop conditi on of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. table 25: serial presence-detect eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +1.7v to +3.6v parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd x 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il -0.6 v ddspd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li 0.10 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current: i sb 1.6 4 a power supply current, read: scl clock frequency = 100 khz i cc r 0.4 1 ma powr supply current, write: scl clock frequency = 100 khz i cc w 23ma table 26: serial presence-detect eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +1.7v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f 300 ns 2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time constant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock frequency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 33 ?2003 micron technology. inc. table 27: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low? byte description entry (version) mt18htf6472d mt18htf12872d mt18htf25672d 0 number of spd bytes used by micron 128 80 tbd tbd 1 total number of bytes in spd device 256 08 tbd tbd 2 fundamental memory type sdram ddr2 08 tbd tbd 3 number of row addresses on assembly 13 or 14 0d tbd tbd 4 number of column addresses on assembly 10 0a tbd tbd 5 dimm height and module ranks 1.18in., dual rank 61 tbd tbd 6 module data width 64 48 tbd tbd 7 module data width (continued) 000tbdtbd 8 module voltage interface levels sstl 1.8v 05 tbd tbd 9 sdram cycle time, t ck (cas latency = 4) -53e -40e 3d 50 tbd tbd 10 sdram access from clock, t ac (cas latency = 4) -53e -40e 50 60 tbd tbd 11 module configuration type ecc 02 tbd tbd 12 refresh rate/type 7.81s/self 82 tbd tbd 13 sdram device width (primary sdram) 808tbdtbd 14 error-checking sdram data width 808tbdtbd 15 minimum clock delay, back-to-back random column access 1 clock 00 tbd tbd 16 burst lengths supported 4, 8 0c tbd tbd 17 number of banks on sdram device 404tbdtbd 18 cas latencies supported 2, 3, 4 18 tbd tbd 19 reserved 000tbdtbd 20 ddr2 dimm type rdimm 01 tbd tbd 21 sdram module attributes 00 tbd tbd 22 sdram device attributes: general weak driver 01 tbd tbd 23 sdram cycle time, t ck, (cas latency = 3) -53e -40e 50 50 tbd tbd 24 sdram access from ck, t ac, (cas latency = 3) -53e -40e 50 60 tbd tbd 25 sdram cycle time, t ck, (cas latency = 2) n/a 00 tbd tbd 26 sdram access from ck, t ac, (cas latency = 2) n/a 00 tbd tbd 27 minimum row precharge time, t rp -53e -40e 3c 3c tbd tbd 28 minimum row active to row active, t rrd -53e -40e 1e 1e tbd tbd 29 minimum ras# to cas# delay, t rcd -53e -40e 3c 3c tbd tbd 30 minimum ras# pulse width, t ras -53e -40e 2d 2d tbd tbd 31 module rank density 256mb, 512mb, 1gb 40 tbd tbd
512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 34 ?2003 micron technology. inc. 32 address and command setup time, t is -53e -40e 50 60 tbd tbd 33 address and command hold time, t ih -53e -40e 50 60 tbd tbd 34 data/ data mask input setup time, t ds -53e -40e 35 40 tbd tbd 35 data/ data mask input hold time, t dh -53e -40e 35 40 tbd tbd 36 write recovery time, t wr 3c tbd tbd 37 write to read cmd delay, t wtr -53e -40e 1e 28 tbd tbd 38 read to precharge cmd delay, t rtp 1e tbd tbd 39 mem analysis probe 00 tbd tbd 40 extension for bytes 41 and 42 00 tbd tbd 41 min active auto refresh time, t rc 3c tbd tbd 42 minimum auto refresh to active/ auto refresh command period, t rfc 4b tbd tbd 43 sdram device max cycle time, t ck max 80 tbd tbd 44 sdram device max dqs-dq skew time, t dqsq -53e -40e 1e 23 tbd tbd 45 sdram device max read data hold skew factor, t qhs -53e -40e 28 2d tbd tbd 46 pll relock time 0f tbd tbd 47-61 reserved reserved 00 tbd tbd 62 spd revision release 1.0 10 10 10 63 checksum for bytes 0-62 -53e -40e 31 ae tbd tbd tbd tbd 64 manufacturer?s jedec id code micron 2c 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff ff 72 manufacturing location 01?12 01?0c 01?0c 01?0c 73-90 module part number (ascii) variable data variable data variable data 91 pcb identification code 1-9 01-09 01-09 01-09 92 identification code (continued) 0000000 93 year of manufacture in bcd variable data variable data variable data 94 week of manufacture in bcd variable data variable data variable data 95-98 module serial number variable data variable data variable data 99-127 manufacturer-specific data (rsvd) ??? table 27: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low? byte description entry (version) mt18htf6472d mt18htf12872d mt18htf25672d
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. 512mb, 1gb, 2gb (x72, dr, registered) pc2-3200, pc2-4300, 240-pin ddr2 sdram dimm preliminary 09005aef80e934a6 micron technology, inc., reserves the right to change products or specifications without notice.. htf18c64_128_256x72dg_a.fm - rev. a 10/03 en 35 ?2003 micron technology, inc figure 16: 240-pin ddr2 dimm dimensions note: all dimensions are in inches (millimeters); or typical where noted. data sheet designation advance: this datasheet contains initial descrip- tions of products still under development. the advance designation applies to mt18htf12872d and mt18htf25672d only. preliminary: initial characterization limits, subject to change upon full characterization of production devices. the preliminary designation applies to mt18htf6472d only. 1.20 (30.50) 1.175 (29.85) pin 1 0.700 (17.78) typ. 0.098 (2.50) d (2x) 0.091 (2.30) typ. 0.197 (5.0) typ. 4.840 (123.0) typ. 0.039 (1.0) typ. 0.031 (0.80) typ. 0.079 (2.00) r (4x) 0.030 (0.76) r pin 120 front view 5.256 (133.50) 5.244 (133.20) 2.48 (63.0) typ. 2.165 (55.0) typ. 0.394 (10.00) typ. back view pin 240 pin 121 0.054 (1.37) 0.046 (1.17) 0.157 (4.0) max u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u22 u21 u20 u19 u18 u17 u16 u15 u14 u13 max min

▲Up To Search▲

Price & Availability of MT18HTF12872DG-53EXX

	To Download MT18HTF12872DG-53EXX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .