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ddr2 sdram fbdimm mt18htf12872fd C 1gb mt18htf25672fd C 2gb features ? 240-pin, ddr2 fully buffered dual in-line memory module (fbdimm) ? fast data transfer rates: pc2-4200, pc2-5300, or pc2-6400 ? 1gb (128 meg x 72), 2gb (256 meg x 72) ? 3.2 gb/s, 4 gb/s, or 4.8 gb/s link transfer rates ? high-speed, 1.5v differential, point-to-point link be- tween the host controller and advanced memory buffer (amb) ? fault-tolerant; can work around a bad bit lane in each direction ? high-density scaling with up to eight fbdimm devi- cess per channel ? smbus interface to amb for configuration register access ? in-band and out-of-band command access ? deterministic protocol C enables memory controller to optimize dram ac- cesses for maximum performance C delivers precise control and repeatable memory behavior ? automatic ddr2 sdram bus and channel calibra- tion ? transmitter de-emphasis to reduce isi ? mbist and ibist test functions ? transparent mode for dram test support ? v dd = v ddq = 1.8v for dram ? v ref = 0.9v sdram command/address termination ? v cc = 1.5v for amb ? v ddspd = 3C3.6v for amb and eeprom ? serial presence-detect (spd) with eeprom ? gold edge contacts ? dual rank ? supports 95c operation with 2x refresh figure 1: 240-pin fbdimm (mo-256 r/c b) module height: 30.35mm (1.19in) options marking ? package C 240-pin dimm (pb-free) y ? frequency/cas latency C 2.5ns @ cl = 5 (ddr2-800) -80e C 3.0ns @ cl = 5 (ddr2-667) -667 C 3.75ns @ cl = 4 (ddr2-533) 1 -53e note: 1. not recommended for new designs. 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm features pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 5 cl = 4 cl = 3 -80e pc2-6400 800 533 C 12.5 12.5 55 -667 pc2-5300 667 533 400 15 15 55 -53e pc2-4200 C 533 400 15 15 55 table 2: addressing parameter 1gb 2gb refresh count 8k 8k device bank address 4 ba[1:0] 8 ba[2:0] device page size per bank 1kb 1kb device configuration 512mb (64 meg x 8) 1gb (128 meg x 8) row address 16k a[13:0] 16k a[13:0] column address 2k a[9:0] 2k a[9:0] module rank address 2 s#[1:0] 2 s#[1:0] table 3: part numbers and timing parameters C 1gb base device: mt47h64m8, 1 512mb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) link transfer rate mt18htf12872fdy-80e__ 1gb 128 meg x 72 6.4 gb/s 2.5ns/800 mt/s 5-5-5 4.8 gt/s mt18htf12872fdy-667__ 1gb 128 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 4.0 gt/s mt18htf12872fdy-53e__ 1gb 128 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 3.2 gt/s table 4: part numbers and timing parameters C 2gb base device: mt47h128m8, 1 1gb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) link transfer rate mt18htf25672fdy-80e__ 2gb 256 meg x 72 6.4 gb/s 2.5ns/800 mt/s 5-5-5 4.8 gt/s mt18htf25672fdy-667__ 2gb 256 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 4.0 gt/s mt18htf25672fdy-53e__ 2gb 256 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 3.2 gt/s notes: 1. data sheets for the base devices can be found on microns web page. 2. all part numbers end with a four-place code (not shown) that designates component, pcb, and amb revi- sions. consult factory for current revision codes. example: mt18htf25672fdy-667 e1d4. 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm features pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
pin assignments and descriptions table 5: pin assignments 240-pin fbdimm front 240-pin fbdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin sym- bol 1 v dd 31 pn3 61 pn9# 91 ps9# 1 121 v dd 151 sn3 181 sn9# 211 ss9# 1 2 v dd 32 pn3# 62 v ss 92 v ss 122 v dd 152 sn3# 182 v ss 212 v ss 3 v dd 33 v ss 63 pn10 93 ps5 123 v dd 153 v ss 183 sn10 213 ss5 4 v ss 34 pn4 64 pn10# 94 ps5# 124 v ss 154 sn4 184 sn10# 214 ss5# 5 v dd 35 pn4# 65 v ss 95 v ss 125 v dd 155 sn4# 185 v ss 215 v ss 6 v dd 36 v ss 66 pn11 96 ps6 126 v dd 156 v ss 186 sn11 216 ss6 7 v dd 37 pn5 67 pn11# 97 ps6# 127 v dd 157 sn5 187 sn11# 217 ss6# 8 v ss 38 pn5# 68 v ss 98 v ss 128 v ss 158 sn5# 188 v ss 218 v ss 9 v cc 39 v ss 69 v ss 99 ps7 129 v cc 159 v ss 189 v ss 219 ss7 10 v cc 40 pn13 1 70 ps0 100 ps7# 130 v cc 160 sn13 1 190 ss0 220 ss7# 11 v ss 41 pn13# 1 71 ps0# 101 v ss 131 v ss 161 sn13# 1 191 ss0# 221 v ss 12 v cc 42 v ss 72 v ss 102 ps8 132 v cc 162 v ss 192 v ss 222 ss8 13 v cc 43 v ss 73 ps1 103 ps8# 133 v cc 163 v ss 193 ss1 223 ss8# 14 v ss 44 dnu 74 ps1# 104 v ss 134 v ss 164 dnu 194 ss1# 224 v ss 15 v tt 45 dnu 75 v ss 105 dnu 135 v tt 165 dnu 195 v ss 225 dnu 16 dnu 46 v ss 76 ps2 106 dnu 136 dnu 166 v ss 196 ss2 226 dnu 17 reset# 47 v ss 77 ps2# 107 v ss 137 m_test (dnu) 167 v ss 197 ss2# 227 v ss 18 v ss 48 pn12 1 78 v ss 108 v dd 138 v ss 168 sn12 1 198 v ss 228 sck 19 dnu 49 pn12# 1 79 ps3 109 v dd 139 dnu 169 sn12# 1 199 ss3 229 sck# 20 dnu 50 v ss 80 ps3# 110 v ss 140 dnu 170 v ss 200 ss3# 230 v ss 21 v ss 51 pn6 81 v ss 111 v dd 141 v ss 171 sn6 201 v ss 231 v dd 22 pn0 52 pn6# 82 ps4 112 v dd 142 sn0 172 sn6# 202 ss4 232 v dd 23 pn0# 53 v ss 83 ps4# 113 v dd 143 sn0# 173 v ss 203 ss4# 233 v dd 24 v ss 54 pn7 84 v ss 114 v ss 144 v ss 174 sn7 204 v ss 234 v ss 25 pn1 55 pn7# 85 v ss 115 v dd 145 sn1 175 sn7# 205 v ss 235 v dd 26 pn1# 56 v ss 86 dnu 116 v dd 146 sn1# 176 v ss 206 dnu 236 v dd 27 v ss 57 pn8 87 dnu 117 v tt 147 v ss 177 sn8 207 dnu 237 v tt 28 pn2 58 pn8# 88 v ss 118 sa2 148 sn2 178 sn8# 208 v ss 238 v ddspd 29 pn2# 59 v ss 89 v ss 119 sda 149 sn2# 179 v ss 209 v ss 239 sa0 30 v ss 60 pn9 90 ps9 1 120 scl 150 v ss 180 sn9 210 ss9 1 240 sa1 note: 1. the following signals are cyclical redundancy code (crc) bits and thus appear out of the normal sequence: pn12/pn12#, sn12/sn12#, pn13/pn13#, sn13/sn13#, ps9/ps9#, ss9/ss9#. 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm pin assignments and descriptions pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
table 6: pin descriptions symbol type description ps[9:0] input primary southbound data, positive lines. ps#[9:0] input primary southbound data, negative lines. sck input system clock input, positive line. sck# input system clock input, negative line. scl input serial presence-detect (spd) clock input. ss[9:0] input secondary southbound data, positive lines. ss#[9:0] input secondary southbound data, negative lines. pn[13:0] output primary northbound data, positive lines. pn#[13:0] output primary northbound data, negative lines. sn[13:0] output secondary northbound data, positive lines. sn#[13:0] output secondary northbound data, negative lines. sa[2:0] i/o spd address inputs, also used to select the fbdimm number in the amb. sda i/o spd data input/output. reset# supply amb reset signal. v cc supply amb core power and amb channel interface power (1.5v). v dd supply dram power and amb dram i/o power (1.8v). v ddspd supply spd/amb smbus power (3.3v). v ss supply ground. v tt supply dram address/command/clock termination power (v dd /2). m_test C the m_test pin provides an external connection for testing the margin of v ref , which is pro- duced by a voltage divider on the module. it is not intended to be used in normal system operation and must not be connected (dnu) in a system. this test pin may have other fea- tures on future card designs and will be included in this specification at that time. dnu C do not use. 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm pin assignments and descriptions pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
system block diagram figure 2: system block diagram ck source smbus up to 8 modules ? ? ? memory controller 10 14 commodity ddr2 sdram devices ddr2 connector with unique key common clock source smbus access to buffer registers amb ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component amb ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component amb ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component amb ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component ddr2 component 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm system block diagram pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
functional block diagram figure 3: functional block diagram dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm/ cs# dqs dqs# rdqs u1 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u19 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm/ cs# dqs dqs# rdqs u6 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u13 dqs0 dqs0# dm0 dqs4 dqs4# dm4 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm/ cs# dqs dqs# rdqs u18 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u2 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm/ cs# dqs dqs# rdqs u12 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u7 dqs5 dqs5# dm5 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm/ cs# dqs dqs# rdqs u3 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u17 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm/ cs# dqs dqs# rdqs u8 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u11 dqs2 dqs2# dm2 dqs6 dqs6# dm6 dq dq dq dq dq dq dq dq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm/ cs# dqs dqs# rdqs u16 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u4 dq dq dq dq dq dq dq dq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm/ cs# dqs dqs# rdqs u10 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u9 dqs7 dqs7# dm7 dq dq dq dq dq dq dq dq cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dm/ cs# dqs dqs# rdqs u14 dq dq dq dq dq dq dq dq dm/ cs# dqs dqs# rdqs u15 dqs8 dqs8# dm8 a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp a m b sn[13:0] sn#[13:0] ss[9:0] ss#[9:0] a[15:0] ras#, cas# we#, odt0 cs0#, cs1# cke0, cke1 ck0, ck0# ck1, ck1# pn[13:0] pn#[13:0] ps[9:0] ps#[9:0] dq[63:0] dqs[8:0] dqs#[8:0] cb[7:0] dm[8:0] scl sda sa0 sa[2:] sck, sck# reset# v ref v ss v dd ddr2 sdram v ddspd spd eeprom, amb u20 command, address, and clock signals to ddr2 channel u1Cu4, u6Cu9, u10Cu19 data input/output signals to ddr2 channel u1Cu4, u6Cu9, u10Cu19 v tt v cc terminators amb ddr2 sdram spd eeprom, amb ddr2 sdram u5 cs1# cs0# dqs1 dqs1# dm5 dqs3 dqs3# dm5 out to controller in from adjacent fbdimm in from controller out to adjacent fbdimm v ss v tt ck0, ck0#, ck1, ck1#, odt0, cs0#, cke0, ras#, cas#, we#, a[15:0], ba[2:0] clock, command, and address line terminations: 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm functional block diagram pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
general description microns fbdimm devices adhere to the currently proposed industry specifications for fbdimms. the following specifications contain detailed information on fbdimm de- sign, interfaces, and theory of operation and are listed here for the system designers convenience. refer to the jedec web site for available specifications. ? fbdimm design specification C pending jedec approval ? fbdimm: architecture and protocol C jesd206 ? fbdimm: advanced memory buffer (amb) C jesd82-20 ? design for test, design for validation (df x ) specification ? serial presence-detect (spd) for fully buffered dimm C jedec standard no. 21-c, page 4.1.2.7-1 this ddr2 sdram module is a high-bandwidth, large-capacity channel solution that has a narrow host interface. fbdimm devices use ddr2 sdram devices isolated from the channel behind an amb buffer on the fbdimm. memory device capacity remains high, and total memory capacity scales with ddr2 sdram bit density. as shown in the system block diagram, the fbdimm channel provides a communica- tion path from a host controller to an array of ddr2 sdram devices, with the ddr2 sdram devices buffered behind an amb device. the physical isolation of the ddr2 sdram devices from the channel enhances the communication path and significantly increases the reliability and availability of the memory subsystem. advanced memory buffer the amb isolates the ddr2 sdram devices from the channel. this single-chip amb component, located in the center of each fbdimm, acts as a repeater and buffer for all signals and commands exchanged between the host controller and ddr2 sdram devi- ces, including data input and output. the amb communicates with the host controller and adjacent fbdimms on a system board using an industry-standard, high-speed, dif- ferential, 1.5v, point-to-point interface. the amb also enables buffering of memory traffic to support large memory capacities. refer to the jedec jesd82-20 specification for further information. i dd conditions and specifications table 7: i dd conditions symbol condition i dd_idle_0 idle current, single, or last dimm: l0 state; idle (0% bandwidth); primary channel ena- bled; secondary channel disabled; cke high; command and address lines stable; ddr2 sdram clock active i dd_idle_1 idle current, first dimm: l0 state; idle (0% bandwidth); primary and secondary channels enabled; cke high; command and address lines stable; ddr2 sdram clock active i dd_active_1 active power: l0 state; 50% dram bandwidth; 67% read; 33% write; primary and secon- dary channels enabled; ddr2 sdram clock active; cke high i dd_active_2 active power, data pass through: l0 state; 50% dram bandwidth to downstream dimm; 67% read; 33% write; primary and secondary channels enabled; ddr2 sdram clock active; cke high; command and address lines stable 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm general description pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
table 7: i dd conditions (continued) symbol condition i dd_training training: primary and secondary channels enabled; 100% toggle on all channel lanes; drams idle; 0% bandwidth; cke high; command and address lines stable; ddr2 sdram clock active i dd_ibist ibist over all ibist modes: dram idle (0% bandwidth); primary channel enabled; secon- dary channel enabled; cke high; command and address lines stable; ddr2 sdram clock active i dd_ei electrical idle: dram idle (0% bandwidth); primary channel disabled; secondary channel disabled; cke low; command and address lines floated; ddr2 sdram clock active; odt and cke driven low note: 1. actual test conditions may vary from published jedec test conditions. table 8: i dd specifications C 1gb ddr2-533 symbol i dd_idle_0 i dd_idle_1 i dd_active_1 i dd_active_2 i dd_training i dd_ibist i dd_ei units i cc 2200 3000 3400 3200 3500 3800 2000 a i dd 1420 1420 2545 1420 1420 1420 326 a total power 6.2 7.4 10.2 7.7 8.2 8.7 3.8 w table 9: i dd specifications C 1gb ddr2-667 symbol i dd_idle_0 i dd_idle_1 i dd_active_1 i dd_active_2 i dd_training i dd_ibist i dd_ei units i cc 2600 3400 3900 3700 4000 4500 2500 a i dd 1510 1510 2777 1510 1510 1510 326 a total power 7.0 8.2 11.4 8.7 9.2 10.0 4.6 w table 10: i dd specifications C 1gb ddr2-800 symbol i dd_idle_0 i dd_idle_1 i dd_active_1 i dd_active_2 i dd_training i dd_ibist i dd_ei units i cc tbd tbd tbd tbd tbd tbd tbd a i dd tbd tbd tbd tbd tbd tbd tbd a total power tbd tbd tbd tbd tbd tbd tbd w table 11: i dd specifications C 2gb ddr2-533 symbol i dd_idle_0 i dd_idle_1 i dd_active_1 i dd_active_2 i dd_training i dd_ibist i dd_ei units i cc 2200 3000 3400 3200 3500 3800 2000 a i dd 1420 1420 2425 1420 1420 1420 326 a total power 6.2 7.4 10.0 7.7 8.2 8.7 3.8 w 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm i dd conditions and specifications pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
table 12: i dd specifications C 2gb ddr2-667 symbol i dd_idle_0 i dd_idle_1 i dd_active_1 i dd_active_2 i dd_training i dd_ibist i dd_ei units i cc 2600 3400 3900 3700 4000 4500 2500 a i dd 1420 1420 2515 1420 1420 1420 326 a total power 6.8 8.1 11.0 8.5 9.0 9.8 4.6 w table 13: i dd specifications C 12b ddr2-800 symbol i dd_idle_0 i dd_idle_1 i dd_active_1 i dd_active_2 i dd_training i dd_ibist i dd_ei units i cc tbd tbd tbd tbd tbd tbd tbd a i dd tbd tbd tbd tbd tbd tbd tbd a total power tbd tbd tbd tbd tbd tbd tbd w note: 1. total power is based on maximum voltage levels, i cc at 1.575v and i dd at 1.9v. serial presence-detect table 14: serial presence-detect eeprom dc operating conditions parameter/condition symbol min max units eeprom and amb supply voltage v ddspd 3 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il C0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li 0.10 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current i sb 1.6 4 a power supply current, read: scl clock frequency = 100 khz i ccr 0.4 1 ma power supply current, write: scl clock frequency = 100 khz i ccw 2 3 ma table 15: serial presence-detect eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 C s data-out hold time t dh 200 C ns sda and scl fall time t f C 300 ns 2 data-in hold time t hd:dat 0 C s start condition hold time t hd:sta 0.6 C s clock high period t high 0.6 C s noise suppression time constant at scl, sda inputs t i C 50 ns clock low period t low 1.3 C s 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm serial presence-detect pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
table 15: serial presence-detect eeprom ac operating conditions (continued) parameter/condition symbol min max units notes sda and scl rise time t r C 0.3 s 2 scl clock frequency f scl C 400 khz data-in setup time t su:dat 100 C ns start condition setup time t su:sta 0.6 C s 3 stop condition setup time t su:sto 0.6 C s write cycle time t wrc C 10 ms 4 notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull- up resistance, and the eeprom does not respond to its slave address. serial presence-detect data for the latest serial presence-detect data, refer to micron's spd page: www.micron.com/ spd . 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm serial presence-detect pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
module dimensions figure 4: 240-pin ddr2 fbdimm 30.5 (1.201) 30.2 (1.189) pin 1 17.3 (0.681) typ 2.6 (0.102) d (2x) 5.2 (0.205) typ 5.0 (0.197) typ 123.0 (4.843) typ 1.0 (0.039) typ 0.8 (0.031) typ 1.5 (0.059) r (4x) 0.75 (0.03) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 67.0 (2.638) typ 51.0 (2.01) typ 9.5 (0.374) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 5.1 (0.201) max 1.25 (0.0492) typ 66.68 (2.63) typ 0.595 (0.0234) r 2.0 (0.079) typ 3.9 (0.153) typ (x2) 120 (2x) 2.18 (0.086) typ 74.68 (2.94) typ 3.05 (0.12) typ 66.68 (2.63) typ 24.95 (0.982) typ detail a detail a 1.19 (0.047) 1.06 (0.042) 1.06 (0.042) 45 x 0.18 (0.0071) 0.5 (0.02) r (4x) 0.75 (0.03) r 8x 9.9 (0.39) typ (x4) front view with heat spreader back view with heat spreader 7.68 (0.302) max* 3.1 (0.122) typ 5.48 (0.216) typ u1 u2 u3 u4 u5 u6 u7 u8 u10 u11 u9 u9 u1 u2 u3 u4 u5 u6 u7 u8 u10 u11 1.37 (0.054) 1.17 (0.046) *including clip radius 7.92 (0.312) notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. refer to the jedec mo document for additional design dimensions. 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm module dimensions pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 1gb, 2gb (x72, dr) 240-pin ddr2 sdram fbdimm module dimensions pdf: 09005aef81a2f237 htf18c128_256x72fdy.pdf - rev. d 12/09 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2005 micron technology, inc. all rights reserved.

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