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ddr2 sdram mini-rdimm mt18hts25672pky C 2gb mt18hts51272pky C 4gb features ? 244-pin, mini registered dual in-line memory module ? fast data transfer rates: pc2-5300, pc2-4200, or pc2-3200 ? 2gb (256 meg x 72) or 4gb (512 meg x 72) ? supports ecc error detection and correction ? dual-rank, twindie ? (2cob) dram devices ? v dd = v ddq = 1.8v ? v ddspd = 1.7C3.6v ? jedec-standard 1.8v i/o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ? 4 n -bit prefetch architecture ? multiple internal device banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst length (bl) 4 or 8 ? adjustable data-output drive strength ? 64ms, 8192-cycle refresh ? on-die termination (odt) ? serial presence-detect (spd) with eeprom ? phase-lock loop (pll) to reduce loading on system clock ? gold edge contacts ? lead-free figure 1: 244-pin mini-rdimm (mo-244 r/c x) module height: 30mm (1.18in) options marking ? parity p ? operating temperature C commercial (0c t a 70c) none C industrial (C40c t a 85c) 1 i ? package C 244-pin dimm (lead-free) y ? frequency/cl 2 C 2.5ns @ cl = 5 (ddr2-800) -80e C 3.0ns @ cl = 5 (ddr2-667) -667 notes: 1. contact micron for industrial temperature module offerings. 2. cl = cas (read) latency; registered mode will add one clock cycle to cl. table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 6 cl = 5 cl = 4 cl = 3 -80e pc2-6400 800 800 533 400 12.5 12.5 55 -800 pc2-6400 800 667 533 400 15 15 55 -667 pc2-5300 C 667 553 400 15 15 55 -53e pc2-4200 C C 553 400 15 15 55 -40e pc2-3200 C C 400 400 15 15 55 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm features pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 2gb 4gb refresh count 8k 8k row address 16k a[13:0] 32k a[14:0] device bank address 8 ba[2:0] 8 ba[2:0] twindie device configuration 2gb twindie (256 meg x 8) 4gb twindie (512 meg x 8) column address 1k a[9:0] 1k a[9:0] module rank address 2 s#[1:0] 2 s#[1:0] table 3: part numbers and timing parameters C 2gb base device: mt47h256m8thn, 1 2gb twindie ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18hts25672pk(i)y-80e__ 2gb 256 meg x 72 6.4 gb/s 2.5ns/800mt/s 5-5-5 mt18hts25672pk(i)y-667__ 2gb 256 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 table 4: part numbers and timing parameters C 4gb base device: mt47h512m8thm, 1 4gb twindie ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18hts51272pk(i)y-80e__ 4gb 512 meg x 72 6.4 gb/s 2.5ns/800mt/s 5-5-5 mt18hts51272pk(i)y-667__ 4gb 512 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 notes: 1. data sheets for the base devices can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. con- sult factory for current revision codes. example: mt18hts25672pky-667 e1. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm features pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
pin assignments table 5: pin assignments 244-pin mini-rdimm front 244-pin mini-rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v ref 32 v ss 63 v ddq 94 dqs5# 123 v ss 154 dq28 185 a3 216 nf/ rdqs5# 2 v ss 33 dq24 64 a2 95 dqs5 124 dq4 155 dq29 186 a1 217 v ss 3 dq0 34 dq25 65 v dd 96 v ss 125 dq5 156 v ss 187 v dd 218 dq46 4 dq1 35 v ss 66 v ss 97 dq42 126 v ss 157 dm3/ rdqs3 188 ck0 219 dq47 5 v ss 36 dqs3# 67 v ss 98 dq43 127 dm0/ rdqs0 158 nf/ rdqs3# 189 ck0# 220 v ss 6 dqs0# 37 dqs3 68 par_in 99 v ss 128 nf/ rdqs0# 159 v ss 190 v dd 221 dq52 7 dqs0 38 v ss 69 v dd 100 dq48 129 v ss 160 dq30 191 a0 222 dq53 8 v ss 39 dq26 70 a10 101 dq49 130 dq6 161 dq31 192 ba1 223 v ss 9 dq2 40 dq27 71 ba0 102 v ss 131 dq7 162 v ss 193 v dd 224 rfu 10 dq3 41 v ss 72 v dd 103 sa2 132 v ss 163 cb4 194 ras# 225 rfu 11 v ss 42 cb0 73 we# 104 nc 133 dq12 164 cb5 195 v ddq 226 v ss 12 dq8 43 cb1 74 v ddq 105 v ss 134 dq13 165 v ss 196 s0# 227 dm6/ rdqs6 13 dq9 44 v ss 75 cas# 106 dqs6# 135 v ss 166 dm8/ rdqs8 197 v ddq 228 nf/ rdqs6# 14 v ss 45 dqs8# 76 v ddq 107 dqs6 136 dm1/ rdqs1 167 nf/ rdqs8# 198 odt0 229 v ss 15 dqs1# 46 dqs8 77 s1# 108 v ss 137 nf/ rdqs1# 168 v ss 199 a13 230 dq54 16 dqs1 47 v ss 78 odt1 109 dq50 138 v ss 169 cb6 200 v dd 231 dq55 17 v ss 48 cb2 79 v ddq 110 dq51 139 nc 170 cb7 201 nc 232 v ss 18 nc 49 cb3 80 nc 111 v ss 140 nc 171 v ss 202 v ss 233 dq60 19 nc 50 v ss 81 v ss 112 dq56 141 v ss 172 nc 203 dq36 234 dq61 20 v ss 51 nc 82 dq32 113 dq57 142 dq14 173 v ddq 204 dq37 235 v ss 21 dq10 52 v ddq 83 dq33 114 v ss 143 dq15 174 cke1 205 v ss 236 dm7/ rdqs7 22 dq11 53 cke0 84 v ss 115 dqs7# 144 v ss 175 v dd 206 dm4/ rdqs4 237 nf/ rdqs7# 23 v ss 54 v dd 85 dqs4# 116 dqs7 145 dq20 176 a15 207 nf/ rdqs4# 238 v ss 24 dq16 55 ba2 86 dqs4 117 v ss 146 dq21 177 nf/a14 1 208 v ss 239 dq62 25 dq17 56 err_out# 87 v ss 118 dq58 147 v ss 178 v ddq 209 dq38 240 dq63 26 v ss 57 v ddq 88 dq34 119 dq59 148 dm2/ rdqs2 179 a12 210 dq39 241 v ss 27 dqs2# 58 a11 89 dq35 120 v ss 149 nf/ rdqs2# 180 a9 211 v ss 242 sda 28 dqs2 59 a7 90 v ss 121 sa0 150 v ss 181 v dd 212 dq44 243 scl 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm pin assignments pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 5: pin assignments (continued) 244-pin mini-rdimm front 244-pin mini-rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 29 v ss 60 v dd 91 dq40 122 sa1 151 dq22 182 a8 213 dq45 244 v ddspd 30 dq18 61 a5 92 dq41 152 dq23 183 a6 214 v ss 31 dq19 62 a4 93 v ss 153 v ss 184 v ddq 215 dm5/ rdqs5 note: 1. pin 177 is nf for 2gb and a14 for 4gb. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm pin assignments pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
pin descriptions the pin description table below is a comprehensive list of all possible pins for all ddr2 modules. all pins listed may not be supported on this module. see pin assignments for information specific to this module. table 6: pin descriptions symbol type description ax input address inputs: provide the row address for active commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by bax) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. see the pin assignments table for density-specific addressing information. bax input bank address inputs: define the device bank to which an active, read, write, or precharge command is being applied. ba define which mode register (mr0, mr1, mr2, and mr3) is loaded during the load mode command. ckx, ck#x input clock: differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. ckex input clock enable: enables (registered high) and disables (registered low) internal circui- try and clocks on the ddr2 sdram. dmx, input data mask (x8 devices only): dm is an input mask signal for write data. input data is masked when dm is sampled high, along with that input data, during a write ac- cess. although dm pins are input-only, dm loading is designed to match that of the dq and dqs pins. odtx input on-die termination: enables (registered high) and disables (registered low) termi- nation resistance internal to the ddr2 sdram. when enabled in normal operation, odt is only applied to the following pins: dq, dqs, dqs#, dm, and cb. the odt input will be ignored if disabled via the load mode command. par_in input parity input: parity bit for ax, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input reset: asynchronously forces all registered outputs low when reset# is low. this signal can be used during power-up to ensure that cke is low and dq are high-z. s#x input chip select: enables (registered low) and disables (registered high) the command decoder. sax input serial address inputs: used to configure the spd eeprom address range on the i 2 c bus. scl input serial clock for spd eeprom: used to synchronize communication to and from the spd eeprom on the i 2 c bus. cbx i/o check bits. used for system error detection and correction. dqx i/o data input/output: bidirectional data bus. dqsx, dqs#x i/o data strobe: travels with the dq and is used to capture dq at the dram or the con- troller. output with read data; input with write data for source synchronous opera- tion. dqs# is only used when differential data strobe mode is enabled via the load mode command. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm pin descriptions pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 6: pin descriptions (continued) symbol type description sda i/o serial data: used to transfer addresses and data into and out of the spd eeprom on the i 2 c bus. rdqsx, rdqs#x output redundant data strobe (x8 devices only): rdqs is enabled/disabled via the load mode command to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only and is ignored during write data. when rdqs is disa- bled, rdqs becomes data mask (see dmx). rdqs# is only used when rdqs is enabled and differential data strobe mode is enabled. err_out# output (open drain) parity error output: parity error found on the command and address bus. v dd /v ddq supply power supply: 1.8v 0.1v. the component v dd and v ddq are connected to the mod- ule v dd . v ddspd supply spd eeprom power supply: 1.7C3.6v. v ref supply reference voltage: v dd /2. v ss supply ground. nc C no connect: these pins are not connected on the module. nf C no function: these pins are connected within the module, but provide no functionality. nu C not used: these pins are not used in specific module configurations/operations. rfu C reserved for future use. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm pin descriptions pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
functional block diagram figure 2: functional block diagram r e g i s t e r s par_in s0# s1# ba[2:0] a[15:0] ras# cas# we# cke0 cke1 odt0 odt1 reset# err_out# rs0#: rank 0 rs1#: rank 1 rba[2/1:0]: ddr2 sdram ra[14/13:0]: ddr2 sdram rras#: ddr2 sdram rcas#: ddr2 sdram rwe#: ddr2 sdram rcke0: rank 0 rcke1: rank 1 rodt0: rank 0 rodt1: rank 1 u4, u10 v ref v ss ddr2 sdram ddr2 sdram v dd / v ddq v ddspd spd eeprom ddr2 sdram a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp pll ck0 ck0# ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 register x 2 reset# u11 u7 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm/ nf/ cs# dqs dqs# rdqs rdqs# u1b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u1t dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm/ nf/ cs# dqs dqs# rdqs rdqs# u5b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u5t dqs0 dqs0# dm0/rdqs0 nf/rdqs0# dqs4 dqs4# dm4/rdqs4 nf/rdqs4# dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm/ nf/ cs# dqs dqs# rdqs rdqs# u13b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u13t dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm/ nf/ cs# dqs dqs# rdqs rdqs# u9b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u9t dqs1 dqs1# dm1/rdqs1 nf/rdqs1# dqs5 dqs5# dm5/rdqs5 nf/rdqs5# dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm/ nf/ cs# dqs dqs# rdqs rdqs# u2b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u2t dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm/ nf/ cs# dqs dqs# rdqs rdqs# u6b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u6t dqs2 dqs2# dm2/rdqs2 nf/rdqs2# dqs6 dqs6# dm6/rdqs6 nf/rdqs6# dq dq dq dq dq dq dq dq dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm/ nf/ cs# dqs dqs# rdqs rdqs# u3b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u3t dq dq dq dq dq dq dq dq dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm/ nf/ cs# dqs dqs# rdqs rdqs# u8b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u8t dqs3 dqs3# dm3/rdqs3 nf/rdqs3# dqs7 dqs7# dm7/rdqs7 nf/rdqs7# dq dq dq dq dq dq dq dq cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dm/ nf/ cs# dqs dqs# rdqs rdqs# u12b dq dq dq dq dq dq dq dq dm/ nf/ cs# dqs dqs# rdqs rdqs# u12t dqs8 dqs8# dm8/rdqs8 nf/rdqs8# rs1# rs0# rank 0 = u1bCu3b, u5b , u6b, u8b, u9b, u12b, u13b rank 1 = u1tCu3t, u5t , u6t, u8t, u9t, u12t, u13t v ss 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm functional block diagram pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
general description ddr2 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 4 or 8-bank ddr2 sdram devices. ddr2 sdram modules use ddr architecture to achieve high-speed operation. ddr2 architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data trans- fers at the i/o pins. ddr2 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. a bidirectional data strobe (dqs, dqs#) is trans- mitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory con- troller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. com- mands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. serial presence-detect eeprom operation ddr2 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to identify the mod- ule type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimms scl (clock) sda (data), and sa (address) pins. write protect (wp) is connected to v ss , permanently disabling hardware write protection. register and pll operation ddr2 sdram modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the ddr2 sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differential clock signals (ck, ck#) to the ddr2 sdram devices. the registers and pll minimize system and clock loading. pll clock timing is defined by jedec specifications and en- sured by use of the jedec clock reference board. registered mode will add one clock cycle to cl. parity operations the registering clock driver can accept a parity bit from the systems memory control- ler, providing even parity for the control, command, and address bus. parity errors are flagged on the err_out# pin. systems not using parity are expected to function without issue if par_in and err_out# are left as no connects (nc) to the system. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm general description pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the dram devices on the module. this is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated on each devices data sheet is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. table 7: absolute maximum dc ratings symbol parameter min max units v dd /v ddq v dd /v ddq supply voltage relative to v ss C0.5 2.3 v v in , v out voltage on any pin relative to v ss C0.5 2.3 v i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) address inputs: ras#, cas#, we# s#, cke, ba, odt C5 5 a ck, ck# C250 250 dm C10 10 i oz output leakage current; 0v v out v ddq ; dqs and odt are disabled dq, dqs, dqs# C10 10 a i vref v ref leakage current; v ref = valid v ref level C36 36 a t a module ambient operating temperature commercial 0 70 c industrial C40 85 c t c 1 ddr2 sdram component case operating tempera- ture 2 commercial 0 85 c industrial C40 95 c notes: 1. the refresh rate is required to double when 85c < t c 95c. 2. for further information, refer to technical note tn-00-08: thermal applications, avail- able on microns web site. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm electrical specifications pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr2 component data sheets. component specifications are available on micron's web site. module speed grades cor- relate with component speed grades. table 8: module and component speed grades ddr2 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -1ga -187e -80e -25e -800 -25 -667 -3 -53e -37e -40e -5e design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. mi- cron encourages designers to simulate the signal characteristics of the system's memo- ry bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm dram operating conditions pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
i dd specifications table 9: i dd specifications and conditions C 2gb values are shown for the mt47h256m8 ddr2 sdram only and are computed from values specified in the 2gb twindie (256 meg x 8) component data sheet parameter/condition symbol -80e -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd0 918 873 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i cdd1 1098 1008 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i cdd2p 126 126 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus in- puts are floating i cdd2q 513 423 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i cdd2n 558 468 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i cdd3p 333 333 ma slow pdn exit mr[12] = 1 153 153 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i cdd3n 648 603 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd4w 1548 1323 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd4r 1548 1323 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i cdd5 2223 2043 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i cdd6 126 126 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high be- tween valid commands; address bus inputs are stable during deselects; data bus inputs are switching i cdd7 3123 2628 ma 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm i dd specifications pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 10: i dd specifications and conditions C 4gb values are shown for the mt47h512m8 ddr2 sdram only and are computed from values specified in the 4gb twindie (512 meg x 8) component data sheet parameter/condition symbol -80e -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd0 1017 1035 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i cdd1 1620 1440 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i cdd2p 180 180 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus in- puts are floating i cdd2q 675 585 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i cdd2n 765 675 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i cdd3p 432 432 ma slow pdn exit mr[12] = 1 162 162 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i cdd3n 720 630 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd4w 1755 1485 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd4r 1845 1665 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i cdd5 2835 2655 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i cdd6 180 180 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high be- tween valid commands; address bus inputs are stable during deselects; data bus inputs are switching i cdd7 3645 3295 ma 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm i dd specifications pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
register and pll specifications table 11: register specifications sstu32866 devices or equivalent parameter symbol pins condition min max units dc high-level input voltage v ih(dc) control, command, address sstl_18 v ref(dc) + 125 v ddq + 250 mv dc low-level input voltage v il(dc) control, command, address sstl_18 0 v ref(dc) - 125 mv ac high-level input voltage v ih(ac) control, command, address sstl_18 v ref(dc) + 250 C mv ac low-level input voltage v il(ac) control, command, address sstl_18 C v ref(dc) - 250 mv output high voltage v oh parity output lvcmos 1.2 C v output low voltage v ol parity output lvcmos C 0.5 v input current i i all pins v i = v dd or v ss C 0.5 a static standby i dd all pins reset# = v ssq (i o = 0) C5 5 ma static operating i dd all pins reset# = v ss ; v i = v ih(ac) or v il(dc) i o = 0 C 100 ma dynamic operating (clock tree) i ddd n/a reset# = v dd ; v i = v ih(dc) or v il(ac) , i o = 0; ck and ck# switch- ing 50% duty cycle C varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd ; v i = v ih(ac) or v il(dc) , i o = 0; ck and ck# switching 50% duty cy- cle; one data in/out switching at t ck/2, 50% duty cycle C varies by manufacturer a input capacitance (per device, per pin) c in all inputs except reset# v i = v ref 250mv; v dd = 1.8v 2.5 3.5 pf input capacitance (per device, per pin) c in reset# v i = v dd or v ss varies by manufacturer varies by manufacturer pf note: 1. timing and switching specifications for the register listed are critical for proper opera- tion of the ddr2 sdram rdimms. these are meant to be a subset of the parameters for the specific device used on the module. detailed information for this register is available in jedec standard jesd82. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm register and pll specifications pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 12: pll specifications cu877 device or equivalent parameter symbol pins condition min max units dc high-level input voltage v ih reset# lvcmos 0.65 v dd C v dc low-level input voltage v il reset# lvcmos C 0.35 v dd v input voltage (limits) v in reset#, ck, ck# C 0.3 v dd + 0.3 v dc high-level input voltage v ih ck, ck# differential input 0.65 v dd C v dc low-level input voltage v il ck, ck# differential input C 0.35 v dd v input differential-pair cross voltage v ix ck, ck# differential input (v ddq /2) - 0.15 (v dd /2) - 0.15 v input differential voltage v id(dc) ck, ck# differential input 0.3 v dd - 0.4 v input differential voltage v id(ac) ck, ck# differential input 0.6 v dd - 0.4 v input current i i reset# v i = v dd or v ss C10 10 a ck, ck# v i = v dd or v ss C250 250 a output disabled current i odl reset# = v ss ; v i = v ih(ac) or v il(dc) 100 C a static supply current i ddld ck = ck# = low C 500 a dynamic supply i dd n/a ck, ck# = 270 mhz, all outputs open (not con- nected to pcb) C 300 ma input capacitance c in each input v i = v dd or v ss 2 3 pf table 13: pll clock driver timing requirements and switching characteristics parameter symbol min max units stabilization time t l C 15 s input clock slew rate slr(i) 1.0 4.0 v/ns ssc modulation frequency C 30 33 khz ssc clock input frequency deviation C 0.0 C0.5 % pll loop bandwidth (C3db from unity gain) C 2.0 C mhz note: 1. pll timing and switching specifications are critical for proper operation of the ddr2 dimm. this is a subset of parameters for the specific pll used. detailed pll information is available in jedec standard jesd82. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm register and pll specifications pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
serial presence-detect for the latest spd data, refer to micron's spd page: www.micron.com/spd . table 14: spd eeprom operating conditions parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il C0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li 0.1 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current i sb 1.6 4 a power supply current, read: scl clock frequency = 100 khz i ccr 0.4 1 ma power supply current, write: scl clock frequency = 100 khz i ccw 2 3 ma table 15: spd eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time bus must be free before a new transition can start t buf 1.3 C s data-out hold time t dh 200 C ns sda and scl fall time t f C 300 ns 2 sda and scl rise time t r C 300 ns 2 data-in hold time t hd:dat 0 C s start condition hold time t hd:sta 0.6 C s clock high period t high 0.6 C s noise suppression time constant at scl, sda inputs t i C 50 s clock low period t low 1.3 C s scl clock frequency t scl C 400 khz data-in setup time t su:dat 100 C ns start condition setup time t su:sta 0.6 C s 3 stop condition setup time t su:sto 0.6 C s write cycle time t wrc C 10 ms 4 notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull- up resistance, and the eeprom does not respond to its slave address. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm serial presence-detect pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
module dimensions figure 3: 244-pin ddr2 mini-rdimm 82.127 (3.233) 81.873 (3.223) front view 30.152 (1.187) 29.848 (1.175) 20.0 (0.787) typ 10.0 (0.394) typ 1.0 (0.039) typ 2.0 (0.079) r x2 1.0 (0.039) r x2 0.50 (0.02) r 1.80 (0.071) d x2 6.0 (0.236) typ 2.0 (0.079) typ 78.0 (3.071) typ 0.60 (0.024) typ 0.45 (0.018) typ pin 1 pin 122 42.9 (1.689) typ back view 3.3 (0.130) typ 3.6 (0.142) typ 33.6 (1.323) typ 38.4 (1.512) typ 3.2 (0.126) typ 3.80 (0.150) max 1.10 (0.043) 0.90 (0.035) pin 244 pin 123 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. refer to the jedec mo document for additional design dimensions. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 2gb, 4gb (x72, dr) 244-pin ddr2 mini-rdimm module dimensions pdf: 09005aef82218d23 hts18c256_512x72pky.pdf - rev. c 3/10 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.

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