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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80b10a55 mt28c128564w18e_b.fm - rev. b, pub 11/03 en 1 ?2003 micron technology, inc. all rights reserved. 128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary ? flash and cellularram ? combo memory mt28c128532w18/w30e mt28c128564w18/w30e low voltage, wireless temperature features stacked die combo package ? includes two 64mb flash devices choice of either one 32mb or one 64mb cellularram device basic configuration flash flexible multibank architecture 4 meg x 16 async/page/burst interface support for true concurrent operations with no latency cellularram low-power, high-density design 2 meg x 16 or 4 meg x 16 configurations burst f_v cc , v cc q, f_v pp , c_v cc voltages 1.70v (min)/1.95v (max) f_v cc , c_v cc 1.70v (min)/2.24v (max) v cc q (w18) 2.20v (min)/3.30v (max) v cc q (w30) 1.80v (typ) f_v pp (in-system program/erase) 12v 5% (hv) f_ v pp tolerant (factory programming compatibility) fast programming algorithm (fpa) enhanced suspend options erase-suspend-to-read within same bank program-suspend-to-read within same bank erase-suspend-to-program within same bank each flash contains two 64-bit chip protection registers for security purposes 100,000 erase cycles per block cross-compatible command set support extended command set common flash interface (cfi) compliant manufacturer?s identification code (manid) micron ? intel ? options flash timing 60ns 1 (w18) 70ns (w18/w30) flash burst frequency 66 mhz 1 (w18) 54 mhz (w18/w30) flash boot block configuration top/top top/bottom bottom/top bottom/bottom cellularram timing 70ns 85ns cellularram burst frequency 66 mhz i/o voltage range vccq 1.70v?2.24v (w18) vccq 2.20v?3.30v (w30) manufacturer?s identification code (manid) micron (0x2ch) intel (0x89h) operating temperature range wireless temperature (-25c to +85c) package 77-ball fbga (standard) 8 x 10 grid 77-ball fbga (lead-free) 8 x 10 grid 2 note: 1. contact factory for availability. 2. contact factory for details. a b c d e f g h j k 1 2 3 4 5 6 7 8 top view (ball down) c_vss c_vss f_vpp f_ w p# f_rst# dq10 dq3 dq11 nc f_vcc a19 c_ub# dq2 dq1 dq9 nc vccq a4 a5 a3 a2 a1 a0 c_oe# nc f_ce1# c_vss f_vcc clk c_ce# a20 a8 dq13 dq14 dq6 f_vcc vssq a11 a12 a13 a15 a16 f_ce2# f_oe2# vccq c_cre c_vss f_vcc nc c_ w e# ad v # f_we# dq5 dq12 dq4 c_vcc c_vss a18 c_lb# a17 a7 a6 dq8 dq0 f_oe1# nc vssq rfu a9 a10 a14 w ait# dq7 dq15 vccq f_vss a21 figure 1: 77-ball fbga
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 128mb multibank burst flash and 32/64mb burst cellularram combo memory micron technology, inc., reserves the right to change pro ducts or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 2 ?2003 micron technology. inc. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 device general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 flash general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 flash configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 cellularram general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 part number information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 boot configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 multichip packaging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 unique ids, state machines, and registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 flash reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 3 ?2003 micron technology. inc. list of figures figure 1: 77-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: flash memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 5: 77-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 128mb multibank burst flash and 32/64mb burst cellularram combo memory micron technology, inc., reserves the right to change pro ducts or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 4 ?2003 micron technology. inc. list of tables table 1: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 2: possible boot configurations for flash die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 3: truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 4: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 6: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 7: dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 8: cfi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 9: references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 5 ?2003 micron technology. inc. device general description the mt28c128532w18/w30e/mt28c128564w18/ w30e combination flash and cellularram devices are a high-performance, high-density, memory solution that can significantly improve system performance. this memory solution is comprised of two 64mb flash devices and one 32mb or one 64mb cellularram device. it is important to note that the specifications con- tained in this document supersede the specifications listed in the referenced individual flash and cellular- ram data sheets. flash general description the flash architecture features a multipartition configuration that supports read-while-program/ erase operations with no latency. a 4mb partition size enables optimal design flexibility. two flash devices are stacked to achieve the 128mb density. each flash die has a dedicated ce# and oe# control. the stacked flash device enables soft protection for blocks, as read only, by configuring soft protection reg- isters with dedicated command sequences. for secu- rity purposes, two user-programmable 64-bit chip protection registers are provided for each flash device. the embedded word program and block erase functions are fully automated by an on-chip write state machine (wsm). an on-chip device status register can be used to monitor the wsm status and determine the progress of the program/erase tasks. each flash device has a read configuration register (rcr) that defines how the flash interacts with the memory bus. for device specifications and additional documentation concerning flash features, please refer to the mt28f644w18 data sheet at www.micron.com/ flash . flash configurations each flash memory implements a multibank archi- tecture (16 banks of 4mb each) to allow concurrent operations. any address within a block address range selects that block for the required read, program, or erase operation. each flash memory features eight 4k-word sectors (8 x 65,536 bits), designated as parameter blocks, and the remaining part is organized in main blocks of 32k words each (524,288 bits). the parameter blocks are addressed either by the low order addresses (bottom boot) or by the higher order addresses (top boot). the two flash devices can be supplied with any combination of top or bottom boot (e.g., top/top, bot- tom/bottom, top/bottom, or bottom/top). cellularram general description the cellularram architecture features high-speed cmos, dynamic random-access memories developed for low-power portable applications the cellularram device is available in either 32mb or 64mb densities. two user-accessible control registers define the device operation. the bus configuration register (bcr) defines how the cellularram device interacts with the system memory bus and is nearly identical to its counterpart on burst mode flash devices. the refresh configuration register (rcr) is used to control how refresh is performed on the cellularram array. these registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. to operate seamlessly on a burst flash bus, cellularram products have incorporated a transparent self-refresh mechanism. the hidden refresh requires no addition al support from the system memory controller and has no significant impact on device read/write performance. cellularram products include three system-acces- sible mechanisms used to minimize standby current. partial array refresh (par) limits refresh to the portion of the memory array being used. temperature com- pensated refresh (tcr) is used to adjust the refresh rate according to the ambient temperature. the refresh rate can be decreased at lower temperatures to minimize current consumption during standby. deep sleep mode halts the refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are adjusted through the refresh configuration register (rcr). for device specifications and additional documen- tation concerning cellularram features, please refer to the mt45w2mw16bfb and mt45w4mw16bfb data sheets at www.micron.com/cellularram .
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 6 ?2003 micron technology. inc. figure 2: flash memory map note: figure 2 shows a tb (top/bottom) dual flash configuration. parameter blocks ? top boot f_ce2#/f_oe2# controlled upper address space (64mb to 128mb) main main main parameter blocks ? bottom boot f_ce1#/f_oe1# controlled lower address space (0mb to 64mb) main main main
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 7 ?2003 micron technology. inc. figure 3: block diagram c_oe# c_cre c_ce# c_we# dq0 ? dq15 a0 ? a21 f_we# f_ wp# wait # flash #2 cellularram f_rst# c_ub# c_lb# 4,096k x 16 2,048k x 16 4,096k x 16 bank 31 bank 16 c_v cc f_oe2# f_ce2# adv# c_v ss flash #1 4,096k x 16 bank 15 bank 0 v cc q v ss q f_v cc f_v ss f_v pp clk f_oe1# f_ce1#
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 8 ?2003 micron technology. inc. part number information micron?s combination memory devices are available with several different combinations of features (see figure 4). figure 4: part number chart note: 1. the first character in this field refers to flash die #2. th e second character in this field refers to flash die #1. 2. contact factory for availability. valid part number combinations after building the part number from the part num- ber chart above, please go to micron?s part marking decoder web site at www.micron.com/decoder to ver- ify that the part number is offered and valid. if the device required is not on this list, please contact the factory. device marking due to the size of the package, the micron standard part number is not printed on the top of each device. instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at www.micron.com/decoder . to view the location of the abbreviated mark on the device, please refer to customer service note csn-11, ?product mark/ label,? at www.micron.com/csn . micron technology flash family 28c = dual-supply flash/cellularram combo density/organization/banks 128 = two 64mb (4,096k x 16) bank x = 5 multibank 32 banks (all banks have the same dimensions) flash access time f60 = 60ns 2 f70 = 70ns cellularram density 32 = 32mb cellularram (2 meg x 16) 64 = 64mb cellularram (4 meg x 16) flash read operation w = flash async/page/burst read package code fw = 77-ball fbga (standard) 8 x 10 grid bw = 77-ball fbga (lead-free) 8 x 10 grid 2 operating temperature range wt = wireless (-25oc to +85oc) flash burst frequency 5 = 54 mhz 6 = 66 mhz 2 flash boot block starting address 1 tt = top boot/top boot tb = top boot/bottom boot bt = bottom boot/top boot bb = bottom boot/bottom boot operating voltage range 18 v cc = 1.70v?1.95v v cc q = 1.70v?2.24v 30 v cc = 1.70v?1.95v v cc q = 2.20v?3.30v ce select/special mark e = dual ce flash with burst cellularram memory production status blank = production es = engineering samples qs = qualification samples mt 28c 1285 64 w18 e fw -f70 5 -p85 6 bb wt es flash manufacturer's identification code none = micron (2ch) k = intel (89h) cellularram access time p70 = 70ns p85 = 85ns cellularram burst frequency 6 = 66 mhz
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 9 ?2003 micron technology. inc. table 1: ball descriptions 77-ball fbga numbers symbol ty p e descriptions f1, e1, d1, c1, a1, b1, e2, d2, e6, c7, d7, a8, b8, c8, e7, d8, e8, c2, a2, a3, d6, a7 a0?a21 input addresses: flash: a0?a21 (128mb). cellularram: a0?a21 (64mb). cellularram: a0?a20 (32mb). j1 f_ce1# input flash chip enable #1. f8 f_ce2# input flash chip enable #2. h2 f_oe1# input flash output enable #1. g8 f_oe2# input flash output enable #2. e5 f_we# input flash write enable. d4 f_wp# input flash write protect. e4 f_rst# input flash reset. b2 c_lb# input cellularram lower byte control. e3 c_ub# input cellularram upper byte control. c5 c_we# input cellularram write enable. g1 c_oe# input cellularram output enable. c6 c_ce# input cellularram chip enable. j8 c_cre input cellularram deep sleep mode and configuration mode. d5 adv# input address valid (burst operation only). b6 clk input clock (burst operation only). g2, g3, f3, g4, h5, f5, h6, g7, f2, h3, f4, h4, g5, f6, g6, h7 dq0?dq15 i/o flash/cellularram data input/output. f7 wait# output wait#. see ?wait ball operation? on page 10. k7 f_v ss supply flash core ground. c4 f_v pp supply flash v pp . a5, a6, j6, k4 f_v cc supply flash core power supply. a4, b4, k1, k5, k8 c_v ss supply cellularram core ground. j5 c_v cc supply cellularram core power supply. h8, j7, k3 v cc q supply flash/cellularram i/o supply. k2, k6 v ss q supply flash/cellularram i/o ground. b5, h1, j2, j3, j4 nc ? no connect. not internally connected to the die. b7 rfu ? reserved for future use (a22). b3, c3, d3 ? ? ball not mounted. reserved for future use (a23, a24, a25).
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 10 ?2003 micron technology. inc. boot configurations the possible configurations for flash die are shown in table 2 below. this table shows the possible config- urations of the two flash de vices for either top boot or bottom boot: f_ce1# and f_ce2# indicate to which flash die the configuration is referred. multichip packaging considerations multichip packaging presents unique chal- lenges when controlling complex memory devices. the mt28c128532w18/w30e and mt28c128564w18/w30e devices combine two micron flash devices with a single cellularram device. unique ids, stat e machines, and registers each flash device has a separate command state machine (csm) and status register (sr) and read con- figuration register (rcr). the read configuration regis- ter (rcr) settings are separate and can be different for the upper and lower device. each flash device has its own otp, cfi, and device code. depending on the boot configuration of each flash device, the otp, cfi, and device code information may differ. both flash devices will share the same manid, either micron (0x2ch) or intel (0x89h), which is defined by the part number. the cellularram memory has a refresh configura- tion register (rcr) that defines how the device per- forms self refresh, and a bus configuration register (bcr) to define the interface configuration. command codes all flash command codes are independent within each device. care must be taken when crossing the array boundary between the upper and lower flash and the cellularram memory to ensure that only one device is enabled at one time. in a two-cycle command sequence such as word program (0x40/data), it is required that both com- mands be issued to the same device. it is not recommended that simultaneous read, simultaneous write, or simultaneous erase opera- tions occur on both flash devices. read operation all read operations are limited to the address boundaries of each device. a new read operation must be started when crossing a device boundary. flash reset the reset control is shared by both flash die. bringing f_rst# control low will reset both the upper and lower device. wait ball operation it is important to note that the flash and cellular- ram devices share the wait ball functionality and must be configured correctly for proper burst mode operation. the flash and cellularram devices use dif- ferent registers to configure the wait polarity and have opposite default values. the wait ball polarity for the flash device is config- ured by programming bit 10 in the read configuration register (rcr). the default is active low. the wait ball polarity for the cellularram device is configured by programming bit 10 in the bus configu- ration register (bcr). the default is active high. both the flash and cellularram wait ball polarities must be set to the same active level for proper opera- tion. power consumption multiple chip packaging requires that power calculations consider the active operation of the upper and lower flash as well as that of the cellularram device. total power consumed will be the sum of the currents associated with the state of each device. table 2: possible boot configurations for flash die configuration f_ce2# f_ce1# order code top/top top top tt top/bottom top bottom tb bottom/top bottom top bt bottom/bottom bottom bottom bb
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 11 ?2003, micron technology, inc. note: 1. wait status is only valid for burst mode operation. wait should be ignored for all other operating modes. table 3: truth table modes flash signals shared signals cellularram signals memory output f_ce1# f_ce2# f_oe1# f_oe2# f_we# f_rst# adv# wait# c_ce# c_cre c_oe# c_ub/lb# c_we# memory bus control dq0? dq15 flash f_ce1# read l h l x h h l active 1 cellularram memory must be in high-z flash d out write l h h x l h x asserted flash d in standby hx x xxh xhigh-z cellularrammemory any mode allowable other high-z output disable lxhxhh x active 1 other high-z reset x x x x x l x high-z none high-z flash f_ce2# read h l x l h h l active 1 cellularram memory must be in high-z flash d out write h l x h l h x asserted flash d in standby xhx xxh xhigh-z cellularram memory any mode allowable other high-z output disable xlxhhh x active 1 other high-z reset x x x x x l x high-z none high-z cellularram memory read flash must be in high-z l active 1 lll l h cellular ram d out write l active 1 llh l l cellular ram d in standby flash any mode allowable x xhlxxxotherhigh-z output disable xxllhxhotherhigh-z deep sleep mode x xhhxxxotherhigh-z
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 12 ?2003 micron technology. inc. electrical specifications note: 1. stresses greater than those listed in table 5 may cause perm anent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. see technical note tn-00-15 for more information. table 4: absolute maximum ratings note 1 parameters/conditions min max units notes operating temperature range -25 +85 c storage temperature range -55 +125 c soldering cycle +260 c 2 table 5: recommended operating conditions parameter symbol min typ max units v cc supply voltage (f_v cc and c_v cc ) v cc 1.70 ? 1.95 v i/o supply voltage vccq (w18) 1.70 ? 2.24 v vccq (w30) 2.20 3.30 table 6: capacitance t a = +25 c; f = 1 mhz parameter/condition symbol ty p max units input capacitance c in 13 17 pf output capacitance c out 18 20 pf clock capacitance c clk 22 23 pf
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 13 ?2003 micron technology. inc. note: 1. c_cre ball high, cr4 bit in the cellularram refresh conf iguration register set to zero. measured at 25c, this standby current is the sum of the flash standby current and the cellularram deep-power down mode current. 2. i cces and i ccws values are valid when the device is deselected. any read operation performed while in suspend mode will have an additional current draw of suspend current. 3. automatic power save (aps) mode reduces i cc to approximately i ccs levels. 4. currents are measured using cellularram full array self-refresh. currents may be further reduced by using the tcr or par features. table 7: dc characteristics it is important to note that the specifications contained in this document supersede the specifications listed in the referenced individual flash and cellularram data sh eets. all currents are in rms unless otherwise noted. parameter symbol w18/w30 units notes typ max v cc standby current with 32mb cellularram device with 64mb cellularram device i ccs 140 150 a 4 v cc standby with cellularram device in deep power- down (dpd) mode with 32mb cellularram device with 64mb cellularram device i sbzz 60 60 a 1, 4 v cc program suspend current with 32mb cellularram device with 64mb cellularram device i ccws 140 150 a 2, 4 v cc erase suspend current with 32mb cellularram device with 64mb cellularram device i cces 140 150 a 2, 4 v cc automatic power save current with 32mb cellularram device with 64mb cellularram device i ccaps 140 150 a 3, 4 ta bl e 8 : cf i it is important to note that the specifications contained in this document supersede the specifications listed in the referenced individual flash and cellularram data sheets. offset data description 78 32mb: 0020 cellularram density 64mb: 0040
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice.. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 14 ?2003 micron technology, inc ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. cellularram is a trademark of micron technology, inc., inside the u.s. and a trademark of infineon technologies outside the u.s . all other trademarks are the property of their respective owners. figure 5: 77-ball fbga note: 1. all dimensions in millimeters. data sheet designation preliminary: this data sheet contains initial characterization limits that are subject to change upon full charac- terization of production devices. for additional documentation concerning flash and cell ularram features, functional descriptions, program- ming, and timing, please refer to the table below. ball a1 id 1.025 0.075 seating plane 0.10 c c 1.40 max ball a8 ball a1 id 0.80 typ 0.80 typ 2.80 0.05 5.60 ball a1 8.00 0.10 4.00 0.05 solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.35mm on a 0.30mm smd ball pad. 77x ? 0.35 solder ball material: eutectic 62% sn, 36% pb, 2% ag mold compound: epoxy novolac substrate: plastic laminate 7.20 3.60 0.05 5.00 0.05 10.00 0.10 c l c l table 9: references device part number link flash mt28f644w18/w30 www.micron.com/flash cellularram mt45w2mw16pfa and mt45w4mw16pfa www.micron.com/cellularram
128mb multibank burst flash 32mb/64mb burst cellularram combo preliminary 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18e_b.fm - rev. b, pub 11/03 en 15 ?2003 micron technology. inc. revision history rev b, preliminary ............................................................................................................. ............................................11/03 original document, rev. a, preview............................................................................................. ..................................8/03

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