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| products and specifications discussed herein ar e subject to change by micron without notice. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii features pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d1.fm - rev d 3/08 en 1 ?2004 micron technology, inc. all rights reserved. cio rldram ? ii mt49h64m9 ? 64 meg x 9 x 8 banks mt49h32m18 ? 32 meg x 18 x 8 banks mt49h16m36 ? 16 meg x 36 x 8 banks features ? 533 mhz ddr operation (1.067 gb/s/pin data rate) ? 38.4 gb/s peak bandwidth (x36 at 533 mhz clock frequency) ? organization ? 64 meg x 9, 32 meg x 18, and 16 meg x 36 i/o ? 8 banks ? reduced cycle time (15ns at 533 mhz) ? nonmultiplexed addresses (address multiplexing option available) ? sram-type interface ? programmable read latency (rl), row cycle time, and burst sequence length ? balanced read and write latencies in order to optimize data bus utilization ? data mask for write commands ? differential input clocks (ck, ck#) ? differential input data clocks (dk x , dk x #) ? on-die dll generates ck edge-aligned data and output data clock signals ? data valid signal (qvld) ? 32ms refresh (16k refresh for each bank; 128k refresh command must be issued in total each 32ms) ? 144-ball fbga package ? hstl i/o (1.5v or 1.8v nominal) ? 25?60 matched impedance outputs ? 2.5v v ext , 1.8v v dd , 1.5v or 1.8v v dd q i/o ? on-die termination (odt) r tt figure 1: 144-ball fbga notes: 1. contact micron for availability of industrial temperature products. 2. contact micron for availability of pb-free products. options marking ? clock cycle timing ? 1.875ns @ t rc = 15ns -18 ? 2.5ns @ t rc = 15ns -25e ? 2.5ns @ t rc = 20ns -25 ? 3.3ns @ t rc = 20ns -33 ? configuration ? 64 meg x 9 64m9 ? 32 meg x 18 32m18 ? 16 meg x 36 16m36 ? operating temperature ? commercial (0 to +95c) none ? industrial (t c = ?40c to +95c; t a = ?40c to +85c) it 1 ?package ? 144-ball fbga hu ? 144-ball fbga (pb-free) ht 2
pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d1.fm - rev d 3/08 en 2 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii features figure 2: 576mb rldram ii cio part numbers bga part marking decoder due to space limitations, bga-packaged components have an abbreviated part marking that is different from the part number. micron?s bga part marking decoder is available on micron?s web site at micron.com . package 144- b all fbga 144- b all fbga (p b -free) hu ht example part number: mt49h16m36hu-25 t c k = 1.875ns t c k = 2.5ns t c k = 2.5ns t c k = 3.3ns speed grade -18 -25e -25 -33 - c onfi g uration mt49h pa c ka g e s pee d temp i/o temperature c ommer c ial in d ustrial none it configuration 6 4 me g x 9 32 me g x 18 1 6 me g x 3 6 6 4m9 32m18 1 6 m3 6 i/o c ommon s eparate none c pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ciotoc.fm - rev d 3/08 en 3 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii table of contents table of contents bga part marking decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ball assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 electrical specifications ? i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 electrical specifications ? ac and dc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 ac and dc operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 input slew rate derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 temperature and thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 auto refresh (aref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 on-die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 ieee 1149.1 serial boundary scan (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 disabling the jtag feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 test access port (tap). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 tap controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 performing a tap reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 tap registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 tap instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ciolof.fm - rev d 3/08 en 4 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii list of figures list of figures figure 1: 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: 576mb rldram ii cio part number s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 3: simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 7: 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8: clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 9: nominal tas/tcs/tds and tah/tch/td h slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 10: example temperature test point location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 12: read burst lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 13: on-die termination-equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 14: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 15: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 16: auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 17: power-up/initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 18: power-up/initialization flow ch art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 19: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 20: consecutive write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 24: basic read burst timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 25: consecutive read bursts (bl = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 26: consecutive read bursts (bl = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 27: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 28: read data valid window for x9 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 29: read data valid window for x18 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 30: read data valid window for x36 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 31: auto refresh cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 32: read burst with odt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 33: read-nop-read with odt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 35: command description in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 37: mode register definition in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 38: burst refresh operation with mu ltiplexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 39: consecutive write bursts with mu ltiplexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 43: tap controller state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 44: tap controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 45: jtag operation ? loading instruct ion code and shifting out data . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 46: tap timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ciolot.fm -rev d 3/08 en 5 ?2004 micron technology, inc. all rights reserved. 576mb:x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii lisf of tables lisf of tables table 1: 64 meg x 9 ball assignments (top view) 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 2: 32 meg x 18 ball assignments (top view) 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 3: 16 meg x 36 ball assignments (top view) 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 4: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 5: i dd operating conditions and maximum limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 6: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 8: input ac logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 9: differential input clock operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 10: address and command setup and hold derating values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 11: data setup and hold derating values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 12: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 13: ac electrical characte ristics: -18, -25e, -25, -33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 14: temperature limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 15: thermal impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 16: description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 17: command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 18: cycle time and read/write latency configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 19: address widths at different burst lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 20: on-die termination dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 21: 576mb address mapping in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 22: cycle time and read/write late ncy configuration table in multiplexed mode . . . . . . . . . . . . . .61 table 23: tap input ac logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 24: tap ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 25: tap dc electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 26: identification register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 27: scan register sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 28: instruction codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 29: boundary scan (exit) order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 6 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii general description general description the micron ? reduced latency dram (rldram ? ) ii is a high-speed memory device designed for high bandwidth data stor age?telecommunications, networking, and cache applications, etc. the chip?s 8-bank architecture is optimized for sustainable high speed operation. the ddr i/o interface transfers two data words per clock cycle at the i/o balls. output data is referenced to the fr ee-running output data clock. commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is r egistered at both positive and negative edges of the input data clock(s). read and write accesses to the rldram are burst-oriented. the bu rst length (bl) is programmable from 2, 4, or 8 by setting the mode register. the device is supplied with 2.5v and 1.8v for the core and 1.5v or 1.8v for the output drivers. bank-scheduled refresh is supported with the row address generated internally. the fbga 144-ball package is used to enable ultra high-speed data transfer rates and a simple upgrade path from early generation devices. pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 7 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii state diagram state diagram figure 3: simplified state diagram initialization sequen c e d s el/nop read write mr s aref automati c sequen c e c omman d sequen c e pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d en 8 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii functional block diagrams functional block diagrams figure 4: 64 meg x 9 functional block diagram notes: 1. example for bl = 2; colu mn address will be reduced with an increase in burst length. 2. 16 = (length of burst) x 2^(number of colu mn addresses to write fifo and read logic). 14 we# ck# cs# ref# ck 8 a0?a21 1 ba0?ba2 zq 25 32 i/o gating dqm mask logic column decoder bank 0 memory array (16,384 x 32 x 16 x 9) 2 16,384 bank control logic bank 1 bank 0 bank 2 bank 3 bank 4 bank 6 bank 5 bank 7 14 8 1 3 8 8 refresh counter 14 18 mode register control logic command decode row- address mux address register column- address counter/ latch 8 1 288 read logic write fifo and drivers clk in 288 288 n n 9 9 9 9 dq latch qk/qk# generator drivers dll ck/ck# rcvrs input logic (0 ....8) v tt r tt odt control odt control v tt r tt odt control qk0/qk0# qvld dk/dk# dm output drivers zq cal zq cal 5 3 1 3 1 sense amplifiers sense amplifiers 16,384 n n 9 9 bank 0 row- address latch and decoder dq0?dq8 2 pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d en 9 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii functional block diagrams figure 5: 32 meg x 18 functional block diagram notes: 1. example for bl = 2; colu mn address will be reduced with an increase in burst length. 2. 8 = (length of burst) x 2^(number of colu mn addresses to write fifo and read logic). 14 we# ck# cs# ref# ck 8 a0?a20 1 ba0?ba2 zq 24 32 i/o gating dqm mask logic column decoder bank 0 memory array (16,384 x 32 x 8 x 18) 2 16,384 bank control logic bank 1 bank 0 bank 2 bank 3 bank 4 bank 6 bank 5 bank 7 14 7 1 3 8 8 refresh counter 14 18 mode register control logic command decode row- address mux address register column- address counter/ latch 7 1 288 read logic write fifo and drivers clk in 288 288 n n 18 18 18 4 2 18 dq latch qk/qk# generator drivers dll ck/ck# rcvrs input logic (0 ....17) v tt r tt odt control odt control v tt r tt odt control dq0?dq17 qk0?qk1/qk0#?qk1# qvld dk/dk# dm output drivers zq cal zq cal 5 2 1 2 1 sense amplifiers sense amplifiers 16,384 18 18 bank 0 row- address latch and decoder pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d en 10 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii functional block diagrams figure 6: 16 meg x 36 functional block diagram notes: 1. example for bl = 2; colu mn address will be reduced with an increase in burst length. 2. 4 = (length of burst) x 2^(number of colu mn addresses to write fifo and read logic). 14 we# ck# cs# ref# ck 8 a0?a19 1 ba0?ba2 zq 24 32 i/o gating dqm mask logic column decoder bank 0 memory array (16,384 x 32 x 4 x 36) 2 16,384 bank control logic bank 1 bank 0 bank 2 bank 3 bank 4 bank 6 bank 5 bank 7 14 6 1 3 8 8 refresh counter 14 18 mode register control logic command decode row- address mux address register column- address counter/ latch 6 1 288 read logic write fifo and drivers clk in 288 288 n n 36 36 36 4 4 36 dq latch qk/qk# generator drivers dll ck/ck# rcvrs input logic (0 ....35) v tt r tt odt control odt control v tt r tt odt control dq0?dq35 qk0?qk1/qk0#?qk1# qvld dk0?dk1/dk0#?dk1# dm output drivers zq cal zq cal 5 1 1 1 1 sense amplifiers sense amplifiers 16,384 36 36 bank 0 row- address latch and decoder pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 11 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ball assignments and descriptions ball assignments and descriptions notes: 1. reserved for future use. this signal is not connected. 2. no function. this signal is internally connec ted and has parasitic char acteristics of a clock input signal. this may opti onally be connected to g nd. 3. do not use. this signal is inte rnally connected and ha s parasitic characterist ics of an i/o. this may optionally be connected to g nd. note that if odt is enabled, these pins will be con- nected to v tt . table 1: 64 meg x 9 ball assignments (top view) 144-ball fbga 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd dnu 3 dnu 3 v ss qv ss q dq0 dnu 3 v dd c v tt dnu 3 dnu 3 v dd qv dd q dq1 dnu 3 v tt d a22 1 dnu 3 dnu 3 v ss qv ss q qk0# qk0 v ss e a21 dnu 3 dnu 3 v dd qv dd q dq2 dnu 3 a20 f a5 dnu 3 dnu 3 v ss qv ss q dq3 dnu 3 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h b2 a9 v ss v ss v ss v ss a4 a3 j nf 2 nf 2 v dd v dd v dd v dd b0 ck k dk dk# v dd v dd v dd v dd b1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 dnu 3 dnu 3 v ss qv ss q dq4 dnu 3 a19 p a15 dnu 3 dnu 3 v dd qv dd q dq5 dnu 3 dm r v ss dnu 3 dnu 3 v ss qv ss q dq6 dnu 3 v ss t v tt dnu 3 dnu 3 v dd qv dd q dq7 dnu 3 v tt u v dd dnu 3 dnu 3 v ss qv ss q dq8 dnu 3 v dd v v ref zq v ext v ss v ss v ext tdo tdi pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 12 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ball assignments and descriptions notes: 1. reserved for future use. th is may optionally be connected to g nd. 2. reserved for future use. this signal is inte rnally connected and has parasitic characteristics of an address input signal. this may optionally be connected to g nd. 3. no function. this signal is internally connec ted and has parasitic char acteristics of a clock input signal. this may opti onally be connected to g nd. 4. do not use. this signal is internally connecte d and has parasitic characteristics of a i/o. this may optionally be connected to g nd. note that if odt is enabled, these pins will be con- nected to v tt . table 2: 32 meg x 18 ball assignments (top view) 144-ball fbga 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd dnu 4 dq4 v ss qv ss q dq0 dnu 4 v dd c v tt dnu 4 dq5 v dd qv dd q dq1 dnu 4 v tt d a22 1 dnu 4 dq6 v ss qv ss q qk0# qk0 v ss e a21 2 dnu 4 dq7 v dd qv dd q dq2 dnu 4 a20 f a5 dnu 4 dq8 v ss qv ss q dq3 dnu 4 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h b2 a9 v ss v ss v ss v ss a4 a3 j nf 3 nf 3 v dd v dd v dd v dd b0 ck k dk dk# v dd v dd v dd v dd b1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 dnu 4 dq14 v ss qv ss q dq9 dnu 4 a19 p a15 dnu 4 dq15 v dd qv dd q dq10 dnu 4 dm r v ss qk1 qk1# v ss qv ss q dq11 dnu 4 v ss t v tt dnu 4 dq16 v dd qv dd q dq12 dnu 4 v tt u v dd dnu 4 dq17 v ss qv ss q dq13 dnu 4 v dd v v ref zq v ext v ss v ss v ext tdo tdi pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 13 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ball assignments and descriptions notes: 1. reserved for future use. th is may optionally be connected to g nd. 2. reserved for future use. this signal is inte rnally connected and has parasitic characteristics of an address input signal. this may optionally be connected to g nd. table 3: 16 meg x 36 ball assignments (top view) 144-ball fbga 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd dq8 dq9 v ss qv ss q dq1 dq0 v dd c v tt dq10 dq11 v dd qv dd q dq3 dq2 v tt d a22 1 dq12 dq13 v ss qv ss q qk0# qk0 v ss e a21 2 dq14 dq15 v dd qv dd q dq5 dq4 a20 2 f a5 dq16 dq17 v ss qv ss q dq7 dq6 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h b2 a9 v ss v ss v ss v ss a4 a3 j dk0 dk0# v dd v dd v dd v dd b0 ck k dk1 dk1# v dd v dd v dd v dd b1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 dq24 dq25 v ss qv ss q dq35 dq34 a19 p a15 dq22 dq23 v dd qv dd q dq33 dq32 dm r v ss qk1 qk1# v ss qv ss q dq31 dq30 v ss t v tt dq20 dq21 v dd qv dd q dq29 dq28 v tt u v dd dq18 dq19 v ss qv ss q dq27 dq26 v dd v v ref zq v ext v ss v ss v ext tdo tdi pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 14 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ball assignments and descriptions table 4: ball descriptions symbol type description a0?a21 input address inputs: a0?a21 define the row and column ad dresses for read and write operations. during a mode re g ister set, the address inputs define th e register settings. they are sampled at the rising edge of ck. ba0?ba2 input bank address inputs: select to which internal bank a command is being applied. ck, ck# input input clock: ck and ck# are differential input clocks . addresses and commands are latched on the rising edge of ck. ck# is ideall y 180 degrees out of phase with ck. cs# input chip select: cs# enables the command decoder when low and disables it when hi g h. when the command decoder is disabled, new commands are ignored, but internal operations continue. dq0?dq35 input data input: the dq signals form the 36-bit data bu s. during read commands, the data is referenced to both edges of qk x . during write commands, the data is sampled at both edges of dk. dk, dk# input input data clock: dk and dk# are the differential input da ta clocks. all input data is referenced to both edges of dk. dk# is id eally 180 degrees out of phase with dk. for the x36 device, dq0? dq17 are referenced to dk0 and dk0# and dq18 ?dq35 are referenced to dk1 and dk1#. for the x9 and x18 devices, all dqs are re ferenced to dk and dk#. all dk x and dk x # pins must always be supplied to the device. dm input input data mask: the dm signal is the input mask signal for write data. input data is masked when dm is sampled hi g h. dm is sampled on both edges of dk (dk1 for the x36 configuration). tie signal to ground if not used. tck input ieee 1149.1 clock input: this ball must be tied to v ss if the jta g function is not used. tms, tdi input ieee 1149.1 test inputs: these balls may be left as no connects if the jta g function is not used. we#, ref# input command inputs: sampled at the positive edge of ck, we# and ref# define (together with cs#) the command to be executed. v ref input input reference voltage: nominally v dd q/2. provides a reference voltage for the input buffers. zq i/o external impedance (25?60 ): this signal is used to tune the device outp uts to the system data bus impedance. dq output impedance is set to 0.2 rq, where rq is a resistor from this signal to ground. connecting zq to g nd invokes the minimum impedanc e mode. connecting zq to v dd invokes the maximum impedance mode. refer to fi gure 11 on page 32 to activate this function. qk x , qk x # output output data clocks: qk x and qk x # are opposite polarity, outpu t data clocks. they are free- running, and during reads, are edge-aligned with data output from the rldram. qk x # is ideally 180 degrees out of phase with qk x . for the x36 device, qk0 and qk0# are aligned with dq0?dq17, and qk1 and qk1# are aligned with dq18?dq35. for the x18 device, qk0 and qk0# are aligned with dq0?dq8, while qk1 and qk1# ar e aligned with q9?q17. for the x9 device, all dqs are aligned with qk0 and qk0#. qvld output data valid: the qvld pin indicates valid output data. qvld is edge-aligned with qk x and qk x #. tdo output ieee 1149.1 test output: jta g output. this ball may be left as no connect if the jta g function is not used. v dd supply power supply: nominally, 1.8v. see table 7 on page 18 for range. v dd q supply dq power supply: nominally, 1.5v or 1.8v. isolated on the device for improved noise immunity. see table 7 on page 18 for range. v ext supply power supply: nominally, 2.5v. see table 7 on page 18 for range. v ss supply g round. v ss q supply dq ground: isolated on the device for improved noise immunity. v tt supply power supply: isolated termination supply. nominally, v dd q/2. see table 7 on page 18 for range. a22 ? reserved for future use: this signal is not connected and may be connected to ground. dnu ? do not use: these balls may be connected to ground. note that if odt is enable d, these pins will be connected to v tt . nf ? no function: these balls can be connected to ground. pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 15 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii package dimensions package dimensions figure 7: 144-ball fbga notes: 1. all dimensions are in millimeters. ball a1 id s ol d er b all material: 6 2% s n, 3 6 % p b , 2% a g or 9 6 .5% s n, 3% a g , 0.5% c u mol dc ompoun d : epoxy novola c s u b strate material: plasti c laminate ball a1 ball a1 id c l c l 0.12 a a 0.75 0.05 144x ? 0.55 ball a12 17.00 8.50 9.25 0.05 18.50 0.10 1.00 typ 0.80 typ 8.80 4.40 5.50 0.05 11.00 0.10 1.20 max s eatin g plane dimensions apply to sol d er b alls post- reflow. the pre- reflow d iameter is ?0.5 on a ?0.4 n s md b all pa d . pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 16 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? i dd electrical specifications ? i dd ta bl e 5 : i dd operating conditions and maximum limits description condition symbol -18 -25e -25 -33 units standby current t ck = idle; all banks idle; no inputs toggling i sb 1 (v dd ) x9/x18 55 53 48 48 ma i sb 1 (v dd ) x36 55 53 48 48 i sb 1 (v ext ) 5555 active standby current cs# = 1; no commands; bank address incremented and half address/data change once every four clock cycles i sb 2 (v dd ) x9/x18 365 293 288 233 ma i sb 2 (v dd ) x36 365 293 288 233 i sb 2 (v ext ) 5555 operational current bl = 2; se q uential bank access; bank transitions once every t rc; half address transitions once every t rc; read followed by write se q uence; continuous data during write commands i dd 1 (v dd ) x9/x18 465 380 348 305 ma i dd 1 (v dd ) x36 485 400 374 343 i dd 1 (v ext )15151513 operational current bl = 4; se q uential bank access; bank transitions once every t rc; half address transitions once every t rc; read followed by write se q uence; continuous data during write commands i dd 2 (v dd ) x9/x18 475 400 362 319 ma i dd 2 (v dd ) x36 510 425 418 389 i dd 2 (v ext )15151513 operational current bl = 8; se q uential bank access; bank transitions once every t rc; half address transitions once every t rc; read followed by write se q uence; continuous data during write commands i dd 3 (v dd ) x9/x18 505 430 408 368 ma i dd 3 (v dd ) x36 625 540 460 425 i dd 3 (v ext )20202018 burst refresh current eight bank cyclic refresh; continuous address/ data; command bus remains in refresh for all eight banks i ref 1 (v dd ) x9/x18 995 790 785 615 ma i ref 1 (v dd ) x36 995 915 785 615 i ref 1 (v ext )80808070 distributed refresh current single bank refresh; se q uential bank access; half address transitions once every t rc; continuous data i ref 2 (v dd ) x9/x18 425 330 325 267 ma i ref 2 (v dd ) x36 425 390 326 281 i ref 2 (v ext )20202018 operating burst write current example bl = 2; cyclic bank access; half of address bits change every clock cycl e; continuous data; measurement is taken during continuous write i dd 2w (v dd ) x 9/ x 18 1335 980 970 819 ma i dd 2w (v dd ) x 36 1545 1,105 1,100 914 i dd 2w (v ext )50505040 operating burst write current example bl = 4; cyclic bank access; half of address bits change every two clock cycles; continuous data; measurement is taken during continuous write i dd 4w (v dd ) x 9/ x 18 985 785 779 609 ma i dd 4w (v dd ) x 36 1185 887 882 790 i dd 4w (v ext )30303025 operating burst write current example bl = 8; cyclic bank access; half of address bits change every four clock cycles; continuous data; measurement is taken during continuous write i dd 8w (v dd ) x 9/ x 18 770 675 668 525 ma i dd 8w (v dd ) x 36 1095 755 750 580 i dd 8w (v ext )30303025 operating burst read current example bl = 2; cyclic bank access; half of address bits change every clock cycl e; continuous data; measurement is taken during continuous read i dd 2r (v dd ) x9/x18 1225 940 935 735 ma i dd 2r (v dd ) x36 1270 995 990 795 i dd 2r (v ext )50505040 operating burst read current example bl = 4; cyclic bank access; half of address bits change every two clock cycles; continuous data; measurement is taken during continuous read i dd 4r (v dd ) x9/x18 860 685 680 525 ma i dd 4r (v dd ) x36 920 735 730 660 i dd 4r (v ext )30303025 operating burst read current example bl = 8; cyclic bank access; half of address bits change every four clock cycles; continuous data; measurement is taken during continuous read i dd 8r (v dd ) x9/x18 655 575 570 450 ma i dd 8r (v dd ) x36 855 665 660 505 i dd 8r (v ext )30303025 pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 17 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? i dd notes: 1. i dd specifications are tested after the de vice is properly initialized. +0c t c +95c; +1.7v v dd +1.9v, +2.38v v ext +2.63v, +1.4v v dd q v dd , v ref = v dd q/2. 2. t ck = t dk = min, t rc = min. 3. input slew rate is spec ified in table 8 on page 19. 4. definitions for i dd conditions: 4a. low is defined as v in v il ( ac ) max. 4b. hi g h is defined as v in v ih ( ac ) min. 4c. stable is defined as inputs remaining at a hi g h or low level. 4d. floating is defined as inputs at v ref = v dd q/2. 4e. continuous data is defined as half the dq signals changing between hi g h and low every half clock cycle (twice per clock). 4f. continuous address is defined as half the address signals changing between hi g h and low every clock cycle (once per clock). 4g. se q uential bank access is de fined as the bank address incrementing by one every t rc. 4h. cyclic bank access is defined as the bank address incrementing by one for each com- mand access. for bl = 2 this is every clock, for bl = 4 this is every other clock, and for bl = 8 this is every fourth clock. 5. cs# is hi g h unless a read, write, aref, or mrs co mmand is registered. cs# never transi- tions more than once per clock cycle. 6. i dd parameters are specified with odt disabled. 7. tests for ac timing, i dd , and electrical ac and dc characte ristics may be conducted at nomi- nal reference/supply voltage leve ls, but the related specificati ons and device operations are tested for the full vo ltage range specified. 8. i dd tests may use a v il -to-v ih swing of up to 1.5v in the te st environment, bu t input timing is still referenced to v ref (or to the crossing po int for ck/ck#), and pa rameter specifications are tested for the specified ac input levels un der normal use conditio ns. the minimum slew rate for the input signals used to test the device is 2 v/ns in the range between v il ( ac ) and v ih ( ac ). pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 18 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc electrical specific ations ? ac and dc absolute maximum ratings stresses greater than those listed in table 6 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ac and dc operating conditions notes: 1. all voltages referenced to v ss ( g nd). 2. overshoot: v ih ( ac ) v dd + 0.7v for t t ck/2. undershoot: v il ( ac ) ?0.5v for t t ck/2. dur- ing normal operation, v dd q must not exceed v dd . control input signals may not have pulse widths less than t ck/2 or operate at fre q uencies exceeding t ck (max). 3. v dd q can be set to a nominal 1.5v 0.1v or 1.8v 0.1v supply. 4. typically the value of v ref is expected to be 0.5 x v dd q of the transmitting device. v ref is expected to track variations in v dd q. 5. peak-to-peak ac noise on v ref must not exceed 2 percent v ref ( dc ). 6. v ref is expected to e q ual v dd q/2 of the transmitting device and to track variations in the dc level of the same. peak-to-pe ak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd q/2, v ref is allowed 2 percent v dd q/2 for dc error and an additional 2 percent v dd q/2 for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. table 6: absolute maximum ratings parameter min max units i/o voltage ?0.3 v dd q + 0.3 v voltage on v ext supply relative to v ss ?0.3 +2.8 v voltage on v dd supply relative to v ss ?0.3 +2.1 v voltage on v dd q supply relative to v ss ?0.3 +2.1 v table 7: dc electrical characteristics and operating conditions note 1 applies to the entire table; unless otherwise noted: +0c t c +95c; +1.7v v dd +1.9v description conditions symbol min max units notes supply voltage ?v ext 2.38 2.63 v supply voltage ?v dd 1.7 1.9 v 2 isolated output buffer supply ?v dd q1.4 v dd v 2, 3 reference voltage ?v ref 0.49 v dd q 0.51 v dd qv 4, 5, 6 termination voltage ?v tt 0.95 v ref 1.05 v ref v7, 8 input high (logic 1) voltage ?v ih v ref + 0.1 v dd q + 0.3 v 2 input low (logic 0) voltage ?v il v ss q - 0.3 v ref - 0.1 v 2 output high current v oh = v dd q/2 i oh (v dd q/2)/ (1.15 rq/5) (v dd q/2)/ (0.85 rq/5) a 9, 10, 11 output low current v ol = v dd q/2 i ol (v dd q/2)/ (1.15 rq/5) (v dd q/2)/ (0.85 rq/5) a 9, 10, 11 clock input leakage current 0v v in v dd i lc ?5 5 a input leakage current 0v v in v dd i li ?5 5 a output leakage current 0v v in v dd qi lo ?5 5 a reference voltage current ?i ref ?5 5 a pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 19 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc 7. v tt is expected to be set e q ual to v ref and must track variations in the dc level of v ref . 8. on-die termination may be sele cted using mode regi ster bit 9 (see figure 11 on page 32). a resistance r tt from each data input si gnal to the nearest v tt can be enabled. r tt = 125?185 at 95c t c . 9. i oh and i ol are defined as absolute values and are measured at v dd q/2. i oh flows from the device, i ol flows into the device. 10. if mrs bit a8 is 0, use rq = 250 in the e q uation in lieu of presence of an external imped- ance matched resistor. 11. for v ol and v oh , refer to the rldram ii hspice or ibis driver models. notes: 1. all voltages referenced to v ss ( g nd). 2. the ac and dc input level specifications are as defined in the hstl standard (that is, the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [hi g h] level). 3. the minimum slew rate for the input signals used to test the device is 2 v/ns in the range between v il ( ac ) and v ih ( ac ). see illustration below: table 8: input ac logic levels notes 1?3 apply to en tire table; unless ot herwise noted: +0c t c +95c; +1.7v v dd +1.9v description symbol min max units input high (logic 1) voltage v ih v ref + 0.2 ? v input low (logic 0) voltage v il ?v ref - 0.2 v v ih ( ac ) min v il ( ac ) max rise time: 2 v/ns fall time: 2 v/ns v dd q g nd v swin g pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 20 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc notes: 1. dk x and dk x # have the same re q uirements as ck and ck#. 2. all voltages referenced to v ss ( g nd). 3. the ck/ck# input reference level (for timing re ferenced to ck/ck#) is the point at which ck and ck# cross. the input reference level for signals other than ck/ck# is v ref . 4. ck and ck# input slew rate must be 2 v/ns ( 4 v/ns if measured differentially). 5. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 6. the value of v ix is expected to e q ual v dd q/2 of the transmitting device and must track vari- ations in the dc level of the same. figure 8: clock input notes: 1. ck and ck# must cr oss within this region. 2. ck and ck# must meet at least v id ( dc ) min when static and centered around v dd q/2. 3. minimum peak-to-peak swing. 4. it is a violation to tristate ck and ck# after the part is initialized. table 9: differential input clock operating conditions notes 1?4 apply to the entire table; unless otherwise noted: +0c t c +95c; +1.7v v dd +1.9v parameter/condition symbol min max units notes clock input voltage level: ck and ck# v in ( dc )?0.3v dd q + 0.3 v clock input differential voltage: ck and ck# v id ( dc )0.2v dd q + 0.6 v 5 clock input differential voltage: ck and ck# v id ( ac )0.4v dd q + 0.6 v 5 clock input crossing point voltage: ck and ck# v ix ( ac )v dd q/2 - 0.15 v dd q/2 + 0.15 v 6 ck ck# v in ( dc ) max 1 maximum clock level minimum clock level v in ( dc ) min v dd q/2 v dd q/2 + 0.15 v dd q/2 - 0.15 x x x x v id ( ac ) 3 v id ( dc ) 2 v ix ( ac ) max v ix ( ac ) min pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 21 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc input slew rate derating table 10 on page 22 and table 11 on page 23 define the address, command, and data setup and hold derating values. thes e values are added to the default t as/ t cs/ t ds and t ah/ t ch/ t dh specifications when the slew rate of any of these input signals is less than the 2 v/ns the nominal setup and hold specifications are based upon. to determine the setup and hold time needed for a given slew rate, add the t as/ t cs default specification to the ? t as/ t cs v ref to ck/ck# crossing? and the t ah/ t ch default specification to the " t ah/ t ch ck/ck# crossing to v ref " derated values on table 10. the derated data setup and hold values can be determined in a like manner using the ? t ds v ref to ck/ck# crossing? and ? t dh to ck/ck# crossing to v ref ? values on table 11. the derating values on table 10 and table 11 apply to all speed grades. the setup times on table 10 and table 11 represen t a rising signal. in this case, the time from which the rising signal crosses v ih ( ac ) min to the ck/ck# cross point is static and must be maintained across all slew rates. the derated setup timing represents the point at which the rising signal crosses v ref ( dc ) to the ck/ck# cross point. this derated value is calculated by determining the time needed to maintain the given slew rate and the delta between v ih ( ac ) min and the ck/ck# cross point. the setup values in table 10 and table 11 are also valid for falling signals (with respect to v il [ ac ] max and the ck/ ck# cross point). the hold times in table 10 and table 11 represent falling signals. in this case, the time from the ck/ck# cross point to when the signal crosses v ih ( dc ) min is static and must be maintained across all slew rates. the derated hold timing represents the delta between the ck/ck# cross point to when the falling signal crosses v ref ( dc ). this derated value is calculated by determining the time needed to maintain the given slew rate and the delta between the ck/ck# cross point and v ih ( dc ). the hold values in table 10 and table 11 are also valid for rising signals (with respect to v il [ dc ] max and the ck and ck# cross point). note: the above descriptions also pertain to data setup and hold derating when ck/ck# are replaced with dk/dk#. pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 22 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc table 10: address and command set up and hold derating values command/ address slew rate (v/ns) t as/ t cs v ref to ck/ck# crossing t as/ t cs v ih ( ac ) min to ck/ck# crossing t ah/ t ch ck/ck# crossing to v ref t ah/ t ch ck/ck# crossing to v ih ( dc ) min units ck, ck# differential slew rate: 2.0 v/ns 2.0 0 ?100 0 ?50 ps 1.9 5 ?100 3 ?50 ps 1.8 11 ?100 6 ?50 ps 1.7 18 ?100 9 ?50 ps 1.625?10013 ?50ps 1.533?10017 ?50ps 1.443?10022 ?50ps 1.354?10027 ?50ps 1.267?10034 ?50ps 1.182?10041 ?50ps 1.0 100 ?100 50 ?50 ps ck, ck# differential slew rate: 1.5 v/ns 2.0 30 ?70 30 ?20 ps 1.9 35 ?70 33 ?20 ps 1.8 41 ?70 36 ?20 ps 1.7 48 ?70 39 ?20 ps 1.6 55 ?70 43 ?20 ps 1.5 63 ?70 47 ?20 ps 1.4 73 ?70 52 ?20 ps 1.3 84 ?70 57 ?20 ps 1.2 97 ?70 64 ?20 ps 1.1 112 ?70 71 ?20 ps 1.0 130 ?70 80 ?20 ps ck, ck# differential slew rate: 1.0 v/ns 2.0 60 ?40 60 10 ps 1.9 65 ?40 63 10 ps 1.8 71 ?40 66 10 ps 1.7 78 ?40 69 10 ps 1.6 85 ?40 73 10 ps 1.5 93 ?40 77 10 ps 1.4 103 ?40 82 10 ps 1.3 114 ?40 87 10 ps 1.2 127 ?40 94 10 ps 1.1 142 ?40 101 10 ps 1.0 160 ?40 110 10 ps pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 23 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc table 11: data setup and hold derating values data slew rate (v/ns) t ds v ref to ck/ck# crossing t ds v ih ( ac ) min to ck/ck# crossing t dh ck/ck# crossing to v ref t dh ck/ck# crossing to v ih ( dc ) min units dk, dk# differential slew rate: 2.0 v/ns 2.0 0 ?100 0 ?50 ps 1.9 5 ?100 3 ?50 ps 1.8 11 ?100 6 ?50 ps 1.7 18 ?100 9 ?50 ps 1.625?10013 ?50ps 1.533?10017 ?50ps 1.443?10022 ?50ps 1.354?10027 ?50ps 1.267?10034 ?50ps 1.182?10041 ?50ps 1.0 100 ?100 50 ?50 ps dk, dk# differential slew rate: 1.5 v/ns 2.0 30 ?70 30 ?20 ps 1.9 35 ?70 33 ?20 ps 1.8 41 ?70 36 ?20 ps 1.7 48 ?70 39 ?20 ps 1.6 55 ?70 43 ?20 ps 1.5 63 ?70 47 ?20 ps 1.4 73 ?70 52 ?20 ps 1.3 84 ?70 57 ?20 ps 1.2 97 ?70 64 ?20 ps 1.1 112 ?70 71 ?20 ps 1.0 130 ?70 80 ?20 ps dk, dk# differential slew rate: 1.0 v/ns 2.0 60 ?40 60 10 ps 1.9 65 ?40 63 10 ps 1.8 71 ?40 66 10 ps 1.7 78 ?40 69 10 ps 1.6 85 ?40 73 10 ps 1.5 93 ?40 77 10 ps 1.4 103 ?40 82 10 ps 1.3 114 ?40 87 10 ps 1.2 127 ?40 94 10 ps 1.1 142 ?40 101 10 ps 1.0 160 ?40 110 10 ps pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 24 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc figure 9: nominal t as/ t cs/ t ds and t ah/ t ch/ t dh slew rate notes: 1. capacitance is not tested on zq pin. 2. jta g pins are tested at 50 mhz. table 12: capacitance notes 1?2 apply to entire table description symbol conditions min max units address/control input capacitance c i t a = 25c; f = 100 mhz v dd = v dd q = 1.8v 1.5 2.5 pf input/output capacitance (dq, dm, and qk/qk#) c o 3.5 5.0 pf clock capacitance (ck/ck#, and dk/dk#) c ck 2.0 3.0 pf jta g pins c jta g 2.0 5.0 pf v swin g (max) v ref to ac region v ref to dc region v ref to dc region v ref to ac region v ref(dc) v il(dc) max v il(ac) max v ss q v ih(dc) min v ih(ac) min v dd q pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 25 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc table 13: ac electrical characteristics: -18, -25e, -25, -33 notes 1?4 (page 27) appl y to the entire table description symbol -18 -25e -25 -33 units notes min max min max min max min max clock input clock cycle time t ck 1.875 2.7 2.5 5.7 2.5 5.7 3.3 5.7 ns input data clock cycle time t dk t ck t ck t ck t ck ns clock jitter: period t jit per ?100 100 ?150 150 ?150 150 ?200 200 ps 5, 6 clock jitter: cycle-to- cycle t jit cc 200 300 300 400 ps clock hi g h time t ckh, t dkh 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low time t ckl, t dkl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock to input data clock t ckdk ?0.3 0.3 ?0.45 0.5 ?0.45 0.5 ?0.45 1.2 ns mode register set cycle time to any command t mrsc 6 ? 6 ? 6 ? 6 ? t ck setup times address/command and input setup time t as/ t cs 0.3 ? 0.4 ? 0.4 ? 0.5 ? ns data-in and data mask to dk setup time t ds 0.17 ? 0.25 ? 0.25 ? 0.3 ? ns hold times address/command and input hold time t ah/ t ch 0.3 ? 0.4 ? 0.4 ? 0.5 ? ns data-in and data mask to dk hold time t dh 0.17 ? 0.25 ? 0.25 ? 0.3 ? ns data and data strobe output data clock hi g h time t qkh 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ckh output data clock low time t qkl 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ckl half-clock period t qhp min ( t qkh, t qkl) ?min ( t qkh, t qkl) ?min ( t qkh, t qkl) ?min ( t qkh, t qkl) ? qk edge to clock edge skew t ckqk ?0.2 0.2 ?0.25 0.25 ?0.25 0.25 ?0.3 0.3 ns qk edge to output data edge t qkq0, t qkq1 ?0.12 0.12 ?0.2 0.2 ?0.2 0.2 ?0.25 0.25 ns 7 qk edge to any output data edge t qkq ?0.22 0.22 ?0.3 0.3 ?0.3 0.3 ?0.35 0.35 ns 8 qk edge to qvld t qkvld ?0.22 0.22 ?0.3 0.3 ?0.3 0.3 ?0.35 0.35 ns pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 26 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc data valid window t dvw t qhp - ( t qkq x [max] + | t qkq x [min]|) ? t qhp - ( t qkq x [max] + | t qkq x [min]|) ? t qhp - ( t qkq x [max] + | t qkq x [min]|) ? t qhp - ( t qkq x [max] + | t qkq x [min]|) ? refresh average periodic refresh interval t refi ? 0.24 ? 0.24 ? 0.24 ? 0.24 s 9 table 13: ac electrical characteristics: -18, -25e, -25, -33 (continued) notes 1?4 (page 27) appl y to the entire table description symbol -18 -25e -25 -33 units notes min max min max min max min max pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 27 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii electrical specifications ? ac and dc notes 1. all timing parameters are measured relative to the crossing point of ck/ck#, dk/dk# and to the crossing point with v ref of the command, address, and data signals. 2. outputs measured with equivalent load: 3. tests for ac timing, i dd , and electrical ac and dc ch aracteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified. 4. ac timing may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are tested for the specifie d ac input levels under normal use condi- tions. the minimum slew rate for the input sign als used to test the device is 2 v/ns in the range between v il ( ac ) and v ih ( ac ). 5. clock phase jitter is the variance from clock rising edge to the next expected clock ris- ing edge. 6. frequency drift is not allowed. 7. t qkq0 is referenced to dq0?dq17 for the x36 configuration and dq0?dq8 for the x18 configuration. t qkq1 is referenced to dq18?dq35 for the x36 configuration and dq9?dq17 for the x18 configuration. 8. t qkq takes into account the skew between any qk x and any q. 9. to improve efficiency, eight aref commands (one for each bank) can be posted to the rldram on consecutive cycles at periodic intervals of 1.95s. 10pf dq 50 v tt test point pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 28 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii temperature and thermal impedance temperature and thermal impedance it is imperative that the rldram device?s temperature specifications, shown in table 14, be maintained in order to ensure the juncti on temperature is in the proper operating range to meet data sheet specifications. an important step in maintaining the proper junction temperature is using the device?s thermal impedances correctly. the thermal impedances are listed fo r the packages available. incorrectly using thermal impedances can produce significant errors. read micron tech- nical note tn-00-08, ?thermal applications? prior to using the thermal impedances listed in table 14. for designs that are expect ed to last several years and require the flexi- bility to use several dram die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. the rldram device?s safe junction temperature range can be maintained when the t c specification is not exceeded. in applications where the device?s ambient temperature is too high, use of forced air and/or heat sinks may be required in order to satisfy the case temperature specifications. notes: 1. max storage case temperature; t st g is measured in the center of the package, as shown in figure 10 on page 29. this case temperature limi t is allowed to be exceeded briefly during package reflow, as noted in micron technical note tn-00-15 . 2. temperatures greater than 110c may cause permanent damage to the device. this is a stress rating only and functional operation of the device at or above this is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect reliability of the part. 3. junction temperature depends upon package type, cycle time, load ing, ambient tempera- ture, and airflow. 4. max operating case temperature; t c is measured in the center of the package, as shown in figure 10 on page 29. 5. device functionality is not guarant eed if the device exceeds maximum t c during operation. 6. both temperature specific ations must be satisfied. notes: thermal impedance data is based on a number of samples from multiple lots and should be viewed as a typical number. ta bl e 1 4 : te mp er a t ure l im it s parameter symbol min max units notes storage temperature t st g ?55 +150 c1 reliability junction temperature commercial t j ?+110 c2 industrial ?+110 c2 operating junction temperature commercial t j 0+100 c3 industrial ?40 +100 c3 operating case temperature commercial t c 0+95 c4, 5 industrial ?40 +95 c4, 5, 6 table 15: thermal impedance package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) fb g a 2-layer 43.8 31.2 26.9 16.7 2.2 4-layer 31.3 24.3 21.9 16.5 pdf: 09005aef80fe62fb/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio_d2.fm - rev d 3/08 en 29 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii temperature and thermal impedance figure 10: example temperature test point location 11.00 5.50 18.50 9.25 test point pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 30 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands commands the following table provides descriptions of the valid commands of the rldram. all input states or sequences not shown are illegal or reserved. all command and address inputs must meet setup and hold times around the rising edge of ck. notes: 1. when the chip is deselected, internal nop commands are generated and no commands are accepted. 2. n = 21. notes: 1. x = ?don?t care;? h = logic hi g h; l = logic low; a = valid addr ess; ba = valid bank address. 2. n = 21. 3. only a0?a17 are used for the mrs command. 4. address width varies with burst leng th; see table 19 on page 34 for details. table 16: description of commands command description notes dsel/nop the nop command is used to perform a no operation to the rldram, which essentially deselects the chip. use the nop command to prevent unwanted commands from being registered during idle or wait states. operations already in pr ogress are not affected. output values depend on command history. 1 mrs the mode register is set via the address inpu ts a0?a17. see figure 11 on page 32 for further information. the mrs command can only be issu ed when all banks are idle and no bursts are in progress. read the read command is used to initiate a bur st read access to a bank. the value on the ba0? ba2 inputs selects the bank, and the address provided on inputs a0?a n selects the data location within the bank. 2 write the write command is used to initiate a bu rst write access to a bank. the value on the ba0? ba2 inputs selects the bank, and the address provided on inputs a0?a n selects the data location within the bank. input data appearin g on the dq is written to the memory array subject to the dm input logic level appearing co incident with the data. if the dm signal is registered low, the corresponding data will be written to memory. if the dm signal is registered hi g h, the corresponding data inputs will be ignored (that is, this part of the data word will not be written). 2 aref the aref command is used during normal op eration of the rldram to refresh the memory content of a bank. the command is nonpersistent, so it must be issued each time a refresh is re q uired. the value on the ba 0?ba2 inputs selects the bank. the refresh address is generated by an internal refr esh controller, effectively making each address bit a ?don?t care? during the aref command. see ?auto re fresh (aref)? on page 39 for more details. ta bl e 1 7 : com ma nd tab le notes 1?2 apply to the entire table operation code cs# we# ref# a0?a n 2 ba0?ba2 notes device deselect/no operation dsel/nop h x x x x mrs mrslllopcodex 3 read read l h h a ba 4 write write l l h a ba 4 auto refresh aref l h l x ba pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 31 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands mode register set (mrs) the mode register set stores the data for co ntrolling the operating modes of the memory. it programs the rldram configuration, bu rst length, test mode, and i/o options. during an mrs command, the address inputs a0?a17 are sampled and stored in the mode register. after issuing a valid mrs command, t mrsc must be met before any command can be issued to the rldram. this statement does not apply to the consecu- tive mrs commands needed for internal logic reset during the initialization routine. the mrs command can only be issued when all bank s are idle and no bursts are in progress. note: the data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed. don ? t c are c k c k# cs # we# ref# op c ode addre ss bank addre ss pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 32 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands figure 11: mode register definition in nonmultiplexed address mode notes: 1. a10?a17 must be set to zero; a18?a n = ?don?t care.? 2. a6 not used in mrs. 3. bl = 8 is not available. 4. dll reset turns the dll off. 5. available in 576mb part only. 6. 30 percent temperature variation. config bl am reserved 1 a9 a10 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (m x ) address bus 97 6 543 82 1 0 a17 17?10 configuration 1 3 (default) 1 3 2 3 4 3,5 5 5 reserved reserved m0 0 1 0 1 0 1 0 1 m 1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m5 0 1 a dd ress mux nonmultiplexed (default) multiplexed m8 0 1 drive impe d an c e internal 50 6 (default) external (zq) m9 0 1 on-die termination off (default) on dll na 2 odt m3 0 1 0 1 burst length 2 (default) 4 8 reserved m4 0 0 1 1 im . . . m7 0 1 dll reset dll reset 4 (default) dll enabled pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 33 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands configuration tables table 18 shows the different configurations that can be programmed into the mode register. the write latency is equal to the re ad latency plus one in each configuration in order to maximize data bus utilization. bits m0, m1, and m2 are used to select the configuration during the mrs command. notes: 1. t rc < 20ns in any configuration only ava ilable with -25e and -18 speed grades. 2. minimum op erating fre q uency for -18 is 370 mhz. 3. bl = 8 is not available. 4. the minimum t rc is typically 3 cycles, ex cept in the case of a wri te followed by a read to the same bank. in this instance the minimum t rc is 4 cycles. burst length (bl) burst length is defined by m3 and m4 of the mode register. read and write accesses to the rldram are burst-oriented, with the burst length being programmable to 2, 4, or 8. figure 12 on page 34 illustrates the different burst lengths with respect to a read command. changes in the burst length affect the width of the address bus (see table 19 on page 34 for details). note: the data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed. table 18: cycle time and read/wri te latency configuration table notes 1?2 apply to the entire table parameter configuration units 1 3 2 3 4 3, 4 5 t rc 46835 t ck t rl 46835 t ck t wl 57946 t ck valid fre q uency range 266?175 400?175 533?175 200?175 333?175 mhz pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 34 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands figure 12: read burst lengths notes: 1. do a n = data-out from bank a and address an . 2. subse q uent elements of data-out appear after do n . 3. shown with nominal t ckqk. address multiplexing although the rldram has the ability to oper ate with an sram interface by accepting the entire address in one clock, an option in the mode register can be set so that it func- tions with multiplexed addresses, similar to a traditional dram. in multiplexed address mode, the address can be provided to the rldr am in two parts that are latched into the memory with two consecutive rising clock ed ges. this provides the advantage of only needing a maximum of 11 address balls to control the rldram, reducing the number of table 19: address widths at different burst lengths burst length x9 x18 x36 2 a0?a21 a0?a20 a0?a19 4 a0?a20 a0?a19 a0?a18 8 a0?a19 a0?a18 a0?a17 c ommand addre ss dq qvld do an qk qk# qk qk# qk qk# rl = 4 c k c k# dq do an don ? t c are tran s itioning data dq do an read nop nop nop nop nop nop nop bank a , c ol n t0 t1 t2 t3 t4n t5n t4 t5 t 6 n t7n t 6 t7 qvld qvld bl = 2 bl = 4 bl = 8 nop pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 35 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands signals on the controller side. the data bus e fficiency in continuous burst mode is only affected when using the bl = 2 setting since the device requires two clocks to read and write the data. the bank addresses are delivere d to the rldram at th e same time as the write and read command and the first address part, a x . table 21 on page 60 and table 22 on page 61 show the addresses needed for both the first and second rising clock edges (a x and a y , respectively). the aref command do es not require an address on the second rising clock edge, as only the bank address is ne eded during this command. because of this, aref commands may be issued on consecutive clocks. the multiplexed address option is available by setting bit m5 to ?1? in the mode register. once this bit is set, the read, write, and mrs commands follow the format described in figure 35 on page 57. further information on operation with multiplexed addresses can be seen in ?multiplexed address mode? on page 57. dll reset dll reset is selected with bit m7 of the mode register as is shown in figure 11 on page 32. the default setting for this option is low, whereby the dll is disabled. once m7 is set high, 1,024 cycles (5s at 200 mhz) are needed before a read command can be issued. this time allows the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ckqk parameter. a reset of the dll is necessary if t ck or v dd is changed after the dll has already been enabled. to reset the dll, an mrs command must be issued where m7 is set low. after waiting t mrsc, a subsequent mrs command should be issued whereby m7 goes high. 1,024 clock cycles are then needed before a read command is issued. drive impedance matching the rldram ii is equipped with programmable impedance output buffers. this option is selected by setting bit m8 high during the mrs command. the purpose of the programmable impedance output buffers is to allow the user to match the driver imped- ance to the system. to adjust the impedance, an external precision resistor (rq) is connected between the zq ball and v ss . the value of the resistor must be five times the desired impedance. for example, a 300 resistor is required for an output impedance of 60 . the range of rq is 125?300 , which guarantees output impedance in the range of 25?60 (within 15 percent). output impedance updates may be required be cause over time variations may occur in supply voltage and temperature. when the ex ternal drive impedance is enabled in the mrs, the device will periodically sample th e value of rq. an impedance update is trans- parent to the system and does not affect device operation. all data sheet timing and current specifications are met during an update. when bit m8 is set low during the mrs co mmand, the rldram provides an internal impedance at the output buffer of 50 (30 percent with temperature variation). this impedance is also periodical ly sampled and adjusted to compensate for variation in supply voltage and temperature. on-die termination (odt) odt is enabled by setting m9 to ?1? during an mrs command. with odt on, the dqs and dm are terminated to v tt with a resistance r tt . the command, address, qvld, and clock signals are not terminat ed. figure 13 on page 36 shows the equivalent circuit of a dq receiver with odt. the odt function is dynamically switched off when a dq begins pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 36 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands to drive after a read command is issued. similarly, odt is designed to switch on at the dqs after the rldram has issued the last pi ece of data. the dm pin will always be terminated. see section entitled ?operations? on page 40 for relevant timing diagrams. notes: 1. all voltages referenced to v ss ( g nd). 2. v tt is expected to be set e q ual to v ref and must track variations in the dc level of v ref . 3. the r tt value is measured at 95c t c . figure 13: on-die termination-equivalent circuit table 20: on-die termination dc parameters description symbol min max units notes termination voltage v tt 0.95 v ref 1.05 v ref v1, 2 on-die termination r tt 125 185 3 v tt s w r tt dq re c eiver pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 37 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands write write accesses are initiated with a write co mmand, as shown in figure 14. the address needs to be provided during the write command. during write commands, data will be register ed at both edges of dk according to the programmed burst length (bl) . the rldram operates with a write latency (wl) that is one cycle longer than the programmed read latency (rl + 1), with the first valid data registered at the first rising dk edge wl cycles after the write command. any write burst may be followed by a subsequent read command (assuming t rc is met). to avoid external data bus contention, at least one nop command is needed between the write and read commands. figure 21 on page 45 and figure 22 on page 46 illustrate the timing requirements for a write followed by a read where one and two intermediary nops are required, respectively. setup and hold times for incoming dq relative to the dk edges are specified as t ds and t dh. the input data is masked if the corresponding dm signal is high. the setup and hold times for the dm signal are also t ds and t dh. figure 14: write command c k# c k we# ref# cs # a addre ss bank addre ss ba don ? t c are pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 38 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands read read accesses are initiated with a read co mmand, as shown in figure 15. addresses are provided with the read command. during read bursts, the memory device drives the read data so it is edge-aligned with the qk x signals. after a programmable read late ncy, data is available at the outputs. one half clock cycle prior to valid data on the read bus, the data valid signal, qvld, tran- sitions from low to high. qvld is also edge-aligned with the qk x signals. the skew between qk and the crossing point of ck is specified as t ckqk. t qkq0 is the skew between qk0 and the last valid data edge generated at the dq signals associated with qk0 ( t qkq0 is referenced to dq0?dq17 for the x36 configuration and dq0?dq8 for the x18 configuration). t qkq1 is the skew between qk1 and the last valid data edge generated at the dq signal s associated with qk1 ( t qkq1 is referenced to dq18?dq35 for the x36 and dq9?dq17 for the x18 configuration). t qkq x is derived at each qk x clock edge and is not cumulative over time. t qkq is defined as the skew between either qk differential pair and any output data edge. after completion of a burst, assuming no other commands have been initiated, output data (dq) will go high-z. the qvld signal transitions low on the last bit of the read burst. note that if ck/ck# violates the v id ( dc ) specification while a read burst is occur- ring, qvld will remain high until a dummy read command is issued. the qk clocks are free-running and will continue to cycl e after the read burst is complete. back-to- back read commands are possible, producin g a continuous flow of output data. the data valid window is derived from each qk transition and is defined as: t qhp - ( t qkq [max] + | t qkq [min]|). see figures 28?30 for illustration. any read burst may be followed by a subsequent write command. figure 27 on page 50 illustrate the timing requirements for a read followed by a write. some systems having long line le ngths or severe skews may need additional idle cycles inserted between read and write comma nds to prevent data bus contention. figure 15: read command don ? t c are c k c k# cs # we# ref# a ba addre ss bank addre ss pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 39 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii commands auto refresh (aref) aref is used to perform a refresh cycle on one row in a specific bank. because the row addresses are generated by an internal refresh counter for each bank, the external address balls are ?don?t care.? the bank addresses must be provided during the aref command. the bank address is needed during the aref command so refreshing of the part can effectively be hidden behind comma nds to other banks. the delay between the aref command and a subsequent command to the same bank must be at least t rc. within a period of 32ms ( t ref), the entire device must be refreshed. for the 576mb device, the rldram requires 128k cycles at an average periodic interval of 0.24s max (actual periodic refresh interval is 32ms/16 k rows/8 = 0.244s). to improve efficiency, eight aref commands (one for each bank) can be posted to the rldram at periodic intervals of 1.95s (32ms/16k rows = 1.95s). fi gure 31 on page 54 illustrates an example of a refresh sequence. figure 16: auto refresh command ck# ck we# ref# cs# address bank address ba don?t care pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 40 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations operations initialization the rldram must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operations or permanent damage to the device. the following sequence is used for power-up: 1. apply power (v ext , v dd , v dd q, v ref , v tt ) and start clock as soon as the supply volt- ages are stable. apply v dd and v ext before or at the same time as v dd q. 1 apply v dd q before or at the same time as v ref and v tt . although there is no timing relation between v ext and v dd , the chip starts the power-up sequence only after both volt- ages approach their nominal levels. ck/ck# must meet v id ( dc ) prior to being applied. 2 apply nop conditions to comman d pins. ensuring ck/ck# meet v id ( dc ) while applying nop conditions to the co mmand pins guarantees that the rldram will not receive unwanted commands during initialization. 2. maintain stable conditions for 200s (min). 3. issue at least three consecutive mrs commands: two or more dummies plus one valid mrs. the purpose of these consecutive mrs co mmands is to internally reset the logic of the rldram. note that t mrsc does not need to be met between these consecutive commands. it is recommended that all addr ess pins are held low during the dummy mrs commands. 4. t mrsc after the valid mrs, an auto refr esh command to all 8 banks (along with 1,024 nop commands) must be issued prior to normal operation. the sequence of the eight auto refresh commands (with respect to the 1,024 nop commands) does not matter. as is required for any operation, t rc must be met between an auto refresh command and a subsequent valid command to the same bank. note that older versions of the data sheet required each of these auto refresh commands be separated by 2,048 nop commands. this properly initializes the rldram but is no longer required. notes: 1. it is possible to apply v dd q before v dd . however, when doing this, the dqs, dm, and all other pins with an output driver, will go high instead of tri-stating. these pins will remain high until v dd is at the same level as v dd q. care should be taken to avoid bus conflicts during this period. 2. if v id ( dc ) on ck/ck# can not be met prior to being applied to the rldram, placing a large external resistor from cs# to v dd is a viable option for ensuring the command bus does not receive unwanted comma nds during this unspecified state. pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 41 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 17: power-up/initialization sequence notes: 1. recommend all address pins held low during dummy mrs commands. 2. a10?a17 must be low. 3. dll must be reset if t ck or v dd are changed. 4. ck and ck# must be separated at all times to prevent bogus commands from being issued. 5. the se q uence of the eight auto refresh command s (with respect to the 1,024 nop com- mands) does not matter. as is re q uired for any operation, t rc must be met between an auto refresh command and a subse q uent valid command to the same bank. r tt bank addre ss power-up: v dd an d sta b le c lo c k ( c k, c k#) t = 200s (min) dm ( ) ( ) ( ) ( ) addre ss v tt v ref v dd q c ommand nop nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don ? t c are v dd v ext dq t mr sc refresh all b anks 5 1,024 nop c omman d s ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) mr s ref c ode 2 bank 0 bank 7 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) mr s mr s c ode 1,2 c ode 1,2 ( ) ( ) ( ) ( ) valid valid valid c k c k# t c kl t0 t2 t1 t c kh t c k t3 ( ) ( ) ( ) ( ) t8 t9 t 6 t7 t4 t5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dk dk# t dkl t dkh t dk ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ref ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) hi g h-z ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) in d i c ates a b reak in time s c ale pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 42 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 18: power-up/initialization flow chart notes: 1. the se q uence of the eight auto refresh command s (with respect to the 1,024 nop com- mands) does not matter. as is re q uired for any operation, t rc must be met between an auto refresh command and a subse q uent valid command to the same bank. v dd, an d v ext ramp v dd q ramp apply v ref an d v tt apply sta b le c k/ c k# an d dk/dk# issue mr s c omman d ?a10?a17 must b e low wait at least 200s issue mr s c omman d ?a10?a17 must b e low desire d loa d mo d e re g ister with a10?a17 low assert nop for t mr sc issue auto refre s h to b ank 0 issue auto refre s h to b ank 1 issue auto refre s h to b ank 4 issue auto refre s h to b ank 5 issue auto refre s h to b ank 6 issue auto refre s h to b ank 7 vali d c omman d wait 1,024 nop c omman d s 1 s tep 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 6 17 18 19 issue auto refre s h to b ank 3 issue auto refre s h to b ank 2 mr s c omman d s must b e on c onse c utive c lo c k c y c les volta g e rails c an b e applie d simultaneously pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 43 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations write figure 19: write burst notes: 1. di an = data-in for bank a and address n ; subse q uent elements of burst are applied follow- ing di an . 2. bl = 4. t ckdk (nom) c ommand write nop nop nop nop nop addre ss bank a , a dd n nop c k c k# t0 t1 t2 t3 t4 t5 t5n t 6 t 6 nt7 dk dk# dq dm di an t ckdk (min) dq dm di an t ckdk (max) dq dm di an don ? t c are tran s itioning data wl = 5 dk dk# dk dk# nop wl - t c kdk wl + t c kdk pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 44 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 20: consecutive write-to-write notes: 1. di an (or bn) = data-in for bank a (or b ) and address n . 2. three subse q uent elements of the burst are ap plied following di for each bank. 3. bl = 4. 4. each write command may be to any bank; if the second write is to the same bank, t rc must be met. 5. nominal conditions are assumed for specifications not defined. c k c k# c ommand write nop write write nop nop nop nop nop bank a , a dd n bank b , a dd n bank a , a dd n nop addre ss t0 t1 t2 t3 t4 t5 t 6 t 6 n t5n t7 t8 t9 t8n t7n dq dm di bn di an di an don ? t c are tran s itioning data wl = 5 t r c = 4 wl = 5 dk dk# pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 45 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 21: write-to-read notes: 1. di an = data-in for bank a and address n . 2. do bn = data-out from bank b and address n . 3. two subse q uent elements of each burst follow di an and do bn . 4. bl = 2. 5. nominal conditions are assumed for specifications not defined. c ommand nop read nop nop nop addre ss bank a , a dd n nop c k c k# t0 t1 t2 t3 t4 t5 t5n t 6 t 6 nt7 dq dm di an do bn don ? t c are tran s itioning data wl = 5 qvld dk# dk qk# qk nop bank b , a dd n write rl = 4 pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 46 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 22: write-to-read (separated by two nops) notes: 1. di an = data-in for bank a and addre ss n . 2. do bn = data-out from bank b and address n . 3. one subse q uent element of each burst follow both di an and do bn . 4. bl = 2. 5. only one nop separating the write and read would have led to contention on the data bus because of the input and output data timing conditions being used. 6. nominal conditions are assumed for specifications not defined. c ommand nop nop read nop nop nop addre ss bank a , a dd n c k c k# t0 t1 t2 t3 t4 t5 t5n t 6 t7n t7 t8 dq dm di an do bn don ? t c are tran s itioning data wl = 5 qvld dk# dk qk# qk nop nop bank b , a dd n write rl = 4 t qkq (min) t c kqk (min) t c kdk (max) t dh pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 47 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 23: write ? dm operation notes: 1. di an = data-in for bank a and address n . 2. subse q uent elements of burst are provided on following clock edges. 3. bl = 4. 4. nominal conditions are assumed for specifications not defined. c k c k# dk dk# t c k t c h t c l t0 t1 t2 t3 t4 t5 t7n t 6 t7 t8 t 6 n nop nop c ommand write bank a , a dd n nop nop nop nop nop t dkl t dkh dq dm di an t d s t dh don ? t c are tran s itioning data addre ss wl = 5 nop pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 48 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations read figure 24: basic read burst timing notes: 1. do an = data-out from bank a and address an . 2. three subse q uent elements of the burst are applied following do an . 3. bl = 4. 4. nominal conditions are assumed for specifications not defined. c k c k# t c k t c h t c l t qk t qkh t qkl t r c = 4 rl = 4 dm t0 t1 t2 t3 t4 t5 t5n t 6 n t 6 t7 qk qvld qk# dq t ckqk ( min) t c kqk ( min) do an do an nop nop c ommand read bank a a dd n bank a a dd n nop nop read nop nop t qk t qkh t qkl don ? t c are tran s itioning data addre ss qk qvld qk# dq t ckqk ( max) t c kqk ( max) t qkvld t qkvld pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 49 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 25: consecutive read bursts (bl = 2) notes: 1. do an (or bn or cn ) = data-out from bank a (or bank b or bank c ) and address n . 2. one subse q uent element of the burst from each bank appears after each do x . 3. nominal conditions are assumed for specifications not defined. 4. example applies only when read co mmands are issued to same device. 5. bank address can be to any bank, but the subse q uent read can only be to the same bank if t rc has been met. 6. data from the read commands to bank d through bank g will appear on subse q uent clock cycles that are not shown. figure 26: consecutive read bursts (bl = 4) notes: 1. do an (or bn ) = data-out from bank a (or bank b ) and address n . 2. three subse q uent elements of the burst from each bank appears after each do x . 3. nominal conditions are assumed for specifications not defined. 4. example applies only when read co mmands are issued to same device. 5. bank address can be to any bank, but the subse q uent read can only be to the same bank if t rc has been met. 6. data from the read commands to banks c and d will appear on subse q uent clock cycles that are not shown. c ommand read read read read read read addre ss c k c k# qk qk# qvld dq rl = 4 do an do bn do c n t0 t1 t2 t3 bank a a dd n bank b a dd n bank c a dd n bank d a dd n bank e a dd n bank f a dd n bank g a dd n read t4n t4 t5 t 6 t5n t 6 n don ? t c are tran s itioning data c ommand read nop read nop read nop addre ss bank a a dd n bank b a dd n bank c a dd n bank d a dd n c k c k# qk qk# qvld dq rl = 4 do an do bn t0 t1 t2 t3 read t4n t4 t5 t 6 t5n t 6 n don ? t c are tran s itioning data pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 50 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 27: read-to-write notes: 1. do an = data-out from bank a and address n . 2. di bn = data-in for bank b and address n . 3. three subse q uent elements of each burst follow di bn and each do an . 4. bl = 4. 5. nominal conditions are assumed for specifications not defined. c k c k# c ommand addre ss qvld dq read t0 t1 t2 don ? t c are tran s itioning data write nop t3 t4 t5 nop nop t 6 nop wl = rl + 1 = 5 t7 t8 nop nop dk dk# qk dm qk# do an di bn rl = 4 bank a , a dd n bank b , a dd n nop nop pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 51 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 28: read data valid window for x9 device notes: 1. t qhp is defined as the lesser of t qkh or t qkl. 2. t qkq0 is referenced to dq0?dq8. 3. minimum data valid window ( t dvw) can be expressed as t qhp - ( t qkq x [max] + | t qkq x [min]|). t qhp 1 t qhp 1 t qhp 1 t qhp 1 t qkq0 (max) 2 t qkq0 (max) 2 t qkq0 (min) 2 t qkq0 (min) 2 t qkq0 (min) 2 t qkq0 (max) 2 t qkq0 (min) 2 t qkq0 (max) 2 dq0 . . . . . . . . . . . . . . . dq8 dq (last vali d d ata) dq (first vali d d ata) all dqs an d qks c olle c tively qk0# qk0 t dvw 3 t dvw 3 t dvw 3 t dvw 3 pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 52 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 29: read data valid window for x18 device notes: 1. t qhp is defined as the lesser of t qkh or t qkl. 2. t qkq0 is referenced to dq0?dq8. 3. minimum data valid window ( t dvw) can be expressed as t qhp - ( t qkq x [max] + | t qkq x [min]|). 4. t qkq1 is referenced to dq9?dq17. 5. t qkq takes into account the skew between any qk x and any dq. t qhp 1 t qhp 1 t qhp 1 t qhp 1 t qkq0 (max) 2 t qkq0 (max) 2 t qkq0 (min) 2 t qkq0 (min) 2 t qkq0 (min) 2 t qkq0 (min) 2 t qkq0 (max) 2 t qkq0 (max) 2 dq0 . . . . . . . . . . . . . . . dq8 dq (last valid data) dq (first valid data) all dqs and qks collectively qk0# qk0 t dvw 3 t dvw 3 t dvw 3 t dvw 3 t qhp 1 t qhp 1 t qhp 1 t qhp 1 t qkq1 (max) 4 t qkq1 (max) 4 t qkq1 (min) 4 t qkq1 (min) 4 t qkq1 (min) 4 t qkq1 (min) 4 t qkq1 (max) 4 t qkq1 (max) 4 dq9 . . . . . . . . . . . . . . . dq17 dq (last valid data) dq (first valid data) all dqs and qks collectively qk1# qk1 t dvw 3 t dvw 3 t dvw 3 t dvw 3 pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 53 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 30: read data valid window for x36 device notes: 1. t qhp is defined as the lesser of t qkh or t qkl. 2. t qkq0 is referenced to dq0?dq17. 3. minimum data valid window, t dvw, can be expressed as t qhp - ( t qkq x [max] + | t qkq x [min]|). 4. t qkq1 is referenced to dq18?dq35. 5. t qkq takes into account the skew between any qk x and any dq. t qhp 1 t qhp 1 t qhp 1 t qhp 1 t qkq0 (min) 2 t qkq0 (max) 2 t qkq0 (max) 2 t qkq0 (min) 2 t qkq0 (max) 2 t qkq0 (min) 2 t qkq0 (max) 2 t qkq0 (min) 2 dq0 . . . . . . . . . . . . . . . dq17 dq (last valid data) dq (first valid data) all dqs and qks collectively qk0# qk0 t dvw 3 t dvw 3 t dvw 3 t dvw 3 lower word t qhp 1 t qhp 1 t qhp 1 t qhp 1 t qkq1 (min) 4 t qkq1 (max) 4 t qkq1 (max) 4 t qkq1 (min) 4 t qkq1 (max) 4 t qkq1(min) 4 t qkq1(max) 4 t qkq1 (min) 4 dq18 . . . . . . . . . . . . . . . dq35 dq (last valid data) dq (first valid data) all dqs and qks collectively qk1# qk1 t dvw 3 t dvw 3 t dvw 3 t dvw 3 upper word pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 54 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations auto refresh figure 31: auto refresh cycle notes: 1. aref x = auto refresh command to bank x . 2. ac x = any command to bank x ; ac y = any command to bank y . 3. ba x = bank address to bank x ; ba y = bank address to bank y . c k c k# c ommand aref x a c x aref y a c y addre ss bank ba x ba y t c k t c h t c l dq dm dk, dk# t r c t0 t1 t2 t3 don ? t c are ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) in d i c ates a b reak in time s c ale pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 55 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations on-die termination figure 32: read burst with odt notes: 1. do an = data out from bank a and address n . 2. do an is followed by the remaining bits of the burst. 3. nominal conditions are assumed for specifications not defined. c ommand addre ss dq dq odt qvld do an dq odt off qk qk# qk qk# qk qk# rl = 4 c k c k# dq dq odt dq odt do an don ? t c are tran s itioning data dq do an read nop nop nop nop nop nop nop bank a , c ol n t0 t1 t2 t3 t4n t5n t4 t5 t 6 n t7n t 6 t7 qvld qvld bl = 2 bl = 4 bl = 8 nop dq odt on dq odt on dq odt off dq odt on on dq odt off dq odt on dq odt on pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 56 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 33: read-nop-read with odt notes: 1. do an (or bn ) = data-out from bank a (or bank b ) and address n . 2. bl = 2. 3. one subse q uent element of the burst appear after do an and do bn . 4. nominal conditions are assumed for specifications not defined. figure 34: read-to-write with odt notes: 1. do an = data-out from bank a and address n ; di bn = data-in for bank b and address n . 2. bl = 2. 3. one subse q uent element of each burst appears after each do an and di bn . 4. nominal conditions are assumed for specifications not defined. c ommand addre ss dq dq odt qvld do an do bn dq odt off dq odt off qk qk# rl = 4 c k c k# don ? t c are tran s itioning data read nop read nop nop nop nop nop bank a , c ol n bank b , c ol n t0 t1 t2 t3 t4n t4 t5 t 6 n t 6 t7 nop dq odt on dq odt on dq odt on ck# ck command address rl = 4 dq qk x qk x # do an di bn read bank a add n write nop nop nop nop nop nop nop don?t care undefined odt odt on odt on odt off wl = 5 dk x # dk x bank b add n t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t4n t6n pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 57 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations multiplexed address mode figure 35: command description in multiplexed address mode notes: 1. the minimum setup and hold time s of the two address parts are defined t as and t ah. ba ba ba addre ss bank addre ss a x a y a x a y ba a x a y mr s ref write read don ? t c are c k# c k cs # we# ref# pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 58 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 36: power-up/initialization sequence in multiplexed address mode notes: 1. recommended that all address pins held low during dummy mrs commands. 2. a10?a18 must be low. 3. set address a5 hi g h. this enbles the part to enter mu ltiplexed address mode when in non- multiplexed mode operation. multiplexed addres s mode can also be entered at some later time by issuing an mr s command with a5 hi g h. once address bit a5 is set hi g h, t mrsc must be satisfied before th e two-cycle multip lexed mode mrs command is issued. 4. address a5 must be set hi g h. this and the following step set the desired mode register once the rldram is in multiplexed address mode. 5. any command or address. 6. the above se q uence must be followed in order to powe r up the rldram in the multiplexed address mode. 7. dll must be reset if t ck or v dd are changed. 8. ck and ck# must separated at all times to prevent bogus commands from being issued. 9. the se q uence of the eight auto refresh command s (with respect to the 1,024 nop com- mands) does not matter. as is re q uired for any operation, t rc must be met between an auto refresh command and a subse q uent valid command to the same bank. r tt bank addre ss power-up: v dd an d sta b le c lo c k ( c k, c k#) t = 200s (min) dm ( ) ( ) ( ) ( ) addre ss v tt v ref v dd q c ommand nop nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don ? t c are v dd v ext dq t mr sc t mr sc refresh all b anks 9 1,024 nop c omman d s ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) mr s mr s c ode 2,3 a x 2,4 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) mr s mr s c ode 1,2 c ode 1,2 ( ) ( ) ( ) ( ) valid 5 valid 5 valid 5 c k c k# t c kl t0 t1 t2 t c kh t c k t3 ( ) ( ) t8 t9 t10 t11 t 6 t7 t4 t5 ( ) ( ) ( ) ( ) dk dk# t dkl t dkh t dk ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop hi g h-z ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) bank 7 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop ref ref ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a y 2 bank 0 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) in d i c ates a b reak in time s c ale pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 59 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 37: mode register defini tion in multiplexed address mode notes: 1. bits a10?a18 must be set to zero. 2. bl = 8 is not available. 3. 30 percent temperature variation. 4. dll reset turns the dll off. 5. a y 8 not used in mrs. 6. available only in 576mb device. 7. ba0?ba2 are ?don?t care.? 8. addresses a0, a3, a4, a5, a8, and a9 must be set as shown in order to activate the mode register in the multip lexed address mode. 2 1 0 3 4 5 8 9 1 8? 1 07 6 config bl am reserved 1 mode register (m x ) configuration 1 2 (default) 1 2 2 3 4 2,6 5 6 reserved reserved m 1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m5 0 1 a dd ress mux nonmultiplexed (default) multiplexed m8 0 1 drive impe d an c e internal 50 3 (default) external (zq) m9 0 1 on-die termination off (default) on dll na 5 m7 0 1 dll reset dll reset 4 (default) dll enabled odt m3 0 1 0 1 burst length 2 (default) 4 8 reserved m4 0 0 1 1 im m0 0 1 0 1 0 1 0 1 a3 a4 a8 a9 a y . . . a18 a0 a3 a4 a5 a8 a9 a x a10 . . . a18 a10 pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 60 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations address mapping in multiplexed address mode notes: 1. x = ?don?t care.? table 21: 576mb address mapping in multiplexed address mode data width burst length ball address a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 x36 2 a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 a y x a1 a2 x a6 a7 a19 a11 a12 a16 a15 4a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 a y x a1 a2 x a6 a7 x a11 a12 a16 a15 8a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 x a y x a1 a2 x a6 a7 x a11 a12 a16 a15 x18 2 a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 a y a20 a1 a2 x a6 a7 a19 a11 a12 a16 a15 4a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 a y x a1 a2 x a6 a7 a19 a11 a12 a16 a15 8a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 a y x a1 a2 x a6 a7 x a11 a12 a16 a15 x9 2 a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 a y a20 a1 a2 a21 a6 a7 a19 a11 a12 a16 a15 4a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 a y a20 a1 a2 x a6 a7 a19 a11 a12 a16 a15 8a x a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 a y x a1 a2 x a6 a7 a19 a11 a12 a16 a15 pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 61 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations configuration tables in multiplexed address mode in multiplexed address mode, the read and write latencies are increased by one clock cycle. however, the rldram cycle time remains the same as when in non-multiplexed address mode. notes: 1. t rc <20ns in any configuration is only av ailable with -25e and -18 speed grades. 2. minimum op erating fre q uency for -18 is 370 mhz. 3. bl = 8 is not available. 4. the minimum t rc is typically 3 cycles, ex cept in the case of a wri te followed by a read to the same bank. in this instance the minimum t rc is 4 cycles. refresh command in multiplexed address mode similar to other commands when in multiplexe d address mode, aref is executed on the rising clock edge following the one on which the command is issued. however, since only the bank address is required for aref, the next command can be applied on the following clock. the operation of the aref command and any other command is repre- sented in figure 38 on page 61. figure 38: burst refresh operation with multiplexed addressing notes: 1. any command. 2. bank n is chosen so that t rc is met. table 22: cycle time and read/write latenc y configuration table in multiplexed mode notes 1?2 apply to the entire table parameter configuration units 1 3 2 3 4 3, 4 5 t rc 46835 t ck t rl 57946 t ck t wl 681057 t ck valid fre q uency range 266?175 400?175 533?175 200?175 333?175 mhz c k c k# c ommand a c 1 nop a y aref aref aref aref aref aref aref aref a c 1 bank bank 0 bank n bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank n addre ss a x a y a x t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 don ? t c are pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 62 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 39: consecutive write bur sts with multiplexed addressing notes: 1. data from the second write command to bank a will appear on subse q uent clock cycles that are not shown. 2. di a = data-in for bank a ; di b = data-in for bank b . 3. three subse q uent elements of the burst are ap plied following di for each bank. 4. each write command may be to any bank; if the second write is to the same bank, t rc must be met. c k c k# c ommand write nop a y write write nop nop nop nop nop bank bank a a y nop bank b bank a 1 addre ss a x a x a x ay t0 t1 t2 t3 t4 t5 t 6 t 6 nt7 t8 t9 t8n t7n dq dm di b di a don ? t c are tran s itioning data wl = 6 t r c = 4 dk dk# pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 63 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 40: write-to-read with multiplexed addressing notes: 1. di a = data-in for bank a . 2. do b = data-out from bank b . 3. one subse q uent element of each burst follows di a and do b . 4. bl = 2. 5. nominal conditions are assumed for specifications not defined. 6. bank address can be to any bank, but the subse q uent read can only be to the same bank if t rc has been met. c ommand nop read nop nop nop addre ss a x a y nop c k c k# t0 t1 t2 t3 t4 t5 t 6 t 6 n t7n t7 dm don ? t c are tran s itioning data wl = 6 qvld dk# dk qk# qk nop bank bank a bank b write rl = 5 dq di a a x a y do b pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 64 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 41: consecutive read bursts with multiplexed addressing notes: 1. do a = data-out from bank a . 2. nominal conditions are assumed for specifications not defined. 3. bl = 4. 4. three subse q uent elements of the burst appear following do a . 5. example applies only when read co mmands are issued to same device. 6. bank address can be to any bank, but the subse q uent read can only be to the same bank if t rc has been met. 7. data from the read commands to banks b through bank d will appear on subse q uent clock cycles that are not shown. c ommand read nop read nop read nop addre ss a x a y bank a c k c k# qk qk# bank qvld dq rl = 5 do a t0 t1 t2 t3 read t4 t5 t 6 t5n t 6 n don ? t c are tran s itioning data bank b bank c bank d a x a x a x a y a y pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 65 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii operations figure 42: read-to-write with multiplexed addressing notes: 1. do an = data-out from bank a . 2. di bn = data-in for bank b . 3. nominal conditions are assumed for specifications not defined. 4. bl = 4. 5. three subse q uent elements of the burst are applied following do an . 6. three subse q uent elements of the burst which appear following di bn are not all shown. 7. bank address can be to any bank, but the wr ite command can only be to the same bank if t rc has been met. c k c k# c ommand addre ss bank qvld dq read t0 t1 t2 don ? t c are tran s itioning data write nop t3 t4 t5 t5n nop nop t 6 t 6 n nop wl = rl + 1 = 6 t7 t8 t8n nop nop dk dk# qk dm qk# do an di bn rl = 5 a x a y a y bank a a x bank b nop nop pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 66 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) ieee 1149.1 serial boundary scan (jtag) rldram incorporates a serial boundary-scan test access port (tap) for the purpose of testing the connectivity of the device once it has been mounted on a printed circuit board (pcb). as the complexity of pcb hi gh-density surface mounting techniques increases, the boundary-scan architecture is a valuable resource for interconnectivity debug. this port operates in accordance with ieee standard 1149.1-2001 (jtag) with the exception of the zq pin. to ensure proper boundary-scan testing of the zq pin, mrs bit m8 needs to be set to 0 until the jtag te sting of the pin is complete. note that upon power up, the default state of mrs bit m8 is low. the input signals of the test access port (tdi, tms, and tck) use v dd as a supply, while the output signal of the tap (tdo) uses v dd q. the jtag test access port utilizes the tap controller on the rldram, from which the instruction register, boundary scan register , bypass register, and id register can be selected. each of these functions of the ta p controller is described in detail below. disabling the jtag feature it is possible to operate rldram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconne cted. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state, which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. all of the states in figure 43: ?tap controller state diagram,? on page 68 are entered through the serial input of the tms pin. a ?0? in the diagram represents a low on the tms pin during the rising edge of tck while a ?1? represents a high on tms. test data-in (tdi) the tdi ball is used to serially input test in structions and data into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded in to the tap instruction register. for informa- tion on loading the instruction register, see figure 43 on page 68. tdi is connected to the most significant bit (msb) of any register (see figure 44 on page 68). test data-out (tdo) the tdo output ball is used to serially cl ock test instructions and data out from the registers. the tdo output driver is only ac tive during the shift-ir and shift-dr tap controller states. in all other states, the tdo pin is in a high-z state. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register (see figure 44 on page 68). pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 67 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) tap controller the tap controller is a finite state machine that uses the state of the tms pin at the rising edge of tck to navigate through its various modes of operation. the tap controller state diagram can be seen in figure 43 on page 68. each state is described in detail below. test-logic-reset the test-logic-reset controller state is entered when tms is held high for at least five consecutive rising edges of tck. as long as tms remains high, the tap controller will remain in the test-logic-reset state. the test logic is inactive during this state. run-test/idle the run-test/idle is a controller state in between scan operations. this state can be maintained by holding tms low. from here either the data register scan, or subse- quently, the instruction register scan can be selected. select-dr-scan select-dr-scan is a temporary controller state. all test data registers retain their previous state while here. capture-dr the capture-dr state is where the data is para llel-loaded into the test data registers. if the boundary scan register is the currently selected register, then the data currently on the pins is latched into the test data registers. shift-dr data is shifted serially through the data regist er while in this state. as new data is input through the tdi pin, data is shifted out of the tdo pin. exit1-dr, pause-dr, and exit2-dr the purpose of exit1-dr is used to provide a path to return back to the run-test/idle state (through the update-dr state). the pause- dr state is entered when the shifting of data through the test registers needs to be suspended. when shifting is to reconvene, the controller enters the exit2-dr state and then can re-enter the shift-dr state. update-dr when the extest instruction is selected, there are latched parallel outputs of the boundary-scan shift register that only change state during the update-dr controller state. instruction register states the instruction register states of the tap contro ller are similar to the data register states. the desired instruction is serially shifted into the instruction register during the shift-ir state and is loaded during the update-ir state. pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 68 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) figure 43: tap controller state diagram figure 44: tap controller block diagram notes: 1. x = 112 for all configurations. capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 test-logic reset run-test/ idle select ir-scan select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 0 0 1 2 3 4 5 6 7 0 1 2 29 30 31 . . . 0 1 2 . . . . . tck tms selection circuitry selection circuitry tdo tdi boundry scan register identification register instruction register tap controller bypass register x 1 pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 69 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) performing a tap reset a reset is performed by forcing tms high (v dd q) for five rising edges of tck. this reset does not affect the operation of th e rldram and may be performed while the rldram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the rldram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register eight-bit instructions can be serially loaded into the instruction register. this register is loaded during the update-ir state of the ta p controller. upon power-up, the instruction register is loaded with the idcode instruct ion. it is also loaded with the idcode instruction if the controller is placed in a re set state as described in the previous section. when the tap controller is in the capture-ir state, the two lsbs are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the rldram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the rldram. several balls are also included in the scan register to reserved balls. the rldram has a 113-bit register. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. table 29 on page 74 shows the order in which the bits are connected. each bit corre- sponds to one of the balls on the rldram pa ckage. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-speci fic, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hard- wired into the rldram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code an d other information described in table 26 on page 73. pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 70 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) tap instruction set overview many different instructions (2 8 ) are possible with the 8-bi t instruction register. all combinations used are listed in table 28 on page 74. these six instructions are described in detail below. the remaining instructions are reserved and should not be used. the tap controller used in this rldram is fully compliant to the 1149.1 convention. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register thro ugh the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest the extest instruction allows circuitry extern al to the component package to be tested. boundary-scan register cells at output balls ar e used to apply a test vector, while those at input balls capture test results. typically, th e first test vector to be applied using the extest instruction will be shifted into th e boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on, and the preload data is driven onto the output balls. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. high-z the high-z instruction causes the boundary scan register to be connected between the tdi and tdo. this places all rldr am outputs into a high-z state. clamp when the clamp instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary scan register. sample/preload when the sample/preload instruction is load ed into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirec- tional balls is captured in the boundary scan register. the user must be aware that the tap controll er clock can only operate at a frequency up to 50 mhz, while the rldram clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar- antee as to the value that will be captur ed. repeatable results may not be possible. to ensure that the boundary scan register will capture the correct value of a signal, the rldram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time ( t cs plus t ch). the rldram clock input might not be captured pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 71 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) correctly if there is no way in a design to stop (or slow) the clock during a sample/ preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens th e boundary scan path when multiple devices are connected together on a board. reserved for future use the remaining instructions are not implemente d but are reserved for future use. do not use these instructions. figure 45: jtag operation ? loading instruction code and shifting out data tm s tdi t c k tdo t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 tap c ontroller s tate test-lo g i c - reset run-test i d le c apture-ir s hift-ir s ele c t-dr- sc an s ele c t-ir- sc an ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) pause-ir pause-ir s hift-ir exit 1-ir ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 8- b it instru c tion c o d e don ? t c are tran s itioning data tm s tdi t c k tdo tap c ontroller s tate t10 t11 t12 t13 t14 t15 t1 6 t17 t18 exit 2-ir s ele c t-dr- sc an c apture-dr s hift-dr s hift-dr exit1-dr up d ate-dr run-test i d le up d ate-ir ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) n - b it re g ister b etween tdi an d tdo t19 run-test i d le pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 72 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) figure 46: tap timing notes: 1. t cs and t ch refer to the setup and hold time re q uirements of latching data from the bound- ary scan register. table 23: tap input ac logic levels +0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted description symbol min max units input high (logic 1) voltage v ih v ref + 0.3 ? v input low (logic 0) voltage v il ?v ref - 0.3 v notes: 1. all voltages referenced to v ss ( g nd). table 24: tap ac electrical characteristics +0c t c +95c; +1.7v v dd +1.9v description symbol min max units clock clock cycle time t thth 20 ns clock fre q uency f tf 50 mhz clock hi g h time t thtl 10 ns clock low time t tlth 10 ns tdi/tdo times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 10 ns tdi valid to tck hi g h t dvth 5 ns tck hi g h to tdi invalid t thdx 5 ns setup times tms setup t mvth 5 ns capture setup t cs 5 ns hold times tms hold t thmx 5 ns capture hold t ch 5 ns don?t care t tlth t thtl t thth t thmx t mvth t thdx t dvth t tlox t tlov undefined test clock (tck) test mode select (tms) test data-in (tdi) test data-out (tdo) t1 t2 t3 t4 t5 t6 pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 73 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) notes: 1. all voltages referenced to v ss ( g nd). 2. overshoot = v ih ( ac ) v dd + 0.7v for t t ck/2; undershoot = v il ( ac ) ?0.5v for t t ck/2; during normal operation, v dd q must not exceed v dd . table 25: tap dc electrical characteristics and operating conditions +0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted description condition symbol min max units notes input high (logic 1) voltage v ih v ref + 0.15 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il v ss q - 0.3 v ref - 0.15 v 1, 2 input leakage current 0v v in v dd il i ?5.0 5.0 a output leakage current output disabled, 0v v in v dd q il o ?5.0 5.0 a output low voltage i olc = 100a v ol 10.2v1 output low voltage i olt = 2ma v ol 20.4v1 output high voltage |i ohc | = 100a v oh 1v dd q - 0.2 v 1 output high voltage |i oht | = 2ma v oh 2v dd q - 0.4 v 1 table 26: identification register definitions instruction field all devices description revision number (31:28) abcd ab = die revision cd = 00 for x9, 01 for x18, 10 for x36 device id (27:12) 00jkidef10100111 def = 000 for 288mb, 001 for 576mb i = 0 for common i/o, 1 for separate i/o jk = 01 for rldram ii, 00 for rldram micron jedec id code (11:1) 00000101100 allows uni q ue identification of rldram vendor id register presence indicator (0) 1 indicates the presence of an id register table 27: scan register sizes register name bit size instruction 8 bypass 1 id 32 boundary scan 113 pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 74 ?2004 micron technology, inc. all rights reserved. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) table 28: instruction codes instruction code description extest 0000 0000 captures i/o ring contents; places the boun dary scan register between tdi and tdo; this operation does not affect rldram operations id code 0010 0001 loads the id register with the vendor id co de and places the register between tdi and tdo; this operation does not affect rldram operations sample/preload 0000 0101 captures i/o ring contents; places the bo undary scan register between tdi and tdo clamp 0000 0111 selects the bypass register to be connec ted between tdi and tdo; data driven by output balls are determined from values held in the boundary scan register high-z 0000 0011 selects the bypass register to be conn ected between tdi and tdo; all outputs are forced into high-z bypass 1111 1111 places the bypass register between tdi and tdo; this operation does not affect rldram operations table 29: boundary scan (exit) order bit# ball bit# ball bit# ball 1k139r1177c11 2k240r1178c11 3l241p1179c10 4l142p1180c10 5m143p1081b11 6m344p1082b11 7 m2 45 n11 83 b10 8 n1 46 n11 84 b10 9 p1 47 n10 85 b3 10 n3 48 n10 86 b3 11 n3 49 p12 87 b2 12 n2 50 n12 88 b2 13 n2 51 m11 89 c3 14 p3 52 m10 90 c3 15 p3 53 m12 91 c2 16 p2 54 l12 92 c2 17 p2 55 l11 93 d3 18 r2 56 k11 94 d3 19 r3 57 k12 95 d2 20 t2 58 j12 96 d2 21 t2 59 j11 97 e2 22 t3 60 h11 98 e2 23 t3 61 h12 99 e3 24 u2 62 g 12 100 e3 25 u2 63 g 10 101 f2 26 u3 64 g 11 102 f2 27 u3 65 e12 103 f3 28 v2 66 f12 104 f3 29 u10 67 f10 105 e1 30 u10 68 f10 106 f1 31 u11 69 f11 107 g 2 32 u11 70 f11 108 g 3 ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of mi cron technology, inc. rldram is a trademark of qimonda a g in various countries, and is used by micron technology, inc. under license from qimonda. all other trademarks are the property of their re spective owners. this data sheet contains minimum and maximum limits spec ified over the power supply and temperature range set forth her ein. although considered final, these specifications are subject to change, as further product develo pment and data characterization some- times occur. 576mb: x9, x18, x36 2.5v v ext , 1.8v v dd , hstl, cio, rldram ii ieee 1149.1 serial boundary scan (jtag) pdf: 09005aef80a41b46/source: 09005aef809f284b micron technology, inc., reserves the right to change products or specifications without notice. 576mb_rldram_ii_cio.core.fm - rev a 3/08 en 75 ?2004 micron technology, inc. all rights reserved. 33 t10 71 e10 109 g 1 34 t10 72 e10 110 h1 35 t11 73 e11 111 h2 36 t11 74 e11 112 j2 37 r10 75 d11 113 j1 38 r10 76 d10 ? ? table 29: boundary scan (exit) order (continued) bit# ball bit# ball bit# ball |
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