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TC58NVM9S3ETA00 2010-05-21a 1 tentative toshiba mos digital inte grated circuit silicon gate cmos 512m bit (64m 8 bit) cmos nand e 2 prom description the tc58nvm9s3e is a single 3.3v 512mbit (553,648,128bits) nand electrically erasable and programmable read-only memory (nand e 2 prom) organized as (2048 + 64) bytes 64 pages 512blocks. the device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. the erase operation is implemented in a single block unit (128 kbytes + 4 kbytes: 2112 bytes 64 pages). the tc58nvm9s3e is a serial-type memory device whic h utilizes the i/o pins for both address and data input/output as well as for command in puts. the erase and program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recordin g, image file memory for still cameras and other systems which require high-d ensity non-volatile memory data storage. features ? organization x8 memory cell array 2112 32k 8 register 2112 8 page size 2112 bytes block size (128k + 4k) bytes ? modes read, reset, auto page program, auto block erase, status read ? mode control serial input/output command control ? number of valid blocks min 502 blocks max 512 blocks ? power supply v cc = 2.7v to 3.6v ? access time cell array to register 30 s max serial read cycle 25 ns min (cl=100pf) ? program/erase time auto page program 300 s/page typ. auto block erase 2.5 ms/block typ. ? operating current read (25 ns cycle) 30 ma max. program (avg.) 30 ma max erase (avg.) 30 ma max standby 50 a max ? package tsop i 48-p-1220-0.50 (weight: 0.53 g typ.)
TC58NVM9S3ETA00 2010-05-21a 2 pin assignment (top view) pin names i/o1 to i/o8 i/o port ce chip enable we write enable re read enable cle command latch enable ale address latch enable wp write protect by / ry ready/busy v cc power supply v ss ground nc nc nc nc i/o8 i/o7 i/o6 i/o5 nc nc nc v cc v ss nc nc nc i/o4 i/o3 i/o2 i/o1 nc nc nc nc 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 nc nc nc nc nc nc by / ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc nc nc 8 8 TC58NVM9S3ETA00
TC58NVM9S3ETA00 2010-05-21a 3 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage ? 0.6 to 4.6 v v in input voltage ? 0.6 to 4.6 v v i/o input /output voltage ? 0.6 to v cc + 0.3 ( 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10 s) 260 c t stg storage temperature ? 55 to 150 c t opr operating temperature 0 to 70 c capacitance * (ta = 25c, f = 1 mhz) symb0l parameter condition min max unit c in input v in = 0 v ? 10 pf c out output v out = 0 v ? 10 pf * this parameter is periodically sampl ed and is not tested for every device. i/o control circuit status register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control by / ry v cc i/o1 v ss i/o8 ce cle ale we re by / ry row address buffer decoder to wp address register
TC58NVM9S3ETA00 2010-05-21a 4 valid blocks symbol parameter min typ. max unit n vb number of valid blocks 502 ? 512 blocks note: the device occasionally contains unus able blocks. refer to application note (13) toward the end of this document. the first block (block 0) is guaranteed to be a valid block at the time of shipment. the specification for the minimum number of valid blocks is applicable over lifetime recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 ? 3.6 v v ih high level input voltage 2.7 v v cc 3.6 v vcc x 0.8 ? v cc + 0.3 v v il low level input voltage 2.7 v v cc 3.6 v ? 0.3 * ? vcc x 0.2 v * ? 2 v (pulse width lower than 20 ns) dc characteristics (ta = 0 to 70 ? , v cc = 2.7 to 3.6v) symbol parameter condition min typ. max unit i il input leakage current v in = 0 v to v cc ? ? 10 a i lo output leakage current v out = 0 v to v cc ? ? 10 a i cco1 serial read current ce = v il , i out = 0 ma, tcycle = 25 ns ? ? 30 ma i cco2 programming current ? ? ? 30 ma i cco3 erasing current ? ? ? 30 ma i ccs standby current ce = v cc ? 0.2 v, wp = 0 v/v cc ? ? 50 a v oh high level output voltage i oh = ? 0.1 ma vcc ? 0.2 ? ? v v ol low level output voltage i ol = 0.1 ma ? ? 0.2 v i ol ( by / ry ) output current of by / ry pin v ol = 0.2 v ? 4 ? ma
TC58NVM9S3ETA00 2010-05-21a 5 ac characteristics and recommended operating conditions (ta = 0 to 70 ? , v cc = 2.7 to 3.6v) symbol parameter min max unit t cls cle setup time 12 ? ns t clh cle hold time 5 ? ns t cs ce setup time 20 ? ns t ch ce hold time 5 ? ns t wp write pulse width 12 ? ns t als ale setup time 12 ? ns t alh ale hold time 5 ? ns t ds data setup time 12 ? ns t dh data hold time 5 ? ns t wc write cycle time 25 ? ns t wh we high hold time 10 ? ns t ww wp high to we low 100 ? ns t rr ready to re falling edge 20 ? ns t rp read pulse width 12 ? ns t rc read cycle time 25 ? ns t rea re access time ? 20 ns tcea ce access time ? 25 ns t clr cle low to re low 10 ? ns t ar ale low to re low 10 ? ns t rhoh re high to output hold time 22 ? ns t rloh re low to output hold time 5 ? ns t rhz re high to output high impedance ? 60 ns t chz ce high to output high impedance ? 20 ns t csd ce high to ale or cle don?t care 0 ? ns t reh re high hold time 10 ? ns t ir output-high-impedance-to- re falling edge 0 ? ns t rhw re high to we low 30 ? ns t whc we high to ce low 30 ? ns t whr we high to re low 60 ? ns t r memory cell array to starting address ? 30 s t wb we high to busy ? 100 ns t rst device reset time (ready/read/program/erase) ? 6/6/10/500 s *1: tcls and tals can not be shorter than twp *2: tcs should be longer than twp + 8ns.
TC58NVM9S3ETA00 2010-05-21a 6 ac test conditions condition parameter v cc : 2.7 to 3.6v input level v cc ? 0.2 v, 0.2 v input pulse rise and fall time 3 ns input comparison level vcc / 2 output data comparison level vcc / 2 output load c l (100 pf) + 1 ttl note: busy to ready time depends on the pull-up resistor tied to the by / ry pin. (refer to application note (9) toward the end of this document.) programming and erasing characteristics (ta = 0 to 70 ? , v cc = 2.7 to 3.6v) symbol parameter min typ. max unit notes t prog average programming time ? 300 700 s n number of partial program cycles in the same page ? ? 4 (1) t berase block erasing time ? 2.5 10 ms (1) refer to application note (12) toward the end of this document. data output when treh is long, output buffers are disabled by /re=hi gh, and the hold time of da ta output depend on trhoh (25ns min). on this condition, wavefo rms look like normal serial read mode. when treh is short, output buffers are not disabled by /re=high, and th e hold time of data output depend on trloh (5ns min). on this condition, output buffers are disabled by the rising edge of cle,ale,/ce or falling edge of /we, and waveforms look like extended data output mode.
TC58NVM9S3ETA00 2010-05-21a 7 timing diagrams latch timing diagram for command/address/data command input cycle timing diagram cle ale ce re we hold time t dh setup time t ds i/o : v ih or v il t cs t dh t ds t als t alh t wp t cls t ch t clh : v ih or v il ce cle we ale i/o
TC58NVM9S3ETA00 2010-05-21a 8 address input cycle timing diagram data input cycle timing diagram we t wp t wp t wh t wp t als t wc t dh t ds d in 0 d in 1 t clh t ch ale cle ce i/o d in 2111 t dh t ds t dh t ds t cs t cls t ch t cs t alh pa8 to 14 ca8 to 11 : v ih or v il t dh t ds t cls cle t als t alh t wp t wh t wp ca0 to 7 t dh t ds t cs t cs ce we ale i/o t dh t ds t wp t wh t dh t ds t wp t wh t wc pa0 to 7 t clh t ch t ch
TC58NVM9S3ETA00 2010-05-21a 9 serial read cycle timing diagram status read cycle timing diagram t reh t chz ce t rhz t rea t rc t rr t rhz t rea t rhz t rea re by / ry i/o t rhoh t rhoh t rhoh t rp t rp t rp : v ih or v il t cea t cea : v ih or v il * : 70h represents the hexadecimal number t whr we t dh t ds t cls t clr t cs t clh t ch t wp status output 70h * t whc t ir t rea t rhz t chz ce cle re by / ry i/o t rhoh t cea
TC58NVM9S3ETA00 2010-05-21a 10 read cycle timing diagram read cycle timing diagram: when interrupted by ce t clr 30h pa8 to 14 pa0 to 7 ca8 to 11 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea col. add. n data out from col. add. n 00h d out n d out n + 1 by / ry t cea 30h pa8 to 14 pa0 to 7 ca8 to 11 ca0 to 7 i/o t cs t cls t clh t ch t dh t ds t wc t als t alh we cle ce ale re t dh t ds t dh t ds t dh t ds t dh t ds t alh t clr t r t dh t ds t wb t cs t cls t clh t ch t als t rc t rr t rea col. add. n 00h d out n d out n + 1 by / ry t chz t rhz t rhoh col. add. n t csd t cea
TC58NVM9S3ETA00 2010-05-21a 11 column address change in read cycle timing diagram (1/2) t clr i/o t cs t cls t clh t ch t wc t als t alh t r cle ce ale re t dh t ds t dh t ds t alh t wb t cs t cls t clh t ch t als t rc t rea tcea t rr page address p page address p column address a 00h ca0 to 7 t dh t ds ca8 to 11 t dh t ds pa0 to 7 t dh t ds pa8 to 14 t dh t ds 30h d out a d out a + 1 d out a + n we 1 continues from of next page 1 by / ry
TC58NVM9S3ETA00 2010-05-21a 12 column address change in read cycle timing diagram (2/2) i/o t cs t cls t clh t ch 05h ca0 to 7 ca8 to 11 t wc t als t alh cle ce ale re t dh t ds t dh t ds t dh t ds column address b e0h t dh t ds t alh t cs t cls t clh t ch t als t rea d out a + n t rhw page address p column address b t rc t clr tcea t ir d out b + n? d out b + 1 d out b 1 continues from of last page 1 we by / ry t whr
TC58NVM9S3ETA00 2010-05-21a 13 data output timing diagram command i/o t rc t dh t rp t rp we cle ce ale re t rloh t reh t rea t rhz t rea t cs t cls t clh t ch t rp t rr t rea t rloh t ds by / ry t chz t rhoh t rhoh t cea dout dout t alh
TC58NVM9S3ETA00 2010-05-21a 14 auto-program operation timing diagram ca0 to 7 t cls t cls t als t ds t dh we cle ce ale re by / ry : v ih or v il t clh t ch t cs t ds t dh t alh i/o : do not input data while data is being output. t cs t dh t ds t dh t prog t wb t ds t alh t als * ) m: up to 2112 (byte input data for 8 device). column address n ca8 to 11 d in n d in m 10h 70h status output pa0 to 7 pa8 to 14 80h d in n+1
TC58NVM9S3ETA00 2010-05-21a 15 auto block erase timing diagram t cs 60h pa8 to 14 we cle ce ale re by / ry : v ih or v il t cls t clh t cls pa0 to 7 t ds t dh t als : do not input data while data is being output. auto block erase setup command i/o d0h 70h t wb t berase busy status read command erase start command status output t alh
TC58NVM9S3ETA00 2010-05-21a 16 id read operation timing diagram : v ih or v il we cle re t cea ce ale i/o t ar id read command address 00 maker code device code t rea t cls t cs t ds t ch t alh t als t cls t cs t ch t alh t dh 90h 00h 98h t rea f0h t rea t rea see table 5 see table 5 t rea see table 5
TC58NVM9S3ETA00 2010-05-21a 17 pin functions the device is a serial access memory which utiliz es time-sharing input of address information. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command regi ster from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading address in formation into the internal address register. address information is latched into the address register from the i/o port on the rising edge of we while ale is high. chip enable: the device goes into a low-power standby mode when ce goes high during the device is in ready state. the ce signal is ignored when device is in busy state ( by / ry = l), such as during a program or erase or read operation, and will not enter standby mode even if the ce input goes high. write enable: the we signal is used to control the acqu isition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also increme nted (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/ output data to and from the device. write protect: the wp signal is used to protect the de vice from accidental programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usua lly used for protecting the data during the power-on/off sequence when input signals are invalid. ready/busy: the by / ry output signal is used to indicate th e operating condition of the device. the by / ry signal is in busy state ( by / ry = l) during the program, erase and read operations and will return to ready state ( by / ry = h) after completion of the operation. the output buff er for this signal is an open drain and has to be pulled-up to vccq with an appropriate resister. if by / ry signal is not pulled-up to vccq( ?open? state ), device operation can not guarantee. ce we re wp by / ry
TC58NVM9S3ETA00 2010-05-21a 18 schematic cell layout and address assignment the program operation works on page units wh ile the erase operation works on block units. a page consists of 2112 bytes in which 2048 bytes are used for main memory storage and 64 bytes are for redundancy or for other uses. 1 page = 2112 bytes 1 block = 2112 bytes 64 pages = (128k + 4k) bytes capacity = 2112 bytes 64pages 512 blocks an address is read in via the i/o port over four consecutive clock cycles, as shown in table 1. table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l l l ca11 ca10 ca9 ca8 third cycle pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 ca0 to ca11: column address pa0 to pa14: page address pa6 to pa14: block address pa0 to pa5: nand address in block fourth cycle l pa14 pa13 pa12 pa11 pa10 pa9 pa8 2112 32768 pages 512 blocks 64 pages = 1 block 8i/o 2048 64 i/o8 i/o1
TC58NVM9S3ETA00 2010-05-21a 19 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by command operations shown in table 3. address input, comma nd input and data input/output are controlled by the cle, ale, ce , we , re and wp signals, as shown in table 2. table 2. logic table cle ale ce we re wp * 1 command input h l l h * data input l l l h h address input l h l h * serial data output l l l h * during program (busy) * * * * * h during erase (busy) * * * * * h * * h * * * during read (busy) * * l h ( * 2) h ( * 2) * program, erase inhibit * * * * * l standby * * h * * 0 v/v cc h: v ih , l: v il , * : v ih or v il * 1: refer to application note (10) toward the end of this document regarding the wp signal when program or erase inhibit * 2: if ce is low during read busy, we and re must be held high to avoid unintended command/address input to the device or read to device. reset or status read command can be input during read busy.
TC58NVM9S3ETA00 2010-05-21a 20 table 3. command table (hex) first cycle second cycle acceptable while busy serial data input 80 ? read 00 30 column address change in serial data output 05 e0 auto page program 80 10 column address change in serial data input 85 ? auto block erase 60 d0 id read 90 ? status read 70 ? { reset ff ? { table 4. read mode operation states cle ale ce we re i/o1 to i/o8 power output select l l l h l data output active output deselect l l l h h high impedance active h: v ih , l: v il hex data bit assignment (example) 1 0 0 0 0 0 0 0 8765432i/o1 serial data input: 80h
TC58NVM9S3ETA00 2010-05-21a 21 device operation read mode read mode is set when the "00h" and ?30h? commands are issued to th e command register. between the two commands, a start address for the read mode needs to be issued. refer to the figures below for the sequence and the block diagram (refer to the detailed timing chart.). random column address change in read cycle a data transfer operation from the cell array to the register starts on the rising edge of we in the 30h command input cycle (after the address information has been latched). the device will be in the busy state during this transfer period. after the transfer period, the device returns to ready state. serial data can be output synchronously with the re clock from the start address designated in the address input cycle. cell array select page n m m i/o1 to 8: m = 2111 select page n m m? during the serial data output from the register, the column address can be changed by inputting a new column address using the 05h and e0h commands. the data is read out in serial starting at the new column address. random column address change operation can be done multiple times within the same page. by / ry we cle re 00h ce ale i/o busy 30h page address n column address m m m+1 m+2 page address n t r start-address input start-address input by / ry we cle 00h ce ale i/o col. m page n busy page n 30h 05h e0h col. m? m m + 1 m? m? + 1 m? + 2 m? + 3m? + 4 page n col. m start from col. m start from col. m? t r m + 2m + 3 re
TC58NVM9S3ETA00 2010-05-21a 22 auto page program operation the device carries out an automatic page program operation when it receives a "10h" program command after the address and data have been input. the sequence of command, addr ess and data input is shown below. (refer to the detailed timing chart.) by / ry random column address change in auto page program operation the column address can be changed by the 85h command duri ng the data input sequence of the auto page program operation. two address input cycles after the 85h command are recognized as a new column address for the data input. after the new data is input to the new column address, the 10h command initiates the actual data program into the selected page automatically. the random column address ch ange operation can be repeated multiple times within the same page. the data is transferred (programmed) from the register to the selected page on the rising edge of we following input of the ?10h? command. after programming, the programmed data is transferred back to the register to be automatically verified by the device. if the programming does not succeed, the program/verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. selected page program data input read& verification cle 80h ale i/o page p ce we col. m din 10h 70h din din din data status out re selected page readin g & verification program data input col. m col. m? 80h page n col. m 85h din din 10h status din din din din col. m? din din 70h 90h
TC58NVM9S3ETA00 2010-05-21a 23 auto block erase the auto block erase operation st arts on the rising edge of we after the erase start command ?d0h? which follows the erase setup command ?60h?. this two-cycle process for erase oper ations acts as an extra layer of protection from accidental erasure of data due to external noise. the de vice automatically executes the erase and verify operations. pass i/o fail by / ry 60 d0 70 block address input: 2 cycles status read command busy erase start command
TC58NVM9S3ETA00 2010-05-21a 24 id read the device contains id codes which can be used to iden tify the device type, the ma nufacturer, and features of the device. the id codes can be read out under the following timing conditions: table 5. code table description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1st data maker code 1 0 0 1 1 0 0 0 98h 2nd data device code 1 1 1 1 0 0 0 0 f0h 3rd data chip number, cell type ? ? ? ? ? ? ? ? see table 4th data page size, block size, ? ? ? ? ? ? ? ? see table 5th data plane number ? ? ? ? ? ? ? ? see table 3rd data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 internal chip number 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 00h 98h f0h see table 5 see table 5 we cle re t cea ce ale i/o t ar t rea id read command address 00 maker code device code see table 5
TC58NVM9S3ETA00 2010-05-21a 25 4th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 page size (without redundant area) 1 kb 2 kb 4 kb 8 kb 0 0 1 1 0 1 0 1 block size (without redundant area) 64 kb 128 kb 256 kb 512 kb 0 0 1 1 0 1 0 1 5th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 plane number 1 plane 2 plane 4 plane 8 plane 0 0 1 1 0 1 0 1
TC58NVM9S3ETA00 2010-05-21a 26 status read the device automatically implements the execution and verification of the program and erase operations. the status read function is used to monitor the ready/ busy status of the device, determine the result (pass /fail) of a program or erase operation, and determine whether the device is in protect mode. the device status is output via the i/o port using re after a ?70h? command input. the status read can also be used during a read operation to find out the ready/busy status. the resulting information is outlined in table 6. table 6. status output table definition page program block erase read i/o1 chip status1 pass: 0 fail: 1 pass/fail invalid i/o2 not used 0 or 1 invalid i/o3 not used 0 0 i/o4 not used 0 0 i/o5 not used 0 0 i/o6 ready/busy ready: 1 busy: 0 ready/busy ready/busy i/o7 not used 0 or 1 0 or 1 i/o8 write protect not protected :1 protected: 0 write protect write protect the pass/fail status on i/o1 is only valid during a program/erase operation when the device is in the ready state.
TC58NVM9S3ETA00 2010-05-21a 27 an application example with multiple de vices is shown in the figure below. system design note: if the by / ry pin signals from multiple devices are wired together as shown in the diagram, the status read function can be used to determine the status of each individual device. reset the reset mode stops all operations. for example, in ca se of a program or erase operation, the internally generated voltage is discharged to 0 volt and the device enters the wait state. the response to a ?ffh? reset co mmand input during the various device operations is as follows: when a reset (ffh) command is input during programming internal v pp 80 10 ff 00 by / ry t rst (max 10 s) device 1 cle 1 ce device 2 2 ce device 3 3 ce device n n ce device n + 1 1 n ce + ale we re by / ry we re status on device 1 70h 1 ce ale i/o 70h status on device n by / ry cle n ce busy i/o1 to i/o8
TC58NVM9S3ETA00 2010-05-21a 28 when a reset (ffh) command is input during erasing when a reset (ffh) command is input during read operation when a reset (ffh) command is input during ready when a status read command (70h) is input after a reset when two or more reset commands are input in succession 10 by / ry ff ff (3) (2) (1) the second command is invalid, but the third command is valid. ff ff ff i/o status : pass/fail pass : ready/busy ready ff 70 by / ry 00 ff 00 by / ry t rst (max 6 s) 30 internal erase voltage d0 ff 00 by / ry t rst (max 500 s) 00 by / ry t rst (max 6 s) ff
TC58NVM9S3ETA00 2010-05-21a 29 application notes and comments (1) power-on/off sequence: the timing sequence shown in the figure below is necessary for the power-on/off sequence. the device internal initialization starts after the powe r supply reaches an appropriate level in the power on sequence. during the initialization th e device ready/busy signal indicates the busy state as shown in the figure below. in this time period, the acceptable commands are ffh or 70h. the wp signal is useful for protecting against data corruption at power-on/off. (2) power-on reset the following sequence is necessary because some input signals may not be stable at power-on. (3) prohibition of unspecified commands the operation commands are listed in t able 3. input of a command other th an those specified in table 3 is prohibited. stored data may be co rrupted if an unknown command is entered during the command cycle. (4) restriction of commands while in the busy state during the busy state, do not in put any command except 70h and ffh. v il operation 0 v v cc 2.7 v 2.5v v il don?t care don?t care v ih ce , we , re wp cle, ale invalid don?t care ready/busy 1 ms max 100 s max ff reset power on
TC58NVM9S3ETA00 2010-05-21a 30 (5) acceptable commands after serial input command ?80h? once the serial input command ?80h ? has been input, do not input an y command other than the column address change in serial data input command ?85h?, auto program command ?10h?, or the reset command ?ffh?. if a command other than ?85h? , ?10h? or ?ffh? is in put, the program operation is not performed and the device operation is set to the mode which the input co mmand specifies. (6) addressing for program operation within a block, the pages must be programmed consecut ively from the lsb (least significant bit) page of the block to msb (most significant bit) page of the bl ock. random page address programming is prohibited. command other than ?85h?, ?10h? or ?ffh? 80 programming cannot be executed. 10 xx mode specified by the command. we by / ry 80 ff address input data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (1) (2) (3) (32) (64) data (64) from the lsb page to msb page data in: data (1) page 0 data register page 2 page 1 page 31 page 63 (2) (32) (3) (1) (64) data (64) ex.) random page program (prohibition)
TC58NVM9S3ETA00 2010-05-21a 31 (7) status read during a read operation the device status can be read out by inputting the status read command ?70h? in read mode. once the device has been set to status read mode by a ?70h ? command, the device will not return to read mode unless the read command ?00h? is inputted during [a]. if the read command ?00h? is inputted during [a], status read mode is reset, and the device returns to read mode. in this ca se, data output starts automatically from address n and address input is unnecessary (8) auto programming failure (9) by / ry : termination for the ready/busy pin ( by / ry ) a pull-up resistor needs to be used for termination because the by / ry buffer consists of an open drain circuit. fail 80 10 80 10 address m data input 70 i/o address n data input if the programming result for page address m is fail, do not try to program the page to address n in another block without the data input sequence. because the previous input data has been lost, the same input sequence of 80h command, address and data is necessary. 10 80 m n this data may vary fr om device to device. we recommend that you use this data as a reference when selecting a resistor value. v cc v cc device v ss r by / ry c l 1.5 s 1.0 s 0.5 s 0 1 k ? 4 k ? 3 k ? 2 k ? 15 ns 10 ns 5 ns t f t r r t r t f v cc = 3.3 v ta = 25c c l = 100 pf t f ready v cc t r busy 00 address n command ce we by / ry re [a] status read command input status read status output . 70 00 30
TC58NVM9S3ETA00 2010-05-21a 32 (10) note regarding the wp signal the erase and program operations are automatically reset when wp goes low. the operations are enabled and disabled as follows: enable programming disable programming enable erasing disable erasing wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din wp t ww (100 ns min) 80 10 we by / ry din wp t ww (100 ns min) 60 d0 we by / ry din
TC58NVM9S3ETA00 2010-05-21a 33 (11) when five address cycles are input although the device may read in a fifth address, it is ignored inside the chip. read operation program operation cle ce we ale i/o address input ignored 80h data input cle address input 00h ce we ale i/o by / ry ignored 30h
TC58NVM9S3ETA00 2010-05-21a 34 (12) several programming cycles on the same page (partial page program) each segment can be programme d individually as follows: data pattern 4 data pattern 1 all 1 s all 1 s all 1 s all 1 s 1st programming 2nd programming 4th programming result data pattern 1 data pattern 2 data pattern 4 data pattern 2
TC58NVM9S3ETA00 2010-05-21a 35 (13) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: please do not perform an erase op eration to bad blocks. it may be impossible to recover the bad block information if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the perfor mance of good blocks because it is isolated from the bit lines by select gates. the number of valid blocks over th e device lifetime is as follows: min typ. max unit valid (good) block number 502 ? 512 block bad block test flow regarding invalid blocks, bad block mark is in either the 1st or the 2nd page. * 1: no erase operation is allowed to detected bad blocks bad block bad block pass read check start bad block * 1 last block end yes fail block no = 1 no block no. = block no. + 1 read check : read either column 0 or 2048 of the 1st page or the 2nd page of each block. if the data of the column is not ff (hex), define the block as a bad block.
TC58NVM9S3ETA00 2010-05-21a 36 (14) failure phenomena for prog ram and erase operations the device may fail during a program or erase operation. the following possible failure modes should be consid ered when implementing a highly reliable system. failure mode detection and countermeasure sequence block erase failure status read after erase block replacement page programming failure status read after program block replacement single bit programming failure ?1 to 0? ecc ? ecc: error correction code. 1 bit correction per 512 bytes is necessary. ? block replacement program erase when an error occurs during an erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) do not turn off the power before write/erase operation is complete. avoid using th e device when the battery is low. power shortage and/or power failure before wr ite/erase operation is complete will cause loss of data and/or damage to data. when an error happens in block a, try to reprogram the data into another block (block b) by loading from an external buffer. then, prevent further system accesses to block a ( by creating a bad block table or by using another appropriate scheme). block a block b error occurs buffer memory
TC58NVM9S3ETA00 2010-05-21a 37 (16) reliability guidance this reliability guidance is intended to notify some guidance related to using nand flash with 1 bit ecc for each 512 bytes. for detailed reliability data, please refer to toshiba?s reliability note. although random bit errors may occur during use, it does not necessarily mean that a block is bad. generally, a block should be marked as bad when a progra m status failure or erase st atus failure is detected. the other failure modes may be recovered by a block erase. ecc treatment for read data is mandatory due to the following data retention and read disturb failures. ? write/erase endurance write/erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either an auto program or au to block erase operation. the cumula tive bad block count will increase along with the number of write/erase cycles. ? data retention the data in memory may change after a certain amount of storage time. this is due to charge loss or charge gain. after block erasure and reprogramming, the block may become usable again. here is the combined characteristics image of write/erase endurance and data retention. ? read disturb a read operation may disturb the data in memory. th e data may change due to charge gain. usually, bit errors occur on other pages in the block, not the page being read. after a large number of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. after block erasure and reprogramming, the block may become usable again. write/erase endurance [cycles] data retention [years]
TC58NVM9S3ETA00 2010-05-21a 38 package dimensions weight: 0.53g (typ.)
TC58NVM9S3ETA00 2010-05-21a 39 revision history date rev. description 2009-08-31 1.00 original version 2010-01-25 1.10 deleted an invalid description at page 20. deleted confidential notation. changed ?restrictions on product use?. 2010-05-21 1.20 corrected timing diagram of id read.
TC58NVM9S3ETA00 2010-05-21a 40 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (colle ctively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software a nd systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product's quality a nd reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situat ions in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, cu stomers must also refer to and comply with (a) the latest ve rsions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and applicat ion notes for product and the precautions and condi tions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be us ed with or for. customers are solely responsible for all aspe cts of their own product design or applications , including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) eval uating and determining the applicability of any info rmation contained in this document, or in c harts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operatin g parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specif ic applications as expre ssly stated in this document . product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for au tomobiles, trains, ships and other transportation, traffic s ignaling equipment, equipment used to control combustions or explosions, safety dev ices, elevators and escalators, devices related to el ectric power, and equipment used in finance-related fields. do not use product for unintended use unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is pres ented only as guidance for product use. no re sponsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, w hether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related soft ware or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manuf acturing of nuclear, chemical, or biological weapons or missi le technology products (mass destruction w eapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. expor t administration regulations. ex port and re-export of product or related software or technology are strictly prohibited exc ept in compliance with all applicable export laws and regulations. ? product is subject to foreign exchange and foreign trade control laws. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba a ssumes no liability for damages or losses occurring as a result o f noncompliance with applicable laws and regulations.

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