preliminary pci-express clock generato r cy28src02 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 001-00042 rev. *a revised june 30, 2005 features ? two 100-mhz differential src clocks ? low-voltage frequency select input ?i 2 c support with readback capabilities ? ideal lexmark spread spectrum profile for maximum electromagnetic interference (emi) reduction ? 3.3v power supply ? 20-pin tssop package block diagram pin configuration vss_src vdd_src srcc2 srct1 srcc1 vss_src vdd_src vdd_src sdata vdd_ref xin nc xout sclk 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 xtal pll ref freq xout xin osc sclk pll i 2 c logic sdata divider network iref vdd_src srct[2:1],srcc[2:1] srct2 vss_ref 20 tssop 9 10 11 12 vss_src iref vssa vdda
preliminary cy28src02 document #: 001-00042 rev. *a page 2 of 10 serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initialize to their default sett ing upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface ca nnot be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. for block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to st op after any complete byte has been transferred. for byte writ e and byte read operations, the system controller can access indi vidually indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 1 . the block write and block read protocol is outlined in table 2 while table 3 outlines the correspondi ng byte write and byte read protocol. the slave receiver address is 11010010 (d2h). pin description pin no. name type description 10 iref i a precision resistor (475 ? ) attached to this pin is connected to the internal current reference. 18 sclk i,pu smbus compatible sclock .this pin has an internal pull-up, but is tri-stated in power-down. 19 sdata i/o, pu smbus compatible sdata .this pin has an internal pull-up, but is tri-stated in power-down. 3, 4, 5, 6 src[t/c][2:1] o, dif differential selectable serial reference clocks . intel type-x buffer. 15 xin i 14.318-mhz crystal input 16 xout o 14.318-mhz crystal output 2, 8, 20 vdd_src pwr 3.3v power supply for src outputs 1, 7, 9 vss_src gnd ground for src outputs 12 vdda pwr 3.3v power supply for pll 11 vssa gnd analog ground 14 vdd_ref pwr power for xtal 13 vss_ref gnd ground for xtal 17 nc nc no connect table 1. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:5) chip select address, se t to ?00? to access device (4:0) byte offset for byte read or byte wr ite operation. for block read or block writ e operations, these bits should be '00000' table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 27:21 slave address ? 7 bits
preliminary cy28src02 document #: 001-00042 rev. *a page 3 of 10 control registers 36:29 data byte 1 ? 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2 ? 8 bits 37:30 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave ? 8 bits .... data byte n ? 8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave ? 8 bits .... stop 56 acknowledge .... data bytes from slave / acknowledge .... data byte n from slave ? 8 bits .... not acknowledge table 2. block read and block write protocol (continued) block write protocol block read protocol bit description bit description table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte ? 8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave ? 8 bits 38 not acknowledge 39 stop byte 0:control register 0 bit @pup name description 7 0 reserved reserved 6 1 src[t/c]4 src[t/c]4 output enable - only for cy28src04 0 = disable (hi-z), 1 = enable 5 1 src[t/c]3 src[t/c]3 output enable - only for cy28src04 0 = disable (hi-z), 1 = enable 4 1 src[t/c]2 src[t/c]2 output enable - only for cy28src02 and cy28src04 0 = disable (hi-z) 1 = enable 3 1 src[t/c]1 src[t/c]1 output enable - only for cy28src02 and cy28src04 0 = disable (hi-z), 1 = enable 2 1 src [t/c]0 src[t/c]0 output enable - only for cy28src01 0 = disable (hi-z), 1 = enable
preliminary cy28src02 document #: 001-00042 rev. *a page 4 of 10 1 0 reserved reserved 0 0 reserved reserved byte 1: control register 1 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 2: control register 2 bit @pup name description 7 1 srct/c spread spectrum selection ?0? = ?0.35% ?1? = ?0.50% 6 1 reserved reserved 5 1 reserved reserved 4 0 reserved reserved 3 1 reserved reserved 2 0 src src spread spectrum enable 0 = spread off, 1 = spread on 1 1 reserved reserved 0 1 reserved reserved byte 3: control register 3 bit @pup name description 7 1 reserved reserved 6 0 reserved reserved 5 1 reserved reserved 4 0 reserved reserved 3 1 reserved reserved 2 1 reserved reserved 1 1 reserved reserved 0 1 reserved reserved byte 0:control register 0 (continued) bit @pup name description byte 4: control register 4 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved
preliminary cy28src02 document #: 001-00042 rev. *a page 5 of 10 \ crystal recommendations the cy28src02 requires a parallel resonance crystal. substituting a series resonance crystal will cause the cy28src02 to operate at the wrong frequency and violate the ppm specification. for most a pplications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. 1 0 reserved reserved 0 1 reserved reserved byte 4: control register 4 (continued) bit @pup name description byte 5: control register 5 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 6: control register 6 bit @pup name description 7 0 test_sel ref/n or tri-state select 1 = ref/n clock, 0 = tri-state 6 0 test_mode test clo ck mode entry control 1 = ref/n or tri-state m ode, 0 = normal operation 5 0 reserved reserved 4 1 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 1 reserved reserved 0 1 reserved reserved byte 7: control register 7 bit @pup name description 7 0 revision code bit 3 6 0 revision code bit 2 5 1 revision code bit 1 4 1 revision code bit 0 3 1 vendor id bit 3 2 0 vendor id bit 2 1 0 vendor id bit 1 0 0 vendor id bit 0 table 4. crystal recommendations frequency (fund) cut loading load cap drive (max.) shunt cap (max.) tolerance (max.) stability (max.) aging (max.) 14.31818 mhz at parallel 12pf - 16pf 1 mw 7 pf + 50ppm + 50ppm 5 ppm
preliminary cy28src02 document #: 001-00042 rev. *a page 6 of 10 crystal loading crystal loading plays a critical role in achieving low ppm perfor- mance. to realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (cl). figure 1 shows a typical crystal configuration using the two trim capacitors. an important clarification for the following discussion is that the trim capa citors are in series with the crystal not parallel. it?s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. this is not true. calculating load capacitors in addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal load ing. as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitive loading on both sides. as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this mean the total capac- itance on each side of the cryst al must be twice the specified load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitance loading on both sides. use the following formulas to calculate the trim capacitor values for ce1 and ce2. cl ........................................... .........crystal load capacitance cle ............. .............. .............. actual loading seen by crystal using standard value trim capacitors ce ..................................................... external trim capacitors cs ........................................ ......stray capaci tance (terraced) ci .......................................................... internal capacitance (lead frame, bond wires etc.) figure 1. crystal capacitive clarification xtal ce2 ce1 cs1 cs2 x1 x2 ci1 ci2 clock chip trace 2.8pf trim 27pf pin 3 to 6p figure 2. crystal loading example load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 ( ) 1 = cle
preliminary cy28src02 document #: 001-00042 rev. *a page 7 of 10 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dda analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non functional ?65 +150 c t a temperature, operating ambient functional 0 70 c t j temperature, junction functional ? 150 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ? jc dissipation, junction to case mil-spec 883e method 1012.1 ? 20 c/w ? ja dissipation, junction to ambient jedec (jesd 51) ? 60 c/w ul-94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 multiple supplies : the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. dc electrical specifications parameter description condition min. max. unit vdd_src, vdda 3.3v operating voltage 3.3v 5% 3.135 3.465 v v ilsmbus input low voltage sdata, sclk ? 1.0 v v ihsmbus input high voltage sdata, sclk 2.2 ? v v il input low voltage v dd v ss ? 0.3 0.8 v v ih input high voltage 2.0 v dd + 0.3 v i il input leakage current except pull-ups or pull-downs 0 preliminary cy28src02 document #: 001-00042 rev. *a page 8 of 10 ac electrical specifications parameter description condition min. max. unit crystal t dc xin duty cycle the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within specification 47.5 52.5 % t period xin period when xin is dr iven from an external clock source 69.841 71.0 ns t r / t f xin rise and fall times measured between 0.3v dd and 0.7v dd ?10.0ns src t dc srct and srcc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz srct and srcc period measured at crossing point v ox 9.997001 10.00300 ns t periodss 100-mhz srct and srcc period, ssc measured at crossing point v ox 9.997001 10.05327 ns t periodabs 100-mhz srct and srcc absolute period measured at crossing point v ox 10.12800 9.872001 ns t periodssabs 100-mhz srct and srcc absolute period, ssc measured at crossing point v ox 9.872001 10.17827 ns t skew any srct/c to srct/c clock skew measured at crossing point v ox ? 250 ps t skew any srcs clock to any srcs clock skew measured at crossing point v ox - 250 ps t ccj srct/c cycle to cycle jitter measured at crossing point v ox ? 125 ps l acc srct/c long term accuracy measured at crossing point v ox ? 300 ppm t r / t f srct and srcc rise and fall times measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% ? t r rise timevariation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 3 660 850 mv v low voltage low math averages figure 3 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 3. measure se ? 0.2 v t ccj cycle to cycle jitter measurement at 1.5v ? 350 ps t ltj long term jitter measurement at 1.5v @ 1 s-tbdps
preliminary cy28src02 document #: 001-00042 rev. *a page 9 of 10 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. test and measurement set-up for differential src output signals the following diagram shows the test load configuration for the differential cpu and src outputs. purchase of i2c components from cypress or one of its sublicen sed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, prov ided that the system conforms to the i2c standard specification as defined by philips. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. 33? 33? 49.9? 49.9? measurem ent point 2pf 475? ir e f measurem ent point 2pf 100 ? 100 ? srct srcc figure 3. 0.7v load configuration ordering information part number package type product flow lead-free cy28srczxc-02 20-pin tssop commercial, 0 to 70 c CY28SRCZXC-02T 20-pin tssop?tape and reel commercial, 0 to 70 c package diagram 20 pin1id seating plane 1 bsc. bsc 0-8 plane gauge 6.40[0.252] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 6.60[0.260] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] dimensions in mm[inches] min. max. reference jedec mo-153 part # z20.173 standard pkg. zz20.173 lead free pkg. 20-lead thin shrunk small outline package (4.40-mm body) z20 51-85118-*a
preliminary cy28src02 document #: 001-00042 rev. *a page 10 of 10 document history page document title: cy28src02 pci-express clock generator document number: 001-00042 rev. ecn no. issue date orig. of change description of change ** 370534 see ecn rgl new data sheet *a 385834 see ecn rgl swapped pin 5 and 6
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