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- -1 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary 128mb ddr sdram module unbuffered 184pin dimm (16mx64 based on 16mx8 ddr sdram) revision 0.2 aug. 1999 64-bit non-ecc/parity
- 0 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary revision history revision 0 (aug 1998) 1. first release for internal usage revision 0.1 (may. 1999) 1. changed die revision from b-die to c-die 2. changed dc/ac characteristics item from old version revision 0.2 (aug. 1999) 1. changed die revision from c-die to b-die 2. modified binning policy from to -z (133mhz) -z (133mhz/266mbps@cl=2) -8 (125mhz) -y (133mhz/266mbps@cl=2.5) -0 (100mhz) -0 (100mhz/200mbps@cl=2) 3.modified the following ac spec values *1 : changed description method for the same functionality. this means no difference from the previous version. 4.changed the following ac parameter symbol from tdqck to tac output data access time from ck/ ck from. to. -z -0 -z -y -0 tac +/- 0.75ns +/- 1ns +/- 0.75ns +/- 0.75ns +/- 0.8ns tdqsck +/- 0.75ns +/- 1ns +/- 0.75ns +/- 0.75ns +/- 0.8ns tdqsq +/- 0.5ns +/- 0.75ns +/- 0.5ns +/- 0.5ns +/- 0.6ns tds/tdh 0.5 ns 0.75 ns 0.5 ns 0.5 ns 0.6 ns tcdlr *1 2.5tck-tdqss 2.5tck-tdqss 1tck 1tck 1tck tpre *1 1tck +/- 0.75ns 1tck +/- 1ns 0.9/1.1 tck 0.9/1.1 tck 0.9/1.1 tck trpst *1 tck/2 +/- 0.75ns tck/2 +/- 1ns 0.4/0.6 tck 0.4/0.6 tck 0.4/0.6 tck thzq *1 tck/2 +/- 0.75ns tck/2 +/- 1ns +/- 0.75ns +/- 0.75ns +/-0.8ns
- 1 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary ? performance range ? ? ? ? ? ? ? ? power supply vdd: 2.5v 0.2v power: g - normal, f - low power ? mrs cycle with address key programs cas latency (access from column address):2,2.5 burst length ;2, 4, 8 data scramble ;sequential & interleave ? serial presence detect with eeprom ? pcb : height 1450 (mil) , double sided component part no. max freq. interface kmm 368l1713bt -g(f)z 133mhz(7.5ns@cl=2) sstl_2 kmm 368l1713bt -g(f)y 133mhz(7.5ns@cl=2.5) kmm 368l1713bt -g(f)0 100mhz(10ns@cl=2) 2. feature 1. general description 4. pin description * these pins are not used in this module. pin name function a0 ~ a11 address input (multiplexed) ba0 ~ ba1 bank select address dq0 ~ dq63 data input/output dqs0 ~ dqs7 data strobe input/output ck0, ck0 ~ ck2, ck2 clock input cke0 clock enable input cs0 chip select input ras row address strobe cas column address strobe we write enable dm0 ~ dm7 data - in mask vdd power supply (2.5v) vddq power supply for dqs(2.5v) vss ground vref power supply for reference v33 serial eeprom power supply (3.3v) sda serial data i/o scl serial clock sa0 ~ 2 address in eeprom wp write protection vddid vdd identification flag du don ? t use nc no connection 3. pin configurations (front side/back side) pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 front vref dq0 vss dq1 dqs0 dq2 vdd dq3 nc nc vss dq8 dq9 dqs1 vddq ck0 /ck0 vss dq10 dq11 cke0 vddq dq16 dq17 dqs2 vss a9 dq18 a7 vddq dq19 pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 front a5 dq24 vss dq25 dqs3 a4 vdd dq26 dq27 a2 vss a1 *cb0 *cb1 vdd *dqs8 a0 *cb2 vss *cb3 ba1 dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 front vddq /we dq41 /cas vss dqs5 dq42 dq43 vdd nc dq48 dq49 vss /ck2 ck2 vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss wp sda scl pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 back vss dq4 dq5 vddq dm0 dq6 dq7 vss nc nc *a13 vddq dq12 dq13 dm1 vdd dq14 dq15 * cke1 vddq *ba2 dq20 *a12 vss dq21 a11 dm2 vdd dq22 a8 dq23 pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 back vss a6 dq28 dq29 vddq dm3 a3 dq30 vss dq31 *cb4 *cb5 vddq ck1 /ck1 vss *dm8 a10 *cb6 vddq *cb7 vss dq36 dq37 vdd dm4 dq38 dq39 vss dq44 pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 back /ras dq45 vddq /cs0 * /cs1 dm5 vss dq46 dq47 nc vddq dq52 dq53 nc vdd dm6 dq54 dq55 vddq nc dq60 dq61 vss dm7 dq62 dq63 vddq sa0 sa1 sa2 v33 samsung electronics co., ltd. reserves the right to change products and specifications without notice. key key kmm368l1713bt ddr sdram 184pin dimm 16mx64 ddr sdram 184pin dimm based on 16mx8 the samsung kmm368l1713bt is 16m bit x 64 double data rate sdram high density memory modules based on first gen of 128mb ddr sdram respectively. the samsung kmm368l1713bt consists of eight cmos 16m x 8 bit with 4banks double data rate sdrams in 66pin tsop- ii(400mil) packages mounted on a 184pin glass-epoxy sub- strate. four 0.1uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the kmm368l1713bt is dual in-line memory modules and inten- ded for mounting into 184pin edge connector sockets. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges of dqs. range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory sys- tem applications.
- 2 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary 5. functional block diagram dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0 i/o 5 i/o 4 i/o 3 i/o 2 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 i/o 5 i/o 4 i/o 3 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 i/o 5 i/o 4 i/o 3 i/o 2 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 i/o 5 i/o 4 i/o 3 i/o 2 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4 i/o 5 i/o 4 i/o 3 i/o 2 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 i/o 5 i/o 4 i/o 3 i/o 2 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 i/o 5 i/o 4 i/o 3 i/o 2 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 i/o 5 i/o 4 i/o 3 i/o 2 dm7 a0 - an a0-an: sdrams d0 - d7 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d7 cs 0 cs cs cs cs cs cs cs cs ba0 - ban ba0-ban: sdrams d0 - d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 2 wp dqs dqs dqs dqs v dd v ss d0 - d7 d0 - d7 v ddq d0 - d7 d0 - d7 vref notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/ cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. v ddid strap: see note 4 *clock net wiring card edge dram1 cap dram3 cap dram5 cap r=120 w *(cap) cap will replace dram3 *if two drams are loaded, dummy cap = 3.0pf * clock wiring clock input sdrams ck0/ ck0 ck1/ ck1 ck2/ ck2 3 sdrams+3*dummy cap 2 sdrams+3*dummy cap 3 sdrams+3*dummycap 47k w
- 3 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary 6. absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 4.6 v voltage on v ddq supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 8 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : 7. power & dc operating conditions (sstl_2 in/out) recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) note : parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 v i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref 1.15 1.35 v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.18 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.18 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v input leakage current i i -5 5 ua 3 output leakage current i oz -5 5 ua output high current (v out = 1.95v) i oh -15.2 ma output low current (v out = 0.35v) i ol 15.2 ma 1. typically, the value of v ref is expected to be about 0.5*v ddq of the transmitting device. v ref is expected to track variation in v ddq . 2. peak to peak ac noise on v ref may not exceed 2% v ref (dc). 3. v tt of the transmitting device must track v ref of the receiving device.
- 4 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary 8. dc characteristics recommended operating conditions unless otherwise noted, t a =0 to 70 c ) note : 1. measured with outputs open. 2. refresh period is 64ms parameter symbol test condition cas latency version unit note -z -y -0 operating current (one bank active) i dd1 burst=2 trc = trc(min), cl=2.5 i out =0ma, active-read-precharge t.b.d t.b.d t.b.d ma 1 precharge power-down standby current i dd2 p cke vil(max), tck=tck(min), all banks idle t.b.d ma precharge standby current in non power-down mode i dd2 n cke 3 vih(min), cs 3 vih(min), tck=tck(min) t.b.d ma active standby current in power-down mode i dd3 p all banks idle,cke vil(max),tck=tck(min) t.b.d ma active standby current in non power-down mode i dd3 n one bank; active-precharge, trc=tras(max), tck=tck(min) t.b.d ma operating current(read) i dd4r burst=2, tck=tck(min), i out =0ma 2.5 t.b.d t.b.d t.b.d ma 1 2 t.b.d t.b.d t.b.d operating current(write) i dd4w burst=2, tck=tck(min) 2.5 t.b.d t.b.d t.b.d ma 1 2 t.b.d t.b.d t.b.d auto refresh current i dd5 t rc 3 t rfc (min) t.b.d ma 2 self refresh current i dd6 cke 0.2v t.b.d ma 9. ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.35 v input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.35 v input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 note 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same.
- 5 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary 10. ac operating test conditions (v dd =3.3v, v ddq =2.5v, t a = 0 to 70 c ) parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate 1.0 v/ns input levels(v ih /v il ) v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit (fig. 1) output load circuit (sstl_2) output z0=50 w c load =30pf v ref =0.5*v ddq r t =50 w v tt =0.5*v ddq 11. input/output capacitance (v dd =3.3v, v ddq =2.5v, t a = 25 c , f=1mhz) parameter symbol min max unit input capacitance(a 0 ~ a 11 , ba 0 ~ ba 1 , ras , cas , we ) c in1 - 62 pf input capacitance(cke 0 ) c in2 - 62 pf input capacitance( cs 0 ) c in3 - 55 pf input capacitance( clk 0 , clk 1 , clk 2 ) c in4 - 27 pf data & dqs input/output capacitance(dq 0 ~dq 63 ) c out - 9 pf input capacitance(dm 0 ~dm 8 ) c in5 - 9 pf
- 6 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary 12. ac characteristics. (these ac charicteristics were tested on the component) parameter symbol - z(pc266@cl=2) - y(pc266@cl=2.5) - 0(pc200@cl=2) unit note min max min max min max row cycle time trc 65 65 70 ns refresh row cycle time trfc 75 75 80 ns row active time tras 45 12k 48 12k 48 12k ns ras to cas delay trcd 20 20 20 ns row precharge time trp 20 20 20 ns row active to row active delay trrd 15 15 15 ns write recovery time twr 2 2 2 tck last data in to read command tcdlr 1 1 1 tck last data in to write command tcdlw 0 0 0 tck col. address to col. address delay tccd 1 1 1 tck clock cycle time cl=2.0 tck 7.5 15 10 15 10 15 ns cl=2.5 7 15 7.5 15 8 15 ns clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ ck tac -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to ouput data edge tdqsq -0.5 +0.5 -0.5 +0.5 -0.6 +0.6 ns read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck data out high impedence time from ck/ ck thzq -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 2 ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 ns 3 dqs-in hold time twpreh 0.25 0.25 0.25 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time tis 1.1 1.1 1.2 ns address and control input hold time tih 1.1 1.1 1.2 ns mode register set cycle time tmrd 15 15 16 ns dq & dm setup time to dqs tds 0.5 0.5 0.6 ns dq & dm hold time to dqs tdh 0.5 0.5 0.6 ns dq & dm input pulse width tdipw 1.75 1.75 2 ns power down exit time tpdex 10 10 10 ns exit self refresh to write command txsw 95 116 ns
- 7 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary . 1. maximum burst refresh of 8 2. thzq transitions occurs in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. 3. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 4. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. parameter symbol pc266a pc266b pc200 unit note min max min max min max exit self refresh to bank active command txsa 75 75 80 ns exit self refresh to read command txsr 200 200 200 cycle refresh interval time 128mb tref 15.6 15.6 15.6 us 1 output dqs valid window tdv 0.35 0.35 0.35 tck dqs write postamble time twpst 0.25 0.25 0.25 tck 4 auto precharge write recovery + precharge time tdal 35 35 35 ns
- 8 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary 13. simplified truth table (v=valid, x=don ? t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dm ba 0,1 a 10 /ap a 11 a 9 ~ a 0 note register extended mrs h x l l l l x op code 1, 2 register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~a 7 ) 4 auto precharge enable h 4 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~a 7 ) 4 auto precharge enable h 4, 6 burst stop h x l h h l x x 7 precharge bank selection h x l l h l x v l x all banks x h 5 active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dm h x v x 8 no operation command h x h x x x x x l h h h 1. op code : operand code. a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2.emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). note :
- 9 - 184pin unbuffered ddr sdram module rev. 0.2 aug. 1999 kmm368l1713bt preliminary tolerances : 0.005(.13) unless otherwise specified. the used device is 16mx8 sdram, tsop. sdram part no : km48l16031bt 14. package dimensions 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.145 max 0.050 0.0039 (1.270 0.10) 0 . 1 0 0 m i n ( 2 . 3 0 m i n ) 0 . 3 9 3 ( 1 0 . 0 0 ) (1.270 ) 0 . 1 0 0 ( 2 . 5 0 ) detail b a b 0.089 (2.26) (128.950) (133.350 0.15 ) 0.250 (6.350 ) detail a 0.157 (4.00 ) 0.071 (1.8 0) 0 . 1 5 7 ( 4 . 0 0 t y p ) (3.67 max) 0.039 0.002 (1.000 0. 050) (3.80) 2.175 (6.62) (64.77) (49.53) (19.80) ( 1 7 . 8 0 ) 2.55 1.95 0.78 0.26 2.500 0 . 7 0.10 m c b a 0.10 m c b a m 0.1496 (3.00) 0.118 (2.00) 0.0787 (4.00) 0.1575 1.45 0.006 (36.83 0.15)

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