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db14-000284-02 LSIFC949X dual channel fibre channel i/o processor technical manual november 2005 version 2.0
ii copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?er of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?er is prohibited. db14-000284-02, november 2005 this document describes the lsi logic corporation LSIFC949X dual channel fibre channel i/o processor and will remain the of?ial reference source for all revisions/releases of this product until rescinded by an update. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. trademark acknowledgment lsi logic, the lsi logic logo design, fusion-mpt, gigablaze, mystorage, and smarthpath are trademarks or registered trademarks of lsi logic corporation. arm is a registered trademark of arm ltd., used under license. all other brand and product names may be trademarks of their respective companies. db to receive product literature, visit us at http://www.lsilogic.com . for a current list of our distributors, sales of?es, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/index.html
LSIFC949X dual channel fibre channel i/o processor technical manual iii copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. preface this book is the primary reference and technical manual for the LSIFC949X dual channel fibre channel i/o processor. it contains a complete functional description for the LSIFC949X and includes complete physical and electrical speci?ations for the product. audience this document was prepared for logic designers and applications engineers and is intended to provide an overview of the lsi logic LSIFC949X and to explain how to use the LSIFC949X in the initial stages of system design. this document assumes that you have some familiarity with microprocessors and related support devices. the people who bene? from this book are ? engineers and managers who are evaluating the LSIFC949X for possible use in a system ? engineers who are designing the LSIFC949X into a system organization this document has the following chapters and appendixes: ? chapter 1, introduction , provides a general description of the LSIFC949X. ? chapter 2, fibre channel overview , brie? describes some key elements of fibre channel, including layers, topologies, and classes of service.
iv preface copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. ? chapter 3, LSIFC949X overview , provides an introduction to the basic features of the LSIFC949X, including the message interface, protocol assist engines, and support components. ? chapter 4, signal descriptions , lists and describes the signals on the LSIFC949X. ? chapter 5, pci-x functional description , describes the pci-x features contained in the LSIFC949X. ? chapter 6, registers, brie? describes the pci-x address space, the con?uration registers, and the host interface registers. ? chapter 7, speci?ations , describes the electrical speci?ations of the LSIFC949X and provides pinout information and packaging dimensions. ? appendix a, register summary , is a register summary. ? appendix b, reference speci?ations , lists several speci?ations and applicable world wide web urls that may bene? the reader. ? appendix c, glossary of terms and abbreviations , provides de?itions for terms and abbreviations used in this manual. related publications fusion-mpt message passing interface speci?ation, version 1.5, document no. db14-000174-03 pci local bus speci?ation, revision 2.3 pci-x addendum to the pci local bus speci?ation, revision 2.0 conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. signals that are active low end in a slash (??. hexadecimal numbers are indicated by the pre? ?xfor example, 0x32cf. binary numbers are indicated by the pre? ?bfor example, 0b0011.0010.1100.1111.
preface v copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. revision history document number date/version remarks db14-000284-02 november 2005 version 2.0 section 1.1.1 (page 1-8); modi?d ?mware support for concur- rent commands and concurrent logins. throughout document; changed hotswapen/ signal name to cpci_en/. table 4.1; added text to 64en/ and cpci_en/ description. table 4.3; rewrote description for ma[23:0] and added reference to sen #s11066, ?sifc949x design considerations. table 4.4; modi?d description of gpio[5:0], led[4:0]/, and mode[7:0]. chapter 6; added per-vector masking capable bit to msi mes- sage control register, modi?d msi enable bit description in msi message control register, added msi mask bits, msi pend- ing bits, msi-x capability id, msi-x next pointer, msi-x message control, msi-x table offset, and msi-x pba offset register descriptions. chapter 6; changed values in designed maximum cumulative read size and designed maximum split transactions bit ?lds of the pci-x status register. table 7.2; added maximum i ddc and i ddio speci?ations. modi?d table 7.9, ?ci bidirectional signals and table 7.11, ?sram read/write/read timings. replaced figure 7.4 with one-page top view. added alphanumeric pad listing tables (tables 7.14 and 7.15). various additional minor editorial changes throughout document. db14-000284-01 september 2004 version 0.6 updated to re?ct LSIFC949X support of pci local bus spec- i?ation, revision 2.3, and pci-x addendum to the pci local bus speci?ation, revision 2.0; added section 1.2.5, ?ncits t10 authorized dif, page 1-6 ; deleted the snooze control feature, pad name zz (bga pad number k3 becomes ?c?; changed bga pad numbers v3, aa13, ab13, ac13, af12, and ac25 to ?c? corrected bga pad number b19 to ?d[48]? corrected bga pad number p2 to ?xvss0? deleted section 6.3, ?hared memory? updated ?evice id designations on pages 6-4 and 6-5; made several changes to speci?ations on pages 7-2, 7-4, 7-5, and 7-6; changed mclk cycle time on pages 7-7 and 7-8; added separate designation for mxsvdd on pages 4-14 and 7-10; updated figure 7.5 to package code ?t, deleted section 7.4, ?ackage thermal considerations? and corrected several other minor typos throughout the document. db14-000284-00 june 2004 version 0.5 initial release.
vi preface copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
contents vii copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. contents chapter 1 introduction 1.1 overview 1-1 1.1.1 hardware features 1-1 1.1.2 fc features 1-2 1.1.3 software features 1-3 1.1.4 os support 1-3 1.1.5 targeted applications 1-3 1.2 general description 1-4 1.2.1 multifunction pci-x 1-5 1.2.2 autospeed negotiation 1-5 1.2.3 autotopology negotiation 1-5 1.2.4 failover and load balancing 1-6 1.2.5 incits t10 authorized dif 1-6 1.3 hardware overview 1-6 1.3.1 pci/pci-x interface 1-7 1.3.2 32-bit memory controller 1-7 1.3.3 i/o processor 1-7 1.3.4 system interface 1-8 1.3.5 integrated 4 gbit/s transceivers 1-8 1.3.6 link controllers 1-8 1.3.7 datapath 1-8 1.3.8 context managers 1-8 1.4 initiator operations 1-9 1.5 target operations 1-9 1.6 diagnostics 1-9
viii contents copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 2 fibre channel overview 2.1 introduction 2-1 2.2 fc layers 2-2 2.3 frames 2-3 2.4 exchanges 2-4 2.5 fc ports 2-7 2.6 fc topologies 2-7 2.6.1 point-to-point topology 2-8 2.6.2 fabric topology 2-8 2.6.3 arbitrated loop topology 2-8 2.7 classes of service 2-9 chapter 3 LSIFC949X overview 3.1 introduction 3-1 3.2 message interface 3-3 3.2.1 messages 3-3 3.2.2 message flow 3-4 3.3 scsi message 3-6 3.4 target message 3-6 3.5 support components 3-7 3.5.1 ssram memory 3-7 3.5.2 flash rom 3-8 3.5.3 serial eeprom 3-8 chapter 4 signal descriptions 4.1 pci/pci-x interface 4-3 4.2 fibre channel interface 4-6 4.3 memory interface 4-9 4.4 con?uration and miscellaneous 4-11 4.5 test and i/o processor debug 4-13 4.6 power and ground 4-15
contents ix copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 5 pci-x functional description 5.1 overview 5-1 5.2 pci-x addressing 5-2 5.2.1 pci con?uration space 5-2 5.2.2 pci i/o space 5-2 5.2.3 pci memory space 5-3 5.3 pci/pci-x bus commands and implementation 5-3 5.3.1 interrupt acknowledge command 5-4 5.3.2 special cycle command 5-4 5.3.3 i/o read command 5-4 5.3.4 i/o write command 5-5 5.3.5 memory read command 5-5 5.3.6 memory read dword command 5-5 5.3.7 memory write command 5-5 5.3.8 alias to memory read block command 5-5 5.3.9 alias to memory write block command 5-6 5.3.10 con?uration read command 5-6 5.3.11 con?uration write command 5-6 5.3.12 memory read multiple command 5-6 5.3.13 split completion command 5-7 5.3.14 dual address cycles (dac) command 5-7 5.3.15 memory read line command 5-7 5.3.16 memory read block command 5-8 5.3.17 memory write and invalidate command 5-8 5.3.18 memory write block command 5-9 5.4 pci arbitration 5-9 5.5 pci cache mode 5-9 chapter 6 registers 6.1 pci-x con?uration space register description 6-1 6.2 pci i/o space and memory space register description 6-32
x contents copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 7 speci?ations 7.1 electrical requirements 7-1 7.2 ac timing 7-4 7.2.1 pci/pci-x interface timings 7-5 7.2.2 fibre channel interface timings 7-5 7.2.3 memory interface timings 7-5 7.3 packaging 7-9 appendix a register summary appendix b reference speci?ations appendix c glossary of terms and abbreviations index customer feedback
contents xi copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figures 1.1 LSIFC949X typical implementation 1-5 1.2 LSIFC949X functional block diagram 1-7 2.1 fc layers 2-2 2.2 link control frame 2-3 2.3 data frame 2-3 2.4 exchange to character 2-5 2.5 fcp exchange 2-6 2.6 write event trellis 2-7 2.7 point-to-point topology 2-8 2.8 fabric topology 2-8 2.9 arbitrated loop topology 2-9 3.1 LSIFC949X block diagram 3-2 3.2 LSIFC949X message flow 3-5 3.3 LSIFC949X typical implementation 3-7 4.1 LSIFC949X functional signal grouping 4-2 7.1 ssram read/write/read timing waveforms 7-6 7.2 flash rom read timing waveforms 7-7 7.3 flash rom write timing waveforms 7-8 7.4 LSIFC949X 544-pin fpbga top view 7-9 7.5 LSIFC949X 544-pad fpbga mechanical drawing 7-14
xii contents copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
contents xiii copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. tables 4.1 pci/pci-x interface 4-3 4.2 fibre channel interface 4-6 4.3 memory interface 4-9 4.4 con?uration and miscellaneous 4-12 4.5 test and i/o processor debug 4-14 4.6 power and ground 4-15 5.1 pci/pci-x bus commands and encodings 5-3 6.1 LSIFC949X pci-x con?uration space address map 6-2 6.2 device id values 6-3 6.3 multiple message enable field bit encoding 6-23 6.4 bir field de?itions 6-27 6.5 maximum outstanding split transactions 6-29 6.6 maximum memory read count 6-30 6.7 pci i/o space address map 6-33 6.8 pci memory [0] address map 6-34 6.9 pci memory [1] address map 6-34 6.10 interrupt signal routing 6-41 7.1 absolute maximum stress ratings 7-1 7.2 operating conditions 7-2 7.3 capacitance 7-2 7.4 input signals (fault1/, fault0/, mode[7:0], switch, cpci_en/) 7-2 7.5 schmitt input signals (refclk, tck, tdi, trst/, tms_chip, tms_ice) 7-3 7.6 4 ma bidirectional signals (lipreset/, odis1, odis0, bypass1/, bypass0/, md[31:0], ma[23:0], mwe[1:0]/, flashcs/, bwe[3:0]/, ramcs/, mp[3:0], scl, sda, rxlos1, rxlos0, adsc/, adv/, tdo) 7-3 7.7 8 ma bidirectional signals (moddef1[2:0], moddef0[2:0], gpio[5:0], moe[1:0]/, led[4:0]/, mclk) 7-3 7.8 pci input signals (pciclk, gnt/, idsel, rst/) 7-4 7.9 pci bidirectional signals (ad[63:0], c_be[7:0]/, frame/, irdy/, trdy/, stop/, perr/, par, ack64/, enum/, 64en/) 7-4 7.10 pci output signals (par64, req/, req64/, devsel/, serr/, inta/, intb/) 7-4 7.11 ssram read/write/read timings 7-6
xiv contents copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 7.12 flash rom read timings 7-7 7.13 flash rom write timings 7-8 7.14 alphanumeric pad listing by pbga position 7-10 7.15 alphanumeric pad listing by signal name 7-12 a.1 LSIFC949X multifunction pci registers a-1 a.2 LSIFC949X host interface registers a-3 b.1 reference speci?ations b-1
LSIFC949X dual channel fibre channel i/o processor technical manual 1-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 1 introduction this chapter provides an overview of the LSIFC949X dual channel fibre channel i/o processor. the chapter contains the following sections: ? section 1.1, ?verview ? section 1.2, ?eneral description ? section 1.3, ?ardware overview ? section 1.4, ?nitiator operations ? section 1.5, ?arget operations ? section 1.6, ?iagnostics 1.1 overview the LSIFC949X is a high-performance, cost-effective, dual channel fibre channel (fc) i/o processor. it represents the latest system level integration technology in intelligent i/o processors from lsi logic. the storage area network (san) environment is fully supported with fibre channel protocol (fcp) for scsi. 1.1.1 hardware features the LSIFC949X supports the following list of hardware features: ? highly integrated, full duplex, dual channel fc i/o processor ? integrated 4 gbit/s dual channel fc serial link ? 64-bit/66 mhz host pci bus and 133 mhz pci-x bus (both are backward compatible with 32-bit/33 mhz) ? 32-bit arm risc processor ? intelligent, high-performance context management
1-2 introduction copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. ? integrated bit error rate (ber) testing (with special test utilities) ? synchronous sram (ssram) external memory interface ? full simultaneous target and initiator operations ? implementation of common message passing interface (mpi) ? firmware support for concurrent host commands 128 concurrent commands with internal sram only 1000 concurrent commands with 1 mbyte sram 4000 concurrent commands with 4 mbytes sram ? firmware support for concurrent logins 32 concurrent logins with internal sram only 256 concurrent logins with 1 mbyte sram 2048 concurrent logins with 4 mbytes sram ? pc2001 compliant ? peripheral component interface (pci), revision 2.3 compliant ? jtag debug interface ? 544-pin flip chip plastic ball grid array (fpbga) 1.1.2 fc features the LSIFC949X supports the following list of fc features: ? bb credit of 16, alternate login of 1 (each channel) ? up to 126 alias addresses (alpas) ? class 3 connectionless service ? fc-ph compliance ? fc-al 7.0 compliance ? fc-fcp, fc-plda compliance ? fc-fla compliance ? fca-ip, ietf-ipfc compliance ? nl_port (arbitrated loop) ? n_port (point-to-point)
overview 1-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. ? fl_port (public loop attach) ? f_port (fabric attach) ? autonegotiation between link speeds under ?mware control; provides automatic interoperability between 1 gbit/s, 2 gbit/s and 4 gbit/s links (independent for each channel) ? autotopology negotiation enables automatic interoperability of each LSIFC949X port to the current port type 1.1.3 software features the LSIFC949X supports the following list of software features: ? fusion-mpt drivers ? optimum server i/o pro?e with low cpu utilization ? optimum workstation i/o pro?e with maximum i/o performance ? diagnostic capability ? host driver support for failover and load balancing ? san storage management ? mystorage and smartpath support 1.1.4 os support the LSIFC949X supports the following list of operating systems: ? windows 2000, windows server 2003 ? windows xp ? solaris x86 ? solaris sparc ? suse and red hat linux 1.1.5 targeted applications the LSIFC949X targets the following list of key applications: ? sans ? storage virtualization
1-4 introduction copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. ? server clustering environments ? embedded raid ? host main boards ? routers and bridges 1.2 general description the LSIFC949X dual channel fc i/o processor is a high-performance, intelligent i/o processor (iop) that simultaneously supports mass storage and ip protocols on a full duplex 1 gbit/s, 2 gbit/s, or 4 gbit/s fc link. the sophisticated design and local memory architecture work together to reduce the host cpu and pci bandwidth required to support fc i/o operations. from the host cpu perspective, the LSIFC949X manages the fc link at the exchange level for mass storage (fcp) protocols. the LSIFC949X supports multiple i/o requests per host interrupt in most applications. from the fc link perspective, the LSIFC949X is a highly ef?ient nl_port supporting point-to-point topologies, public and private loop topologies, and the fc switch/attach topology de?ed under the ansi x3t11 fc-fs standard. the LSIFC949X uniquely supports fc environments where independent, full duplex transmission is required for maximum fc link ef?iency. special attention has been given to the design to accelerate context switching and link utilization. the LSIFC949X includes a 64-bit, 66 mhz host pci interface and a 133 mhz pci-x interface to the host environment. the host interface minimizes the amount of time spent on the pci bus for nondata moving activities such as initialization, command, and error recovery. in addition, the host interface has inherent ?xibility to support the oem implementation tradeoffs between cpu, pci-x, and i/o bandwidth. the high level of integration in the LSIFC949X controller enables low cost fc implementations. figure 1.1 shows a typical implementation incorporating the LSIFC949X controller.
general description 1-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 1.1 LSIFC949X typical implementation 1.2.1 multifunction pci-x coupled with the dual channel operation, the LSIFC949X adds multifunction capability on the pci-x bus. this capability allows the host to see two distinct ?hannels or host adapters. each channel provides full, concurrent support for fcp initiator and target protocols. 1.2.2 autospeed negotiation backward compatibility with 1 gbit/s and 2 gbit/s fc devices is maintained through autospeed negotiation. after a power-on, loss of signal, or loss of word synchronization for longer than the r_t_tov time-out, the LSIFC949X performs this operation to determine whether a point-to-point device or all of the devices on a link are either 1, 2, or 4 gbit/s devices, and it automatically con?ures itself to be compatible with the devices on the link. 1.2.3 autotopology negotiation the LSIFC949X maintains compatibility with private loop, public loop, and point-to-point topologies through autotopology negotiation. the LSIFC949X performs this operation to determine the type of attached link, and automatically con?ures each LSIFC949X port to the current port type. LSIFC949X integrated transceiver memory controller 2 2 serial eeprom (8 kbyte min.) flash rom (1 mbyte) ssram (1 mbyte min.) clock (106.25 mhz) 32 pci-x bus 32/64 integrated transceiver 2 2 fc channel 0 fc channel 1 support components
1-6 introduction copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 1.2.4 failover and load balancing the LSIFC949X supports two pci-x functions and two fc ports, which improves performance and provides a redundant path in high-availability systems that require failover capabilities. in case of a link failure, the LSIFC949X architecture allows the os driver to support automatic failover without the need for LSIFC949X intervention. load balancing also can be provided in the host driver to partition the i/o workload across each channel of the LSIFC949X. 1.2.5 incits t10 authorized dif the LSIFC949X uses the new international committee for information technology standards (incits) t10 authorized data integrity field (dif) for additional end-to-end data protection. the LSIFC949X provides extended data protection by appending the dif to block level data, allowing integrity checks at each node of a system for enhanced data integrity and debug capability. 1.3 hardware overview in todays fast growing san, storage virtualization, server/workstation, and raid storage systems marketplaces, higher levels of performance, scalability, and reliability are required to stay competitive. the LSIFC949X provides the performance and ?xibility to meet future fc connectivity requirements. the LSIFC949X and lsi logic software drivers provide superior performance and lower host cpu overhead than other competitive solutions. because of its high level of integration and streamlined architecture, the LSIFC949X provides the highest level of performance in a more cost effective fc solution. figure 1.2 shows the functional block diagram for the LSIFC949X. the architecture maximizes performance and ?xibility by deploying ?ed gates in critical performance areas and utilizing multiple arm risc processors (two for context management and one for the i/o processor). each of the major blocks is described brie?.
hardware overview 1-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 1.2 LSIFC949X functional block diagram 1.3.1 pci/pci-x interface the LSIFC949X uses a 64-bit (33 mhz, 66 mhz, or 133 mhz) pci/pci-x interface or a 32-bit (33 mhz, 66 mhz, or 133 mhz) pci/pci-x interface. in addition, support is provided for dual address cycle (dac), pci-x power management, subsystem vendor id, vendor product data (vpd), and message signaled interrupt (msi and msi-x) and data integrity field (dif). 1.3.2 32-bit memory controller the memory controller provides access to flash rom and 32-bit synchronous sram. it supports both interleaved and noninterleaved con?urations up to a maximum of 4 mbytes of synchronous sram. a general purpose memory expansion bus supports up to 1 mbyte of flash rom. 1.3.3 i/o processor the LSIFC949X uses a 32-bit arm risc processor to control all system interface and message transport functionality. this frees the host cpu for other processing activity and improves overall i/o performance. the risc processor and associated ?mware can manage an i/o from start to ?ish without host intervention. the risc processor also manages the message passing interface. LSIFC949X i/o processor fc xcvr ssram 400 mbps 64-bit 133 mhz pci-x 32-bit memory controller pci-x interface 4 gbit/s fc 400 mbps 4 gbit/s fc xmtr context rcvr link system interface fc xcvr xmtr context rcvr controller link controller
1-8 introduction copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 1.3.4 system interface the system interface ef?iently passes messages between the LSIFC949X and other i/o agents. it consists of ?e hardware fifos for the message queuing lists: request free, request post, reply free, reply post, and high priority request. control logic for the fifos is provided within the LSIFC949X system interface with messages stored in external memory. 1.3.5 integrated 4 gbit/s transceivers the LSIFC949X implements gigablaze 4 gbit/s transceivers. gigablaze is backward-compatible with 2 gbit/s and 1 gbit/s systems, using a rmware-implemented ?utospeed negotiation for automatic compatibility between 1 gbit/s, 2 gbit/s, and 4 gbit/s links. the integrated 4 gbit/s transceivers provide a fc-compliant physical interface for cost conscious and real estate limited applications. 1.3.6 link controllers the integrated link controller is fc-al-2 (rev. 7.0) compatible and performs all link operations. the controller monitors the link state and strictly adheres to the loop port state machine, ensuring maximum system interoperability. the link controller interfaces to the integrated transceiver. 1.3.7 datapath the transmitter builds sequences based on context information and transmits resulting frames to the fc link using the link controller. each transmitter includes three 2 kbyte buffers to support frame payloads. the receivers accept frame data from the link controller and dmas the encapsulated information to local or system memory. each receiver contains sixteen 2112-byte buffers that support a bb credit of up to sixteen or an alternate login bb credit of 1 on each channel. 1.3.8 context managers the LSIFC949X uses an arm risc processor in each channel to support i/o context swap to external memory and fcp management for both initiator and target applications. context operations include support
initiator operations 1-9 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. for transmit and resource queue management, as well as scatter/gather list management. 1.4 initiator operations the LSIFC949X autonomously handles fcp exchanges upon request from the host. the LSIFC949X generates appropriate sequences and frames necessary to complete the request and provides feedback to the host on the status of the request. 1.5 target operations the LSIFC949X provides for general purpose target functions such as those required for front-end raid applications. 1.6 diagnostics the LSIFC949X provides the capabilities to do a simpli?d ?ink check ber test on the link for diagnostic purposes. in a special test mode the controller can transmit and verify a programmed data pattern for link evaluation.
1-10 introduction copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
LSIFC949X dual channel fibre channel i/o processor technical manual 2-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 2 fibre channel overview this chapter provides general overview information on fibre channel (fc). the chapter contains the following sections: ? section 2.1, ?ntroduction ? section 2.2, ?c layers ? section 2.3, ?rames ? section 2.4, ?xchanges ? section 2.5, ?c ports ? section 2.6, ?c topologies ? section 2.7, ?lasses of service 2.1 introduction fc is a high-performance, hybrid interface. it is both a channel and a network interface that contains network features to provide the required connectivity, distance, protocol multiplexing, as well as traditional channel features to retain the required simplicity, repeatable performance, and guaranteed delivery. popular industry standard networking protocols such as internet protocol (ip) and channel protocols such as small computer system interface (scsi) have been mapped to the fc standard. the fc structure is de?ed by ?e functional layers. these layers, shown in figure 2.1 , de?e the physical media and transmission rates, encoding scheme, framing protocol and ?w control, common services, and the upper level protocol (ulp) interfaces.
2-2 fibre channel overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 2.1 fc layers 2.2 fc layers the lowest layer, fc-0, is the media interface layer. it de?es the physical characteristics of the interface. it includes transceivers, copper-to-optical transducers, connectors, and any other associated circuitry necessary to transmit or receive at 1062 or greater mbit/s rates over copper or optical cable. the fc-1 layer de?es the 8b/10b encoding/decoding scheme, the transmission protocol necessary to integrate the data and transmit clock, and the receive clock recovery. implementation of this layer is usually divided between the hardware implementing the fc-0 layer in a transceiver, and the protocol device that implements the fc-2 layer. speci?ally, the fc-0 transceivers can include the clock recovery circuitry while the 8b/10b encoding/decoding is provided in the protocol device. the fc-2 layer de?es the rules for the signaling protocol and describes transfer of the frames, sequences, and exchanges. the meaning of the data being transmitted or received is transparent to the fc-2 layer. however, the context between any given set of frames is maintained at the fc-2 layer through the sequence and exchange constructs. the ip escon hippi ipi-3 fcp 8496 4248 2124 1062 upper layer protocol (ulp) common services ?for example, ...striping (not de?ed) framing protocol/flow control 8b/10b encode/decode system interface fc-4 fc-3 fc-2 fc-1 fc-0 mbits/s (full duplex) fc-ph-2 mbytes/s 100 200 400 800 behaviors logical layers physical layers
frames 2-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. framing protocol creates the constructs necessary to form frames with the data being packetized within the payload of each frame. the fc-3 layer provides common services that span multiple n_ports. some of these services include striping, hunt groups, and multicasting. all of these services allow a single port or fabric to communicate to several n_ports at one time (refer to section 2.6, ?c topologies, on page 2-7 for details). the fc-4 layer is the top layer de?ed in the fc. the fc-4 layer provides a seamless integration of existing standards. it speci?s the mapping of ulps to the layers below. some of these ulps include scsi and ip. each of these ulps is de?ed in its own ansi document. 2.3 frames there are two types of frames used in fc: link control frames and data frames. link control frames, which contain no payload, are ?w control responses to data frames. an example of a link control frame is the ack frame ( figure 2.2 ). figure 2.2 link control frame a data frame is any frame that contains data in the payload ?ld. an example of a data frame is the login frame ( figure 2.3 ). figure 2.3 data frame in fc, an ordered set is a group of four 10-bit characters that provide low level link functions, such as frame demarcation and signaling start of frame (4 bytes) frame header (24 bytes) crc (4 bytes) end of frame (4 bytes) start of frame (4 bytes) frame header (24 bytes) crc (4 bytes) end of frame (4 bytes) data field (optional headers payload ) (0 to 2112 bytes) and
2-4 fibre channel overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. between two ends of a link. all frames start with a start-of-frame (sof) and end with an end-of-frame (eof) ordered set. each frame contains at least a 24-byte header de?ing such things as destination and source id, class of service and type of frame (for example, fcp or fc-le). the biggest ?ld within a frame can be the payload ?ld. if the frame is a link control frame, then there is no payload. if it is a data frame, then the frame contains a payload ?ld of up to 2112 bytes. finally, the frame includes a crc ?ld used for detection of transmission errors, followed by the eof ordered set. 2.4 exchanges figure 2.4 outlines the fc hierarchical data structures. at the most elemental level, four 8b/10b encoded characters make up an fc word. an fc frame is a collection of fc words. an fc sequence is made up of one or more frames, and a fc exchange is made up of one or more sequences.
exchanges 2-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 2.4 exchange to character the following discussion illustrates an exchange by considering a typical parallel scsi i/o. in parallel scsi, several phases make up the i/o. these phases include command, data, message, and status. using the fcp for the scsi ulp, these phases can be mapped into the other lower fc layers. figure 2.5 shows the components that make up the fcp exchange. seq 1 seq 2 seq 4 seq n exchange frame 1 frame 2 frame 4 frame n seq 3 frame 3 sof header data crc eof frame k28.5 d21.5 d23.0 word d23.0 0 character 0 1 1 1 1 1 0 1 0
2-6 fibre channel overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 2.5 fcp exchange figure 2.6 shows how the exchange ?ws between the initiator and target. the initiator starts the fcp exchange by sending a command sequence containing one frame to the target. the frame payload contains the command descriptor block (cdb). the target then responds with a data delivery request sequence containing one frame. the payload of this frame contains a xfer_rdy response. when the initiator receives the targets response, it begins to send the data sequence(s), which may contain one or more frames. this is analogous to parallel scsi data_out phase. when the target has received the last frame of the data sequence(s), it sends a response sequence containing one frame to the initiator, thus concluding the fcp exchange. cmdseq datareqseq fcp exchange frame 1 frame 2 frame n frame 1 responseseq dataseq frame 1 frame 1
fc ports 2-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 2.6 write event trellis 2.5 fc ports fc devices are called nodes. each node has at least one port to provide access to other ports in other nodes. the ?ort is the hardware entity within a node that performs data communications over the fc link. various types of ports are de?ed within the fc standard, based on the location of the port and the topology associated with it. the most commonly used ports are n_ports, nl_ports, f_ports, and fl_ports. these types of ports appear in figure 2.7 , figure 2.8, and figure 2.9 . 2.6 fc topologies topologies are de?ed, based on the capability and the presence or absence of fabric between the n_ports: ? point-to-point topology ? fabric topology ? arbitrated loop topology fc-ph protocols are topology-independent. attributes of a fabric may restrict operation to certain communication models. initiator fabric cmd seq data seq frame 1 data seq frame 2 data seq frame n data req seq rsp seq target
2-8 fibre channel overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 2.6.1 point-to-point topology the topology shown in figure 2.7 , in which communication between n_ports occurs without the use of fabric, is de?ed as point-to-point. figure 2.7 point-to-point topology 2.6.2 fabric topology figure 2.8 illustrates multiple n_ports interconnected by a fabric. this topology uses the destination_identi?r (d_id) embedded in the frame header to route the frame through a fabric to the desired destination n_port. figure 2.8 fabric topology 2.6.3 arbitrated loop topology the arbitrated loop topology permits between 2 and 127 l_ports to communicate without the use of a fabric, as in fabric topology. the arbitrated loop supports a maximum of one point-to-point circuit at a time. when two l_ports are communicating, the arbitrated loop topology supports simultaneous, symmetrical bidirectional ?w. figure 2.9 illustrates two independent arbitrated loop configurations, each with multiple l_ports attached. each line in the figure between l_ports represents a single fibre. the lower configuration shows an arbitrated loop composed of three nl_ports and one fl_port (a public loop). n_port b n_port a fabric f_port n_port n_port f_port n_port f_port f_port n_port
classes of service 2-9 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 2.9 arbitrated loop topology 2.7 classes of service there are several classes of service in fc. the different classes are distinguished from each other in three ways: by the level of guarantee for data being delivered, the order in which data is delivered, and how data ?w control is maintained. class 1 is a dedicated connection between two n_ports. the data delivered is guaranteed with a required acknowledgement frame (ack), which a class 1 device uses for ow control. all frames are received in order. class 2 is a connectionless class. the data delivered is guaranteed with an ack frame. the frames can be received out of order. class 2 uses both ack frames and the r_rdy ordered set for ow control. class 3 is also a connectionless class (the data being delivered is not guaranteed). the frames can be received out of order. class 3 uses only the r_rdy ordered set for ow control. nl_port nl_port nl_port nl_port private loop fabric element fl_port nl_port nl_port nl_port public loop
2-10 fibre channel overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. intermix is an enhancement of class 1 service. a dedicated class 1 connection may waste fabric bandwidth while frames are not being transmitted or received between two n_ports. to recover some of this bandwidth, intermix allows class 2 and class 3 frames to be transmitted/received between class 1 frames. n_ports advertising intermix capability must be capable of receiving class 2 and class 3 frames from other n_ports while maintaining the original class 1 link.
LSIFC949X dual channel fibre channel i/o processor technical manual 3-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 3 LSIFC949X overview this chapter provides a general description of the LSIFC949X dual channel fibre channel i/o processor ?mware. the chapter contains the following sections: ? section 3.1, ?ntroduction ? section 3.2, ?essage interface ? section 3.3, ?csi message ? section 3.4, ?arget message ? section 3.5, ?upport components 3.1 introduction the lsi logic LSIFC949X connects a host to a high-speed fc link. the fcp ansi standard, fc private loop direct attach, and fabric loop attach profiles are supported with a sophisticated firmware implementation. all profiles, specifications, and interoperability maintained by the LSIFC949X are listed in appendix b, ?eference specifications. although optimized for a 64-bit pci-x interface to communicate with the system cpu(s) and memory, the LSIFC949X also supports a 32-bit peripheral component interface (pci) environment. the system interface to the LSIFC949X minimizes the amount of pci-x bandwidth required to support i/o requests. a packetized message passing interface reduces the number of single cycle pci bus cycles. all fc data traf? on the pci-x bus occurs with zero wait state bursts across the pci-x bus.
3-2 LSIFC949X overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. the intelligent LSIFC949X architecture allows the system to specify i/os at the command level. the LSIFC949X manages i/os at the frame, sequence and exchange level. error detection and i/o retries are also handled by the LSIFC949X, allowing the system to of?ad part of the exception handling work from the system driver. data flows the LSIFC949X uses a 64-bit (33 mhz, 66 mhz, or 133 mhz) pci-x interface to pass control and data information between the system and the protocol controller. this interface is managed by the pci-x interface block, as shown in figure 3.1 . it is backward compatible with 32-bit/33 or 66 mhz buses. figure 3.1 LSIFC949X block diagram for incoming serial data, the physical link transfers the data to link control using the gigablaze integrated transceiver. the link controller analyzes the received frame, and if appropriate, it passes the frame to the receiver. the receiver strips off the frame header and places it in a separate header buffer while the data in the frame payload is placed in a data buffer. the frame receiver uses the receive context manager to manage the order and priority of the received frame. the data contained in the receiver buffers is associated with a specific scatter/gather entry and passed on to the pci-x interface. the data also requests the pci-x bus and bursts the data into system memory. the i/o processor (iop), with its ?mware, provides the translation from fc speci? protocols to the high level block storage and scsi message interface. this translation allows the LSIFC949X to be integrated into the system as if it were a native parallel scsi device, hiding all fc-unique i/o processor fc xcvr ssram 400 mbps 64-bit 133 mhz pci-x 32-bit memory controller external pci-x interface 64-bit 4 gbit/s fc 400 mbps 4 gbit/s fc xmtr context rcvr link system interface fc xcvr xmtr context rcvr link
message interface 3-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. characteristics. internal communication between the iop and the context manager occurs over an internal bus, which also is connected to an external memory controller. the iop uses the external memory controller to access local memory. this memory contains the ?mware, as well as the dynamic data structures used by the ?mware. 3.2 message interface the LSIFC949X system interface is a high-performance, packetized, mailbox architecture that leverages the intelligence in the LSIFC949X to minimize traf? on the pci-x bus. the fusion-mpt architecture also provides a high priority request fifo to provide high priority request free messages to the host on reads, and to accept high priority request post messages from the host on writes. the high priority request post fifo is similar to the request post fifo, except that the LSIFC949X processes requests from the high priority request post fifo before processing requests from the request post fifo. this high-priority queue has dedicated resources which do not become depleted when the request queue gets full. there are two basic constructs in the message interface. the ?st construct, the message, communicates between the system and the LSIFC949X. messages are moved between the system(s) and the LSIFC949X using the second construct, a transport mechanism. 3.2.1 messages the LSIFC949X uses two types of messages to communicate with the system. request messages are created by the system to ?equest an action by the LSIFC949X. reply messages are used by the LSIFC949X to send status information back to the system. request message data structures are up to 128 bytes in length. the message includes a message header and a payload. the header includes information to uniquely identify the message. the payload is speci? to the request itself, and is unique for scsi and target messages. for more information regarding the details of the message format, refer to the fusion-mpt message passing interface speci?ation, version 1.5.
3-4 LSIFC949X overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 3.2.2 message flow before requests can be posted to the LSIFC949X, the system must allocate and initialize a pool of message frames, and provide a mechanism to assign individual message frames on a per-request basis. the host also must provide one message frame per target lun, and prime the reply free fifos for each function with the physical address of these message frames. when allocation has been completed, requests flow from the host to the LSIFC949X, as represented below and in figure 3.2 . 1. the host driver receives an i/o request from the operating system. 2. the host driver allocates a system message frame (smf) and builds an i/o request message within the smf. the allocation method is the responsibility of the host driver. 3. the host driver creates the message frame descriptor (mfd) and writes the mfd to the request post fifo. 4. the i/o controller (ioc) reads the mfd from the request post fifo and dmas the request to a local message frame. 5. the ioc sends the appropriate fibre channel request and subsequently receives the reply from the target. if the i/o status is successful, the ioc writes the messagecontext value, plus turbo reply bits, to the reply post fifo, which automatically generates a system interrupt. if the i/o status is not successful, the ioc pops a reply message frame from the reply free fifo and generates a reply message in the reply message frame. the ioc then writes the system physical address of the reply message frame to the reply post fifo, which generates a system interrupt. 6. the host driver receives a system interrupt and reads the reply register. if there are no posted messages, the system reads the value 0xffffffff. 7. the host driver responds to the operating system appropriately. 8. if the i/o status is not successful, the host driver returns it to the reply free fifo.
message interface 3-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 3.2 LSIFC949X message flow host driver reply register ioc 1 2 n 3 message pci-x bus 2 operating system frames 7 1 8 1 2 n reply free 1 2 n reply post 1 2 n request post 5 request register 3 6 3 5 4 6 mfd system fifo fifo fifo
3-6 LSIFC949X overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 3.3 scsi message the scsi message interface provides the most direct interface for block-oriented storage media. this includes disk drives and tape devices. the scsi i/o path translates a scsi command descriptor block (cdb) into a fibre channel protocol (fcp) exchange. all fc device and target discovery operations are managed completely within the LSIFC949X. fc target devices are assigned a logical (bus, target id) identi?r, and are accessed by the system as if they were parallel scsi devices. the system is responsible for scanning the target devices and identifying luns on the target devices. in general, the system is responsible for retrying operations at an i/o request level. the LSIFC949X is responsible for responding to bus protocol-speci? errors and exceptions and retrying bus sequences within the scope of an i/o operation. the system is also responsible for maintaining a timer for scsi i/o operations if this is required by the host system. the host driver may use the provided scsi task management functions to terminate one or more i/o operations when a timeout occurs. for details regarding the scsi message class, refer to the fusion- mpt message passing interface speci?ation, version 1.5. 3.4 target message the target interface allows the LSIFC949X to be used as the system interface for fc bridge controllers. the LSIFC949X provides an fcp exchange level message interface that routes commands to the system. the system identi?s the appropriate data, and passes a scatter gather list (sgl) to the LSIFC949X describing the data to transfer. a single target message directs the LSIFC949X to send a xfer_rdy, as needed, and to transfer data and an fcp response. target speci? process login/logout is managed by the system. refer to the fusion-mpt message passing interface speci?ation, version 1.5, for details on the target message class.
support components 3-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 3.5 support components the memory controller block within the LSIFC949X provides access to external local memory resources required to manage fcp. the following sections provide guidance in choosing the support components necessary for a fully functional implementation using the LSIFC949X. figure 3.3 shows an LSIFC949X typical implementation diagram. figure 3.3 LSIFC949X typical implementation 3.5.1 ssram memory the primary function of this memory is to store data structures used by the LSIFC949X to manage exchanges and transmit and receive queues. the ssram memory also stores part of the run time image of the LSIFC949X firmware, such as initialization and error recovery code. the mainline code is stored within the internal lram for performance reasons. the LSIFC949X uses a 32-bit, nonmultiplexed memory bus to access the ssram. this memory bus has the capability to address up to 4 mbytes of ssram. LSIFC949X integrated transceiver memory controller 2 2 serial eeprom (8 kbyte min.) flash rom (1 mbyte) clock (106.25 mhz) 32 pci-x bus 32/64 integrated transceiver 2 2 fc channel 0 fc channel 1 support components ssram (1 mbyte min.) memory
3-8 LSIFC949X overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. the LSIFC949X ?mware also supports optional byte wide parity error detection. this con?urable option is speci?d as a serial eeprom parameter. the amount of ssram (1 mbyte) determines the maximum number of outstanding request messages (1024). this roughly equates to the maximum number of outstanding i/o requests pending in the LSIFC949X. the LSIFC949X also provides an internal sram, which allows the chip to function without an external sram attached. the number of concurrent commands and concurrent logins is reduced in this mode of operation (128 concurrent commands and 32 concurrent logins). 3.5.2 flash rom the memory controller in the LSIFC949X also manages an optional flash rom. if present, the flash rom stores the ?mware for the LSIFC949X, and if desired, the intel bios and/or solaris open boot bios software. if the flash rom is not used, then the host platform is responsible for downloading the iop firmware to the LSIFC949X through the pci-x interface. the LSIFC949X supports a simple register handshake interface for firmware download. firmware may be directly written to the LSIFC949X internal memory and external ssram through this interface. details of this implementation are available in the fusion-mpt message passing interface speci?ation, version 1.5. flash rom is optional for the LSIFC949X, but it is required for applications that require intel or solaris bios software. the flash rom is accessed using the upper 8 bits of the memory interface. if a flash rom is to be used, then it should have a capacity of 1 mbyte with a maximum access time of 150 ns. refer to the fusion- mpt message passing interface speci?ation, version 1.5 , for details on the programming of the flash rom. 3.5.3 serial eeprom the serial eeprom stores nonvolatile data for the LSIFC949X, such as the world wide name, vpd, and other vendor-speci? information. the seeprom data is programmed by the ?mware, so the ?mware must
support components 3-9 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. be downloaded and running before the seeprom is programmed. the required size of the seeprom is 64 kbits / 8 kbytes.
3-10 LSIFC949X overview copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
LSIFC949X dual channel fibre channel i/o processor technical manual 4-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 4 signal descriptions this chapter contains signal descriptions for the LSIFC949X. a slash (/) indicates an active low signal, i/o = bidirectional signal, i = input signal, o = output signal, t/s = 3-state, and s/t/s = sustained 3-state. the chapter contains the following sections: ? section 4.1, ?ci/pci-x interface ? section 4.2, ?ibre channel interface ? section 4.3, ?emory interface ? section 4.4, ?on?uration and miscellaneous ? section 4.5, ?est and i/o processor debug ? section 4.6, ?ower and ground figure 4.1 on page 4-2 is a functional signal grouping for the chip.
4-2 signal descriptions copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 4.1 LSIFC949X functional signal grouping tx0+ tx0- tx1+ tx1- rx1- rtrim lipreset/ fault0/ fault1/ odis0 odis1 bypass0/ bypass1/ tck trst/ tdi tdo tms tms_ice tdi_ice tdo_ice LSIFC949X fibre channel interface test and i/o processor mode[7:0] gpio[5:0] led[4:0]/ serial_clock serial_data flashcs/ ramcs/ ma[23:0] md[31:0] mp[3:0] adv/ adsc/ bwe[3:0]/ mwe[1:0]/ moe[1:0]/ mclk ad[63:0] gnt/ c_be[7:0]/ frame/ trdy/ stop/ serr/ intb/ rst/ req/ idsel irdy/ devsel/ perr/ pa r req64/ ack64/ par64 pciclk memory interface pci-x interface con?uration inta/ rx0- rx1+ rx0+ rxlos0 rxlos1 moddef0[4:0] moddef1[4:0] refclkp and miscellaneous enum/ 64en/ switch cpci_en/ debug scan_mode scan_enable refclkn refclkb fsela test_reset/ tck_ice rtck_ice trst_ice/ proc_mon tn
pci/pci-x interface 4-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 4.1 pci/pci-x interface table 4.1 lists the pci/pci-x interface signals. table 4.1 pci/pci-x interface signal i/o bga pad no. pad type description pciclk i af22 pci in clock . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. rst/ i aa26 pci in reset . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. gnt/ i/o aa21 bidir pci grant . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. req/ i/o y25 bidir pci request . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. req64/ i/o j21 bidir pci request64 . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. ack64/ s/t/s j24 bidir pci acknowledge64 . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. ad[63:0] t/s see table 7.14 and table 7.15 on pages 7-10 and 7-12 , respectively. bidir pci address and data . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. c_be[7:0]/ t/s k20, j23, j22, j20, ac17, y19, u26, p22 bidir pci command and byte enables . refer to the pci local bus speci?ation, revision 2.3 , and the pci-x addendum to the pci local bus speci?ation, revision 2.0 , for this signal description. (sheet 1 of 4)
4-4 signal descriptions copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. idsel i/o y26 bidir pci initialization device select . refer to the pci local bus speci?ation, revision 2.3, and the pci- x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. frame/ s/t/s aa22 bidir pci cycle frame . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. irdy/ s/t/s ab23 bidir pci initiator ready . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. trdy/ s/t/s v23 bidir pci target ready . refer to the pci local bus speci?ation, revision 2.3 , and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. devsel/ i/o u21 bidir pci device select . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. stop/ s/t/s w20 bidir pci stop . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. perr/ s/t/s u23 bidir pci parity error . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. serr/ o v24 bidir pci system error . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. par t/s u25 bidir pci parity . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. table 4.1 pci/pci-x interface (cont.) signal i/o bga pad no. pad type description (sheet 2 of 4)
pci/pci-x interface 4-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. par64 i/o h26 bidir pci parity64 . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. inta/ o ab24 bidir pci interrupt a . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. intb/ o aa24 bidir pci interrupt b . refer to the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0, for this signal description. enum/ o aa23 bidir pci enumeration interrupt . this signal must be asserted by a hot swap capable card immediately after insertion and during removal. this signal noti?s the system host either that a board has been freshly inserted or that one is about to be extracted, and informs the system host that the con?uration of the system has changed. the system host then can perform any necessary maintenance such as installing a device driver upon board insertion, or quiescing a device driver and the board, prior to extracting the board. 64en/ i/o ac26 bidir pci pci bus width enable . this signal indicates the width of the bus when hot swap capability is enabled. use an external pull-up on this signal when compactpci is enabled. float this signal when compactpci is disabled. switch i ae13 pci in (pull- down) insertion/deassertion indicator . this signal is an input to the LSIFC949X to signal the insertion or impending extraction of a board. this signal causes the assertion of enum/. the operator normally activates the switch (actuator), waits for the illumination of the led, and then extracts the board. table 4.1 pci/pci-x interface (cont.) signal i/o bga pad no. pad type description (sheet 3 of 4)
4-6 signal descriptions copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 4.2 fibre channel interface table 4.2 lists the fibre channel interface signals. cpci_en/ i y13 pci in (pull-up) compactpci enable . when this signal is low, the LSIFC949X is con?ured to conform to hot swap protocol. this includes changing the bus width detection method, the addition of con?uration registers, and support for the enum/, blueled/, and switch pins. when cpci_en/ is active (low), pull up ma[7] to force conventional pci mode. blueled/ o ae10 3.3 v bidir 8 ma with pull-up blueled/ . this signal drives a blue led that is mounted on the front of hot swap capable host adapters. this signal indicates that the system software has been placed in a state for orderly extraction of the board. table 4.1 pci/pci-x interface (cont.) signal i/o bga pad no. pad type description (sheet 4 of 4) table 4.2 fibre channel interface signal i/o bga pad no. pad type description tx0+ o n6 diff tx transmit differential data (channel 0). tx1+ o p7 diff tx transmit differential data (channel 1). tx0 ? o n7 diff tx transmit differential data (channel 0). tx1 ? o p6 diff tx transmit differential data (channel 1). rx0+ i n4 diff rx receive differential data (channel 0). rx1+ i p4 diff rx receive differential data (channel 1). rx0 ? i n5 diff rx receive differential data (channel 0). rx1 ? i p5 diff rx receive differential data (channel 1). (sheet 1 of 4)
fibre channel interface 4-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. rtrim i v2 trim resistor . this pin is the analog current reference for the integrated transceiver core. a 3.01 k ? 1% resistor should be tied from the rtrim pad to either the rxvdd0 or the rxvdd1 pin . lipreset/ o ad9 3.3 v bidir 4ma loop initialization primitive reset . this pin is asserted low when a selective reset is received that is targeted to an alias of this device. this pin is asserted for 1? ms after the last lipr is received. fault0/ i y8 3.3 v ttl input with pull-up electrical fault . this active-low pin indicates that an electrical fault has been detected by the channel 0 phy device/module and, if the module has a laser, the laser has been turned off. this pin causes no interrupt or other reaction. it is assumed that a link failure occurs, and that the register bit reporting the value of this pin diagnoses the problem. fault1/ i ac10 3.3 v ttl input with pull-up electrical fault . this active-low pin indicates that an electrical fault has been detected by the channel 1 phy device/module and, if the module has a laser, the laser has been turned off. this pin causes no interrupt or other reaction. it is assumed that a link failure occurs, and that the register bit reporting the value of this pin diagnoses the problem. odis0 o ac5 3.3 v bidir 4ma output disable, channel 0. this output, when asserted, disables an external gbic or mia transmitter for channel 0. this output also clears a module fault. odis1 o ab9 3.3 v bidir 4ma output disable, channel 1. this output when asserted disables an external gbic or mia transmitter for channel 1. this output also clears a module fault. table 4.2 fibre channel interface (cont.) signal i/o bga pad no. pad type description (sheet 2 of 4)
4-8 signal descriptions copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. bypass0/ o ac9 3.3 v bidir 4ma bypass . this line is driven low when the LSIFC949X link controller block determines that channel 0 of the device is operating in a loop environment and that the device has entered a bypassed mode. this may be caused by an internal request or by a loop primitive generated at another node. bypass1/ o aa10 3.3 v bidir 4ma bypass . this line is driven low when the LSIFC949X link controller block determines that channel 1 of the device is operating in a loop environment and the device has entered a bypassed mode. this may be caused by an internal request or a loop primitive generated at another node. rxlos0 i ab10 3.3 v 4 ma bidir with pull-up received signal loss . this line is driven high, disabling the on-chip receiver, when the gbic for channel 0 of the LSIFC949X detects a loss of signal. if enabled through the link control register, this signal becomes an output test strobe. rxlos1 i aa7 3.3 v 4 ma bidir with pull-up received signal loss . this line is driven high, disabling the on-chip receiver, when the gbic for channel 1 of the LSIFC949X detects a loss of signal. if enabled through the link control register, this signal becomes an output test strobe. moddef0[4:0] i/o ae6, af5, af6, aa6, y7 3.3 v bidir 8ma with pull-up module identi?rs . gbic and pluggable small form factor (sfp) optical module identi?rs (channel 0). moddef1[4:0] i/o ae7, af7, ae8, af8, ab6 3.3 v bidir 8ma with pull-up module identi?rs . gbic and pluggable small form factor (sfp) optical module identi?rs (channel 1). refclkp i u7 3.3 v schmitt input fc reference clock . (106.25 mhz 100 ppm). refer to the oscillator requirements section of sen #s11066, ?sifc949x design considerations, for further information regarding the refclkp and refclkn inputs. table 4.2 fibre channel interface (cont.) signal i/o bga pad no. pad type description (sheet 3 of 4)
memory interface 4-9 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 4.3 memory interface table 4.3 shows the memory interface signals. refclkn i v6 3.3 v schmitt input fc reference clock . (106.25 mhz 100 ppm). if using a single crystal for the fc reference clock, tie the crystal to refclkp, and tie refclkn to a resistor terminator. refclkb i v4 3.3 v schmitt input internal reference clock . (use 106.25 mhz). this pin will typically be tied to the refclkp pin. table 4.2 fibre channel interface (cont.) signal i/o bga pad no. pad type description (sheet 4 of 4) table 4.3 memory interface signal i/o bga pad no. pad type description md[31:0] 1 i/o see table 7.14 and table 7.15 on pages 7-10 and 7-12 , respectively. 3.3 v bidir 4 ma with pull-down ssram read/write data . see table note 1 on page 4-11 . mp[3:0] i/o f6, g7, g2, g1 3.3 v 4 ma bidir with pull-up memory parity . byte lane parity is as follows: ? mp [0]: parity for md[7: 0] ? mp [1]: parity for md[15: 8] ? mp [2]: parity for md[23:16] ? mp [3]: parity for md[31:24] memory parity may be optionally even, odd, or none (not used) as de?ed in the LSIFC949X programming model. (sheet 1 of 3)
4-10 signal descriptions copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. ma[23:0] i/o see table 7.14 and table 7.15 on pages 7-10 and 7-12 , respectively. 3.3 v output with pull-down ssram/flash rom address . the ma[19:0] pins are also used at power-on to provide con?uration information to the LSIFC949X. the LSIFC949X uses ma[12:11] to determine the external flash rom con?uration, ma[2] to determine whether to operate as a single- function or dual-function pci device, and ma[0] to indicate the use of an external 8 kbyte eeprom. the de?itions for these power-on sense options are shown below: 2 ma[12:11] 01 = no flash rom present 10 = 1 mbyte flash rom ma[2] 0 = two pci-x functions 1 = one pci-x function ma[0] 0 = n/a 1 = 8 kbyte eeprom refer to sen #s11066, ?sifc949x design considerations, for further information about the power-on sense de?itions. moe[1:0]/ o k4, h7 3.3 v bidir 8ma memory output enable . when asserted low, the selected sram or flash (moe[1]/) device may drive data. this signal is typically an asynchronous input to sram and/or flash devices. the two output enables allow for interleaving con?urations, with moe[0]/ being the only output enable used for a noninterleaved implementation. mwe[1:0]/ o k5, g6 3.3 v bidir 4ma memory write enables . these active-low bank write enables are required for interleaving con?urations. mwe[0]/ is the only write enable used for a noninterleaved implementation. flashcs/ o j3 3.3 v bidir 4ma flash chip select . this active-low chip select allows connection of a single, 8-bit flash rom device. table 4.3 memory interface (cont.) signal i/o bga pad no. pad type description (sheet 2 of 3)
con?uration and miscellaneous 4-11 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 4.4 con?uration and miscellaneous table 4.4 shows the con?uration and miscellaneous signals. mclk o f5 3.3 v 8 ma t/s output memory clock . all synchronous ram control/data signals are referenced to the rising edge of this clock. the exception is moe/, which is typically an asynchronous input to sram and/or flash devices. adsc/ o h1 3.3 v 4 ma t/s output address-strobe-controller . initiates read, write, or chip deselect cycle. when this signal is asserted, it also latches the memory address signals. adv/ o h2 3.3 v 4 ma t/s output advance . when asserted low, the adv/ input causes a selected synchronous sram to increment its burst address counter. bwe[3:0]/ o e4, j5, j4, k6 3.3 v bidir 4ma memory byte write enables . these active-low, byte lane write enables allow writing of partial words to memory. ramcs/ o j2 3.3 v bidir 4ma ram chip select . this pin is an active-low synchronous chip select for all ssrams (up to four ssrams for interleaved and depth expanded con?uration without additional decode logic). 1. md[31:24] are used for the flash rom read/write data. 2. ? means the pin is pulled up on reset. ? means the pin is pulled down on reset. table 4.3 memory interface (cont.) signal i/o bga pad no. pad type description (sheet 3 of 3)
4-12 signal descriptions copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 4.4 con?uration and miscellaneous signal i/o bga pad no. pad type description gpio[5:0] i/o ae12, af11, aa9, y10, ae11, af10 3.3 v bidir 8 ma with pull-up general purpose i/o pins . these pins default to input mode on reset. these signals are controlled/observed by rmware. gpio[1:0] are reserved for lsi logic only. gpio[5:2] are available as host-programmable outputs from ioc unit page 3. led[4:0]/ o ae9, ad10, y9, aa8, af9 3.3 v bidir 8ma led outputs . these output signals may be controlled by ?mware or driven by chip activity. when con?ured as activity driven, the led[n] outputs have the following meanings when asserted low: ? led[4]: channel 1 fault (on = no sync) ? led[3]: channel 1 active (on = frame traf? present) ? led[2]: channel 0 fault (on = no sync) ? led[1]: channel 0 active (on = frame traf? present) ? led[0]: processor heartbeat serial_ clock o aa4 3.3 v 4 ma bidir with pull-up serial eeprom clock . serial_ data i/o ab3 3.3 v 4 ma bidir with pull-up serial eeprom data . mode[7:0] i j7, h6, j1, k2, k1, l2, k7, j6 3.3 v ttl input with pull-down mode select . this 8-bit bus de?es operational and test modes for the chip. valid mode encodings are as follows: ? mode[7:0] = 001xxxxx interleaved bsram ? mode[7:0] = 000xxxxx noninterleaved bsram ? mode[7:0] = 00xx01xx soft reset mode0 ? mode[7:0] = 00xx11xx soft reset mode1 1 ? mode[7:0] = 00xxxx11 normal seprom auto load ? mode[7:0] = 00xxxx10 fast seprom auto load ? mode[7:0] = 00xxxx01 firmware pci con?uration mode 2 ? mode[7:0] = 00xxxx00 pci con?uration (use default values) (sheet 1 of 2)
test and i/o processor debug 4-13 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 4.5 test and i/o processor debug table 4.5 shows the test and i/o processor debug signals. test_ reset/ iv7 3.3v schmitt with pull-up test reset . forces the LSIFC949X into power-on reset state or soft-reset state, depending on the state of the mode pins. scan_ mode i v5 3.3 v ttl input with pull-down scan mode . reserved for lsi logic test purposes only. scan_ enable i w6 3.3 v ttl input with pull-down scan enable . reserved for lsi logic test purposes only. tdiodevss i u5 reserved for lsi logic test purposes only. tdiodep i u6 3.3 v input with pull- down reserved for lsi logic test purposes only. fsela i ac2 3.3 v ttl input with pull-down arm966/ahb clock select . reserved for lsi logic test purposes only. bzrset ae21 reference resistor node for the pci-x impedance controller. a 49.9 ? 1% resistor should be tied between the bzrset pad and the bzvdd pad. bzvdd ae22 reference resistor node for the pci-x impedance controller. a 49.9 ? 1% resistor should be tied between the bzvdd pad and the bzrset pad. uartrx i ab5 3.3 v in receive for on-chip uart uarttx i/o ac4 3.3 v bidir transmit for on-chip uart 1. soft reset mode1 also resets the link control logic in addition to the normal soft reset effects. 2. ma[17] must have a pull-up (for power-on sense purposes) to disable arm booting. table 4.4 con?uration and miscellaneous (cont.) signal i/o bga pad no. pad type description (sheet 2 of 2)
4-14 signal descriptions copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 4.5 test and i/o processor debug signal i/o bga pad no. pad type description tck i aa1 3.3 v schmitt with pull-up jtag/ctxmgr debug test clock . trst/ i ab1 3.3 v schmitt with pull-up jtag/debug test reset . asynchronous active low. tdi i aa3 3.3 v schmitt with pull-up jtag/ctxmgr debug test data in . tdo b ab4 3.3 v 4 ma t/s output with pull-up jtag/ctxmgr debug test data out . tms i aa2 3.3 v schmitt with pull-up jtag test mode select . tms_ice i y2 3.3 v schmitt with pull-up ctxmgr debug test mode select . tdi_ice i y6 3.3 v schmitt with pull-up multi-ice debug test data in. tdo_ice b w7 3.3 v 4 ma t/s output with pull-up multi-ice debug test data out. tck_ice i w2 3.3 v schmitt with pull-up multi-ice debug clock. rtck_ice b w1 3.3 v 4 ma t/s output with pull-up multi-ice debug rclk. trst_ice/ i y1 3.3 v schmitt with pull-up multi-ice debug reset. asynchronous active low. when ice is not used, pull trst_ice/ low through a 220 ? resistor. proc_mon o aa5 process monitor test output driver . reserved for lsi logic test purposes only. tn i ac1 3-state output enable control. reserved for lsi logic test purposes only. iddtn i ab2 in iddtn test pad. reserved for lsi logic test purposes only.
power and ground 4-15 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 4.6 power and ground table 4.6 shows the power and ground signals. table 4.6 power and ground signal bga pad no. description voltage vdd12 1 see table 7.14 and table 7.15 on pages 7-10 and 7-12 , respectively. core power. 1.2 v vss see table 7.14 and table 7.15 on pages 7-10 and 7-12 , respectively. ground. 0 v vddio33 see table 7.14 and table 7.15 on pages 7-10 and 7-12 , respectively. i/o power. 3.3 v vddio33_ pcix see table 7.14 and table 7.15 on pages 7-10 and 7-12 , respectively. pcix power. 3.3 v refpllvdd ad2 analog power for pci fsn cell. 1.2 v refpllvss ac3 analog ground for pci fsn cell. 0 v pcipllvdd ae24 analog power for arm clock generation. 1.2 v pcipllvss ad23 analog ground for arm clock generation. 0 v mxsvdd l3, m3, r4, t4 analog power for integrated transceiver core. 1.2 v rxbvdd0 p1 analog power for integrated transceiver core. 1.2 v rxbvss0 n1 analog ground for integrated transceiver core. 0 v rxbvdd1 u2 analog power for integrated transceiver core. 1.2 v rxbvss1 u1 analog ground for integrated transceiver core. 0 v rxvdd0 r1 analog power for integrated transceiver core. 1.2 v rxvss0 p2 analog ground for integrated transceiver core. 0 v rxvdd1 v1 analog power for integrated transceiver core. 1.2 v rxvss1 u3 analog ground for integrated transceiver core. 0 v (sheet 1 of 2)
4-16 signal descriptions copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. txbvdd0 n3 analog power for integrated transceiver core. 1.2 v txbvss0 m2 analog ground for integrated transceiver core. 0 v txbvdd1 r2 analog power for integrated transceiver core. 1.2 v txbvss1 p3 analog ground for integrated transceiver core. 0 v txvdd0 m1 analog power for integrated transceiver core. 1.2 v txvss0 n2 analog ground for integrated transceiver core. 0 v txvdd1 t2 analog power for integrated transceiver core. 1.2 v txvss1 t1 analog ground for integrated transceiver core. 0 v 1. the required core voltage on the LSIFC949X is 1.2 v. the pcix i/o voltage requires 3.3 v, and the gigablaze fibre channel transceiver interface requires 1.2 v. con?ure the power supply to the chip so that the lower voltages power-up in advance of the higher voltages. the recommended power sequencing depends on the number of supplies used. for a pcix system with pcix buffers, the recommended power sequence is 1.2 v and then 3.3 v; or make certain that the following conditions are met during the power cycling: (vdd1.2 > 1 v) before (vdd3.3 > 1 v) table 4.6 power and ground (cont.) signal bga pad no. description voltage (sheet 2 of 2)
LSIFC949X dual channel fibre channel i/o processor technical manual 5-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 5 pci-x functional description this chapter provides a general description of the pci-x features contained in the LSIFC949X dual channel fibre channel i/o processor chip. the chapter contains the following sections: ? section 5.1, ?verview ? section 5.2, ?ci-x addressing ? section 5.3, ?ci/pci-x bus commands and implementation ? section 5.4, ?ci arbitration ? section 5.5, ?ci cache mode 5.1 overview the host pci-x interface complies with the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0. the LSIFC949X supports up to a 133 mhz, 64-bit pci-x bus. the LSIFC949X supports 64-bit addressing with dual address cycle (dac). the LSIFC949X is a true multifunction pci-x device that presents a single electrical load to the pci-x bus. the LSIFC949X uses a single req/-gnt/ pair to arbitrate for pci-x bus mastership. separate interrupt signals for pci function [0] and pci function [1] allow independent control of the two pci functions.
5-2 pci-x functional description copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 5.2 pci-x addressing the three physical address spaces the pci speci?ation de?es are: ? pci con?uration space ? pci i/o space for operating registers ? pci memory space for operating registers the following sections describe the pci address spaces. 5.2.1 pci con?uration space the LSIFC949X de?es an independent set of pci con?uration space registers for each pci function. each con?uration space is a contiguous, 256-x-8-bit set of addresses. the system bios initializes the con?uration registers using pci-x con?uration cycles. the LSIFC949X decodes the c_be[3:0]/ ?ld to determine whether a pci-x cycle intends to access the con?uration register space. the idsel signal behaves as a chip select signal that enables access to the con?uration register space only. the LSIFC949X ignores con?uration read/write cycles when idsel is not asserted. because the LSIFC949X is a multifunction pci-x device, bits ad[10:8] decode either the pci function [0] con?uration space (ad[10:8] = 0b000) or the pci function [1] con?uration space (ad[10:8] = 0b001). the LSIFC949X does not respond to any other encodings of ad[10:8]. bits ad[7:2] select one of the 64 dword registers in the LSIFC949X pci con?uration space. bits ad[1:0] determine whether the con?uration command is a type 0 con?uration command (ad[1:0] = 0b00) or a type 1 con?uration command (ad[1:0] = 0b01). because the LSIFC949X is not a pci bridge device, all pci con?uration commands designated for the LSIFC949X must be type 0. bits c_be[3:0]/ address the individual bytes within each dword and determine the type of access to perform. 5.2.2 pci i/o space the pci speci?ation de?es i/o space as a contiguous 32-bit, i/o address that all system resources share, including the LSIFC949X. the
pci/pci-x bus commands and implementation 5-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. i/o base address register determines the 256-byte pci i/o area that the pci device occupies. 5.2.3 pci memory space the LSIFC949X contains two pci memory spaces: pci memory space [0] and pci memory space [1]. pci memory space [0] supports normal memory accesses, while pci memory space [1] supports diagnostic memory accesses. the LSIFC949X requires 64 kbytes of memory space. the pci speci?ation de?es memory space as a contiguous, 64-bit memory address that all system resources share. the memory [0] base address low and memory [0] base address high registers determine which 64 kbyte memory area pci memory space [0] occupies. the memory [1] base address low and memory [1] base address high registers determine which 64 kbyte memory area pci memory space [1] occupies. 5.3 pci/pci-x bus commands and implementation bus commands indicate to the target the type of transaction the master is requesting. the master encodes the bus commands on the c_be[3:0]/ lines during the address phase. the pci/pci-x bus commands and their encodings appear in table 5.1 . table 5.1 pci/pci-x bus commands and encodings 1 c_be[3:0]/ pci bus command pci-x bus command supports as master supports as slave 0b0000 interrupt acknowledge interrupt acknowledge no no 0b0001 special cycle special cycle no no 0b0010 i/o read i/o read yes yes 0b0011 i/o write i/o write yes yes 0b0100 reserved reserved n/a n/a 0b0101 reserved reserved n/a n/a 0b0110 memory read memory read dword yes yes (sheet 1 of 2)
5-4 pci-x functional description copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. the following sections describe how the LSIFC949X implements these commands. 5.3.1 interrupt acknowledge command the LSIFC949X ignores this command as a slave and never generates it as a master. 5.3.2 special cycle command the LSIFC949X ignores this command as a slave and never generates it as a master. 5.3.3 i/o read command the i/o read command reads data from an agent mapped in the i/o address space. when decoding i/o commands, the LSIFC949X decodes the lower 32 address bits and ignores the upper 32 address bits. the 0b0111 memory write memory write yes yes 0b1000 reserved alias to memory read block pci: n/a pci-x: no pci: n/a pci-x: yes 0b1001 reserved alias to memory write block pci: n/a pci-x: no pci: n/a pci-x: yes 0b1010 con?uration read con?uration read no yes 0b1011 con?uration write con?uration write no yes 0b1100 memory read multiple split completion yes yes 2 0b1101 dual address cycles (dac) dual address cycles (dac) yes yes 0b1110 memory read line memory read block yes yes 2 0b1111 memory write and invalidate memory write block yes yes 3 1. the LSIFC949X ignores reserved commands as a slave and never generates them as a master. 2. when acting as a slave in the pci mode, the LSIFC949X supports this command as the pci memory read command. 3. when acting as a slave in the pci mode, the LSIFC949X supports this command as the pci memory write command. table 5.1 pci/pci-x bus commands and encodings 1 (cont.) (cont.) c_be[3:0]/ pci bus command pci-x bus command supports as master supports as slave (sheet 2 of 2)
pci/pci-x bus commands and implementation 5-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. LSIFC949X supports this command when operating in either the pci or pci-x bus mode. 5.3.4 i/o write command the i/o write command writes data to an agent mapped in the i/o address space. when decoding i/o commands, the LSIFC949X decodes the lower 32 address bits and ignores the upper 32 address bits. the LSIFC949X supports this command when operating in either the pci or pci-x bus mode. 5.3.5 memory read command the LSIFC949X uses the memory read command to read data from an agent mapped in the memory address space. the target can perform an anticipatory read if such a read produces no side effects. the LSIFC949X supports this command when operating in the pci bus mode. 5.3.6 memory read dword command the memory read dword command reads up to a single dword of data from an agent mapped in the memory address space and can only be initiated as a 32-bit transaction. the target can perform an anticipatory read if such a read produces no side effects. the LSIFC949X supports this command when operating in the pci-x bus mode. 5.3.7 memory write command the memory write command writes data to an agent mapped in the memory address space. the target assumes responsibility for data coherency when it returns ?eady? the LSIFC949X supports this command when operating in either the pci or pci-x bus mode. 5.3.8 alias to memory read block command this command is reserved for future implementations of the pci speci?ation. the LSIFC949X never generates this command as a master. when a slave, the LSIFC949X supports this command using the memory read block command.
5-6 pci-x functional description copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 5.3.9 alias to memory write block command this command is reserved for future implementations of the pci speci?ation. the LSIFC949X never generates this command as a master. when a slave, the LSIFC949X supports this command using the memory write block command. 5.3.10 con?uration read command the con?uration read command reads the con?uration space of a device. the LSIFC949X never generates this command as a master, but does respond to it as a slave. a device on the pci bus selects the LSIFC949X by asserting its idsel signal when bits ad[1:0] = 0b00. during the address phase of a con?uration cycle, bits ad[7:2] address one of the 64 dword registers in the con?uration space of each device. c_be[3:0]/ address the individual bytes within each dword register and determine the type of access to perform. bits ad[10:8] address either the pci function [0] con?uration space (ad[10:8] = 0b000) or the pci function [1] con?uration space (ad[10:8] = 0b001). the LSIFC949X treats ad[63:11] as logical don? cares. 5.3.11 con?uration write command the con?uration write command writes the con?uration space of a device. the LSIFC949X never generates this command as a master, but does respond to it as a slave. a device on the pci bus selects the LSIFC949X by asserting its idsel signal when bits ad[1:0] = 0b00. during the address phase of a con?uration cycle, bits ad[7:2] address one of the 64 dword registers in the con?uration space of each device. c_be[3:0]/ address the individual bytes within each dword register and determine the type of access to perform. bits ad[10:8] decode either the pci function [0] con?uration space (ad[10:8] = 0b000) or the pci function [1] con?uration space (ad[10:8] = 0b001). the LSIFC949X treats ad[63:11] as logical don? cares. 5.3.12 memory read multiple command the memory read multiple command is identical to the memory read command, except it additionally indicates that the master intends to fetch multiple cache lines before disconnecting. the LSIFC949X supports pci memory read multiple functionality when operating in the pci mode
pci/pci-x bus commands and implementation 5-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. and determines when to issue a memory read multiple command instead of a memory read command. burst size selection the memory read multiple command reads multiple cache lines of data during a single bus ownership. the number of cache lines the LSIFC949X reads is a multiple of the cache line size, which the pci local bus speci?ation, revision 2.3, provides. the LSIFC949X selects the largest multiple of the cache line size based on the amount of data to transfer. 5.3.13 split completion command split transactions in pci-x replace the delayed transactions in conventional pci. the LSIFC949X supports one outstanding split transaction when operating in the pci-x mode. a split transaction consists of at least two separate bus transactions: a split request, which the requester initiates; and one or more split completion commands, which the completer initiates. the pci-x addendum to the pci local bus speci?ation, revision 2.0, permits split transaction completion for the memory read block, alias to memory read block, memory read dword, interrupt acknowledge, i/o read, i/o write, con?uration read, and con?uration write commands. when operating in the pci-x mode, the LSIFC949X supports the split completion command for all of these commands except the interrupt acknowledge command, which the LSIFC949X neither responds to nor generates. 5.3.14 dual address cycles (dac) command the LSIFC949X performs dual address cycles (dac), according to the pci local bus speci?ation, revision 2.3. the LSIFC949X supports this command when operating in either the pci or pci-x bus mode. 5.3.15 memory read line command this command is identical to the memory read command except it additionally indicates that the master intends to fetch a complete cache line. the LSIFC949X supports this command when operating in the pci mode.
5-8 pci-x functional description copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 5.3.16 memory read block command the LSIFC949X uses this command to read from memory. the LSIFC949X supports this command when operating in the pci-x mode. 5.3.17 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except it additionally guarantees a minimum transfer of one complete cache line. the master uses this command when it intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register. the LSIFC949X determines when to issue a write and invalidate command instead of a memory write command, and supports this command when operating in the pci bus mode. 5.3.17.1 alignment the LSIFC949X uses the calculated line size value to determine whether the current address aligns to the cache line size. if the address does not align, the LSIFC949X bursts data using a noncache command. if the starting address aligns, the LSIFC949X issues a memory write and invalidate command using the cache line size as the burst size. 5.3.17.2 multiple cache line transfers the memory write and invalidate command can write multiple cache lines of data in a single bus ownership. the LSIFC949X issues a burst transfer as soon as it reaches a cache line boundary. the pci local bus speci?ation states that the transfer size must be a multiple of the cache line size. the LSIFC949X selects the largest multiple of the cache line size based on the transfer size. when the dma buffer contains less data than the value cache line size register speci?s, the LSIFC949X issues a memory write command on the next cache boundary to complete the data transfer.
pci arbitration 5-9 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 5.3.18 memory write block command the LSIFC949X uses this command to burst data to memory. the LSIFC949X supports this command when operating in the pci-x bus mode. 5.4 pci arbitration the LSIFC949X contains independent bus mastering functions for each of the scsi functions and for the system interface. the system interface bus mastering function manages dma operations as well as the request and reply message frames. the scsi channel bus mastering functions manage data transfers across the scsi channels. the LSIFC949X uses a single req/-gnt/ signal pair to arbitrate for access to the pci bus. to ensure fair access to the pci bus, the internal arbiter uses a round robin arbitration scheme to decide which of the three internal bus mastering functions can arbitrate for access to the pci bus. 5.5 pci cache mode the LSIFC949X supports an 8-bit, cache line size register. this register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. the LSIFC949X determines when to issue a pci cache command (memory read line, memory read multiple, and memory write and invalidate) or pci noncache command (memory read or memory write).
5-10 pci-x functional description copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
LSIFC949X dual channel fibre channel i/o processor technical manual 6-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 6 registers this chapter describes the pci host register space. the chapter consists of the following sections: ? section 6.1, ?ci-x con?uration space register description ? section 6.2, ?ci i/o space and memory space register description the register map at the beginning of each register description provides the default bit settings for the register. shading indicates a reserved bit or register. do not access the reserved address areas. there are two pci functions on the LSIFC949X. each pci function has its own independent interrupt pin and its own pci address space. the pci system address space consists of three regions: pci con?uration space, pci memory space, and pci i/o space. pci con?uration space supports the identi?ation, con?uration, initialization, and error management functions for the LSIFC949X pci devices. pci memory space [0] and pci memory space [1] form pci memory space. pci memory space [1] provides diagnostic memory accesses. pci i/o space and pci memory space [0] provide normal system access to memory. 6.1 pci-x con?uration space register description this section provides bit-level descriptions of the pci con?uration space registers. table 6.1 de?es the pci con?uration space registers. a separate set of pci con?uration space registers exists for each pci function. the LSIFC949X enables, orders, and locates the pci-extended capability register structures (power management, messaged signaled interrupts, and pci-x) to optimize device performance. the LSIFC949X does not hardcode the location and order of the pci-extended capability
6-2 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. structures. the address and location of the pci-extended capability structures are subject to change. to access a pci-extended capability structure, follow the pointers held in the capability pointer registers and identify the extended capability structure with the capability id register for the given structure. shading in the following address map and register descriptions indicates reserved bits. table 6.1 LSIFC949X pci-x con?uration space address map 31 16 15 0 offset page device id vendor id 0x00 6-3 status command 0x04 6-4 class code revision id 0x08 6-8 reserved header type latency timer cache line size 0x0c 6-9 i/o base address 0x10 6-10 memory [0] base address low 0x14 6-11 memory [0] base address high 0x18 6-11 memory [1] base address low 0x1c 6-12 memory [1] base address high 0x20 6-12 reserved 0x24 0x28 subsystem id subsystem vendor id 0x2c 6-13 expansion rom base address 0x30 6-14 reserved capabilities pointer 0x34 6-15 0x38 maximum latency minimum grant interrupt pin interrupt line 0x3c 6-16 reserved 0x40 0xff power management capabilities pm next pointer pm capability id 6-19 pm data pm bse power management control/status 6-20 reserved msi message control msi next pointer msi capability id 6-22 msi message lower address 6-23 msi message upper address 6-24 reserved msi message data 6-24 msi mask bits 6-25 msi pending bits 6-25 reserved msi-x message control msi-x next pointer msi-x capability id 6-25 msi-x table offset 6-27 msi-x pba offset 6-27 reserved pci-x command pci-x next pointer pci-x capability id 6-28 pci-x status 6-30 reserved
pci-x con?uration space register description 6-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x00?x01 vendor id read only vendor id [15:0] this 16-bit register identi?s the device manufacturer. the vendor id is 0x1000. register: 0x02?x03 device id read only device id [15:0] this register identi?s the particular device. the most signi?ant 12 bits are hardcoded to a constant of 0x064. the lsb is dependent upon the power-on sense functions corresponding to the states of pins ma[4] and ma[3] as decoded in table 6.2 . 15 8 7 0 vendor id 0001000000000000 15 8 7 0 device id 00000110010000xx table 6.2 device id values single/dual channel state of ma[4:3] device id function 1 dual channel ma[4] = 0 0x0640 dual channel ma[4] = 1 0x0641 single channel ma[4] = 0 0x0642 single channel ma[4] = 1 0x0643 (sheet 1 of 2)
6-4 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x04?x05 command read/write this register provides coarse control over how the pci function generates and responds to pci cycles. writing a zero to this register logically disconnects the LSIFC949X pci function from the pci bus for all accesses except con?uration accesses. reserved [15:9] this ?ld is reserved. serr/ enable 8 setting this bit enables the LSIFC949X to activate the serr/ driver. clearing this bit disables the serr/ driver. reserved 7 this bit is reserved. enable parity error response 6 setting this bit enables the LSIFC949X pci function to detect parity errors on the pci bus and report these errors to the system. clearing this bit causes the LSIFC949X pci function to set the detected parity error bit (bit 15 in the status register (register 0x06?x07)) but not assert the perr/ signal when the pci function function 0 dual channel ma[3] = 0 0x0640 dual channel ma[3] = 1 0x0641 single channel ma[3] = 0 0x0642 single channel ma[3] = 1 0x0643 15 8 7 0 command 0 0 0 0 0 0 00 00 00 0000 table 6.2 device id values (cont.) single/dual channel state of ma[4:3] device id (sheet 2 of 2)
pci-x con?uration space register description 6-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. detects a parity error. this bit only affects parity checking. the pci function always generates parity for the pci bus. reserved 5 this bit is reserved. write and invalidate enable 4 setting this bit enables the pci function to generate write and invalidate commands on the pci bus when operating in the conventional pci mode. reserved 3 this bit is reserved. enable bus mastering 2 setting this bit allows the pci function to behave as a pci bus master. clearing this bit disables the pci function from generating pci bus master accesses. enable memory space 1 this bit controls the ability of the pci function to respond to memory space accesses. setting this bit allows the LSIFC949X to respond to memory space accesses at the address range speci?d by the memory [0] base address low , memory [0] base address high , memory [1] base address low , memory [1] base address high , and the expansion rom base address registers. clearing this bit disables the pci function response to memory space accesses. enable i/o space 0 this bit controls the LSIFC949X pci function response to i/o space accesses. setting this bit enables the pci function to respond to i/o space accesses at the address range the pci con?uration space i/o base address register speci?s. clearing this bit disables the pci function response to i/o space accesses.
6-6 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x06?x07 status read/write reads to this register behave normally. to clear a bit location that is currently set, write the bit to one (1). for example, to clear bit 15 when it is set, and not affect any other bits, write 0x8000 to the register. detected parity error (from slave) 15 this bit is set according to the pci local bus speci?a- tion, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0. signaled system error 14 the LSIFC949X pci function sets this bit when asserting the serr/ signal. received master abort (from master) 13 a master device sets this bit when a master abort command terminates its transaction (except for special cycle). received target abort (from master) 12 a master device sets this bit when a target abort command terminates its transaction. reserved 11 this bit is reserved. devsel/ timing [10:9] these two read-only bits encode the timing of the devsel/ signal and indicate the slowest time that a device asserts the devsel/ signal for any bus command except con?uration read and con?uration write. the 15 8 7 0 status 0000 0010 0 011 0 0 0 0
pci-x con?uration space register description 6-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. LSIFC949X only supports medium devsel/ timing. the possible timing values are as follows: data parity error reported 8 this bit is set according to the pci local bus speci?a- tion, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0. refer to bit 0 of the pci-x command register for details. reserved [7:6] this ?ld is reserved. 66 mhz capable 5 the ma[10] power-on sense pin controls this bit. allowing the internal pull-down to pull ma[10] low sets this bit and indicates to the host system that the LSIFC949X pci function is capable of operating at 66 mhz. pulling ma[10] high clears this bit and indicates to the host system that the LSIFC949X pci function is not capable of operating at 66 mhz. refer to table 4.3 on page 4-9 for details. new capabilities 4 the LSIFC949X pci function sets this read-only bit to indicate a list of pci extended capabilities such as pci power management, message signaled interrupt (msi), and pci-x support. reserved [3:0] this ?ld is reserved. 0b00 fast 0b01 medium 0b10 slow 0b11 reserved
6-8 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x08 revision id read/write revision id [7:0] this register indicates the current revision level of the device. register: 0x09?x0b class code read only class code [23:0] this 24-bit register identi?s the generic function of this device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?s a speci? register-level programming interface. the value of this register is 0x0c0400, and is written by the seeprom (provided the seeprom is present in the system). if no seeprom is present in the system, the default class code is 0x010000. 7 0 revision id xxxxxxxx 23 16 15 8 7 0 class code 000000010000000000000000
pci-x con?uration space register description 6-9 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x0c cache line size read/write cache line size [7:3] this register speci?s the system cache line size in units of 32-bit words. in the conventional pci mode, the LSIFC949X pci function uses this register to determine whether to use write and invalidate or write commands for performing write cycles. programming this register to a number other than a nonzero power of two disables the the use of the pci performance commands to execute data transfers. the LSIFC949X pci function ignores this register when operating in the pci-x mode. reserved [2:0] this ?ld is reserved. register: 0x0d latency timer read/write latency timer [7:4] this register speci?s, in units of pci bus clocks, the value of the latency timer for this pci bus master. reserved [3:0] this ?ld is reserved. 7 0 cache line size 00000 0 0 0 7 0 latency timer 0x00 0 0 0 0
6-10 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x0e header type read only header type [7:0] this 8-bit register identi?s the layout of bytes 0x10 through 0x3f in con?uration space and also indicates whether this device is a single function or multifunction pci device. register: 0x0f reserved reserved [7:0] this register is reserved. register: 0x10?x13 i/o base address read/write this register maps the operating register set into i/o space. the LSIFC949X requires 256 bytes of i/o space for this register. hardware sets bit 0 to 0b1. bit 1 is reserved and returns 0b0 on all reads. 7 0 header type x0000000 7 0 reserved 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 i/o base address 000000000000000000000000 0 0 0 0 0 0 0 1
pci-x con?uration space register description 6-11 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. i/o base address [31:2] this ?ld contains the i/o base address. reserved [1:0] this ?ld is reserved. register: 0x14?x17 memory [0] base address low read/write the memory [0] base address low register and the memory [0] base address high register map scsi operating registers into memory space [0]. the memory [0] base address low register contains the lower 32 bits of the memory space [0] base address. hardware programs bits [9:0] to 0b0000000100, which indicates that the memory space [0] base address is 64 bits wide and that the memory data is not prefetchable. the LSIFC949X requires 1024 bytes of memory space. memory [0] base address low [31:0] this ?ld contains the memory [0] base address low address. register: 0x18?x1b memory [0] base address high read/write the memory [0] base address high register and the memory [0] base address low register map scsi operating registers into memory space [0]. the memory [0] base address high register contains the upper 32 bits of the memory space [0] base address. the LSIFC949X requires 1024 bytes of memory space. 31 24 23 16 15 8 7 0 memory [0] base address low 000000000000000000000 0 0 0 0 0 0 0 0 1 0 0 31 24 23 16 15 8 7 0 memory [0] base address high 00000000000000000000000000000000
6-12 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. memory [0] base address high [31:0] this ?ld contains the memory [0] base address high address. register: 0x1c?x1f memory [1] base address low read/write the memory [1] base address low register and the memory [1] base address high register map the ram into memory space [1]. the memory [1] base address low register contains the lower 32 bits of the memory space [1] base address. hardware programs bits [12:0] to 0b0000000000100, which indicates that the memory space [1] base address is 64 bits wide and that the memory data is not prefetchable. the LSIFC949X requires 64 kbytes of memory for memory space [1]. memory [1] base address low [31:0] this ?ld contains the memory [1] base address low address. register: 0x20?x23 memory [1] base address high read/write the memory [1] base address low register and the memory [1] base address high register map the ram into memory space [1]. the memory [1] base address low register contains the upper 32 bits of the memory space [1] base address. the LSIFC949X requires 64 kbytes of memory for memory space [1]. 31 24 23 16 15 8 7 0 memory [1] base address low 000000000000000000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 31 24 23 16 15 8 7 0 memory [1] base address high 00000000000000000000000000000000
pci-x con?uration space register description 6-13 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. memory [1] base address high [31:0] this ?ld contains the memory [1] base address high address. register: 0x24?x27 reserved reserved [31:0] this register is reserved. register: 0x28?x2b reserved reserved [31:0] this register is reserved. register: 0x2c?x2d subsystem vendor id read only svid subsystem vendor id [15:0] this 16-bit register uniquely identi?s the vendor that manufactures the add-in board or subsystem where the LSIFC949X resides. this register provides a mechanism for an add-in card vendor to distinguish their cards from 31 24 23 16 15 8 7 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 8 7 0 subsystem vendor id xxxxxxxxxxxxxxxx
6-14 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. those of another vendor, even if the cards use the same pci controller (and have the same vendor id and device id). the external serial eeprom can hold a vendor-speci?, 16-bit value for this register, which the board designer must obtain from the pci special interest group (pci-sig). register: 0x2e?x2f subsystem id read only sid subsystem id [15:0] this 16-bit register uniquely identifies the add-in board or subsystem where this pci device resides. this register provides a mechanism for an add-in card vendor to distinguish their cards from one another even if the cards use the same pci controller (and have the same vendor id and device id). the board designer can store a vendor-specific, 16-bit value in an external serial eeprom. register: 0x30?x33 expansion rom base address read/write this 32-bit register contains the base address and size information for the expansion rom. 15 8 7 0 subsystem id xxxxxxxxxxxxxxxx 31 24 23 16 15 8 7 0 expansion rom base address 000000000000000000000 0 0 0 0 0 0 0 0 0 00
pci-x con?uration space register description 6-15 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. expansion rom base address [31:11] these bits correspond to the upper 21 bits of the expansion rom base address. the host system detects the size of the external memory by ?st writing 0xffffffff to this register and then reading the register back. the LSIFC949X responds with zeros in all don? care locations. the least signi?ant one (1) that remains represents the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register returns ones in the upper 17 bits when written with 0xffffffff and read back. reserved [10:1] this ?ld is reserved. expansion rom enable 0 this bit controls whether the device accepts accesses to its expansion rom. setting this bit enables address decoding. depending on the system con?uration, the device can optionally use an expansion rom. note that to access the expansion rom, the user must also set bit 1 in the pci command register. register: 0x34 capabilities pointer read only capabilities pointer [7:0] this register indicates the location of the ?st extended capabilities register in pci con?uration space. the value of this register varies according to system con?uration. 7 0 capabilities pointer xxxxxxxx
6-16 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x35?x37 reserved reserved [23:0] this register is reserved. register: 0x38?x3b reserved reserved [31:0] this register is reserved. register: 0x3c interrupt line read/write interrupt line [7:0] this register communicates interrupt line routing information. power-on-self-test (post) software writes the routing information into this register as it con?ures the system. this register indicates the system interrupt controller input to which this pci function interrupt pin connects. system architecture determines the values in this register. 23 16 15 8 7 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 interrupt line 00000000
pci-x con?uration space register description 6-17 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x3d interrupt pin read only interrupt pin [7:0] the encoding of this read-only register is unique to each function on the LSIFC949X. it indicates which interrupt pin the function uses. the value for function [0] is 0x01, which indicates that function [0] presents interrupts on the inta/ pin. the value for function [1] is 0x02, which indicates that function [1] presents interrupts on the intb/ pin. register: 0x3e minimum grant read only min_gnt [7:0] this register speci?s the desired settings for latency timer values in units of 0.25 s. the min_gnt ?ld speci?s how long of a burst period the device needs. the LSIFC949X sets this register to 0x10, indicating a burst period of 4.0 s. 7 0 function [0] interrupt pin 00000001 function [1] interrupt pin 00000010 7 0 min_gnt 00010000
6-18 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x3f maximum latency read only max_lat [7:0] this register speci?s the desired settings for latency timer values in units of 0.25 s. the max_lat ?ld speci?s how often the device needs to gain access to the pci bus. the LSIFC949X sets this register to 0x06, indicating a burst period of 1.5 s. register: 0xxx power management capability id read only power management capability id [7:0] this register indicates the type of the current data structure. it is set to 0x01 to indicate the power management data structure. register: 0xxx power management next pointer read only 7 0 max_lat 00000110 7 0 power management capability id 00000001 7 0 power management next pointer xxxxxxxx
pci-x con?uration space register description 6-19 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. power management next pointer [7:0] this register contains the pointer to the next item in the pci function extended capabilities list. the value of this register varies according to system con?uration. register: 0xxx power management capabilities read only pme_support [15:11] these bits de?e the power management states in which the device asserts the power management event (pme) pin. the LSIFC949X clears these bits since the LSIFC949X does not provide a pme signal. d2_support 10 the pci function sets this bit since the LSIFC949X supports power management state d2. d1_support 9 the pci function sets this bit since the LSIFC949X supports power management state d1. aux_current [8:6] the pci function clears this ?ld since the LSIFC949X does not support aux_current. device speci? initialization 5 the pci function clears this bit since no special initializa- tion is required before a generic class device driver can use it. reserved 4 this bit is reserved. pme clock 3 the LSIFC949X clears this bit since the chip does not provide a pme pin. 15 8 7 0 power management capabilities 0 0 0 0 0 110000 00010
6-20 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. version [2:0] the pci function programs these bits to 0b010 to indicate that the LSIFC949X complies with the pci bus power management interface speci?ation, revision 1.2. register: 0xxx power management control/status read/write pme_status 15 the pci function clears this bit since the LSIFC949X does not support pme signal generation from d3 cold . data_scale [14:13] the pci function clears these bits since the LSIFC949X does not support the power management data register. data_select [12:9] the pci function clears these bits since the LSIFC949X does not support the power management data register. pme_enable 8 the pci function clears this bit since the LSIFC949X does not provide a pme signal and disables pme assertion. reserved [7:2] this ?ld is reserved. power state [1:0] these bits determine the current power state of the LSIFC949X. power states are: 15 8 7 0 power management control/status 00000000 0 0 0 0 0 000 0b00 d0 0b01 d1 0b10 d2 0b11 d3 hot
pci-x con?uration space register description 6-21 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0xxx power management bridge support extensions read only power management bridge support extensions [7:0] this register indicates pci bridge speci? functionality. the LSIFC949X always returns 0x00 in this register. register: 0xxx power management data read only power management data [7:0] this register provides an optional mechanism for the pci function to report state-dependent operating data. the LSIFC949X always returns 0x00 in this register. register: 0xxx msi capability id read only msi capability id [7:0] this register indicates the type of the current data structure. this register always returns 0x05, indicating message signaled interrupts (msi). 7 0 power management bridge support extensions 00000000 7 0 power management data 00000000 7 0 msi capability id 00000101
6-22 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0xxx msi next pointer read only msi next pointer [7:0] this register points to the next item in the pci functions extended capabilities list. the value of this register varies according to system con?uration. register: 0xxx msi message control read/write reserved [15:9] this ?ld is reserved. per-vector masking capable 8 if this bit is set, the device supports msi per-vector mask- ing. if this bit is cleared, the function does not support msi per-vector masking. this bit is read only. 64-bit address capable 7 the pci function sets this read only bit to indicate support of a 64-bit message address. multiple message enable [6:4] these read/write bits indicate the number of messages that the host allocates to the LSIFC949X. the host system software allocates all or a subset of the requested messages by writing to this ?ld. the number of allocated request messages must align to a power of two. table 6.3 provides the bit encoding of this ?ld. 7 0 msi next pointer xxxxxxxx 15 8 7 0 msi message control 0 0 0 0 0 0 0 x 1 0 0 0 0 0 0 0
pci-x con?uration space register description 6-23 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. multiple message capable [3:1] these read only bits indicate the number of messages that the LSIFC949X requests from the host. the host system software reads this ?ld to determine the number of requested messages. the number of requested messages must align to a power of two. the LSIFC949X sets this ?ld to 0b000 to request one message. all other encodings of this ?ld are reserved. msi enable 0 system software sets this bit to enable msi. to enable msi, the msi-x bit in the msi-x message control register must also be cleared (??. setting this bit enables the device to use msi to interrupt the host and request ser- vice. setting this bit prohibits the LSIFC949X from using the inta/ pin to request service from the host. setting this bit to mask interrupts on the inta/ pin is a violation of the pci speci?ation. register: 0xxx msi message lower address read/write table 6.3 multiple message enable field bit encoding bits [6:4] encoding number of allocated messages 0b000 1 0b001 2 0b010 4 0b011 8 0b100 16 0b101 32 0b110 reserved 0b111 reserved 31 24 23 16 15 8 7 0 msi message address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6-24 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. msi message address [31:2] this register contains message address bits [31:2] for the msi memory write transaction. the host system speci?s and dword aligns the message address. during the address phase, the LSIFC949X drives message address[1:0] to 0b00. reserved [1:0] this ?ld is reserved. register: 0xxx msi message upper address read/write msi message upper address [31:0] the LSIFC949X supports 64-bit msi message. this reg- ister contains the upper 32 bits of the 64-bit message address, which the system speci?s. the host system software can program this register to 0x0000 to force the pci function to generate 32-bit message addresses. register: 0xxx msi message data read/write msi message data [15:0] system software initializes this register by writing to it. the LSIFC949X sends an interrupt message by writing a dword to the address held in the msi message lower address and msi message upper address registers. this register forms bits [15:0] of the dword message that the pci function passes to the host. the pci function drives bits [31:16] of this message to 0x0000. 31 24 23 16 15 8 7 0 msi message upper address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 8 7 0 msi message data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pci-x con?uration space register description 6-25 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0xxx msi mask bits read/write msi mask bits [31:0] for each mask bit that is set, the device is prohibited from sending an associated message. refer to the pci speci?ation for a complete description of this regis- ter.egister register: 0xxx msi pending bits read only msi pending bits [31:0] for each pending bit that is set, the function has a pend- ing associated message. refer to the pci speci?ation for a complete description of this register. register: 0xxx msi-x capability id read only msi-x capability id [7:0] this register indicates the type of the current data structure. this register always returns 0x11, indicating msi-x. 31 24 23 16 15 8 7 0 msi mask bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 msi pending bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 msi-x capability id 00010001
6-26 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0xxx msi-x next pointer read only msi-x next pointer [7:0] this register points to the next item in the extended capa- bilities list. the value of this register varies according to system con?uration. register: 0xxx msi-x message control read/write msi-x enable 15 setting this bit enables the device to use msi-x to request service from the host. to enable msi-x, the msi enable bit in the msi message control register must be cleared (??. setting this bit also prohibits the device from using the inta/ pin to request service from the host. setting this bit to mask interrupts on the inta/ pin is a violation of the pci speci?ation. function mask 14 setting this bit masks all of the reset vectors that are associated with the function. this bit overrides the per- vector mask bit settings. clearing this bit enables the per- vector mask bit to determine if a vector is masked. reserved [13:11] this ?ld is reserved. table size [10:0] host software reads this ?ld to determine the msi-x table size. 7 0 msi-x next pointer xxxxxxxx 15 8 7 0 msi-x message control 0 0 0 0 0 x x x x x x x x x x x
pci-x con?uration space register description 6-27 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0xxx msi-x table offset read only msi-x table offset [31:3] this ?ld provides an offset from the address held in the base address registers of the device to the base of the msi-x table. table bir [2:0] this ?ld indicates which of the base address registers of the device, which are located at 0x10 in pci con?ura- tion space, maps the msi-x table into memory. table 6.4 provides the bir ?ld de?itions. register: 0xxx msi-x pba offset read only 31 24 23 16 15 8 7 0 msi-x table offset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x table 6.4 bir field de?itions bir value base address register 0 0x10 1 0x14 2 0x18 3 0x1c 4 0x20 5 0x24 6 reserved 7 reserved 31 24 23 16 15 8 7 0 msi-x pba offset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
6-28 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. msi-x pba offset [31:3] this ?ld contains an offset from one of the base address registers of the device that points to the msi-x pba. the lower 3 bits of this register are cleared (?? for a 32-bit aligned offset. pba bir [2:0] this ?ld indicates which of the base address registers of the device, which are located at 0x10 in pci con?ura- tion space, maps the msi-x pba into memory. table 6.4 provides the bir ?ld de?itions. register: 0xxx pci-x capability id read only pci-x capability id [7:0] this register indicates the type of the current data structure. this register returns 0x07, indicating the pci-x data structure. register: 0xxx pci-x next pointer read only pci-x next capabilities pointer [7:0] this register points to the next item in the devices capabilities list. the value of this register varies according to system con?uration. 7 0 pci-x capability id 00000111 7 0 pci-x next pointer xxxxxxxx
pci-x con?uration space register description 6-29 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0xxx pci-x command read/write reserved [15:7] this ?ld is reserved. maximum outstanding split transactions [6:4] these bits indicate the maximum number of split transactions the LSIFC949X can have outstanding at one time. the LSIFC949X uses the most recent value of this register each time it prepares a new sequence. note that if the LSIFC949X prepares a sequence before the setting of this ?ld changes, the pci function initiates the prepared sequence with the previous setting. table 6.5 provides the bit encodings for this ?ld. maximum memory read byte count [3:2] these bits indicate the maximum byte count the LSIFC949X uses when initiating a sequence with one of the burst memory read commands. table 6.6 provides the bit encodings for this ?ld. 15 8 7 0 pci-x command 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 table 6.5 maximum outstanding split transactions bits [6:4] encoding maximum outstanding split transactions 0b000 1 0b001 2 0b010 3 0b011 4 0b100 8 0b101 12 0b110 16 0b111 reserved
6-30 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. reserved 1 this bit is reserved. data parity error recovery enable 0 the host device driver sets this bit to allow the LSIFC949X to attempt to recover from data parity errors. if the user clears this bit and the LSIFC949X is operating in the pci-x mode, the LSIFC949X asserts serr/ when- ever the master data parity error bit in the pci status register is set. register: 0xxx pci-x status read/write reserved [31:30] this ?ld is reserved. received split completion error message 29 the LSIFC949X sets this bit upon receipt of a split completion message if the split completion error attribute bit is set. write a one (1) to this bit to clear it. designed maximum cumulative read size [28:26] these read only bits indicate a number greater than or equal to the maximum cumulative size of all outstanding burst memory read transactions for the LSIFC949X pci device. the pci function must report the smallest value that correctly indicates its capability. the LSIFC949X table 6.6 maximum memory read count bits [3:2] encoding maximum memory read byte count 0b00 512 0b01 1024 0b10 2048 0b11 reserved 31 24 23 16 15 8 7 0 pci-x status 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 x x x x x x x x x x x x x x x x
pci-x con?uration space register description 6-31 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. reports 0b100 in this ?ld to indicate a designed maximum cumulative read size of 16 kbytes. designed maximum outstanding split transactions [25:23] these read only bits indicate a number greater than or equal to the maximum number of all outstanding split transactions for the LSIFC949X pci device. the pci function must report the smallest value that correctly indicates its capability. the LSIFC949X reports 0b110 in this ?ld to indicate that the designed maximum number of outstanding split transactions is sixteen. designed maximum memory read byte count [22:21] these read only bits indicate a number greater than or equal to the maximum byte count for the LSIFC949X device. the pci function uses this count to initiate a sequence with one of the burst memory read commands. the pci function must report the smallest value that correctly indicates its capability. the LSIFC949X reports 0b10 in this ?ld to indicate that the designed maximum memory read bytes count is 2048. device complexity 20 the pci function clears this read only bit to indicate that the LSIFC949X is a simple device. unexpected split completion 19 the pci function sets this read only bit when it receives an unexpected split completion. once set, this bit remains set until software clears it. write a one (1) to this bit to clear it. split completion discarded 18 the pci function sets this read only bit when it discards a split completion. once set, this bit remains set until software clears it. write a one (1) to this bit to clear it. 133 mhz capable 17 the ma[8] power-on sense pin controls this read only bit. allowing the internal pull-downs to pull ma[8] low sets this bit and enables 133 mhz operation of the pci bus. pulling ma[8] high clears this bit and disables 133 mhz operation of the pci bus. refer to sen #s11066,
6-32 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. ?sifc949x design considerations, for details on the power-on sense pins. 64-bit device 16 the ma[9] power-on sense pin controls this read only bit. allowing the internal pull-downs to pull ma[9] low sets this bit and indicates a 64-bit pci address/data bus. pulling ma[9] high clears this bit and indicates a 32-bit pci address/data bus. if using the LSIFC949X on an add-in card, this bit must indicate the size of the cards pci address/data bus. refer to sen #s11066, ?sifc949x design considerations, for details on the power-on sense pins. bus number [15:8] these read only bits indicate the number of the LSIFC949X bus segment. the pci function uses this number as part of its requester id and completer id. this ?ld is read for diagnostic purposes only. device number [7:3] these read only bits indicate the device number of the LSIFC949X. the pci function uses this number as part of its requester id and completer id. this ?ld is read for diagnostic purposes only. function number [2:0] these read only bits indicate the number in the function number ?ld (ad[10:8]) of a type 0 pci con?uration transaction. the pci function uses this number as part of its requester id and completer id. this ?ld is read for diagnostic purposes only. 6.2 pci i/o space and memory space register description this section describes the host interface registers in the pci i/o space and in the pci memory space. these address spaces contain the fusion-mpt interface register set. pci memory space [0] and pci memory space [1] form the pci memory space. pci memory space [0] supports normal memory accesses while pci memory space [1] supports diagnostic memory accesses. for all registers except the diagnostic read/write data and diagnostic read/write address registers, access the address offset through pci i/o space. access to
pci i/o space and memory space register description 6-33 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. the diagnostic read/write data and diagnostic read/write address registers is available only through pci i/o space. when the LSIFC949X operates as a multifunction pci device, the entire pci memory and pci i/o space register sets are visible to both pci functions. when the LSIFC949X operates as a single function pci device, only pci function [0] register sets are accessible. table 6.7 de?es the pci i/o space address map. table 6.8 de?es the pci memory space [0] address map. table 6.7 pci i/o space address map 31 16 15 0 offset page system doorbell 0x00 6-34 write sequence 0x04 6-35 host diagnostic 0x08 6-36 test base address 0x0c 6-38 diagnostic read/write data 0x10 6-38 diagnostic read/write address 0x14 6-39 reserved 0x18?x2f host interrupt status 0x30 6-39 host interrupt mask 0x34 6-40 reserved 0x38?x3f request fifo 0x40 6-42 reply fifo 0x44 6-42 high priority request fifo 0x48 6-43 reserved 0x4c host index register 0x50 6-43 reserved 0x54?x7f
6-34 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 6.9 de?es the pci memory space [1] address map. a bit-level description of the pci memory and pci i/o spaces follows. register: 0x00 system doorbell read/write this register is a simple message passing mechanism that allows the system to pass single word messages to the embedded iop processor and vice versa. there is a unique system doorbell for each pci function. when a host system pci master writes to the host registers doorbell register, the LSIFC949X generates a maskable interrupt to the iop. the value written by the host system is available for the iop to read in the system interface registers doorbell register. the iop clears the interrupt status after reading the value. table 6.8 pci memory [0] address map 31 16 15 0 offset page system doorbell 0x00 6-34 write sequence 0x04 6-35 host diagnostic 0x08 6-36 test base address 0x0c 6-38 reserved 0x10?x2f host interrupt status 0x30 6-39 host interrupt mask 0x34 6-40 reserved 0x38?x3f request fifo 0x40 6-42 reply fifo 0x44 6-42 high priority request fifo 0x48 6-43 reserved 0x4c?x7f table 6.9 pci memory [1] address map 31 16 15 0 diagnostic memory 0x00 0x(sizeof(mem1) ? 1) 31 24 23 16 15 8 7 0 system doorbell 00000000000000000000000000000000
pci i/o space and memory space register description 6-35 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. conversely, when the iop processor writes to the system interface registers doorbell register, the LSIFC949X generates a maskable interrupt to the pci system. the host system can read the value written by the iop in the host registers doorbell register. the host system clears the interrupt status bit and interrupt pin by writing any value to the host registers interrupt status register. host doorbell value [31:0] during a write, this register contains the doorbell value that the host system passes to the iop. during a read, this register contains the doorbell value that the iop passes to the host system. register: 0x04 write sequence read/write this register provides a protection mechanism against inadvertent writes to the host diagnostic register. there is one write i/o register that is visible to both pci functions. the two pci functions physically share this register. reserved [31:4] this ?ld is reserved. write i/o key [3:0] to enable write access to the diagnostic read/write data , diagnostic read/write address , and host diagnostic register, perform ve data-speci? writes to the write i/o key. writing an incorrect value to the write i/o key invalidates the key sequence, and the host must rewrite the entire sequence. the write i/o key sequence is: 0x0004, 0x000b, 0x0002, 0x0007, and 0x000d. to disable write access to the diagnostic read/write data , diagnostic read/write address , and host diagnostic registers, write any value (except the write i/o key sequence) to the write i/o register. the diagnostic write 31 24 23 16 15 8 7 0 write sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01011
6-36 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. enable bit (bit 7 in the host diagnostic register) indicates the write access status. register: 0x08 host diagnostic read/write this register contains diagnostic controls and status information. there is one host diagnostic register that is visible to both pci functions. the two pci functions physically share this register. however, the reset history bit operates independently for each pci function. this register can only be written when bit 7 of this register is set. reserved [31:12] this ?ld is reserved. bist read enable 11 setting this bit enables reading the two bist results registers (0x18 and 0x1c) from the host. clear flash bad signature 10 write this bit to clear the bad signature bit (bit 6 of this register). prevent iop boot 9 set this bit to keep the iop in a reset state. bist all done 8 when this bit is set, all internal built-in self-test (bist) operations are complete. diagnostic write enable 7 the LSIFC949X sets this read-only bit when the host writes the correct write i/o key to the write sequence register. the LSIFC949X clears this bit when the host writes a value other than the write i/o key to the write sequence register. 31 24 23 16 15 8 7 0 host diagnostic 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001 00 0 x0
pci i/o space and memory space register description 6-37 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. flash bad signature 6 the LSIFC949X sets this bit if the iop arm966e-s processor encounters a bad flash signature when booting from flash rom. the LSIFC949X also sets the disarm bit (bit 1 in this register) to hold the iop arm processor in a reset state. the LSIFC949X maintains this state until the pci host clears both the flash bad signature and disarm bits. reset history 5 the LSIFC949X sets this bit if it experiences a power-on reset (por), pci reset, or testreset/. a host driver can clear this bit to help coordinate recovery between multiple driver instances in a multifunction pci implementation. diagnostic read/write enable 4 setting this bit enables access to the diagnostic read/write data and diagnostic read/write address registers. ttl interrupt 3 setting this bit con?ures pci inta/ as a ttl output. clearing this bit con?ures pci inta/ as an open-drain output. use this bit for test purposes only. reset adapter 2 setting this write-only bit causes a hard reset within the LSIFC949X. the bit self-clears after eight pci clock periods. after deasserting this bit, the iop arm processor executes from its default reset vector. disarm 1 setting this bit disables the iop arm processor. diagnostic memory enable 0 setting this bit enables diagnostic memory accesses through pci memory space [1]. clearing this bit disables diagnostic memory accesses to pci memory space [1] and returns 0xffff on reads.
6-38 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x0c test base address read/write this register speci?s the base address for memory space [1] accesses. there is one test base address register that is visible to both pci functions. the two pci functions physically share this register. because diagnostic memory is visible only to pci function [0], pci function [1] cannot write to this register. test base address [31:16] the number of signi?ant bits is determined by the size of pci memory space [1] in the serial eeprom. reserved [15:0] this ?ld is reserved. register: offset 0x10 diagnostic read/write data read/write this register reads or writes dword locations on the LSIFC949X internal bus. this register is only accessible through pci i/o space and returns 0xffffffff if read through pci memory space. the host can enable write access to this register by writing the correct write i/o key to the write sequence register and setting bit 4, the diagnostic write enable bit, of the host diagnostic register. a write of any value other than the correct write i/o key to the write sequence register disables write access to this register. there is one diagnostic read/write data register that is visible to both pci functions. the two pci functions physically share this register. 31 24 23 16 15 8 7 0 test base address 0000000000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 24 23 16 15 8 7 0 diagnostic read/write data 00000000000000000000000000000000
pci i/o space and memory space register description 6-39 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. diagnostic read/write data [31:0] using this register, the LSIFC949X reads/writes data at the address that the diagnostic read/write address register speci?s. register: 0x14 diagnostic read/write address read/write this register speci?s a dword location on the internal bus. the address increments by a dword whenever the host system accesses the diagnostic read/write address register. this register is only accessible through pci i/o space and returns 0xffffffff if read through pci memory space. the host can enable write access to this register by writing the correct write i/o key to the write sequence register and setting bit 4, the diagnostic write enable bit, of the host diagnostic register. a write of any value other than the correct write i/o key to the write sequence register disables write access to this register. there is one diagnostic read/write address register that is visible to both pci functions. the two pci functions physically share this register. diagnostic read/write address [31:0] this register holds the address that the diagnostic read/write data register writes data to or reads data from. register: 0x30 host interrupt status read only 31 24 23 16 15 8 7 0 diagnostic read/write address 00000000000000000000000000000000 31 24 23 16 15 8 7 0 host interrupt status 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x0 x x0
6-40 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. this register provides read-only interrupt status information to the pci host. a write to this register of any value clears the associated system doorbell interrupt. there is a unique host interrupt status register for each pci function. iop doorbell status 31 the LSIFC949X sets this bit when the iop receives a message from the system doorbell but has yet to process it. the iop processes the system doorbell message by clearing the corresponding system request interrupt. reserved [30:4] this ?ld is reserved. reply interrupt 3 the LSIFC949X sets this bit when the reply post fifo is not empty. the LSIFC949X generates a pci interrupt when this bit is set and the corresponding mask bit in the host interrupt mask register is cleared. reserved [2:1] this ?ld is reserved. system doorbell interrupt 0 the LSIFC949X sets this bit when the iop writes a value to the system doorbell. the host can clear this bit by writing any value to this register. the LSIFC949X generates a pci interrupt when this bit is set and the corresponding mask bit in the host interrupt mask register is cleared. register: 0x34 host interrupt mask read/write this register masks and/or routes the interrupt conditions that the host interrupt status register reports. there is a unique host interrupt mask register for each pci function. 31 24 23 16 15 8 7 0 host interrupt mask x x x x x x x x x x x x x x x x x x x x x x00 x x x x1 x x1
pci i/o space and memory space register description 6-41 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. reserved [31:10] this ?ld is reserved. interrupt request routing mode [9:8] this ?ld routes pci interrupts to the intx/ pins according to the bit encodings in table 6.10 . if the host system enables msi, the LSIFC949X does not signal pci interrupts on the intx/ pins. reserved [7:4] this ?ld is reserved. reply interrupt mask 3 setting this bit masks reply interrupts and prevents the assertion of a pci interrupt for all reply interrupt conditions. reserved [2:1] this ?ld is reserved. doorbell interrupt mask 0 setting this bit masks system doorbell interrupts and prevents the assertion of a pci interrupt for all system doorbell interrupt conditions. table 6.10 interrupt signal routing bit [9:8] encodings interrupt signal routing 0b00 intx/ and alt_intx/ 0b01 intx/ only 0b10 1 1. the LSIFC949X does not support alternate interrupt signals (no device pins are provided). programming this ?ld to 0b10 effectively disables pci interrupts for the given pci function. alt_intx/ only 0b11 intx/ and alt_intx/
6-42 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x40 request fifo read/write this register provides request free message frame addresses (mfas) to the host system on reads and accepts request post mfas from the host system on writes. there is one request fifo register that is visible to both pci functions. the two pci functions physically share this register. request fifo [31:0] for reads, the request free mfa is empty and this register contains 0xffffffff. for writes, the register contains the request post mfa. register: 0x44 reply fifo read/write this register provides reply post mfas to the host system on reads and accepts reply free mfas from the host system on writes. there is one unique reply fifo register for each pci function. reply fifo [31:0] for reads, the request free mfa is empty and this register contains 0xffffffff. for writes, the register contains the reply free mfa. 31 24 23 16 15 8 7 0 request fifo 11111111111111111111111111111111 31 24 23 16 15 8 7 0 reply fifo 11111111111111111111111111111111
pci i/o space and memory space register description 6-43 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. register: 0x48 high priority request fifo read/write the high priority request fifo is used to provide high priority request free mfas to the host on reads, and to accept high priority request post mfas from the host on writes. these mfas will not be automatically pulled even if the enhwpull bit is set. this is a hardware fifo with a maximum depth of 256 32-bit entries.there is one high priority request fifo register which is visible to both, but physically shared between the two pci functions. pci function information is saved with the mfa in the singular high priority request fifo. high priority request fifo [31:0] for reads, the high priority request fifo is empty and this register contains 0xffffffff. for writes, the regis- ter contains the high priority request post mfa. register: 0x50 host index register read/write these registers are used with the outbound reply option (altreplypost method) to enable host-resident reply post queues. reserved [31:14] this ?ld is reserved. host index value [13:0] the host index provides an indication of which reply post mfas the host system has processed, and 31 24 23 16 15 8 7 0 high priority request fifo 11111111111111111111111111111111 31 24 23 16 15 8 7 0 reply fifo 11111111111111111111111111111111
6-44 registers copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. generates reply interrupts when the altreplypost option is enabled. there is a unique host index register associated with each pci function.
LSIFC949X dual channel fibre channel i/o processor technical manual 7-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. chapter 7 speci?ations this chapter provides a description of the dc and ac electrical characteristics of the LSIFC949X dual channel fibre channel i/o processor chip, and the available packaging. the chapter contains the following sections: ? section 7.1, ?lectrical requirements ? section 7.2, ?c timing ? section 7.3, ?ackaging 7.1 electrical requirements table 7.1 provides absolute maximum stress ratings for the LSIFC949X, while table 7.2 speci?s the normal operating conditions. table 7.3 through table 7.10 specify the input and output electrical characteristics. table 7.1 absolute maximum stress ratings 1 1. stresses beyond those listed in this table may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied. symbol parameter min max unit test conditions t stg storage temperature ? 55 150 ?c v dd supply voltage ? 0.5 4.5 v v in input voltage v ss ? 0.3 v dd + 0.3 v i lp 2 2. see eia/jesd78 for further information on latch-up testing. latch-up current 150 ma eia/jesd78 esd hbm electrostatic discharge ? human body model (hbm) 1.5 kv jesd-a114-b
7-2 speci?ations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 7.2 operating conditions 1 1. conditions that exceed the operating limits may cause the device to function incorrectly. symbol parameter min max unit test conditions v ddc 2 2. refer to note 1 at the end of table 4.6 (page 4-17) for instructions on power sequencing for the LSIFC949X. core supply voltage 1.14 1.26 v v ddio i/o supply voltage 3.0 3.6 v i ddc 3 3. the maximum current speci?ation for i ddc includes any current drawn by the analog pll. core supply current 1100 ma i ddio i/o supply current 950 ma t a 4 4. the LSIFC949X does not require a heatsink when operating within the temperature range speci?d in this table. operating free air 0 70 ?c jma thermal resistance (junction to moving air) 11.2 ?c/w table 7.3 capacitance symbol parameter min max unit test conditions c i input capacitance of input pads 7 pf c io input capacitance of i/o pads 10 pf table 7.4 input signals (fault1/, fault0/, mode[7:0], switch, cpci_en/) symbol parameter min max unit test conditions v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage v ss ? 0.3 0.2 v dd v i in input leakage 10 10 a
electrical requirements 7-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 7.5 schmitt input signals (refclk, tck, tdi, trst/, tms_chip, tms_ice) symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage v ss ? 0.3 0.8 v i in input leakage 10 10 a table 7.6 4 ma bidirectional signals (lipreset/, odis1, odis0, bypass1/, bypass0/, md[31:0], ma[23:0], mwe[1:0]/, flashcs/, bwe[3:0]/, ramcs/, mp[3:0], scl, sda, rxlos1, rxlos0, adsc/, adv/, tdo) symbol parameter min max unit test conditions v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage v ss ? 0.3 0.2 v dd v v oh output high voltage 2.4 v dd v ? 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage ? 10 10 a table 7.7 8 ma bidirectional signals (moddef1[2:0], moddef0[2:0], gpio[5:0], moe[1:0]/, led[4:0]/, mclk) symbol parameter min max unit test conditions v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage v ss ? 0.3 0.2 v dd v v oh output high voltage 2.4 v dd v ? 8ma v ol output low voltage v ss 0.4 v 8 ma i oz 3-state leakage ? 10 10 a
7-4 speci?ations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 7.2 ac timing the ac timing characteristics described in this section apply over the entire range of operating conditions. chip timings are based on simulation at worst-case voltage, temperature, and processing. timings have been developed with a load capacitance of 50 pf. table 7.8 pci input signals (pciclk, gnt/, idsel, rst/) symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd 5.5 v 3.3 v pci system v il input low voltage ? 0.5 0.3 v dd v 3.3 v pci system table 7.9 pci bidirectional signals (ad[63:0], c_be[7:0]/, frame/, irdy/, trdy/, stop/, perr/, par, ack64/, enum/, 64en/) symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd 5.5 v 3.3 v pci system v il input low voltage ? 0.5 0.3 v dd v 3.3 v pci system v oh output high voltage 0.9 v dd v dd v ? 0.5 ma v ol output low voltage v ss 0.1 v dd v 1.5 ma i oz 3-state leakage ? 10 10 a table 7.10 pci output signals (par64, req/, req64/, devsel/, serr/, inta/, intb/) symbol parameter min max unit test conditions v oh output high voltage 0.9 v dd v dd v ? 0.5 ma v ol output low voltage v ss 0.1 v dd v 1.5 ma i oz 3-state leakage ? 10 10 a
ac timing 7-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 7.2.1 pci/pci-x interface timings the LSIFC949X pci/pci-x signals conform to the electrical and timing standards as shown in the pci local bus speci?ation, revision 2.3, and the pci-x addendum to the pci local bus speci?ation, revision 2.0. all hardware validation testing performed by lsi logic guarantees that the LSIFC949X meets or exceeds the speci?ations contained in those documents. 7.2.2 fibre channel interface timings the LSIFC949X receiver and transmitter serial differential signal pairs conform to the electrical and timing standards as shown in the fibre channel physical interface speci?ation (fc-pi, rev. 11). all hardware validation testing performed by lsi logic guarantees that the LSIFC949X meets or exceeds the speci?ations contained in that document. 7.2.3 memory interface timings see the following sections for memory interface timings descriptions: ? section 7.2.3.1, ?sram timings, on page 7-6 ? section 7.2.3.2, ?lash rom read timings, on page 7-7 ? section 7.2.3.3, ?lash rom write timings, on page 7-8
7-6 speci?ations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 7.2.3.1 ssram timings figure 7.1 ssram read/write/read timing waveforms mclk ma/ctl md moe[0]/ moe[1]/ addr(x) adsc addr(y) adsc addr(y) addr (y+1) addr(z) adsc addr(z) addr(z) addr addr(z+2) (z+1) read data invalid data(y) data (y+1) read data(z+2) read data(z+1) read data(z) t cyc t wdv t wdh rd deselect and bus wr address and select wr data wr data wr deselect, rd address, and select rd pipe wait rd data rd data turnaround t rsu t rh t enov t ohz t olz t oev table 7.11 ssram read/write/read timings symbol parameter min max unit t cyc mclk cycle time 9.411 9.413 ns t rsu read setup time 4.1 ns t rh read hold time 0 ns t wdv 1 1. refer to sen #11066, ?sifc949x design considerations? for further details regarding write valid and write hold times for md[31:0]. write valid time md[31:0], mp[3:0] 5.0 ns ma[21:0] 6.4 ns control signals 2 2. control signals include mwe[1:0]/, bwe[3:0]/, ramcs/, adsc/, and adv/ . 6.6 ns t wdh 1 write hold time md[31:0], mp[3:0] 0.1 ns ma[21:0] 0.3 ns control signals 2 0.6 ns t oev output enable valid 0.75 ns t olz data low impedance 0.5 2.5 ns t ohz data high impedance 0 1.75 ns t enov output enable nonoverlap 0 ns
ac timing 7-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 7.2.3.2 flash rom read timings figure 7.2 flash rom read timing waveforms mclk ma md flashcs/ moe[1]/ addr(?) addr(x) addr(y) read/write data t cyc idle or s-xfer f-addr f-addr f-wait(n) f-data f-turn f-turn f-addr t hz t as data(x) t rh bwe[3]/ m-state n = 16 t rs t ah f-addr table 7.12 flash rom read timings symbol parameter min max unit t cyc mclk cycle time 9.410 9.413 ns t as address setup time ? 5.0 1 1. address setup time defaults to one (1) mclk but may be programmed to zero (0) mclks using the serial eeprom. 1 mclk 2 ns t ah address hold time 0 ns t rs read setup time 7 ns t rh read hold time 0 ns t hz data high impedance 0 32 ns
7-8 speci?ations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 7.2.3.3 flash rom write timings figure 7.3 flash rom write timing waveforms addr(?) addr(x) addr(y) read/write data t cyc idle or s-xfer f-addr f-addr f-wait(n) f-data idle f-addr f-addr data(x) n = 16 t as data(y) t ws t ah t wh f-turn mclk ma md flashcs/ moe[1]/ bwe[3]/ m-state table 7.13 flash rom write timings symbol parameter min max unit t cyc mclk cycle time 9.410 9.413 ns t as address setup time ? 5.0 1 1. address setup time defaults to one (1) mclk but may be programmed to zero (0) mclks using the serial eeprom. 1 mclk 2 ns t ah address hold time 1 mclk ns t ws 2 2. the default write setup time is 17 ns. write setup time 2 3 3. programmed using the serial eeprom. 32 mclk t wh write hold time 1 mclk ns
packaging 7-9 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. 7.3 packaging figure 7.4 illustrates the signal locations for the 544 flip chip plastic ball grid array (fpbga). also in this section are two listings of he alphanumeric pads: table 7.14 lists them by pbga position, and table 7.15 by signal name. and a mechanical drawing of the package for the LSIFC949X ( figure 7.5 on page 7-14 ). figure 7.4 LSIFC949X 544-pin fpbga top view
7-10 speci?ations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 7.14 alphanumeric pad listing by pbga position m5 vddio33 m6 vss m7 vddio33 m12 vss m13 vdd12 m14 vss m15 vdd12 m20 vss m21 vddio33_pcix m22 vss m23 vddio33_pcix m24 vss m25 vss m26 ad[8] n1 rxbvss0 n2 txvss0 n3 txbvdd0 n4 rx0+ n5 rx0- n6 tx0+ n7 tx0- n12 vdd12 n13 vss n14 vdd12 n15 vss n20 vss n21 ad[5] n22 ad[1] n23 ad[2] n24 vss n25 ad[7] n26 ad[9] p1 rxbvdd0 p2 rxvss0 p3 txbvss1 p4 rx1+ p5 rx1- p6 tx1- p7 tx1+ p12 vss p13 vdd12 p14 vss p15 vdd12 p20 vss p21 ad[11] p22 c_be[0]/ p23 vss p24 ad[12] p25 vss p26 vss r1 rxvdd0 r2 txbvdd1 r3 vss r4 mxsvdd r5 vss r6 vddio33 r7 vss r12 vdd12 r13 vss r14 vdd12 ball # signal ball # signal a2 vss a3 md[11] a4 md[15] a5 md[21] a6 md[22] a7 md[26] a8 md[28] a9 ma[12] a10 ma[10] a11 ma[6] a12 ma[0] a13 vss a14 vss a15 vss a16 vss a17 ad[38] a18 vss a19 vss a20 ad[49] a21 vss a22 ad[52] a23 ad[55] a24 vss a25 vddio33_pcix b1 vddio33 b2 vss b3 vss b4 md[12] b5 md[16] b6 md[20] b7 md[25] b8 md[27] b9 ma[16] b10 ma[11] b11 ma[9] b12 ma[5] b13 ma[3] b14 vss b15 ad[35] b16 vss b17 ad[39] b18 vss b19 ad[48] b20 vss b21 ad[53] b22 ad[54] b23 vss b24 vss b25 vss b26 vss c1 md[9] c2 vss c3 vss c4 md[10] c5 md[13] c6 md[19] c7 vddio33 c8 vddio33 c9 ma[17] c10 ma[15] c11 vss c12 vss c13 ma[4] c14 ad[34] c15 vddio33 c16 vddio33 c17 vss c18 vss c19 vss c20 vss c21 vss c22 vss c23 vss c24 vss c25 vss c26 vss d1 md[6] d2 md[8] d3 vss d4 vss d5 md[18] d6 md[14] d7 vss d8 vss d9 ma[23] d10 ma[18] d11 vddio33 d12 vddio33 d13 ma[13] d14 ma[1] d15 vss d16 vss d17 ad[42] d18 vss d19 vddio33_pcix d20 vddio33_pcix d21 vss d22 ad[46] d23 vss d24 vss d25 vss d26 ad[57] e1 md[1] e2 md[5] e3 md[4] e4 bwe3/ e5 vss e6 md[17] e7 vddio33 e8 vddio33 e9 md[31] e10 ma[21] e11 vss e12 vss e13 ma[14] e14 ma[2] e15 vddio33_pcix e16 vddio33_pcix e17 ad[44] e18 vss e19 vss e20 vss e21 ad[47] e22 vss e23 ad[58] e24 vss e25 vss e26 ad[60] f1 md[0] f2 md[2] f3 md[3] f4 md[7] f5 mclk f6 mp[3] f7 md[24] f8 md[30] f9 ma[19] f10 ma[22] f11 vddio33 f12 vddio33 f13 ma[7] f14 ad[32] f15 vss f16 vss f17 ad[45] f18 ad[36] f19 ad[40] f20 vss f21 ad[51] f22 vss f23 ad[56] f24 ad[59] f25 vss f26 ad[61] g1 mp[0] g2 mp[1] g3 vss g4 vddio33 g5 vss g6 mwe0/ g7 mp[2] g8 md[23] g9 md[29] g10 ma[20] g11 vss g12 vss g13 ma[8] g14 ad[33] g15 vddio33_pcix g16 vddio33_pcix g17 ad[37] g18 ad[41] g19 ad[43] g20 ad[50] g21 ad[62] g22 vddio33_pcix g23 vss g24 vddio33_pcix g25 ad[63] g26 vss h1 adsc/ h2 adv/ h3 vss h4 vddio33 h5 vss h6 mode[6] h7 moe0/ h20 vss h21 vss h22 vddio33_pcix h23 vss h24 vddio33_pcix h25 vss h26 par64 j1 mode[5] j2 ramcs/ j3 flashcs/ j4 bwe1/ j5 bwe2/ j6 mode[0] j7 mode[7] j20 c_be[4]/ j21 req64/ j22 c_be[5]/ j23 c_be[6]/ j24 ack64/ j25 ad[0] j26 vss k1 mode[3] k2 mode[4] k3 nc k4 moe1/ k5 mwe1/ k6 bwe0/ k7 mode[1] k20 c_be[7]/ k21 vss k22 vss k23 vss k24 vss k25 ad[3] k26 ad[4] l1 vss l2 mode[2] l3 mxsvdd l4 vss l5 vddio33 l6 vss l7 vddio33 l20 vss l21 vddio33_pcix l22 vss l23 vddio33_pcix l24 vss l25 vss l26 ad[6] m1 txvdd0 m2 txbvss0 m3 mxsvdd m4 vss ball # signal ball # signal ball # signal 1. nc pins are not connected.
packaging 7-11 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 7.14 alphanumeric pad listing by pbga position (cont.) ae3 vss ae4 vss ae5 vss ae6 moddef0[4] ae7 moddef1[4] ae8 moddef1[2] ae9 led[4]/ ae10 blueled/ ae11 gpio[1] ae12 gpio[5] ae13 switch ae14 vss ae15 ad[30] ae16 vss ae17 ad[26] ae18 vss ae19 ad[18] ae20 vss ae21 bzrset ae22 bzvdd ae23 vss ae24 pcipllvdd ae25 vss ae26 vddio33 af2 vddio33 af3 vss af4 vss af5 moddef0[3] af6 moddef0[2] af7 moddef1[3] af8 moddef1[1] af9 led[0]/ af10 gpio[0] af11 gpio[4] af12 nc af13 vss af14 vss af15 vss af16 vss af17 ad[27] af18 vss af19 vss af20 ad[17] af21 vss af22 pciclk af23 vss af24 vss af25 vss ball # signal ball # signal r15 vss r20 vddio33_pcix r21 vss r22 vddio33_pcix r23 vss r24 vddio33_pcix r25 ad[13] r26 ad[10] t1 txvss1 t2 txvdd1 t3 vss t4 mxsvdd t5 vss t6 vddio33 t7 vss t20 vddio33_pcix t21 vss t22 vddio33_pcix t23 vss t24 vddio33_pcix t25 vss t26 vss u1 rxbvss1 u2 rxbvdd1 u3 rxvss1 u4 vss u5 tdiodevss u6 tdiodep u7 refclkp u20 ad[15] u21 devsel/ u22 vss u23 perr/ u24 vss u25 par u26 c_be[1]/ v1 rxvdd1 v2 rtrim v3 nc v4 refclkb v5 scan_mode v6 refclkn v7 test_reset/ v20 vss v21 ad[14] v22 vss v23 trdy/ v24 serr/ v25 vss v26 vss w1 rtck_ice w2 tck_ice w3 vddio33 w4 vss w5 vddio33 w6 scan_enable w7 tdo_ice w20 stop/ w21 vss w22 vss w23 vddio33_pcix w24 vss w25 vss w26 vss y1 trst_ice/ y2 tms_ice y3 vddio33 y4 vss y5 vddio33 y6 tdi_ice y7 moddef0[0] y8 fault0/ y9 led[2]/ y10 gpio[2] y11 vddio33 y12 vddio33 y13 cpci_en/ y14 ad[28] y15 vss y16 vss y17 vss y18 ad[19] y19 c_be[2]/ y20 vss y21 vss y22 vss y23 vddio33_pcix y24 vss y25 req/ y26 idsel aa1 tck aa2 tms aa3 tdi aa4 serial_clock aa5 proc_mon aa6 moddef0[1] aa7 rxlos1 aa8 led[1]/ aa9 gpio[3] aa10 bypass1/ aa11 vss aa12 vss aa13 nc aa14 ad[29] aa15 vddio33 aa16 vddio33 aa17 ad[21] aa18 ad[23] aa19 ad[20] aa20 ad[16] aa21 gnt/ aa22 frame/ aa23 enum/ aa24 intb/ aa25 vss aa26 rst/ ab1 trst/ ab2 iddtn ab3 serial_data ab4 tdo ab5 uartrx ab6 moddef1[0] ab7 vss ab8 vss ab9 odis1 ab10 rxlos0 ab11 vddio33 ab12 vddio33 ab13 nc ab14 ad[24] ab15 vss ab16 vss ab17 ad[22] ab18 vss ab19 vddio33 ab20 vddio33 ab21 vss ab22 vss ab23 irdy/ ab24 inta/ ab25 vss ab26 vss ac1 tn ac2 fsela ac3 refpllvss ac4 uarttx ac5 odis0 ac6 vss ac7 vddio33 ac8 vddio33 ac9 bypass0/ ac10 fault1/ ac11 vss ac12 vss ac13 nc ac14 ad[25] ac15 vddio33_pcix ac16 vddio33_pcix ac17 c_be[3]/ ac18 vss ac19 vss ac20 vss ac21 vss ac22 vss ac23 vss ac24 vss ac25 nc ac26 64_en/ ad1 vss ad2 refpllvdd ad3 vss ad4 vss ad5 vss ad6 vss ad7 vss ad8 vss ad9 lipreset/ ad10 led[3]/ ad11 vddio33_pcix ad12 vddio33_pcix ad13 nc ad14 ad[31] ad15 vss ad16 vss ad17 vss ad18 vss ad19 vddio33 ad20 vddio33 ad21 vss ad22 vss ad23 pcipllvss ad24 vss ad25 vss ad26 vss ae1 vss ae2 vss ball # signal ball # signal ball # signal 1. nc pins are not connected.
7-12 speci?ations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 7.15 alphanumeric pad listing by signal name scan_enable w6 scan_mode v5 serial_clock aa4 serial_data ab3 serr/ v24 stop/ w20 switch ae13 tck aa1 tck_ice w2 tdi aa3 tdiodep u6 tdiodevss u5 tdi_ice y6 tdo ab4 tdo_ice w7 test_reset/ v7 tms aa2 tms_ice y2 tn ac1 trdy/ v23 trst/ ab1 trst_ice/ y1 tx0+ n6 tx0- n7 tx1+ p7 tx1- p6 txbvdd0 n3 txbvdd1 r2 txbvss0 m2 txbvss1 p3 txvdd0 m1 txvdd1 t2 txvss0 n2 txvss1 t1 uartrx ab5 uarttx ac4 vdd12 m13 vdd12 m15 vdd12 n12 vdd12 n14 vdd12 p13 vdd12 p15 vdd12 r12 vdd12 r14 vddio33 b1 vddio33 c7 vddio33 c8 vddio33 c15 vddio33 c16 vddio33 d11 vddio33 d12 vddio33 e7 vddio33 e8 vddio33 f11 vddio33 f12 vddio33 g4 vddio33 h4 vddio33 l5 vddio33 l7 vddio33 m5 signal ball #l signal ball # 64_en/ ac26 ack64/ j24 adsc/ h1 adv/ h2 ad[0] j25 ad[1] n22 ad[2] n23 ad[3] k25 ad[4] k26 ad[5] n21 ad[6] l26 ad[7] n25 ad[8] m26 ad[9] n26 ad[10] r26 ad[11] p21 ad[12] p24 ad[13] r25 ad[14] v21 ad[15] u20 ad[16] aa20 ad[17] af20 ad[18] ae19 ad[19] y18 ad[20] aa19 ad[21] aa17 ad[22] ab17 ad[23] aa18 ad[24] ab14 ad[25] ac14 ad[26] ae17 ad[27] af17 ad[28] y14 ad[29] aa14 ad[30] ae15 ad[31] ad14 ad[32] f14 ad[33] g14 ad[34] c14 ad[35] b15 ad[36] f18 ad[37] g17 ad[38] a17 ad[39] b17 ad[40] f19 ad[41] g18 ad[42] d17 ad[43] g19 ad[44] e17 ad[45] f17 ad[46] d22 ad[47] e21 ad[48] b19 ad[49] a20 ad[50] g20 ad[51] f21 ad[52] a22 ad[53] b21 ad[54] b22 ad[55] a23 ad[56] f23 ad[57] d26 ad[58] e23 ad[59] f24 ad[60] e26 ad[61] f26 ad[62] g21 ad[63] g25 blueled/ ae10 bwe0/ k6 bwe1/ j4 bwe2/ j5 bwe3/ e4 bypass0/ ac9 bypass1/ aa10 bzrset ae21 bzvdd ae22 cpci_en/ y13 c_be[0]/ p22 c_be[1]/ u26 c_be[2]/ y19 c_be[3]/ ac17 c_be[4]/ j20 c_be[5]/ j22 c_be[6]/ j23 c_be[7]/ k20 devsel/ u21 enum/ aa23 fault0/ y8 fault1/ ac10 flashcs/ j3 frame/ aa22 fsela ac2 gnt/ aa21 gpio[0] af10 gpio[1] ae11 gpio[2] y10 gpio[3] aa9 gpio[4] af11 gpio[5] ae12 iddtn ab2 idsel y26 inta/ ab24 intb/ aa24 irdy/ ab23 led[0]/ af9 led[1]/ aa8 led[2]/ y9 led[3]/ ad10 led[4]/ ae9 lipreset/ ad9 ma[0] a12 ma[1] d14 ma[2] e14 ma[3] b13 ma[4] c13 ma[5] b12 ma[6] a11 ma[7] f13 ma[8] g13 ma[9] b11 ma[10] a10 ma[11] b10 ma[12] a9 ma[13] d13 ma[14] e13 ma[15] c10 ma[16] b9 ma[17] c9 ma[18] d10 ma[19] f9 ma[20] g10 ma[21] e10 ma[22] f10 ma[23] d9 mclk f5 md[0] f1 md[1] e1 md[2] f2 md[3] f3 md[4] e3 md[5] e2 md[6] d1 md[7] f4 md[8] d2 md[9] c1 md[10] c4 md[11] a3 md[12] b4 md[13] c5 md[14] d6 md[15] a4 md[16] b5 md[17] e6 md[18] d5 md[19] c6 md[20] b6 md[21] a5 md[22] a6 md[23] g8 md[24] f7 md[25] b7 md[26] a7 md[27] b8 md[28] a8 md[29] g9 md[30] f8 md[31] e9 moddef0[0] y7 moddef0[1] aa6 moddef0[2] af6 moddef0[3] af5 moddef0[4] ae6 moddef1[0] ab6 moddef1[1] af8 moddef1[2] ae8 moddef1[3] af7 moddef1[4] ae7 mode[0] j6 mode[1] k7 mode[2] l2 mode[3] k1 mode[4] k2 mode[5] j1 mode[6] h6 mode[7] j7 moe0/ h7 moe1/ k4 mp[0] g1 mp[1] g2 mp[2] g7 mp[3] f6 mwe0/ g6 mwe1/ k5 mxsvdd l3 mxsvdd m3 mxsvdd r4 mxsvdd t4 nc k3 nc v3 nc aa13 nc ab13 nc ac13 nc ac25 nc ad13 nc af12 odis0 ac5 odis1 ab9 par u25 par64 h26 pciclk af22 pcipllvdd ae24 pcipllvss ad23 perr/ u23 proc_mon aa5 ramcs/ j2 refclkb v4 refclkn v6 refclkp u7 refpllvdd ad2 refpllvss ac3 req/ y25 req64/ j21 rst/ aa26 rtck_ice w1 rtrim v2 rx0+ n4 rx0- n5 rx1+ p4 rx1- p5 rxbvdd0 p1 rxbvdd1 u2 rxbvss0 n1 rxbvss1 u1 rxlos0 ab10 rxlos1 aa7 rxvdd0 r1 rxvdd1 v1 rxvss0 p2 rxvss1 u3 signal ball # signal ball # signal ball # 1. nc pins are not connected.
packaging 7-13 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. table 7.15 alphanumeric pad listing by signal name (cont.) vss ac11 vss ac12 vss ac18 vss ac19 vss ac20 vss ac21 vss ac22 vss ac23 vss ac24 vss ad1 vss ad3 vss ad4 vss ad5 vss ad6 vss ad7 vss ad8 vss ad15 vss ad16 vss ad17 vss ad18 vss ad21 vss ad22 vss ad24 vss ad25 vss ad26 vss ae1 vss ae2 vss ae3 vss ae4 vss ae5 vss ae14 vss ae16 vss ae18 vss ae20 vss ae23 vss ae25 vss af3 vss af4 vss af13 vss af14 vss af15 vss af16 vss af18 vss af19 vss af21 vss af23 vss af24 vss af25 signal ball # signal ball # vddio33 m7 vddio33 r6 vddio33 t6 vddio33 w3 vddio33 w5 vddio33 y3 vddio33 y5 vddio33 y11 vddio33 y12 vddio33 aa15 vddio33 aa16 vddio33 ab11 vddio33 ab12 vddio33 ab19 vddio33 ab20 vddio33 ac7 vddio33 ac8 vddio33 ad19 vddio33 ad20 vddio33 ae26 vddio33 af2 vddio33_pcix a25 vddio33_pcix d19 vddio33_pcix d20 vddio33_pcix e15 vddio33_pcix e16 vddio33_pcix g15 vddio33_pcix g16 vddio33_pcix g22 vddio33_pcix g24 vddio33_pcix h22 vddio33_pcix h24 vddio33_pcix l21 vddio33_pcix l23 vddio33_pcix m21 vddio33_pcix m23 vddio33_pcix r20 vddio33_pcix r22 vddio33_pcix r24 vddio33_pcix t20 vddio33_pcix t22 vddio33_pcix t24 vddio33_pcix w23 vddio33_pcix y23 vddio33_pcix ac15 vddio33_pcix ac16 vddio33_pcix ad11 vddio33_pcix ad12 vss a2 vss a13 vss a14 vss a15 vss a16 vss a18 vss a19 vss a21 vss a24 vss b2 vss b3 vss b14 vss b16 vss b18 vss b20 vss b23 vss b24 vss b25 vss b26 vss c2 vss c3 vss c11 vss c12 vss c17 vss c18 vss c19 vss c20 vss c21 vss c22 vss c23 vss c24 vss c25 vss c26 vss d3 vss d4 vss d7 vss d8 vss d15 vss d16 vss d18 vss d21 vss d23 vss d24 vss d25 vss e5 vss e11 vss e12 vss e18 vss e19 vss e20 vss e22 vss e24 vss e25 vss f15 vss f16 vss f20 vss f22 vss f25 vss g3 vss g5 vss g11 vss g12 vss g23 vss g26 vss h3 vss h5 vss h20 vss h21 vss h23 vss h25 vss j26 vss k21 vss k22 vss k23 vss k24 vss l1 vss l4 vss l6 vss l20 vss l22 vss l24 vss l25 vss m4 vss m6 vss m12 vss m14 vss m20 vss m22 vss m24 vss m25 vss n13 vss n15 vss n20 vss n24 vss p12 vss p14 vss p20 vss p23 vss p25 vss p26 vss r3 vss r5 vss r7 vss r13 vss r15 vss r21 vss r23 vss t3 vss t5 vss t7 vss t21 vss t23 vss t25 vss t26 vss u4 vss u22 vss u24 vss v20 vss v22 vss v25 vss v26 vss w4 vss w21 vss w22 vss w24 vss w25 vss w26 vss y4 vss y15 vss y16 vss y17 vss y20 vss y21 vss y22 vss y24 vss aa11 vss aa12 vss aa25 vss ab7 vss ab8 vss ab15 vss ab16 vss ab18 vss ab21 vss ab22 vss ab25 vss ab26 vss ac6 signal ball # signal ball # signal ball #
7-14 speci?ations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. figure 7.5 LSIFC949X 544-pad fpbga mechanical drawing important: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code 7u.
LSIFC949X dual channel fibre channel i/o processor technical manual a-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. appendix a register summary table a.1 and table a.2 list the register summary for the LSIFC949X. . table a.1 LSIFC949X multifunction pci registers register name address read/write page vendor id 0x00 read only 6-3 device id 0x02 read only 6-3 command 0x04 read/write 6-4 status 0x06 read/write 6-6 revision id 0x08 read/write 6-8 class code 0x09 read/write 6-8 cache line size 0x0c read/write 6-9 latency timer 0x0d read/write 6-9 header type 0x0e read only 6-10 reserved 0x0f read only 6-10 i/o base address 0x10 read/write 6-10 memory[0] base address low 0x14 read/write 6-11 memory[0] base address high 0x18 read/write 6-11 memory[1] base address low 0x1c read/write 6-12 memory[1] base address high 0x20 read/write 6-12 reserved 0x24?x28 read only 6-12 (sheet 1 of 3)
a-2 register summary copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. subsystem vendor id 0x2c read only 6-13 subsystem id 0x2e read only 6-13 expansion rom base address 0x30 read/write 6-14 capabilities pointer 0x34 read only 6-15 reserved 0x38 read only 6-16 interrupt line 0x3c read/write 6-16 interrupt pin 0x3d read only 6-17 minimum grant 0x3e read only 6-17 minimum latency 0x3f read only 6-18 power management capability id 0xxx read only 6-18 power management next pointer 0xxx read only 6-20 power management capabilities 0xxx read only 6-19 power management control/status 0xxx read/write 6-20 power management bridge support extensions 0xxx read only 6-21 power management data 0xxx read only 6-21 msi capability id 0xxx read only 6-21 msi next pointer 0xxx read only 6-22 msi message control 0xxx read/write 6-22 msi message lower address 0xxx read/write 6-23 msi message upper address 0xxx read/write 6-24 msi message data 0xxx read/write 6-24 msi mask bits 0xxx read/write 6-25 msi pending bits 0xxx read only 6-25 msi-x capability id 0xxx read only 6-25 table a.1 LSIFC949X multifunction pci registers (cont.) register name address read/write page (sheet 2 of 3)
register summary a-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. msi-x next pointer 0xxx read only 6-26 msi-x message control 0xxx read/write 6-26 msi-x table offset 0xxx read only 6-27 msi-x pba offset 0xxx read only 6-27 pci-x capability id 0xxx read only 6-28 pci-x next pointer 0xxx read only 6-28 pci-x command 0xxx read/write 6-29 pci-x status 0xxx read/write 6-30 table a.2 LSIFC949X host interface registers register name address read/write page system doorbell 0x00 read/write 6-34 write sequence 0x04 read/write 6-35 host diagnostic 0x08 read/write 6-36 test base address 0x0c read/write 6-38 diagnostic read/write data 0x10 read/write 6-38 diagnostic read/write address 0x14 read/write 6-39 host interrupt status 0x30 read only 6-39 host interrupt mask 0x34 read/write 6-40 request fifo 0x40 read/write 6-42 reply fifo 0x44 read/write 6-42 high priority request fifo 0x48 read/write 6-43 host index register 0x50 read/write 6-43 table a.1 LSIFC949X multifunction pci registers (cont.) register name address read/write page (sheet 3 of 3)
a-4 register summary copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
LSIFC949X dual channel fibre channel i/o processor technical manual b-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. appendix b reference speci?ations the LSIFC949X is compliant with the speci?ations in ta b l e b . 1 . : table b.1 reference speci?ations speci?ation revision fibre channel physical interface (fc-pi-2) 5 fibre channel arbitrated loop (fc-al-2) 7.0 fc private loop direct attach (fc-plda) 1.5 fibre channel protocol for scsi (fcp) 12 pci local bus 2.3 pci-x addendum to the pci local bus 2.0 pci bus power management interface speci?ation 1.2
b-2 reference speci?ations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
LSIFC949X dual channel fibre channel i/o processor technical manual c-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. appendix c glossary of terms and abbreviations 8b/10b a data encoding scheme, developed by ibm, that translates byte wide data to an encoded 10-bit format. ansi american national standards institute, the coordinating organization for voluntary standards in the united states. arbitrated loop topology (fc-al) a fc topology that provides a low-cost solution to attach multiple ports in a loop without switches. ber bit error rate. bit a binary digit. the smallest unit of information a computer uses. the value of a bit (0 or 1) represents a two-way choice, such as on or off, and true or false. broadcast sending a transmission to all n_ports on a fabric. bus a collection of unbroken signal lines across which information is transmitted from one part of a computer system to another. connections to the bus are made using taps on the lines. bus mastering a high-performance way to transfer data. the host adapter controls the transfer of data directly to and from system memory without bothering the computers microprocessor. this is the fastest way for multitasking operating systems to transfer data. byte a unit of information consisting of 8 bits. channel a point-to-point link, the main task of which is to transport data from one point to another.
c-2 glossary of terms and abbreviations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. con?uration refers to the way a computer is set up; the combined hardware components (computer, monitor, keyboard, and peripheral devices) that make up a computer system; or the software settings that allow the hardware components to communicate with each other. cpu central processing unit. the ?rain of the computer that performs the actual computations. the term microprocessor unit (mpu) is also used. crosspoint- switched topology (fc-xs) highest performance fc fabric, providing a choice of multiple path routings between pairs of f_ports. dma direct memory access. a method of moving data from a storage device directly to ram without using the resources of the cpu. dma bus master a feature that allows a peripheral to control the ?w of data to and from system memory by blocks, as opposed to pio (programmed i/o), where the processor is in control and the ?w is by byte. device driver a program that allows a microprocessor (through the operating system) to direct the operation of a peripheral device. eeprom electronically erasable programmable read only memory. a memory chip that typically stores con?uration information. eisa extended industry standard architecture. an extension of the 16-bit isa bus standard. it allows devices to perform 32-bit data transfers. exchange a term that refers to one of the fc ?uilding blocks, composed of one or more nonconcurrent sequences for a single operation. fabric fc-de?ed interconnection methodology that handles routing in fc networks. fc fibre channel. fc-ph fc physical standard, consisting of the three lower levels: fc-0, fc-1, and fc-2. fc-0 lowest level of fc-ph, covering the physical characteristics of the interface and media. fc-1 middle level of fc-ph, de?ing the 8b/10b encoding/decoding and transmission protocol.
glossary of terms and abbreviations c-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. fc-2 highest level of fc-ph, de?ing the rules for signaling protocol and describing transfer of the frame, sequence, and exchanges. fc-3 the hierarchical level in the fc standard that provides common services, such as striping de?ition. fc-4 the hierarchical level in the fc standard that speci?s the mapping of upper layer protocols (ulps) to levels below. fcc federal communications commission. fcp fibre channel protocol. fddi fiber distributed data interface. the ansi option for a metropolitan area network (man); a network based on the use of optical ?er cable to transmit data at 100 mbits/s. fibre channel service protocol (fsp) the common fc-4 level protocol for all services, transparent to the fabric type or topology. file a named collection of information stored on a disk. firmware software that is permanently stored in rom. therefore, it can be accessed during boot time. f_port a fabric port, the access point of the fabric for physically connecting the n_port. fl_port a fabric port con?ured for loop functionality. frame a linear set of transmitted bits that de?e a basic transport element. hard disk a disk made of metal and permanently sealed into a drive cartridge. a hard disk can store very large amounts of information. hal hardware abstraction layer. hippi high performance parallel interface, an 800 mbit/s interface to supercomputer networks (formerly known as high speed channel) developed by ansi. host the computer system in which a scsi host adapter is installed. it uses the scsi host adapter to transfer information to and from devices attached to the scsi bus.
c-4 glossary of terms and abbreviations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. host adapter a circuit board or integrated circuit that provides a scsi bus connection to the computer system. iop i/o processor. ip internet protocol. ipi intelligent peripheral interface. isa industry standard architecture. a type of computer bus used in most pcs. it allows devices to send and receive data up to 16 bits at a time. kbyte kilobyte. a measure of computer storage equal to 1024 bytes. lct logical con?uration table. link_control_ facility a termination card that handles the logical and physical control of the fc link for each mode of use. llc logical link control. local bus a way to connect peripherals directly to computer memory. it bypasses the slower isa and eisa buses. pci is a local bus standard. login server entity within the fc fabric that receives and responds to login requests. l_port an fc port which supports the arbitrated loop topology. lun logical unit number. an identi?r, zero to seven, for a logical unit. mbyte megabyte. a measure of computer storage equal to 1024 kilobytes. mfa message frame address. msi message signaled interrupt. multicast refers to delivering a single transmission to multiple destination n_ports. nic network interface card. n_port a node port, an fc-de?ed hardware entity at the node end of a link. nl_port a node port con?ured for loop functionality.
glossary of terms and abbreviations c-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. operating system a program that organizes the internal activities of the computer and its peripheral devices. an operating system performs basic tasks such as moving data to and from devices, and managing information in memory. it also provides the user interface. operation a term, de?ed in fc-2, that refers to one of the fc building blocks composed of one or more, possibly concurrent, exchanges. ordered set an fc term referring to four 10-bit characters (a combination of data and special characters) that provide low level link functions, such as frame demarcation and signaling between two ends of a link. it provides for initialization of the link after power-on and for some basic recovery actions. originator an fc term referring to the initiating device. parity checking a way to verify the accuracy of data transmitted over the scsi bus. one bit in the transfer makes the sum of all the 1 bits either odd or even (for odd or even parity). if the sum is not correct, an error message appears. pci peripheral component interconnect. a local bus speci?ation that allows connection of peripherals directly to computer memory. it bypasses the slower isa and eisa buses. pdb packet descriptor block. pio programmed input/output. a way the cpu can transfer data to and from memory using the computer i/o ports. pio is usually faster than dma, but requires cpu time. port the hardware entity within a node that performs data communications over the fc link. port address also port number. the address through which commands are sent to a host adapter board. this address is assigned by the pci bus. port number see port address. ram random access memory. the primary working memory of the computer in which program instructions and data are stored and are accessible to the cpu. information can be written to and read from ram. the contents of ram are lost when the computer is turned off. responder an fc term referring to the answering device.
c-6 glossary of terms and abbreviations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. risc core LSIFC949X chips contain a risc (reduced instruction set computer) processor, programmed through microcode scripts. rom read only memory. memory from which information can be read but not changed. the contents of rom are not erased when the computer is turned off. san storage area network. scam scsi con?uration automatically. a method that automatically allocates scsi ids using software when scam compliant scsi devices are attached. scatter/gather a device driver feature that lets the host adapter modify a transfer data pointer so that a single host adapter transfer can access many segments of memory. this minimizes interrupts and transfer overhead. scb scsi command block. scsi small computer system interface. a speci?ation for a high-performance peripheral bus and command set. the original standard is referred to as scsi-1. scsi-2 the current scsi speci?ation, which adds features to the original scsi-1 standard. scsi id a way that uniquely identi?s each scsi device on the scsi bus. each scsi bus has eight available scsi ids numbered 0? (or 0?5 for wide scsi). the host adapter usually gets id 7, giving it priority to control the bus. sequence a term referring to one of the fc building blocks, which are composed of one or more related frames for a single operation. sff small form factor. sgl scatter-gather list. snap subnetwork access protocol. synchronous data transfer one of the ways data is transferred over the scsi bus. transfers are clocked with ?ed frequency pulses. this is faster than asynchronous data transfer. synchronous data transfers are negotiated between the scsi host adapter and each scsi device.
glossary of terms and abbreviations c-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. system bios controls the low level post (power-on self test), and basic operation of the cpu and computer system. tid target id. topology the logical and/or physical arrangement of stations on a network. ulp upper layer protocol. vcci voluntary control council for interference. virtual memory space on a hard disk that can be used as if it were ram. vpd vendor product data. word a 2-byte (or 16-bit) unit of information. x3t9 a technical committee of the accredited standards committee x3, titled x3t9 i/o interfaces. it develops standards for moving data in and out of central computers.
c-8 glossary of terms and abbreviations copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
LSIFC949X dual channel fibre channel i/o processor technical manual ix-1 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. index numerics 133 mhz capable bit 6-31 133 mhz pci-x bit 6-31 4 ma bidirectional signals 7-3 64-bit address capable bit 6-22 64-bit device bit 6-32 64en/ 4-5 66 mhz capable 6-7 8 ma output signals 7-3 8b/10b decoding 2-2 8b/10b encoding 2-2 a ac timing 7-4 ack64/ 4-3 ad[1:0] 5-2 ad[10:8] 5-2 ad[63:0] 4-3 ad[7:2] 5-2 address/data bus 6-32 adsc/ 4-11 adv/ 4-11 alias to memory read block 5-4 , 5-5 , 5-7 alias to memory write block 5-4 , 5-6 alignment 5-8 arbitrated loop topology 2-8 arbitration 5-9 architecture 1-6 arm966e-s 6-37 aux_current bit 6-19 b base address register zero 5-3 ber 1-9 bios 5-2 bir 6-27 bit 133 mhz capable 6-31 64-bit address capable 6-22 64-bit device 6-32 aux current 6-19 bus number 6-32 d1 support 6-19 d2 support 6-19 data parity error recovery enable 6-30 data scale 6-20 data select 6-20 designed maximum cumulative read size 6-30 designed maximum memory read byte count 6-31 designed maximum outstanding split transactions 6-31 device complexity 6-31 device number 6-32 device specific initialization 6-19 function number 6-32 msi enable 6-23 multiple message 6-23 per-vector masking capable 6-22 pme clock 6-19 pme enable 6-20 pme status 6-20 pme support 6-19 power management version 6-20 power state 6-20
ix-2 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. received split completion error message 6-30 table bir 6-27 unexpected split completion 6-31 bit error rate 1-9 block diagram 3-2 burst size selection 5-7 bus number 6-32 bus commands 5-3 bus mastering 5-9 functions 5-9 bwe[3:0]/ 4-11 bypass0/ 4-8 bypass1/ 4-8 c c_be[3:0]/ 5-2 , 5-3 , 5-6 c_be[7:0]/ 4-3 cache line size 5-7 , 5-8 , 6-9 cache line size alignment 5-8 cache line size register 6-9 capabilities pointer register 6-15 capability id 6-2 msi 6-21 , 6-25 pci-x 6-28 power management 6-18 channel protocol 2-1 class 1 2-9 class 2 2-9 class 3 2-9 class code register 6-8 class intermix 2-10 classes of service 2-9 clock pme 6-19 cls 6-9 cls alignment 5-8 command descriptor block (cdb) 2-6 command register 6-4 completer id 6-32 configuration read command 5-2 , 5-4 , 5-6 , 5-7 , 6-6 write command 5-2 , 5-4 , 5-6 , 5-7 , 6-6 configuration space 5-2 , 6-1 ad[1:0] 5-2 ad[10:8] 5-2 ad[7:2] 5-2 c_be[3:0]/ 5-2 , 5-3 context manager 1-8 controller link 1-8 memory 1-7 cpci_en/ 4-6 crc 2-4 cyclic redundancy check (crc) 2-4 d d0 6-20 d1 6-20 d1 support bit 6-19 d2 6-20 d2 support bit 6-19 d3 6-20 dac 5-1 , 5-4 , 5-7 data parity error recovery enable bit 6-30 parity error reported 6-7 scale bit 6-20 select bit 6-20 data flows 3-2 data frames 2-3 , 2-4 data sequence 2-6 decoding 8b/10b 2-2 designed maximum cumulative read size bit 6-30 designed maximum memory read byte count bit 6-31 designed maximum outstanding split transactions bit 6-31 destination identifier (d_id) 2-8 detected parity error (from slave) bit 6-6 device complexity bit 6-31 device id register 6-3 device number bit 6-32 device specific initialization bit 6-19 devsel/ 4-4 devsel/ timing bit 6-6
ix-3 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. diagnostic memory 6-32 diagnostic memory enable bit 6-37 diagnostic read/write address register 6-39 diagnostic read/write data register 6-38 diagnostic read/write enable bit 6-37 diagnostic write enable bit 6-36 disarm bit 6-37 dma 5-9 doorbell status bit 6-40 system interrupt bit 6-40 doorbell interrupt mask bit 6-41 dual address cycle (dac) 1-7 dual address cycles command 5-1 , 5-4 , 5-7 e enable bus mastering bit 6-5 diagnostic memory bit 6-37 diagnostic write bit 6-36 i/o space bit 6-5 memory space bit 6-5 msi bit 6-23 parity error response bit 6-4 write and invalidate bit 6-5 encode/decode 2-2 end-of-frame (eof) 2-4 enum/ 4-5 exchanges transfer 2-2 expansion rom base address register 6-14 expansion rom enable bit 6-15 f fabric topology 2-8 fault0/ 4-7 fault1/ 4-7 fc data structure 2-4 data traffic 3-1 devices 2-7 exchange 2-4 fibre channel 2-1 frames 2-4 interface 2-1 layer 2-2 link 1-8 n_ports 2-3 sequence 2-4 structure 2-1 word 2-4 fcp 2-5 exchange 2-6 fibre channel protocol 1-1 fibre channel (fc) 2-1 fibre channel protocol (fcp) 1-1 fifo reply 6-42 , 6-43 request 6-42 flash rom bad signature bit 6-37 flash rom read timing 7-7 flash rom write timing 7-8 flashcs/ 4-10 frame data 2-3 end of 2-4 link control 2-3 payload 2-6 start of 2-4 transfer 2-2 frame/ 4-4 function number bit 6-32 functional block diagram 1-7 functional signal grouping 4-2 g gigablaze transceiver 3-2 gnt/ 4-3 , 5-9 gpio[2](blueled/) 4-6 gpio[3:0] 4-12 grant 5-9 h header type register 6-10 host diagnostic register 6-36 host doorbell value 6-35 host interrupt mask register 6-40 host interrupt status register 6-39
ix-4 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. i i/o base address register 5-3 , 6-10 key 6-35 read command 5-3 , 5-4 , 5-7 space 5-2 , 6-1 , 6-32 write command 5-3 , 5-5 , 5-7 iddtn 4-13 , 4-14 idsel 4-4 , 5-2 implementation 1-5 , 3-7 initiator command sequence 2-6 input signals 7-2 inta/ 4-5 , 6-23 , 6-26 , 6-37 intb/ 4-5 integrated transceiver 1-8 integration 2-3 interface fc 2-1 media 2-2 system 1-7 , 1-8 upper level protocol (ulp) 2-1 interface timing ssram read/write/read 7-6 intermix class 2-10 internet protocol (ip) 2-1 interrupt acknowledge command 5-3 , 5-4 , 5-7 doorbell mask bit 6-41 line register 6-16 pin register 6-17 reply bit 6-40 reply mask bit 6-41 request routing mode bits 6-41 signal routing 6-41 system doorbell bit 6-40 ttl bit 6-37 iop doorbell status bit 6-40 irdy/ 4-4 k key i/o 6-35 l latency timer register 6-9 led[4:0]/ 4-12 link control frames 2-3 , 2-4 link controller 1-8 lipreset/ 4-7 m ma[21:0] 4-10 mad[14] 6-32 mad[15] 6-31 master data parity error 6-30 maximum latency register 6-18 maximum memory read byte count bits 6-29 maximum outstanding split transactions bits 6-29 maximum stress ratings 7-1 mclk 4-11 md[31:0] 4-9 media interface 2-2 memory alias to read block 5-5 , 5-7 alias to write block 5-4 , 5-6 read block command 5-4 , 5-5 , 5-7 , 5-8 read command 5-3 , 5-5 , 5-6 , 5-7 , 5-9 read dword command 5-3 , 5-5 , 5-7 read line command 5-4 , 5-7 , 5-9 read multiple command 5-4 , 5-6 , 5-9 space 5-3 , 6-1 write and invalidate command 5-4 , 5-8 , 5-9 write block command 5-4 , 5-6 , 5-9 write command 5-4 , 5-5 , 5-8 , 5-9 memory [0] high register 6-11 memory [0] low register 6-11 memory [1] high register 6-12 memory [1] low register 6-12 memory controller 1-7 memory read 6-31 memory space [0] 5-3 , 6-1 , 6-32 memory space [1] 5-3 , 6-1 memory space[1] 6-32 message flow 3-5
ix-5 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. message interface 3-3 message queueing models 3-4 message transport 1-7 minimum grant register 6-17 mode[7:0] 4-12 modef0[2:0] 4-8 modef1[2:0] 4-8 moe[1:0] 4-10 mp[3:0] 4-9 msi capability id register 6-21 enable bit 6-23 mask bits 6-25 message address 6-23 message data 6-24 message upper address register 6-24 multiple message 6-23 next pointer register 6-22 pending bits 6-25 msi mask bits register 6-25 msi message address register 6-23 msi message control register 6-22 msi message data register 6-24 msi message upper address register 6-24 msi pending bits register 6-25 msi-x capability id register 6-25 next pointer register 6-26 pba offset 6-27 table offset 6-27 msi-x message control register 6-26 msi-x pba offset register 6-27 msi-x table offset register 6-27 multifunction pci 5-2 multiple cache line transfers 5-8 multiple message capable 6-23 multiple message enable 6-22 mwe[1:0]/ 4-10 n new capabilities 6-7 o odis0 4-7 odis1 4-7 operating conditions 7-2 overview 1-1 1-4 p par 4-4 par64 4-5 parity error 6-7 payload 2-4 , 2-6 pba offset 6-27 pci 66 mhz capable 6-7 address/data bus 6-32 addressing 5-2 alias to memory read block command 5-5 , 5-7 alias to memory write block command 5-6 arbitration 5-9 bus commands 5-3 bus commands and encoding types 5-3 cache line size register 5-8 cache mode 5-9 command 5-3 configuration read 5-2 configuration write 5-2 dual address cycles 5-1 memory read block 5-5 memory write 5-5 configuration read command 5-4 , 5-6 , 5-7 , 6-6 configuration space 5-2 , 6-1 ad[1:0] 5-2 ad[10:8] 5-2 ad[7:2] 5-2 address map 6-2 c_be[3:0]/ 5-2 , 5-3 configuration write command 5-4 , 5-6 , 5-7 , 6-6 dac 5-1 , 5-4 , 5-7 device complexity bit 6-31 dual address cycles command 5-4 , 5-7 functional description 5-1 i/o read command 5-3 , 5-4 , 5-7 i/o space 5-2 , 6-1 , 6-32
ix-6 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. i/o space address map 6-33 i/o space and memory space [0] 6-32 i/o write command 5-3 , 5-5 , 5-7 interrupt acknowledge command 5-3 , 5-4 , 5-7 memory [0] address map 6-34 memory [1] address map 6-34 memory read block command 5-7 , 5-8 memory read command 5-3 , 5-5 , 5-6 , 5-7 , 5-9 memory read dword command 5-5 , 5-7 memory read line command 5-4 , 5-7 , 5-9 memory read multiple command 5-4 , 5-6 , 5-9 memory space 5-2 , 5-3 , 6-1 memory space [0] 5-3 , 6-1 memory space [1] 5-3 , 6-1 memory write and invalidate command 5-4 , 5-8 , 5-9 memory write block command 5-6 , 5-9 memory write command 5-4 , 5-8 , 5-9 multifunction 5-2 new capabilities 6-7 reset 6-37 special cycle command 5-3 , 5-4 , 6-6 split completion command 5-7 system address space 6-1 pci bidirectional signals 7-4 pci input signals 7-4 pci output signals 7-4 pciclk 4-3 pci-x 5-1 133 mhz capable bit 6-31 64-bit device bit 6-32 alias to memory read block command 5-4 alias to memory write block command 5-4 bus commands 5-3 bus number 6-32 capability id register 6-28 command 5-3 command register 6-29 data parity error recovery enable bit 6-30 designed maximum cumulative read size bit 6-30 designed maximum memory read byte count bit 6-31 designed maximum outstanding split transactions bit 6-31 device complexity bit 6-31 device number bit 6-32 function number bit 6-32 maximum memory read byte count bits 6-29 maximum outstanding split transactions bits 6-29 memory read block command 5-4 memory read dword command 5-3 memory write block command 5-4 next pointer register 6-28 received split completion error message bit 6-30 split completion command 5-4 split completion discarded bit 6-31 status register 6-30 unexpected split completion bit 6-31 pending bits 6-25 perr/ 4-4 per-vector masking capable bit 6-22 pme 6-19 , 6-20 clock bit 6-19 enable bit 6-20 status bit 6-20 support bits 6-19 point-to-point topology 2-8 por 6-37 ports 2-7 power management aux_current bit 6-19 bridge support extensions register 6-21 capabilities register 6-19 capability id register 6-18 control/status register 6-20 d0 6-20 d1 6-20 d1 support bit 6-19 d2 6-20 d2 support bit 6-19 d3 6-20
ix-7 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. data register 6-21 data scale bit 6-20 data select bit 6-20 device specific initialization bit 6-19 event 6-19 next pointer register 6-18 pme clock bit 6-19 pme enable bit 6-20 pme status bit 6-20 power state bit 6-20 support bits 6-19 version bit 6-20 power on reset 6-37 power state d3 6-20 power state bit 6-20 proc_drvls 4-13 , 4-14 processor arm risc 1-6 , 1-7 , 1-8 i/o 1-7 protocol channel 2-1 fibre channel (fcp) 1-1 , 2-5 internet 2-1 signaling 2-2 transmission 2-2 upper level 2-1 protocols upper layer 2-3 r ramcs/ 4-11 received master abort (from master) bit 6-6 target abort (from master) bit 6-6 received split completion error message bit 6-30 receiver 1-8 refclk 4-8 , 4-9 reference specifications b-1 register cache line size 6-9 capabilities pointer 6-15 class code 6-8 command 6-4 device id 6-3 diagnostic read/write address 6-39 diagnostic read/write data 6-38 expansion rom base address 6-14 header type 6-10 host diagnostic 6-36 host interrupt mask 6-40 host interrupt status 6-39 i/o base address 6-10 interrupt line 6-16 interrupt pin 6-17 latency timer 6-9 map pci i/o space 6-33 maximum latency 6-18 memory [0] high 6-11 memory [0] low 6-11 memory [1] high 6-12 memory [1] low 6-12 minimum grant 6-17 msi capability id 6-21 msi mask bits 6-25 msi message address 6-23 msi message control 6-22 msi message data 6-24 msi message upper address 6-24 msi next pointer 6-22 msi pending bits 6-25 msi-x capability id 6-25 msi-x message control 6-26 msi-x next pointer 6-26 msi-x pba offset 6-27 msi-x table offset 6-27 pci memory [0] address map 6-34 pci memory [1] address map 6-34 pci-x capability id 6-28 pci-x command 6-29 pci-x next pointer 6-28 pci-x status 6-30 power management bridge support extensions 6-21 power management capabilities 6-19 power management capability id 6-18 power management control/status 6-20
ix-8 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. power management data 6-21 power management next pointer 6-18 reply fifo 6-42 , 6-43 request fifo 6-42 revision id 6-8 status 6-6 subsystem id 6-14 subsystem vendor id 6-13 system doorbell 6-34 test base address 6-38 vendor id 6-3 write sequence 6-35 register map a-1 , a-3 pci configuration space 6-2 reply fifo register 6-42 , 6-43 reply interrupt bit 6-40 reply interrupt mask bit 6-41 reply message 3-3 reply message frames 5-9 req/ 4-3 , 5-9 req64/ 4-3 request fifo register 6-42 request message 3-3 request message frames 5-9 request status 1-9 requester id 6-32 reset adapter bit 6-37 reset history bit 6-37 response sequence 2-6 revision id register 6-8 rom expansion enable bit 6-15 rst/ 4-3 rtrim 4-7 rx0neg 4-6 rx0pos 4-6 rx1neg 4-6 rx1pos 4-6 rxlos0 4-8 rxlos1 4-8 s schmitt input signals 7-3 scl 4-12 , 4-13 scsi bus mastering functions 5-9 functions 5-9 scsi message interface 3-6 sda 4-12 sequences transfer 2-2 serr/ 4-4 , 6-30 serr/ enable bit 6-4 signaled system error bit 6-6 signaling protocol 2-2 special cycle command 5-3 , 5-4 , 6-6 split completion command 5-4 , 5-7 split completion discarded bit 6-31 split completion error 6-30 split completion received error message 6-30 split completion unexpected 6-31 split transaction 6-31 ssram memory 3-7 start-of-frame (sof) 2-4 status register 6-30 status iop doorbell bit 6-40 status register 6-6 stop/ 4-4 subsystem id register 6-14 subsystem vendor id register 6-13 support components 3-7 flash rom 3-8 serial eeprom 3-8 ssram memory 3-7 switch/ 4-5 system address space 6-1 system bios 5-2 system doorbell interrupt bit 6-40 system doorbell register 6-34 system interface 1-7 , 1-8 , 5-9 bus mastering function 5-9 t table bir 6-27 table offset 6-27 target message class 3-6 target operation 1-9 target response 2-6
ix-9 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved. tck 4-14 tdi 4-14 tdo 4-14 test base address register 6-38 testreset/ 6-37 timing diagram flash rom read 7-7 flash rom write 7-8 ssram read/write/read 7-6 tms_chip 4-14 tms_ice 4-14 topology arbitrated loop 2-7 fabric 2-7 point-to-point 2-7 transceiver 1-8 , 3-2 transfer exchanges 2-2 frames 2-2 sequences 2-2 transmission protocol 2-2 transmitter 1-8 trdy/ 4-4 trst 4-14 ttl interrupt bit 6-37 tx0neg 4-6 tx0pos 4-6 tx1neg 4-6 tx1pos 4-6 u unexpected split completion bit 6-31 upper layer protocols (ulps) 2-3 v vendor id register 6-3 version bit 6-20 w write and invalidate enable bit 6-5 write i/o key 6-35 write sequence register 6-35
ix-10 copyright 2003, 2004, 2005 by lsi logic corporation. all rights reserved.
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