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products and specifications discussed herein ar e subject to change by micron without notice. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm features pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_1.fm - rev. g 5/05 en 1 ?2004, 2005 micron technology, inc. all rights reserved. ddr sdram unbuffered dimm mt8vddt3232u ? 128mb mt8vddt6432u ? 256mb mt8vddt12832u ? 512mb for ddr sdram component specificat ions, please refer to the micron ? web site: www.micron.com/ features ? 100-pin, dual in-line memory module (dimm) ? fast data transfer rate: pc2100 and pc2700 ? utilizes 266 mt/s or 333 mt/s ddr sdram components ? 128mb (16 meg x 32), 256mb (32 meg x 32), 512mb (64 meg x 32) ?v dd = +2.5v ? 2.5v i/o (sstl_2 compatible) ? commands entered on each positive ck edge ? dqs edge-aligned with data for reads; center- aligned with data for writes ? internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle ? bidirectional data strobe (dqs) transmitted/ received with data? i.e. , source-synchronous data capture ? differential clock inputs ck and ck# ? four internal device banks for concurrent operation ? programmable burst lengths: 2, 4, or 8 ? auto precharge option ? serial presence detect (spd) with eeprom ? programmable read cas latency ? auto refresh and self refresh modes ? 15.625s (128mb), 7.8125s (256mb, 512mb) maximum average periodic refresh interval ? gold edge contacts ?dual rank figure 1: 100-pin dimm (mo-161) notes: 1. contact micron for product availability. 2. cl = cas (read) latency. options marking ?package 100-pin dimm (standard) g 100-pin dimm (lead-free) 1 y ? operating temperature range commercial (ambient) none industrial (ambient) i ? frequency/cas latency 2 6ns/167 mhz (333mt/s) cl = 2.5 -6 7.5ns/133 mhz (266 mt/s) cl = 2 -75z 1 7.5ns/133 mhz (266 mt/s) cl = 2.5 -75
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_1.fm - rev. g 5/05 en 2 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm features table 1: address table mt8vddt3232u mt8vddt6432u mt8vddt12832u refresh count 4k 8k 8k row addressing 4k (a0?a11) 8k (a0?a12) 8k (a0?a12) device bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) device configuration 128mb (16 meg x 8) 256mb (32 meg x 8) 512mb (64 meg x 8) column addressing 1k (a0?a9) 1k (a0?a9) 1k (a0?a9, a11) module rank addressing 2 (s0#, s1#) 2 (s0#, s1#) 2 (s0#, s1#) table 2: part numbers and timing parameters part number module density configuration module bandwidth memory clock/ data bit rate latency (cl - t rcd - t rp) mt8vddt3232ug-6__ 128mb 16 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt3232uy-6__ 128mb 16 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt3232ug-75z__ 128mb 16 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt3232uy-75z__ 128mb 16 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt3232ug-75__ 128mb 16 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt3232uy-75__ 128mb 16 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt6432ug-6__ 256mb 32 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt6432uy-6__ 256mb 32 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt6432ug-75z__ 256mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt6432uy-75z__ 256mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt6432ug-75__ 256mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt6432uy-75__ 256mb 32 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt12832ug-6__ 512mb 64 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt12832uy-6__ 512mb 64 meg x 32 2.7 gb/s 6ns/333 mt/s 2.5-3-3 mt8vddt12832ug-75z__ 512mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt12832uy-75z__ 512mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt8vddt12832ug-75__ 512mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 mt8vddt12832uy-75__ 512mb 64 meg x 32 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 all part numbers end with a two-place co de (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt8vddt3232ug-75b1 .
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32utoc.fm - rev. g 5/05 en 3 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 pin assignments and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 serial presence-detect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 dll enable/disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 parameter tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 serial presence detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 spd clock and data conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 spd start condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 spd stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 spd acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 module dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ulof.fm - rev. g 5/05 en 4 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm list of figures list of figures figure 1: 100-pin dimm (mo-161) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: module layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: functional block diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: mode register definition diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 5: cas latency diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 6: extended mode register definition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 7: derating data valid window t qh - t (dqsq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 8: pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 9: pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 10: initialization flow di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 11: data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 12: definition of start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 13: acknowledge response from receiv er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 14: spd eeprom timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 15: 100-pin dimm dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ulot.fm - rev. g 5/05 en 5 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm list of tables list of tables table 1: address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 2: part numbers and timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 5: burst definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: cas latency (cl) table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7: commands truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 8: dm operation truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 9: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 10: ac input operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 11: i dd specifications and conditions ? 128mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 12: i dd specifications and conditions ? 256mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 13: i dd specifications and conditions ? 512mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 14: capacitance (all modules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 15: component electrical characte ristics and recommended ac operating conditions. . . . . . . . . . . .21 table 16: eeprom device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 17: eeprom operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 18: serial presence-detect eeprom dc operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 19: serial presence-detect eeprom ac op erating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 20: serial presence-detect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 6 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm pin assignments and descriptions pin assignments and descriptions note: pin 21 is no connect for the 128mb mo dule, or a12 for the 256mb or 512mb modules. figure 2: module layout table 3: pin assignment 100-pin dimm front 100-pin dimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1dq0 14 v dd 26 a5 39 dq18 51 dq4 64 v dd 76 a2 89 dq22 2v ss 15 dq11 27 a3 40 dq19 52 v ss 65 dq15 77 a0 90 dq23 3dq1 16 v ss 28 a1 41 v dd 53 dq5 66 v ss 78 ba1 91 v dd 4dqs017ck0 29 a10 42 dq24 54 dm0 67 ck1 79 ras# 92 dq28 5v dd 18 ck0# 30 v dd 43 dq25 55 v dd 68 ck1# 80 v dd 93 dq29 6dq2 19 v dd 31 ba0 44 v ss 56 dq6 69 v dd 81 cas# 94 v ss 7dq3 20 cke1 32 we# 45 dqs3 57 dq7 70 cke0 82 s1# 95 dm3 8v dd 21 nc/ a12 33 s0# 46 dq26 58 v dd 71 a11 83 dnu 96 dq30 9dq8 22 nc 34 dq16 47 v ss 59 dq12 72 a8 84 dq20 97 v ss 10 dq9 23 a9 35 v ss 48 dq27 60 dq13 73 a6 85 v ss 98 dq31 11 v ss 24 a7 36 dq17 49 sa0 61 v ss 74 a4 86 dq21 99 sda 12 dqs1 25 v ss 37 dqs2 50 v ref 62 dm1 75 v ss 87 dm2 100 scl 13 dq10 38 v dd 63 dq14 88 v dd u1 u2 u3 u4 u5 u6 u7 u8 u9 pin100 pin 50 pin 23 pin 1 pin 51 pin 73 indicates a v dd or v ddq pin indicates a v ss pin front view back view
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 7 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm pin assignments and descriptions table 4: pin descriptions pin numbers may not correlate wi th symbols; refer to figure 3 on page 6 for more information pin numbers symbol type description 32, 79, 81 we#, cas#, ras# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 17, 18, 67, 68 ck0, ck0#, ck1, ck1# input clock: ck, ck# are differential clock inputs. all address and control input signals are samp led on the crossing of the positive edge of ck,and negative edge of ck#. output data (dq and dqs) is referenced to the crossings of ck and ck#. 20, 70 cke0, cke1 input clock enable: cke hi gh activates and ck e low deactivates the internal clock, input buffers and outp ut drivers. taking cke low provides precha rge power-down and self refresh operations (all device banks idle), or active power- down (row active in any device bank).cke is synchronous for power-down entry and exit , and for self refresh entry. cke is asynchronous for self re fresh exit and for disabling the outputs. cke must be main tained high thro ughout read and write accesses. input buffers (excluding ck, ck#, and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self re fresh. cke is an sstl_2 input but will detect an lv cmos low level after v dd is applied and until cke is first brought high. after cke is brought high, it becomes an sstl_2 input only. 33, 82 s0#, s1# input chip selects: s# enables (r egistered low) and disables (registered high) the command decoder. all commands are masked when s# is registered hi gh. s# is considered part of the command code. 31, 78 ba0, ba1 input bank address: ba0 and ba1 define to which device bank an active, read, write, or pr echarge command is being applied. 21 (256mb, 512mb) , 23, 24, 26-29, 71-74, 76, 77 a0?a11 (128mb) a0?a12 (256mb, 512mb) input address inputs: provide th e row address for active commands, and the column addr ess and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs al so provide the op-c ode during a mode register set command. ba0 and ba1 define which mode register (mode register or extend ed mode register) is loaded during the load mode register command. 4, 12, 37, 45 dqs0?dqs3 input/ output data strobe: output with read data, input with write data. dqs is edge-aligned with read data, centered in write data. used to capture data. 54, 62, 87, 95 dm0?dm3 input data write mask. dm low allows write operation. dm high blocks write operation. dm lines do not affect read operation. 1, 3, 6, 7, 9,10, 13, 15, 34, 36, 39, 40, 42, 43, 46, 48, 51, 53, 56, 57, 59, 60, 63, 65, 84, 86, 89, 90, 92, 93, 96, 98 dq0?dq31 input/ output data i/os: data bus. 49 sa0 input presence-detect address inputs: these pins are used to configure the presence-detect device.
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 8 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm pin assignments and descriptions 99 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. 100 scl input serial clock for presen ce-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 50 v ref supply sstl_2 reference voltage. 5, 8, 14, 19, 30, 38, 41, 55, 58, 64, 69, 80, 88, 91 v dd supply power supply: +2.5v 0.2v. 2, 11, 16, 25, 35, 44, 47, 52, 61, 66, 75, 85, 94, 97 v ss supply ground. 83 dnu ? do not use: this pin is not connected on these modules, but is an assigned pin on other modu les in this product family. 21 (128mb), 22 nc ? no connect: these pins should be left unconnected. table 4: pin descriptions (continued) pin numbers may not correlate wi th symbols; refer to figure 3 on page 6 for more information pin numbers symbol type description
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 9 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm functional block functional block all resistor values are 22 unless otherwise specified. per industry standard, micron modules utilize various component speed grades, as referenced in the module part number guide at www.m icron.com/numberguide. standard modules use the following dd r sdram devices: mt46v16m8tg (128mb); mt46v32m8tg (256mb); and mt46v64m8tg (512mb). lead-free modules use the fol- lowing ddr sdram devices: mt46v16m8p (128mb); mt46v32m8p (256mb); and mt46v64m8tg (512mb). figure 3: functional block diagram a0 sa0 spd u5 sda a1 a2 ras# cas# cke0 ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams u1-u4 cke1: ddr sdrams u5-u8 we#: ddr sdrams a0-a11: ddr sdrams a0-a12: ddr sdrams ba0: ddr sdrams ba1: ddr sdrams cke1 we# a0-a11 (128mb) a0-a12 (256mb, 512mb) ba0 ba1 v dd v dd spd ddr sdrams (v dd and v dd q) scl s0# s1# u9 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm0 u3 dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dm1 dqs1 dm2 dqs2 dm cs# dqs u8 dm cs# dqs dm cs# dqs dm cs# dqs dm3 dqs3 dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq ddr sdram x 4 ck0 ck0# 120 ddr sdram x 4 ck1 ck1# 120 wp v ss v ref ddr sdrams ddr sdrams, spd u6 dq dq dq dq dq dq dq dq u7
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 10 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm general description general description the mt8vddt3232u, mt8vddt6432u, and mt8vddt12832u are high-speed cmos, dynamic random-access, 128mb, 256mb, an d 512mb memory modules organized in x32 configuration. ddr sdram modules us e internally configured quad-bank ddr sdram devices. ddr sdram modules use a double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram mo dule effectively consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two corresponding n - bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is an intermittent strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. ddr sdram modules operate from differential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dq s, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to ddr sdram modules are burst oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. th e address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select devices bank; a0?a11 select devi ce row for 128mb module, a0?a12 select device row for 256mb and 512mb modules). the address bits registered coincident with the read or write command are used to select the device bank and the starting device column location for the burst access (ba 0, ba1; a0?a9 for 128mb and 256mb, or a0?a9, a11 for 512mb). ddr sdram modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr sdram modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and acti- vation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are compatible with the jedec standa rd for sstl_2. all outputs are sstl_2, class ii compatible. for more information regarding ddr sdram operation, refer to the 128mb, 256mb, or 512mb ddr sdram component data sheets. serial presence-d etect operation ddr sdram modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage de vice contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of stor- age are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 11 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm mode register definition bus using the dimm?s scl (clock) and sda (dat a) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresses. wr ite protect (wp) is tied to ground on the module, permanently disabling hardware write protect. mode register definition the mode register is used to define the specific mode of operation of ddr sdram devices. this definition includes the sele ction of a burst length, a burst type, a cas latency and an operating mode, as shown in figure 4, mode register definition dia- gram, on page 12. the mode register is programmed via the mode register set com- mand (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress , and the controller must wait the specified time before initiating the subs equent operation. violating either of these requirements will result in unspecified operation. mode register bits a0?a2 specify the burst le ngth, a3 specifies the type of burst (sequen- tial or interleaved), a4?a6 specify the cas latency, and a7?a11 (128mb, 256mb) or a7? a12 (512mb) specify the operating mode. burst length read and write accesses to ddr sdram devices are burst oriented, with the burst length being programmable, as shown in figure 4, mode register definition diagram. the burst length determines the maximum nu mber of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a1?a9 (128mb, 256m b) or a1?a9, a11 (512mb) when the burst length is set to two, by a2?a9 (128mb, 2 56mb) or a2?a9, a11 (512mb) when the burst length is set to four and by a3?a9 (128m b, 256mb) or a3?a9, a11 ( 512mb) when the burst length is set to eight. the remaining (l east significant) address bit(s) is (are) used to select the starting location within the bl ock. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 5, burst definition table, on page 13. read latency the read latency is the delay, in clock cycles, between the registration of a read com- mand and the availability of the first bit of ou tput data. the latency can be set to 2 or 2.5 clocks, as shown in figure 5, cas latency diagram, on page 14.
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 12 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm mode register definition if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . the cas latency table indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 4: mode register definition diagram m3 = 0 reserve d 2 4 8 reserve d reserve d reserve d reserve d operating mode normal operation normal operation/reset dll all other states reserve d 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - vali d vali d - 0 1 burst type s equential interleave d cas latency reserve d reserve d 2 reserve d reserve d reserve d 2.5 reserve d burst length m0 0 1 0 1 0 1 0 1 burst len g th c a s laten c ybt 0* a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mo d e re g ister (mx) a dd ress bus 976543 8210 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operatin g mo d e a10 a12 a11 ba0 ba1 10 11 12 13 0* 14 * m14 an d m13 (ba1 an d ba0) must b e ?0, 0? to sele c t the b ase mo d e re g ister (vs. the exten d e d mo d e re g ister). m9 m10 m12 m11 burst len g th c a s laten c ybt 0* 0* a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mo d e re g ister (mx) a dd ress bus 97 6 543 8210 operatin g mo d e a10 a11 ba0 ba1 10 11 12 13 * m13 an d m12 (ba1an d ba0) must b e ?0, 0? to sele c t the b ase mo d e re g ister (vs. the exten d e d mo d e re g ister). 128mb mo d ule a dd ress bus 25 6 mb, 512mb mo d ule a dd ress bus
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 13 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm mode register definition notes: 1. for a burst length of two, a1?a i select the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2?a i select the four-data-element block; a0?a1 select the first access within the block. 3. for a burst length of eight, a3?a i select the eight-data-element block; a0?a2 select the first access within the block. 4. whenever a boundary of the bl ock is reached within a given se q uence above, the follow- ing access wraps within the block. 5. i = 9 (128mb, 256mb) i = 9, 11 (512mb) table 5: burst definition table burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 table 6: cas latency (cl) table speed allowable operating clock frequency (mhz) cl = 2 cl = 2.5 -6 75 f 133 75 f 167 -75z 75 f 133 75 f 133 -75 75 f 100 75 f 133
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 14 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm extended mode register figure 5: cas latency diagram operating mode the normal operating mode is selected by issuing a mode register set command with bits a7?a11 (128mb, 256mb), or a7?a12 (5 12mb) each set to zero, and bits a0?a6 set to the desired values. a dll reset is initiated by issuing a mode register set com- mand with bits a7 and a9?a11 (128mb, 256mb), or a7 and a9?a12 (512mb) each set to zero, bit a8 set to one, and bi ts a0?a6 set to the desired values. although not required by the micron device, jedec specifications recommend when a load mode register command is issued to reset the dll, it should always be followed by a load mode register command to select normal operating mode. all other combinations of values for a7?a 11 (128mb, 256mb), or a7?a12 (512mb) are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable and output drive strength. these functions are controlled via the bits shown in figure 6, extended mode register definition diagram. the extended mode register is programmed via the load mode register command to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the enabling of the dll should always be followed by a load mode register command to the mode register (ba0/ba1 both low) to reset the dll. ck ck# command dq dqs cl = 2 read nop nop nop read nop nop nop burst length = 4 in the cases shown shown with nominal t ac, t dqsck, and t dqsq ck ck# command dq dqs cl = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don?t care transitioning data
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 15 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm extended mode register the extended mode register must be loaded wh en all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any sub- sequent operation. violating either of thes e requirements could result in unspecified operation. dll enable/disable the dll must be enabled for normal operatio n. dll enable is required during power- up initialization and upon returning to norm al operation after having disabled the dll for the purpose of debug or evaluation. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles with cke high must occur before a read command can be issued. figure 6: extended mode register definition diagram notes: 1. ba1 and ba0 (e13 and e12 for 128mb, or e14 and e13 for 256mb, 512mb) must be ?0, 1 ? to select the extended mode registe r (vs. the base mode register). 2. qfc# is not supported. operating mode normal operation all other states reserve d 0 ? 0 ? vali d ? 0 1 dll ena b le disa b le dll 1 1 0 1 a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 exten d e d mo d e re g ister (ex) a dd ress bus 976543 8210 e0 0 drive strength normal e1 e0 e1, operatin g mo d e a10 a11 ba1 ba0 10 11 12 13 e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 d s dll 1 1 0 1 a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 exten d e d mo d e re g ister (ex) a dd ress bus 976543 8210 operatin g mo d e a10 a11 a12 ba1 ba0 10 11 12 13 14 d s 128mb mo d ule a dd ress bus 25 6 mb an d 512mb mo d ules a dd ress bus 0 ? e2 2
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 16 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm commands commands table 7, commands truth table, and table 8, dm operation truth table, provide a gen- eral reference of available commands. for a more detailed description of commands and operations, refer to the 128mb, 256mb, or 512mb ddr sdram component data sheet. notes: 1. deselect and nop are functionally interchangeable. 2. ba0?ba1 provide device bank address an d a0-a11 (128mb) or a0?a12 (256mb, 512mb) provide row address. 3. ba0?ba1 provide device bank address; a0 ?a9 (128mb, 256mb) or a0?a9, a11 (512mb) provide column address; a10 high enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 4. applies only to read bursts wi th auto precharge disabled; th is command is undefined (and should not be us ed) for read bursts with auto precharge enabled and for write bursts. 5. a10 low: ba0?ba1 determine which device bank is precharged. a10 high: all device banks are precharged and ba0?ba1 are ? don?t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls ro w addressing; all inputs and i/os are ? don?t care ? except for cke. 8. ba0?ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 se lect extended mode register; other combina- tions of ba0?ba1 are reserved ). a0?a11 (128mb) or a0?a12 (256mb, 512mb) provide the op-code to be written to the selected mode register. table 7: commands truth table cke is high for all commands shown ex cept self refresh; all states and se q uences not shown are illegal or reserved name (function) cs# ras# cas# we# address notes deselect (nop) hx xx x 1 no operation (nop) lh hh x 1 active (select bank and activate row) l l h h bank/row 2 read (select bank and column, and start read burst) l h l h bank/col 3 write (select bank and colu mn, and start write burst) l h l l bank/col 3 burst terminate lh hl x 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) ll lh x 6, 7 load mode register ll llop-code 8 table 8: dm operation truth table used to mask write data; provided co incident with the corresponding data name (function) dm dqs write enable lvalid write inhibit hx
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 17 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm parameter tables parameter tables absolute maximum ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. voltage on v dd supply relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on v ref and inputs relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +3.6v voltage on i/o pins relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v operating temperature, t a (commercial - ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0c to +70c t a (industrial - ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c storage temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +150c short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma table 9: dc electrical characteristics and operating conditions notes: 1?5, 14, 48; notes appear on pages 23?27; 0c t a +70c parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v 32 i/o supply voltage v dd 2.3 2.7 v 32, 39 i/o reference voltage v ref 0.49 v dd 0.51 v dd v6, 39 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v 7, 39 input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v 25 input low (logic 0) voltage v il (dc) -0.3 v ref - 0.15 v 25 input leakage current any input 0v v in vdd, v ref pin 0v v in 1.35v (all other pins not under test = 0v) command/ address, ras#, cas#, we# i i -16 16 a 47 cke0, cke1, s0#, s1# ck, ck# -8 8 dm -4 4 output leakage current (dqs are disabled; 0v v out v dd ) dq, dqs i oz -10 10 a 47 output levels high current (v out = v dd -0.373v, minimum v ref , minimum v tt ) low current (v out = 0.373v, maximum v ref , maximum v tt ) i oh -16.8 ? ma 33, 34 i ol 16.8 ? ma table 10: ac input operating conditions notes: 1?5, 14, 48, 49; note s appear on pages 23?27; 0c t a +70c; v dd = +2.5v 0.2v parameter/condition symbol min max units notes input high (logic 1) voltage v ih (ac) v ref + 0.310 ? v 12, 25, 35 input low (logic 0) voltage v il (ac) ? v ref - 0.310 v 12, 25, 35 i/o reference voltage v ref (ac) 0.49 v dd 0.51 v dd v6
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 18 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm parameter tables table 11: i dd specifications and conditions ? 128mb ddr sdram components only notes: 1?5, 14, 48; notes appear on pages 23?27; 0c t a +70c; v dd = +2.5v 0.2v max parameter/condition symbol -6 -75z/ -75 units notes operating current: one device bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd0 a 512 432 ma 20, 42 operating current: one device bank; active -read precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 552 492 ma 20, 42 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 24 24 ma 21, 28, 44 idle standby current: cs# = hi gh; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 360 320 ma 45 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 200 160 ma 21, 28, 44 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twic e per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 400 360 ma 41 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 572 512 ma 20, 42 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 572 492 ma 20 auto refresh current t refc = t rfc (min) i dd5 b 2,120 1,760 ma 20, 44 t refc = 15.625s i dd5a b 40 40 ma 24, 44 self refresh current: cke 0.2v i dd6 b 24 16 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 a 1,432 1,312 ma 20, 43 a: value calculated as one module rank in this op erating condition, and all other module ranks in i dd 2p (cke low) mode. b: value calculated reflects all modu le ranks in this operating condition.
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 19 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm parameter tables table 12: i dd specifications and conditions ? 256mb ddr sdram components only notes: 1?5, 14, 48; notes appear on pages 23?27; 0c t a +70c; v dd = +2.5v 0.2v max parameter/condition symbol -6 -75z/ -75 units notes operating current: one devi ce bank; acti ve-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd0 a 516 496 ma 20, 42 operating current: one device bank; active -read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 696 596 ma 20, 42 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 32 32 ma 21, 28, 44 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 400 360 ma 45 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 240 200 ma 21, 28, 44 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 480 400 ma 41 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 716 616 ma 20, 42 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 716 616 ma 20 auto refresh current t refc = t rfc (min) i dd 5 b 2,040 1,880 ma 20, 44 t refc = 7.8125s i dd5a b 48 48 ma 24, 44 self refresh current: cke 0.2v i dd6 b 32 32 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 a 1,656 1,416 ma 20, 43 a: value calculated as one module rank in this operating condition, and all other module ranks in i dd 2p (cke low) mode. b: value calculated reflects all modu le ranks in this operating condition.
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 20 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm parameter tables table 13: i dd specifications and conditions ? 512mb ddr sdram components only notes: 1?5, 14, 48; notes appear on pages 23?27; 0c t a +70c; v dd = +2.5v 0.2v max parameter/condition symbol -6 -75z/ -75 units notes operating current: one devi ce bank; acti ve-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cyle; address and control inputs changing once every two clock cycles i dd0 a 540 480 ma 20, 42 operating current: one device bank; active -read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd1 a 660 600 ma 20, 42 precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd2p b 40 40 ma 21, 28, 44 idle standby current: cs# = high; all device banks idle; t ck = t ck min; cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd2f b 360 320 ma 45 active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd3p b 280 240 ma 21, 28, 44 active standby current: cs# = high; cke = high; one device bank; active-precharge; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd3n b 400 360 ma 41 operating current: burst = 2; reads; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd4r a 680 600 ma 20, 42 operating current: burst = 2; writes; continuous burst; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd4w a 720 560 ma 20 auto refresh current t refc = t rfc (min) i dd 5 b 2,320 2,240 ma 20, 44 t refc = 7.8125s i dd5a b 80 80 ma 24, 44 self refresh current: cke 0.2v i dd6 b 40 40 ma 9 operating current: four device bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd7 a 1,640 1,420 ma 20, 43 a: value calculated as one module rank in this operating condition, and all other module ranks in i dd 2p (cke low) mode. b: value calculated reflects all modu le ranks in this operating condition.
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 21 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm parameter tables table 14: capacitance (all modules) note: 11; notes appear on pages 23?27 parameter symbol min max units input/output capacitance: dq, dqs, dm c io 810 pf input capacitance: command and address c i1 16 24 pf input capacitance: s#; ck/ck#; cke c i2 812 pf table 15: component electrical characteristics and recommended ac operating conditions notes: 1?5, 12?15, 29, 48; note s appear on pages 23?27; 0c t a +70c; v dd = +2.5v 0.2v ac characteristics -6 -75z/-75 parameter symbol min max min max units notes access window of dq from ck/ck# t ac -0.7 +0.7 -0.75 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl = 2.5 t ck (2.5) 6 13 7.5 13 ns 40, 46 cl = 2 t ck (2) 7.5 13 7.5/10 13 ns 40, 46 dq and dm input hold time relative to dqs t dh 0.45 0.5 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.45 0.5 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 ns 27 access window of dqs from ck/ck# t dqsck -0.6 +0.6 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.45 0.5 ns 22, 23 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl ns 30 data-out high-impedance window from ck/ck# t hz +0.70 +0.75 ns 16, 37 data-out low-impedance window from ck/ck# t lz -0.7 -0.75 ns 16, 37 address and control input ho ld time (fast slew rate) t ih f 0.75 0.90 ns 12 address and control input se tup time (fast slew rate) t is f 0.75 0.90 ns 12 address and control input ho ld time (slow slew rate) t ih s 0.8 1 ns 12 address and control input se tup time (slow slew rate) t is s 0.8 1 ns 12 address and control input pulse width (for each input) t ipw 2.2 2.2 ns load mode register command cycle time t mrd 12 15 ns dq?dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.6 0.75 ns active to precharge command t ras 42 70,000 40 120,000 ns 31, 49 active to read with au to precharge command t rap 15 20 ns active to active/auto refresh command period t rc 60 65 ns auto refresh command period t rfc 72 75 ns 44
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 22 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm parameter tables active to read or write delay t rcd 15 20 ns precharge command period t rp 15 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 38 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck 38 active bank a to active bank b command t rrd 12 15 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 ns 18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 ns internal write to read command delay t wtr 1 1 t ck data valid output window na t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command interval 128mb t refc 140 140.6 s 21 256mb, 512mb 70.3 70.3 s 21 average periodic refresh interval 128mb t refi 15.6 15.6 s 21 256mb, 512mb 7.8 7.8 s 21 terminating voltage delay to v dd t vtd 0 0 ns exit self refresh to non-read command t xsnr 75 75 ns exit self refresh to read command t xsrd 200 200 t ck table 15: component electrical characteristics and recommended ac operating conditions (continued) ac characteristics -6 -75z/-75 parameter symbol min max min max units notes
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 23 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm notes notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environ- ment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as th e signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v dd /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd /2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at cl = 2 for -75z and cl = 2.5 for -6 and -75 with the out- puts open. 9. enables on-chip refresh and address counters. 10. i dd specifications are tested after the device is properly initialize d, and is averaged at the defined cycle rate. 11. this parameter is sampled. v dd = +2.5v 0.2v, v ref = vss, f = 100 mhz, t a =25c, v out (dc) = v dd /2, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 12. for slew rates < 1 v/ns and to 0.5 vns. if the slew rate is < 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100 mv/ns reduction in slew rate from 500mv/ns, while t ih is unaffected. if the slew ra te exceeds 4.5 v/ns, functionality is uncertain. for -6, slew rates must be 0.5 v/ns. 13. the ck/ck# input reference level (for ti ming referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke 0.3 x v dd is recognized as low. 15. the output timing reference level, as measured at the timing reference point indi- cated in note 3, is v tt . output (v out ) reference point 50 v tt 30pf
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 24 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm notes 16. t hz and t lz transitions occur in the same access time windows as valid data transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the intent of the ?don?t care? state after completion of the postamble is that the dqs- driven signal should either be high, low, or high-z and that any signal transition within the input switching region must foll ow valid input requirements. if dqs transi- tions high, above dc v ih (min) then it must not transition low, below dc v ih , prior to t dqsh (min). 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 20. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measure- ments is the largest multiple of t ck that meets the maximum absolute value for t ras. 21. the refresh period 64ms. this equates to an average refresh rate of 15.625s (128mb) or 7.8125s (256mb, 512mb). however, an auto refresh command must be asserted at least once every 140.6s ( 128mb) or 70.3s (256mb, 512mb); burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the valid data window is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct propor- tion to the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle vari ation of 45/55, beyond which functionality is uncertain. figure 7, derating data valid window t qh - t (dqsq), shows derating curves for duty cycles ra nging between 50/50 and 45/55. 23. each byte lane has a corresponding dqs. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b. reach at least the target ac level. c. after the ac target level is reached, co ntinue to maintain at least the target dc level, v il (dc) or v ih (dc). 26. jedec specifies ck and ck# input slew rate must be 1 v/ns (2 v/ns differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/dm/dqs slew rate is less than 0.5 v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100 mv/ns reduction in slew rate. if slew rate exceeds 4 v/ns, functionality is uncertain. for -6, slew rates must be 0.5 v/ns. 28. v dd must not vary more than 4 percent if ck e is not active while any bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount.
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 25 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm notes figure 7: derating data valid window t qh - t (dqsq) 30. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck/ inputs, collectively during bank active. 31. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the internal precharge command being issued. 32. any positive glitch to the nominal voltage must be less than 1/3 of the clock and not more than +400mv or 2.9 volts maximum, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mv or 2.2 volts mini- mum, whichever is more positive. 33. normal output drive curves: a. the full variation in driver pull-down current from minimum to maximum pro- cess, temperature and voltage will lie with in the outer bounding lines of the v-i curve of figure 8, pull-down characteristics. b. the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaran teed, to lie within the inner bounding lines of the v-i curve of figure 8, pull-down characteristics. c. the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 9, pull-up characteristics. d. the variation in driver pull-up current within nominal limits of voltage and tem- perature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 9, pull-up characteristics. 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 clo c k duty cy c le n s -75/-75z @ t ck = 10ns -75/-75z @ t ck = 7.5ns -6 @ t ck = 6ns n/a
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 26 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm notes e. the full variation in the ratio of the maximum to minimum pull-up and pull- down current should be between 0.71 and 1.4, for device drain-to-source volt- ages from 0.1v to 1.0v, and at th e same voltage and temperature. f. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drai n-to-source voltages from 0.1v to 1.0v. 34. the voltage levels used are derived from a minimum v dd level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will pro- vide significantly different voltage values. 35. v ih overshoot: v ih (max) = v dd + 1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. v dd and v dd q must track each other. 37. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 38. during initialzation, v dd q, v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v dd q are 0.0v, provided a minimum of 42 of series resistance is used between the v tt supply and the input pin. 39. during initialization, v dd , v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd / v dd are 0 volts, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. 40. the current micron part operates below the slowest jedec operating frequency of 83 mhz. as such, future die may not reflect this option. figure 8: pull-down characteristics
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 27 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm notes figure 9: pull-up characteristics 41. for the -6 and -75 i dd 3n is specified to be 35ma pe r ddr sdram device at 100 mhz. 42. random addressing changing and 50 perc ent of data changing at every transfer. 43. random addressing changing and 100 percent of data at every transfer. 44. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each risi ng clock edge, until t ref later. 45. i dd 2n specifies the dq and dqs to be driven to a valid high or low logic level. i dd 2q is similar to i dd 2f except i dd 2q specifies the address and control inputs to remain stable. although i dd 2f, i dd 2n, and i dd 2q are similar, i dd 2f is ?worst case.? 46. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 47. leakage number reflects the worst case le akage possible through the module pin, not what each memory device contributes. 48. when an input signal is high or low, it is defined as a steady state logic high or low. 49. the -6 speed grade will operate with t ras (min) = 40ns and t ras (max) = 120,000ns at any slower frequency.
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 28 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm initialization initialization to ensure device operation the dram mu st be initialized as described below: 1. simultaneously apply power to v dd and v dd q. 2. apply v ref and then v tt power. 3. assert and hold cke at a lvcmos logic low. 4. provide stable clock signals. 5. wait at least 200s. 6. bring cke high and provide at least one nop or deselect command. at this point the cke input changes from a lvcmos input to a sstl2 input only and will remain a sstl_2 input unless a power cycle occurs. 7. perform a precharge all command. 8. wait at least t rp time, during this time nops or deselect commands must be given. 9. using the lmr command program the extended mode register (e0 = 0 to enable the dll and e1 = 0 for normal drive or e1 = 1 for reduced drive, e2 through en must be set to 0; where n = most significant bit). 10. wait at least t mrd time, only nops or deselect commands are allowed. 11. using the lmr command program the mode register to set operating parameters and to reset the dll. note at least 200 clock cycles are required between a dll reset and any read command. 12. wait at least t mrd time, only nops or deselect commands are allowed. 13. issue a precharge all command. 14. wait at least t rp time, only nops or deselect commands are allowed. 15. issue an auto refresh command (note this may be moved prior to step 13). 16. wait at least t rfc time, only nops or deselect commands are allowed. 17. issue an auto refresh command (note this may be moved prior to step 13). 18. wait at least t rfc time, only nops or deselect commands are allowed. 19. although not required by the micron devi ce, jedec requires a lmr command to clear the dll bit (set m8 = 0). if a lmr command is issued the same operating parameters should be utilized as in step 11. 20. wait at least t mrd time, only nops or deselect commands are allowed. 21. at this point the dram is ready for an y valid command. note 200 clock cycles are required between step 11 (dll reset) and any read command.
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 29 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm initialization figure 10: initialization flow diagram v dd and v dd q ramp apply v ref and v tt cke must be lvcmos low apply stable clocks bring cke high with a nop command wait at least 200us precharge all assert nop or deselect for t rp time configure extended mode register configure load mode register and reset dll assert nop or deselect for t mrd time assert nop or deselect for t mrd time precharge all issue auto refresh command assert nop or deselect for t rfc time optional lmr command to clear dll bit assert nop or deselect for t mrd time dram is ready for any valid command s tep 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 1 5 16 1 7 18 1 9 20 2 1 assert nop or deselect commands for t rfc issue auto refresh command assert nop or deselect for t rp time
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 30 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm serial presence detect serial presence detect spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (as shown in figure 11, data validity, and figure 12, definition of start and stop). spd start condition all commands are preceded by the start cond ition, which is a hi gh-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not re spond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high tran- sition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (as shown in figure 13, acknowledge response from receiver). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both th e device and a write operation have been selected, the spd device will respond with an acknowledge after the receipt of each sub- sequent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop conditio n is generated by the master, the slave will continue to transmit data. if an acknowledge is not dete cted, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. figure 11: data validity scl sda data stable data stable data change
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 31 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm serial presence detect figure 12: definition of start and stop figure 13: acknowledge response from receiver scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 32 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm serial presence detect figure 14: spd eeprom timing diagram table 16: eeprom device select code the most significant bit (b7) is sent first device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1010sa2sa1sa0rw protection register select code 0110sa2sa1sa0rw table 17: eeprom operating modes mode rw bit wc bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1? random address read 0v ih or v il 1 start, device select, rw = ?0?, address 1v ih or v il 1 restart, device select, rw = ?1? se q uential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0? page write 0v il 16 start, device select, rw = ?0? scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 33 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm serial presence detect notes: 1. to avoid spurious start and stop condit ions, a minimum delay is placed between scl = 1 and the falling or ri sing edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write se q uence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tor, and the eeprom does not respond to its slave address. table 18: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v ddspd 2.3 3.6 v input high voltage: logic 1; all inputs v ih v dd 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd + 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = v ss or v dd i sb ?30a power supply current: scl clock fre q uency = 100 khz i cc ?2ma table 19: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss ; v dd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f 300 ns 2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time con stant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock fre q uency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 34 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm serial presence detect table 20: serial presence-detect matrix ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low ? ; notes appear on page 35 byte description entry (version) mt8vddt3232u mt8vddt6432u mt8vddt12832u 0 number of spd bytes used by micron 128 80 80 80 1 total number of bytes in spd device 256 08 08 08 2 fundamental memory type ddr sdram 07 07 07 3 number of row addresses on assembly 12, 13 0c 0d 0d 4 number of column addresses on assembly 10, 11 0a 0a 0b 5 number of physical ranks on dimm 2020202 6 module data width 32 20 20 20 7 module data width (continued) 0000000 8 module voltage interface levels sstl 2.5v 04 04 04 9 sdram cycle time, ( t ck) (cas latency = 2.5) 6ns (-6) 7.0ns (-75z) 7.5ns (-75) 60 70 75 60 70 75 60 70 75 10 sdram access from clock ( t ac) (cas latency = 2.5) 0.7ns (-6) 0.75ns (-75z/-75) 70 75 70 75 70 75 11 module configuration type none 00 00 00 12 refresh rate/type 15.62s, 7.8s/self 80 82 82 13 sdram device width (primary ddr sdram) 8080808 14 error-checking ddr sdram data width none 00 00 00 15 minimum clock delay, back-to-back random column access 1 clock 01 01 01 16 burst lengths supported 2, 4, 8 0e 0e 0e 17 number of banks on ddr sdram device 4040404 18 cas latencies supported 2, 2.5 0c 0c 0c 19 cs latency 0010101 20 we latency 1020202 21 sdram module attributes unbuffered/diff. clock 20 20 20 22 sdram device attr ibutes: general fast/concurrent ap c0 c0 c0 23 sdram cycle time, t ck (cas latency = 2) 7.5ns (-6) 7.5ns (-75z) 10ns (-75) 75 75 a0 75 75 a0 75 75 a0 24 sdram access from clock, t ac (cas latency = 2) 0.7ns (-6) 0.75ns (-75z/-75) 70 75 70 75 70 75 25 sdram cycle time, t ck (cas latency = 1.5) n/a 00 00 00 26 sdram access from clock, t ac (cas latency = 1.5) n/a 00 00 00 27 minimum row precharge time, t rp (see note 3) 18ns (-6) 20ns (-75z/-75) 48 50 48 50 48 50 28 minimum row active to row active, t rrd 12ns (-6) 15ns (-75z/-75) 30 3c 30 3c 30 3c 29 minimum ras# to cas# delay, t rcd (see note 3) 18ns (-6) 20ns (-75z/-75) 48 50 48 50 48 50
pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 35 ?2004, 2005 micron technology, inc. all rights reserved. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm serial presence detect notes: 1. the value of t ras used for -75 modules is calculated from t rc - t rp. actual device spec. value is 40 ns. 2. the jedec spd specification allows fast or slow slew rate values for these bytes. the worst- case (slow slew rate) value is represented here. systems re q uiring the fast sl ew rate setup and hold values are supported, provided the faster minimum slew rate is met. 3. the value of t rp, t rcd and t rap for -335 modules indicated as 18ns to align with industry specifications; actual ddr sdra m device specification is 15ns. 30 minimum ras# pulse width, t ras (see note 1) 42ns (-6) 45ns (-75z/-75) 2a 2d 2a 2d 2a 2d 31 module rank density 64mb, 128mb, 256mb 10 20 40 32 address and command setup time, t is (see note 2) 0.8ns (-6) 1.0ns (-75z/-75) 80 a0 80 a0 80 a0 33 address and command hold time, t ih (see note 2) 0.8ns (-6) 1.0ns (-75z/-75) 80 a0 80 a0 80 a0 34 data/data mask input setup time, t ds 0.45ns (-6) 0.5ns (-75z/-75) 45 50 45 50 45 50 35 data/data mask input hold time, t dh 0.45ns (-6) 0.5ns (-75z/-75) 45 50 45 50 45 50 36-40 reserved 00 00 00 41 min active auto refresh time t rc 60ns (-6) 65ns (-75z/-75) 3c 41 3c 41 3c 41 42 minimum auto refresh to active/auto refresh command period, t rfc 72ns (-6) 75ns (-75z/-75) 48 4b 48 4b 48 4b 43 sdram device max cycle time, t ck max 12ns (-6) 13ns (-75z/-75) 30 34 30 34 30 34 44 sdram device max dqs-dq skew time, t dqsq 0.45ns (-6) 0.5ns (-75z/-75) 2d 32 2d 32 2d 32 45 sdram device max read data hold skew factor, t qhs 0.55ns (-6) 0.75ns (-75z/-75) 55 75 55 75 55 75 46 reserved 00 00 00 47 dimm height 01 01 01 48?61 reserved 00 00 00 62 spd revision release 1.0 10 10 10 63 checksum for bytes 0?62 -6 -75z -75 c5 95 d5 d8 a8 e8 09 c9 f9 64 manufacturer?s jedec id code micron 2c 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff ff 72 manufacturing location 01?12 01?0c 01?0c 01?0c 73-90 module part number (ascii) variable data variable data variable data 91 pcb identification code 1-9 01-09 01-09 01-09 92 identification c ode (continued) 0000000 93 year of manufacturein bcd variable data variable data variable data 94 week of manufacture in bcd variable data variable data variable data 95-98 module serial number variable data variable data variable data 99-127 manufacturer-specific data (rsvd) ??? table 20: serial presence-detect matrix (continued) ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low ? ; notes appear on page 35 byte description entry (version) mt8vddt3232u mt8vddt6432u mt8vddt12832u
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trad emarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 128mb, 256mb, 512mb: (x32, dr) 100-pin ddr udimm module dimensions pdf: 09005aef80745603, source: 09005aef807455eb micron technology, inc., reserves the right to change products or specifications without notice. dd8c32_64_128x32ug_2.fm - rev. g 5/05 en 36 ?2004, 2005 micron technology, inc. all rights reserved. module dimensions all dimensions are in inches (millimeters); or typical where noted. figure 15: 100-pin dimm dimensions data sheet designation released (no mark): this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. max min u1 u2 u3 u4 u5 u 6 u7 u8 u9 0.157 (4.0) max pin 1 3.557 (90.34) 3.545 (90.04) 0.70 (17.8) typ 0.118 (3.0) dia (2x) 0.050 (1.27) typ 0.039 (1.0) typ 0.079 (2.00) r (2x) pin 50 pin 100 pin 51 front view 2.85 (72.39) typ 0.118 (3.0) typ 0.054 (1.37) 0.04 6 (1.17) 0.039 (1.0) r (2x) 0.039 (1.0) typ ba c k view 1.20 6 (30. 6 3) 1.19 6 (30.37) 0.118 (3.0) typ 0.084 (2.13) typ 1.7 6 5 (44.83) typ 1.0 (25.4) typ

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