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| realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 RTL8196C-GR ieee 802.11n ap/router network processor with eee datasheet (confidential: development partners only) rev. 1.2 23 march 2010 track id: jatr-2265-11 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com www.datasheet.net/ datasheet pdf - http://www..co.kr/
realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee ii track id: jatr-2265-11 rev. 1.2 copyright ?2010 realtek semiconductor corp. all rights reserved. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permissi on of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without warranty of any kind. realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. this document could include technical inaccura cies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. using this document this document provides detailed user guidelines to achieve the best performance when implementing the rtl8196c. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the production of this guide. revision history revision release date summary 1.1 2010/03/18 first release. 1.2 2010/03/23 revised ieee 802.3az draft version from draft 2.0 to draft 2.3. revised figure 3 one 16-bit, for 1m/2m/4m/8m bytes flash configuration, page 12. www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee iii track id: jatr-2265-11 rev. 1.2 table of contents 1. general desc ription ............................................................................................................ ..................................1 2. features ....................................................................................................................... ..................................................2 3. block diagram .................................................................................................................. .........................................4 4. pin assignments ................................................................................................................ .........................................5 4.1. p in a ssignments ............................................................................................................................... ........................5 4.2. p ackage i dentification ............................................................................................................................... ............5 5. pin descriptions............................................................................................................... ..........................................6 5.1. rtl8196c c onfiguration u pon p ower o n s trapping ........................................................................................9 5.2. s hared i/o p in m apping ............................................................................................................................... ..........10 6. memory co ntro ller .............................................................................................................. ..............................11 6.1. sdram c ontrol i nterface ............................................................................................................................... ...11 6.1.1. features....................................................................................................................... .........................................11 6.2. nor f lash t ype m emory ............................................................................................................................... .......11 6.2.1. features....................................................................................................................... .........................................11 6.2.2. bank address mapping........................................................................................................... ..............................12 6.2.3. flash command sequence......................................................................................................... ...........................12 6.3. spi f lash c ontroller ............................................................................................................................... ............13 6.3.1. features....................................................................................................................... .........................................13 6.4. s oftware r egister d efinition .............................................................................................................................13 6.4.1. memory control register (mcr) (0xb 800_1000) .................................................................................... ...........13 6.4.2. dram configuration regist er (dcr) (0 xb800_1004)................................................................................ ........14 6.4.3. dram timing register (dtr) (0 xb800_10 08)....................................................................................... .............15 6.4.4. nor flash configuration regi ster (nfcr) (0xb80 0_1100) .......................................................................... .....16 6.4.5. spi flash configuration regi ster (sfcr) (0xb800_1 200).......................................................................... ........16 6.4.6. spi flash configuration regi ster 2 (sfcr2 ) (0xb800 _1204) ....................................................................... ......17 6.4.7. spi flash control and status re gister (sfcsr) (0xb800_1208) .................................................................... ....18 6.4.8. spi flash data register (sfdr) (0 xb800_1 20c) ................................................................................... ............18 6.4.9. spi flash data register 2 (sfdr2) (0xb800_1210)................................................................................ ...........19 7. peripheral and misc control .................................................................................................... ....................20 7.1. gpio c ontrol ............................................................................................................................... ..........................20 7.1.1. gpio register se t (0xb80 0_3500)................................................................................................ .......................20 7.1.2. gpio port a, b, c, d control re gister (pabcd_cnr ) (0xb800_3500)............................................................20 7.1.3. gpio port a, b, c, d direction re gister (pabcd_dir) (0xb800_3508)..........................................................21 7.1.4. port a, b, c, d data regist er (pabcd_dat) (0xb800_3 50c) ........................................................................ ..21 7.1.5. port a, b, c, d interrupt status register (pabcd_isr) (0xb800_3510) ...........................................................2 1 7.1.6. port a, b interrupt mask regi ster (pab_imr) (0xb800_3514) ...................................................................... ....22 7.1.7. port c, d interrupt mask regi ster (pcd_imr) (0xb800_3518)...................................................................... ...22 7.2. gpio s hared p in m apping l ist .............................................................................................................................23 7.2.1. shared pin register (pin _mux_sel) (0xb800_0040) ................................................................................ .......23 7.2.2. shared pin register (pin _mux_sel2) (0 xb800_0 03c) ............................................................................... .....24 8. green eth ernet ................................................................................................................. ......................................25 8.1. c able l ength p ower s aving ............................................................................................................................... .25 8.2. l ink d own p ower s aving ............................................................................................................................... .......25 8.3. e nergy e fficient e thernet (eee)........................................................................................................................25 www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee iv track id: jatr-2265-11 rev. 1.2 9. dc specifications.............................................................................................................. ......................................26 9.1. o perating c onditions ............................................................................................................................... ............26 9.2. p ower d issipation ............................................................................................................................... ...................26 9.3. sdram b us dc p arameters ............................................................................................................................... .27 9.4. f lash b us dc p arameters ............................................................................................................................... .....27 9.5. usb 1.1 dc p arameters ............................................................................................................................... ..........28 9.6. usb 2.0 dc p arameters ............................................................................................................................... ..........28 9.7. uart dc p arameters ............................................................................................................................... ............28 9.8. gpio dc p arameters ............................................................................................................................... ..............29 9.9. jtag dc p arameters ............................................................................................................................... .............29 9.10. led dc p arameters ............................................................................................................................... ...............29 10. ac specifications.............................................................................................................. .................................30 10.1. c lock s ignal t iming ............................................................................................................................... ...............30 10.1.1. sdram cloc k timing............................................................................................................. .........................31 10.2. b us s ignal t iming ............................................................................................................................... ...................32 10.2.1. sdram bus ...................................................................................................................... ...............................32 10.2.2. flash bus ...................................................................................................................... ...................................34 10.2.3. power sequence................................................................................................................. ..............................34 10.2.4. power configur ation ti ming ..................................................................................................... ......................35 11. thermal char acteristics ........................................................................................................ ...................36 11.1. t hermal o perating r ange ............................................................................................................................... ....37 11.2. rtl8196c t hermal p arameters ..........................................................................................................................37 12. mechanical dimensions.......................................................................................................... .......................38 12.1. p lastic q uad f lat p ackage 128-p in 14 x 20 mm o utline ....................................................................................38 13. ordering information ........................................................................................................... ........................39 www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee v track id: jatr-2265-11 rev. 1.2 list of tables t able 1. p in d escriptions ............................................................................................................................... .........................6 t able 2. rtl8196c c onfiguration u pon p ower o n s trapping .........................................................................................9 t able 3. s hared i/o p in m apping ............................................................................................................................... ...........10 t able 4. m emory c ontrol r egister (mcr) (0 x b800_1000) .............................................................................................13 t able 5. dram c onfiguration r egister (dcr) (0 x b800_1004)......................................................................................14 t able 6. dram t iming r egister (dtr) (0 x b800_1008).....................................................................................................15 t able 7. nor f lash c onfiguration r egister (nfcr) (0 x b800_1100)............................................................................16 t able 8. spi f lash c onfiguration r egister (sfcr) (0 x b800_1200) ...............................................................................16 t able 9. spi f lash c onfiguration r egister 2 (spcr2) (0 x b800_120 4) ..........................................................................17 t able 10. spi f lash c ontrol and s tatus r egister (sfcsr) (0 x b800_1208) ..................................................................18 t able 11. spi f lash d ata r egister (sfdr) (0 x b800_120c)...............................................................................................18 t able 12. spi f lash d ata r egister 2 (sfdr2) (0 x b800_12 10)...........................................................................................19 t able 13. gpio r egister s et (0 x b800_35 00)..................................................................................................................... ...20 t able 14. gpio p ort a, b, c, d c ontrol r egister (pabcd_cnr) (0 x b800_3500) .........................................................20 t able 15. gpio p ort a, b, c, d d irection r egister (pabcd_dir) (0 x b800_3508) ........................................................21 t able 16. p ort a, b, c, d d ata r egister (pabcd_dat) (0 x b800_350 c).........................................................................21 t able 17. p ort a, b, c, d i nterrupt s tatus r egister (pabcd_isr) (0 x b800_3510)......................................................21 t able 18. p ort a, b i nterrupt m ask r egister (pab_imr) (0 x b800_351 4) .....................................................................22 t able 19. p ort c, d i nterrupt m ask r egister (pcd_imr) (0 x b800_351 8) .....................................................................22 t able 20. s hared p in r egister (pin_mux_sel) (0 x b800_0040) ......................................................................................23 t able 21. s hared p in r egister (pin_mux_sel2) (0 x b800_003c)....................................................................................24 t able 22. o perating c onditions ............................................................................................................................... ............26 t able 23. p ower d issipation ............................................................................................................................... ...................26 t able 24. sdram b us dc p arameters ............................................................................................................................... .27 t able 25. f lash b us dc p arameters ............................................................................................................................... .....27 t able 26. usb 1.1 dc p arameters ............................................................................................................................... ..........28 t able 27. usb 2.0 dc p arameters ............................................................................................................................... ..........28 t able 28. uart dc p arameters ............................................................................................................................... ............28 t able 29. gpio dc p arameters ............................................................................................................................... ..............29 t able 30. jtag dc p arameters ............................................................................................................................... .............29 t able 31. led dc p arameters ............................................................................................................................... ...............29 t able 32. c lock s ignal t iming ............................................................................................................................... ...............30 t able 33. sdram c lock t iming ............................................................................................................................... .............31 t able 34. sdram i nput t iming ............................................................................................................................... ..............32 t able 35. sdram o utput t iming ............................................................................................................................... ...........32 t able 36. sdram a ccess c ontrol t iming ..........................................................................................................................33 t able 37. f lash a ccess t iming v alues ............................................................................................................................... .34 t able 38. p ower -u p t iming p arameters ..............................................................................................................................3 4 t able 39. t hermal o perating r ange ............................................................................................................................... ....37 t able 40. rtl8196c t hermal p arameters ..........................................................................................................................37 t able 41. o rdering i nformation ............................................................................................................................... ...........39 www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee vi track id: jatr-2265-11 rev. 1.2 list of figures f igure 1. b lock d iagram ............................................................................................................................... .........................4 f igure 2. p in a ssignments ............................................................................................................................... ........................5 f igure 3. o ne 16- bit , for 1m/2m/4m/8m b ytes f lash c onfiguration ............................................................................12 f igure 4. t ypical c onnection to a c rystal ......................................................................................................................30 f igure 5. t ypical c onnection to an o scillator ...............................................................................................................30 f igure 6. sdram c lock s pecifications -1 ..........................................................................................................................31 f igure 7. sdram c lock s pecifications -2 ..........................................................................................................................31 f igure 8. sdram i nput t iming ............................................................................................................................... ..............32 f igure 9. sdram o utput t iming ............................................................................................................................... ..........32 f igure 10. sdram a ccess c ontrol t iming .........................................................................................................................33 f igure 11. f lash a ccess t iming ............................................................................................................................... ..............34 f igure 12. p ower u p s equence t iming d iagram .................................................................................................................34 f igure 13. p ower u p c onfiguration t iming d iagram ........................................................................................................35 www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 1 track id: jatr-2265-11 rev. 1.2 1. general description the rtl8196c is an integrated system-on-a-chip (s oc) application specific integrated circuit (asic) that implements a basic l2 5-port ethernet switc h and a high performance cpu. the embedded risc cpu is an rlx4181, and the clock rate can be up to 400mhz. to improve computational performance, a 16-kbyte i-cache, 8-kbyte d-cache, 16-k i-mem, and 8-kbyte d-mem are provided. a standard 5- signal p1149.1 compliant ejtag test interface is suppor ted for cpu testing and software development. the rtl8196c provides five ports (from port 0 to por t 4), integrated with five mac and five physical layer transceivers for 10b ase-t and 100base-tx. each port of th e rtl8196c may be configured as a lan or wan port. the rtl8196c supports flexible ieee 802.3x full-dupl ex flow control and optional half-duplex backpressure control. for full-duplex, standard i eee 803.3x flow control will enable pause ability only when both sides of utp have auto-negotiation abili ty and have enabled pa use ability. the rtl8196c also provides optional forced mode ieee 802.3x full- duplex flow control. based on optimized packet memory management, the rtl8196c is capab le of head-of-line blocking prevention. l2 switch features: the rtl8196c contains a 1024- entry address look-up table with a 10-bit 4-way xor hashing algorithm for address searching and lear ning. auto aging of each entry is provided and the aging time is 300~450 seconds. the rtl8196c supports ieee 802.3az draft 2.3, also kno wn as energy efficien t ethernet (eee). ieee 802.3az operates with the ieee 802.3 media access cont rol (mac) sublayer to support operation in low power idle mode. when the ethernet network is in low link utilization, eee allows systems on both sides of the link to save power. green ethernet po wer saving provides: link-on and dynamic detection of cable length, and dynamic adjustment of power requi red for the detected cable length. this feature provides high performance with minimum power c onsumption. the rtl8196c also implements link- down power saving on a per-port basis, greatly cutting power consump tion when the network cable is disconnected. for peripheral interfaces, one 1655 0-compatible uart is supported, and a 16-byte fifo buffer is provided. a usb 2.0 host controller is embedded in the rtl8196c to prov ide ehci and ohci 1.1 compliant host functionality. a usb phy is also embedded in the rtl8196c. an mdi/mdix auto-crossover function is suppor ted. for accessing high-speed devices, the rtl8196c provides a pci express bridge to access a pci express interface. the rtl8196c requires only a single 25mhz crystal or 40mhz clock input for the system pll. the rtl8196c also has two hardware timers and one watchdog timer to provide accurate timing and watchdog functionality. for extension and flexib ility, the rtl8196c has up to 22 gpio pins. the rtl8196c is provided in a pqfp 128-pin package. it requires only a 3.3v and 1.0v external power supply. www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 2 track id: jatr-2265-11 rev. 1.2 2. features ? soc ? embedded risc cpu, rlx4181 with 16k i-cache, 8k d-cache, 16k i-mem, 8k d-mem ? supports mips-1 isa, mips16 isa ? clock rate up to 400mhz ? provides a standard 5-signal p1149.1 ejtag test port ? supports rlx4181 cpu suspend mode ? l2 capabilities ? five ethernet mac integrated switch with five 10m/100mbps physical layers and transceivers for ieee 802.3 10base-t and 100base-tx ? non-blocking wire-speed reception and transmission and non-head-of-line- blocking/forwarding ? internal 512kbit sram for packet buffering ? internal 1024 entry 4-way hash l2 look- up table ? supports source and destination mac address filtering ? supports ieee 802.1x port-based and mac-based network access control ? complies with ieee 802.3/802.3u/802.1q/802.1d ? flexible full-duplex 802.3x flow control and optional half-duplex backpressure flow control ? mac learning supports shared vlan learning (svl) and independent vlan learning (ivl) modes ? cpu interface (nic) ? supports bsd mbuf-like packet structure with adjustable cluste r size (128-byte to 2kbyte) to provide optimum memory utilization ? provides the ?to-cpu reason? in the packet header to facilitate packet processing ? the nic dma supports multiple- descriptor-ring architecture for qos applications (supports 6 rx descriptor rings and 2 tx descriptor rings) ? peripheral interfaces ? supports one pci express host with integrated phy ? supports one 16550 uart ? supports up to 22 gpio pins ? supports one-port usb 2.0 host interface ? embedded usb phy ? memory interfaces ? nor flash ? supports two flash banks that can be configured as 8/16-bit bus, 256k/512k /1m/2m/4m/8m bytes ? system supports up to 16mbyte flash memory space ? boot up from nor flash is supported ? spi flash ? supports 4 channels for spi flash application ? boot up from spi flash is supported ? system supports up to 32mbyte flash memory space www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 3 track id: jatr-2265-11 rev. 1.2 ? sdram ? supports two sdram banks that can be configured as 2m/4m/8m/16m/ 32m/64mbyte ? 16-bit sdram data bus is supported. system totally supports up to 128mbyte sdram memory space ? supports green ethernet ? cable length power saving ? power down power saving ? supports ieee 802.3az draft 2.3 energy efficient ethernet (eee) for 100base-tx in full duplex operation, and 10base-t in full/half duplex mode ? other add-on-value features ? supports link down power saving in ethernet phy ? supports two hardware timers and one watchdog timer ? per-port configurable auto-crossover function ? single 25mhz crystal or 40mhz clock input ? pqfp 128-pin package www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 4 track id: jatr-2265-11 rev. 1.2 3. block diagram figure 1. block diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 5 track id: jatr-2265-11 rev. 1.2 4. pin assignments 4.1. pin assignments reset#/gpiob7 gpioc[0] led_port4/gpiob6 40m_sel 40m_clk vdd33 led_port2/gpiob4 led_port3/gpiob5 vdd10 25m_xo vdd10_usb 25m_xi avdd33_25m agnd_pcie refclkp refclkn avdd10_pcie hsop hson usb_dn gnd avdd33_bg vdd33 ma1 ma8 103 124 123 122 121 125 128 127 126 113 112 111 110 109 108 107 106 105 104 114 120 119 118 117 116 115 ma11 55 59 56 58 60 57 62 61 63 64 54 53 47 48 50 49 51 52 43 44 46 45 39 40 42 41 ma3 ma9 ma12 ma2 ma0 ma10 ma14/bs1 ma7 ma19/sf_sdio1/gpioc[3] ma20/sf_sdio0/gpioc[4] ma4 ma21/sf_sck/gpioc[5] ma5 ma6 gnd ma17/sf_sdio3/gpioc[1] ma18/sf_sdio2/gpioc[2] vdd33 vdd33 vdd10 nf_cs0#/sf_cs0# nf_cs1#/sf_cs1#/mclke/gpioa1 avdd33_usb_pcie usb_dp hsin hsip figure 2. pin assignments 4.2. package identification green package is indicated by a ?g? in the location marked ?t? in figure 2. www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 6 track id: jatr-2265-11 rev. 1.2 5. pin descriptions in this section the following abbreviations are used: i: input ai: analog input o: output ao: analog output io: bi-directional input/output ai/o : analog bi-directional input/output p: digital power ap: analog power g: digital ground ag: analog ground t/s: tri-state bi-directional input/o utput s/t/s: sustained tri-state i pd: input pin with pull-down resistor o od: output with open drain i pu: input pin with pull-up resistor; (typical value = 75k ohm) o 3s: output with tri-state table 1. pin descriptions pin name pin no. type description clock & reset 25m_xi 127 i 25mhz crystal clock input 25m_xo 126 o 25mhz crystal clock output 40m_clk 125 i 40mhz clock input v peak-to-peak 1.4 voltage 40m_sel 124 i system clock source select. 0: 25mhz 1: 40mhz reset# 108 i the system reset active low 10m/100mbps physical layer txop[4:0] txon[4:0] 28, 26, 18, 16, 7 29, 25, 19, 15, 8 ao 10/100m ethernet physical layer transmit pair. for differential data transmission rxip[4:0] rxin[4:0] 30, 24, 20, 13, 9 31, 23, 21, 12, 8 ai 10/100m ethernet phys ical layer receive pair. for differential data reception memory bus md[15:0] 94, 93, 92, 91, 90, 89, 88, 87, 74, 75, 77, 78, 79, 80, 81, 82 i/o data for sdram and nor type flash ma[21:0] 48, 47, 46, 45, 43, 85, 72, 63, 65, 57, 56, 62, 55, 53, 52, 51, 50, 49, 58, 59, 60, 61 o address for sdram and nor type flash. shared pins: ma[13]: sdram bs0 ma[14]: sdram bs1 ma[15]: sdram ldqm ma[16]: sdram udqm ma[17]: spi flash sdio3 ma[18]: spi flash sdio2 ma[19]: spi flash sdio1 ma[20]: spi flash sdio0 ma[21]: spi flash sck www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 7 track id: jatr-2265-11 rev. 1.2 pin name pin no. type description sdram control mclk 84 o sdram clock mclke 40 o sdram clock enable mcs0# 66 o sdram bank 0 chip select mcs1# 67 o sdram bank 1 chip select bs[1:0] 63, 65 o sdram chip bank select [1:0] shared with a[14:13] ras# 69 o raw address strobe for sdram cas# 70 o column address strobe for sdram we# 71 o write enable for sdram ldqm 72 o lower data mask output to sdram corresponds to d[7:0] pin shared with a[15] udqm 85 o upper data mask output to sdram corresponds to d[15:8] pin shared with a[16] nor type flash control nf_cs0# 41 o rom bank 0 chip select for nor type flash memory nf_cs1# 40 o rom bank 0 chip select for nor type flash memory oe# 69 o output enable (oe#) for nor type flash. pin shared with sdram ras# we# 71 o write enable for nor type flash. pin shared with sdram we# spi serial flash control sf_cs0# 41 o spi serial flash chip select 0 pin shared with nof_cs0# sf_cs1# 40 o spi serial flash chip select 1 pin shared with nof_cs1# sf_sdio[3:0] 43, 45, 46, 47 i/o spi serial flash se rial data input/output sf_sck 48 o spi serial flas h serial clock output the sf_sdi will be driven on the falling edge the sf_sdo will be latched on the rising edge uart uart_tx 37 o uart data transmit serial output uart_rx 36 i pd uart data receive serial input jtag jtag_tck 100 i pu jtag test clock jtag_tms 97 i pu jtag test mode select jtag_tdo 98 o jtag test data output jtag_tdi 99 i pu jtag test data in jtag_trst# 96 i pu jtag test reset led led_port[4:0] 107, 105, 104, 102, 101 o link/activity status of 5 ethernet ports www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 8 track id: jatr-2265-11 rev. 1.2 pin name pin no. type description gpio gpioa[7:0] 36, 98, 99, 97, 96, 100, 40, 67 i/o gpio port a gpiob[7:0] 108, 107, 105, 104, 102, 101, 4, 37 i/o gpio port b gpioc[5:0] 48, 47, 46, 45, 43, 109 i/o gpio port c pci express interface hson hsop 115 116 ao transmitter differential pair hsin hsip 121 122 ai receiver differential pair refclkn refclkp 118 119 ao reference clock differential pair pcie_rst# 4 o pci express reset active low usb2.0 usb_dp 113 ai/o usb device data plus pin usb_dn 112 ai/o usb device data minus pin test tesetmode 38 i pd for chip internal test 1: test mode 0: normal mode reference voltage ibref 33 ai reference voltage for ethernet phy 2.5k 1% pull down r12k 1 ai reference voltage for system 12k 1% pull down power & gnd vdd33 3, 44, 54, 64, 76, 86, 95, 106 p digital i/o power supply 3.3v avdd33 11, 22, 32 ap ethernet analog power supply 3.3v vdd10 5, 39, 73, 103 p digital core power supply 1.0v avdd10 6, 17, 27 ap ethernet analog power supply 1.0v avdd33_x25m 123 ap 25m crystal power 3.3v avdd33_bg 128 ap system bandgap power supply 3.3v avdd10_pcie 117 ap pci express analog power supply 1.0v avdd10_phypll 34 ap ethernet phy pll power 1.0v avdd33_usb_pcie 114 ap usb2.0 and pci express analog power 3.3v vdd10_usb 110 ap shared power pin for usb2.0 analog power 1.0v and digital core power supply 1.0v (vdd10) gnd 14, 42, 68, 83, 111 g system gnd agnd_syspll 2 ag system pll gnd agnd_pcie 120 ag pci express gnd www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 9 track id: jatr-2265-11 rev. 1.2 5.1. rtl8196c configuration upon power on strapping all mode configuration pins are inte rnal pull low. the 1.0v digital core power input pin voltage is up to 0.7v on system power-on. the strap data wi ll be latched afte r a delay of 300ms. table 2. rtl8196c configuration upon power on strapping h/w pin name configuration name pin no description ma11, ma10, ma9 ck_cpu_freq_sel[2:0] 56, 62, 55 cpu clock configuration 000: 250mhz 001: 270mhz 010: 290mhz 011: 310mhz 100: 330mhz 101: 350mhz 110: 370mhz 111: 390mhz ma8, ma7, ma6 ck_freq_sel[2:0] 53, 52, 51 sdram clock rate configuration 000: 65.625mhz 001: 78.125mhz 010: 125mhz 011: 150mhz 100: 156.25mhz 101: 168.75mhz 110: 193.75mhz 111: reserved ma5 sync_lx_oc 50 selection for internal bus test mode this is a hardware strapping pin. 0: normal mode 1: test mode ma2 enoltautotestmode 59 enable operational level test (olt) auto test mode 0: normal mode 1: test mode ma1 bootsel 60 boot device select for flash booting 0: boot from nor-type flash (default) 1: boot from serial flash (spi) ma3 clklx_from_clkm 58 internal local bus source 0: 200mhz 1: from memory clock ma4 enable_ext_rstn 49 external reset 0: disable chip reset function; pin 108 can be used as a gpio or dbg pin 1: enable chip reset function ma12 ck_cpu_div_sel 57 pll clock for cpu 0: cpu pll clock is not divided by 2 1: cpu pll clock is divided by 2 ma13 en_router_mode 65 router or ap mode select 0: ap mode (turns-off ethernet switch and port 0 to port 3 phy circuit for power-saving) 1: router mode (all ethernet ports are working) ma14 swap_dbg_halfword 63 internal debug mode select www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 10 track id: jatr-2265-11 rev. 1.2 5.2. shared i/o pin mapping table 3. shared i/o pin mapping pin no. gpio ejtag led uart reset memory 67 gpioa[0] - - - - mcs1# 40 gpioa[1] - - - - nf_cs1# sf_cs1# mclke 100 gpioa[2] jtag_tck - - - - 96 gpioa[3] jtag_trst# - - - - 97 gpioa[4] jtag_tms - - - - 99 gpioa[5] jtag_tdi - - - - 98 gpioa[6] jtag_tdo - - - - 36 gpioa[7] - - uart_rx - - 37 gpiob[0] - - uart_tx - - 4 gpiob[1] - - - pcie_rst# - 101 gpiob[2] - led_port0 - - - 102 gpiob[3] - led_port1 - - - 104 gpiob[4] - led_port2 - - - 105 gpiob[5] - led_port3 - - - 107 gpiob[6] - led_port4 - - - 108 gpiob[7] - - - reset# - 109 gpioc[0] - - - - - 43 gpioc[1] - - - - ma17 45 gpioc[2] - - - - ma18 46 gpioc[3] - - - - ma19 47 gpioc[4] - - - - ma20 48 gpioc[5] - - - - ma21 www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 11 track id: jatr-2265-11 rev. 1.2 6. memory controller the rtl8196c integrates a memory control modul e to access external sdram and flash memory. the interface is designed for pc133 or pc166-co mpliant sdram, and suppor ts auto-refresh mode, which requires a 4096 refresh cycle within 64ms, a nd the sdram size and timi ng is configurable in registers. the rtl8196c also supports one flash memory ch ip (nf_cs0#). the interf ace supports 8/16-bit nor- type flash memory. when nor type is used, the system will boot from ks eg1 at virtual address 0xbfc0_0000 (physical address: 0x1fc 0_0000). the flash size is configurab le from 1m to 8m bytes for each chip. if the flash size is set to 4m or 8m bytes, 0xbfc0_0000 still maps the first 4m bytes of flash, and there will be a new memory mapping from 0xbd00_0000 (0xbd00_0000 maps to chip 0 byte 0). 6.1. sdram control interface pc100~pc166-compliant sdram is supported. the sd ram controller supports auto refresh mode, which requires a 4096-cycle refr esh each 64ms. the rtl8196c provides a maximum of 512mbit address space (8mx16x4banks) and the sd ram size is configurable. 6.1.1. features ? interface (bus width): 16-bit ? targeted sdr frequency: up to 166mhz ? supported sdr sdram chip specification: ? bank counts: 2, 4 ? row counts: 2k (a0~a10), 4k (a0~a11), 8k (a0~a12) ? column counts: 256 (a0~a7), 512 (a0~a8 ), 1k (a0~a9), 2k (a0~a9, a11) 6.2. nor flash type memory 6.2.1. features ? interface (bus width): 8-bit/16-bit ? supports nor flash chip specification: ? 8-bit: 256kbyte, 512kbyte, 1mbyte, 2mbyte, 4mbyte ? 16-bit: 512kbyte, 1mbyte, 2mbyte, 4mbyte, 8mbyte www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 12 track id: jatr-2265-11 rev. 1.2 6.2.2. bank address mapping the flash controller supports boot sector flash memory and the syst em always boots from bank0. the boot bank (bank 0) is mapped to kseg1 with the st art physical address of 0x1e 00.0000 (virtual address: 0xbd00.0000). bank0 is also mapped to th e start physical address of 0x1fc0.0000. the system always boots up from bank 0. for software, it is suggested that th e program jumps to the space [0x1e00.0000~0x1eff.ffff] for a larger continuous space after booting up from 0x1fc0.0000. however, for backward compatibility, the program can choose to stay in the 4mbyte space [0x1fc0.0000~0x1fff.ffff]. a4 a12 a18 sys_rst# r 1k a10 a16 d10 d15 a5 a3 a1 d11 d12 a7 f_cs0# c 0.1uf a19 r 1k d13 a13 d3 a0 d4 vddh oe# d7 d1 d2 d0 d14 d8 d9 vddh a21 a20 d6 a15 a9 a14 d5 r 10k a11 a8 a2 flash #1 a6 we# u3 flash 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 48 47 46 45 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we rst nc nc ry/by a18 a17 a7 a6 a5 a4 a3 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe gnd ce a0 a1 a2 a16 byte gnd q15/a-1 a17 figure 3. one 16-bit, for 1m/2m/4m/8m bytes flash configuration 6.2.3. flash command sequence directly write or read the target flash address following the command sequence specified in the flash memory provider?s datasheet. however, program mers must pay attention to the following: ? use 16-bit (half-word) manipulation. byte or full wo rd manipulation will cause unpredictable errors ? the program address is the address defined for the flash ? the command address is 0xbfc 0.0000 + command address * 2 ? program data/command data. the data may be placed in either the lower half-word or upper half- word position in a 32-bit full word. it depends on the least significant two bits of the accessed address www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 13 track id: jatr-2265-11 rev. 1.2 6.3. spi flash controller the spi flash controller is a new de sign and incorporates new features. 6.3.1. features ? targeted spi flash frequency: up to 78mhz (when the sdram clock is 156mhz) ? in addition to a programmed i/o interface, also supports a memory-mapped i/o interface for read operations ? supports read and fast read in memory-mapped i/o mode 6.4. software register definition 6.4.1. memory control register (mcr) (0xb800_1000) this register does not provide byte access. table 4. memory control register (mcr) (0xb800_1000) bit name description mode default 31 dramtype report the hardware st rapping initial value for dram type 0: sdr dram 1: reserved r 0b 30 bootsel report the hardware strapp ing initial value for boot flash type 0: nor flash 1: spi flash r 0b 29 ipref enable instruction prefetch function 0: disable prefetch (als o resets buffer status) 1: enable prefetch (4 words) rw 0b 28 dpref enable data prefetch function 0: disable prefetch (als o resets buffer status) 1: enable prefetch (4 words) rw 0b 27 ipref_mode choose instruction prefetch mode 0: old prefetch mechanism 1: new prefetch mechanism rw 0b 26 dpref_mode choose data prefetch mode 0: old prefetch mechanism 1: new prefetch mechanism rw 0b 25 bootsel2 report the hardware stra pping initial value for boot source 0: flash type (nor or spi flash) 1: reserved r 0b 24:0 reserved reserved r 0b www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 14 track id: jatr-2265-11 rev. 1.2 6.4.2. dram configuration regist er (dcr) (0xb800_1004) this register does not provide byte access. table 5. dram configuration register (dcr) (0xb800_1004) bit name description mode default 31:30 t_cas cas latency 00: latency=2 01: latency=3 10: latency=2.5 11: reserved rw 01b 29:28 dbuswid dram bus width 00: reserved 01: 16-bit 10: reserved 11: reserved rw 01b 27 dchipsel dram chip select 0: test mode 1: normal mode rw 1b 26:25 rowcnt row counts 00: 2k (a0~a10) 01: 4k (a0~a11) 10: 8k (a0~a12) 11: 16k (a0~a13) rw 00b 24:22 colcnt column counts 000: 256 (a0~a7) 001: 512 (a0~a8) 010: 1k (a0~a9) 011: 2k (a0~a9, a11) 100: 4k (a0~a9, a11, a12) 101: reserved 110: reserved 111: reserved rw 000b 21 bstref bursted 8 auto-refresh commands (used for ddr) 0: disable 1: enable rw 0b 20 arbit enforce interface ar bitration to take effect 0: reserved 1: take effect rw 0b 19 bankcnt bank counts 0: 2 banks (used for sdr) 1: 4 banks (used for sdr, ddr) rw 1b 18 fast_rx if rx path turnaround delay is small enough, the memory controller can return read data with reduced latency within 1dram clock cycle (used for ddr). 0: normal path 1: fast path rw 0b 17 mr_mode select the memory command that the memory controller issues (used for ddr) 0: mode register 1: extended mode register rw 0b 16 drv_str drive strength setting of dram chip (used for ddr) for this option to be effective, mr_mode must be first set to 1. 0: normal 1: reduced rw 0b 15:0 reserved reserved - - www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 15 track id: jatr-2265-11 rev. 1.2 6.4.3. dram timing register (dtr) (0xb800_1008) this register does not provide byte access. table 6. dram timing register (dtr) (0xb800_1008) bit name description mode default 31:29 t_rp trp timing parameter of dram basic unit = 1* dram_clk 000 means 1 unit rw 111b 28:26 t_rcd trcd timing parameter of dram basic unit = 1* dram_clk 000 means 1 unit rw 111b 25:21 t_ras minimum t_ras timing parameter of dram basic unit = 1* dram_clk 00000 means 1 unit rw 11111b 20:16 t_rfc trfc timing parameter of dram refresh row cycle time basic unit = 1* dram_clk 00000 means 1 unit rw 11111b 15:12 t_refi tref timing parameter of dram refresh row interval time basic unit = t_refi_unit 0000: 1 unit 0001: 2 units ? 1111: 16 units rw 0000b 11:9 t_refi_unit basic unit of t_refi 000: 32 dram_clk 001: 64 dram_clk 010: 128 dram_clk 011: 256 dram_clk 100: 512 dram_clk 101: 1024 dram_clk 110: 2048 dram_clk 111: 4096 dram_clk rw 111b 8:6 t_wr twr timing parameter of dram write recovery time basic unit = 1* dram_clk 000 means 1 unit rw 111b 5:0 reserved reserved - - www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 16 track id: jatr-2265-11 rev. 1.2 6.4.4. nor flash configuration register (nfcr) (0xb800_1100) this register does not provide byte access. table 7. nor flash configuration register (nfcr) (0xb800_1100) bit name description mode default 31:28 t_cepl the timing interval for ce# to be pulled-low before we#/oe# is pulled-low basic unit = 1 * dram clock cycle 0000 means 1 unit rw 1111b 27:23 t_weoepl the timing interval for we#/oe# to be pulled-low basic unit = 1 * dram clock cycle 00000 means 1 unit rw 11111b 22:19 t_rdoz the timing interval for oe# to be pulled-high before read-data output high-z basic unit = 1 * dram clock cycle 0000 means 1 unit rw 1111b 18:16 nfsize nor flash size 000: 256kbyte 001: 512kbyte 010: 1mbyte 011: 2mbyte 100: 4mbyte 101: 8mbyte 110: reserved 111: reserved rw 110b 15 nbusw nor flash bus width 0: 8-bit 1: 16-bit r 1b 14:0 reserved reserved - - 6.4.5. spi flash configuration regi ster (sfcr) (0xb800_1200) this register does not provide byte access. table 8. spi flash configurat ion register (sfcr) (0xb800_1200) bit name description mode default 31:29 spi_clk_div spi operating clock rate selection the value defines the divisor to generate the spi clock. spi clock = (sdram clock) / (spi_clk_div) 000: div = 2 001: div = 4 010: div = 6 011: div = 8 100: div = 10 101: div = 12 110: div = 14 111: div = 16 rw 111b 28 rbo serial flash read byte ordering 0: the byte order is from low to high 1: the byte order is from high to low rw 1b 27 wbo serial flash write byte ordering 0: the byte order is from low to high 1: the byte order is from high to low rw 1b 26-23 spi_tcs spi chip deselect time basic unit = 1 * dram clock cycle 0000 means 1 unit, 0001 means 2 units, etc. rw 1111b 22:0 reserved reserved - - www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 17 track id: jatr-2265-11 rev. 1.2 6.4.6. spi flash configuration regi ster 2 (sfcr2) (0xb800_1204) this register does not provide byte access. table 9. spi flash configuration register 2 (spcr2) (0xb800_1204) bit name description mode default 31:24 sfcmd spi flash 8-bit command code of a read transaction example: ?read data? is 0x03. ?fast read? is 0x0b. rw 0x03h 23:21 sfsize spi flash size 000: 128kbytes 001: 256kbytes 010: 512kbytes 011: 1mbytes 100: 2mbytes 101: 4mbytes 110: 8mbytes 111: 16mbytes rw 111b 20 rd_opt spi flash sequential access optimization 0: no optimization 1: optimization for sequential access rw 0b 19:18 cmd_io spi flash i/o mode selection for the command phase of a read transaction 00: serial i/o (8 cycles) 01: dual i/o (4 cycles) 10: quad i/o (2 cycles) 11: reserved rw 00b 17:16 addr_io spi flash i/o mode selection for the address phase of a read transaction 00: serial i/o (24 cycles) 01: dual i/o (12 cycles) 10: quad i/o (6 cycles) 11: reserved rw 00b 15:13 dummy_cycles spi flash inserted dummy cy cles for the dummy cycle phase of a read transaction 000: 0 cycles 001: 2 cycles 010: 4 cycles 011: 6 cycles 100: 8 cycles 101: 10 cycles 110: 12 cycles 111: 14 cycles rw 000b 12:11 data_io spi flash i/o mode selection fo r the data phase of a read transaction (assume 8*n cycles) 00: serial i/o (8*n cycles) 01: dual i/o (4*n cycles) 10: quad i/o (2*n cycles) 11: reserved rw 00b 10 hold_till_sfdr2 if this bit is ?1?, it indicates the write operation to this register (sfcr2) will not take effect immediately but will be delayed until another write operation to sfdr2. rw 0b 9:0 reserved reserved - - www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 18 track id: jatr-2265-11 rev. 1.2 6.4.7. spi flash control and status register (sfcsr) (0xb800_1208) this register does not provide byte access. table 10. spi flash control and status register (sfcsr) (0xb800_1208) bit name description mode default 31 spi_csb0 spi flash ch ip select 0 (cs0#) 0: active 1: not active rw 1b 30 spi_csb1 spi flash ch ip select 1 (cs1#) 0: active 1: not active rw 1b 29:28 len spi read/write data length (unit = byte) 00: 1 byte 01: 2 byte 10: 3 byte 11: 4 byte rw 11b 27 spi_rdy spi flash operation busy indication flag 0: busy (operation in progress) 1: ready (idle or spi access command is ready) r 1b 26:25 io_width spi flash i/o mode selection of a transaction 00: serial i/o 01: dual i/o 10: quad i/o 11: reserved rw 00b 24 chip_sel chip selection 0: cs0# 1: cs1# rw 0b 23:16 cmd_byte spi flash 8-bit command code of a transaction this field is only used in memory-mapped i/o (mmio) mode. example: ?read data? is 0x03. ?fast read? is 0x0b. rw 0b 15:0 reserved reserved - - 6.4.8. spi flash data register (sfdr) (0xb800_120c) this register does not provide byte access. this configuration register is used under pio (programmed i/o) access mode. table 11. spi flash data register (sfdr) (0xb800_120c) bit name description mode default 31:24 data3 read/write data byte 3 rw 0b 23:16 data2 read/write data byte 2 rw 0b 15:8 data1 read/write data byte 1 rw 0b 7:0 data0 read/write data byte 0 rw 0b www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 19 track id: jatr-2265-11 rev. 1.2 6.4.9. spi flash data register 2 (sfdr2) (0xb800_1210) this register does not provide byte access. this configuration register is used und er memory-mapped i/o (mmio) access mode. table 12. spi flash data register 2 (sfdr2) (0xb800_1210) bit name description mode default 31:24 data3 read/write data byte 3 rw 0b 23:16 data2 read/write data byte 2 rw 0b 15:8 data1 read/write data byte 1 rw 0b 7:0 data0 read/write data byte 0 rw 0b www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 20 track id: jatr-2265-11 rev. 1.2 7. peripheral and misc control 7.1. gpio control the rtl8196c provides four sets of general purpos e input/output (gpio) pins (gpio a, b, c, d). each gpio pin may be configured as an input or output pin. the gp io data register may be used to control gpio pin signals. the gpio pins are shared w ith some peripheral pins, and the type of peripheral can affect the attributes of the shared pins. all gpio sets can be used to generate interrupts, and an interrupt mask and status register are provided. all the gpio control registers are defined in the following tables. 7.1.1. gpio register set (0xb800_3500) table 13. gpio register set (0xb800_3500) offset size (byte) name description 0x00 4 pabcd_cnr port a, b, c, d control register 0x08 4 pabcd_dir port a, b, c, d direction register 0x0c 4 pabcd_dat port a, b, c, d data register 0x10 4 pabcd_isr port a, b, c, d interrupt status register 0x14 4 pab_imr port a, b interrupt mask register 0x18 4 pcd_imr port c, d interrupt mask register 7.1.2. gpio port a, b, c, d co ntrol register (pabcd_cnr) (0xb800_3500) table 14. gpio port a, b, c, d co ntrol register (pabcd_cnr) (0xb800_3500) bit name description rw default 31:24 pfc_d[7:0] pin function configuration of port d rw ffh 23:16 pfc_c[7:0] pin function configuration of port c rw ffh 15:8 pfc_b[7:0] pin function configuration of port b rw ffh 7:0 pfc_a[7:0] pin function configuration of port a bit value: 0: configured as gpio pin 1: configured as dedicated peripheral pin rw ffh www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 21 track id: jatr-2265-11 rev. 1.2 7.1.3. gpio port a, b, c, d dire ction register (pabcd_dir) (0xb800_3508) table 15. gpio port a, b, c, d dir ection register (pabcd_dir) (0xb800_3508) bit name description rw default 31:24 drc_d[7:0] pin direction configuration of port d 0: configured as input pin 1: configured as output pin rw 00h 23:16 drc_c[7:0] pin direction configuration of port c 0: configured as input pin 1: configured as output pin rw 00h 15:8 drc_b[7:0] pin direction configuration of port b 0: configured as input pin 1: configured as output pin rw 00h 7:0 drc_a[7:0] pin direction configuration of port a 0: configured as input pin 1: configured as output pin rw 00h 7.1.4. port a, b, c, d data regi ster (pabcd_dat) (0xb800_350c) table 16. port a, b, c, d data register (pabcd_dat) (0xb800_350c) bit name description rw default 31:24 pd_d[7:0] pin data of port d 0: data=0 1: data=1 rw 00h 23:16 pd_c[7:0] pin data of port c 0: data=0 1: data=1 rw 00h 15:8 pd_b[7:0] pin data of port b 0: data=0 1: data=1 rw 00h 7:0 pd_a[7:0] pin data of port a 0: data=0 1: data=1 rw 00h 7.1.5. port a, b, c, d interrupt status register (pabcd_isr) (0xb800_3510) table 17. port a, b, c, d interrupt st atus register (pabcd_isr) (0xb800_3510) bit name description rw default 31:24 ips_d[7:0] interrupt pending status of port d write ?1? to clear the interrupt rw 00h 23:16 ips_c[7:0] interrupt pending status of port c write ?1? to clear the interrupt rw 00h 15:8 ips_b[7:0] interrupt pending status of port b write ?1? to clear the interrupt rw 00h 7:0 ips_a[7:0] interrupt pending status of port a write ?1? to clear the interrupt rw 00h www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 22 track id: jatr-2265-11 rev. 1.2 7.1.6. port a, b interrupt mask re gister (pab_imr) (0xb800_3514) table 18. port a, b interrupt mask register (pab_imr) (0xb800_3514) bit name description rw default 31:30 pb7_im[1:0] portb.7 interrupt mode rw 00b 29:28 pb6_im[1:0] portb.6 interrupt mode rw 00b 27:26 pb5_im[1:0] portb.5 interrupt mode rw 00b 25:24 pb4_im[1:0] portb.4 interrupt mode rw 00b 23:22 pb3_im[1:0] portb.3 interrupt mode rw 00b 21:20 pb2_im[1:0] portb.2 interrupt mode rw 00b 19:18 pb1_im[1:0] portb.1 interrupt mode rw 00b 17:16 pb0_im[1:0] portb.0 interrupt mode rw 00b 15:14 pa7_im[1:0] porta.7 interrupt mode rw 00b 13:12 pa6_im[1:0] porta.6 interrupt mode rw 00b 11:10 pa5_im[1:0] porta.5 interrupt mode rw 00b 9:8 pa4_im[1:0] porta.4 interrupt mode rw 00b 7:6 pa3_im[1:0] porta.3 interrupt mode rw 00b 5:4 pa2_im[1:0] porta.2 interrupt mode rw 00b 3:2 pa1_im[1:0] porta.1 interrupt mode rw 00b 1:0 pa0_im[1:0] porta.0 interrupt mode 00: disable interrupt 01: enable falling edge interrupt 10: enable rising edge interrupt 11: enable both falling or rising edge interrupt rw 00b 7.1.7. port c, d interrupt mask re gister (pcd_imr) (0xb800_3518) table 19. port c, d interrupt mask register (pcd_imr) (0xb800_3518) bit name description rw default 31:30 pd7_im[1:0] portd.7 interrupt mode rw 00b 29:28 pd6_im[1:0] portd.6 interrupt mode rw 00b 27:26 pd5_im[1:0] portd.5 interrupt mode rw 00b 25:24 pd4_im[1:0] portd.4 interrupt mode rw 00b 23:22 pd3_im[1:0] portd.3 interrupt mode rw 00b 21:20 pd2_im[1:0] portd.2 interrupt mode rw 00b 19:18 pd1_im[1:0] portd.1 interrupt mode rw 00b 17:16 pd0_im[1:0] portc.0 interrupt mode rw 00b 15:14 pc7_im[1:0] portc.7 interrupt mode rw 00b 13:12 pc6_im[1:0] portc.6 interrupt mode rw 00b 11:10 pc5_im[1:0] portc.5 interrupt mode rw 00b 9:8 pc4_im[1:0] portc.4 interrupt mode rw 00b 7:6 pc3_im[1:0] portc.3 interrupt mode rw 00b 5:4 pc2_im[1:0] portc.2 interrupt mode rw 00b 3:2 pc1_im[1:0] portc.1 interrupt mode rw 00b 1:0 pc0_im[1:0] portc.0 interrupt mode 00: disable interrupt 01: enable falling edge interrupt 10: enable rising edge interrupt 11: enable both falling or rising edge interrupt rw 00b www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 23 track id: jatr-2265-11 rev. 1.2 7.2. gpio shared pin mapping list the rtl8196c gpio pins are shared with other functions. 7.2.1. shared pin register (pin_mux_sel) (0xb800_0040) table 20. shared pin regist er (pin_mux_sel) (0xb800_0040) bit bit name description rw default 31:24 reserved reserved - - 23 reg_iocfg_pcie configure pcie_rst# as pcie_rst# or gpio 0: pcie_rst# 1: gpiob1 rw 2?b0 22 reg_iocfg_uart configure uart pins as uart, dbg, or gpio mode 0: uart 1: gpioa7 and gpiob0 rw 2?b0 21:20 reg_iocfg_jtag configure jtag pins as jtag, dbg, or gpio mode 0x: jtag 10: dbg mode 11: gpioa[6:2] rw 2?b00 19:18 reg_iocfg_mem configure flash/dram cs1# as flash/dram cs1#, dram cke, dbg, or gpio mode 00: nf_cs1#/mcs1# 01: dram cke 10: dbg mode 11: gpioa[1:0] rw 2?b00 17:14 reserved reserved - - 13:12 reg_iocfg_led_p2 configure ledphase2 pin as dbg or gpio mode 0x: reserved 10: dbg mode 11: gpioc0 rw 2?b00 11:10 reg_iocfg_led_p1 configure ledphase1 pin as dbg or gpio mode 0x: reserved 10: dbg mode 11: gpiob7 rw 2?b00 9:8 reg_iocfg_led_p0 configure ledphase0 pin as led-sw, dbg, or gpio mode 0x: led_port4 10: dbg mode 11: gpioc6 rw 2?b00 7:6 reg_iocfg_led_s3 configure ledsig3 pin as led-sw, dbg, or gpio mode 0x: led_port3 10: dbg mode 11: gpiob5 rw 2?b00 5:4 reg_iocfg_led_s2 configure ledsig2 pin as led-sw, dbg, or gpio mode 0x: led_port2 10: dbg mode 11: gpiob4 rw 2?b00 3:2 reg_iocfg_led_s1 configure ledsig1 pin as led-sw, dbg, or gpio mode 0x: led_port1 10: dbg mode 11: gpiob3 rw 2?b00 1:0 reg_iocfg_led_s0 configure ledsig0 pin as led-sw, dbg, or gpio mode 0x: led_port0 10: dbg mode 11: gpiob2 rw 2?b00 www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 24 track id: jatr-2265-11 rev. 1.2 7.2.2. shared pin register (pin_mux_sel2) (0xb800_003c) table 21. shared pin register (pin_mux_sel2) (0xb800_003c) bit bit name description rw default 31:21 reserved reserved - - 20:19 reg_iocfg_ma21 configure ma21 pin as dbg or gpio mode 00: ma21 01: reserved 10: dbg mode 11: gpioc5 rw 2?b00 18:17 reg_iocfg_ma20 configure ma20 pin as dbg or gpio mode 00: ma20 01: reserved 10: dbg mode 11: gpioc4 rw 2?b00 16:15 reg_iocfg_ma19 configure ma19 pin as dbg or gpio mode 00: ma19 01: reserved 10: dbg mode 11: gpioc3 rw 2?b00 14:13 reg_iocfg_ma18 configure ma18 pin as dbg or gpio mode 00: ma18 01: reserved 10: dbg mode 11: gpioc2 rw 2?b00 12:11 reg_iocfg_ma17 configure ma17 pin as dbg or gpio mode 00: ma17 01: reserved 10: dbg mode 11: gpioc1 rw 2?b00 10:0 reserved reserved - - www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 25 track id: jatr-2265-11 rev. 1.2 8. green ethernet 8.1. cable length power saving the rtl8196c provides link-on and dynamic detection of cable length, and dynamic adjustment of power required for the detected cable length. this feature provides high performance with minimum power consumption. 8.2. link down power saving the rtl8196c implements link-down power saving on a per-port basis, greatly cutting power consumption when the network cable is disconn ected. a port automatically enters link down power saving mode ten seconds after the cable is disconn ected from it. once a port enters link down power saving mode, it transmits normal link pulses on its txop/txon pins and continues to monitor the rxip/rxin pins to detect incoming signals, which might be 100base-tx mlt-3 idle pattern, 10base-t link pulses, or auto-negotiation?s flp (fast link puls e). after it detects an inco ming signal, it wakes up from link down power saving mode and operates in norma l mode according to the result of the connection. 8.3. energy efficient ethernet (eee) the rtl8196c supports ieee 802.3az draft 2.0, also kno wn as energy efficient ethernet (eee) in 100base-tx in full duplex operation, and 10base-t in full/half duplex mode. th is standard is being developed by the ieee 802.3az task force, and shoul d be finalized by sept ember 2010. it provides a protocol to coordinate transitions to/from a lower power consumption level (low power idle mode) based on link utilization. when no packets are being transmitte d, the system goes to low power idle mode to save power. once packets need to be transmitted, th e system returns to normal mode, and does this without changing the link status a nd without dropping/corrupting frames. to save power, when the system is in low power idle mode, most of the circui ts are disabled, however, the transition time to/from low power idle mode is kept small enough to be transparent to upper layer protocols and applications. eee also specifies a negotiation method to enable li nk partners to determine whether eee is supported and to select the best set of pa rameters common to both devices. ? for 100base-tx phy: supports energy efficient ethe rnet with the optional function of low power idle. ? for 10base-t, eee defines a 10mbps phy (10b ase-te) with reduced transmit amplitude requirements. 10base-te is fully interoperable w ith 10base-t phys over 100m of class-d (cat-5) cable. refer to http://ieee802.org/3/interi ms/index.html for more details. www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 26 track id: jatr-2265-11 rev. 1.2 9. dc specifications 9.1. operating conditions table 22. operating conditions symbol parameter min. typ. max. units vdd33 digital i/o power supply 3.3v 3.135 3.3 3.465 v avdd33 ethernet analog power supply 3.3v 3.135 3.3 3.465 v vdd10 core power supply 1.0v 0.95 1.0 1.05 v avdd10 ethernet analog power supply 1.0v 0.95 1.0 1.05 v avdd33_x25m 25m crystal power 3.3v 3.135 3.3 3.465 v vdd33_bg system bandgap power supply 3.3v 3.135 3.3 3.465 v avdd10_pcie pci express analog power 1.0v 0.95 1.0 1.05 v avdd10_phypll ethernet phy pll power 1.0v 0.95 1.0 1.05 v avdd33_usb_pcie usb 2.0 analog power 3.3v 3.135 3.3 3.465 v vdd10_usb usb 2.0 analog power 1.0v 0.95 1.0 1.05 v 9.2. power dissipation table 23. power dissipation parameter sym conditions typ. units power supply current for vdd33 i vdd33 all lan ports idle lan full load active for link at 10base-t lan full load active for link at 100base-tx 8 25 25 ma power supply current for vdd10 i vdd10 all lan ports idle and cpu suspend all lan ports idle lan full load active for link at 10base-t lan full load active for link at 100base-tx 110 210 300 300 ma 3.3v ethernet analog current for av d d 3 3 i avdd33 all lan ports idle lan ports no load link at 10base-t lan ports no load link at 10base-t (eee) lan ports no load link at 100base-t lan ports no load link at 100base-t (eee) lan full load active for link at 10base-t lan full load active for link at 100base-tx 30 72 72 72 13 113 72 ma 1.0v ethernet analog current for av d d 1 0 i avdd10 all lan ports idle lan ports no load link at 10base-t lan ports no load link at 10base-t (eee) lan ports no load link at 100base-t lan ports no load link at 100base-t (eee) lan full load active for link at 10base-t lan full load active for link at 100base-tx 5 5 5 48 5 5 48 ma 3.3v current for avdd33_x25m i avddx 25m crystal 3.3v current 2 ma 3.3v current for avdd33_bg i avddbg system bandgap 3.3v current 18 ma 1.0v current for avdd10_pcie i pcie pci express 1.0v current 63 ma 1.0v current for avdd10_phypll i phypll ethernet phy pll power 1.0v 4 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 27 track id: jatr-2265-11 rev. 1.2 parameter sym conditions typ. units 3.3v current for avdd33_usb_pcie i usb_avdd33 usb 2.0 and pci express analog power 3.3v 13 ma 1.0v current for vdd10_usb i lv_usb_pcie usb 2.0 analog power 1.0v 21 ma total power consumption ps all lan ports idle and cpu suspended all lan ports idle lan full load active for link at 10base-t lan full load active for link at 100base-tx 0.34 0.51 0.92 0.83 watt 9.3. sdram bus dc parameters table 24. sdram bus dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage lvttl 2.0 - - v 1 v il input-low voltage lvttl - - 0.8 v 2 v oh output-high voltage - 2.4 - - v 3 v ol output-low voltage - - - 0.4 v 3 i il input-leakage current v in =3.3v or 0 -10 1 10 a - i oz tri-state output-leakage current - -10 1 10 a - r pu input pull-up resistance - - 75 - k ? 4 r pd input pull-down resistance - - 75 - k ? 4 note 1: vih overshot: vih (max)=vddh + 2v for a pulse width 3ns, and the pulse width not greater than one third of the cycle rate. note 2: vil undershot: vil (min)=-2v for a pulse width 3ns cannot be exceeded. note 3: the output current buffer is 16ma for sdram clock, address, and data bus. note 4: these values are typica l values checked in the manufact uring process and are not tested. 9.4. flash bus dc parameters table 25. flash bus dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage lvttl 2.0 - - v 1 v il input-low voltage lvttl - - 0.8 v 2 v oh output-high voltage - 2.4 - - v 3 v ol output-low voltage - - - 0.4 v 3 i il input-leakage current v in =3.3v or 0 -10 1 10 a - i oz tri-state output-leakage current - -10 1 10 a - r pu input pull-up resistance - - 75 - k ? 4 r pd input pull-down resistance - - 75 - k ? 4 note 1: vih overshot: vih (max)=vddh + 2v for a pulse width 3ns. note 2: vil undershot: vil (min)= -2v for a pulse width 3ns. note 3: the output current buffer is 8ma for the flash address and data bus; and is 8ma for flash control signals. note 4: these values are typica l values checked in the manufact uring process and are not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 28 track id: jatr-2265-11 rev. 1.2 9.5. usb 1.1 dc parameters table 26. usb 1.1 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage - 2.0 - - v 2 v il input-low voltage - - - 0.8 v 2 v oh output-high voltage - 2.4 - - v 2 v ol output-low voltage - - - 0.4 v 2 i il input-leakage current v in =3.3v or 0 - - - a 1 note 1: these values are typica l values checked in the manufact uring process and are not tested. note 2: for additional information, see the usb 1.1 specification. 9.6. usb 2.0 dc parameters table 27. usb 2.0 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage - 200 - - mv 2 v il input-low voltage - - - 10 mv 2 v oh output-high voltage - 300 - 500 mv 2 v ol output-low voltage - -10 - 10 mv 2 i il input-leakage current - - - - a 1 note 1: these values are typica l values checked in the manufact uring process and are not tested. note 2: for additional information, see the usb 2.0 specifications. 9.7. uart dc parameters table 28. uart dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage lvttl 2.0 - - v - v il input-low voltage lvttl - - 0.8 v - v oh output-high voltage - 2.4 - - v 1 v ol output-low voltage - - - 0.4 v 1 i il input-leakage current v in =3.3v or 0 -10 1 10 a 2 r pu input pull-up resistance - - 75 - k ? 2 r pd input pull-down resistance - - 75 - k ? 2 note 1: the output current buffer is 8ma for uart related signals. note 2: these values are typica l values checked in the manufact uring process and are not tested. www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 29 track id: jatr-2265-11 rev. 1.2 9.8. gpio dc parameters table 29. gpio dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage lvttl 2.0 - - v - v il input-low voltage lvttl - - 0.8 v - v oh output-high voltage - 2.4 - - v 1 v ol output-low voltage - - - 0.4 v 1 i il input-leakage current - -10 1 10 a 2 r pd input pull-down resistance - - 75 - k ? 2 note 1: the output current buffer is 8ma for gpio related signals. note 2: these values are typica l values checked in the manufact uring process and are not tested. 9.9. jtag dc parameters table 30. jtag dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage lvttl 2.0 - - v - v il input-low voltage lvttl - - 0.8 v - v oh output-high voltage ? i oh ? =2~16ma 2.4 - - v 1 v ol output-low voltage ? i ol ? =2~16ma - - 0.4 v 1 i il input-leakage current - -10 1 10 a 2 r pd input pull-down resistance - - 75 - k ? 2 note 1: the output current buffer is 8ma for jtag related signals. note 2: these values are typica l values checked in the manufact uring process and are not tested. 9.10. led dc parameters table 31. led dc parameters symbol parameter conditions min. typ. max. units v ohed output-high voltage - 2.4 - - v v olled output-low voltage - - - 0.4 v note: the output current buffer for led signals is 8ma. www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 30 track id: jatr-2265-11 rev. 1.2 10. ac specifications 10.1. clock signal timing table 32. clock signal timing symbol parameter min. typ. max. units notes v ih input-high voltage 2.0 - - v - v il input-low voltage - - 0.8 v - t frequency clock frequency for rtl8196c crystal or oscillator - 25 - mhz 1 ? frequency clock tolerance (between 0oc~50oc) -50 - 50 ppm - c shunt crystal parameter note: sometimes referred to as the holder capacitance. - - 7 pf 2 c 1 load capacitance - - 30 pf 3 c 2 load capacitance - - 30 pf 3 t dc duty cycle note: this parameter applies when driving the clock input with an oscillator. - 50 - % - note 1: this value could be an oscillator input or a series re sonant frequency from a crystal. if used as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. note 2: the 25mhz crystal cl=16pf is used on the rtl8196c. note 3: the rtl8196c pll circuit requ ires an external 25mhz crystal with shunt capacitors. these shunt capacitors cannot be over 30pf due to chip design requirements. figure 4. typical connection to a crystal figure 5. typical connection to an oscillator www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 31 track id: jatr-2265-11 rev. 1.2 10.1.1. sdram clock timing table 33. sdram clock timing symbol parameter 130~180mhz units notes min. (130mhz) typ. (160mhz) max. (180mhz) t period_sdramclk clock period for sdram clock 7.7 6.25 5.5 ns - t clkhigh sdram clock high time 3.57 3.57 3.57 ns - t clklow sdram clock low time 3.57 3.57 3.57 ns - t rise/fall rising and falling time requirements for sdram clock - - 2 ns - t rise/fall_output propagation delay for output rising and falling - na - ns 1 note 1: please contact realtek for the ibis model. t period_sdramclk t clkhigh t clklow 0.5v ddh figure 6. sdram clock specifications-1 figure 7. sdram clock specifications-2 www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 32 track id: jatr-2265-11 rev. 1.2 10.2. bus signal timing 10.2.1. sdram bus 10.2.1.1 sdram input timing table 34. sdram input timing symbol parameter min. typ. max. units t setup input setup prior to rising edge of clock. inputs included in this timing are d[31:0] (during a read operation) - 1.13 - ns t hold input hold time after the rising edge of clock. inputs included in this timing are d[31:0] (during a read operation) - 0 - ns note: the rtl8196c integrates some timing controls on the in terface. here the timing parameters listed in the table are extracted in the default situation (without specific controls). figure 8. sdram input timing 10.2.1.2 sdram output timing table 35. sdram output timing symbol parameter min. typ. max. units t clk2out rising edge of clock-to-signal output. outputs included in this timing are d[31:0], cs0#, cs1#, ras#, cas#, ldqm, udqm, we# (during a write operation) - - 2.3 ns t holdout signal output hold time after the rising edge of the clock. outputs included in this timing are d[31:0] (during a write operation) 0.8 - - ns note: the rtl8196c integrates some timing controls on the in terface. here the timing parameters listed in the table are extracted in the default situation (without specific controls). figure 9. sdram output timing www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 33 track id: jatr-2265-11 rev. 1.2 10.2.1.3 sdram access control timing table 36. sdram access control timing symbol parameter units notes t refresh auto-refresh timing controlled by reg. 0xb8001008 (dtr) s - t rcd the time interval between ras# active and cas# active controlled by reg. 0xb8001008 (dtr) ns - t rp the time interval between pre-charge and the next active controlled by reg. 0xb8001008 (dtr) ns - t ras the time interval between active and pre-charge controlled by reg. 0xb8001008 (dtr) ns - t rc the time interval between active and the next active controlled by reg. 0xb8001008 (dtr) ns 1 t rfc the time interval between auto-refresh and active controlled by reg. 0xb8001008 (dtr) ns - t cas_latency the data output delay after cas# active controlled by reg. 0xb8001004 (dcr) ns - note 1: trc = tras + trp figure 10. sdram access control timing www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 34 track id: jatr-2265-11 rev. 1.2 10.2.2. flash bus table 37. flash access timing values symbol parameter min. typ. max. units t cs the timing interval between nf_cs0# (or nf_cs1#) and we# controlled by reg. 0xb8001100 (nfcr) ns t wp the timing interval for we# to be pulled low (ras# for read operation) controlled by reg. 0xb8001100 (nfcr) ns figure 11. flash access timing 10.2.3. power sequence table 38. power-up timing parameters symbol parameter min. typ. max. units t1 3.3v stable to 1.0v 1 - - ms note: the 3.3v (i/o) must be powered up before 1.0v core voltage and 1.0v analog voltage. figure 12. power up sequence timing diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 35 track id: jatr-2265-11 rev. 1.2 10.2.4. power configuration timing power up configuration only re lates to internal timing. the external ha rdware pin reset is irrelevant with regard to power up configuration. the hardware reset pin is valid when an internal reset ends the active state. 300ms ~ the latest stable power (1.0v) clk (25mhz crystal) config data (strapping pin) latch config data internal reset 200s ~ ~ ~ figure 13. power up configuration timing diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 36 track id: jatr-2265-11 rev. 1.2 11. thermal characteristics heat generated by the chip causes a temperature rise of the package. if the temp erature of the chip (tj, junction temperature) is beyond the design limits, ther e will be negative effects on operation and the life of the ic package. heat di ssipation, either through a he at sink or electrical fan, is necessary to provide a reasonable environment (ta, ambient temperature) in a closed case. as power density increases, thermal management becomes more critical. a method to estimate the possible ta is outlined below. thermal parameters are defined as below acco rding to jedec standard jesd 51-2, 51-6: (1) ja (thermal resistance from junction to ambient), represents resistance to heat flow from the chip to ambient air. this is an index of heat dissipation capability. a lower ja means better thermal performance. ja=(tj - ta) / p where tj is the die junction temperatur e, ta is the ambient air temperature p is the power dissipation by device (watts) (2) jc (thermal resistance junction-to-case, c/w), m easures the heat flow resistance between the die surface and the surface of the package (case). this data is relevant for packages used with external heat sinks. jc=(tj - tc) / p where tj is the die junction temperatur e, tc is the package case temperature p is the power dissipation by device (watts) (3) jt (thermal characterization para meter: junction to package top), represents the correlation between the temperature of the ch ip and the package top. jt=(tj - tt) / p where tj is the die junction temperature, tt is the top of package temperature p is the power dissipation by device (watts) www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 37 track id: jatr-2265-11 rev. 1.2 thermal terminology the major thermal dissipation paths can be illustrated as follows: tj: the maximum junction temperature ta: the ambient or environment temperature tc: the maximum compound surface temperature tb: the maximum surface temperature of pcb bottom p: total input power pqfp junction to ambient thermal resistance, ja, defined as: ja = tj - ta p 11.1. thermal operating range table 39. thermal operating range parameter sym condition min typical max units junction operating temperature tj - 0 - 125 c ambient operating temperature ta 4-layer fr4 pcb (without head sink) 0 25 65 c note: pcb conditions (jedec jesd51-7). dimensions: 76.2mm x 114.3mm; thickness: 1.6mm. 11.2. thermal parameters table 40. thermal parameters parameter sym condition air flow 0 m/s air flow 1 m/s air flow 2 m/s air flow 3 m/s units thermal resistance: junction to ambient ja 2-layer fr4 pcb 42.7 39.1 37.7 37.1 c/w thermal resistance: junction to ambient ja 4-layer fr4 pcb 35.4 34 33.4 32.9 c/w thermal characterization: junction to package top jt 2-layer fr4 pcb 6.8 7.8 8.3 8.8 c/w thermal characterization: junction to package top jt 4-layer fr4 pcb 4.6 5.3 5.7 5.9 c/w note: pcb conditions (jedec jesd51-7): dimensions: 76.2mm x 114.3mm; thickness: 1.6mm. t j t c t b ? ? ? t a t a p thermal dissipation of pqfp package www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 38 track id: jatr-2265-11 rev. 1.2 12. mechanical dimensions 12.1. plastic quad flat package 128-pin 14x20mm outline symbol dimension in mm dimension in inch min nom max min nom max a - - 3.40 - - 0.134 a 1 0.25 - - 0.010 - - a 2 2.50 2.70 2.90 0.100 0.106 0.114 b 0.17 0.22 0.27 0.007 0.009 0.011 d 23.2bsc 0.913bsc d 1 20.00bsc 0.787bsc e 17.20bsc 0.677bsc e 1 14.00bsc 0.551bsc e 0.50bsc 0.020bsc l 0.73 0.88 1.03 0.029 0.035 0.041 l1 1.60ref 0.063ref notes: controlling dime nsion: millimeter (mm). www.datasheet.net/ datasheet pdf - http://www..co.kr/ realtek confidential files the document authorized to t&w 2010-07-02 17:17:51 rtl8196c datasheet ieee 802.11n ap/router network processor with eee 39 track id: jatr-2265-11 rev. 1.2 13. ordering information table 41. ordering information part number package status RTL8196C-GR 128-pin pqfp, ?green? package mass production note: see page 5 for package and version identification. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu, 300, taiwan, r.o.c. tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com www.datasheet.net/ datasheet pdf - http://www..co.kr/ |
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