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4-bit single-chip microcomputer m pd75237 mos integrated circuit data sheet the information in this document is subject to change without notice. ? nec corporation 1991 document no. ic-2807a (o. d. no. ic-8009a) date published march 1993 p printed in japan the mark h shows major revised points. description the m pd75237 is a microcomputer with a cpu capable of 1-, 4-, and 8-bit-wise data processing, a rom, a ram, i/o ports, a fluorescent display tube (fip ? ) controller/driver, a/d converters, a watch timer, a timer/pulse generator capable of outputting 14-bit pwm, a serial interface and a vectored interrupt function integrated on a single-chip. the m pd75237 has the more improved peripheral functions including the ram capacity, fip controller/driver display capabilities, i/o ports, a/d converter and serial interface than those of the m pd75217. the m pd75237 is most suited for advanced and popular vcr timer and tuner applications, single-chip configu- rations of system computers, advanced cd players and advanced microwave ovens. the m pd75p238 prom product and various types of development tools (ie-75001-r, assemblers and others) are available for evaluation in system development or small-volume production. features l built-in, large-capacity rom and ram ? program memory (rom): 24k 8 ? data memory (ram): 1k 4 l i/o port: 64 ports (except fip dedicated pins) l minimum instruction execution time: 0.67 m s (when operated at 6.0 mhz) l instruction execution time varying function to achieve a wide range of power supply voltages l built-in programmable fip controller/driver ? number of segments: 9 to 24 ? number of digits: 9 to 16 l 8-bit a/d converter: 8 channels l powerful timer/counter function: 5 channels l 8-bit serial interface: 2 channels l interrupt function with importance attached to appli- cations l product with built-in prom: m pd75p238 ordering information ordering code package quality grade m pD75237GJ- -5bg 94-pin plastic qfp (20 20 mm) standard please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
2 m pd75237 item built-in memory capacity i/o line except fip dedicated pins instruction cycle fluorescent display tube (fip) controller/driver timer/counter interrupt mask option operating temperature range operating voltage package list of m pd75237 functions ( ) function rom: 24448 8 bits, ram: 1024 4bits l l input pin : 16 64 lines l l input/output pin : 24 l l output pin : 24 l l 0.67 m s/1.33 m s/2.67 m s/10.7 m s (when operated at 6.0 mhz) l l 0.95 m s/1.91 m s/3.82 m s/15.3 m s (when operated at 4.19 mhz) l l 122 m s (when operated at 32.768 khz) l l number of segments : 9 to 24 l l number of digits : 9 to 16 l l dimmer function : 8 levels l l pull-down resistor mask option l l key scan interrupt generation enabled l l basic interval timer : watchdog timer applicable l l timer/event counter 5 channels l l watch timer : buzzer output enabled l l timer/pulse generator : 14-bit pwm output enabled l l event counter l l sbi/3-wire type l l 3-wire type l l multi-interrupt enabled by hardware l l both-edge detection l l external interrupt: 3 interrupts l l detected edge programmable (with noise remove function) l l detected edge programmable l l external test input: 1 input l l rising edge detection l l timer/pulse generator l l timer/event counter l l internal interrupt: 5 interrupts l l basic interval timer l l serial interface #0 l l key scan interrupt l l internal test input: 2 inputs l l clock timer l l serial interface #1 l l main system clock : 6.0 mhz, 4.19 mhz l l subsystem clock : 32.768 khz standard l l high withstand voltage port : pull-down resistor or open-drain output l l ports 4 and 5 : pull-up resistors l l port 7 : pull-down resistor C40 to +85 c 2.7 to 6.0 v (standby data hold: 2.0 to 6.0 v) 94-pin plastic qfp (20 20 mm) system clock oscillator 2 channels serial interface
3 m pd75237 an0 av ref av dd v dd v dd x2 x1 ic xt2 xt1 v ss s16/p100 s17/p101 s18/p102 s19/p103 s20/p110 s21/p111 s22/p112 s23/p113 s0/p120 s1/p121 s2/p122 s3/p123 s4/p130 s5/p131 s6/p132 s7/p133 s8/p140 s9/p141 v load t15/s10/p142 t14/s11/p143 ph0/t13/s12/p150 ph1/t12/s13/p151 ph2/t11/s14/p152 t9 ph3/t10/s15/p153 t8 t7 t6 t5 t4 t3 t2 t1 t0 v dd v dd p83/si1 p82/so1 p81/sck1 p80/ppo p73 p72 p71 p70 p63 p62 p61 p60 p53 p52 p51 p50 v ss p43 p42 p41 p40 p33 p32 p31 p30 p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si0/sb1 p02/so0/sb0 p01/sck0 p00/int4 reset an7/p93 an6/p92 an5/p91 an4/p90 an3 an2 an1 av ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 pin configuration note be sure to supply power to av dd , v dd , v ss and av ss pins (pin nos. 3, 4, 5, 11, 30, 48, 65 and 87) . remarks connect the ic (internally connected) pin to gnd. m pD75237GJ- -5bg
4 m pd75237 block diagram * port4 and port5 are 10 v middle-high voltage n-ch open-drain input/output ports. port0 port1 port2 port3 port4 port5 port6 port7 port8 port9 4 4 4 4 4 4 4 4 4 4 p00-p03 p90-p93 p10-p13 p20-p23 p30-p33 p40-p43 * p50-p53 * p60-p63 p70-p73 p80-p83 fip controller/ driver 10 4 2 8 10 t0-t9 t10/s15/ph3/p153- t13/s12/ph0/p150 t14/s11/p143- t15/s10/p142 s0/p120-s9/p141 s16/p100-s23/p113 v load p100-p153 port10-15 24 basic interval timer intbt timer/event counter #0 watch timer intt0 intw timer/pulse generator inttpg serial interface0 intcsi serial interface1 interrupt control counter event a/d converter bit seq. buffer(16) ti0 ti0/p13 pto0/p20 buz/p23 ppo/p80 si0/sb1/p03 so0/sb0/p02 sck0/p01 si1/p83 so1/p82 sck1/p81 int0/p10 int1/p11 int2/p12 int4/p00 ti0 8 an0-an3 an4/p90-an7/p93 av dd av ref av ss program counter (15) alu cy sp (8) sbs (2) bank general reg. ram data memory 1024x4 decode and control rom program memory 24448x8 cpu clock stand by control clock generator sub main clock divider xt1 xt2 x1 x2 clock output control pcl/p22 v dd v ss v dd reset fx/ n 2 f
5 m pd75237 contents 1. pin functions ......................................................................................................................................... 7 1.1 port pins ........................................................................................................................................................... 7 1.2 non-port pins .................................................................................................................................................. 9 1.3 pin input/ouput circuit list ................................................................................................................... 11 1.4 recommended connections of m pd75237 unused pins ............................................................... 15 2. m pd75237 architecture and memory map ................................................................................ 16 2.1 data memory bank configuration and addressing mode ..................................................... 16 2.2 general register bank configuration ............................................................................................ 19 2.3 memory mapped i/o .................................................................................................................................... 22 3. internal cpu functions .................................................................................................................. 28 3.1 program counter (pc): 15 bits .............................................................................................................. 28 3.2 program memory (rom): 24448 words 8 bits ............................................................................... 28 3.3 data memory ................................................................................................................................................ 30 3.4 general register: 8 4 bits 4 banks ............................................................................................... 32 3.5 accumulator ............................................................................................................................................... 33 3.6 stack pointer (sp) and stack bank select register (sbs) ....................................................... 33 3.7 program status word (psw): 8 bits ................................................................................................... 36 3.8 bank select register (bs) ....................................................................................................................... 40 4. peripheral hardware functions ............................................................................................... 41 4.1 digital input/output ports ................................................................................................................... 41 4.2 clock generator ........................................................................................................................................ 50 4.3 clock output circuit ................................................................................................................................ 58 4.4 basic interval timer ................................................................................................................................. 61 4.5 timer/event counter ................................................................................................................................ 63 4.6 watch timer .................................................................................................................................................. 69 4.7 timer/pulse generator ........................................................................................................................... 71 4.8 event counter ............................................................................................................................................. 77 4.9 serial interface .......................................................................................................................................... 79 4.10 a/d converter ........................................................................................................................................... 113 4.11 bit sequential buffer: 16 bits ............................................................................................................. 119 4.12 fip controller/driver ............................................................................................................................ 119 5. interrupt functions ...................................................................................................................... 131 5.1 interrupt control circuit configuration ................................................................................... 131 5.2 interrupt control circuit hardware devices ........................................................................... 133 5.3 interrupt sequence ................................................................................................................................ 138 5.4 multi-interrupt service control ..................................................................................................... 139 5.5 vector address sharing interrupt servicing ........................................................................... 141 6. standby functions ......................................................................................................................... 142 6.1 standby mode setting and operating state .............................................................................. 142 6.2 standby mode release .......................................................................................................................... 144 6.3 operation after standby mode release ....................................................................................... 146
6 m pd75237 h 7. reset functions ............................................................................................................................... 147 8. instruction set ................................................................................................................................ 150 8.1 characteristic instructions of m pd75237 ..................................................................................... 150 8.2 instruction set and operation ......................................................................................................... 153 8.3 operation codes ....................................................................................................................................... 162 9. mask option selection ................................................................................................................. 168 10. application block diagram ........................................................................................................ 169 11. electrical specifications ........................................................................................................... 170 12. characteristic curves (reference values) ........................................................................ 183 13. package information ................................................................................................................... 185 14. recommeded soldering conditions ....................................................................................... 186 appendix a. list of m pd75238 series product functions ..................................................... 187 appendix b. development tools ................................................................................................... 188
7 m pd75237 1. pin functions 1.1 port pins (1/2) p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 p31 p32 p33 p40 to p43 p50 to p53 p60 p61 p62 p63 p70 p71 p72 p73 pin name i/o after reset input/ output *2 4-bit input port (port0). built-in pull-up resistor can be specified in 3-bit units by software for p01 to p03. 4-bit input port (port1). built-in pull-up resistor can be specified in 4-bit units by software. noise removing function available 4-bit input/ output port (port2). built-in pull-up resistor can be specified in 4-bit units by software. b f C a f C b m C c b C c e C b input input input input input input/ output programmable 4-bit input/ output port (port3). input/ output specifiable in 1-bit units. built-in pull-up resistor can be specified in 4-bit units by software. input/ output input/ output n-ch open-drain 4-bit input/output port (port4). pull-up resistor can be incorporated in 1-bit units (mask option). 10 v withstand voltage with open drain. n-ch open-drain 4-bit input/ output port (port5). pull-up resistor can be incorporated in 1-bit units (mask option). 10 v withstand voltage with open drain. l l input e C c m m function dual- function pin *2 *2 *2 *2 *2 l l input/ output input/ output 4-bit input/output port (port7). built-in pull-down resistor can be incorporated in 1-bit units (mask option). int4 sck0 so0/sb0 si0/sb1 int0 int1 int2 ti0 pto0 pcl buz input v ss level (when a pull- down resistor is incorpo- rated) or high impedance e C c v programmable 4-bit input/output port (port6). input/output specifiable in 1-bit units. built -in pull-up resistor can be specified in 4-bit units by software. input / output circuit type *1 8-bit i/o *1. schmitt trigger inputs are circled. 2. can drive led directly. high level (when a pull- up resistor is incorporated) or high im- pedance high level (when a pull- up resistor is incorporated) or high im- pedance
8 m pd75237 pin name i/o function dual- function pin after reset input/ output input/ output input/ output 4-bit input port (port9). p-ch open-drain 4-bit high-voltage output port. pull-down resistor can be incorporated (mask op- tion). p-ch open-drain 4-bit high-voltage output port. pull-down resistor can be incorporated (mask op- tion). a f e b input y C a l l i C f p-ch open-drain 4-bit high-voltage output port. pull-down resistor can be incorporated (mask op- tion). p-ch open-drain 4-bit high-voltage output port. pull-down resistor can be incorporated (mask op- tion). l l p80 p81 p82 p83 p90 p91 p92 p93 p100 p101 p102 p103 p110 p111 p112 p113 p120 p121 p122 p123 p130 p131 p132 p133 p140 p141 p142 p143 p150 p151 p152 p153 ph0 ph1 ph2 ph3 p-ch open-drain 4-bit high-voltage output port. pull-down resistor can be incorporated (mask op- tion). p142 and p143 can drive led directly. input ppo sck1 so1 si1 an4 an5 an6 an7 s16 s17 s18 s19 s20 s21 s22 s23 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10/t15 s11/t14 s12/t13/ph0 s13/t12/ph1 s14/t11/ph2 s15/t10/ph3 s12/t13/p150 s13/t12/p151 s14/t11/p152 s15/t10/p153 input output output output output output output output p-ch open-drain 4-bit high-voltage output port. pull-down resistor can be incorporated (mask op- tion). l l 1.1 port pins (2/2) * schmitt trigger inputs are circled. v load level (when a pull- down resistor to v load is in- corporated) or high imped- ance i C c p-ch open-drain 4-bit high-voltage output port. pull-down resistor can be incorporated (mask op- tion). these ports can drive led directly. input / output circuit type * 4-bit input port (port8). input v load level (when a pull- down resistor to v load is in- corporated), v ss level (when a pull- down resistor to v ss is incor- porated) or high imped- ance 8-bit i/o
9 m pd75237 1.2 non-port pins (1/2) pin name i/o dual- function pin input / output circuit type * t0 to t9 t10/s15 to t13/s12 t14/s11 t15/s10 s0 to s3 s4 to s7 s8 s9 s16 to s19 s20 to s23 ti0 pto0 pcl buz sck0 so0/sb0 si0/sb1 after reset output i C c i C f v load level (when a pull-down resistor to v load is in- corpo- rated), v ss level (when a pull-down resistor to v ss is incor- porated) or high im- pedance segment high-voltage output pins. these pins can be used as port10 and port11 in the static mode. ph3/p153 to ph0/p150 p143 p142 p120 to p123 p130 to p133 p140 p141 p100 to p103 p110 to p113 p13 p20 p22 p23 p01 p02 p03 fip controller/driver out- put pins. pull-down resistor can be incorporated in bit units (mask option). digit/segment output dual-func- tion high-voltage high-current output pins. extra pins can be used as porth. these pins can be used as port15 in the static mode. digit output high-voltage high- current output pins. digit/segment output dual-func- tion high-voltage high-current output pins. these pins can be used as potr14 in the static mode. clock output. fixed frequency output (for buzzer or system clock trim- ming). input/ output input/ output serial clock input/output. serial data output. serial bus input/output. input/ output serial data input. serial bus input/output. timer/event counter output. output output external event pulse input to timer/event counter #0 and event counter #1. input input input input input input input b C c e C b e C b e C b f C a f C b m C c * schmitt trigger inputs are circled. output segment high-voltage output pins. these pins can be used as port12 to port14 in the static mode. v load level (when a pull-down resistor to v load is in- corpo- rated) or high im- pedance. function
10 m pd75237 1.2 non-port pins (2/2) input edge-detected testable input (rising edge detection). input input/ output output serial data output. b C c input input input input output serial data input. input analog input to a/d converter. a/d converter power supply. a/d converter reference voltage input. a/d converter reference gnd potential. subsystem clock oscillation crystal connection. an exter- nal clock is input to xt1 and xt2 is made open. system reset input. timer/pulse generator pulse output. gnd potential. positive power supply. fip controller/driver pull-down resistor connect/power supply. input dual- function pin pin name i/o after reset input / output circuit type * * schmitt trigger inputs are circled. edge-detected vectored interrupt input (valid for detec- tion of rising and falling edges). clocked asynchronous asynchronous serial clock input/output. main system clock oscillation crystal/ceramic connec- tion. an external clock is input to x1 and an antiphase clock is input to x2. function int4 int0 int1 int2 sck1 so1 si1 an0 to an3 an4 to an7 av dd av ref av ss x1, x2 xt1 xt2 reset ppo v dd (3 C pin) v ss (2 C pin) v load p00 p10 p11 p12 p81 p82 p83 p90 to p93 p80 input edge-detected vectored interrupt in- put (detected edge selection possible). input input input input b b C c f e b y y C a z b
11 m pd75237 1.3 pin input/output circuit list (1/4) in v dd p-ch n-ch cmos-specified input buffer in v dd p-ch p.u.r in p.u.r enable p.u.r:pull-up resistor schmitt trigger input having hysteresis char- acteristics push-pull output which can be set to output high impedance (with both p-ch and n-ch set to off) data output disable type d in/out type a schmitt trigger input having hysteresis characteristics input/output circuit consisting of type d push-pull output and type a input buffer type d type b-c type e-b type a v dd p-ch n-ch out data output disable type b type e output disable data output disable type d type a v dd p-ch p.u.r in/out p.u.r:pull-up resistor
12 m pd75237 type f-b type e-c input/output circuit consisting of type d push-pull output and type b schmitt trig- ger input type f-c type f p.u.r enable data output disable type d type a v dd p.u.r p-ch in/out p.u.r:pull-up resistor data output disable type d in/out type b output disable (p-ch) data output disable output disable (n-ch) p.u.r enable v dd p-ch n-ch type b in/out p-ch p.u.r v dd p.u.r:pull-up resistor p.u.r enable data output disable type d type b in/out p-ch p.u.r v dd p.u.r:pull-up resistor 1.3 pin input/output circuit list (2/4) p.u.r enable data output disable type d type b in/out p-ch p.u.r v dd p.u.r:pull-up resistor data v dd p-ch n-ch v dd p-ch out p.d.r (mask option) v load p.d.r:pull-down resistor type f-a type i-c
13 m pd75237 type y middle-high voltage input buffer v dd p.u.r p-ch in/out n-ch p.u.r enable data output disabie type b p.u.r:pull-up resistor reference voltage (from the series resistance string voltage tap) 1.3 pin input/output circuit list (3/4) data output disable v dd p.u.r (mask option) in/out n-ch p.u.r:pull-up resistor data v dd p-ch n-ch v dd p-ch p.d.r (mask option) out v load p.d.r:pull-down resistor data output disable type d type a in/out p.d.r (mask option) p.d.r:pull-down resistor in av dd av ss p-ch n-ch av ss av ss av dd sampling c reference voltage (from the series resistance string voltage tap) type y-a type m-c type m type i-f type v in av dd av ss p-ch n-ch av ss av dd av ss sampling c
14 m pd75237 1.3 pin input/output circuit list (4/4) av type z ss
15 m pd75237 1.4 recommended connections of m pd75237 unused pins p00/int4 p01/sck0 p02/so0/sb0 p03/si1/sb1 p10/int0 to p12/int2 p13/ti0 p20/pto0 p21 p22/pcl p23/buz p30 to p33 p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80/ppo p81/sck1 p82/so1 p83/si1 p90/an4 to p93/an7 p100/s16 to p103/s19 p110/s20 to p113/s23 p120 to p123 p130 to p133 p140 to p143 p150 to p153 an0 to an3 av ref av dd av ss xt1 xt2 v load pin connect to v ss connect to v ss or v dd input state : connect to v ss or v dd ouput state : leave open connect to v ss connect to v dd connect to v ss connect to v ss or v dd leave open connect to v ss recommended connection connect to v ss leave open connect to v ss
16 m pd75237 2. m pd75237 architecture and memory map the m pd75237 has the following three architectural features. (a) data memory bank configuration (b) general register bank configuration (c) memory mapped i/o each feature is outlined below. 2.1 data memory bank configuration and addressing mode as shown in fig. 2-1, the m pd75237 incorporates a static ram (928 words 4 bits) at addresses 000h to 19fh and 200h to 3ffh in the data memory space and a display data memory (96 words 4 bits) at addresses 1a0h to 1ffh and peripheral hardware (input/output ports, timers, etc.) at addresses f80h to fffh. for addressing of this 12-bit address data memory space, the memory bank has a configuration wherein the lower 8 bits are directly or indirectly specified by an instruction and the higher 4-bit address is specified by a memory bank (mb). a memory bank enable flag (mbe) and a memory bank select register (mbs) are incorporated to specify the memory bank (mb) and addressing operations shown in fig. 2-1 and table 2-1 can be carried out. (mbs is a register to select the memory bank and can set 0, 1, 2, 3 and 15. mbe is a flag to determine whether the memory bank selected by mbs should be validated or not. since mbe is automatically saved/reset for interrupt or subroutine processing, it can be freely set for either processing.) for data memory space addressing, set mbe = 1 normally and manipulate the memory bank static ram specified by mbs. efficient programming is possible by using the mbe = 0 or mbe = 1 mode for each program processing. applicable program processing interrupt service mbe = 0 mode processing of repeating built-in hardware manipulation and static ram manipulation subroutine processing mbe = 1 mode normal program processing
17 m pd75237 fig. 2-1 date memory configuration and addressing range in each addressing mode addressing mode mem mem. bit @hl @h+mem. bit @de @dl pmem. @l remarks : dont care stack address- ing fmem. bit general register area 01fh 020h 000h 07fh data area static ram (memory bank 1) 0ffh 100h display data memory area stack area 19fh 1a0h 1ffh 200h data area static ram (memory bank 2) 3ffh data area static ram (memory bank 3) 2ffh 300h fffh fc0h f80h peripheral hardware area (memory bank 15) not incorporated memory bank enable flag mbe = 0 mbe = 1 mbe = 0 mbe = 1 data area static ram (memory bank 0) mbs = 0 mbs = 0 sbs = 0 mbs = 1 mbs = 1 sbs = 1 mbs = 2 mbs = 2 sbs = 2 mbs = 3 sbs = 3 mbs = 3 mbs = 15 mbs = 15
18 m pd75237 table 2-1 addressing modes addressing mode identifier address specified mbe = 0 bit indicated by bit of address indicated by mb and mem, where: when mem = 00h to 7fh, mb = 0 when mem = 80h to ffh, mb = 15 mbe = 1 mb = mbs address indicated by mb and mem, where : when mem = 00h to 7fh, mb = 0 when mem = 80h to ffh, mb = 15 mbe = 1 mb = mbs address indicated by mb and mem (mem is an even address), where: when mem = 00h to 7fh, mb = 0 when mem = 80h to ffh, mb = 15 mbe = 1 mb = mbs address indicated by mb and hl, where : mb = mbe? mbs address indicated by mb and hl, where : mb = mbe? mbs hl+ automatically increments l register after addressing. hlC automatically decrements l register after addressing. address indicated by de of memory bank 0 address indicated by dl of memory bank 0 address indicated by mb and hl, where : mb = mbe? mbs bit 0 of l register is ignored. bit indicated by bit of address indicated by fmem, where: fb0h to fbfh (interrupt-related hardware) ff0h to fffh (i/o port) bit indicated by the lower 2 bits of l register of the address indicated by the higher 10 bits of pmem and the higher 2 bits of l register, where: pmem = fc0h to fffh bit indicated by bit of the address indicated by mb, h and the lower 4 bits of mem, where: mb = mbe? mbs address indicated by sp of memory banks 0, 1, 2 and 3 selected by sbs mem.bit mem @hl @hl+ @hlC @de @dl @hl fmem.bit pmem.@l @h + mem.bit 1-bit direct addressing 4-bit direct addressing 8-bit direct addressing 4-bit register indirect addressing 8-bit register indirect addressing bit manipulation addressing stack addressing as described in table 2-1, direct and indirect addressing is possible for each of 1-bit, 4-bit and 8-bit data in m pd75237 data memory manipulation. thus, easy-to-understand programs can be created very efficiently. mbe = 0 mbe = 0 fmem =
19 m pd75237 2.2 general register bank configuration the m pd75237 incorporates four register banks, each bank consisting of eight general registers, x, a, b, c, d, e, h and l. this general register area is mapped at addresses 00h to 1fh of the memory bank 0 of the data memory (refer to fig. 2-2 general register configuration (4-bit processing) ). a register bank enable flag (rbe) and a register bank select register (rbs) are incorporated to specify the above general register banks. rbs is a register to select a register bank and rbe is a flag to determine whether the register bank selected by rbs should be validated or not. the register bank (rb) which is validated for instruction execution is given as rb = rbe? rbs. as described above, with the m pd75237 having four register banks, programs can be created very efficiently by using different register banks for normal processing and interrupt service as described in table 2-2. (rbe is automatically saved and set for interrupt service and automatically reset upon termination of the interrupt service.) table 2-2 recommended use of register banks in normal and interrupt routines normal processing use register banks 2 and 3 with rbe = 1. single interrupt service use register bank 0 with rbe = 0. double interrupt service use register bank 1 with rbe = 1. (it is necessary to save/reset rbs.) triple or more interrupt service save/reset registers by push and pop. not only in 4-bit units, a register pair of xa, hl, de or bc can transfer, compare, operate, increment or decrement data in 8-bit units. in this case, register pairs with the reversed bit 0 of the register bank specified by rbe?rbs can be specified as xa, hl, de and bc. thus, the m pd75237 has eight 8-bit registers (refer to fig. 2-3 general register configuration (8-bit processing) ).
20 m pd75237 fig. 2-2 general register configuration (4-bit processing) x a h l d e b c x a h l d e b c x a h l d e b c x a h l d e b c 01h 00h 03h 02h 05h 04h 07h 06h 09h 08h 0bh 0ah 0dh 0ch 0fh 0eh 11h 10h 13h 12h 15h 14h 17h 16h 19h 18h 1bh 1ah 1dh 1ch 1fh 1eh register bank 0 (rbe?bs = 0) register bank 1 (rbe?bs = 1) register bank 2 (rbe?bs = 2) register bank 3 (rbe?bs = 3)
21 m pd75237 fig. 2-3 general register configuration (8-bit processing) xa hl de bc xa' hl' de' bc' 00h 02h 04h 06h 08h 0ah 0ch 0eh when rbe?bs = 0 xa' hl' de' bc' xa hl de bc 00h 02h 04h 06h 08h 0ah 0ch 0eh when rbe?bs = 1 xa hl de bc xa' hl' de' bc' 10h 12h 14h 16h 18h 1ah 1ch 1eh when rbe?bs = 2 xa' hl' de' bc' xa hl de bc 10h 12h 14h 16h 18h 1ah 1ch 1eh when rbe?bs = 3
22 m pd75237 2.3 memory mapped i/o as shown in fig. 2-1, the m pd75237 employs the memory mapped i/o with the peripheral hardware including input/output ports and timers mapped at addresses f80h to fffh in the data memory space. thus, there are no special instructions to control the peripheral hardware and all operations are controlled by memory manipulation instructions. (some hardware control mnemonics are available to make the program easy to understand.) when operating the peripheral hardware, the addressing modes listed in table 2-3 can be used. manipulate the display data memory, key scan register and port h mapped at addresses 1a0h to 1ffh by specifying memory bank 1. table 2-3 addressing modes applicable when operating the peripheral hardware at addresses f80h to fffh applicable addressing mode specify by direct addressing mem.bit with mbe = 0 or (mbe = 1, mbs = 15) specify by direct addressing fmem.bit irrespective of mbe and mbs specify by indirect addressing pmem.@l irrespective of mbe and mbs specify by direct addressing mem with mbe = 0 or (mbe = 1, mbs = 15) specify by register indirect addressing @hl with (mbe = 1, mbs = 15) specify by direct addressing mem with mbe = 0 or (mbe = 1, mbs = 15) (mem is an even address.) specify by register indirect addressing @hl with mbe = 1 and mbs = 15 (l register contents are even.) applicable hardware all hardware devices enabled for bit manipulation ist0, ist1, mbe, rbe, ie , irq , portn. 0 to 3 portn. all hardware devices enabled for 4-bit manipulation all hardware devices enabled for 8-bit manipulation bit manipulation 4-bit manipulation 8-bit manipulation table 2-4 shows the m pd75237 i/o map. in the table, each item has the following meanings: ? symbol ............. name indicating the on-chip hardware address. can be described in the instruction operand column. ? r/w ................... indicates whether the corresponding hardware is enabled for read/write. r/w : read/write enable r : read only w : write only ? no. of manipulatable bits ........ indicates the number of applicable bits before operating the correspond- ing hardware. ? bit manipulated addressing .... indicates the applicable bit manipulated addressing before operating the applicable hardware.
23 m pd75237 table 2-4 m pd75237 i/o map (1/5) address r/w no. of manipulatable bits 1 bit 4 bits 8 bits remarks f80h f82h f83h f84h f85h f86h f88h f89h f8ah stack pointer (sp) register bank select register (rbs) memory bank select register (mbs) stack bank select register (sbs) basic interval timer mode register (btm) basic interval timer (bt) display mode register (dspm) dimmer select register (dims) ksf digit select register (digs) r/w r *1 r/w w r w w r/w hardware name (symbol) b3 b2 b1 b0 be sure to write 0 to bit 0. *2 be sure to write 0 to bits 3 and 2. only bit 3 is bit-manipula- table. only bit 3 is bit- testable. s s s s l l l l l l l l l l l l l l bit manipulated addressing l l l l l l mem.bit mem.bit f90h f94h f96h f98h timer pulse generator mode register (tpgm) timer pulse generator modulo register l (modl) timer pulse generator modulo register h (modh) watch mode register (wm) w r/w r/w w s s s s l l l l l l l l mem.bit h only bit 3 is bit-manipu- latable. *1. can be read/written by the sel instruction. 2. individually manipulatable as rbs and mbs by 4-bit manipulation. manipulatable as bs by 8-bit manipulation.
24 m pd75237 table 2-4 m pd75237 i/o map (2/5) address r/w no. of manipulatable bits 1 bit 4 bits 8 bits remarks fa0h fa2h fa4h fa6h fa8h fabh fach hardware name (symbol) b3 b2 b1 b0 bit manipulated addressing l l l l l l l l l l timer/event counter 0 mode register (tm0) toe0 timer/event counter 0 count register (t0) timer/event counter 0 modulo register (tmod0) event counter mode register (tm1) gate control register (gatec) counter register (t1) w w r w w w r s s l l s s l l only bit 3 is bit-manipulatable. only bit 3 is bit-manipulatable.
25 m pd75237 table 2-4 m pd75237 i/o map (3/5) address r/w no. of manipulatable bits 1 bit 4 bits 8 bits remarks hardware name (symbol) b3 b2 b1 b0 ist1 ist0 mbe rbe bit manipulated addressing fb0h fb2h fb3h fb4h fb5h fb7h fb8h fb9h fbah fbbh fbch fbdh fbeh fbfh program status word (psw) interrupt priority select register (ips) processor clock control register (pcc) int0 mode register (im0) int1 mode register (im1) system clock control register (scc) ie4 irq4 iebt irqbt eot iew irqw ieks irqks ietpg irqtpg irqt1 iet0 irqt0 iecsi0 irqcsi0 ie1 irq1 ie0 irq0 ie2 irq2 r/w w w w w w r/w r/w r/w r/w r/w r/w r/w r/w l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l fmem.bit be sure to write 0 to bit 2. be sure to write 0 to bits 3, 2 and 1. only bits 3 and 0 are bit-manipulatable. fmem.bit fc0h fc1h fc2h fc3h fc8h fc9h fcch bit sequential buffer 0 (bsb0) bit sequential buffer 1 (bsb1) bit sequential buffer 2 (bsb2) bit sequential buffer 3 (bsb3) csim11 csim10 csie1 serial i/o shift register (sio1) r/w r/w r/w r/w w w r/w l l l l l l l l l l l l l l l l l l l l l l l l l l h h h
26 m pd75237 table 2-4 m pd75237 i/o map (4/5) address r/w no. of manipulatable bits 1 bit 4 bits 8 bits remarks hardware name (symbol) b3 b2 b1 b0 bit manipulated addressing fd0h fd4h fd6h fd8h fdah fdch clock output mode register (clom) static mode register b (statb) static mode register a (stata) soc eoc a/d conversion mode register (adm) sa register (sa) pull-up register specification reg- ister group a (poga) w w w r/w r w s s l l l l l l l l l l l l l l l l l l l l l l w r/w r/w r/w w w w l l l l write only in 8-bit ma- nipulation mem.bit write only in 8-bit ma- nipulation l l h port mode register group a (pmga) serial operating mode register (csim0) csie0 coi wup cmdd reld cmdt relt sbi control register (sbic) bsye ackd acke ackt serial i/o shift register 0 (sio0) slave address register (sva) pm33 pm32 pm31 pm30 fe0h fe2h fe4h fe6h fe8h fech pm63 pm62 pm61 pm60 pm2 port mode register group b (pmgb) pm7 pm5 pm4 mem.bit
27 m pd75237 table 2-4 m pd75237 i/o map (5/5) address r/w no. of manipulatable bits 1 bit 4 bits 8 bits remarks hardware name (symbol) b3 b2 b1 b0 bit manipulated addressing ff0h port 0 (port0) r l l l l ff1h port 1 (port1) r l l l l ff2h port 2 (port2) r/w l l l l ff3h port 3 (port3) r/w l l l l ff4h port 4 (port4) r/w l l l l ff5h port 5 (port5) r/w l l l l ff6h port 6 (port6) r/w l l l l ff7h port 7 (port7) r/w l l l l ff8h port 8 (port8) r l l l l ff9h port 9 (port9) r l l l l ffah port 10 (port10) w l l l l ffbh port 11 (port11) w l l l l ffch port 12 (port12) w l l l l ffdh port 13 (port13) w l l l l ffeh port 14 (port14) w l l l l fffh port 15 (port15) w l l l l l l l l l l l l l l 1a0h+4n 1a1h+4n 1beh 1bfh 1c0h+4n 1c1h+4n 1c2h+4n 1c3h+4n 1fch 1fdh 1feh 1ffh l l l l l l l l l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l r/w l l l l display data memory: s16 to s23 (n = 0 to 15) key scan register (ks2) display data memory: s0 to s7 (n = 0 to 15) display data memory: s8 to s15 (n = 0 to 15) key scan register (ks0) key scan register (ks1) port h (porth) fmem.bit pmem.@l mem.bit
28 m pd75237 3. internal cpu functions 3.1 program counter (pc): 15 bits this is a 15-bit binary counter to hold the program memory address information. fig. 3-1 program counter configuration when reset is input, the lower 6 bits at address 0000h and the contents at address 0001h of the program memory are set to pc13 to pc8 and pc7 to pc0, respectively, and the pc is initialized. the reset start address should therefore be located in the 16k space (0000h to 3fffh). 3.2 program memory (rom): 24448 words 8 bits this is a mask programmable rom having a configuration of 24448 words 8 bits to store programs, table data, etc. the program memory is addressed by the program counter. table data can be referred to by the table reference instruction (movt). the branch range enabled by the branch and subroutine call instructions is shown in fig. 3-2. the entire space branch instruction (bra !addr1) and the entire space call instruction (calla !addr1) allow direct branching to the entire space from 0000h to 5f7fh. the relative branch instruction (br $addr) enables branch to the [pc contents C15 to C1, +2 to +16] address irrespective of the block boundary. the program memory addresses are 0000h to 5f7fh and the following addresses are especially assigned. (all areas except 0000h and 0001h can be used as the normal program memory.) ? addresses 0000 and 0001h vector address table for writing the program start address to be set upon reset input and the rbe and mbe set values. can be reset and started at any address in a 16k space (0000h to 3fffh). ? addresses 0002 to 000fh vector address table for writing the program start address to be set by each vectored interrupt and the rbe and mbe set values. interrupt service can be started at any address in a 16k space (0000h to 3fffh). ? addresses 0020 to 007fh table area to be referred to by geti instruction * . * geti instruction is an instruction to realize any 2-byte/3-byte instruction or two 1-byte instructions with one byte. it is used to decrease the number of program bytes. (refer to 8.1 characteristic instructions of m pd75237 .) pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0
29 m pd75237 fig. 3-2 program memory map note as stated above, the interrupt vector start address is 14 bits in length, and should therefore be set in the 16k space (0000h to 3fffh). remarks in all cases other than those listed above, branch to the address with only the lower 8 bits of the pc changed is enabled by br pcde and br pcxa instructions. mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe intbt/int4 start address internal reset start address (most significant 6 bits)? (least significant 8 bits)? (most significant 6 bits) (least significant 8 bits) int0 start address (most significant 6 bits) (least significant 8 bits) intcsi0 start address (most significant 6 bits) (least significant 8 bits) intt0 start address (most significant 6 bits) (least significant 8 bits) inttpg start address (most significant 6 bits) (least significant 8 bits) intks start address (most significant 6 bits) (least significant 8 bits) (most significant 6 bits) (least significant 8 bits) int1 start address geti instruction reference table 0002h 0004h 0006h 0008h 000ah 000ch 000eh 0000h 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 5f7fh callf !faddr instruction entry address brcb !caddr instruction branch address br !addr instruction branch address call !addr instruction branch address branch/call address by geti brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address bra !addr1 instruction branch address calla !addr1 instruction branch address br $addr1 instruction relative branch address (-15 to -1 and +2 to +16) 3fffh 4000h 4fffh 5000h brcb !caddr instruction branch address brcb !caddr instruction branch address
30 m pd75237 3.3 data memory the data memory consists of a static ram and peripheral hardware. the static ram incorporates 160 words 4 bits of memory banks 0, 2 and 3, 768 words 4 bits of memory bank 1 and 96 words 4 bits of memory bank 1 which also serves as a display data memory. it is used to store process data and to serve as a stack memory for interrupt execution. general registers, display data memory and various registers of peripheral hardware are mapped at particular addresses of the data memory and such data is manipulated by the general register and memory manipulation instructions. (refer to fig. 2-1 data memory configuration and addressing range in each addressing mode .) all addresses (000h to 3ffh) of memory banks 0, 1, 2 and 3 can be used as a stack area. although the data memory consists of one address and 4 bits, it can be manipulated in 8-bit units by the 8-bit memory mainipulation instruction or in bit units by the bit manipulation instruction. specify an even address by the 8-bit manipulation instruction. the display data memory area (1a0h to 1ffh) is made up as shown in fig. 3-4. fig. 3-3 data memory map (32 4) 256 4 256 4 (96 4) 256 4 data memory memory bank 0 1 2 128 4 15 not incorporated f80h fffh peripheral hardware area 3ffh 200h 1ffh 1a0h 19fh 100h 0ffh 020h 000h general register area stack area display data memory, etc. data area static ram (1024 4) 01fh 3 256 4 300h 2ffh
31 m pd75237 fig. 3-4 display data memory configuration 1a1h 1a0h 1c3h 1c2h 1c1h 1c0h 1a3h 1a2h 1c7h 1c6h 1c5h 1c4h 1a5h 1a4h 1cbh 1cah 1c9h 1c8h 1a7h 1a6h 1cfh 1ceh 1cdh 1cch 1a9h 1a8h 1d3h 1d2h 1d1h 1d0h 1abh 1aah 1d7h 1d6h 1d5h 1d4h 1adh 1ach 1dbh 1dah 1d9h 1d8h 1afh 1aeh 1dfh 1deh 1ddh 1dch 1b1h 1b0h 1e3h 1e2h 1e1h 1e0h 1b3h 1b2h 1e7h 1e6h 1e5h 1e4h 1b5h 1b4h 1ebh 1eah 1e9h 1e8h 1b7h 1b6h 1efh 1eeh 1edh 1ech 1b9h 1b8h 1f3h 1f2h 1f1h 1f0h 1bbh 1bah 1f7h 1f6h 1f5h 1f4h 1bdh 1bch 1fbh 1fah 1f9h 1f8h 1bfh 1beh (ks2) iffh (porth) 1feh (ks1) 1fdh 1fch (ks0) 1 bit 4 bits 8 bits no. of manipulatable bits remarks 1. ks0, ks1 and ks2: key scan register 2. porth: high-voltage, high-current output port which also serves as digit output port
32 m pd75237 3.4 general register: 8 4 bits 4 banks the general registers are mapped at the special addresses of the data memory. there are 4-bank registers, each bank consisting of eight 4-bit registers (b, c, d, e, h, l, x, a). the register bank (rb) which becomes valid for instruction is given as rb = rbe? rbs (rbs = 0 to 3). each general register is operated in 4-bit units. bc, de, hl and xa form register pairs and are used for 8-bit manipulation. in addition to de and hl, dl also makes up a pair and these three pairs can be used as a data pointer. the general register area can be accessed by address specification as a normal ram whether or not it is used as a register. fig. 3-5 general register configuraton fig. 3-6 register pair configuration a register x register l register h register e register d register c register b register 000h 001h 002h 003h 004h 005h 006h 007h same configuration as bank 0 same configuration as bank 0 same configuration as bank 0 008h ......... 00fh 010h ......... 017h 018h ......... 01fh 3 data memory 0 register bank 0 register bank 1 register bank 2 register bank 3 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 b d h x c e l a 1 bank address
33 m pd75237 3.5 accumulator in the m pd75237, a register and xa register pair function as an accumulator. the 4-bit data processing instruction is executed mainly by a register and the 8-bit data processing instruction is executed mainly by xa register pair. for execution of the bit manipulation instruction, the carry flag (cy) functions as a bit accumulator. fig. 3-7 accumulator 3.6 stack pointer (sp) and stack bank select register (sbs) in the m pd75237, the static ram is used as a static memory (lifo type) and the 8-bit register which holds the start address information in the stack area is a stack pointer (sp). the stack area is located at addresses 000h to 3ffh of memory banks 0, 1, 2 and 3. specify one memory bank by a 4-bit sbs. the sp is decremented prior to a write (save) to the stack memory and incremented after a read (restore) from the stack memory. set sbs by the 4-bit memory manipulation instruction. in this case, set the higher 2-bits to 00. the data to be saved/restored by each stack operation is shown in figs. 3-9 and 3-10. the sp initial value is set by the 8-bit memory manipulation instruction and the sbs initial value is set by the 4-bit memory manipulation instruction and then the stack area is determined. the sp and sbs contents can also be read. table 3-1 stack areas to be selected by sbs when the sp initial value is set to 00h, stack starts with the most significant address (nffh) of the memory bank (n: n = 0, 1, 2, 3) specified by sbs. the stack area is limited to the memory bank specified by sbs. when stack operation is further carried out at address n00h, the address is reset to nffh in the same bank. linear stack past the memory bank boundary is not possible without rewriting sbs. since reset input makes the sp and sbs undefined, be sure to initialize the sp and sbs to any desired value at the beginning of the program. sbs sbs1 sbs0 0 0 memory bank 0 0 1 memory bank 1 1 0 memory bank 2 1 1 memory bank 3 stack area ------------------------------- cy bit accumulator a 4-bit accumulator xa 8-bit accumulator
34 m pd75237 sp sp sp sp7 sp6 sp5 sp4 sp3 sp2 sp1 sbs1 sbs0 f80h f84h sbs 000h 0ffh 100h 200h 2ffh 1ffh sp sbs memory bank 0 memory bank 1 memory bank 2 symbol address fixed to 0 sp memory bank 3 300h 3ffh fig. 3-8 stack bank select register configuration
35 m pd75237 fig. 3-9 data to be saved into stack memory fig. 3-10 data to be restored from stack memory * psw except mbe and rbe are not saved/restored. remarks * means undefined. psw stack lower half of register pair upper half of register pair sp - 2 sp - 1 sp sp - 6 sp - 5 stack pc11-pc8 0 pc14 pc13 pc12 pc3-pc0 pc7-pc4 * * mbe rbe * * * * sp - 4 sp - 3 sp - 2 sp - 1 sp stack pc11-pc8 0 pc14 pc13 pc12 pc3-pc0 pc7-pc4 ist1 ist0 mbe rbe cy sk2 sk1 sk0 psw lower half of register pair upper half of register pair stack sp sp + 1 stack pc11-pc8 0 pc14 pc13 pc12 pc3-pc0 pc7-pc4 * * mbe rbe * * * * sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 stack pc11-pc8 0 pc14 pc13 pc12 pc3-pc0 pc7-pc4 ist1 ist0 mbe rbe cy sk2 sk1 sk0 sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 sp - 6 sp - 5 sp - 4 sp - 3 sp - 2 sp - 1 sp push instruction call, calla and callf instructions interrupt pop instruction ret and rets instruction reti instruction * * sp sp + 1 sp + 2
36 m pd75237 3.7 program status word (psw): 8 bits the program status word (psw) consists of various types of flags closely related to processor operation. the psw is mapped at addresses fb0h and fb1h in the data memory space and 4 bits at address fb0h can be operated by the memory manipulation instruction. normal data memory manipulation instructions cannot be used at address fb1h. fig. 3-11 program status word configuration table 3-2 psw flag to be saved/restored in stack operation save restore flag to be saved/restored during call/calla/callf instruction execution mbe and rbe saved upon hardware interruption all psw bits saved during ret/rets instruction execution mbe and rbe restored during reti instruction execution all psw bits restored cy sk2 sk1 sk0 ist1 ist0 mbe rbe fb1h fb0h address symbol psw manipulatable manipulatable by a dedicated instruction non-manipulatable
37 m pd75237 (1) carry flag (cy) the carry flag is a 1-bit flag to store the overflow and underflow generate information when a carry operation instruction (addc, subc) is executed. it has the bit accumulator function to execute boolean algebraic operations with the data memory specified by the bit address and to store the result. carry flag manipulation is carried out using a dedicated instruction irrespective of other psw bits. when reset signal is generated, the carry flag becomes undefined. table 3-3 carry flag manipulation instructions remarks mem * .bit indicates the following three bit manipulated addressing operations. ? fmem.bit ? pmem.@l ? @h + mem.bit (2) skip flags (sk2, sk1, sk0) the skip flag is used to store the skipped state and is automatically set/reset when the cpu executes an instruction. the user cannot directly operate the skip flags as operands. instruction (mnemonic) carry flag operation and processing set1 cy clr1 cy not1 cy skt cy mov1 mem * .bit cy mov1 cy, mem * .bit and1 cy, mem * .bit or1 cy, mem * .bit xor1 cy, mem * .bit during interrupt execution reti cy set (1) cy clear (0) cy contents invert skip if cy contents are 1 cy contents transfer to the specified bit specified bit contents transfer to cy specified bit contents anded/ored/xored with cy contents and the results set to cy parallel save of other psw bits and 8 bits to the stack memory restore from the stack memory in parallel to other psw bits --------------------------------------------------------------------------------------------------------------------------------------------------- carry flag manipu- lation dedicated instruction bit transfer instruction bit boolean instruction interrupt service
38 m pd75237 (3) interrupt status flags (ist1, ist0) the interrupt status flag is a 2-bit flag to store the status of the processing currently being executed. (refer to table 5-3 ist1 and ist0 interrupt servicing statuses for details.) table 3-4 interrupt status flag directive contents the interrupt priority control circuit (see fig. 5-1 interrupt control circuit block diagram ) identifies the interrupt status flag contents and executes multiple interrupt control. if the interrupt is acknowledged, the ist1 and ist0 contents are saved to the stack memory as part of psw and are automatically changed to the status higher by one level and the values prior to interruption by reti instruction are restored. the interrupt status flag can be operated by the memory manipulation instruction and the processing status being executed can be changed by program control. note before operating this flag, be sure to disable interruption by executing di instruction and enable interruption by execution ei instruction after operation. ist1 ist0 00 01 10 11 servicing contents and interrupt control normal program being executed. all interrupts acknowledgeable. low or high interrupt being executed. only high interrupt acknowledgeable. high interrupt being executed. all interrupts non-acknowledgeable. setting disable status of processing being executed status 0 status 1 status 2
39 m pd75237 (4) memory bank enable flag (mbe) this is a 1-bit flag to specify the mode to generate the address information of the most significant 4 bits of the 12 bits of the data memory address. when this flag is set (1), the data memory address space is expanded and all data memory spaces become addressible. when this flag is reset (0), the data memory address space is fixed irrespectively of mbs setting. (see fig. 2-1 data memory configuration and addressing range in each addressing mode .) when reset input is applied, the bit 7 contents at address 0 of the program memory are set and the mbe is automatically initialized. in vectored interrupt service, the bit 7 contents of the corresponding vector address table are set and the mbe status in the interrupt service is automatically set. normally, set mbe = 0 for interrupt service and use the static ram of memory bank 0. (5) register bank enable flag (rbe) this is a 1-bit flag to determine whether or not the general register bank configuration should be expanded. when this flag is set (1), one general register can be selected from register banks 0 to 3 depending on the register bank select register (rbs) contents. when this flag is reset (0), register bank 0 is selected as a general register irrespective of the register bank select register (rbs) contents. upon reset input, the bit 6 contents at address 0 of the program memory are set and the flag is automatically initialized. when a vectored interrupt is generated, the bit 6 contents of the corresponding vector address table are set and the rbe status in interrupt service is automatically set. normally, set rbe = 0 for interrupt service. use register bank 0 for 4-bit operation and register banks 0 and 1 for 8-bit operation.
40 m pd75237 3.8 bank select register (bs) the bank select register (bs) consists of a register bank select register (rbs) and a memory bank select register (mbs). the rbs and mbs are used to specify the register bank and the memory bank to be used, respectively. the rbs and mbs are set by sel rbn and sel mbn instructions, respectively. the bs can be saved/restored the stack area in 8-bit units by push bs/pop bs instruction. fig. 3-12 bank select register configuration (1) memory bank select register (mbs) the memory bank select register in a 4-bit register to store the most significant 4-bit address information of the data memory address (12 bits) and the memory bank to be accessed is specified by the mbs contents. banks 0, 1, 2, 3 and 15 can be specified. the mbs is set by sel mbn instruction. (n = 0, 1, 2, 3, 15) the address range for mbe and mbs setting is shown in fig. 2-1. upon reset input, the mbs is initialized to 0. (2) register bank select register (rbs) the register bank select register is used to specify the register bank for use as a general register and can set banks 0 to 3. the rbs is set by sel rbn instruction. (n = 0 to 3) upon reset input, the rbs is initialized to 0. table 3-5 rbe, rbs and register banks to be selected remarks : dont care 3210 000 fixed to bank 0 0 0 bank 0 selected 0 1 bank 1 selected 1 0 bank 2 selected 1 1 bank 3 selected rbs register bank rbe 100 fixed to 0 mbs3 mbs2 mbs1 mbs0 0 0 rbs1 rbs0 mbs rbs address symbol bs f82h
41 m pd75237 4. peripheral hardware functions 4.1 digital input/output ports the m pd75237 employs the memory mapped i/o and all input/output ports are mapped in the data memory space. fig. 4-1 digital port data memory address p03 p13 p23 p33 p43 p53 p63 p73 p83 p93 p103 p113 p123 p133 p143 p153 p02 p12 p22 p32 p42 p52 p62 p72 p82 p92 p102 p112 p122 p132 p142 p152 p00 p10 p20 p30 p40 p50 p60 p70 p80 p90 p100 p110 p120 p130 p140 p150 port0 port1 port2 port3 port4 port5 port6 port7 port8 port9 port10 port11 port12 port13 port14 port15 symbol ff0h ff1h ff2h ff3h ff4h ff5h ff6h ff7h ff8h ff9h ffah ffbh ffch ffdh ffeh fffh address 3 2 1 0 p01 p11 p21 p31 p41 p51 p61 p71 p81 p91 p101 p111 p121 p131 p141 p151
42 m pd75237 (1) digital input/output port configuration the digital input/output port configurations are shown in figs. 4-2 to 4-11. (2) input/output mode setting the input/output mode of each input/output port is set by the port mode register as shown in fig. 4-12. each port acts as an input when the corresponding port mode register bit is 0 and as an output port when the bit is 1. port mode register groups a and b each are set by the 8-bit memory manipulation instruction. upon reset input, all bits of each port mode register are cleared to 0. thus, the output buffer is turned off and all the ports are set to the input mode. (3) digital input/output port operation the operations of the port and pin for instruction execution vary, depending on the input/output mode setting as shown in table 4-1. table 4-1 input/output port operations for input/output instruction execution input mode (corresponding bit 0 of mode register) [output buffer off] output mode (corresponding bit 1 of mode register) [output buffer on] when 1-bit test instruction, 1-bit input instruction, 4-bit or 8-bit in- struction is executed when 4-bit or 8-bit output instruction is executed when 1-bit output instruction * is executed each pin data input accumulator data transfer to out- put latch output latch contents become un- defined output latch contents input accumulator data output to out- put pin output pin status change accord- ing to instruction * set1/clr1/mov1 portn.bit, cy, etc.
43 m pd75237 8 8 csim0 csim1 si0 sck0 int4 sck0 so0 v dd p-ch p00/int4 p02/so0/sb0 p03/si0/sb1 p01/ sck0 v dd p-ch p10/int0 p12/int2 p13/ti0 ti0 int2 int1 int0 si1 so1 sck1 sck1 ppo p80/ppo p82/so1 p83/si1 p11/int1 p81/ sck1 fig. 4-2 configurations of port 0, 1 and 8 input buffer pull-up resistor input buffer ? or f x /64 bit 1 of poga internal bus input buffer having hyster- esis characteristics internal input buffer bit 0 of poga pull-up resistor output buffer capable of switching between push-pull output and n-ch open drain output noise eliminator selector selector p01 output latch internal
44 m pd75237 v dd p-ch pmm=0 pmm=1 m p x pmm pm0 pm1 pm2 pm3 m p x pmm n=0 pmm n=1 pmm n pm n v dd p-ch fig. 4-3 port 3n and port 6n configurations (n = 0 to 3) input buffer output latch internal bus corresponding bit of port mode reg- ister group a m = 3, 6 n = 0 to 3 ( ) output buffer bit m of poga pull-up resistor fig. 4-4 port 2 configuration internal bus input buffer bit m of poga output latch corresponding bit of port mode register group b (m = 2) output buffer pull-up resistor
45 m pd75237 pmm=0 pmm=1 pm0 pm1 pm2 pm3 v dd pmm m p x fig. 4-5 configurations of ports 4 and 5 internal bus corresponding bit of port mode register group b (m = 4, 5) n-ch open drain output buffer output latch pull-up resistor mask option input buffer
46 m pd75237 m p x pmm=0 pmm=1 pm0 pm1 pm2 pm3 pmm fig. 4-6 port 7 configuration internal bus output latch corresponding bit of port mode register group b (m = 7) pull-down resistor mask option output buffer input buffer fig. 4-7 port 9 configuration p90/an4 p91/an5 p92/an6 p93/an7 internal bus input instruction to a/d converter input buffer
47 m pd75237 s k s k+1 s k+2 s k+3 s k /pm0 s k+1 /pm1 s k+2 /pm2 s k+3 /pm3 v load statb dspm 4 8 fig. 4-8 configurations of ports 10 and 11 remarks 1. port 10: k = 16, m = 10 2. port 11: k = 20, m = 11 remarks 1. port 12: k = 0, m = 12 2. port 13: k = 4, m = 13 fig. 4-9 configurations of ports 12 and 13 s k s k /pm0 s k+1 s k+2 s k+3 s k+1 /pm1 s k+2 /pm2 s k+3 /pm3 v load stata dspm 4 8 internal bus internal bus pull-down resistor mask option (simultaneously specified for s16 to s23) p-ch open drain output buffer pull-down resistor mask option mask option p-ch open drain output buffer
48 m pd75237 m p x v load digs stata dspm.3 4 8 4 ph0 ph2 ph1 ph3 s15 s14 s13 s12 t13 t11 t12 t10 s13/t12/p151/ph1 s14/t11/p152/ph2 s15/t10/p153/ph3 s12/t13/p150/ph0 s8 s9 s10 s11 m p x 4 8 4 dspm.3 stata digs v load s8/p140 s9/p141 s10/t15/p142 s11/t14/p143 s15 s14 fig. 4-10 port 14 configuration internal bus output buffer p-ch open drain output buffer pull-down resistor mask option (for each pin) * * * selector fig. 4-11 configurations of ports 15 and h * * * * output buffer internal bus * selector pull-down resistor mask option (for each pin) p-ch open drain output buffer * * * *
49 m pd75237 fig. 4-12 port mode register format port mode register group a pm63 pm62 pm61 pm60 pm33 pm32 pm31 pm30 7 6 54 3 2 10 address fe8h symbol pmga pm3n, pm6n 0 1 input mode (output buffer off) output mode (output buffer on) remarks CCCC : 0 or 1 (4) pull-up resistor register group a (poga) pull-up resistor register group a is intended to specify pull-up resistors to be built in ports 0 to 3 and port 6 (except p00). fig. 4-13 shows the format. set 1 when a pull-up resistor is incorporated or 0 when it is not incorporated. note mask option by which pull-up resistors at ports 4 and 5 and pull-down resistors at port 7 and ports 10 to 15 can be incorporated bit-wise. fig. 4-13 pull-up resistor register group a format po6 po3 po2 po1 po0 7 6 54 3 2 10 address fdch symbol poga port 0 (p01 to p03) port 1 (p10 to p13) port 2 (p20 to p23) port 3 (p30 to p33) port 6 (p60 to p63) symbol pmga remarks CCCC : 0 or 1 pm7 pm5 pm4 pm2 7 6 54 3 2 10 address fech pmgb symbol pmn 0 1 input mode (output buffer off) output mode (output buffer on) symbol pmgb p3n and p6n pin input/output specification (n = 0 to 3) port mode register group b port n input/output specification (n = 2, 4, 5, 7)
50 m pd75237 xt1 xt2 x1 x2 f xt f x scc pcc halt stop halt f/f stop f/f 4 q s r s r 1/ 4 1/ 1/ 1/ 1/8~1/4096 2 4 16 scc3 scc0 pcc0 pcc1 pcc2 pcc3 q 4.2 clock generator (1) clock generator configuration the clock generator is a circuit to generate clocks to be supplied to the cpu and the peripheral hardware. its configuration is shown in fig. 4-14. fig. 4-14 clock generator block diagram frequency divider timer/pulse generator watch timer subsystem clock gen- erator mainsystem clock gen- erator ? cpu ? int0 noise eliminator ? clock output circuit selector selector * instruction execution remarks 1. f x = main system clock frequency 2. f xt = subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. 1 clock cycle (t cy ) of f is 1 machine cycle of an instruction. for t cy , see ac characteristics in 11. electrical specifications . pcc2 and pcc3 clear f frequency divider wait release signal from bt standby release signal from interrupt control circuit reset signal internal bus * * h ? fip controller/driver ? basic interval timer ? timer/event counter ? serial interface ? watch timer ? clock output circuit ? int0 noise eliminator oscilla- tion stop
51 m pd75237 (2) clock generator functions the clock generator generates the following clocks and controls the cpu operating modes including the standby mode. ? main system clock : f x ? subsystem clock : f xt ? cup clock : f ? clocks for peripheral hardware the following clock generator operations are determined by the processor clock control register (pcc) and the system clock control register (scc): (a) upon reset input, the lowest speed mode (10.7 m s : at 6.0 mhz operation) *1 of the main system clock is selected. (pcc = 0, scc = 0) (b) one of the four-level cpu clocks can be selected by setting the pcc with the main system clock selected. (0.67 m s, 1.33 m s, 2.67 m s, 10.7 m s : at 6.0 mhz operation) *2 (c) two standby modes, the stop and halt modes, are available with the main system clock selected. (d) the clock generator can be operated at an ultra-low speed and with low-level power consumption (122 m s : at 32.768 khz operation) by selecting the subsystem clock with scc. (e) main system clock oscilloation can be stopped by scc with the subsystem clock selected. the halt mode can also be used but the stop mode cannot be used. (subsystem clock oscillation cannot be stopped.) (f) divided system clocks are supplied to the peripheral hardware. subsystem clocks can be directly supplied to the watch timer to that the timer function can be continued. (g) when the subsystem clock is selected, the watch timer can operate normally. however, other hardware cannot be used if the main system clock is stopped. *1. 15.3 m s : at 4.19 mhz operation 2. 0.95 m s, 1.91 m s, 3.82 m s, 15.3 m s : at 4.19 mhz operation
52 m pd75237 (3) processor clock control register (pcc) the pcc is a 4-bit register to select the cpu clock f with the lower 2 bits and to control the cpu operating mode with the higher 2 bits. (see fig. 4-15 processor clock control register format .) when bit 3 or 2 is set (1), the standby mode is set. if the standby mode is released by the standby release signal, both bits are automatically cleared and the normal operating mode is set. (for details, refer to 6. standby functions .) the lower 2 bits of the pcc are set by the 4-bit memory manipulation instruction (with the higher 2 bits set to 0). bits 3 and 2 are reset 1 by the stop and halt instructions, respectively. the stop and halt instructions can always be executed irrespective of the mbe contents. the cpu clock selection is possible only when operated on the main system clock. when operated on the subsystem clock, the lower 2 bits of pcc are invalidated and f xt /4 is set. the stop instruction is also enabled only when in operation with the main system clock. reset input clears pcc to 0.
53 m pd75237 fig. 4-15 processor clock control register format fb3h pcc3 pcc2 pcc1 pcc0 pcc 3210 cpu clock select bit (when f x = 6.0 mhz) address symbol 0 0 1 1 0 1 0 1 normal operating mode halt mode stop mode setting prohibited cpu operating mode control bit remarks 1. f x : main system clock oscillator output frequency 2. f xt : subsystem clock oscillator output frequency 0 0 1 1 scc = 1 values in parentheses are when f xt = 32.768 khz scc = 0 values in parentheses are when f x = 4.19 mhz cpu clock frequency 1 machine cycle cpu clock frequency 1 machine cycle f = f x /64 (65.5 khz) f = f x /16 (262 khz) f = f x /8 (524 khz) f = f x /4 (1.05 mhz) f = f xt /4 (8.192 khz) 15.3 m s 3.81 m s 1.91 m s 0.95 m s 0 1 0 1 setting prohibited f = f xt /4 (8.192 khz) 122 m s 122 m s 0 0 1 1 scc = 1 values in parentheses are when f xt = 32.768 khz scc = 0 values in parentheses are when f x = 6.0 mhz cpu clock frequency 1 machine cycle cpu clock frequency 1 machine cycle f = f x /64 (93.7 khz) f = f x /16 (375 khz) f = f x /8 (750 khz) f = f x /4 (1.5 mhz) f = f xt /4 (8.192 khz) 10.7 m s 2.67 m s 1.33 m s 0.67 m s 0 1 0 1 setting prohibited f = f xt /4 (8.192 khz) 122 m s 122 m s (when f x = 4.19 mhz)
54 m pd75237 (4) system clock control register (scc) the scc is a 4-bit register to select the cpu clock f with the least significant bit and to control main system clock oscillation stop with the most significant bit (refer to fig. 4-16 ). although scc.0 and scc.3 are located at the same data memory address, both bits cannot be changed simultaneously. thus, scc.0 and scc.3 are set by the bit manipulation instruction. scc.0 and scc.3 can always be bit manipulated irrespective of the mbe contents. main system clock oscillation can be stopped by setting scc.3 only when in operation with the subsystem clock. oscillation when in operation with the main system clock is stopped by the stop instruction. reset input clears scc to 0. fig. 4-16 system clock control register format fb7h scc3 scc0 scc 3210 address symbol 0 0 1 1 main system clock subsystem clock subsystem clock oscillation enabled oscillation stop system clock selection main system clock oscillation setting prohibited scc3 scc0 0 1 0 1 note 1. a maximum of 1/f xt is required to change the system clock. thus, when stopping the main system clock oscillation, change the clock to the subsystem clock and set scc.3 following the passage of more than the machine cycles described in table 4-2. 2. the normal stop mode cannot be set if oscillation is stopped by setting scc.3 while in operation with the main system clock. 3. if scc.3 is set to 1, x1 input is internally short-circuited to v ss (gnd potential) to suppress crystal oscillator leakage. thus, when using an external clock for the main system clock do not set scc.3 to 1. 4. when pcc = 0001b ( f = f x /16 selected), do not set scc.0 to 1. when switching from the main system clock to the subsystem clock, do so after setting pcc to another value (pcc 1 0001b). do not set pcc = 0001b while in operation with the subsystem clock.
55 m pd75237 note when using a main system clock and subsystem clock oscillator, wire the crosshatched section in figs. 4-17 and 4-18 as follows to prevent any effect of the wiring capacity. ? make the wiring as short as possible. ? do not allow wiring to intersect with other signal conductors. do not allow wiring to be near a line through which varying high current flows. ? set the oscillator capacitor grounding point to the same potential as that of v ss . do not ground to a ground pattern through which high current flows. ? do not fetch signals from the oscillator. the subsystem clock oscillator has a low amplification factor to maintain low current consumption and is more likely to malfunciton due to noise than the main system clock oscillator. thus, take extra care when using a subsystem clock. (5) system clock oscillator the main system clock oscillator oscillates with a crystal resonator (with a standard frequency of 6.0 mhz) or a ceramic resonator connected to the x1 and x2 pins. external clocks can be input to this oscillator. fig. 4-17 external circuit of main system clock oscillator (a) crystal/ceramic oscillation (b) external clock external clock xt1 xt2 xt1 xt2 32.768 khz m pd75237 m pd75237 leave open x1 x2 x1 x2 external clock crystal or ceramic resonator m pd75237 m pd75237 note the stop mode cannot be set while an external clock is input because the x1 pin is short-circuited to v ss in the stop mode. the subsystem clock oscillator oscillates with a crystal resonator (with a standard frequency of 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to this oscillator. fig. 4-18 external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock
56 m pd75237 (6) time required for system clock and cpu clock switching the system clock and the cpu clock can be switched to each other with the least significant bit of the scc and the lower 2 bits of the pcc. this switching is not executed just after register rewrite and operation continues with the previous clock during the specified machine cycle. thus, to stop main system clock oscillation, it is necessary to execute the stop instruction or to set scc.3 after the specified switching time. table 4-2 maximum time required for system clock and cpu clock switching scc 0 pcc 1 pcc 0 scc0 0 pcc1 0 pcc0 0 scc0 0 pcc1 0 pcc0 1 scc0 0 pcc1 1 pcc0 0 scc0 0 pcc1 1 pcc0 1 scc0 1 pcc1 set value before switching set value after switching 0 0 1 1 0 1 0 1 0 1 4 machine cycle 8 machine cycle 16 machine cycle 1 machine cycle 1 machine cycle 8 machine cycle 16 machine cycle setting prohibited 1 machine cycle 4 machine cycle 16 machine cycle 1 machine cycle 1 machine cycle 4 machine cycle 8 machine cycle 1 machine cycle f x 4f xt machine cycle f x 8f xt machine cycle setting prohibited f x 64f xt machine cycle (3 machine cycle) (23 machine cycle) (64 machine cycle) pcc0 remarks 1. cpu clock f is a clock to be supplied to the internal cpu of m pd75237 and its inverse number is the minimum instruction time (defined as one machine cycle in this manual). 2. values in parentheses are when f x = 6.0 mhz and f xt = 32.768 khz. note when pcc = 0001b ( f = f x /16 selected), do not set scc.0 to 1. when switching from the main system clock to the subsystem clock, do so after setting pcc to another value (pcc 1 0001b). do not set pcc = 0001b while in operation with the subsystem clock.
57 m pd75237 f x f x f xt f x f x =6.0 mhz f xt =32.768 khz ( ) (7) system clock and cpu clock switching procedure system clock and cpu clock switching is described referring to fig. 4-19. fig. 4-19 system clock and cpu clock switching commercial power supply on off system clock cpu clock internal reset operation v dd pin voltage res signal wait 21.8 ms [31.3 ms] 10.7 m s [15.3 m s] 0.67 m s [0.95 m s] 122 m s 0.67 m s [0.95 m s] reset input starts the cpu at the lowest speed (21.8 ms : at 6.0 mhz operation) *1 of the main system clock after the wait time (10.7 m s : at 6.0 mhz operation) *2 for maintaining the oscillation stabilize time. the cpu rewrites the pcc and operates at its maximum available speed after the lapse of sufficient time for the v dd pin voltage to increase to a voltage allowing the highest speed operation. a the cpu detects commercial power-off from the interrupt input (int4 is effective), sets scc.0 and operates with the subsystem clock. (at this time, subsystem clock oscillation must have started before- hand. ) after the passage of time required for the cpu clock to switch to the subsystem clock (32 machine cycles), the cpu sets scc.3 to stop main system clock oscillation. after the cpu detects the commercial power restored from the interrupt, it clears scc.3 and starts main system clock oscillation. following the passage of time required for oscillation stabilization, the cpu clears scc.0 and operates at its highest speed. *1. 31.3 ms at 4.19 mhz operation 2. 15.3 m s at 4.19 mhz operation , values in brackets are when f x = 4.19 mhz. remarks 4
58 m pd75237 clom 3 0 clom 1 clom 0 clom port2.2 pcl/p22 f x /2 3 f x /2 4 f x /2 6 4 4.3 clock output circuit (1) clock output circuit configuration the clock output circuit is configured as shown in fig. 4-20. (2) clock output circuit functions the clock output circuit is intended to generate clock pulses from the p22/pcl pin. it is used for remote- controlled output or clock pulse supply to the peripheral lsi. follow the procedure below to generate clock pulses. (a) select the clock output frequency. do not output clocks. (b) write 0 to p22 output latch. (c) set the port 2 input/output mode to output. (d) enable clock output. fig. 4-20 clock output circuit configuration remarks the clock output circuit has such a configuration as to prevent pulses having short widths when switching clock output enable/disable. f selector output buffer pmgb bit 2 p22 output latch internal bus port 2 input/ output mode specification bit from clock generator
59 m pd75237 f output * (1.50 mhz, 750 khz, 375 khz, 93.7 khz) f x /2 3 output (750 khz) f x /2 4 output (375 khz) f x /2 6 output (93.7 khz) clom3 0 clom 1 clom0 (3) clock output mode register (clom) the clom is a 4-bit register to control clock output. the clom is set by a 4-bit memory manipulation instruction. data cannot be read from the clom. example cpu clock f output from pcl/p22 pin sel mb15 ; or clr1 mbe mov a, #1000b mov clom, a reset input clears the clom to 0 and disables clock output. fig. 4-21 clock output mode register format fd0h clom 3210 address symbol 0 0 1 1 0 1 0 1 clock output enable/disable bit note be sure to write 0 to bit 2 of clom. output disabled output enabled 0 1 f output * (1.05 mhz, 524 khz, 262 khz, 65.5 khz) f x /2 3 output (524 khz) f x /2 4 output (262 khz) f x /2 6 output (65.5 khz) 0 0 1 1 0 1 0 1 * f is a cpu clock to be selected by pcc. clock output frequency select bit (when f x = 6.0 mhz) (when f x = 4.19 mhz)
60 m pd75237 (4) example of application to remote-controlled output the clock output function of the m pd75237 can be applied to remote-controlled output. the carrier frequency of remote-controlled output is selected by the clock frequency select bit of the clock output mode register. pulse output is enabled/disabled by controlling the clock output enable/disable bit by software. the clock output circuit has such a configuration as to prevent pulses having short widths when switching clock output enable/disable. fig. 4-22 remote-controlled output application example pcl pin output clom.3
61 m pd75237 4.4 basic interval timer (1) basic interval timer configuration the basic interval timer configuration is shown in fig. 4-23. (2) basic interval timer functions the basic interval timer has the following functions: (a) interval timer operation to generate reference time (at any of four time intervals) (b) watchdog timer application to detect inadvertent program loop (c) wait time select and count upon standby mode release (d) count contents read fig. 4-23 basic interval timer configuration f x /2 5 4 f x /2 7 f x /2 9 f x /2 12 set1 btm3 btm2 btm1 btm0 8 bt irqbt btm 3 mpx clear basic interval timer (8-bit freqency divider) vectored interrupt request signal clear set wait release signal upon standby mode release internal bus from clock generator * bt interrupt request flag * instruction execution
62 m pd75237 (3) basic interval timer mode register (btm) the btm is a 4-bit register to control basic interval timer operations. the btm is set by a 4-bit memory manipulation instruction. bit 3 can be set independently by a bit manipulation instruction. when bit 3 is set 1, the basic interval timer contents and the basic interval timer interrupt request flag (irqbt) are simultaneously cleared (basic interval timer start). reset input clears the contents to 0 and sets the interrupt request signal generation interval time to its maximum value. fig. 4-24 basic interval timer mode register format btm3 btm2 btm1 btm0 f85h btm 3210 address symbol the basic interval timer is started (counter and interrupt request flag clear) by writing 1. when the timer starts operating, it is automatically reset to 0. interrupt interval time (wait time upon standby mode release) f x /2 12 (1.46 khz) f x /2 9 (11.7 khz) f x /2 7 (46.9 khz) f x /2 5 (188 khz) 2 20 /f x (175 ms) 2 17 /f x (21.8 ms) 2 15 /f x (5.46 ms) 2 13 /f x (1.37 ms) in all other cases setting prohibited input clock specification interrupt interval time (wait time upon standby mode release) f x /2 12 (1.02 khz) f x /2 9 (8.18 khz) f x /2 7 (32.768 khz) f x /2 5 (131 khz) 2 20 /f x (250 ms) 2 17 /f x (31.3 ms) 2 15 /f x (7.82 ms) 2 13 /f x (1.95 ms) in all other cases setting prohibited input clock specification 0 0 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 (when f x = 6.0 mhz) (when f x = 4.19 mhz) basic interval timer start control bit
63 m pd75237 (4) basic interval timer operation the basic interval timer (bt) is always incremented by clocks from the clock generator and sets the interrupt request flag (irqbt) due to an overflow. bt count operation cannot be stopped. four interrupt generate intervals are available by setting the btm (refer to fig. 4-24 basic interval timer mode register format ). the basic interval timer and the interrupt request flag can be cleared by setting bit 3 of the btm (1) (interval timer start instruction). the count state can be read from the basic interval timer (bt) by the 8-bit manipulation instruction. data cannot be written to the bt. note when reading the basic interval timer count contents, execute the read instruction twice and compare the two read contents so as not to read unstable data undergoing count update. if the two values are both acceptable, use the second read value as the correct one. if they differ completely, execute reading again from the beginning. to obtain the oscillation stabilize time from stop mode release to system clock oscillation stabilization, the wait function is available to stop cpu operation until the basic interval timer overflows. wait time after reset input is fixed, however, if the stop mode has been released by interrupt generation, the wait time can be selected by btm setting. in that case, the wait time is equal to the interval time shown in fig. 4-24. btm setting must be done before stop mode setting. (for details, refer to 6 . standby functions .) 4.5 timer/event counter (1) timer/event counter functions the timer/event counter has the following functions. (a) program interval timer operation (b) output of square wave with any frequency to pto0 pin (c) event counter operation (d) output of n-divided ti0 pin input to pto0 pin (frequency divider operation) (e) serial shift clock supply to the serial interface circuit (f) count state read function
64 m pd75237 8 8 8 8 8 tm07 tm06 tm05 tm04 tm03 tm02 ? ? set1 tm0 tmod0 toe0 port2.0 port1.3 p13/ti0 mpx cp t0 tout f/f p20/pto0 reset intt0 irqt0 fig. 4-25 timer/event counter block diagram internal bus port 2 input /output mode pgmb bit 2 irqt0 set signal ( ) reset timer operation start output buffer to serial interface *1. instruction execution 2. p13/ti0 pin is an external event pulse input pin which serves as timer/event counter and event counter. match event counter #1 input buffer modulo register (8) comparator (8) count register (8) clear (refer to fig. 4-26 ) irqt0 clear signal *1 from clock genera- tor p20 output latch to enable flag *2
65 m pd75237 (2) timer/event counter mode register (tmo) and timer/event counter output enable flag (toe0) the timer/event counter mode register (tm0) is an 8-bit register to control the timer/event counter and is set by an 8-bit memory manipulation instruction. fig. 4-27 shows the timer/event counter mode register format. bit 3 is a timer start command bit which can be set independently. when the timer starts operating, this bit is automatically reset to 0. reset input clears all bits of the tm0 to 0. the timer/event counter output enable flag (toe0) controls enable/disable for output to the pto0 pin in the timer out f/f (tout f/f) state. fig. 4-26 shows the timer/event counter output enable flag format. the timer out f/f (tout f/f) is an f/f which is reversed by a match signal transmitted from the comparator. the timer out f/f is reset by an instruction which sets bit 3 of the tm0. reset input clears toe0 and tout f/f to 0. fig. 4-26 timer/event counter output enable flag format 3 toe0 0 1 disabled enabled address fa2h timer/event counter output enable flag
66 m pd75237 fig. 4-27 timer/event counter mode register format tm06 tm05 tm04 tm03 tm02 7 6 54 3 2 10 address fa0h symbol tm0 count operation writing 1 clears the counter and irqt0 flag. if bit 2 has been set to "1", the counter operation starts. 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 tm06 tm05 tm04 count pulse (cp) in all other cases ti0 input rising edge ti0 input falling edge f x /2 10 (4.09 khz) f x /2 8 (16.4 khz) f x /2 6 (65.5 khz) f x /2 4 (262 khz) setting prohibited operating mode timer start command bit (when f x = 4.19 mhz) 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 tm06 tm05 tm04 count pulse (cp) in all other cases ti0 input rising edge ti0 input falling edge f x /2 10 (5.86 khz) f x /2 8 (23.4 khz) f x /2 6 (93.8 khz) f x /2 4 (375 khz) setting prohibited count pulse (cp) select bit (when f x = 6.0 mhz) 0 1 count operation stop (with count con- tents held)
67 m pd75237 mpx (3) timer/event counter operating modes the count operation stop mode and the count operating mode are available by setting the mode register for the timer/event counter operation. the following operations are enabled irrespective of the mode register setting: (a) ti0 pin signal input and test (dual-function pin p13 input testable) (b) output of the timer out f/f state to pto0 (c) modulo register (tmod0) setting (d) count register (t0) read (e) interrupt request flag (irqt0) set/clear/test (a) count operation stop mode when tm0 bit 2 is 0, this mode is set. in this mode, count operation is not carried out because count pulse (cp) supply to the count register is stopped. (b) count operating mode when tm0 bit 2 is 1, this mode is set. the count pulse selected by bits 4 to 6 is supplied to the count register and the count operation shown in fig. 4-28 is carried out. the timer operation is normally started by the following operations in the described order. set the number of counts to the modulo register (tmod0). set the operating mode, count clock and start command to the mode register (tm0). set the modulo register by an 8-bit data transfer instruction. fig. 4-28 operation in count operating mode ti0 count register (t0) modulo register (tmod0) comparator cp clear intt0 (irqt0 set signal) tout f/f to serial interface (channel 0) { match internal clock pto0
68 m pd75237 (4) timer/event counter time setting [timer set time] (cycle) is obtained by dividing [modulo register contents + 1] by [count pulse frequency] selected by timer mode register setting. t (sec) t (sec) : timer set time (sec) f cp (hz) : count pulse frequency (hz) n : modulo register value (n 1 0) once the timer is set, an interrupt request signal (irqt0) is generated at the set intervals. table 4-3 shows the resolutions with each count pulse of the timer/event counter and the maximum set time (with ffh set to the modulo register). table 4-3 resolution and maximum set time 1 1 1 1 0 0 1 1 0 1 0 1 resolution maximum set time tm06 tm05 tm04 43.7 ms 10.9 ms 2.73 ms 683 m s 171 m s 42.7 m s 10.7 m s 2.67 m s mode register timer channel 0 (when f x = 6.0 mhz) 1 1 1 1 0 0 1 1 0 1 0 1 resolution maximum set time tm06 tm05 tm04 62.5 ms 15.6 ms 3.91 ms 977 m s 244 m s 61.1 m s 15.3 m s 3.81 m s mode register timer channel 0 (when f x = 4.19 mhz) = n + 1 f cp = (n + 1) ? (resolution)
69 m pd75237 128 f x f xt f w (32.768 khz) 8 f w 16 f w (4.096 khz) 2 14 f w 2 7 f w (256 hz : 3.91 ms) 2 hz 0.5 sec ( ) intw p23/buz port2.3 wm wm7 0 wm5 wm4 0 wm2 wm1 wm0 8 4.6 watch timer (1) watch timer the m pd75237 incorporates one channel of watch timer having a configuration shown in fig. 4-29. (2) watch timer functions (a) sets the test flag (irqw) at 0.5-sec intervals. the standby mode can be released by irqw. (b) 0.5-second interval can be set with the main system clock (4.19 mhz) or subsystem clock (32.768 khz). (c) the fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection. (d) the fixed frequencies (2.048 khz, 4.096 khz and 32.768 khz) can be output to the p23/ buz pin for use to generate buzzer sound and trim the system clock oscillator frequency. (e) since the frequency divider can be cleared, the watch can be started from zero second. fig. 4-29 watch timer block diagram remarks values at f x = 4.194304 mhz and f xt = 32.768 khz are indicated in parentheses. note in the main system clock 6.0 mhz operation, 0.5-second interval can be generated. therefore, after switching to the subsystem clock, 0.5-second interval should be generated. internal bus clear frequency divider selector bit 2 of pmgb p ort 2 input/ output mode output buffer p23 output latch ) ( irqw set signal selector selector (32.768 khz) from clock generator (32.768 khz)
70 m pd75237 (3) watch mode register (wm) the watch mode register (wm) is an 8-bit register to control the watch timer. its format is shown in fig. 4-30. the watch mode register is set by an 8-bit memory manipulation instruction. reset input clears all bits to 0. fig. 4-30 watch mode register format 7 6 5 432 10 count clock (f w ) select bit operating mode select bit watch operation enable/disable bit buz output frequency select bit * not supported with ie-75000-r buz output enable/disable bit wm7 0 wm5 wm4 0 wm2 wm1 wm0 wm f98h address symbol wm0 0 1 subsystem clock: f xt selected system clock divided output: selected normal watch mode : irqw set at 0.5 sec wm1 0 1 fast watch mode : irqw set at 3.91 ms wm2 0 1 watch operation enabled watch operation stopped (frequency divider clear) 0 0 0 1 1 1 0 1 wm4 wm5 buz output frequency f w /2 4 (2.048 khz) f w /2 3 (4.096 khz) * setting prohibited f w (32.768 khz) * wm7 0 1 buz output enabled buz output disabled f x 128 f w 2 7 f w 2 14 ( ) ) (
71 m pd75237 4.7 timer/pulse generator (1) timer/pulse generator functions the m pd75237 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse generator. the timer/pulse generator has the following functions. (a) functions available in the timer mode ? 8-bit interval timer operation (irqtpg generation) enabling the clock source to be varied at 5 levels ? square wave output to ppo pin (b) functions available in the pwm pulse generate mode ? 14-bit accuracy pwm pulse output to the ppo pin (used as a digital-to-analog converter and applicable to tuning) ? interrupt generation of fixed time interval ( = 5.46 ms : at 6.0 mhz operation) * * 7.81 ms at 4.19 mhz operation if pulse output is not necessary, the ppo pin can be used as a 1-bit output port. note if the stop mode is set while the timer/pulse generator is in operation, miss-operation may result. to prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register. 2 15 f x
72 m pd75237 (2) timer/pulse generator mode register (tpgm) the timer/pulse generator mode register (tpgm) is an 8-bit register to control timer/pulse generator operations. its format is shown in fig. 4-31. the tpgm is set by the 8-bit memory manipulation instruction. bit 3 enables or disables the timer/pulse generator modulo register (modh, modl) contents to be transferred (reloaded) to the modulo latch and can be manipulated individually. the timer/pulse generator operation can be stopped and current consumption can be decreased by setting the tpgm1 to 0. reset input clears all bits to 0. fig. 4-31 timer/pulse generator mode register format timer/pulse generator operating mode select bit timer/pulse generator operation enable/disable bit modulo register reload enable/disable bit ppo output latch data ppo pin output select bit static/pulse ppo pin output enable/disable bit 765 43 210 tpgm7 tpgm5 tpgm4 tpgm3 0 tpgm1 tpgm0 address symbol f90h tpgm pwm pulse generate mode selected tpgm0 0 1 timer mode selected timer/pulse generator operation stopped tpgm1 0 1 timer/pulse generator operation enabled modulo register reload disabled tpgm3 0 1 modulo register reload enabled output 0 to ppo output latch tpgm4 0 1 output 1 to ppo output latch static output from ppo pin tpgm5 0 1 pulse (square wave/pwm) output from ppo pin ppo pin output disabled (high impedance) tpgm7 0 1 ppo pin output enabled
73 m pd75237 8 8 modl modh tpgm3 8 8 1/2 f x tpgm1 cp tpgm4 tpgm5 tpgm7 ppo inttpg (3) configuration and operation for use in the timer mode the timer/pulse generator configuration for use in the timer mode is shown in fig. 4-32. the timer mode is selected by setting tpgm bit 0 to 1. in the timer mode, enable modulo register reload by setting tpgm3 to 1. in the timer mode, select the prescalar with modulo register l (modl) and set the frequency or interrupt interval set value to modulo register h (modh). start the timer by resetting the tpgm1 from 0 to 1. the operation timing for modh setting is shown in fig. 4-33 and the frequency or interrupt interval setting is shown in table 4-4. square wave output or static output to the ppo pin can be switched. in the case of square wave output, set tpgm5 to 1 and tpgm7 to 1. fig. 4-32 block diagram of timer/pulse generator (timer mode) note if the timer is stopped in the timer operating mode, the irqtpg may be set because the t f/f is set. thus, when stopping the timer, do so with interruption disabled, and after the timer has stopped, clear the irqtpg. modulo register l (8) modulo register h (8) clear clear match output buffer irqtpg set signal ( ) set internal bus selector frequency divider (set to "1") prescalar select latch (5) count register (8) t f/f comparator (8) modulo latch h (8)
74 m pd75237 65432 10000 01000 00100 00010 00001 interrupt generate interval square wave output frequency (f x = 6.0 mhz) (f x = 6.0 mhz) 256( n+1) f x f x 128( n+1) 64( n+1) 32( n+1) 16( n+1) f x f x f x = 10.7 m s to 1.37 ms f x 256( n+1) f x f x 128( n+1) 64( n+1) 32( n+1) 16( n+1) f x f x = 91.6 hz to 11.7 khz fig. 4-33 timer mode operation timing table 4-4 modulo register setting 65432 10000 01000 00100 00010 00001 interrupt generate interval square wave output frequency (f x = 4.19 mhz) (f x = 4.19 mhz) 256( n+1) f x = 122 m s to 15.6 ms f x 128( n+1) 64( n+1) 32( n+1) 16( n+1) f x f x f x f x 256( n+1) f x f x 128( n+1) 64( n+1) 32( n+1) 16( n+1) f x f x = 512 hz to 65 khz note 1. only the above values can be set to modl. be sure to set 0 to bits 0, 1 and 7. 2. n is the modh set value. 0 cannot be set to n. be sure to set a value in the range from 1 to 255 to n. cp modh t f/f (ppo) 0 1 2 n-1 n 0 n 0 n 0 n tpgm1 set irqtpg generated count register (when f x = 6.0 mhz) (when f x = 4.19 mhz) = 15.3 m s to 1.95 ms = 61.0 m s to 7.81 ms modl bits 2 to 6 modl bits 2 to 6 = 85.3 m s to 10.9 ms = 42.7 m s to 5.45 ms = 183 hz to 23.4 khz = 21.3 m s to 2.73 ms = 366 hz to 46.9 khz = 732 hz to 93.8 khz = 5.33 m s to 683 m s = 1465 hz to 188 khz = 64 hz to 8 khz = 128 hz to 16 khz = 30.5 m s to 3.91 ms = 256 hz to 32 khz = 1024 hz to 131 khz = 7.63 m s to 977 m s
75 m pd75237 (4) configuration and operation for use in the pwm pulse generate mode the timer/pulse generator for use in the pwm pulse generate mode is shown in fig. 4-34. the pwm pulse generate mode is selected by setting tpgm0 to 0. pulse output is enabled by setting tpgm5 and tpgm7 to 1. in the pwm mode, pwm pulse can be output from the ppo pin and the irqtpg can be set at the fixed interval (2 15 /f x = 5.46 ms : at 6.0 mhz operation) *1 . the pwm pulse generated by the m pd75237 is an active-low, 14-bit accuracy pulse. this pulse is converted to an analog voltage by integrating it using an external low-pass filter and can be applied for electronic tuning and dc motor control. (refer to fig. 4-35 example of d/a conversion configuration with m pd75237. ) the pwm pulse is generated by combining the fundamental period determined by 2 10 /f x (171 m s: at 6.0 mhz operation) *2 and the sub period of 2 15 /f x (5.46 ms: at 6.0 mhz operation) *1 and the time constant of the external low-pass filter can be shortened. the low-level width of the pwm pulse is determined by the 14-bit modulo latch value. the modulo latch value is determined as a result of transfer of modh 8 bits to the most significant 8 bits of the modulo latch and modl most significant 6 bits to the least significant 6 bits of the modulo latch. the digital-to analog converted output voltage is given as in the m pd75237, all 14 bits can be transferred simultaneously to the modulo latch after correct data has been written to modh and modl by the 8-bit manipulation instruction. this aims at preventing the pwm from being generated with an unstable value in the process of modulo latch rewrite. this transfer is called reload and is controlled by tpgm3. note 1. setting 0 to modulo register h (modh) disables the pwm pulse generator to operate normally. be sure to set to modh a value in the range from 1 to 255. 2. when the least significant 2 bits of modulo register l (modl) are read, an undefined value is read. 3. the fundamental period of the pwm pulse is 2 10 /f x (171 m s: at 6.0 mhz operation)*2. if the module latch is changed with a shorter period, the pwm pulse remains unchanged. *1. 7.81 ms at 4.19 mhz operation 2. 244 m s at 4.19 mhz operation (5) static output to the ppo pin if pulse output is not necessary, the ppo pin can be used for normal static output. in this case, set output data to tpgm4 with tpgm5 and tpgm7 set to 0 and 1, respectively. v an = v ref where v ref : external switching circuit reference voltage modulo latch value 2 14
76 m pd75237 f x tpgm1 tpgm3 8 8 modh modl (2) modh (8) ppo tpgm5 tpgm7 inttpg 1/2 modl 7-2 (6) fig. 4-34 timer/pulse generator block diagram (pwm pulse generate mode) fig. 4-35 example of d/a conversion configuration with m pd75237 m pd75237 signal switching circuit low-pass filter (analog voltage) internal bus modulo register h (8) modulo register l (6) modulo latch (14) pwm pulse generator output buffer frequency divider ppo pwm v ref v an (irqtpg set signal) ( =5.46 ms : at 6.0 mhz operation) * 2 15 f x selector * 7.81 ms at 4.19 mhz operation
77 m pd75237 4.8 event counter (1) event counter configuration the event counter of the m pd75237 incorporates a noise eliminator and has a configuration shown in fig. 4-36. fig. 4-36 event counter block diagram note ti0/p13 pin is an external event pulse input pin which serves as timer/event counter #0 and event counter #1. (2) event counter functions the event counter has the following functions. (a) event counter operation (b) count state read function (c) count pulse edge specification (d) noise eliminating function internal bus 8-bit counter overflow flag noise eliminator timer/counter #0 selector selector tm1.2 ti0/p13 t1 irqt1 gatec.0 tm1.4 f x 4
78 m pd75237 (3) event counter mode register the event counter mode register (tm1) is an 8-bit register to control the event counter. its format is shown in fig. 4-37. tm1 is set by an 8-bit memory manipulation instruction. bit 3 is an event counter start bit and can be set independently. when the counter starts operating, bit 3 is automatically reset to 0. fig. 4-37 event counter mode register format event count operation enable/disable bit event counter start command bit count pulse edge specification (4) overflow flag (irqt1) the overflow flag is a flag which is set (1) by an overflow of the event counter count register and is cleared (0) by a count operation start command. (5) event counter control register (gatec) this is a register to select sampling with a sampling clock (f x /4). a pulse having a smaller width than that of two sampling clock cycles (8/f x ) is eliminated as noise by a noise eliminator and a pulse having a width larger than that of the sampling clock is securely acknowledged as an interrupt signal. its format is shown in fig. 4-38. fig. 4-38 event counter control register format 76543 210 0 0 0 tm14 tm13 tm12 0 0 address symbol tm1 fa8h count operation stopped (with count value held) tm12 0 1 count operation enabled tm13 ti0 input rising edge tm14 0 1 ti0 input falling edge writing "1" clears the counter and irqt1 flag. if tm12 is "1", count operation starts. 1 0 symbol address fabh gatec 32 1 0 00 0 gatec0 sampling by f x /4 no sampling
79 m pd75237 4.9 serial interface the m pd75237 incorporates two channels of clocked 8-bit serial interfaces. table 4-5 gives differences between channel 0 and channel 1. table 4-5 differences between channels 0 and 1 channel 1 channel 0 3-wire serial i/o clock selection transfer mode transfer end flag serial transfer end flag (eot) f x /2 4 , f x /2 3 , tout f/f, external clock f x /2 4 , f x /2 3 , external clock msb first/lsb first switchable msb first serial transfer end interrupt request flag (irqcsi0) use enabled none serial transfer mode and function 2-wire serial i/o serial bus interface
80 m pd75237 (1) serial interface (channel 0) functions the following four modes are available for the m pd75237 serial interface (channel 0). the functions of each mode are outlined below. ? operation stop mode this is the mode used when no serial transfer is performed. low power consumption operation is possible in this mode. ? 3-wire serial i/o mode 8-bit data is transferred using three lines of serial clock (sck0), serial output (so0) and serial input (si0). the 3-wire serial i/o mode enables simultaneous transmission/reception, thus shortening the data transfer processing time. since the start bit of 8-bit data for serial transfer can be switched between msb and lsb, channel 0 can be connected to a device having either start bit. in the 3-wire serial i/o mode, channel 0 can be connected to the 75x series, 78k series and various types of peripheral i/o devices. ? 2-wire serial i/o mode 8-bit data is transferred using two lines of serial clock (sck0) and serial data bus (sb0 or sb1). communication is possible with two or more devices by controlling the level of output to the two lines by software. since the output level of sck0 and sb0 (or sb1) can be controlled by software, any transfer format is applicable. thus, the number of handshake lines previously required to connect two or more devices can be decreased and so the input/output ports can be used efficiently. ? sbi mode (serial bus interface mode) this mode enables communication with two or more devices with two lines of serial clock (sck0) and serial data bus (sb0 or sb1). this mode is compliant with the nec serial bus format. in the sbi mode, the transmitter can output an address for selection of a serial communication target device on the serial data bus, a command to provide instructions to the target device and actual data. the receiver can distinguish between address, command and data by hardware. as in the 2- wire serial i/o mode, this function enables the input/output ports to be used efficiently and the serial interface control portions of any applied program to be simplified. (2) serial interface (channel 0) configuration fig. 4-39 is a block diagram of serial interface (channel 0).
81 m pd75237 8/4 8 8 8 csim0 sbic relt cmdt clr set p03/si0/sb1 p02/so0/sb0 p01/sck0 (8) (8) (8) d q ackt acke bsye reld cmdd ackd intcsi0 fx/2 3 fx/2 4 fx/2 6 tout f/f intcsi0 p01 fig. 4-39 serial interface (channel 0) block diagram internal bus selector selector address comparator bus release /command /acknowledge detector bit manipulation bit test bu sy /acknowledge output circuit serial clock selector s lave address register (sva) match signal external sck0 so0 latch shift register 0 (sio0) i ntcsi0 control circuit bit test ( from timer/event counter) p01 output latch ) ( irqcsi0 set signal serial clock control circuit s erial clock counter
82 m pd75237 csie0 coi wup csim04 csim03 csim02 csim01 csim00 7 6 5 4 3 2 1 0 symbol address csim0 fe0h serial clock select bit (w) wake-up function specify bit (w) serial interface operating mode select bit (w) signal (r) from address comparator serial interface operation enable/disable specify bit (w) (3) serial interface (channel 0) register functions (a) serial operating mode register 0 (csim0) fig. 4-40 shows a serial operating mode register 0 (csim0) format. csim0 is an 8-bit register to specify the serial interface (channel 0) operating mode, serial clock and the wake-up function. an 8-bit memory manipulation instruction is used for csim0 operations. the higher 3 bits can be manipulated in 1-bit units. use each bit name for bit manipulation. read/write operation is enabled/disabled depending on the bit (refer to fig. 4-40 ). bit 6 is only enabled for test and the written data is invalidated. reset input clears all bits to 0. fig. 4-40 serial operating mode register 0 (csim0) format (1/3) remarks 1. (r) : read only 2. (w) : write only
83 m pd75237 () ( ) ( ) ) ( fig. 4-40 serial operating mode register 0 (csim0) format (2/3) serial clock select bit (w) * values in parentheses are when f x = 6.0 mhz or when f x = 4.19 mhz. serial interface operating mode select bit (w) remarks : dont care wake-up function specify bit (w) note when wup = 1 is set during busy signal output, busy is not released. in sbi, busy signal continues to be output up to the falling edge of the next serial clock (sck0) after busy release. ensure to set wup = 1 after releasing busy and confirming that the sb0 (or sb1) pin has become high level. serial clock csim01 csim00 0 0 1 1 0 1 0 1 3-wire serial i/o mode sbi mode 2-wire serial i/o mode input output input clock to sck0 pin from outside. timer/event counter output (t0) f x /2 4 (375 khz, or 262 khz) * f x /2 3 (750 khz, or 524 khz) * f x /2 6 (93.8 khz, or 65.5 khz) * wup 0 1 irqcsi0 is set upon termination of serial transfer in each mode. used in sbi mode only. irqcsi0 is set only when the address received after bus release matches the slave address register data (wake-up state). sb0/sb1 is high impedance. csim04 0 1 0 1 csim03 0 1 1 csim02 0 1 0 1 operating mode 3-wire serial i/o mode sbi mode 2-wire serial i/o mode bit order of shift register 0 sio0 7C0 ? xa (transferred with msb first) sio0 0C7 ? xa (transferred with lsb first) sio0 7C0 ? xa (transferred with msb first) sio0 7C0 ? xa (transferred with msb first) so0 pin function so0/p02 (cmos output) sb0/p02 n-ch open drain input/output p02 input sb0/p02 n-ch open drain input/output p02 input si0 pin function si0/p03 (input) p03 input sb1/p03 n-ch open drain input/output p03 input sb1/p03 n-ch open drain input/output sck0 pin mode
84 m pd75237 high-level output serial clock output (high-level output) clear condition (coi = 0) set condition (coi = 1) 1 shift register 0 operation serial clock counter irqcsi0 flag so0/sb0, si0/sb1 pins shift operation disabled shift operation enabled clear count operation hold settable dedicated to port 0 functions 0 when the slave address register (sva) data unmatches the shift register 0 data. when the slave address register (sva) data matches the shift register 0 data. coi * fig. 4-40 serial operating mode register 0 (csimo) format (3/3) signal (r) from address comparator * coi read is only valid before serial transfer and after its completion. only undefined value is read during transfer. the coi data written by an 8-bit manipulation instruction is ignored. serial interface operation enable/disable specify bit (w) remarks 1. each mode can be selected by setting csie0, csim03 and csim02. csie0 csim03 csim02 operating mode 0 operation stop mode 10 3-wire serial i/o mode 1 1 0 sbi mode 1 1 1 2-wire serial i/o mode 2. p01/sck0 pin becomes as follows depending on the settings of csie0, csim01 and csim00. csie0 csim01 csim00 p01/sck0 pin status 0 0 0 input port 1 0 0 high impedance 001 010 011 101 110 111 functions in each mode and operations with port 0 csie0
85 m pd75237 remarks 3. clear csie0 during serial transfer using the following procedure. disable interrupt by clearing the interrupt enable flag. clear csie0. ? clear the interrupt request flag. example 1. select fx/2 4 for serial clock and generate serial interrupt irqcsi0 upon termination of each serial transfer and select a serial transfer mode in the sbi mode using the sb0 pin as serial data bus. sel mb15 ; or clr1 mbe mov xa, #10001010b mov csim0, xa ; csim0 ? 10001010b 2. enable serial transfer in accordance with the csim0 contents. sel mb15 ; or clr1 mbe set1 csie0
86 m pd75237 bsye ackd acke ackt cmdd reld cmdt relt 7 6 5 4 3 2 1 0 symbol address sbic fe2h bus release trigger bit (w) command trigger bit (w) bus release detect flag (r) command detect flag (r) acknowledge trigger bit (w) acknowledge enable bit (r/w) acknowledge detect flag (r) busy enable flag (r/w) (b) serial bus interface control register (sbic) fig. 4-41 shows a serial bus interface control register (sbic) format. sbic is an 8-bit register which consists of a serial bus control bit and flags indicating various statuses of input data received from the serial bus. sbic is manipulated using a bit manipulation instruction. it cannot be manipulated using a 4-bit or 8-bit manipulation instruction. read/write operation enable/disable depends on the bit (refer to fig. 4-41 ). reset input clears all bits to 0. note only the following bits can be used in the 3-wire and 2-wire serial i/o modes. ? bus release trigger bit (relt) ........ so0 latch set ? command trigger bit (cmdt) ........ so0 latch clear fig. 4-41 serial bus interface control register (sbic) format (1/3) remarks 1. (r) only read 2. (w) only write 3. (r/w) read/write enabled
87 m pd75237 clearing conditions (reld = 0) setting conditions (reld = 1) bus release signal (rel) detection clearing conditions (cmdd = 0) setting conditions (cmdd = 1) command signal (cmd) detection ackt acke 1 when set before termination of tr ansfer ack is output in synchronization with the 9th clock of sck0. when set after termination of transfer fig. 4-41 serial bus interface control register (sbic) format (2/3) bus release trigger bit (w) bus release signal (rel) trigger output control bit. when set (relt = 1), so0 latch is set (1) and then the relt bit is automatically cleared (0). note do not clear sb0 (or sb1) during serial transfer. be sure to do so before transfer start or after transfer end. command trigger bit (w) command signal (cmd) trigger output control bit. when set (cmdt = 1), so0 latch is cleared (0) and then the cmdt bit is automatically cleared (0). note do not clear sb0 (or sb1) during serial transfer. be sure to do so before transfer start or after transfer end. bus release detect flag (r) transfer start instruction execution reset input a csie0 = 0 (refer to fig. 4-40) sva and sio0 mismatch upon address reception. command detect flag (r) transfer start instruction execution bus release signal (rel) detection a reset input csie0 = 0 (refer to fig. 4-40) acknowledge trigger bit (w) setting this bit after termination of transfer outputs ack in synchronization with the next sck0. after output of ack signal, this bit is automatically cleared (0). note 1. do not set (1) this bit during serial transfer. 2. ackt cannot be cleared by software. 3. when setting ackt, set acke = 0. acknowledge enable bit (r/w) 0 automatic output of acknowledge signal (ack) is disabled (output by ackt enabled). relt cmdt ack is output in synchronization with sck0 just after execution of a set instruction. reld cmdd 4 4
88 m pd75237 fig. 4-41 serial bus interface control register (sbic) format (3/3) acknowledge detect flag (r) transfer start instruction execution reset input busy enable bit (r/w) busy signal automatic output disabled busy signal output stopped at the falling edge of sck0 just after clear instruction execution. 1 busy signal output at the falling edge of sck0 following the acknowledge signal. example 1. output the command signal. sel mb15 ; or clr1 mbe set1 cmdt 2. identify the receive data type by testing reld and cmdd for proper processing. set wup = 1 for this interruput routine so that processing is carried out only in the case of a match address. sel mb15 skf reld ; reld test br !adrs skt cmdd ; cmdd test br !data cmd : ....................................... ; command interpret date : ....................................... ; data processing adrs : ....................................... ; address decode bsye ackd setting conditions (ackd = 1) clearing conditions (ackd = 0) acknowledge signal (ack) detection (at the rising edge of sck0) 0
89 m pd75237 relt cmdt set clr q d clk busy/ack csim0 internal bus address comparator shift register 0 shift clock n-ch open drain output so0 latch (c) shift register 0 (sio0) fig. 4-42 shows a shift register 0 peripheral configuration. sio0 is an 8-bit register which executes parallel-to-serial conversion and carries out serial transmission/reception (shift operation) in synchroni- zation with a serial clock. serial transfer is started by writing data to sio0. in transmission, the data written to sio0 is output to the serial output (so0) or serial data bus (sb0/sb1). in reception, data is read from the serial input (si0) or sb0/sb1 to sio0. this register can be read/written by an 8-bit manipulation instruction. reset input during operation makes the sio0 value undefined. reset input in the standby mode holds the sio0 value. shift operation stops after 8-bit transmission /reception. fig. 4-42 shift register 0 peripheral configuration sio0 read and serial transfer start (write) are enabled at the following timings. ? serial interface operation enable/disable bit (csie0) = 1 except when csie0 is set to 1 after data write to the shift register. ? when the serial clock is masked after 8-bit serial transfer. ? when sck0 is at a high level be sure to write/read data to sio0 when sck0 is at a high level. in the 2-wire serial i/o or sbi mode, the data bus has a configuration that the input pins serve as output pins and vice versa. each output pin has an n-ch open drain configuration. thus, set ffh to sio0 for the device for data reception.
90 m pd75237 (d) slave address register (sva) the slave address register (sva) has the following two functions. only write is enabled for the sva by an 8-bit manipulation instruction. reset input makes the sva value undefined. reset input in the standby mode holds the sva value. ? slave address detection [sbi mode] use this mode to connect the m pd75237 as a slave device to the serial bus. the sva is an 8-bit register for the slave to set the slave address value (own specification number). the master outputs a slave address for particular slave selection to the connected slave. these two date (salve address and sva values output from the master) are compared by an address comparator. when they match, the slave has been selected. in this case, bit 6 (coi) of the serial operating mode register 0 (csim0) is set to 1. note 1. the slave selection or non-selection status is checked by detecting the matching of the slave address received after bus release (reld = 1). use the address match interrupt (irqcsi0) to be normally generated with wup = 1 to detect the matching. thus, detect selection or non-selection by slave address when wup = 1. 2. if selection or non-selection is to be detected without using an interrupt when wup = 0, do so by transmitting/receiving the command preset by a program without using the method of detecting address matching. ? error detection [2-wire serial i/o and sbi modes] when an address, a command and data are to be transmitted using the m pd75237 as the master device or data is to be transmitted using the m pd75237 as the slave device, the sva detects errors. (4) various types of signals table 4-6 gives a list of various types of signals. figs. 4-43 to 4-48 show the various types of signals and flag operation.
91 m pd75237 cmd signal is output to indicate that transmit data is an address. i) transmit data is an ad- dress after rel signal output ii) no rel signal output. transmit data is a com- mand. completion of reception serial reception disabled because of processing serial reception enabed signal name output device timing chart definition output condition effect on flag meaning of signal rising edge of sb0/sb1 when sck0 = 1 falling edge of sb0/sb1 when sck0 = 1 lowClevel signal to be output to sb0/sb1 during one-clock period of sck0 after comple- tion of serial reception [synchronous busy signal] lowClevel signal to be output to sb0/sb1 following the acknowledge signal high- level signal to be output to before serial transfer start or after its compleltion sck0 sb0/sb1 sb0/sb1 d0 d0 9 ack busy ready ready busy ack sck0 sb0/sb1 " h " sck0 sb0/sb1 " h " [synchronous busy output] ? relt set ? cmdt set acke = 1 ackt set ? bsye = 1 bsye = 0 execution of an instruc- tion for data write to sio0 (transfer start command) table 4-6 various types of signals in sbi mode (1/2) ? reld set ? cmdd clear ? cmdd set ? ackd set master master master/ slave slave slave bus release signal (rel) command signal (cmd) acknowledge signal (ack) busy signal (busy) ready signal (ready)
92 m pd75237 table 4-6 various types of signals in sbi mode (2/2) signal name output device timing chart definition output condition effect on flag meaning of signal *1. when wup = 0, irqcsi0 is always set at the rising edge of the 9th clock of sck0. when wup = 1, an address is received. only when the received address matches the slave adress register (sva) value, irqcsi0 is set at the rising edge of the 9th clock of sck0. 2. transfer starts after the busy state is changed to the ready state. 1 2 7 8 sck0 sb0/sb1 sck0 sb0/sb1 1 2 7 8 cmd sck0 sb0/sb1 1 2 7 8 rel cmd 1 2 7 8 9 10 sck0 sb0/sb1 execution of an instruction for data write to sio0 when csie0 = 1 (se- rial transfer start com- mand) *2 synchronous clock to ouput address, command, data, ack signal and synchronous busy signal. address, command and data are transferred by the first eight clocks. 8-bit data to be transferred in synchronization with sck0 af- ter output of rel and cmd signals 8-bit data to be transferred in synchronization with sck0 af- ter output of cmd signal only without rel signal output 8-bit data to be transferred in synchronization with sck0 without output of rel and cmd signals timing of signal output to the serial data bus address value of slave device on the serial bus command and message for the slave device numeric value to be pro- cessed by a slave or mas- ter device irqcsi0 set (rising edge of 9th clock) *1 serial clock (sck0) address (a7 to 0) command (c7 to 0) data (d7 to 0) master master master master/ slave
93 m pd75237 sio0 sck0 reld cmdd 1 2 7 8 d7 d6 d1 d0 when the address matches when the address does not match set after completion of transfer ack signal is output during 1-clock period just after setting when set during this period fig. 4-43 relt, cmdt, reld and cmdd (master) operations fig. 4-44 relt, cmdt, reld and cmdd (slave) operations fig. 4-45 ackt operations note do not set ackt just before termination of transfer. transfer start directive so0 latch sio0 sck0 "h" relt cmdt reld cmdd write to sio0 transfer start directive so0 latch relt (master) cmdt (master) 6 7 8 9 sck0 d2 d1 d0 sb0/sb1 ackt ack
94 m pd75237 fig. 4-46 acke operation (a) when acke = 1 upon completion of transfer (b) when set after completion of transfer (c) when acke = 0 upon completion of transfer (d) when the acke = 1 period is short 1 2 7 8 9 sck0 sb0/sb1 d7 d6 d2 d1 d0 ack acke ack signal is output at the 9th clock 1 2 7 8 9 sck0 sb0/sb1 acke d7 d6 d2 d1 d0 ack signal is not output sck0 sb0/sb1 acke when set and cleared during this period and acke=0 at the falling edge of ack0 ack signal is not output when acke=1 at this point when acke = 0 at this point 6 7 8 9 sck0 sb0/sb1 acke d2 d1 d0 ack ack signal is output during 1-clock period just after setting when set during this period and acke=1 at the falling edge of the next sck0.
95 m pd75237 (c) clear timing with transfer start command during busy (b) when ack signal is output after the 9th clock of sck0 fig. 4-48 bsye operation transfer start transfer start transfer start directive transfer start directive when bsye=1 at this point when reset during this pe- riod and bsye=0 at the fall- ing edge of sck0 fig. 4-47 ackd operations (a) when ack signal is output during the 9th clock period of sck0. transfer start directive 6 7 8 9 sck0 sb0/sb1 ackd d2 d1 d0 sio0 ack 6 7 8 9 sck0 sb0/sb1 ackd sio0 d2 d1 d0 ack 6 7 8 9 sck0 sb0/sb1 bsye ack busy 6 7 8 9 sck0 sb0/sb1 ackd sio0 d2 d1 d0 d7 d6 ack busy
96 m pd75237 (5) serial interface (channel 0) operations (a) operation stop mode the operation stop mode is used when serial transfer is not carried out. power consumption is decreased in this mode. in this mode, shift register 0 does not carry out shift operation and thus can be used as a normal 8- bit register. reset input sets the operation stop mode. the p02/so0/sb0 pin and p03/si0/sb1 pins are fixed to the input port. p01/sck0 can be used as an input port by setting serial operating mode register 0. (b) 3-wire serial i/o mode operations the 3-wire serial i/o mode allows connection with the methods employed with another 75x series and 78k series. communication is carried out using three lines of serial clock (sck0), serial output (so0) and serial input (si0). (i) communication the 3-wire serial i/o mode is used for data transmission and reception in 8-bit units. bit-wise data transmission/reception is carried out in synchronization with the serial clock. shift operation of shift register 0 is carried out at the falling edge of serial clock (sck0). transmit data is held at the so0 latch and output from the so0 pin. receive data input to the si0 pin is latched to the shift register 0 at the rising edge of sck0. shift register 0 operation automatically stops upon termination of 8-bit transfer and the interrupt request flag (irqcsi0) is set. fig. 4-49 3-wire serial i/o mode timing sck0 si0 so0 irqcsi0 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 1 2 3 4 5 6 7 8 transfer start at the falling edge of sck0 execution of data write instruction to sio0 (transfer start directive) end of transfer
97 m pd75237 the so0 pin serves as cmos output to output the so0 latch status. thus, the so0 pin output status can be manipulated by setting the relt and cmdt bits. however, do not carry out this manipulation during serial transfer. the sck0 pin can control the output status by manipulating the p01 output latch in the output mode (internal system clock mode) (refer to 4.9 (7) sck0 pin output manipulation ). (ii) msb/lsb first switching the 3-wire serial i/o mode has a function which allows msb-first or lsb-first transfer to be selected. fig. 4-50 shows shift register 0 (sio0) and internal bus configurations. as shown in fig. 4-50, msb/ lsb can be reversed and read/written. msb/lsb first switching can be specified by bit 2 of serial operating mode register 0 (csim0). fig. 4-50 transfer bit switching circuit first bit switching is realized by switching the bit order of data write to the shift register 0 (sio0). the sio0 shift order remains the same. thus, switch the msb/lsb first bit before writing data to the shift register 0. sck0 so0 si0 d q 7 6 1 0 internal bus lsb first msb first read/write gate read/write gate so0 latch shift register 0 (sio0)
98 m pd75237 (c) 2-wire serial i/o mode operations the 2-wire serial i/o mode can be applied to any communication format by program. communication is basically carried out using two lines of serial clock (sck0) and serial data input/ output (sb0 or sb1). (i) communication the 2-wire serial i/o mode is used for data transmission and reception in 8-bit units. bit-wise data transmission/reception is carried out in synchronization with the serial clock. shift operation of shift register 0 is carried out at the falling edge of serial clock (sck0). transmit data is held at the so0 latch and output from the sb0/p02 (or sb1/p03) pin with msb set as the first bit. receive data input from the sb0 (or sb1) pin at the sck0 rising edge is latched to the shift register 0. upon termination of 8-bit transfer, the shift register 0 operation automatically stops and the interrupt request flag (irqcsi0) is set. fig. 4-51 2-wire serial i/o mode timing since the pin specified for the serial data bus of the sb0 (or sb1) pin becomes an n-ch open drain input/ output, it must be pulled up externally. since the sb0 (or sb1) pin outputs the so0 latch status, the sb0 (or sb1) pin status can be manipulated by setting the relt and cmdt bits. however, do not carry out this operation during serial transfer. the sck0 pin can control the output status by manipulating the p01 output latch in the output mode (internal system clock mode) (refer to 4.9 (7) sck0 pin output manipulation ). sck0 sb0/sb1 irqcsi0 1 2 3 4 5 6 7 8 d7 d6 d5 d4 d3 d2 d1 d0 execution of data write instruction to sio0 (transfer start directive) transfer start at the falling edge of sck0 end of transfer
99 m pd75237 (d) sbi mode operations sbi (serial bus interface) is a high-speed serial interface method compliant with the nec serial bus format. sbi is a single master high-speed serial bus based on the format with bus configuration functions added to the clocked serial synchronization i/o method so that communication can be carried out with two or more devices using two signal conductors. thus, the number of ports used and that of wires on the board can be decreased for serial bus configuration with two or more microcomputers and peripheral ics. fig. 4-52 shows the sbi system configuration example. fig. 4-52 sbi system configuration example note 1. because in the sbi the serial data bus pin sb0 (or sb1) is an open drain output, the serial data bus line is wired-or. a pull-up resistor is necessary for the serial data bus line. 2. for master/slave replacement, a pull-up resistor is necessary for sck0 because serial clock line (sck0) input/output switching is executed asynchronously between the master and slave. address 1 address 2 address n sb0 (ab1) sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 slave ic slave cpu master cpu m pd75237 slave cpu m pd75237
100 m pd75237 sck0 sb0/sb1 8 9 a7 a0 ack busy sck0 sb0/sb1 sck0 sb0/sb1 9 c7 c0 ack busy ready ack busy ready 8 9 d7 d0 (i) sbi functions ? address/command/data identification sbi distinguishes serial data between address, command and data. ? chip select function by address the master executes slave chip selection by address transmission. ? wake-up function the slave can easily make an address receive judgment (chip select judgment) using the wake- up function (which can be set/cancelled by software). when the wake-up function is set, an interrupt (irqcsi0) is generated upon reception of a match address. thus, when communication is carried out with two or more devices, cpus except the selected slave can operate irrespective of serial communication. ? acknowledge signal (ack) control function acknowledge signal is controlled to confirm serial data reception. ? busy signal (busy) control function the busy signal is controlled to inform the slave busy status. fig. 4-53 sbi transfer timing bus release signal command transfer command signal data transfer address transfer
101 m pd75237 (ii) communication in the sbi, the master normally selects one slave device for communication target from among two or more devices by outputting an address to the serial bus. after the communication target device has been determined, serial communication is achieved through command and data transmission/reception between the master and slave devices. figs. 4-54 to 4-57 show the timing charts of data communication. in the sbi mode, shift operation of shift register 0 is carried out at the falling edge of serial clock (sck0) and transmit data is output from the sb0/p02 or sb1/p03 pin with msb as the first bit. receive data input to the sb0 (or sb1) pin at the rising edge of sck0 is latched to the shift register 0.
102 m pd75237 fig. 4-54 address transmission from master device to slave device (wup = 1) 1 2 3 4 5 6 7 8 9 a7 a6 a5 a4 a3 a2 a1 a0 busy ready wup ? 0 ack master device processing (transmitter side) program processing hardware operation transfer line sck0 pin sb0 pin slave device processing (receiver side) program processing hardware operation write to sio0 cmdt set cmdt set relt set serial transmission interrupt servicing (preparation for the next serial transfer) irqcsi0 generation ackd set sck0 stop address serial reception cmdd set cmdd clear cmdd set reld set irqcsi0 generation ack output busy output busy clear busy clear ackt set (when sva = sio0)
103 m pd75237 fig. 4-55 command transmission from master device to slave device 1 2 3 4 5 6 7 8 9 c7 c6 c5 c4 c3 c2 c1 c0 busy ready ack master device processing (transmitter side) program processing hardware operation transfer line sck0 pin sb0 pin slave device processing (receiver side) program processing hardware operation cmdd set serial reception irqcsi0 generation ack output busy output busy clear busy clear ackt set command analysis sio0 read cmdt set write to sio0 serial transmission ackd set sck0 stop irqcsi0 generation interrupt servicing (preparation for the next serial transfer) command
104 m pd75237 fig. 4-56 data transmission from master device to slave device 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 d0 ack busy ready master device processing (transmitter side) program processing hardware operation transfer line sck0 pin sb0 pin slave device processing (receiver side) program processing hardware operation serial reception irqcsi0 generation busy clear ack output busy output busy clear ackt set sio0 read ackd set sck0 set irqcsi0 generation interrupt servicing (preparation for the next serial transfer) serial transmission write to sio0 data
105 m pd75237 fig. 4-57 data transmission from slave device to master device h 1 2 3 4 5 6 7 8 9 1 2 d6 d7 d5 d4 d3 d2 d1 d0 d6 d7 ack busy busy ready ready transfer line sck0 pin sb0 pin slave device processing (transmitter side) program processing hardware operation irqcsi0 generation ackd output busy output busy clear master device processing (receiver side) program processing hardware operation write to sio0 busy clear serial transmission write to sio0 irqcsi0 generation ack output serial reception receive data processing ackt set sio0 read ffh write to sio0 ffh write to sio0 serial reception data sck0 stop
106 m pd75237 (6) transfer start in each mode in each of the 3-wire and 2-wire serial i/o modes and the sbi mode, serial transfer is started by setting transfer data to the shift register 0 (sio0) under the following two conditions. ? serial interface operation enable/disable bit (csie0) = 1 ? the internal serial clock has stopped or sck0 is at high level after 8-bit serial transfer. note transfer does not start if csie0 is set to 1 after data is written to the shift register 0. serial transfer automatically stops and the interrupt request flag (irqcsi0) is set upon termination of 8-bit transfer. [2-wire serial i/o mode transfer start precautions] note because it is necessary to turn off the n-ch transistor upon data reception, write ffh to sio0 in advance. [sbi mode transfer start precautions] note 1. because it is necessary to turn off the n-ch transistor upon data reception, write ffh to sio0 in advance. however, in the case of wake-up function specify bit (wup) = 1, the n-ch transistor remains off. thus, it is not necessary to write ffh to sio0 before reception. 2. if data is written to sio0 when the slave is busy, the written data is not lost. transfer starts when the busy status is cancelled and the sb0 (or sb1) input becomes high level (ready status). example the ram data specified by the hl register is transferred to sio0 and simultaneously the sio0 data is fetched into the accumulator and serial transfer is started. mov xa, @hl ; transmit data is fetched from the ram. sel mb15 ; or clr1 mbe xch xa, sio0 ; transmit data is exchanged with receive data and transfer is started.
107 m pd75237 (7) sck0 pin output manipulation because the sck0/p01 pin incorporates an output latch, static output is possible by software in addition to normal serial clocks. p01 output latch manipulation enables to set any number of sck0 by software (so0/sb0/sb1 pin is controlled by the relt and cmdt bits of sbic). sck0/p01 pin output manipulation is described below. set the serial operating mode register 0 (csim0) (sck0 pin: output mode, serial operation: enabled). while serial transfer is stopped, sck0 from the serial clock control circuit remains 1. manipulate the p01 output latch by a bit manipulation instruction. example 1 clock output to sck0/p01 pin by software. sel mb15 ; or clr1 mbe mov xa,#10000011b ; sck0(f x /2 3 ), output mode mov csim0,xa clr1 0ff0h.1 ; sck0/p01 ? 0 set1 0ff0h.1 ; sck0/p01 ? 1 fig. 4-58 sck0/p01 pin configuration the p01 output latch is mapped at bit 1 of address ff0h. reset signal generation sets the p01 output latch to 1. note 1. it is necessary to set the p01 output latch to 1 during normal serial transfer. 2. the p01 output latch address cannot be set by port0.1 as shown below. describe address (0ff0h.1) directly for the operand. however, it is necessary to preset mbe = 0 or (mbe = 1 and mbs = 15) for instruction execution. clr1 port0.1 set1 port0.1 clr1 0ff0h.1 set1 0ff0h.1 use disabled use enabled p01/sck0 sck0 p01 output latch csie0 = 1 and csim01 and csim00 00 address ff0h.1 to internal circuit from serial clock control circuit
108 m pd75237 (8) serial interface (channel 1) functions the following two modes are available to the m pd75237 serial interface (channel 1). the summary of each mode is shown below. ? operation stop mode the operation stop mode is used when serial transfer is not carried out. power consumption is decreased in this mode. ? 3-wire serial i/o mode 8-bit data transfer is carried out using three lines of serial clock (sck1), serial output (so1) and serial input (si1). in the 3-wire serial i/o mode which enables simultaneous transmission and reception, the data transfer rate is improved. the first bit of 8-bit data for serial transfer is fixed to msb. in the 3-wire serial i/o mode, channel 1 can be connected to the 75x series, 78k series and various types of peripheral i/o devices. (9) serial interface (channel 1) configuration fig. 4-59 shows a serial interface (channel 1) block diagram. h
109 m pd75237 fig. 4-59 serial interface (channel 1) block diagram 8 8 0 csim1 fx/2 3 fx/2 4 r s q p83/si1 p82/so1 p81/sck1 bit0 7 sio1 bit7 internal bus sio1 write signal (serial start signal) bit mani- pulation serial operating mode register (8) bit mani- pulation serial transfer end flag (eot) serial clock selector set clear clear serial clock counter (3) overflow shift register 1 (8)
110 m pd75237 (10) serial interface (channel 1) register functions (a) serial operating mode register 1 (csim1) fig. 4-60 shows a serial operating mode register 1 (csim1) format. csim1 is an 8-bit register to specify the serial interface (channel 1) operating mode and serial clock. it is manipulated by an 8-bit memory manipulation instruction. the higher 1 bit can be manipulated bit-wise. use each bit name for bit manipulation. reset input clears all bits to 0. fig. 4-60 serial operating mode register 1 format serial clock select bit (w) serial interface operation enable/disable specify bit (w) csim11 csim10 serial clock 3-wire serial i/o mode sck pin mode 0 0 external input clock to sck1 pin input 0 1 setting disabled 10f x /2 4 (375 khz, or 262 khz) * 11f x /2 3 (750 khz, or 524 khz) * shift register 1 operation serial clock counter irqcsi flag so1 and si1 pins 0 shift operation disabled clear hold dedicated to port 8 functions 1 shift operation enabled count operation settable functions in each mode and operations with port 8 csie1 * values in parentheses are when f x = 6.0 mhz or f x = 4.19 mhz. note be sure to write 0 to bits 2 to 6 of the serial operating mode register. h h 76543210 csie1 0 0 0 0 0 csim11 csim10 address fc8h symbol csim1 output
111 m pd75237 (b) shift register 1 (sio1) sio1 is an 8-bit register which executes parallel to serial conversion and carries out serial transmission/ reception (shift operation) in synchronization with a serial clock. serial transfer is started by writing data to sio1. in transmission, the data written to sio1 is output to the serial output (so1). in reception, data is read from the serial input (si1) to sio1. this register can be read/written by an 8-bit manipulation instruction. reset input during operation makes the sio1 value undefined. reset input in the standby mode holds the sio1 value. shift operation stops after 8-bit transmission/reception. sio1 read and serial transfer start (write) are enabled at the following timings. ? serial interface operation enable/disable bit (csie1) = 1 except when csie1 is set to 1 after data write to the shift register. ? when the serial clock is masked after 8-bit serial transfer. ? when sck1 is at a high level.
112 m pd75237 (11) serial interface (channel 1) operations (a) operation stop mode the operation stop mode is used when serial transfer is not carried out. power consumption is decreased in this mode. in this mode, shift register 1 does not carry out shift operation and thus can be used as a normal 8- bit register. reset input sets the operation stop mode. the p82/so1 pin and p83/si1 pin are fixed to the input port. p81/sck1 can be used as an input port by setting serial operating mode register 1. (b) 3-wire serial i/o mode operations the 3-wire serial i/o mode allows connection with the methods employed with another 75x series and 78k series, etc. communication is carried out using three lines of serial clock (sck1), serial output (so1) and serial input (si1). the 3-wire serial i/o mode is used for data transmission and reception in 8-bit units. bit-wise data transmission/reception is carried out in synchronization with the serial clock. shift operation of shift register 1 is carried out at the falling edge of serial clock (sck1). transmit data is held at the so1 latch and output from the so1 pin. receive data input to the si1 pin is latched to the shift register 1 at the rising edge of sck1. shift register 1 operation automatically stops upon termination of 8-bit transfer and the serial transfer end flag (eot) is set. fig. 4-61 3-wire serial i/o mode timing sck1 si1 so1 eot do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 1 2 3 4 5 6 7 8 transfer start at the falling edge of sck1 execution of data write instruction to sio1 (transfer start directive) end of transfer
113 m pd75237 4.10 a/d converter the m pd75237 incorporates an 8-bit resolution a/d converter with 8-channel analog inputs (an0 to an7). the a/d converter employs successive approximation. (1) a/d converter configuration fig. 4-62 shows an a/d converter configuration. fig. 4-62 a/d converter block diagram an0 an1 an2 an3 an4 an5 an6 an7 av ss av ref r/2 r r r r/2 + ? 8 8 0 adm6 adm5 adm4 soc eoc 0 0 8 internal bus control circuit sa register (8) comparator simple & hold circuit tap decoder multiplexer
114 m pd75237 (2) a/d converter pin functions (a) an0 to an7 these are 8-channel analog signal input pins to the a/d converter. an analog signal to undergo a/ d conversion is input to these pins. the a/d converter incorporates a sample hold circuit. the analog input voltage is internally held during a/d conversion. (b) av ref and av ss the a/d converter reference voltage is input to these pins. signals input to an0 to an7 are converted to digital signals in accordance with the voltage applied between av ref and av ss . av ss should always be set to the same voltage as v ss . (c) av dd av dd is a power supply pin for the a/d converter. it should be set to the same voltage as v dd , even when the a/d converter is not used, or in standby mode. (3) a/d conversion mode register the a/d conversion mode register (adm) is an 8-bit register for analog input channel selection, conversion start command and conversion end detection (see fig. 4-63 ). the adm is set by an 8-bit manipulation instruction. the bit 2 conversion end detection flag (eoc) and the bit 3 conversion start command bit (soc) can be manipulated in bit units. reset input initializes the adm to 04h (only eoc is set to 1 and all other bits are cleared to 0). h
115 m pd75237 0 being converted 1 end of conversion eoc soc setting this bit starts a/d conversion. upon conversion start, this bit is automati- cally cleared. adm6 adm5 adm4 analog channel 0 0 0 an0 0 0 1 an1 0 1 0 an2 0 1 1 an3 1 0 0 an4 1 0 1 an5 1 1 0 an6 1 1 1 an7 76543210 0 adm6 adm5 adm4 soc eoc 0 0 symbol adm address fd8h fig. 4-63 a/d conversion mode register format note a/d conversion starts with a maximum delay of 2 4 /f x sec (2.67 m s: at 6.0 mhz operation)* after soc setting (refer to 4.10 (5) a/d converter operations). * 3.81 m s at 4.19 mhz operation conversion end detection flag conversion start directive bit analog channel select bit
116 m pd75237 (4) sa register (sa) the sa register (successive approximation register) is an 8-bit register to store the result of a/d conversion by successive approximation. the sa register is read by an 8-bit manipulation instruction. data cannot be written to this register by software. reset input sets the sa register undefined. (5) a/d converter operations the analog input signal to undergo a/d conversion is specified by setting bits 6, 5 and 4 (adm6, 5 and 4) of the a/d conversion mode register. a/d conversion is started by setting (1) adm bit 3 (soc). soc is automatically cleared (0) after the setting. a/d conversion is executed using successive approximation by hardware and the 8-bit conversion result data is stored into the sa register. upon termination of conversion, bit 2 (eoc) of adm is set (1). fig. 4-64 is an a/d conversion timing chart. use the a/d converter as follows. select the analog input channel (adm 6, 5 and 4 setting). instruct a/d conversion start (soc setting). a wait for a/d conversion to terminate (wait for eoc to be set or wait with a software timer). read the a/d conversion result (sa register reading). note 1. and can be carried out simultaneously. 2. a maximum delay of 2 4 /f x sec (2.67 m s: at 6.0 mhz operation)* occurs from a/d conversion start to eoc clear after soc setting. thus, test eoc after the passage of time indicated in table 4-7 after soc setting. table 4-7 shows a/d conversion times as well. * 3.81 m s at 4.19 mhz operation table 4-7 scc and pcc settings scc and pcc set value a/d conversion time wait not required 1 machine cycle 2 machine cycles 4 machine cycles wait not required wait time till eoc test after soc setting wait time till the end of a/d conver- sion after soc setting 3 machine cycles 11 machine cycles 21 machine cycles 42 machine cycles wait not required scc3 scc0 pcc1 pcc0 00 01 10 11 01 1 168/f x (28 m s : at 6.0 mhz operation) * conversion op- eration stopped * 40.1 m s at 4.19 mhz operation remarks x : dont care 00 4
117 m pd75237 fig. 4-64 a/d conversion timing chart (6) standby mode precautions the a/d converter operates with the main system clock. thus, the converter operation stops in the stop mode or in the halt mode with the subsystem clock. in this case also, current flows to the av ref pin. thus, it is necessary to cut the current to decrease the power consumption of the whole system. the p21 pin has a more improved driving capacity than any other port and so can directly supply a voltage to the av ref pin. however, in this case, the actual av ref voltage have no accuracy. thus, the conversion value itself has no accuracy and can only be used for relative comparison. in the standby mode, power consumption can be decreased by generating a low level to p21. the av dd pin should be set to the same voltage as v dd in the standby mode. fig. 4-65 av ref pin processing in standby mode 168/f x sec (28 m s: at 6.0 mhz operation) * av ref av ss av ref v dd p21 v dd m pd75237 p-ch large av ref = v dd . . soc eoc previous data sa register time until a/d conversion start (2 /f x sec max.) 4 a/d conversion undefined conversion result sampling * 40.1 m s at 4.19 mhz operation
118 m pd75237 av ref av dd v ss v dd an0 - an7 av ss v dd c = 100 ?1000pf v dd if noise larger than v dd or smaller than v ss may be generated, clamp with a diode having a small v f (0.3 v or less). (7) others and operating precautions (a) an0 to an7 input range use an0 to an7 input voltages in the specified range. if a voltage larger than v dd or smaller than v ss is input (if in the absolute maximum range), the conversion value of the channel becomes undefined and may affect the conversion values of other channels. (b) countermeasures against noise to maintain 8-bit accuracy, extra attention must be paid to noise in the av ref and an0 to an7 pins. the higher the analog input source output impedance becomes the more the noise effect becomes. to prevent that from occurring, mount c externally as shown in fig. 4-66. fig. 4-66 analog input pin processing (c) an4/p90 to an7/p93 pins analog inputs an4 to an7 also serve as the input port (port9) pin. do not execute a port9 input instruction during a/d conversion with any one of an4 to an7 selected. the conversion accuracy may be deteriorated. if a digital pulse is applied to a pin contiguous to the pin undergoing a/d conversion, the expected a/ d conversion value may not be obtained because of coupling noise. thus, do not apply pulses to such pins. (d) av dd pin av dd pin should be set to the same voltage even when a/d converter is not used, or in standby mode. m pd75237 h h
119 m pd75237 4.11 bit sequential buffer : 16 bits the bit sequential buffer (bsb0 to bsb3) is a special data memory for bit manipulation. since this buffer can easily carry out bit manipulation by sequentially changing address and bit specification, it is useful to process data having long bit lengths in bit units. this data memory consists of 16 bits and can execute the pmem.@l addressing of bit manipulation instructions. thus, it can indirectly specify bits with the l register. in this case, processing can be carried out by sequentially shifting the specified bit by simply incrementing/decrementing the l register in the program loop. fig. 4-67 bit sequential buffer format remarks in pmem.@l addressing, the specified bit shifts in accordance with the l register. the bit sequential buffer can be operated irrespective of mbe or mbs specification. data manipulation is also possible by direct addressing. 1-, 4- and 8-bit direct addressing can be combined with pmem.@l addressing for applications to continuous 1-bit data input/output. in the case of 8-bit manipulation, the most and least significant 8 bits each are manipulated by specifying bsb0 and bsb2, respectively. 4.12 fip controller/driver (1) fip controller/driver configuration the m pd75237 incorporates a display controller which automatically generates the digit and segment signals by reading the display data memory contents by carrying out dma operation and a high-voltage output buffer which can directly drive the fluorescent display tube (fip). the fip controller/driver configuration is shown in fig. 4-68. note the fip controller/driver can only operate at high and intermediate speeds (pcc = 0011b or 0010b) of the main system clock (scc.0 = 0). it may malfunction with any other clock or in the standby mode. thus, be sure to stop fip controller operation (dspm.3 = 0) and then shift the unit to any other clock mode or the standby mode. bsb3 bsb2 bsb1 bsb0 fc3h fc2h fc1h fc0h 3 2 10 3 2 10 32 10 3 210 address bit symbol l=f l register l=c l=b l=7 l=8 l=3 l=4 l=0 decs l incs l
120 m pd75237 fig. 4-68 fip controller/driver block diagram 4/8 4/8 4 4 4 8 8 8 8 10 12 4 4 4 4 4 4 2 10 2 2 2 10 8 10 intks v load t0-t9 4 s12/t13/p150/ph0- s15/t10/p153/ph3 s10/t15/p142- s11/t14/p143 s0/p120- s9/p141 internal bus static mode register b display data memory (32 4 bits) key scan register (ks2) segment data latch (8) high-voltage output buffer s16/p100- s23/p113 selector selector segment data latch (16) display data memory (64 4 bits) key scan registers (ks0, ks1) port h digit signal generator irqks set signal key scan flag (ksf) static mode register a key scan flag (ksf) display mode register digit select register dimmer select register high-voltage output buffer
121 m pd75237 (2) fip controller/driver functions the fip controller/driver built in the m pd75237 has the following functions: (a) segment signal output (dma operation) and automatic digit signal output are possible by automatic read of display data. (b) the fip with 9 to 24 segments and 9 to 16 digits (up to a total of 34 display outputs) can be controlled using the display mode register (dspm), digit select register (digs), static mode register a (stata) and static mode register b (statb). (c) output not used for dynamic display can be used for static output or output port. (d) 8 brightness levels can be adjusted using the dimmer function. (e) hardware is incorporated for key scan application. ? key scan interrupt (irqks) generation (key scan timing detection) ? key scan data output from segment output is possible with the key scan buffers (ks0, ks1 and ks2). (f) high-voltage output pin (40 v) capable of directly driving fip. ? segment output pins (s0 to s9, s16 to s23) : v od = 40 v, i od = 3 ma ? digit output pins (t0 to t15) : v od = 40 v, i od = 15 ma (g) display output pin mask option ? t0 to t9 and s0 to s15 can incorporate a pull-down resistor in bit units to v load . ? s16 to s23 can incorporate a pull-down resistor in bit units to v load or v ss . determine in 8-bit units whether a pull-down resistor should be incorporated to v load or v ss . (3) display output function differences between m pd75237 and m pd75216a/ m pd75217 table 4-8 shows display output function differences between m pd75237 and m pd75216a/ m pd75217. table 4-8 display output function differences between m pd75237 and m pd75216a/ m pd75217 high-voltage output display fip output total : 34 outputs segment output : 9 to 24 outputs digit output : 9 to 16 outputs fip output total : 26 outputs segment output : 9 to 16 outputs digit output : 9 to 16 outputs 1a0h to 1ffh s0 to s23 (port10 to port15) display data area output dual-function pin 1c0h to 1ffh ks0 to ks2 key scan register s12 to s15 (porth) ks0, ks1 m pd75237 m pd75216a, 75217
122 m pd75237 fig. 4-69 fip controller operation timing n : digit select register set value t dsp : 1 display cycle t cyt : display period (t cyt = t dsp (n + 2)) t dig : digit signal pulse width variable at 8 levels using a dimmer select register = 171 m s: at 6.0 mhz operation *1 or 2048 f x 1024 = 341 m s: at 6.0 mhz operation *2 f x *1. 244 m s at 4.19 mhz operation 2. 489 m s at 4.19 mhz operation t cyt t dsp t ks t dig t0 t1 t2 tn changeable any time key scan timing irqks generation 1 display cycle segment data key scan flag (ksf)
123 m pd75237 3210 dspm3 dspm2 dspm1 dspm0 (4) display mode register (dspm) the display mode register (dspm) is a 4-bit register to enable/disable display operation and to specify the number of display segments. its format is shown in fig. 4-70. the display mode register is set by the 4-bit memory manipulation instruction. when setting the standby mode (stop mode, halt mode) or operating the dspm with the subsystem clock (f xt ), stop the display operation by presetting dspm.3 to 0. reset input clears all bits to 0. fig. 4-70 display mode register format dspm2 dspm1 dspm0 number of display segments 0 0 0 9 segments (+ 8 segments) 0 0 1 10 segments (+ 8 segments) 0 1 0 11 segments (+ 8 segments) 0 1 1 12 segments (+ 8 segments) 1 0 0 13 segments (+ 8 segments) 1 0 1 14 segments (+ 8 segments) 1 1 0 15 segments (+ 8 segments) 1 1 1 16 segments (+ 8 segments) remarks values when s16 to s23 are set to the dynamic mode by statb are in parentheses. 0 display stopped 1 display enabled note 0 to 7 cannot be set in n. (5) digit select register (digs) the digit select register (digs) is a 4-bit register to specify the number of digits to be displayed. its format is shown in fig. 4-71. digs is set by the 4-bit memory manipulation instruction. the number of digits to be displayed can be set in the range from 9 to 16 by digs setting. the value of 8-digit or less cannot be selected. reset input initializes digs to 1000b and selects 9-digit display. fig. 4-71 digit select register format digs0 to 3 set value no. of digits to be displayed n ( = 8 to 15) n + 1 address f88h symbol dspm dspm3 symbol digs address f8ah 3210 digs3 digs2 digs1 digs0 display segment number specify bit display operation enable/disable bit
124 m pd75237 (6) dimmer select register (dims) the dimmer select register (dims) is a 4-bit register to specify the digit signal cut width to prevent display light emission from leaking and to maintain the dimmer (brightness adjustment) function. it is also used to select the display cycle (t dsp ). the dims format is shown in fig. 4-72. the dims is set by the 4-bit memory manipulation instruction. the display cycle of 341 m s: at 6.0 mhz operation *1 is normally selected with dims.0 set to 1 to minimize light emission leakage. because if the number of digits to be displayed increases, the display period becomes equivalent to the commercial power supply frequency and display flickers, select 171 m s: at 6.0 mh z operation *2 . if any light emission leakage occurs, adjust the digit signal cut width with dims.1 to dims.3. reset input clears all bits to 0. fig. 4-72 dimmer select register format dims3 dims2 dims1 dims0 f x dims3 dims2 dims1 digit signal cut width 0 0 0 1/16 0 0 1 2/16 0 1 0 4/16 0 1 1 6/16 1 0 0 8/16 1 0 1 10/16 1 1 0 12/16 1 1 1 14/16 address f89h symbol dims digit signal cut width specify bit display cycle specify bit dims0 1 0 sets 1024 as one display cycle (1 cycle = 171 m s:6.0 mhz) *1 sets f x 2048 as one display cycle (1 cycle = 341 m s:6.0 mhz) *2 *1. 244 m s at 4.19 mhz operation 2. 489 m s at 4.19 mhz operation *1. 489 m s at 4.19 mhz operation 2. 244 m s at 4.19 mhz operation
125 m pd75237 (7) static mode register the static mode register is intended to specify the static output/dynamic output of the segment output pin. there are two types of static mode registers: static mode register a, static mode register b. figs. 4-73 and 4-74 show their formats, respectively. these two types of static mode registers are set by an 8-bit manipulation instruction. reset input clears all bits to 0. (a) static mode register a (stata) static mode register a (stata) is intended to specify the static output/dynamic output of the s0/p120 to s15/p153/t10/ph3 pins. fig. 4-73 static mode register a (stata) 76543210 0 0 0 0 stata3 stata2 stata1 stata0 stata3 stata2 stata1 stata0 s0 to s15 pins output status s0 to s15 become dynamic output. the numbers of segments and digits are set by dspm and digs. s0 to s15 become static output. perform static data output using an out- put instruction for ports 12 to 15. these pins are not affected by the dspm.3 value. symbol stata address fd6h note it is not possible to set some of the s0 to s15 pins to dynamic output and the remaining pins to static output. 0000 1111 s0 to s15 pin stactic output/dynamic output select bit
126 m pd75237 (b) static mode register b (statb) static mode register b (statb) is intended to specify the static output/dynamic output of the s16/p100 to s23/p113 pins. fig. 4-74 static mode register b (statb) 76543210 0 0 statb5 statb4 0 0 0 0 s16 to s23 pins output status 00 static output. perform static data output using an output instruction for ports 10 and 11. these pins are not affected by the dspm.3 value. 11 note it is not possible to set some of the s16 to s23 pins to dynamic output and the remaining pins to static output. symbol statb address fd4h statb5 statb4 s16 to s23 pin static output/dynamic output select bit dynamic output. dynamic output is generated in accor- dance with 1a0h to 1bdh contents.
127 m pd75237 (8) display mode selection the numbers of segments and digits which can be displayed using the built-in fip controller/driver depend on the display mode. fig. 4-75 shows a display mode selection diagram. fig. 4-75 display mode selection diagram remarks the circled modes with shading are those expanded from the m pd75216a and m pd75217. 0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 digit number selection 9-segment mode 10-segment mode 11-segment mode 12-segment mode 13-segment mode 14-segment mode 15-segment mode 16-segment mode 17-segment mode 18-segment mode 19-segment mode 20-segment mode 21-segment mode 22-segment mode 23-segment mode 24-segment mode segment number selection
128 m pd75237 key scan register (9) display data memory the display data memory is an area storing the displayed segment data and is mapped at addresses 1a0h to 1ffh of the data memory. display data is automatically read by a display controller (dma operation). the areas not used for display can be used as normal data memory. display data operation is carried out by a data memory manipulation instruction. data manipulation is possible in 1-, 4- and 8-bit units. only even addressed can be specified for 8-bit manipulation instruction execution. addresses 1fch to 1ffh, 1beh and 1bfh of the display data memory also serve as key scan registers (ks0, ks1 and ks2). table 4-9 data memories which also serve as key scan registers data memory which also serves as key scan register ks0 1fch, 1fdh ks1 1feh, 1ffh ks2 1beh, 1bfh note extra caution is necessary when transferring a program developed for the m pd75237 to one for the m pd75216a and m pd75217 because a maximum of 16 segments are displayed and no data memory is incorporated at addresses (1a0h + 4n and 1a1h + 4n) in the case of the m pd75216a and m pd75217.
129 m pd75237 3 0 3 0 3 0 3 0 3 0 3 0 1a1h 1a0h 1c3h 1c2h 1c1h 1c0h 1a3h 1a2h 1c7h 1c6h 1c5h 1c4h 1a5h 1a4h 1cbh 1cah 1c9h 1c8h 1a7h 1a6h 1cfh 1ceh 1cdh 1cch 1a9h 1a8h 1d3h 1d2h 1d1h 1d0h 1abh 1aah 1d7h 1d6h 1d5h 1d4h 1adh 1ach 1dbh 1dah 1d9h 1d8h 1afh 1aeh 1dfh 1deh 1ddh 1dch 1b1h 1b0h 1e3h 1e2h 1e1h 1e0h 1b3h 1b2h 1e7h 1e6h 1e5h 1e4h 1b5h 1b4h 1ebh 1eah 1e9h 1e8h 1b7h 1b6h 1efh 1eeh 1edh 1ech 1b9h 1b8h 1f3h 1f2h 1f1h 1f0h 1bbh 1bah 1f7h 1f6h 1f5h 1f4h 1bdh 1bch 1fbh 1fah 1f9h 1f8h 1bfh 1beh(ks2) 1ffh 1feh(ks1) 1fdh 1fch(ks0) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 tks ks0 ks1 ks2 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 t10 t11 t12 t13 t14 t15 ph3 ph2 ph1 ph0 24-segment mode 23-segment mode 22-segment mode 21-segment mode 20-segment mode 19-segment mode 18-segment mode 17-segment mode 16-segment mode 15-segment mode 14-segment mode 13-segment mode 12-segment mode 11-segment mode 10-segment mode 9-segment mode timing output display data memory key scan data segment output timing output port h output (when specified by digit select register) (when none of segment output and timing output are used) bit fig. 4-76 display data memory contents and segment outputs
130 m pd75237 (10) key scan registers (ks0, ks1 and ks2) the key scan registers (ks0, ks1 and ks2) are used to set the segment output data in the key scan timing mapped in the part of the display data memory (addresses 1fch, 1fdh, 1feh, 1ffh, 1beh and 1bfh). ks0, ks1 and ks2 are 8-bit registers and are normally manipulated by an 8-bit manipulation instruction (the lower 4 bits can be manipulated bit-wise or in 4-bit units). data set to ks0, ks1 and ks2 is output from the segment output pin at the key scan timing. during the key scan timing the segment output data can be immediately changed by rewriting ks0, ks1 and ks2. key scan can be performed using the segment output. (11) key scan flag (ksf) the key scan flag is set (1) during the key scan timing and is automatically reset (0) in all other timings. the ksf is mapped at bit 3 of address f8ah and is bit-wise testable. no write is possible. whether the ksp is at the key scan timing can be checked by testing it. thus, it is possible to check whether key input data is correct or not.
131 m pd75237 5. interrupt functions the m pd75237 has eight types of interrupt sources and can generate multiple interrupts with priority order. it is also equipped with two types of test sources. int2 is an edge detected testable input. table 5-1 interrupt source types *1. interrupt order is priority order to be applied when two or more interrupt requests are generated simulta- neously. 2. these are test sources. they are affected by interrupt enable flags as in the case of interrupt sources, but no vectored interrupt is generated. the m pd75237 interrupt control circuit has the following functions: (a) hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (ie ) and the interrupt master enable flag (ime). (b) function of setting any interrupt start address. (c) multiple interrupt function which can specify priority order with the interrupt priority select register (ips). (d) interrupt request flag (irq ) test function. (interrupt generation can be checked by software.) (e) standby mode release function. (interrupt to be released by interrupt enable flag can be selected.) 5.1 interrupt control circuit configuration the interrupt control circuit has a configuration shown in fig. 5-1 and each hardware is mapped in the data memory space. vectored interrupt request signal (vector table address) vrq1 (0002h) vrq2 (0004h) vrq3 (0006h) vrq4 (0008h) vrq5 (000ah) vrq6 (000ch) vrq7 (000eh) interrupt order *1 1 2 3 4 5 6 7 internal/ external internal external external external internal internal internal internal external internal interrupt source intbt (reference timer interval signal from the basic interval timer) int4 (rising or falling edge detection) int0 int1 intcsi0 (serial data transfer end signal) intt0 (match signal from timer event/counter 0) inttpg (match signal from timer/pulse generator) intks (key scan timing signal from display controller) int2 *2 (rising edge detection) intw *2 (signal from watch timer) (rising and falling detected edge selection) testable input signal (irq2 and irqw set)
132 m pd75237 fig. 5-1 interrupt control circuit block diagram 2 2 4 2 im1 im0 (ime) ips ist int bt int4 /p00 int0 /p10 int1 /p11 intcsi0 intt0 inttpg intks intw irqbt irq4 irq0 irq1 irqcsi0 irqt0 irqtpg irqks irqw irq2 int2 /p12 vrq n vector table address generator priority control circuit standby release signal decoder internal bus interrupt enable flag (ie ) both edge detector edge detector edge detector noise eliminator rising edge detector
133 m pd75237 5.2 interrupt control circuit hardware devices (1) interrupt request flag, interrupt enable flag there are ten interrupt request flags (irq ) corresponding to interrupt sources (interrupt :8, test :2) as shown below. int0 interrupt request flag (irq0) serial interface interrupt request flag (irqcsi0) int1 interrupt request flag (irq1) timer/event counter interrupt request flag (irqt0) int2 interrupt request flag (irq2) timer/pulse generator interrupt request flag (irqtpg) int4 interrupt request flag (irq4) key scan interrupt request flag (irqks) bt interrupt request flag (irqbt) watch timer interrupt request flag (irqw) interrupt request flag is set to 1 at generation of an interrupt request and is automatically cleared (0) upon execution of interrupt service. irqbt and irq4 carry out clear operation differently because they share the vector address. (see 5.5 vector address sharing interrupt servicing .) there are ten interrupt enable flags (ie ) corresponding to interrupt request flags as shown below. int0 interrupt enable flag (ie0) serial interface interrupt enable flag (iecsi0) int1 interrupt enable flag (ie1) timer/event counter interrupt enable flag (iet0) int2 interrupt enable flag (ie2) timer/pulse generator interrupt enable flag (ietpg) int4 interrupt enable flag (ie4) key scan interrupt enable flag (ieks) bt interrupt enable flag (iebt) watch timer interrupt enable flag (iew) when the contents of interrupt enable flag is 1, interrupt is enabled and when it is 0, interrupt is disabled. when the interrupt request flag is set and the interrupt enable flag has enabled interrupt, the vectored interrupt request (vrqn) is generated. this signal is also used to release the standby mode. both the interrupt request flag and interrupt enable flag are operated by the bit manipulation instruction and 4-bit memory manipulation instruction. they can be operated directly by the bit manipulation instruction irrespective of mbe setting. the interrupt enable flag is operated by the ei ie and di ie instruction. the sktclr instruction is normally used to test the interrupt request flag. when the interrupt request flag is set by an instruction even if an interrupt has not been generated, the vectored interrupt is executed in the same way as when an interrupt had been generated. reset input clears the interrupt request flag and the interrupt enable flag (0) and disables all interrupts. h h
134 m pd75237 table 5-2 interrupt request flag set signals (2) noise eliminator and edge detection mode register int0, int1 and int2 each have the configuration shown in figs. 5-2 and 5-3 and serve as the external interrupt input capable of selecting detected edges. int0 has a function of eliminating noise with sampling clock. pulses having a shorter width than 2 sampling clock cycles * are eliminated as noise by noise eliminator. however, pulses having a larger width than 1 sampling clock cycle may be acknowledged as an interrupt signal depending on the sampling timing. pulses having a larger width than 2 sampling clock cycles are securely acknowledged as an interrupt signal. int0 has two sampling clocks, f and f x /64 and can select and use either clock. selection is made by bit 3 (im03) of the edge detection mode register (refer to fig. 5-4 ). irq2 is set by detecting the rising edge of int2 pin input. edge detection mode registers (im0 and im1) to select detection edge have the format shown in fig. 5-4. im0 and im1 each are set by a 4-bit memory manipulation instruction. reset input clears all bits to 0 and specifies int0, int1 and int2 for the rising edge. * when sampling clock is f : 2t cy when sampling clock is fx/64 : 128/f x note 1. since int0 samples by clock, it is not operated in the standby mode. 2. pulses are input to the int0/p10 pin serving as a port via the noise eliminator. thus, input pulses having two sampling clock cycles or larger. interrupt request flag set signal set by the reference time interval signal generated by the basic interval timer. set upon detection of the rising or falling edge of the int4/p00 input signal. set upon detection of the int0/p10 pin input signal edge. the detected edge is selected using the int0 mode register (im0). set upon detection of the int1/p11 pin input signal edge. the detected edge is selected using the int1 mode register (im1). set by the serial data transfer operation end signal of the serial interface. set by the match signal from the timer/event counter #0. set by the match signal from the timer/pulse generator. set by the key scan timing signal from the display controller. set by a signal from the watch timer. set upon detection of the rising edge of the int2/p12 pin input signal. interrupt request flag irqbt irq4 irq0 irq1 irqcsi0 irqt0 irqtpg irqks irqw irq2 interrupt enable flag iebt ie4 ie0 ie1 iecsi0 iet0 ietpg ieks iew ie2 h
135 m pd75237 fig. 5-2 int0 and int1 configuration fig. 5-3 int2 configuration int0/ p10 int0 im01, im00 im03 im10 im1 im0 4 4 f 64 f x int1/ p11 2 int2/p12 noise eliminator edge detector irq0 set signal int1 irq1 set signal int2 irq2 set signal rising edge detector input buffer internal bus internal bus input buffer selector edge detector
136 m pd75237 fig. 5-4 edge detection mode register format note if the edge detection mode register is changed, the interrupt request flag may be set. to prevent that from occurring, disable interrupt and change edge detection mode register first, then enable interruption after clearing the interrupt request flag by the clr1 instruction. if f x /64 has been selected as sampling clock by changing im0, it is necessary to clear the interrupt request flag 16 machine cycles after the mode register has been changed. 0 0 rising edge specification 0 1 falling edge specification 1 0 rising and falling edge specification 1 1 ignored (interrupt request flag not set) im03 0 im01 im00 3210 fb4h im0 address symbol 0 f (0.67, 1.33, 2.67, 10.7 m s: at 6.0 mhz operation) *1 1f x /64 (10.7 m s: at 6.0 mhz operation) *2 0 0 0 im10 fb5 im1 0 rising edge specification 1 falling edge specification *1. 0.95, 1.91, 3.82, 15.3 m s at 4.19 mhz operation 2. 15.3 m s at 4.19 mhz operation detection edge specification sampling clock h
137 m pd75237 (3) interrupt priority select register (ips) the interrupt priority select register is used to select high interrupt enabled for multiple interrupt and is specified by the least significant 3 bits. bit 3 is an interrupt master enable flag (ime) to specify whether all interrupts should be disabled or not. the ips is set by the 4-bit memory manipulation instruction and bit 3 is set/reset by the ei/di instruction. when changing the low-order 3-bit contents of ips, it is necessary to do so with interrupt disabled (ime = 0). reset input clears all bits to 0. fig. 5-5 interrupt priority select register 0 0 0 none of interrupts are made high interrupts. 0 0 1 vrq1 (intbt/int4) 0 1 0 vrq2 (int0) 0 1 1 vrq3 (int1) 1 0 0 vrq4 (intcsi0) 1 0 1 vrq5 (intt0) 1 1 0 vrq6 (inttpg) 1 1 1 vrq7 (intks) ips3 ips2 ips1 ips0 3210 fb2h ips address symbol all interrupts are disabled and vectored interrupt is not started. interrupt enable/disable is controlled by the correspond- ing interrupt enable flag. high interrupt select interrupt mask enable flag (ime) vectored interrupts on the left are taken as high interrupts. 0 1
138 m pd75237 5.3 interrupt sequence if interrupt is generated, it is processed using the following procedure: *1. ist1 and ist0 : interrupt status flags (psw bits 3, 2: refer to table 5-3 ist1 and ist0 interrupt servicing statuses ). 2. the start address of the interrupt service program and the mbe and rbe set values at the start of interrupt are stored in each vector table. no yes no ime = 1 yes no yes no yes yes no *1 ist 1,0 = 00 interrupt (intxxx) generated irqxxx set iexxx set? is vrqn a high interrupt? *1 ist 1,0 = 00 or 01 depends on the instruction being executed when irqn is set. 2 machine cycles pc and psw contents are saved into the stack memory and the data *2 in the vector table corresponding to the started vrqn is set to pc, rbe and mbe. ist0 and ist1 contents are changed from 00 to 01 or from 01 to 10. acknowledged irqxxx is reset. (if the interrupt source shares the vector address, refer to 5.5 vector address sharing interrupt servicing.) interrupt service program processing start selected vrqn remaining vrqn if two or more vrqn have been gene- rated simultaneously, one vrqn is se- lected according to the interrupt order shown in table 5-1. reserved until termination of operation being executed reserved until ime is set reserved until iexxx is set corresponding vrqn generated
139 m pd75237 table 5-3 ist1 and ist0 interrupt servicing statuses when an interrupt is acknowledged, ist1 and ist0 are saved into the stack memory together with other psw and is changed to a status higher by one level. when ret1 instruction is executed, the original ist1 and ist0 values are reset. 5.4 multi-interrupt service control the following two methods are available for the m pd75237 to generate multi-interrupts. (1) multi-interruption specifying high interrupt this is a standard multi-interrupt method of the m pd75237 in which one interrupt source is selected and multi-interruption (dual interrupt) is enabled. in other words, the high interrupt specified using the interrupt priority select register (ips) is enabled when the status of the operation being executed is 0 or 1. all other interrupts (low interrupts) are only enabled when the status is 0. (refer to fig. 5-6 and table 5-3 .) fig. 5-6 multi-interruption by high interrupt interrupt disable ips set interrupt enable low or high interrupt generated high interrupt generated normal processing (status 0) low or high interrupt servicing (status 1) high interrupt servicing (status 2) after interrupt acknowledgement ist1 ist0 01 10 CC interrupt acknowledgeable interrupt request all interrupts acknowledgeable only high interrupt acknowledgeable all interrupts not acknowledgeable cpu processing contents normal program being processed low or high interrupt being servicing high interrupt being servicing status of servicing being executed status 0 status 1 status 2 ist1 ist0 00 01 10 11 setting prohibited
140 m pd75237 (2) multi-interruption changing the interrupt status flag as is clear from table 5-3, multi-interrupt is enabled by changing the interrupt status flag using the program. that is, multi-interrupt is enabled by changing ist1 and ist0 each to 0 using the interrupt servicing program and setting status 0. this method is used to enable multi-interrupt with two to more interrupts or multi-interruption with triple or more interrupts. before changing ist1 and ist0, disable interruption by di instruction. fig. 5-7 multi-interruption by changing the interrupt status flag interrupt disable ips set interrupt enable low or high interrupt generated interrupt disable ist change interrupt enable low or high interrupt generated status 1 status 0 status 0 high interrupt generated status 1 status 2 normal processing (status 0) single interrupt dual interrupt triple interrupt
141 m pd75237 5.5 vector address sharing interrupt servicing since the intbt and int4 interrupt sources share the vector table, interrupt source selection is carried out as follows: (1) when only one interrupt source is used among the two interrupt sources sharing the vector table, set the interrupt enable flag of the necessary interrupt source (1) and clear the other interrupt enable flag (0). in this case, an interrupt request is generated by the enabled interrupt source (ie =1). when the request is acknowledged, the corresponding interrupt request flag is reset (as is the case with an interrupt not sharing the vector address). (2) when both interrupt sources are used set the interrupt enable flags corresponding to the two interrupt sources (1). in this case, the logical sum of the interrupt request flags of the two interrupt sources becomes an interrupt request. and, if an interrupt request by the setting of one or both interrupt request flags is acknowledged, none of the interrupt request flag is reset. accordingly, it is necessary to check in the interrupt service routing by which interrupt source the interrupt has been generated. it can be done by executing the di instruction at the beginning of the interrupt service routine and checking the interrupt request flag by the sktclr instruction.
142 m pd75237 stop mode stop instruction setting enabled only with main system clock. oscillator stops only with main system clock. operation enabled only when external sck0 input is selected for serial clock. operation enabled only when external sck1 input is selected for serial clock. operation stopped. operation enabled only when ti0 pin input is specified for count clock. operation enabled only f xt is selected for count clock. operation stopped. operation stopped. operation stopped. halt mode halt instruction setting enabled with either main system clock or subsystem clock. stops only with cpu clock f (oscillation continued). operation enabled when the main system clock oscillates or with external sck0. operation enabled only when the main system clock oscillates. operation (irqbt set at reference time intervals). operation enabled. operation enabled. operation enabled only when the main system clock oscillates. operation enabled only when the main system clock oscillates. operation enabled only when the main system clock oscillates. operating state operation disabled (display off mode set before disabling). int0 operation disabled. int1, int2 and int4 operation enabled. operation stopped. interrupt request signal or reset input from operational hardware enabled by interrupt enable flag. 6. standby functions two standby modes (stop mode and halt mode) are available for the m pd75237 to decrease power consumption in the program standby mode. 6.1 standby mode setting and operating state table 6-1 operation status in standby mode set instruction system clock when set clock oscillator serial interface (channel 0) serial interface (channel 1) basic interval timer timer/event counter watch timer timer/pulse generator event counter a/d converter fip controller/driver external interrupt cpu release signal
143 m pd75237 the stop and halt modes are set by stop and halt instructions, respectively. (the two instructions are instructions to set pcc bit 3 and bit 2, respectively.) when changing the cpu operation clock with the least significant 2 bits of pcc, a delay may result from pcc rewrite to cpu clock change as shown in table 4-1. thus, when changing the operation clock before the standby mode is set or the cpu clock after the standby mode is released, set the standby mode after the passage of the machine cycle required for cpu clock change following pcc rewrite. in the standby mode, the data of all registers and data memories which stop operating is held. such units include general registers, flag, mode registers and output latches. note 1. when the stop mode is set, x1 input is internally short-circuited to v ss (gnd potential) to prevent leakage from the crystal resonator unit. thus, the use of stop mode is prohibited in a system using external clocks. 2. because the interrupt request signal is used to release the standby mode, the standby mode is immediately released if there is an interrupt source with both the interrupt request flag and interrupt enable flag set. thus, the stop mode is set to the halt mode just after stop instruction execution. after waiting for the time period set by the btm register, the operating mode is reset.
144 m pd75237 6.2 standby mode release the stop and halt modes each are released upon generation of the interrupt request signal * enabled by the interrupt enable flag or by reset input. fig. 6-1 shows release operation in each mode. * except int0 to int2. fig. 6-1 standby mode release operation (1/2) (a) release by reset input in stop mode (b) release by interrupt generation in stop mode remarks the broken line shows the case in which the interrupt request which released the standby mode has been acknowledged (ime = 1). (c) release by reset input in halt mode * 31.3 ms at 4.19 mhz operation reset signal stop instruction operating mode stop mode halt mode operating mode oscillation oscillation stop oscillation clock wait (approx. 21.8 ms : 6.0 mhz) * reset signal halt instruction operating mode halt mode operating mode clock oscillation wait (approx. 21.8 ms : 6.0 mhz) * stop instruction standby release signal operating mode stop mode halt mode operating mode oscillation oscillation stop oscillation clock wait (time set by btm)
145 m pd75237 halt instruction standby release signal operating mode clock halt mode operating mode oscillation fig. 6-1 standby mode release operation (2/2) (d) release by interrupt generation in halt mode remarks the broken line shows the case in which the interrupt request which released the standby mode has been acknowledged (ime = 1). the wait time upon stop mode release does not include a time from stop mode release to clock oscillation start (a below) whether the stop mode is released by reset input or interrupt generation. if the stop mode has been released by interrupt generation, the wait time is determined by btm setting. (refer to table 6-2 .) table 6-2 wait time selection by btm * wait time does not include a time from stop mode release to oscillation start. btm3 btm2 btm1 btm0 C000 C011 C101 C111 in all other cases wait time * (values at f x = 4.19 mhz are shown in parentheses) approx. 2 20 /f x (approx. 250 ms) approx. 2 17 /f x (approx. 31.3 ms) approx. 2 15 /f x (approx. 7.82 ms) approx. 2 13 /f x (approx. 1.95 ms) setting prohibited (when f x = 4.19 mhz) btm3 btm2 btm1 btm0 C000 C011 C101 C111 in all other cases wait time * (values at f x = 6.0 mhz are shown in parentheses) approx. 2 20 /f x (approx. 175 ms) approx. 2 17 /f x (approx. 21.8 ms) approx. 2 15 /f x (approx. 5.46 ms) approx. 2 13 /f x (approx. 1.37 ms) setting prohibited (when f x = 6.0 mhz) a v ss stop mode release x1 in voltage waveform
146 m pd75237 6.3 operation after standby mode release (1) if the stop mode has been released by reset input, normal reset operation is carried out. (2) if the stop mode has been released by interrupt generation, the bit 3 (ime) contents of the ips determine whether a vectored interrupt should be executed when the cpu resumes instruction execution. (a) when ime = 0 execution is resumed with the instruction (nop instruction) following standby mode setting after the standby mode has been released. the interrupt request flag is held. (b) when ime = 1 vectored interrupt is executed following execution of two instructions after the standby mode has been released. if the standby mode has been released by intw (testable input), no vectored interrupt is generated; so the same processing as with (a) is carried out.
147 m pd75237 7. reset functions the reset signal (res) generator has a configuration shown in fig. 7-1. fig. 7-1 reset signal generator reset operation is shown in fig. 7-2. the output buffer is turned off upon reset input. table 7-1 shows each hardware status after reset. fig. 7-2 reset operation by reset input table 7-1 shows each hardware status after reset. reset interrupt reset signal (res) (21.8 ms : 6.0 mhz) * wait reset input operating mode or standby mode halt mode operating mode internal reset operation * 31.3 ms at 4.19 mhz operation
148 m pd75237 table 7-1 hardware statuses after reset (1/2) reset input in operation undefined 0 0 undefined undefined 0, 0 undefined undefined undefined 0 0 ffh 0 0, 0 0 hold 0 0 0 0 undefined 0 0 undefined 1 undefined 0 0 hardware program counter (pc) carry flag (cy) skip flag (sk0-sk2) interrupt status flag (ist1, ist2) bank enable flags (mbe, rbe) data memory (ram) general registers (x, a, h, l, d, e, b, c) bank select registers (mbs, rbs) stack pointer (sp) stack bank select register (sbs) counter (bt) mode register (btm) counter (t0) modulo register (tmod0) mode register (tm0) toe0, tout f/f mode register (wm) modulo register (modh, modl) mode registet (tpgm) counter (t1) mode register (tm1) gate control register (gatec) shift register (sio0) operating mode register (csim0) sbi control register (sbic) slave address register (sva) p01/sck0 output latch shift register (sio1) operating mode register (csim1) serial transfer end flag (eot) psw basic interval timer timer/event counter watch timer timer/pulse generator event counter serial inter- face (channel 1) reset input in standby mode sets the low-order 6 bits of program memory address 0000h to pc 13-8 and the contents of address 0001h to pc 7-0 . hold 0 0 sets bit 6 of program memory address 0000h to rbe and bit 7 to mbe. hold hold 0, 0 undefined undefined undefined 0 0 ffh 0 0,0 0 hold 0 0 0 0 hold 0 0 hold 1 hold 0 0 serial inter- face (channel 0)
149 m pd75237 hardware mode register (adm), eoc sa register bit sequential buffer (bsb0 to bsb3) mode register (dspm) dimmer select register (dims) digit select register (digs) display data memory output buffer static mode register (stata, statb) processor clock control register (pcc) system clock control register (scc) clock output mode register (clom) interrupt request flag (irq ) interrupt enable flag (ie ) interrupt master enable flag (ime) int0 and int1 mode registers (im0, im1) output buffer (ports 2 to 7) output latch (ports 2 to 7) input/output mode register (pmga, pmgb) pull-up resistor specify register (poga) output buffer output latch output latch table 7-1 hardware statuses after reset (2/2) reset input in operation 04h (eoc = 1) undefined undefined 0 0 8h hold off 0, 0 0 0 0 reset 0 0 0, 0 off clear 0 0 off 0 undefined reset input in standby mode 04h (eoc = 1) undefined hold 0 0 8h hold off 0, 0 0 0 0 reset 0 0 0, 0 off clear 0 0 off 0 hold ports 10 to 15 port h fip controller/ driver clock genera- tor and clock output circuit interrupt function a/d converter digital port
150 m pd75237 8. instruction set 8.1 characteristic instructions of m pd75237 (1) geti instruction the geti instruction is a 1-byte instruction to execute the following three types of operations by referring to the 2-byte table in the program memory. it can considerably help to decrease the number of program steps. (a) subroutine call to 16k-byte space (0000h to 3fffh) of table data as call instruction call address. (b) branch to 16k-byte space (0000h to 3fffh) of table data as branch instruction branch address (c) execution of table data as 2-byte instruction (except brcb and callf instructions) (d) execution of table data as 1-byte instruction and 2 operation codes. as shown in fig. 3-2, the table addressed referred to by geti instruction as 0020h to 007fh of the program memory and data can be set in 48 tables. when describing table addresses as operands, describe even addresses. note 1. 2-byte instructions which can be referred to by geti instruction are limited to 2-machine cycle instructions. 2. when referring to two 1-byte instructions by geti instruction, combinations are limited as follows. 1st byte instruction 2nd byte instruction incs l decs l incs h decs h incs hl incs e decs e incs d decs d incs de incs l decs l incs d decs d mov a, @hl mov @hl, a xch a, @hl mov a, @de xch a, @de mov a, @dl xch a, @dl 3. when a branch instruction or subroutine instruction is referenced by a geti instruction, the relevant branch destination or subroutine call address must be within 16k bytes (0000h to 3fffh). it is not possible to use a geti instruction to reference a branch instruction or subroutine call instruction to an address outside this range (4000h to 5f7fh).
151 m pd75237 since the pc does not increment during execution of geti instruction, it continues processing with the address following geti instruction. if an instruction preceding the geti instruction has the skip function, the geti instruction is skipped as is the case with all other 1-byte instructions. if the instruction referred to by the geti instruction has the skip function, an instruction following the geti instruction is skipped. when instructions having stack effects are referred to by the geti instruction, the following operations are carried out: ? if an instruction preceding geti instruction also has the stack effects of the same group, the execution of geti instruction eliminates the stack effects and the instructions referred to are not skipped. ? if an instruction following geti instruction also has the stack effects of the same group, the stack effects derived from the instructions referred to are valid and the following instruction is skipped. (2) bit manipulation instruction in addition to normal bit manipulation instructions (set and clear instructions), the bit test instruction, bit transfer instruction and bit boolean instructions (and, or, xor) are available for the m pd75237. manipulation bits are specified by bit manipulation addressing. three types of available addressing operations and bits manipulated by each addressing are shown below. addressing specifiable peripheral hardware specifiable bit address range rbe/mbe/ist1, ist0/ie /irq fb0h to fbfh port0 to port15 ff0h to fffh pmem.@l bsb0 to bsb3, port0 to port15 fc0h to fffh all peripheral hardware devices enabled all manipulatable bits of the memory for bit manipulation bank specified by mb fmem.bit @h+mem.bit remarks 1. : 0, 1, 2, 3, 4, bt, t0, tpg, csi0, ks, w 2. mb = mbe? mbs
152 m pd75237 (3) stack instructions if the instructions of the same group of the following three instructions are stacked (set at two or more continuous addresses) in the program, the stack instruction placed at the start point is executed. in the subsequent execution, one stack instruction is replaced with one nop instruction. group a: mov a, #n4, mov xa, #n8 group b: mov hl, #n8 (4) radix adjustment instructions radix adjustment instructions to adjust the result of 4-bit data addition or subtraction to any radix is available for the m pd75237. when the radix to be adjusted is m. ? add adds a, #16-m addc a, @hl adds a, #m ? subtract subc a, @hl adds a, #m using the above combinations, the addition/subtraction result with the memory addressed by the accumu- lator and register pair hl is adjusted to a m-ary radix. in the case of subtraction, ms complement of the subtraction result is set to the accumulator. the overflow/underflow remains in the carry flag (in these instruction combinations, the "adds a, #m" instruction skip function is disabled).
153 m pd75237 identifier description method reg x, a, b, c, d, e, h, l reg 1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hl-, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label * bit 2-bit immediate data or label fmem fb0h to fbfh and ff0h to fffh immediate data or labels pmem fc0h to fffh immediate data or labels addr1 0000h to 5f7fh immediate data or labels addr 0000h to 3f7fh immediate data or labels caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (bit0 = 0) or label portn port0 to port15 ie iebt, iecsi0, iet0, ietpg, ie0, ie1, ie2, ieks, iew, ie4 rbn rb0 to rb3 mbn mb0, mb1, mb2, mb3, mb15 8.2 instruction set and operation (1) operand identifier and description enter an operand in the operand column of each instruction using the description method relating to the operand identifier of the instruction (refer to the assembler specifications for details). if more than one description method is available, select one. capital alphabetic letters, plus and minus signs are keywords. describe them as they are. in the case of immediate data, describe appropriate numerical values or labels. symbols in the register and flag format diagrams in chapters 3 to 5 can be described as labels in place of mem, fmem, pmem, bit, etc. (available labels are limited for fmem and pmem. refer to 8.1 (2) bit manipulation instruction .) * for 8-bit data processing, only even addresses can be specified.
154 m pd75237 (2) legend for operation description a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expanded register pair (xa) bc : expanded register pair (bc) de : expanded register pair (de) hl : expanded register pair (hl) pc : program counter sp : stack pointer sbs : stack bank select register cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 15) ime : interrupt master enable flag ips : interrupt priority select register ie : interrupt enable flag rbs : register bank select register mbs : memory bank select register pcc : processor clock control register ? : address and bit delimiter ( ) : contents addressed by h : hexadecimal data
155 m pd75237 * 1 mb = mbe? mbs (mbs = 0, 1, 2, 3, 15) * 2 mb = 0 * 3 mbe = 0 : mb = 0 (00h to 7fh) mb = 15 (80h to ffh) mbe = 1 : mb = mbs (mbs = 0, 1, 2, 3, 15) * 4 mb = 15, fmem = fb0h to fbfh, ff0h to fffh * 5 mb = 15, pmem = fc0h to fffh * 6 addr = 0000h to 3fffh * 7 addr = (current pc) C 15 to (current pc) C 1, (current pc) + 2 to (current pc) + 16 * 8 caddr = 0000h to 0fffh (pc 14, 13, 12 = 00b) or 1000h to 1fffh (pc 14, 13, 12 = 01b) or 2000h to 2fffh (pc 14, 13, 12 = 10b) or 3000h to 3fffh (pc 14, 13, 12 = 11b) or 4000h to 4fffh (pc 14, 13, 12 = 100b) or 5000h to 5f7fh (pc 14, 13, 12 = 101b) * 9 faddr = 0000h to 07ffh *10 taddr = 0020h to 007fh *11 addr1 = 0000h to 5f7fh (3) description of symbols in the addressing area column data memory addressing program memory addressing remarks 1. mb indicates accessible memory bank. 2. in *2, mb = 0 irrespective of mbe and mbs. 3. in *4 and *5, mb = 15 irrespective of mbe and mbs. 4. *6 to *10 indicate addressable areas. (4) description of the machine cycle column s indicates the number of machine cycles required for skip operation by an instruction having skip function. the s value varies as follows: ? when not skipped .............................................................................. s = 0 ? when 1-byte or 2-byte instructions are skipped ............................ s = 1 ? when 3-byte instructions are skipped ............................................. s = 2 note geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle of cpu clock f and five time periods are available according to pcc and scc setting. (refer to 4.2 (3) processor clock control register (pcc) .)
156 m pd75237 note mnemonic operands machine cycle skip condition addressing area operation no. of bytes a, #n4 1 1 a ? n4 stack a reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 stack a hl, #n8 2 2 hl ? n8 stack b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2 + s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 @hl, a 1 1 (hl) ? a*1 @hl, xa 2 2 (hl) ? xa *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 mem, a 2 2 (mem) ? a*3 mem, xa 2 2 (mem) ? xa *3 a, reg 2 2 a ? reg xa, rp' 2 2 xa ? rp' reg1, a 2 2 reg1 ? a rp'1, xa 2 2 rp'1 ? xa a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l ? l+1 *1 l = 0 a, @hlC 1 2 + s a ? (hl), then l ? lC1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp' 2 2 xa ? rp' xa, @pcde 1 3 xa ? (pc 14C8 +de) rom xa, @pcxa 1 3 xa ? (pc 14C8 +xa) rom xa, @bcde 1 3 xa ? (bcde) rom *11 xa, @bcxa 1 3 xa ? (bcxa) rom *11 mov xch movt transfer table reference note instruction group
157 m pd75237 mnemonic operand machine cycle skip condition addressing area operation no. of bytes cy, fmem.bit 2 2 cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy ? (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? (h+mem 3C0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) ? cy *4 pmem.@l, cy 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? cy *5 @h+mem.bit, cy 2 2 (h+mem 3C0 .bit) ? cy *1 a, #n4 1 1 + s a ? a+n4 carry xa, #n8 2 2 + s xa ? xa+n8 carry a, @hl 1 1 + s a ? a+(hl) *1 carry xa, rp' 2 2 + s xa ? xa+rp' carry rp'1, xa 2 2 + s rp'1 ? rp'1+xa carry a, @hl 1 1 a, cy ? a+(hl)+cy *1 xa, rp' 2 2 xa, cy ? xa+rp'+cy rp'1, xa 2 2 rp'1, cy ? rp'1+xa+cy a, @hl 1 1 + s a ? aC(hl) *1 borrow xa, rp' 2 2 + s xa ? xaCrp' borrow rp'1, xa 2 2 + s rp'1 ? rp'1Cxa borrow a, @hl 1 1 a, cy ? aC(hl)Ccy *1 xa, rp' 2 2 xa, cy ? xaCrp'Ccy rp'1, xa 2 2 rp'1, cy ? rp'1CxaCcy a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa a, #n4 2 2 a ? a n4 a, @hl 1 1 a ? a (hl) *1 xa, rp' 2 2 xa ? xa rp' rp'1, xa 2 2 rp'1 ? rp'1 xa a11cy ? a 0 , a 3 ? cy, a nC1 ? a n a22a ? a note 1. instruction group 2. accumulator manipulation bit transfer operation note 2 mov1 adds addc subs subc and or xor rorc not note 1
158 m pd75237 mnemonic operands machine cycle skip condition addressing area operation no. of bytes reg 1 1 + s reg ? reg+1 reg = 0 rp1 1 1 + s rp1 ? rp1+1 rp1 = 00h @hl 2 2 + s (hl) ? (hl)+1 *1 (hl) = 0 mem 2 2 + s (mem) ? (mem)+1 *3 (mem) = 0 reg 1 1 + s reg ? regC1 reg = fh rp' 2 2 + s rp' ? rp'C1 rp' = ffh reg, #n4 2 2 + s skip if reg = n4 reg = n4 @hl, #n4 2 2 + s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1 + s skip if a = (hl) *1 a = (hl) xa, @hl 2 2 + s skip if xa = (hl) *1 xa = (hl) a, reg 2 2 + s skip if a = reg a = reg xa.rp' 2 2 + s skip if xa = rp' xa = rp' cy 1 1 cy ? 1 cy 1 1 cy ? 0 cy 1 1 + s skip if cy = 1 cy = 1 cy 1 1 cy ? cy increment/decrement note set1 clr1 skt not1 incs decs ske compare carry flag manipulation note instruction group
159 m pd75237 mem.bit 2 2 (mem.bit) ? 1*3 fmem.bit 2 2 (fmem.bit) ? 1*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 1*5 @h + mem.bit 2 2 (h+mem 3C0 .bit) ? 1*1 mem.bit 2 2 (mem.bit) ? 0*3 fmem.bit 2 2 (fmem.bit) ? 0*4 pmem.@l 2 2 (pmem 7C2 +l 3C2 .bit(l 1C0 )) ? 0*5 @h+mem.bit 2 2 (h+mem 3C0 .bit) ? 0*1 mem.bit 2 2 + s skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2 + s skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit) = 1 *1 (@h+mem.bit) = 1 mem.bit 2 2 + s skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2 + s skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit) = 0 *1 (@h+mem.bit) = 0 fmem.bit 2 2 + s skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if (pmem 7C2 +l 3C2 .bit(l 1C0 ))=1 and clear *5 (pmem.@l) = 1 @h+mem.bit 2 2 + s skip if (h+mem 3C0 .bit)=1 and clear *1 (@h+mem.bit)=1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 cy, fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy (pmem 7C2 +l 3C2 .bit(l 1C0 )) *5 cy, @h+mem.bit 2 2 cy ? cy (h+mem 3C0 .bit) *1 pc 14C0 ? addr1 (optimum instruction is addr selected from among br !addr, *11 bra !addr1, brcb !caddr and br $addr1 by an assembler.) $addr1 1 2 pc 14C0 ? addr1 *7 !addr 3 3 pc 14 ? 0, pc 13C0 ? !addr *6 pcde 2 3 pc 14C0 ? pc 14C8 +de pcxa 2 3 pc 14C0 ? pc 14C8 +xa bcde 2 3 pc 14C0 ? bcde bcxa 2 3 pc 14C0 ? bcxa !addr1 3 3 pc 14C0 ? !addr1 *11 !caddr 2 2 pc 14C0 ? pc 14, 13,12 +caddr 11C0 *8 mnemonic operands machine cycle skip condition addressing area operation no. of bytes note branch set1 clr1 skt skf sktclr and1 or1 xor1 br memory bit manipulation h brcb bra note instruction group
160 m pd75237 (spC5) (spC6) (spC3) (spC4) ? pc 14C0 !addr 3 4 (spC2) ? , , mbe, rbe *6 pc 14 ? 0, pc 13C0 ? addr, sp ? spC6 (spC5) (spC6) (spC3) (spC4) ? pc 14C0 !addr1 3 3 (spC2) ? , , mbe, rbe *11 pc 14C0 ? addr1, sp ? spC6 (spC5) (spC6) (spC3) (spC4) ? pc 14C0 !faddr 2 3 (spC2) ? , , mbe, rbe *9 pc 14C0 ? 0000, faddr, sp ? spC6 , , mbe, rbe ? (sp+4) 13pc 14C0 ? (sp+1) (sp) (sp+3) (sp+2) sp ? sp+6 , , mbe, rbe ? (sp+4) pc 14C0 ? (sp+1) (sp) (sp+3) (sp+2) unconditional sp ? sp+6 then skip unconditionally , pc 14, 13, 12 ? (sp+1) 13pc 11C0 ? (sp) (sp+3) (sp+2) psw ? (sp+4) (sp+5), sp ? sp+6 rp 1 1 (spC1) (spC2) ? rp, sp ? spC2 bs 2 2 (spC1) ? mbs, (spC2) ? rbs, sp ? spC2 rp 1 1 rp ? (sp+1) (sp), sp ? sp+2 bs 2 2 mbs ? (sp+1), rbs ? (sp), sp ? sp+2 2 2 ime(ips.3) ? 1 ie 22ie ? 1 2 2 ime(ips.3) ? 0 ie 22ie ? 0 a, portn 2 2 a ? portn xa, portn 2 2 xa ? portn+1, portn portn, a 2 2 portn ? a portn, xa 2 2 portn+1, portn ? xa 2 2 set halt mode (pcc.2 ? 1) 2 2 set stop mode (pcc.3 ? 1) 1 1 no operation mnemonic operands machine cycle skip condition addressing area operation no. of bytes note call callf ret rets 1 3 + s reti push pop ei di in * interrupt control input/output cpu control out * * mbe = 0 or mbe = 1 and mbe = 15 must be set for execution of in/out instruction note instruction group halt stop nop calla subroutine stack control
161 m pd75237 mnemonic operands machine cycle skip condition addressing area operation no. of bytes note rbn 2 2 rbs ? n (n = 0 to 3) mbn 2 2 mbs ? n (n = 0, 1, 2, 3, 15) ? tbr instruction pc 13C0 ? (taddr) 5C0 +(taddr+1) pc 14 ? 0 ? tcall instruction (spC5)(spC6)(spC3)(spC4) ? pc 14C0 4 (spC2) ? , , mbe, rbe pc 13C0 ? (taddr) 5C0 +(taddr+1) sp ? spC6, pc 14 ? 0 ? (taddr) (taddr+1) instruction depends on executed in the case of instructions instruction except tbr and referred to. tcall instructions special sel 3 1 taddr get1 * *10 h 3 ------------------------------------------------------------------ ------------------------ ------------------------ ------------------------------------------------------------------ * tbr and tcall instructions are assembled pseudo-instructions to define the geti instruction table. note instruction group
162 m pd75237 r 2 r 1 r 0 reg 0 0 0 a 0 0 1 x 0 1 0 l 0 1 1 h 1 0 0 e 1 0 1 d 1 1 0 c 1 1 1 b reg 8.3 operation codes (1) description of operation code symbols p 2 p 1 p 0 reg-pair 0 0 0 xa 0 0 1 xa' 0 1 0 hl 0 1 1 hl' 1 0 0 de 1 0 1 de' 1 1 0 bc 1 1 1 bc' reg1 rp' rp'1 q 2 q 1 q 0 addressing 0 0 1 @hl 0 1 0 @hl+ 0 1 1 @hlC 1 0 0 @de 1 0 1 @dl p 2 p 1 reg-pair 0 0 xa 0 1 hl 1 0 de 1 1 bc @rpa rp2 rp1 rp n 5 n 2 n 1 n 0 ie 0 0 0 0 iebt 0 0 1 0 iew 0 0 1 1 ietpg 0 1 0 0 iet0 0 1 0 1 iecsi0 0 1 1 0 ie0 0 1 1 1 ie2 1 0 0 0 ie4 1 0 1 1 ieks 1 1 1 0 ie1 in : immediate data for n4 and n8 dn : immediate data for mem bn : immediate data for bit nn : immediate data for n and ie tn : immediate data for taddr 1/2 an : immediate data for [relative address distance from branch destination address (2 to 16)]-1 sn : immediate data for ones complement of [relative address distance from branch destination address (15 to 1)] @rpa1
163 m pd75237 (2) operation codes of bit manipulation addressing *1 in the operand column indicates that the following three addressings are available. ? fmem.bit ? pmem.@l ? @h+mem.bit the 2nd byte *2 of the operation code corresponding to the above addressing is shown below: bn : immediate data for bit fn : immediate data for fmem (indicating the low-order 4-bits of address) gn : immediate data for pmem (indicating the bits 5 to 2 of address) dn : immediate data for mem (indicating the low-order 4 bits of address) *1 2nd byte of operation code accessible bits 10b 1 b 0 f 3 f 2 f 1 f 0 manipulatable bits of fb0h to fbfh 11b 1 b 0 f 3 f 2 f 1 f 0 manipulatable bits of ff0h to fffh pmem.@l 0100g 3 g 2 g 1 g 0 manipulatable bits of fc0h to fffh manipulatable bits of accessible memory banks fmem.bit @h+mem.bit 00b 1 b 0 d 3 d 2 d 1 d 0
164 m pd75237 a, #n4 0 1 1 1 i 3 i 2 i 1 i 0 reg1, #n4 1 0 011010i 3 i 2 i 1 i 0 1r 2 r 1 r 0 rp, #n8 1 0 0 0 1 p 2 p 1 1i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 a, @rpa 1 1 1 0 0 q 2 q 1 q 0 xa, @hl 1 0 10101000 0110 00 @hl, a 1 1 101000 @hl, xa 1 0 10101000 0100 00 a, mem 10 100011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xa, mem 1 0 100010d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 mem, a 1 0 010011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mem, xa 1 0 010010d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 a, reg 10 01100101 111r 2 r 1 r 0 xa, rp' 1 0 10101001 011p 2 p 1 p 0 reg1, a 1 0 01100101 110r 2 r 1 r 0 rp'1, xa 1 0 10101001 010p 2 p 1 p 0 a, @rpa 1 1 1 0 1 q 2 q 1 q 0 xa, @hl 1 0 10101000 0100 01 a, mem 10 110011d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xa, mem 1 0 110010d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 a, reg1 1 1 0 1 1 r 2 r 1 r 0 xa, rp' 1 0 10101001 000p 2 p 1 p 0 xa, @pcde 1 1 010100 xa, @pcxa 1 1 010000 xa, @bcde 1 1 010101 xa, @bcxa 1 1 010001 cy, * 1 10 111101 * 2 * 1 , cy 10 011011 * 2 mov1 operation code b 1 b 2 b 3 mnemonic operands note 1. instruction group 2. bit transfer note 2 xch movt table reference transfer mov note 1
165 m pd75237 a, #n4 0 1 1 0 i 3 i 2 i 1 i 0 xa, #n8 1 0 111001i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 a, @hl 11 010010 xa, rp' 1 0 10101011 001p 2 p 1 p 0 rp'1, xa 1 0 10101011 000p 2 p 1 p 0 a, @hl 10 101001 xa, rp' 1 0 10101011 011p 2 p 1 p 0 rp'1, xa 1 0 10101011 010p 2 p 1 p 0 a, @hl 10 101000 xa, rp' 1 0 10101011 101p 2 p 1 p 0 rp'1, xa 1 0 10101011 100p 2 p 1 p 0 a, @hl 10 111000 xa, rp' 1 0 10101011 111p 2 p 1 p 0 rp'1, xa 1 0 10101011 110p 2 p 1 p 0 a, #n4 10 01100100 11i 3 i 2 i 1 i 0 a, @hl 10 010000 xa, rp' 1 0 10101010 011p 2 p 1 p 0 rp'1, xa 1 0 10101010 010p 2 p 1 p 0 a, #n4 10 01100101 00i 3 i 2 i 1 i 0 a, @hl 10 100000 xa, rp' 1 0 10101010 101p 2 p 1 p 0 rp'1, xa 1 0 10101010 100p 2 p 1 p 0 a, #n4 10 01100101 01i 3 i 2 i 1 i 0 a, @hl 10 110000 xa, rp' 1 0 10101010 111p 2 p 1 p 0 rp'1, xa 1 0 10101010 110p 2 p 1 p 0 a 10 011000 a 10 01100101 0111 11 note 1 operation code b 1 b 2 b 3 mnemonic operands operate note 1. instruction group 2. accumulator manipulation note 2 rorc not adds addc subs subc and or xor
166 m pd75237 reg 11 000r 2 r 1 r 0 rp1 10 001p 2 p 1 0 @hl 10 01100100 0000 10 mem 10 000010d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 reg 11 001r 2 r 1 r 0 rp' 10 10101001 101p 2 p 1 p 0 reg, #n4 1 0 011010i 3 i 2 i 1 i 0 0r 2 r 1 r 0 @hl, #n4 1 0 01100101 10i 3 i 2 i 1 i 0 a, @hl 10 000000 xa, @hl 1 0 10101000 0110 01 a, reg 10 01100100 001r 2 r 1 r 0 xa, rp' 1 0 10101001 001p 2 p 1 p 0 cy 11 100111 cy 11 100110 cy 11 010111 cy 11 010110 mem.bit 1 0 b 1 b 0 0101d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * 1 10 011101 * 2 mem.bit 1 0 b 1 b 0 0100d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * 1 10 011100 * 2 mem.bit 1 0 b 1 b 0 0111d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * 1 10 111111 * 2 mem.bit 1 0 b 1 b 0 0110d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * 1 10 111110 * 2 * 1 10 011111 * 2 cy, * 1 10 101100 *2 cy, * 1 10 101110 *2 cy, * 1 10 111100 *2 note operation code b 1 b 2 b 3 mnemonic operands memory bit manipulation incs decs ske set1 clr1 skt not1 set1 clr1 skt skf sktclr and1 or1 xor1 increment/decrement compare note instruction group carry flag manipulation
167 m pd75237 !addr 1 0 10101100 addr 00 00a 3 a 2 a 1 a 0 11 11s 3 s 2 s 1 s 0 !addr1 1 0 1110100 addr1 !caddr 0 1 0 1 caddr pcde 1 0 01100100 0001 00 pcxa 1 0 01100100 0000 00 bcde 1 0 01100100 0001 01 bcxa 1 0 01100100 0000 01 !addr 1 0 10101101 addr !addr1 1 0 1110110 addr1 !faddr 0 1 0 0 0 faddr 11 101110 11 100000 11 101111 rp 01 001p 2 p 1 1 bs 10 01100100 0001 11 rp 01 001p 2 p 1 0 bs 10 01100100 0001 10 a, portn 1 0 10001111 11n 3 n 2 n 1 n 0 xa, portn 1 0 10001011 11n 3 n 2 n 1 n 0 portn, a 1 0 01001111 11n 3 n 2 n 1 n 0 portn, xa 1 0 01001011 11n 3 n 2 n 1 n 0 10 01110110 1100 10 ie 10 01110110n 5 11n 2 n 1 n 0 10 01110010 1100 10 ie 10 01110010n 5 11n 2 n 1 n 0 10 01110110 1000 11 10 01110110 1100 11 01 100000 rbn 10 01100100 1000n 1 n 0 mbn 10 01100100 01n 3 n 2 n 1 n 0 taddr 0 0 t 5 t 4 t 3 t 2 t 1 t 0 note operation code b 1 b 2 b 3 mnemonic operands branch $addr1 (+16) to (+2) (C1) to (C15) br h brcb br call calla callf ret rets reti subroutine stack control bra geti special push pop in out ei di halt stop nop sel interrupt control input/output cpu control note instruction group
168 m pd75237 9. mask option selection the m pd75237 has the following mask options enabling or disabling on-chip components. * select pull-down resistor incorporation to v load or v ss in 8-bit units. note in a system not using subsystem clocks, power consumption in the stop mode can be decreased by removing the feedback resistor from the oscillator. pin mask option p40 to p43 p50 to p53 p70 to p73 pull-down resistor incorporation enabled bit-wise s0/p120 to s3/p123 s4/p130 to s7/p133 s8/p140, s9/p141 s10/t15/p142, s11/t14/p143 s12/t13/p150/ph0 to s15/t10/p153/ph3 s16/p100 to s19/p103 s20/p110 to s23/p113 deletion of sybsystem clock oscillator feedback resistor possible pull-up resistor incorporation enabled bit-wise pull-down resistor incorporation to v load enabled bit-wise pull-down resistor incorporation to v load or v ss bit-wise * xt1, xt2
169 m pd75237 lpf int4 ppo an n an n port n sck1 so1 l r so0 sck0 port n buz int0 port7 s0-s17 t0-t15 x1 x2 xt1 xt2 bz (18 4) 4.19/6.0 mhz 32.768 khz led osd power failure detection electronic tuner voice lever timer tuner system computer remote controlled reception hsync detection fluorescent display panel (fip) 18 segments 16 digits key matrix remote controlled signal mechanism piozoelectric buzzer servo ic hsync pulse 10. application block diagram m pd75237 remarks lpf : low pass filter osd : on screen display hsync : horizontal synchronous m pc1490
170 m pd75237 power supply voltage range (ta = C40 to +85 c) 11. electrical specifications unit rating except ports 4 and 5 pins except display output pins display output pins 1 pins except display output pins s0 to s9, s16 to s23 1 pin t0 to t15 1 pin total of pins except display output pins total of display output pins 1 pin total of ports 0, 2, 3 and 4 total of ports 5 to 8 plastic qfp pull-up resistor open-drain peak value effective value peak value effective value peak value effective value ( ta = C40 to +70 c ) ( ta = C40 to +85 c ) v v v v v v v ma ma ma ma ma ma ma ma ma ma ma mw mw c c parameter symbol test conditions v dd v load v i1 v i2 v o v od i oh i ol p t t opt t stg power supply voltage input voltage output voltage output current high ports 4 and 5 C0.3 to +7.0 v dd C40 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to +11 C0.3 to v dd +0.3 v dd C40 to v dd +0.3 C15 C15 C30 C30 C120 30 15 100 60 100 60 700 510 C40 to +85 C65 to +150 unit parameter cpu *1 display controller time/pulse generator other hardware *1 v v v v 6.0 6.0 6.0 6.0 *2 4.5 4.5 2.7 min. max. test conditions *1. except the system clock osccillator, display controller and timer/pulse generator. 2. the power supply voltage range varies, depending on the cycle time. refer to the description of ac characteristics. absolute maximum ratings (ta = 25 c) output current low total loss operating temperature storage temperature
171 m pd75237 main system clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) unit max. typ. parameter test conditions min. v dd = oscillation voltage range after v dd reaches the minimum value in the oscillation voltage range v dd = 4.5 to 6.0 v oscillator frequency (f x ) *1 oscillation stabilization time *2 oscillator frequency (f x ) *1 oscillation stabilization time *2 x1 input frequency (f x ) *1 x1 high and low level widths (t xh , t xl ) x1 x2 c1 c2 x1 x2 c1 c2 *1. oscillator characteristics only. refer to the description of ac characteristics for details of instruction execution time. 2. time required for oscillation to become stabilized after v dd application or stop mode release. x1 x2 m pd74hcu04 resonator recommended circuit 2.0 2.0 2.0 81 ceramic resonator crystal resonator external clock 4.19 mhz ms mhz ms ms mhz ns subsystem clock oscillator characteristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v) 6.2 4 6.2 10 30 6.2 250 unit max. typ. min. xt1 xt2 c3 c4 r parameter test conditions oscillator frequency (f xt ) *1 oscillation stabilization time *2 xt1 input frequency (f xt ) *1 xt1 high and low level widths (t xth , t xtl ) xt1 xt2 resonator recommended circuit crystal resonator external clock v dd = 4.5 to 6.0 v 32 32 5 32.768 1.0 35 2 10 100 15 khz s s khz m s *1. oscillator characteristics only. refer to the description of ac characteristics for instruction execution time. 2. time required for oscillation to become stabilized after v dd application or stop mode release.
172 m pd75237 max. input capacitance output capacitance (except display output) input /output capacitance output capacitance ( display output ) 15 15 15 35 pf pf pf pf unit test conditions symbol parameter min. typ. c i c o c io c o f = 1 mhz unmeasured pin returned to 0 v capacitance (ta = 25 c, v dd = 0 v)
173 m pd75237 dc characteristics (ta = C40 to 85 c, v dd = 2.7 to 6.0 v) unit min. parameter symbol test conditions max. typ. 0.7 v dd 0.8 v dd v dd C0.4 0.65 v dd 0.7 v dd 0.7 v dd 0.7 v dd 0 0 0 v dd C1.0 v dd C0.5 v dd v dd v dd v dd v dd v dd 10 0.3 v dd 0.2 v dd 0.4 2.0 0.4 0.5 0.2 v dd 3 20 20 C3 C20 3 20 C3 C10 200 1000 135 80 300 70 60 v v v v v v v v v v v v v v v v m a m a m a m a m a m a m a m a m a ma ma k w k w k w k w k w k w k w v ih1 v ih2 v ih3 v ih4 v ih5 v il1 v il2 v il3 v oh v ol i lih1 i lih2 i lih3 i lil1 i lil2 i loh1 i loh2 i lol1 i lol2 v dd = 4.5 to 6.0 v pull-up resistor incorporated open-drain port 7 input voltage high ports 4, 5 except below ports 0, 1, reset, p81, p83 x1, x2, xt1 except below ports 0, 1 reset, p81, p83 x1, x2, xt1 i oh = C1 ma i oh = C100 m a i ol = 15 ma i ol = 1.6 ma i ol = 400 m a v dd = 4.5 to 6.0v v dd = 2.7 to 6.0v v dd = 4.5 to 6.0v v dd = 4.5 to 6.0v v dd = 2.7 to 6.0v all output pins except ports 4, 5 and p03 0.4 ports 3, 4, 5 all output pins sb0, sb1 open-drain pull-up resis- tance 3 1k w v in = v dd open-drain v in = 10 v except below x1, x2, xt1 ports 4, 5 except below x1, x2, xt1 except below ports 4, 5 except below display output v in = 0 v v out = v dd (open-drain) v out = 10 v v out = 0 v v out = v load = v dd C35 v input voltage low output voltage high output voltage low input leakage current high input leakage current low output leakage current low output leakage current high C5.5 C22 80 50 40 40 C3 C15 20 20 25 15 30 15 10 v dd = 4.5 to 6.0 v v od = v dd C2 v v dd = 4.5 to 6.0 v v dd Cv load = 35 v v dd = 5 v 10% v dd = 3 v 10% v dd = 5 v 10% v dd = 3 v 10% i od r l s0 to s9, s16 to s23 t0 to t15 port 7 v in = v dd r p7 display output r v1 r v2 ports 4 and 5 v out = v dd C2.0 v display output current built-in pull-down resistor (mask option) built-in pull-up resistor ports 0, 1, 2, 3, and 6 (except p00) v in = 0 v
174 m pd75237 dc characteristics (ta = C40 to 85 c, v dd = 2.7 to 6.0 v) unit max. typ. min. symbol test conditions parameter a/d converter charateristics (ta = C40 to +85 c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v, av dd = v dd ) operating mode i dd1 i dd1 6 mhz crystal oscillation c1 = c2 = 22 pf *4 4.19 mhz crystal oscillation c1 = c2 = 22 pf *4 operating mode v dd = 5 v 10% *2 v dd = 3 v 10% *3 v dd = 5 v 10% v dd = 3 v 10% v dd = 5 v 10% *2 v dd = 3 v 10% *3 v dd = 5 v 10% v dd = 3 v 10% v dd = 3 v 10% v dd = 3 v 10% ta = 25 c ma ma m a m a ma ma m a m a m a m a m a m a supply current *1 i dd2 halt mode i dd2 halt mode halt mode i dd4 i dd3 32 khz crystal oscillation *5 operating mode v dd = 5 v 10% v dd = 3 v 10% m a i dd5 xt1 = 0 v stop mode *1. current flowing to the built-in pull-down (pull-up) resistor excluded. 2. when operated in the high speed mode with the processor clock control register (pcc) set to 0011. 3. when operated in the low speed mode with pcc = 0000. 4. subsystem clock oscillation included. 5. when operated with subsystem clock with system clock control register (scc) set to 1001 and the main system clock stopped. 13.5 1.8 1800 600 9 1.5 1800 600 120 15 20 10 5 4.5 0.6 600 200 3 0.5 600 200 40 5 0.5 0.3 unit max. typ. min. parameter symbol test conditions resolution absolute accuracy *1 conversion time sampling time analog input voltage analog input impedance av ref current t conv t samp v ian r an i aref C10 ta +85 c C40 ta < C10 c bit lsb m s m s v m w ma 8 1.5 2.0 168/f x 44/f x av ref 2.0 *2 *3 8 1000 1.0 2.5 v av ref av dd 8 av ss h *1. absolute accuracy with any quantization error ( 1/2 lsb) excluded. 2. time until eoc = 1 after execution of conversion start instruction (f x = 28.0 m s at 6.0 mhz, f x = 40.1 m s at 4.19 mhz). 3. time until the end of sampling after execution of conversion start instruction (f x = 7.33 m s at 6.0 mhz, f x = 10.5 m s at 4.19 mhz).
175 m pd75237 ac characteristics (ta = C40 to +85 c , v dd = 2.7 to 6.0 v) (1) basic operation parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 0.67 64 m s 2.6 64 m s operation with subsystem clock 114 122 125 m s v dd = 4.5 to 6.0 v 0 1 mhz 0 275 khz v dd = 4.5 to 6.0 v 0.48 m s 1.8 m s int0 *2 m s int1, 2, 4 10 m s 10 m s f ti t cy t tih , t til t inth , t intl t rsl cpu clock cycle time (minimum instruction execution time = 1 machine cycle) *1 operation with main system clock ti0 input frequency ti0 input high and low- level widths interrupt input high and low-level widths reset low-level width cycle time t cy [ m s] 70 64 60 6 5 4 3 2 1 0.5 0 1 2 3 4 5 6 operation guaranteed range t cy vs v dd (main system clock in operation) power supply voltage v dd [v] *1. cpu clock ( f ) cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (scc) and the processor clock control register (pcc). the cycle time t cy characteristics for power supply voltage v dd when the main system clock is in operation is shown below. 2. 2t cy or 128/f x is set by interrupt mode register (im0) setting.
176 m pd75237 1340 ns 1600 ns 2680 ns 3800 ns v dd = 4.5 to 6.0 v (t kcy /2)C50 ns (t kcy /2)C150 ns 150 ns 400 ns v dd = 4.5 to 6.0 v 250 ns 1000 ns parameter symbol test conditions min. typ. max. unit (2) serial transfer operation (a) 2-wire and 3-wire serial i/o mode (sck...internal clock output) * r l and c l are so output line load resistance and load capacitance, respectively. (b) 2-wire and 3-wire serial i/o mode (sck...external clock input) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns 400 ns v dd = 4.5 to 6.0 v 300 ns 1000 ns r l = 1 k w c l = 100 pf * sck cycle time t kcy2 t kl2 t kh2 si setup time (to sck - ) t sik2 t ksi2 si hold time (from sck - ) t kso2 so output delay time from sck * r l and c l are so output line load resistance and load capacitance, respectively. sck high and low level widths r l = 1 k w c l = 100 pf * t kl1 t kh1 si setup time (to sck - ) t sik1 t ksi1 si hold time (from sck - ) t kso1 so output delay time from sck sck high and low level widths v dd = 4.5 to 6.0 v sck cycle time t kcy1 f x = 6.0 mhz f x = 4.19 mhz f x = 6.0 mhz f x = 4.19 mhz
177 m pd75237 (c) sbi mode (sck...internal clock output (master)) parameter symbol test conditions min. typ. max. unit * r l and c l are so output line load resistance and load capacitance, respectively. (d) sbi mode (sck...external clock input (slave)) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns t kcy /2 ns v dd = 4.5 to 6.0 v 0 300 ns 0 1000 ns t kcy ns t kcy ns t kcy ns t kcy ns r l = 1 k w c l = 100 pf * t kcy4 t kl4 t kh4 t sik4 t ksi4 t kso4 sck cycle time sb0 and sb1 setup time (to sck - ) sb0 and sb1 hold time (from sck - ) sb0 and sb1 output delay time from sck sck high and low level widths sb0, sb1 from sck - sck from sb0, sb1 sb0 and sb1 low-level widths sb0 and sb1 high-level widths t ksb t sbk t sbl t sbh * r l and c l are so output line load resistance and load capacitance, respectively. r l = 1 k w c l = 100 pf * t kl3 t kh3 t sik3 t ksi3 t kso3 sb0 and sb1 setup time (to sck - ) sb0 and sb1 hold time (from sck - ) sb0 and sb1 output delay time from sck sck high and low level widths sb0, sb1 from sck - sck from sb0, sb1 sb0 and sb1 low-level widths sb0 and sb1 high-level widths t ksb t sbk t sbl t sbh t kcy3 sck cycle time 1340 ns 1600 ns 2680 ns 3800 ns v dd = 4.5 to 6.0 v t kcy /2-50 ns t kcy /2-150 ns 150 ns t kcy /2 ns v dd = 4.5 to 6.0 v 0 250 ns 0 1000 ns t kcy ns t kcy ns t kcy ns t kcy ns f x = 6.0 mhz f x = 4.19 mhz f x = 6.0 mhz f x = 4.19 mhz v dd = 4.5 to 6.0 v
178 m pd75237 ac timing test points (except x1 and xt1 inputs) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points clock timing 1/f xt t xtl t xth v dd - 0.5 v 0.4 v xt1 input ti0 timing 1/f x t xl t xh v dd - 0.5 v 0.4 v x1 input 1/f ti t til t tih ti0
179 m pd75237 serial transfer timing 3-wire serial i/o mode: 2-wire serial i/o mode: t kh1 t kcy1 t kl1 t sik1 t ksi1 t kso1 sck si so input data output data t kcy2 t kl2 t kh2 t sik2 t kso2 t ksi2 sck sb0,1
180 m pd75237 serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing int0,1,2,4 t intl t inth reset t rsl t ksb sck sb0,1 t sbl t sbh t sbk t kl3,4 t kh3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sck t ksb sb0,1 t sbk t kl3,4 t kh3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4
181 m pd75237 data memory stop mode low power supply voltage data hold characteristics (ta = C40 to +85 c) stop instruction execution v dd v dddr operating mode halt mode stop mode data hold mode t wait reset t srel internal reset operation data hold timing (stop mode release by reset) parameter symbol test conditions min. typ. max. unit 2.0 6.0 v v dddr = 2.0 v 0.1 10 m a 0 m s release by reset 2 17 /f x ms release by interrupt request *3 ms data hold power supply voltage data hold power supply current *1 release signal set time oscillation stabilization wait time *2 v dddr i dddr t srel t wait *1. current to the on-chip pull-up (pull-down) resistor is not included. 2. oscillation stabilization wait time is time to stop cpu operation to prevent unstable operation upon oscillation start. 3. according to the setting of the basic interval timer mode register (btm) (see below). wait time (values at f x = 6.0 mhz (values at f x = 4.19 mhz in parentheses) in parentheses) 0 002 20 /f x (approx. 175 ms) 2 20 /f x (approx. 250 ms) 0 112 17 /f x (approx. 21.8 ms) 2 17 /f x (approx. 31.3 ms) 1 012 15 /f x (approx. 5.46 ms) 2 15 /f x (approx. 7.82 ms) 1 112 13 /f x (approx. 1.37 ms) 2 13 /f x (approx. 1.95 ms) btm3 btm2 btm1 btm0
182 m pd75237 data hold timing (standby release signal: stop mode release by interrupt signal) v dd v dddr t srel t wait halt mode operating mode stop mode data hold mode stop instruction execution standby release signal (interrupt request)
183 m pd75237 12. characteristic curves (reference values) i dd vs v dd (main system clock : 6.0 mhz) power supply current i dd ( m a) h 5000 1000 500 100 50 10 5 1 0 1 2 3 4 5 6 7 22pf 22pf 22pf 22pf 6.0mhz 32.768khz 330k w x1 x2 xt1 xt2 (ta=25?) pcc=0011 pcc=0010 pcc=0001 pcc=0000 main system clock halt mode + 32 khz oscillation subsystem clock operating mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode crystal resonator crystal resonator power voltage v dd (v)
184 m pd75237 i dd vs v dd (main system clock : 4.19 mhz) power supply current i dd ( m a) 5000 1000 500 100 50 10 5 1 0 1 2 3 4 5 6 7 30pf 30pf 22pf 22pf 4.19mhz 32.768khz 330k w x1 x2 xt1 xt2 (ta=25?) pcc=0011 pcc=0010 pcc=0001 pcc=0000 main system clock halt mode + 32 khz oscillation subsystem clock operating mode main system clock stop mode + 32 khz oscillation and subsystem clock halt mode crystal resonator crystal resonator power voltage v dd (v)
185 m pd75237 13. package information 94 pin plastic qfp ( 20) item millimeters inches f 1 f 2 i 1.6 0.8 0.15 q 0.063 0.031 0.006 s94gj-80-5bg-3 note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. c 20.0?.2 0.787 m 0.15 0.006 0.1?.1 0.004?.004 +0.004 ?.003 +0.009 ?.008 a 23.2?.4 0.913 h 0.35?.10 0.014 +0.004 ?.005 l 0.8?.2 0.031 +0.009 ?.008 n 0.10 0.004 p 3.7 0.146 s 4.0 max. 0.158 max. +0.10 ?.05 b 20.0?.2 0.787 +0.009 ?.008 +0.017 ?.016 j 0.8 (t.p.) 0.031 (t.p.) r 5 ? 5 ? d 23.2?.4 0.913 +0.017 ?.016 g 1 g 2 1.6 0.8 0.063 0.031 k 1.6?.2 0.063?.008 a b g 1 h i j c d p n k l m detail of lead end f 2 f 1 m 71 72 47 94 24 23 48 1 g 2 s q r
186 m pd75237 14. recommeded soldering conditions the m pd75237 should be soldered and mounted under the conditions recommended in the table below. for soldering methods and conditions other than those recommended below, contact our salesman. table 14-1 list of recommended soldering conditions table 14-2 soldering conditions * for the storage period after dry-pack decompression, storage conditions are max. 25 c, 65% rh. note use of more than one soldering method should be avoided (except in the case of pin part heating). remarks for details of recommended soldering conditions for the surface mounting type, refer to the document semiconductor device mount technology (iei-1207) . product name package recommended condition symbol ws60-107-1 ir30-107-1 vp15-107-1 pin part heating m pD75237GJ- -5bg 94-pin plastic qfp recommended condition symbol soldering conditions solder bath temperature: 260 c or less duration: 10 sec. max. number of times: once time limit: 7 days * (thereafter 10 hours prebaking required at 125 c) preheating temperature: 120 c max. (package surface temperature) package peak temperature: 230 c duration: 30 sec. max. (at 210 c or above) number of times: once time limit: 7 days * (thereafter 10 hours prebaking required at 125 c) package peak temperature: 215 c duration: 40 sec. max. (at 200 c or above) number of times: once time limit: 7 days * (thereafter 10 hours prebaking required at 125 c) pin part temperature: 300 c or less duration: 3 sec. max. (per device side) soldering method wave soldering infrared reflow vps pin part heating ws60-107-1 ir30-107-1 vp15-107-1 pin part heating h
187 m pd75237 appendix a. list of m pd75238 series product functions product name 0.95 m s/1.91 m s/ 15.3 m s (operation at 4.19 mhz) 0.95 m s/1.91 m s/ 3.82 m s/15.3 m s (operation at 4.19 mhz) main system clock selected 0.67 m s/1.33 m s/2.67 m s/10.7 m s (operation at 6.0 mhz) instruction cycle subsystem clock selected 122 m s (operation at 32.768 khz) total 33 64 input 8 16 input/output 20: 8 for led drive 24: 12 for led drive ouptut 5 24 i/o line fip dual-function pin included and fip dedicated pin excluded item m pd75217 m pd75236 m pd75237 m pd75238 m pd75p238 rom 24448 8 16256 8 24448 8 32640 8 ram 768 4 1024 4 a/d converter none 8: 8-bit resolution high-voltage output 26: 40 v max. 34: 40 v max. no. of segments 9 to 16 segments 9 to 24 segments no. of digits 9 to 16 digits fip controller/ driver timer 4 channels 5 channels 1 channel 3-wire interrupt source 10 11 operating temperature range C40 to +85 c C40 to +70 c operating voltage 2.7 to 6.0 v sbi/3-wire 3-wire 2 channels serial interface 94-pin plastic qfp package 64-pin plastic shrink dip 64-pin plastic qfp 94-pin plastic qfp 94-pin ceramic lcc with window h
188 m pd75237 supply medium 3.5-inch 2hd m s5a13ra75x 5-inch 2hd m s5a10ra75x 5-inch 2hc m s7b10ra75x pa-75p238gj hardware prom programmer which can easily program representative 256k-bit to 1m-bit proms and single-chip microcomputers with on-chip prom from the keyboard or by remote control by connecting a board provided and a separately sold socket board. prom programmer adapter for m pd75p238 used in connection with pg-1500. pg-1500 is connected to the host machine via serial and parallel interfaces to control the pg- 1500 on the host machine. os supply medium host machine 3.5-inch 2hd m s5a13pg1500 5-inch 2hd m s5a10pg1500 pc-9800 series ibm pc series 5-inch 2hc m s7b10pg1500 software pc dos (ver.3.1) ordering code (product name) ordering code (product name) pg-1500 pg-1500 controller h appendix b. development tools the following development tools are available for the development of systems using the m pd75237. language processor prom write tools os host machine pc-9800 series ms-dos ? ver.3.10 to ver.3.30c ibm pc series ra75x relocatable assembler pc dos ? (ver.3.1) ms-dos ver.3.10 to ver.3.30c
189 m pd75237 debugging tools hardware the ie-75000-r is an in-circuit emulator corresponding to the 75x series. use the ie-75000-r and emulation probe in combinations for the development of m pd75237. debugging can be carried out efficiently by connecting the ie-75000-r to the host machine and the prom programmer. the ie-75000-r-em is an emulation board for the ie-75000-r and ie-75001-r. it is incorpo- rated in the ie-75000-r. use the ie-75000-r-em and ie-75000-r or ie-75001-r in combinations for the evaluation of m pd75237. the ie-75001-r is an in-circuit emulator corresponding to the 75x series. use the ie-75001-r and emulation board ie-75000-r-em which is sold separately, and emulation probe in combinations for the development of m pd75237. debugging can be carried out efficiently by connecting the ie-75001-r to the host machine and the prom programmer. emulation probe for m pd75237 (94-pin plastic qfp). used in combination with the ie-75000-r or ie-75001-r. 94-pin conversion socket ev-9200g-94 is also provided to facilitate connection with the user system. ie-75000-r * ie-75000-r-em ie-75001-r ie-9200g-94 controls the ie-75000-r and ie-75001-r on the host machine with the ie-75000-r and ie- 75001-r, connected to the host machine via rs-232-c. ep-75238gj-r os supply medium host machine 3.5-inch 2hd m s5a13ie75x 5-inch 2hd m s5a10ie75x pc-9800 series pc dos (ver.3.1) ibm pc series 5-inch 2hc m s7b10ie75x software ie control program * maintenance product ordering code (product name) ms-dos ver.3.10 to ver.3.30c
190 m pd75237 ep-75238gj-r + pa-75p238gj pg-1500 pg-1500 controller ie-75000-r ie-75001-r *1 ie-75000-r-em rs-232-c *2 in-circuit emulator emulation probe user system on-chip prom product prom programmer programmer adapter relocatable assembler ie control program host machine pc-9800 series ibm pc series symbolic debugging possible centronics i/f pd75p238gj/kf m development tool configuration *1. the ie-75001-r does not incorporate the ie-75000- r-em (sold separately). 2. ev-9200g-94
[memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. fip is a trademark of nec corporation. ms-dos ? is a trademark of microsoft corporation. pc dos ? is a trademark of ibm corporation. ? m pd75237

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