corporation signal processing excellence 159 description the sp7514 and hs3140 are precision 14-bit multiplying dacs, that provide four-quadrant multiplication. both parts accept both ac and dc reference voltages. the sp7514 is available for use in commercial and industrial temperature ranges, packaged in a 20-pin soic. the hs3140 is available in commercial and military temperature ranges, packaged in a 20-pin side-brazed dip. n monolithic construction n 14Cbit resolution n 0.003% non-linearity n four-quadrant multiplication n latch-up protected n low power - 30mw n single +15v power supply 96k 96k 48k 6k 20 17 switches are shown in the high state 1 i out 1 r feedback bit 14 lsb 7 6 5 4 bit 1 (msb) bit 2 bit 3 bit 4 4 to 16 decode 3 18 gnd v dd v ref 19 15 equal sections 2 i out 2 96k 96k sp7514 sp7514, hs3140 corporation signal processing excellence sp7514 and hs3140 14-bit multiplying dacs
corporation signal processing excellence 160 specifications (typical @ 25 c, nominal power supply, v ref = +10v, unipolar unless otherwise noted) parameter min. typ. max. units conditions digital input resolution 14 bits 2Cquad, unipolar coding binary 4Cquad, bipolar coding offset binary logic compatibility cmos, ttl note 1 input current 1 m a reference input voltage range 25 v note 2 input impedance 3.25 9.75 kohms analog output scale factor 75 225 m a/v ref scale factor accuracy 1 % note 3 output leakage 10 na note 4 output capacitance c out 1, all inputs high 100 pf c out 1, all inputs low 50 pf c out 2, all inputs high 50 pf c out 2, all inputs low 100 pf static performance integral linearity note 5 sp7514kn/bn, hs3140C4 0.003 0.006 % fsr sp7514jn/an, hs3140C3 0.006 0.012 % fsr differential linearity note 6 sp7514kn/bn, hs3140C4 0.003 0.006 %fsr sp7514jn/an, hs3140C3 0.006 0.012 % fsr monotonicity sp7514kn/bn, hs3140C4 guaranteed to 14 bits sp7514jn/an, hs3140C3 guaranteed to 13 bits stability (t min to t max ) scale factor 4 ppm fsr/ c note 7 and 8 integral linearity 0.5 1.0 ppm fsr/ c differential linearity 0.5 1.0 ppm fsr/ c monotonicity temp. range sp7514jn/kn , hs3140c 0 +70 c sp7514an/bn C40 +85 c hs3140b C55 +125 c dynamic performance digital small signal settling 1.0 m s digital full scale settling 2.0 m s reference feedthrough error (v ref = 20vpp) @ 1khz 200 m v @ 10khz 2 mv reference input bandwidth 1 mhz power supply (v dd ) operating voltage +15 5% v voltage range +8 +18 v current 2.0 ma note 9 rejection ratio 0.005 %/%
corporation signal processing excellence 161 0.048% 0.024% 0.012% 0.006% 0.003% 4 linearity - % 6 8 10 12 14 16 18 v dd -volts linearity vs. supply voltage 2.5 4 10 i 6 8 10 12 14 16 18 2.0 1.5 1.0 dd -ma v dd -volts power supply current vs. voltage 0.048 0.024 0.012 0.006 0.003 0.01 0.1 1 10 integral linearity error - % v ref -volts integral linearity error vs. reference voltage 50 40 30 20 10 0 01020304050 2 lsb 1 lsb 1/2 lsb @ 16 bits linearity error - ppm v os -mv additional linearity error vs. output-amplifier offset-voltage (v ref = + 10v) 0.01 4 gain change - % 6 8 10 12 14 16 18 0.004 0.002 0 v dd -volts 0.008 0.006 gain change vs. supply voltage characteristic curves (typical @ + 25 c, v dd = + 15vdc, v ref = + 10vdc, unless otherwise noted) specifications (continued) (typical @ 25 c, nominal power supply, v ref = +10v, unipolar unless otherwise noted) parameter min. typ. max. units conditions environmental and mechanical operating temperature sp7514jn/kn 0 +70 c sp7514an/bn C40 +85 c hs3140Cc 0 +70 c hs3140Cb C55 +125 c hs3140Cb/883 C55 +125 c storage temperature C65 +150 c package sp7514_n 20-pin soic hs3140 20Cpin sideCbrazed dip notes: 1. digital input voltage must not exceed supply voltage or go below C0.5v ; 0 <0.8v; 2.4v < 1 v dd. 2. ac or dc; use r6758C1 for fixed reference applications 3. using the internal feedback resistor and an external op amp. the scale factor can be adjusted externally by variable resistors in series with the reference input and/or in series to the internal feedback resistor. please refer to the applications information section. 4. at 25 c; the output leakage current will create an offset voltage at the external op amps output. it doubles every 10 c temperature increase. 5. integral linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input combination. 6. differential linearity is the deviation of an output step form the theoretical value of 1lsb for any two adjacent digital input codes. 7. at 25 c, the output leakage current will create an offset voltage output. it doubles every 10 c temperature increase. 8. using the internal feedback resistor and an external op amp. 9. use series 470ohm resistor to limit start-up current.
corporation signal processing excellence 162 pin assignments pin 1 C io 1 C current output 1. pin 2 C io 2 C current output 2. pin 3 C gnd C ground. pin 4 C db 13 C msb, data bit 1. pin 5 C db 12 C data bit 2. pin 6 C db 11 C data bit 3. pin 7 C db 10 C data bit 4. pin 8 C db 9 C data bit 5. pin 9 C db 8 C data bit 6. pin 10 C db 7 C data bit 7. pin 11 C db 6 C data bit 8. pin 12 C db 5 C data bit 9. pin 13 C db 4 C data bit 10. pin 14 C db 3 C data bit 11. pin 15 C db 2 C data bit 12. pin 16 C db 1 C data bit 13. pin 17 C db 0 C lsb, data bit 14. pin 18 C v dd C positive supply voltage. pin 19 C v ref C reference voltage input. pin 20 C r fb C feedback resistor. principles of operation the sp7514/hs3140 achieve high accuracy by using a decoded or segmented dac scheme to implement this function. the following is a brief description of this approach. the most common technique for building a d/a converter of n bits is to use n switches to turn n current or voltage sources on or off. the n switches and n sources are designed so that each switch or bit contrib- utes twice as much to the d/a converters output as the preceding bit. this technique is commonly known as binary weighting and allows an n-bit converter to generate 2 n output levels by turning on the proper combination of bits. in such binary-weighted converter, the switch with the smallest contribution (the lsb) accounts for only 2 -n of the converters full-scale value. similarly, the switch with the largest contribution (the msb) accounts for 2 -1 or half of the converters full-scale output. thus it is easy to see that a given percent change in the msb will have a greater effect on the converters output than would a similar percent change in the lsb. for example, a 1% change in the lsb of a 10 bit converter would only affect the output by 0.001% of full-scale. a 1% change in the msb of the same converter would affect the output by 0.5% of fsr. in order to overcome the problem which results from the large weighting of the msb, the two msbs can be decoded to three equally weighted sources. table 1 shows that all combinations of the two msbs of a converter result in four output levels. so by replacing the two msbs with three bits equally weighted at 1/ 4 full-scale and decoding the two msb digital inputs into three lines which drive the equally weighted bits, the same functional performance can be obtained. thus by replacing the two msb switches of a conven- tional converter with three switches properly de- coded, the contribution of any switch is reduced from 1/2 to 1/4. this reduction in sensitivity also reduces the features the sp7514 and hs3140 are precision 14-bit multi- plying dacs. the dacs are implemented as a one- chip cmos circuit with a resistor ladder network. three output lines are provided on the dacs to allow unipolar and bipolar output connection with a mini- mum of external components. the feedback resistor is internal. the resistor ladder network termination is externally available, thus eliminating an external re- sistor for the 1 lsb offset in bipolar mode. the sp7514 is available for use in commercial and industrial temperature ranges, packaged in a 20-pin soic. the hs3140 is available in commercial and military temperature ranges, packaged in a 20Cpin sideCbrazed dip. for product processed and screened to the requirements of milCmC 38510 and milCstdC883c, please consult the factory ( hs3140b only). figure 1. sp7514/hs3140 equivalent output circuit + e o c f c r p r f c o r i v ref
corporation signal processing excellence 163 2 - 1 (msb) 2 - 2 output 00 0 0 1 1/4 full-scale 1 0 1/2 full-scale 1 1 3/4 full-scale table 1. contribution of the two msb's v ref v dd 470 w digital
inputs r feedback i o1 + - i o2 gnd r os a v out sp7514
hs3140 200 w 400 w figure 2. unipolar operation accuracy required of any switch for a given overall converter accuracy. with the decoded converter described above, a 1% change in any of the converters switches will affect the output by no more than 0.25% of full-scale as compared to 0.5% for a conventional converter. in other words the conventional d/a converter can be made less sensitive to the quality of its individual bits by decoding. in the sp7514/hs3140 the first four msbs are decoded into 16 levels which drive 15 equally weighted current sources. the sensitivity of each switch on the output is reduced by a factor of 8. each of the 15 sources contributes 6.25% output change rather than an msb change of 50% for the common approach. following the decoded section of the dac a standard binary weighted r-2r approach is used. this divides each of the 16 levels (or 6.25% of f.s.) into 4096 discrete levels (the 12 lsbs). output capacitance the sp7514/hs3140 have very low output capaci- tance (c o ). this is specified both with all switches on and all switches off. output capacitance varies from 50pf to 100pf over all input codes. this low capaci- tance is due in part to the decoding technique used. smaller switches are used with resulting less capaci- tance. three important system characteristics are affected by c o and d c o ; namely digital feedthrough, settling time, and bandwidth. the dac output equiva- lent circuit can be represented as shown in figure 1 . digital feedthrough is the change in analog output due to the toggling conditions on the converter input data lines when the analog input v ref is at 0v. the sp7514/hs3140 very low c o and therefore will yield low digital feedthrough. inputs to the dac can be buffered. this input latch with microprocessor control is shown in figure 4 . settling time is directly affected by c o . in figure 1 , c o combines with r f to add a pole to the open loop response, reducing bandwidth and causing excessive phase shift - which could result in ringing and/or oscillation. a feedback capacitor, c f must be added to restore stability. even with c f , there is still a zero-pole mismatch due to r i c o which is code dependent. this code dependent mismatch is minimized when c o r i = r f c f . however c f must now be made larger to compensate for worst case d r i c o - resulting in re- duced bandwidth and increased settling time. with the sp7514/hs3140, small values for c f must be used. digital
inputs r feedback i o1 + - i o2 gnd r os1 a v out 1
+ - a 2 r os2 v out1 a 1 , a 2 , op-07 4k w 4k w r os2 r 200 w v ref v dd 470 w 400 w sp7514
hs3140 figure 3. bipolar operation transfer function (n=14) binary input unipolar output bipolar output 111...111 Cv ref (1 - 2 Cn )Cv ref (1 C 2 C(n C 1) ) 100...001 Cv ref (1/2 + 2 Cn )Cv ref (2 C(n C 1) ) 100...000 Cv ref /2 0 011...111 Cv ref (1/2 C 2 Cn )v ref (2 C(n C 1) ) 000001 Cv ref (2 (n C 1) )v ref (1 C 2 C(n C 1) ) 000...000 0 v ref table 2. transfer function
corporation signal processing excellence 164 figure 4. microprocessor interface to sp7514/hs3140 d0 d1 d2 d3 d4 d5 d6 d7 clk 74273 v ref (+ 25v max) lsb 15 14 13 12 11 10 9 sp7514/ 7516 d0 d1 d2 d3 d4 d5 d6 d7 74273 clk msb gnd 8 7 6 5 4 3 2 latches address decoder g2a 74ls138 g2b c b a d0 d1 d2 d3 d4 d5 d6 d7 + 200 470 3 dd v 400 wr bdsel a 2 a 1 a 0 v ref v dd + r i 01 i 02 unipolar mode (2-quadrant) 6 2 3 a 1 v out 0 to - v ref (1-2 - n ) r 0s f resistor r p can be added, this will parallel r j decreas- ing the effective resistance. if c f is reduced the bandwidth will be increased and settling time de- creased. however a system penalty for lowering c f is to increase noise gain. the trade-off is noise vs. settling time. if r p is added then a large value (1 m f or greater) non-polarized capacitor c p should be added in series with r p to eliminate any dc drifts. if settling time is not important, eliminate r p and c p , and adjust c f to prevent overshoot. output offset in most applications, the output of the dac is fed into an amplifier to convert the dacs current output to voltage. a little known and not commonly discussed parameter is the linearity error versus offset voltage of the output amplifier. all cmos dacs must operate into a virtual ground, i.e., the summing junction of an op amp. any amplifiers offset from the amplifier will appear as an error at the output (which can be related to lsbs of error). most all cmos dacs currently available are imple- mented using an r-2r ladder network. the formula for nonlinearity is typically 0.67mv/mv os (not de- rived here). however the sp7516 has a coefficient of only 0.065mv/mvos. this is due to the decoding technique described earlier. cmos dac applica- tions notes (including this one) always show a poten- tiometer used to null out the amplifiers offset. if an amplifier is chosen having pretrimmed offset it may be possible to eliminate this component. consider the following calculations: sp7514/ hs3140 1. using lf441a amplifier (low power - 741 pinout) 2. specified offset: 0.5mv max 3. temperature coefficient of input offset: 10 m v/ c max v os max (0 c to 70 c) = 0.5mv + (70 m v)10 = 1.2mv add'l nonlinearity (max.) = 1.2mv x 0.065mv/mv = 78 m v (1/2 lsb @ 16 bits) where: 78 m v = 1/2 lsb @ 16 bits (10v range) via the above configuration, the sp7514/hs3140 can be used to divide an analog signal by digital code (i.e. for digitally controlled gain). the transfer func- tion is given in table 2, where the value of each bit is 0 or 1. division by all 0s is undefined and causes the op amp to saturate. applications information unipolar operation figure 2 shows the interconnections for unipolar operation. connect i o1 and fb 1 as shown in diagram. tie i o2 (pin 7), fb 3 (pin 3), and fb 4 (pin 1) to ground (pin 8). as shown, a series resistor is recommended in the v dd supply line to limit current during turn-on. to maintain specified linearity, external amplifiers must be zeroed. apply an all zeroes digital input and adjust r os for v out = 0 1mv. the sp7514 and hs3140 have been used successfully with op-07, op-27 and lf441a. for high speed applications the sp2525 is recommended. bipolar operation figure 3 shows the interconnections for bipolar op- eration. connect i o1 , i o2 , fb 1 , fb 3 , fb 4 as shown in diagram. tie ldtr to i o2 . as shown, a series resistor is recommended in the v dd supply line to limit current during turn-on. to maintain specified linearity, exter- nal amplifiers must be zeroed. this is best done with v ref set to zero and, the dac register loaded with 10...0 (msb = 1). set r 0s1 for v 01 = 0. set r 0s2 for v out = 0. set v ref to +10v and adjust r b for v out to be 0v. grounding connect all gnd pins to system analog ground and tie this to digital ground. all unused input pins must be grounded.
corporation signal processing excellence 165 ordering information model ................................................................ monotonicity .................................. temperature range .................................... package double-buffered 12-bit multiplying dac hs3140c-3q ............................................................ 13-bit ............................................... 0 c to +70 c ................... 20-pin, 0.3" side-brazed dip hs3140b-3q ............................................................ 13-bit ......................................... -55 c to +125 c ................... 20-pin, 0.3" side-brazed dip hs3140b-3/883 ....................................................... 13-bit ......................................... -55 c to +125 c ................... 20-pin, 0.3" side-brazed dip hs3140c-4q ............................................................ 14-bit ............................................... 0 c to +70 c ................... 20-pin, 0.3" side-brazed dip hs3140b-4q ............................................................ 14-bit ......................................... -55 c to +125 c ................... 20-pin, 0.3" side-brazed dip hs3140b-4/883 ....................................................... 14-bit ......................................... -55 c to +125 c ................... 20-pin, 0.3" side-brazed dip sp7514jn ................................................................ 13-bit ............................................... 0 c to +70 c ...................................... 20-pin, 0.3" soic sp7514kn ............................................................... 14-bit ............................................... 0 c to +70 c ...................................... 20-pin, 0.3" soic sp7514an ............................................................... 13-bit .......................................... C40 c to +85 c ...................................... 20-pin, 0.3" soic sp7514bn ............................................................... 14-bit .......................................... C40 c to +85 c ...................................... 20-pin, 0.3" soic
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