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synchronous , step - down dc - to - dc controller with voltage tracking and synchronization data sheet ADP1853 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features input v oltage range: 2.75 v to 20 v output v oltage range: 0.6 v to 90% v in maximu m output current of more than 25 a current mode architecture with current sense input configurable to voltage mode 1% output voltage accuracy over temperature voltage tracking input programmable frequency: 200 khz to 1.5 mhz synchronization input internal clock output power saving mode at light load precision enable input power good with internal pull - up resistor adjustable soft s tart programmable current sense gain integrated bootstrap diode starts into a precharged load externally adjustable slope compensation suitable for any output capacitor overvoltage and overcurrent - limit protection thermal overload protection input undervoltage l ockout (uvlo) availab le in 20 - lead , 4 mm 4 mm lfcsp supported by adisimpower ? d esign t ool applications intermediate bus and pol systems requiring se quencing and tracking, including telecom b ase station and n etworking industrial and instrumentation medical and h ealthcare general description the ADP1853 is a wide range input , dc - to - dc , synchronous buck contr oller capable of running from commonly used 3.3 v to 12 v (up to 20 v) voltage inputs. the device nominally operates in current mode with valley current sensing providing the fastest step response for digital loads. it can also be configured as a voltage m ode controller with low noise and crosstalk for sensitive loads. the ADP1853 can be used as a master synchronization clock for the power system and for convenient synchronization between controllers. the clkou t signal can synchronize other devices in the adp185x family such that slave devices are phase - shifted from the master to reduce th e input ripple current, improve emi , and reduce the size of the input bulk capacitance. the ADP1853 can also be configured as a slave device for current sharing. additionally, t he ADP1853 includes accurate tracking , precision enable, and power g ood functions for sequencing. the ADP1853 provides a high speed, high peak current gate driving capability to enable energy efficient power conversion. t he device can be configured to operate in power saving mode by skipping pulses, reducing swit ching losses and improving efficiency at light load and standby conditions. the accurate current limit allows design within a narrower range of tolerances and can reduce overall converter size and cost. the ad p1853 can regulate down to 0.6 v output using a high accuracy reference with 1% tolerance over the temperature range from ? 40 c to 125 c. with a wide range input voltage, the ADP1853 is designed to provide th e designer with maximum flexibility for use in a variety of system configurations ; loop compensation, soft start, frequen cy setting, power saving mode, current limit , and current sense gain can all be programmed using external components. in addition, the external ramp resistor allows choosing optimal slope and v in feedforward in both current and voltage mode for excellent line rejection. the linear regulator and the b oot strap diode for the high - side drive r are internal. protection features include undervolta ge lock out, overvoltage, over current/short circuit , and overtemperature. figure 1. typical operation circuit vin m2 m1 fb sw pgnd vin l dh bst dl r csg r ramp ramp pgood sync trk ss ilim en comp clkout freq vcco vout ADP1853 hi lo cs agnd v ma 10594-001
ADP1853 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 simplified block diagram ............................................................... 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 12 control architecture .................................................................. 12 oscillat or frequency .................................................................. 12 synchronization .......................................................................... 13 pwm or pulse skip mode of operation ................................. 13 clkout signal .......................................................................... 13 synchronous re ctifier and dead time ................................... 14 input undervoltage lockout ..................................................... 14 internal linear regulator .......................................................... 14 overvolage protection ............................................................... 14 power good ................................................................................. 14 short - circuit and current - limit protection .......................... 15 enable/disable control ............................................................. 15 thermal overload protection .................................................. 16 interleaved dual - phase operation .......................................... 16 applications information .............................................................. 17 adisimpower design tool ....................................................... 17 setting the output voltage ........................................................ 17 so ft start ...................................................................................... 17 setting the current limit .......................................................... 17 accurate current - limit sensing .............................................. 17 input capacitor selection .......................................................... 17 vi n pin filter ............................................................................. 18 boost capacitor selection ......................................................... 18 inductor selection ...................................................................... 18 output capacitor selection ....................................................... 18 mo sfet selection ..................................................................... 19 loop compensation voltage mode ...................................... 20 loop compensation current mode ..................................... 21 switching noise and overshoot reduction ............................ 23 voltage tracking ......................................................................... 23 pcb layout guidlines ............................................................... 24 typical operating circuits ............................................................ 25 outline dimensions ....................................................................... 27 ordering g uide .......................................................................... 27 revision history 5/12 revision 0: initial version
data sheet ADP1853 rev. 0 | page 3 of 28 specifications all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). v in = 12 v . the specifications are valid for t j = ? 40 c to +1 25c, unless otherwise specified. typical values are at t a = 25c . table 1 . parameter symbol test conditions /comments min typ max unit power supply input voltage v in 2.75 20 v undervoltage lockout threshold uvlo trsh v in rising 2.5 5 2.6 5 2.75 v v in falling 2.35 2. 4 5 2.50 v undervoltage lockout hysteresis uvlo hyst 0. 2 v quiescent current i in en = v in = 12 v, v fb = v cco in forced pulse width modulation ( pwm ) mode (no switching) 4.2 5 .7 ma en = v in = 12 v, v fb = v cco in psm mode 2.5 ma shutdown current i in_sd en = gnd, v in = 5.5 v or 20 v 100 200 a error amplifier fb input bias current i fb ?100 +1 +100 na open - loop gain 1 80 db gain - bandwidth product 1 20 mhz trk input bias current i trk 0 v v trk 5 v ?100 +1 +100 na current sense amplifier gain a cs gain resistor connected to dl, r csg = 47 k? 5% 2. 6 3 3. 4 v/v gain resistor connected to dl, r csg = 22 k? 5% 5.2 6 6. 8 v/v default setting, r csg = open 10.5 12 13.5 v/v voltage mode operation, resistor dl to pgnd , r csg = 100 k? 5% 0 v/v output characterictistics feedback accuracy voltage v fb t j = ?4 0 c to +85c 597 6 00 603 m v t j = ?40 c to +125c 594 6 00 606 m v line regulation of pwm v fb /v in 0.015 %/v load regulation of pwm 1 v fb /v comp v comp range = 0.9 v to 2.2 v 0.3 % oscillator frequency f osc r freq = 332 k? to agnd 170 200 230 khz r freq = 78.7 k? to agnd 7 20 800 8 80 khz r freq = 40 .2 k? to agnd 1275 1500 1725 khz freq to agnd 2 40 300 3 60 khz freq to vcco 4 80 600 720 khz sync input frequency range 1 f sync r freq range from 332 k? to 40 .2 k? 170 1725 khz sync input pulse width 1 t syncmin 100 ns sync pin capacitance to gnd c sync 5 pf clkout frequency range 1 f clkout f osc range from 170 khz to 1725 khz 170 1725 khz clkout pulse duty cycle d clkout 50 % clkout rise and fall time c clkout = 47 pf 10 ns linear regulator vcco output voltage i vcco = 100 ma 4.7 5.0 5. 3 v vcco load regulation i vcco = 0 ma to 100 ma 35 mv vcco line regulation v in = 5.5 v to 20 v, i vcco = 20 ma 10 mv vcco current limit 1 vcco drops to 4 v from 5 v 350 ma vcco short - circuit current 1 vcco < 0.5 v 370 400 ma vin to vcco dropout voltage 2 v dropout i vcco = 100 ma, v in 5 v 0.33 v
ADP1853 data sheet rev. 0 | page 4 of 28 parameter symbol test conditions /comments min typ max unit logic input s en en rising 0.57 0.63 0.68 v en hysteresis 0.03 v en input leakage current i en v in = 2.75 v to 20 v 1 200 na sync logic input low 1.3 v sync logic input high 1.9 v sync input pull - down resistance r sync 1 m? gate drivers dh rise time c dh = 3 n f, v bst ? v sw = 5 v 16 ns dh fall time c dh = 3 n f, v bst ? v sw = 5 v 14 ns dl rise time c dl = 3 nf 16 ns dl fall time c dl = 3 nf 14 ns dh to dl dead time external 3 nf is connected to dh and dl 25 ns dh or dl driver r on , sourcing current 1 r on_sourc e sourcing 2 a with a 100 ns pulse 2 ? sourcing 1 a with a 100 ns pulse, v in = 3 v 2.3 ? dh or dl driver r on , tempco tc ron v in = 3 v or 12 v 0.3 %/ o c dh or dl driver r on , sinking current 1 r on_sink sinking 2 a with a 100 ns pulse 1.5 ? sinking 1 a with a 100 ns pulse, v in = 3 v 2 ? dh maximum duty cycle 1 f osc = 300 khz 90 % dh maximum duty cycle 1 f osc = 1500 khz 50 % minimum dh on time f osc = 200 khz to 1500 khz 85 ns minimum dh off time f osc = 200 khz to 1500 khz 3 45 ns minimum dl on time f osc = 200 khz to 1500 khz 2 95 ns comp voltage range comp pulse skip threshold v comp,thres in pulse skip mode (psm) 0.9 v comp clamp high voltage v comp,high 2.2 v thermal shutdown thermal shutdown threshold t tmsd 155 c thermal shutdown hysteresis 20 c overvoltage and power good thresholds fb overvoltage threshold v ov v fb rising 0.630 0.65 0.670 v fb overvoltage hysteresis 18 mv fb undervoltage threshold v uv v fb falling 0.525 0.55 0.575 v fb undervoltage hysteresis 15 mv trk input voltage range 1 0 5 v fb to trk offset voltage trk = 0.1 v to 0.57 v ; o ffset = v fb ? v trk ?10 0 + 10 mv soft start ss output current i ss during start up 4.6 6.5 8.4 a ss pull - down resistor during a fault condition 3 k? fb to ss offset v ss = 0.1 v to 0.6 v; o ffset = v fb ? v ss ? 10 + 10 mv
data sheet ADP1853 rev. 0 | page 5 of 28 parameter symbol test conditions /comments min typ max unit pgood pgood pull - up resistor r pgood internal pull - up resistor to vcco 12.5 k? pgood delay 12 s overv oltage or under v oltage minimum duration this is the minimum duration required to trip the pgood signal 1 0 s ilim threshold voltage 1 relative to pgnd ? 5 0 +5 mv ilim output current ilim = pgnd 45 50 55 a current sense blanking period after dl goes high, current limit is not sensed during this period 100 ns integrated rectifier (boost diode) resistance at 20 ma forward current 16 ? zero current cross offset (sw to pgnd) 1 in pulse skip mode only ; f osc = 3 00 khz 0 2 4 mv 1 guaranteed by design. 2 connect v in to vcco when v in < 5.5 v.
ADP1853 data sheet rev. 0 | page 6 of 28 absolute maximum rat ings table 2 . parameter rating vin, en, ramp 21 v fb, comp, ss, trk, freq, sync, vcco, pgood, clkout ? 0.3 v to +6 v ilim, sw, cs to pgnd ? 0.3 v to +21 v bst, dh to pgnd ?0.3 v to +28 v dl to pgnd ?0.3 v to vcco + 0.3 v bst to sw ?0.3 v to +6 v bst to pgnd to pgnd 20 ns transients 32 v sw, cs to pgnd 20 ns transients 25 v dl, sw, cs, ilim to pgnd 20 ns negative transients ?8 v pgnd to a gnd ? 0.3 v to + 0.3 v pgnd to a gnd 20 ns transients ?8 v to +4 v ja (natural convection ) 1, 2 40 c/w operating junction temperature range 3 ?40 c to +125c storage temperature range ? 65c to +150c maximum soldering lead temperature 260c 1 measured with exposed pad attached to pcb. 2 junction - to - ambient thermal resistance ( ja ) of the pack age was calculated or simulated on multilayer pcb. 3 the junction temperature ( t j ) of the device is depen dent on the ambient temperature ( t a ) the power dissipation of the device ( p d ) and the junction to ambient th ermal resistance of the package ( ja ). maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula t j = t a + p d ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified , all other voltages are referenced to gnd. esd caution
data sheet ADP1853 rev. 0 | page 7 of 28 s implified block d iagram figure 2. bst pgnd + ? + ? + ? + ? fb ov_th uv_th pgood current sense amplifier dh dl ilim sw v ref = 0.6v + + ? error amplifier fb comp ss pwm comparator slope compensation and ramp generator current-limit control ramp 50a ov + trk cs gain driver logic control and state machine over_lim pulse skip over_lim ldo logic en vin uvlo oscillator freq sync ref vcco ov uv 0.6v thermal shutdown agnd cs fault ov logic over_lim ov en en_sw logic uv 3k? 0.9v dcm *0 (zero) gain is for voltage mode with ramp from 0.7v to 2.2v. zero cross detect 12.5k? a v = 0 , * 3, 6, 12 vcco clk en_sw 1m? ? + clkout vcco vcco vcco vcco slave sl_th fb slave 0.6v 6.5a 10594-002
ADP1853 data sheet rev. 0 | page 8 of 28 pin configuration an d function descripti ons figure 3. pin configuration table 3 . pin function descriptions pin no. mnemonic description 1 en enable input. drive en high to turn on the controller, and d rive en low to turn the controller off. tie en to v in for automatic startup. for a precision uvlo, put an appropriately sized resistor divider from v in to agnd, and tie the midpoint to this pin. 2 ss soft start input. connect a capacitor from ss to agnd to set the soft start period. this nod e is internally pulled up to v cco through a 6.5 a current source. 3 fb output voltage feedback . connect t h is pin to an output via a resistor divider. tie fb to vcco for slave mode operation in interleaved dual - phase configuration. 4 comp compensation node. output of the error amplifier. connect a resistor - capacitor network from comp to fb to compensate the regulation control loop. in interleaved dual - phase configuration, t ie this pin to the comp pin of the second channel. 5 agnd analog ground. connect to th e system agnd plane. 6 sync frequency synchronization input. this pin a cce pts an external clock signal with a frequency close to 1 the internal oscillator frequency, f osc , set by the freq pin . the controller operates in forced pwm when a periodic clock s ignal is detected at sync or when sync is high. the re sulting switching frequency is 1 the sync frequency. when sync is low or left floating, the controller operates in pulse skip mode. 7 clkout internal clock output . the clkout is 1 the internal oscillator or input sync signal frequency, 180 phase - shifted. this pin can be used to synchronize another ADP1853 or other controllers. 8 vin connect to main power supply. bypass with a 1 f or larger ceramic capacitor connected as clo se to this pin as possible and a gnd. 9 vcco output of the internal low dropout regulator (ldo). the internal circuitry and gate drivers are powered from vcco. bypass vcco to agnd with a 1 f or larger ceramic capa citor. the vcco output remains active even when en is low. for operations at v in below 5 v, v in may be jumped to vcco. do not use the ldo to pow er other auxiliary system loads. 10 pgnd power ground. ground for internal driver. differential current . 11 dl low - side synchronous rect ifier gate driver output. to program the gain of the current sense amplifier in a current mode or to set voltage mode control , connect a resistor between dl and pgnd . this pin is c apable of driving mosfets with a total input cap acitance up to 20 nf. 12 cs current sense amplifier input . differenti al current is sensed between cs and pgnd . connect this pin to the current sense resistor or to the sw pin to sense the current. tie this pin to pgnd for voltage mode operation. 13 sw power switch node. connect this pin to the source of the high - side n - channel mosfet and the drain of the low - side n - channel mosfet. 14 dh high - side switch gate driver output. this pin is c apable of driving mosfets with a total input capacitance up to 20 nf. 15 bst boot strapped upper rail of high - side internal driver. connect a 0.1 f to a 0.22 f multilayer ceram ic capacitor (mlcc) between bst and sw . the re is an internal boost diode rectifier connected between vcco and bst . 16 ilim current - limit sense comparator inverting input. connect a resistor between ilim and sw to set the current - limit offset. for accurate curr ent - limit sensing, connect ilim to a current sense resistor at the source of the low - side mosfet. 14 1 3 12 1 3 4 dh 15 bst notes 1. connect the bottom of the exposed pad to the system agnd plane. sw cs 1 1 dl en fb 2 ss com p 5 agnd 7 clkout 6 sync 8 vin 9 vcco 10 pgnd 19 freq 20 trk 18 ram p 17 pgood 16 ilim ADP1853 top view 10594-003
data sheet ADP1853 rev. 0 | page 9 of 28 pin no. mnemonic description 17 pgood power good. the o pen - drain power good indicator logic output with an internal 12 .5 k? r esistor is connected between pgood and vcco. pgood is pulled to ground when the output is outside the regulation window. an external pull - up resistor is not required. if the controller is configur ed as a slave in the interleaved dual - phase application by tying the fb pin high to vcco, the pulse skip mode is enabled by driving the pgood pin low externally in case s wh en the master is in pulse skip mode at light loads. otherwise, if the master is conf igured to forced pwm operation, pgood of the slave controller must be connected to the pgood of the master . 18 ramp programmable current setting for slope compensation. co nnect a resistor from ram p to v in . the voltage at ramp is 0.2 v during operation. this pin is high impedance when the channel is disabled. 19 freq internal oscillator frequency , f osc . sets the desired operating frequency between 200 khz and 1.5 mhz with one r esistor between freq and agnd. connect freq to agnd for a preprogrammed 300 khz or tie freq to vcco for 600 khz operating frequency. 20 trk tracking input . connect trk to vcco if tracking is not used. epad exposed pad. connect the bottom of the exposed pad to the system agnd plane.
ADP1853 data sheet rev. 0 | page 10 of 28 typical performance characteristics figure 4. efficiency plot 12 v in to 3. 3 v out , 300 khz , see figure 36 for circuit figure 5. 10 a to 20 a load step , 12 v in to 3.3 v out , 300 khz , current mode figure 6. 9 v to 15 v line step , 3.3 v out , 15 a load, c urrent mode figure 7. efficiency plot 15 v in to 5 v out , 600 khz , see figure 35 for circuit figure 8. 10 a to 20 a load step , 12 v in to 3.3 v out , 300 khz , v oltage mode figure 9. 9 v to 15 v line step , 3.3 v out , 15 a load, voltage mode pulse skip forced pwm 100 90 80 70 60 50 40 30 20 10 0 efficienc y (%) 0.1 1 10 100 load (a) 10594-004 ch2 200mv m 100 s 5.0ms/s 200ns/pt a ch4 14.2 a 2 4 ch4 10 a ? b w b w load current vout_ac 10594-006 ch2 100mv m 100 s 250ms/s 4ns/pt a ch1 12.6v 1 2 ch1 5v b w b w vin vout_ac 10594-008 pulse skip forced pwm 100 90 80 70 60 50 40 30 20 10 0 efficienc y (%) 0.1 1 10 100 load (a) 10594-005 ch2 200mv m 100 s 5.0ms/s 200ns/pt a ch4 14.2 a 4 2 ch4 10 a ? b w b w load current vout_ac 10594-007 ch2 100mv m 100 s 250ms/s 4ns/pt a ch1 12.6v 1 2 ch1 5v b w b w vin vout_ac 10594-009
data sheet ADP1853 rev. 0 | page 11 of 28 figure 10 . synchronization and clkout , f sync = 300 khz figure 11 . dead time vs. temperature figure 12 . typical dh minimum on time and off time figure 13 . soft s tart with precharged output , 3.3 v out forced pwm figure 14 . dead time vs. v in figure 15 . driver resistance vs. temperature ch3 10v m 1.0 s 1.25gs/s 400ps/pt a ch1 3.6v 1 2 3 ch1 5v b w b w ch2 5v b w clkout dh sync 10594-016 25 35 34 33 32 31 30 29 28 27 26 ?40 ?20 0 20 40 60 80 100 120 140 dead time (ns) temperature (c) v in = 12v output is loaded hs fet = bsc080n03ls ls fet = bsc030n03ls dead time between sw falling edge and dl rising edge, including diode recovery time 10594-0 1 1 50 100 150 200 250 300 350 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 time (ns) dh m i n i m u m o ff t i m e dh m i n i m u m o n t i m e v in (v) 10594-012 ch3 10v m 2ms 250ks/s 4 s/pt a ch1 560mv 1 2 3 ch1 2v b w ch2 1v b w b w en vout sw 10594-017 25 45 43 41 39 37 35 33 31 29 27 0 20 15 10 5 dead time (ns) v in (v) t a = 25c output is loaded hs fet = bsc080n03ls ls fet = bsc030n03ls dead time between sw falling edge and dl rising edge, including diode recovery time 10594-014 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?40 ?15 10 35 60 85 110 135 driver resistance (?) temperature ( c) v in = 2.75v, sourcing v in = 12v, sourcing v in = 2.75v, sinking v in = 12v, sinking 10594-015
ADP1853 data sheet rev. 0 | page 12 of 28 theory of operation the ADP1853 is a fixed frequency , step - down , synchronous switching controller with integrated drivers and bootstrapping for external n - channel power mosfets. the current mode control loop can also be configured into the voltage mode. the controller can be set to operate in pulse skip mode for power saving at a light load or in forced pwm. the ADP1853 includes programmable soft start, output overvoltage protection, pro - grammable current limit, power good, and tracking function s. the controller can operate at a switching frequency between 200 khz and 1.5 mhz that is programmed with a resistor or synchronized to an external clock. it also has the internal clock out signal that can be used to synchronize other devices. c ontrol a rchitecture the ADP1853 is based on a fixed frequency, emulated peak current mode, pwm control architecture. the inductor current is sensed by the voltage drop measured across the external low - side mosfet, r dson , or across the sense resistor placed in series between the low - side mosfet source and the power ground. the current is sensed during the off period of the switching cycle and is conditioned with the internal current sense amplifier. t he gain of the current sense amplifier is pro - gramm able to 3 v/v, 6 v/v, or 12 v/v during the controller power - up initialization before the device start s switching. a 47 k? resistor between dl and pgnd programs the gain of 3 v/v; a 22 k? resistor sets a gain of 6 v/v. without a resistor, the gain is programmed to 12 v/v. the output signal of the current sense amplifier is held, added to the emulated current ramp in the next switching cycle during the dh on time, and fed into the pwm comparator, as shown in figure 16 . this signal is compared with the comp signal from the error amplifier and resets the flip - flop, which generates the pwm pulse. if voltage mode control is selected by placing a 100 k? resistor between dl and pgnd, the emulated ramp is fed to the pwm comparator without adding the current sense signal. figure 16 . simplified control architecture as shown in figure 16 , the emulated current ramp is generated inside the ic, but offers programmability through the ramp pin. selecting an appropriate value resistor between v in to the ramp pin programs a desired slope compensation value, and at the same time, provides a v in feed forward featu re. control logic enforces anti shoot - through operation to limit cross conduction of the internal drivers and external mosfets. oscillator f requency the internal oscillator frequency, which ranges from 200 khz to 1.5 mhz, is set by an external resistor, r freq , at the freq pin. some popular f osc values are shown in table 4 , and a graph ical relationship is shown in figure 17 . for instance, a 78.7 k? resistor sets the oscillator frequency to 800 khz. furthermore, connecting freq to agnd or freq to vcco sets the oscil lator frequency to 300 khz or 600 khz, respectively. for other frequencies that are not listed in table 4 , the values of r freq and f osc can be obtained from figure 17 , or use the following empirical formula to calculate these values: 065 . 1 ) khz ( 568 , 96 ) k ( ? = osc freq f r table 4 . setting the oscillator frequency r freq f osc (typical) 332 k? 200 khz 78.7 k? 800 khz 60.4 k? 1000 khz 51 k? 1200 khz 40.2 k? 1500 khz freq to agnd 300 khz freq to vcco 600 khz figure 17 . r freq vs. f osc ff osc q q r s a cs v cs v in v in a r i ramp r ramp c r f r o m e rr o r a m p to drivers c s p g n d 10594-022 410 r freq (k ?) 360 310 260 210 160 1 10 60 10 100 400 700 1000 1300 1600 1900 f osc (khz) r freq n? f osc (khz) ?1.065 10594-023
data sheet ADP1853 rev. 0 | page 13 of 28 synchronization the switching frequency of the ADP1853 can be synchronized to an external clock signal by connecting it to the sync pin. the internal oscillator frequency, programmed by the resistor at the freq pin must be set close to the external clock frequency; therefore, the external clock frequency may vary between 0.85 and 1 .3 of the internal clock set . the resulting switching frequency is 1 of the external sync frequency . when synchronized , the ADP1853 operates in pwm . when an external clock is detected at the first sync edge, the internal oscillator is reset, and the clock control shifts to sync. the sync edges then trigger subsequent clocking of the pwm outputs. the dh rising edg e appears approximately 100 ns after the corresponding sync edge, and the frequency is locked to the external signal. if the external sync signal disappears during operation, the ADP1853 reverts to its internal oscillator. when the sync function is used, it is recommended to connect a pull - up resist or from sync to vcco so that when the sync signal is lost, the ADP1853 continues to operate in pwm. pwm or pulse s kip mo de of operation the sync pin is a multifunctional pin. pwm mode is enabled when sync is connected to vcco or a high logic. with sync connected to ground or left floating, pulse skip mode is enabled. switching sync from low to high or high to low on the fly causes the controller to transition from forced pwm to pulse skip mode or from pulse skip mode to forced pwm, respec tively, in two clock cycles. table 5 . mode of operation sync pin mode of operation low pulse skip mode high forced pwm no connect pulse skip mode clock signal forced pwm the ADP1853 has pulse skip sensing circuitry that allows the controller to skip pwm pulses, reducing the switching frequency at light loads and, therefore, maintaining better efficiency during a light load operation. the resulting output ripple is larger than that of the fixed frequency forced pwm. figure 18 shows the ADP1853 operating i n psm under a light load. pulse skip frequency und er a light load is dependent on the inductor , output capacitance, output load, and input and output voltages. figure 18 . example of pulse skip mode under a light loa d when the output load is greater than the pu lse skip threshold current, that is, when v comp reaches the threshold of 0.9 v , the ADP1853 exits the pulse skip mode of operation and enters the fixed frequency discontinuous conduction mode (dcm), as shown in figure 19 . when the load increases further, the ADP1853 enters continuous conduction mode ( ccm ) . figure 19 . example of discontinuous conduction mode (dcm) waveform in forced pwm, the ADP1853 always operates in ccm at any load; therefore, the inducto r current is always continuous . clkout s ignal the ADP1853 has a clock output , clkout, which can be used for synchronizing other ADP1853 controllers, thus eliminating the need for an external clock source. t he clko ut frequency is 1 the internal oscillator frequency, f osc , and is 180 out of phase. ch2 200mv ch1 10v m200 s a ch1 7.8v 1 3 4 2 ch3 20mv ch4 2 a ? sw com p (ch2) vout ripple induc t or current 10594-024 ch2 5v ch1 10v m1s a ch1 13.4v 1 3 4 2 ch3 20mv ch4 2 a ? dh dl output ripple induc t or current 10594-025
ADP1853 data sheet rev. 0 | page 14 of 28 s ynchronous r ectifier and d ead t ime in the ADP1853 , the antishoot - through circuit monitors the dh to sw and dl to pgnd voltages and adjusts the low - side and high - side drivers to ensure break - before - make switching that prevents cross - conduction or shoot - through between the high - side and low - side mosfets. this break - before - make switching is known as dead time, which is not fixed and depends on how fast the mosfets are turned on and off. in a typical application circuit that uses medium sized mosfets with an input capacitance of approximately 3 nf, the typic al dead time is approximately 25 ns. when small and fast mos f e ts with fast diode recovery time s are used, the dead time can be as low as 13 ns. input u ndervoltage l ockout when the bias input voltage at the v in pin is less than the undervoltage lockout (uvlo) threshold of 2.6 v typical , the swit ch drivers stay inac tive. if en is high, the controller start s switching and the vin pin voltage exceeds the uvlo threshold. i nternal l inear r egulator the internal linear regulator is a low dropout (ldo) vcco . vcco powers up the internal control circuitry and provides power f or the gate drivers. it is guaranteed to have more than 200 ma of output current capability, which is sufficient to handle the gate drive r requirements of typical logic threshold mosfets driven at up to 1.5 mhz. vcco is always active and cannot be shut do wn by the en signal ; however, the over - temperature protection event disables the ldo together with the controller. bypass vcco to agnd with a 1 f or greater capacitor. because the ldo supplies the gate drive r current, the output of vcco is subject to shar p transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. the ldo has been optimized to handle these transients without overload faults. due to the gate drive loading, using the vcco output for other external auxiliary system load s is not recommended. the ldo includes a current limit that is well above the expected maximum gate drive r load. this current limit also includes a short - circuit foldback to further limit the vcco current in the event of a short - circuit fault. for an input voltage of less than 5.5 v, it is recommended to bypass the ldo by connecting vin to vcco, as shown in figure 20 , thus eliminating the dropout voltage. however, if the input range is 4 v to 7 v, the ldo cannot be bypassed by shorting vin to vcco because the 7 v input has exceeded the maximum voltage rating of the vcco pin. in thi s case, use the ldo to drive the internal drivers, but keep in mind that there is a dropout when v in is less t h a n 5 v. figure 20 . configuration for v in < 5.5 v o vervolage p rotection the ADP1853 has a built - in circuit for detecting output over - voltage at the fb node. when the fb voltage, v fb , rises above the overvoltage threshold , the high - side n - channel mosfet ( nmosfet ) is turned off , and the low - side nmosfet is turned on until the v fb drops below the undervoltage threshold. this action is known as the crowbar overvoltage protection. if the overvoltage condition is not removed, the controller maintains the feedback voltage between the overvoltage and undervoltage thresholds, and the ou tput is regul ated to within typically +8% and ?8% of the regulation voltage. during an overvoltage event, the ss node discharges t oward zero through an internal 3 k? pull - down resistor. when the voltage at fb drops below the undervoltage threshold, the sof t start sequence restarts. figure 21 shows the overvoltage protection scheme in action in psm. figure 21 . overvoltage protection in psm pow er g ood the pgood pin is an open - drain nmosfet with an internal 12.5 k? pull - up resistor connected between pgood and vcco. pgood is internally pulled up to vcco during normal operation and is active low when tripped. when the feedback voltage, v fb , rises a bove the overvoltage threshold or drops below the un dervoltage threshold, the pgood output is pulled to ground after a delay of 12 s. the overvoltage or undervoltage condition must exist for more than 10 s for pgood to become active. the pgood output also becomes active if a thermal overload condition is detected. ADP1853 v i n v in = 2.75v to 5.5v v cc o 10594-026 ch 1 20 v ch 2 5 v ch 3 1 v ch 4 10 v m 100 s a ch 1 10 v 1 2 4 3 d h p goo d v o u t = 1 . 8 v s h o r t e d t o 2 v s o urc e v i n 10594-027
data sheet ADP1853 rev. 0 | page 15 of 28 s hort - c ircuit and current - l imit p rotection when the output is shorted or the output cu rrent exceeds the current limit set by the current - limit setting r es istor ( between ilim and cs ) for eight consecutive cycles, the ADP1853 shuts off both the high - side and low - side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. the ss no de discharg es to zero through an internal 3 k? resistor during an overcurrent or short - circuit event. figure 22 shows that the ADP1853 on a high current application circ uit maintains current - limit hiccup mode when the output is shorted. figure 22 . current - limit hiccup mode, 20 a current limit enable/ d isable c ontrol the en pin is used to enable or disable the controller ADP1853 ; the precision enable typical thresho ld is 0.63 v. when the voltage at en rises above the threshold voltage , the controller is enabled and starts normal operatio n after initialization of the internal osci llator, references, settings, and the soft start period. w hen the voltage at en drops to typically 30 mv (hysteresis) below the threshold voltage, the driver and the internal controller circuits in the ADP1853 are turned off. the initial settings are still valid; therefore re - enabling the controller does not change the settings until the power at the vin pin is cycled. in addition , the en signal does not shut down the ldo at vcco, which is always active when v in is above the uvlo threshold . for the purpose of start - up power sequencing, the startup of the ADP1853 can be programmed by connecting an appropriate resistor divider from the master power supply to the en pin, as shown in figure 23 . for instance, if the desired start - up voltage from the master power supply is 10 v, r1 and r2 can be set to 156 k? and 10 k? , respectively. figure 23 . optional power - up sequencing circuit ch1 10v m2ms a ch1 1 1.2v 1 3 4 ch3 500mv ch4 10 a ? sw ss inductor current 10594-028 ADP1853 f b e n r top r bot v out r 1 r 2 master supply voltage 10594-029
ADP1853 data sheet rev. 0 | page 16 of 28 t hermal o verload p rotection the ADP1853 has an internal temperature sensor that senses the junction temperature of the chip. when the junction temperature of the ADP1853 reaches approximately 155c, the ADP1853 goes into thermal shutdown, the converter is turned off, and ss discharges toward ze ro through an internal 3 k? resistor. at the same time, vcco discharges to zero. when the junction temperature drops below 135c, the ADP1853 resumes normal operation after the soft start sequence. i nterleaved dual - p hase o peration two ADP1853 controllers can be configured to design a dual - phase , interleaved , step - down , switching dc - to - dc regulators. in dual - phase operation, the two outputs of the switching regulators are tied together and can source more than 50 a of output current depending on the selection of the power components. see figure 24 for a configuration of a typical dual - phase application circuit. note that only one error amplifier, in the master ADP1853 , works; the error amplifier in t he slave ADP1853 output is turned to tristate by tying fb to vcco. the clkout signal from the m aster is connected to the sync input of the s lave controller; the ss signals of the master and slave are tied together; comp of the slave must be tied to comp of the master; and pgood of the slave must be tied to pgood of the master. figure 24 . dual - phase application vin m2 m1 fb sw pgnd v in l1 dh bst dl r csg r ramp ramp pgood sync trk ss ilim en comp clkout freq vcco v out ADP1853 cs agnd master vin m4 m3 fb sw pgnd v in l2 dh bst dl r csg r ramp ramp pgood sync trk ss ilim en comp clkout freq vcco ADP1853 cs agnd slave 10594-030
data sheet ADP1853 rev. 0 | page 17 of 28 applications information adi sim p ower design tool the ADP1853 is supported by the adisimpower design tool set. adisimpower is a collection of tools that produce complete power designs optimized to a specific design goal. the tools allow the user to generate a full schematic, bill of materials, and calculate performance in minutes. adisimpower can optimize designs for cost, ar ea, efficiency, and parts count while taking into consideration the operating conditions and limitations of the ic and all real external components. the adisimpower tool can be found at www.analog.com/adisi mpower and the user can request an unpopulated board through the tool. setting the o utput v oltage the output voltage is set using a resistive voltage divider from the output to fb. for r bot , use a 1 k to 20 k resistor. choose r top to set the output volta ge by using the following equation: ? ? ? ? ? ? ? ? ? = fb fb out bot top v v v r r where: r top is the high - side voltage divider resistance. r bot is the low - side voltage divider resistance. v out is the regulated output voltage. v fb is the feedback regulation threshold, 0.6 v. soft s tart the soft start period is set by an external capacitor between ss and agnd. the soft start function limits the input in rush current and prevents output overshoot. when en is enabled, a current source of 6.5 a starts charging the capacitor, and the regulation voltage is reached whe n the voltage at ss reaches 0.6 v. the soft start time is approximated by ss ss c t a 5 . 6 v 6 . 0 = the ss pin reaches a final voltage equal to vcco. when a controller is disabled, for instanc e, if en is pulled low or ex periences an overcurrent limit condition, the soft start capacitor is discharged throu gh an internal 3 k? pull - down resistor. s etting the c urrent l imit the current - limit comparator measures the voltage across the low - side mosfet to determine the load curre nt. the current limi t is set by an external current - limit resistor, r ilim , between ilim and cs. the current sense pin, ilim, sources nominally 50 a to this external resistor. this creates an offset voltage of r ilim multiplied by 50 a . when the drop across the current sense element r cs (a sense resistor or low - side mosfet, r dson ) is equal to or greater than this offset voltage, the ADP1853 flags a current - limit event. a 50 06 . 1 cs lpk ilim r i r = where: i lpk is the peak inductor current. a ccurate c urrent - l imit s ensing r dson of the mosfet can vary by more than 50% over the temperature range. accu rate current - limit sensing is achieved by adding a current sense resistor from the source of the low - si de mosfet to pgnd. make sure that the power rating of the current sense resistor is adequate for the application . figure 25 illustrates the implementation of accurate current - limit sensing. figure 25 . accurate current - limit sensing i nput c apacitor s election u se two parallel capac itors pl aced close to the drain of the high - side switch mosfet (one bulk capacitor of sufficiently high current rating and a 10 f ceramic decoupling capacitor). select an input bulk capacitor based on its ripple current rating. the minimum input capacitance req uired for a particular load is sw esr o pp o min in f dr i v d d i c ) ( ) 1 ( , ? ? = where: i o is the output current . d is the duty cycle . v pp is the desired input ripple voltage. r esr is the equivalent series resistance of the capacitor s. v in ADP1853 dh cs ilim dl r ilim r sense 10594-031
ADP1853 data sheet rev. 0 | page 18 of 28 vin p in f ilter i t is recommended to have a low - pass filter at the vin pin. connecting a resistor, between 2 ? an d 10 ?, in series with vin and a 1 f ceramic capacitor between vin and agnd creates a low - pass filter that effectively filters out any unwanted glitches caused by the switching regulator. k eep in mind that the input current could be larger than 100 ma when driving la rge mosfets. a 100 ma across a 10 ? resistor creates a 1 v drop, which is the same voltage drop in vcco. in this case, a lower resistor value is desirable. figure 26 . input filter configuration b oost c apacitor s election connect a boost capacitor between the sw and bst pin s to provid e the current for the high - side driver during switching. choose a ceramic capacitor with a value b etween 0.1 f and 0.22 f. i nductor s election for most applications, c hoose an inductor value such that the inductor ripple current is between 20% and 40% of the maximum dc output load current. choose the inductor value by the following equation: in out l sw out in v v i f v v l ? ? = where: l is the inductor value. f sw is the switching frequency. v out is the output voltage. v in is the input voltage. ? i l is the peak - to - peak inductor ripple current. check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak inductor current of a particular design. o utput c apacitor s election for maximum allowed switching ripple at the output, choose an output capacitor that is larger than ) ) 4 ( ( 1 8 2 2 2 2 esl sw esr l out sw l out l f r i v f i c ? ? ? ? ? ? where: ? v out is the target maximum output ripple voltage. ? i l is the inductor ripple current. r esr is the equivalent series resistance of the output capacitor (or the parallel combination of esr of all output capacitors). l esl is the equivalent series inductance of t he output capacitor (or the parallel combination of esl of all capacitors). the impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. the impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (esr), and the equivalent series inductance (esl). usually th e capacitor impedance is dominated by esr. the maximum esr rating of the capacitor , such as in electrolytic or polymer capacitors, is provided in the manufacturers data sheet; therefore, the output ripple reduces to esr l out r i v ? ? ? electrolytic capacitors also have significant esl, on the order of 5 nh to 20 nh, depending on ty pe, size, and geometry. pcb traces contribute some esr and esl, as well. however, using the maximum esr rating from the capacitor data sheet usually provides some margin such that measuring the esl may not be required. in the case of output capacitors whe re the impedance of the esr and esl are small at the switching frequency, for instance, where the output capacit or is a bank of parallel mlcc capaci - tors, the ca pacitive impedance dominates, so the output capacitance must be larger than sw out l out f v i c ? ? ? 8 make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. to meet the requirement o f the output voltage overshoot during load release, t he output capacitance should be larger than 2 2 2 ) ( out overshoot out step out v v v l i c ? ? + ? ? where: ? v overshoot is the maximum allowed overshoot . select the largest output capacitance given by either of the previous two equations. vin v in agnd 2 ? t o 10 ? 1 f ADP1853 10594-032
data sheet ADP1853 rev. 0 | page 19 of 28 mosfet s election the choice of mosfet directly affects the dc - to - dc converter performance. a mo sfet with low on resistance reduces i 2 r losses, and low gate charge reduces transition losses. the mosfet should have low thermal resistance to ensure that the power dissipated in the mosfet does not result in excessive mosfet die temperature. the high - sid e mosfet carries the load current during on time and usually carries most of the transition losses of the converter. typically, the lower the on resistance of the mosfet, the higher the gate charge and vice versa. therefore, it is important to choose a hig h - side mosfet that balances the two losses. the conduction loss of the high - side mosfet is determined by the equation dson rms load c r i p = 2 ) ( ) ( where: r dson is the mosfet on resistance. the gate charging loss is approximated by the equation sw g pv g f q v p ? w here : v pv is the gate driver supply voltage. q g is the mosfet total gate charge. note that the gate charging power loss is not dissipated in the mosfet but rather in the ADP1853 internal drivers. this power loss should be taken into consideration when calculating the overall power efficiency. the high - side mosfet transition loss is approximated by the equation 2 ) ( sw f r load in t f t t i v p + ? where: p t is the high - side mosfet switching los s power. t r is the rise time in charging the high - side mosfet. t f is the fall time in discharging the high - side mosfet. t r and t f can be estimated by rise driver gsw r i q t _ ? fall driver gsw f i q t _ ? where: q gsw is the gate charge of the mosfet during switching and is given in the mosfet data sheet. i driver_rise and i driver_fall are the driver current out put from the ADP1853 internal gate drivers. if q gsw is not given in the data sheet, it can be approximated by 2 gs gd gsw q q q + ? where: q gd and q gs are the gate - to - drain an d gate - to - source charges given in the mosfet data sheet. i driver_rise and i dri ver _fall can be estimated by gate source on sp dd rise driver r r v v i + ? ? _ _ gate sink on sp fall driver r r v i + ? _ _ where: v dd is the input supply voltage to the driver and is between 2.75 v and 5 v, depending on the input voltage. v sp is the switching point where the mosfet fully conducts; this voltage can be estimated by inspecting the gate charge graph given in the mosfet data sheet. r on_source is the on resistance of the ADP1853 internal driver, given in table 1 , when charging the mosfet. r on_sink is the on resistance of the ADP1853 internal driver, given in table 1 , when discharging the mosfet. r gate is the on gate resistance of mosfet given in the mosfet data sheet. if an external gate resistor is added, add this external resistance to r gate . the total power dissipation of the high - side mosfet is the sum of conduction and transition losses: t c hs p p p + ? the synchronous rectifier, or low - side mosfet, carries the inductor current when the high - side mosfet is off. the low - side mosfet transition loss is small and can be neglected in the calculat ion. for high input voltage and low output voltage, the low - side mosfet carries the current most of the time. therefore, to achieve high efficiency, it is critical to optimize the low - side mosfet for low on resistance. in cases where the power loss exceed s the mosfet rating or lower resistance is required than is available in a single mosfet, connect multiple low - side mosfets in parallel. the equation for low - side mosfet conduction power loss is dson rms load cls r i p = 2 ) ( ) (
ADP1853 data sheet rev. 0 | page 20 of 28 there is also additional power loss during the time, known as dead time, between the turn - off of the high - side switch and the turn - on of the low - side switch, when the body diode of the low - side mosfet conducts the output current. the power loss in the body diode is given by o sw d f bodydiode i f t v p = where: v f is the forward voltage drop of the body diode, typically 0.7 v. t d is the dead time in the ADP1853 , typically 30 ns when drivi ng a medium size mosfets with input capacitanc e, c iss , of approximately 3 nf. the dead time is not fixed. its effective value varies with gate drive resistance and c iss ; therefore, p bodydiode increases in high load current designs and low voltage designs. then the power loss in the low - side mosfet is bodydiode cls ls p p p + = note that mosfet on resistance , r dson , increases with increasing tempera ture with a typical temperature coefficient of 0.4%/ o c. the mosfet junction temperature (t j ) rise over the ambient temperature is t j = t a + ja p d where: ja is the thermal resistance of the mosfet package. t a is the ambient temperature. p d is the total power dissipated in the mosfet. loop compensation v oltage m ode set the controller to voltage mode operation by placing a 100 k? resistor between dl and pgnd. chose the larger possible ramp amplitude for the voltage mode below 1.5 v. the ramp voltage is programmed by a resistor value between v in and the ramp pin : ramp sw in ramp v f v r ? = pf 100 v 2 . 0 the voltage at the ramp pin is fixed at 0.2 v, and the current going in to ramp should be between 10 a and 160 a. make sure that the following condition is satisfied: a 160 v 2 . 0 a 10 ? ramp in r v (1 ) for instance, with an input voltage of 12 v, r ramp should not be less than 73.8 k?. assuming that the lc filter design is complete, the feedback control system can be compensated. in general, aluminum electro lytic capacitors have high esr ; h owever, if several aluminum electrolytic capacitors are connected in parallel and produce a low effective esr, then type iii compensation is needed. in addition, ceramic capacitors have very low esr (only a few milliohms) making type iii compensation a better choice. type iii compensation igure type iii compensation if the output capacitor esr zero frequency is greater than ? of the crossover frequency, use the type iii compensator as shown in figure 27. c alculate t he output lc filter resonant frequency as follows : lc f lc 2 1 = (2 ) chose a crossover frequency that is 1/10 of the switching frequency: 10 sw co f f = (3 ) set the poles and zeros as follows: sw p2 p1 f f f 2 1 = = (4 ) i z sw co z2 z1 c r f f f f 2 1 40 4 = = = = (5 ) or i z lc z2 z1 c r f f f 2 1 2 = = = (6 ) use the lower zero frequency from equation 5 or equation 6 . calculate the compensator resistor, r z , as follows: 2 lc in co z1 ramp top z f v f f v r r = (7 ) next, calculate c i : z1 z i f r c = 2 1 (8 ) because of the finite output current drive of the error amplifier, c i needs to be less than 10 nf. if it is larger than 10 nf, choose a larger r top and recalculate r z and c i until c i is less than 10 nf. g ( d b ) p ha se ? 9 0 ?270 f z f p c h f c i r z r ff r t o p r b o t v o u t internal v r ef ea fb comp ?1 s l o pe ?1 s l o pe c ff + 1 s l o pe 10594-033
data sheet ADP1853 rev. 0 | page 21 of 28 because c hf << c i , calculate c hf as follows: z sw hf r f c = 1 (9 ) next, calculate the fe edforward capacitor , c ff , a ssuming r ff << r top : sw ff ff f c r = 1 (10 ) check that the calculated component values are reasonable. for instance, capacitors smaller than about 10 pf should be avoided . in addition, r z values less than 3 k and c i values greater than 10 nf should be avoided. if necessary, recalculate the comp ensation network with a different starting value for r top . if r z is too small or c i is too big, start with a larger value f or r top . this compensation technique should yield a g ood working solution. when precise compensation is needed, use the adisimpower d esign t ool . loop compensation c urrent m ode compensate the ADP1853 error voltage loop in current mode using type ii compensation. setting the s lope c ompensation in a current - mode control topology, slope compensation is needed to prevent subharmonic oscillations in the inductor current and to maintain a stable output. the external slope compensation is implemented by summing the amplified sense signal and a scaled voltage at the ramp pin. to set the effective slope compensation, connect a resistor ( r ramp ) between the ramp pin and the input voltage ( v in ). r ramp is calculate d by cs cs ramp r a l r = 6 10 7 where: l is the inductor value measured in h. r cs (m?) is resistance of the current sense element between cs and pgnd (for instance, r dson_max is the low - si de mosfet maximum on resistance). a cs is the current sense amplifier gai n and is 3 v / v, 6 v / v, or 12 v/v . thus , the voltage ramp amplitude , v ramp , is: ramp sw in ramp r f v v ? = pf 100 v 2 . 0 where 100 pf is the effective capacitance of the internal ramp capacitor , c ramp , with 4% tolerance over the temperature and v in range. the voltage at the ramp pin is fixed at 0.2 v, and the current going in to ramp should be between 10 a and 160 a. make sure that the following condition is satisfied: a 160 v 2 . 0 a 10 ? ramp in r v for instance, with an input voltage o f 12 v, r ramp should not exceed 1.1 m?. if the calculated r ramp produces less than 10 a , then select an r ramp value that produces between 10 a and 15 a . figure 28 illustrates the connection of the slope compensation resistor , r ramp , and the current sense gain resistor , r csg . figure 28 . slope compensation and cs gain connectio n ADP1853 d h c s i l i m d l r ilim r csg ramp r ramp v in 10594-034
ADP1853 data sheet rev. 0 | page 22 of 28 setting the current sense gain the voltage drop across the external low-side mosfet is sensed by a current sense amplifier by multiplying the peak inductor current and the r dson of the mosfet. the result is then amplified by a gain factor of 3 v/v, 6 v/v, or 12 v/v, which is programmable by an external resistor, r csg , connected to the dl pin. this gain is sensed only during power-up and not during normal operation. the amplified voltage is summed with the slope compensation ramp voltage and fed into the pwm controller for a stable regulation voltage. the voltage range of the internal node, v cs , is between 0.4 v and 2.2 v. select the current sense gain such that the internal minimum amplified voltage (v csmin ) is above 0.4 v and the maximum amplified voltage (v csmax ) is 2.1 v. note that v csmin or v csmax is not the same as v comp , which has a range of 0.85 v to 2.2 v. make sure that the maximum v comp (v compmax ) does not exceed 2.2 v to account for temperature and part-to-part variations. see the following equations for v csmin , v csmax , and v compmax : cs min dson l csmin a ri v ? ??? _ 2 1 v75.0 cs max dson l loadmax csmax a ri i v ? ?? ?? _ ) 2 1 (v75.0 csmax ramp on in compmax v r t v v ? ? ?? ? pf100 )v2.0( where: v csmin is the minimum amplified voltage of the internal current sense amplifier at zero output current. i l is the peak-to-peak ripple current in the inductor. r dson_min is the low-side mosfet minimum on resistance. the zero current level voltage of the current sense amplifier is 0.75 v. v csmax is the maximum amplified voltage of the internal current sense amplifier at the maximum output current. i loadmax is the maximum output dc load current. v compmax is the maximum voltage at the comp pin. t on is the high-side driver (dh) on time. replace r dson with the resistance value of the current sense element, r cs , if it is used. type ii compensation figure 29. type ii compensation in this case, use the circuit shown in figure 29. calculate the compensation resistor, r z , with the following equation: co out s top z fcrrr ? ? ? ? ? 2 (11) where: f co is chosen to be 1/10 of f sw . r s = a cs r dson_min . a cs is the current sense gain of either 3 v/v, 6 v/v, or 12 v/v, set by the gain resistor between dl and pgnd. r dson_min is the low-side mosfet minimum on resistance. if the current is sensed on a current sense resistor, r cs , then r cs becomes cscss rar ? ? next, choose the compensation capacitor to set the compensa- tion zero, f z1 , to the lesser of 1/5 of the crossover frequency or ? of the lc resonant frequency i z sw co z1 cr ff f ? 2 1 505 ??? (12) or i z lc z1 cr f f ? 2 1 2 ?? (13) solving for c i in equation 12 yields sw z i fr c ? 25 ? (14) solving for c i in equation 13 yields lc z i fr c ? 1 ? (15) g (db) phase ?180 ?270 f z f p c hf c i r z r top r bot v out internal vref ea fb comp ? 1 s l o p e ? 1 s l o p e 10594-035
data sheet ADP1853 rev. 0 | page 23 of 28 use the larger value of c i from equation 14 or equation 15. because of the finite output current drive of the error amplifier, c i needs to be less than 1 0 nf. if it is larger than 10 nf, choose a larger r top and recalculate r z and c i until c i is less than 10 nf. next, choose the high frequency pole, f p1 , to be ? of f sw . sw p1 f f 2 1 = ( 16) because c hf << c i , hf z p1 c r f = 2 1 ( 17) combine equation 16 and equation 17 , and solve for c hf , z sw hf r f c = 1 (18 ) for maximally precise compensation solutions , use the adisimpower d esign t ool . s witching n oise and o vershoot r eduction to reduce voltage ri nging and noise, it is recommended to add an rc snubber between sw and pgnd for high current applications , as illustrated in figure 30. in most a pplications, r snub is typically 2 ? to 4 ?, and c snub is typically 1.2 nf to 3 nf. the size of the rc snubber components must be chosen correctly to handle the power dissipation. the power dissipated in r snub is sw snub in snub f c v p = 2 in most applications , a component size of 0805 for r snub is sufficient . the rc snubber does not reduce the voltage over - shoot. a resistor, shown as r rise in figure 30, at the bst pin helps to reduce overshoot and is generally between 2 ? and 4 ?. adding a resistor in series, typically between 2 ? and 4 ?, with the gate driver also helps to reduce oversho ot. if a gate resistor is added, then r rise is not needed. figure 30 . application circuit with a snubber v oltage t racking the ADP1853 includes a tracking feature that tracks a master voltage. in all tracking configurations, the output can be set as low as 0.6 v for a given operating condition. the soft start time setting of the master voltage should be longer than the soft start of the slave voltage. this forces the rise time of the master voltage to be i mposed on the slave voltage . if the soft start setting of the slave voltage is longer, the slave comes up more slowly, and the tracking relation s hip is not seen at the output. two track ing configurations are possible with the ADP1853 : coincident and ratiometric tracking. coincident tracking the most common application is coincident tracking, used in core vs. i/o voltage sequencing and simil ar applica tions. coincident tracking force s the ramp rate of the output voltage to be the same for the master and slave until the slave output reaches its regulation. connect the slave trk input to a resistor divider from the master voltage that is the sam e as the divider used on the slave fb pin. this forces the slave voltage to be the same as the master voltage. for coincident tracking, use r trkt = r top and r trkb = r bot , as shown in figure 32. figure 31 . coincident tracking figure 32 . example of a coincident tracking circuit the ratio of the slave output voltage to the master voltage is a function of the two dividers. ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = trkb trkt bot top master out slave out r r r r v v 1 1 _ _ v in a d p 185 3 d h d l s w b s t p g n d r rise m 1 m 2 l v out c snub c out r snub 10594-036 master voltage slave voltage time voltage (v) 10594-037 ADP1853 fb s s t r k r bot n? r t o p 20k ? 1 . 1 v 3 . 3v v out_master 1 . 8 v v out_slave r trkb n? r trkt n? c ss 20nf 10594-038
ADP1853 data sheet rev. 0 | page 24 of 28 as the master voltage rises, the slave voltage rises identically. eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the trk input continues to incr ease , thus removing itself from influencing the output voltage. to ensure that the output voltage accuracy is not compromised by the trk pin being too close in voltage to the reference vol t - age (v fb , typically 0.6 v) , make sure that the final value of the trk voltage of the slave channel is at least 30 mv above v fb . ratiometric tracking ratiometric tracking limits the output voltage to a fraction of the master voltage , as illustrated in figure 33 and figure 34. the final trk voltage of the slave channel should be set to at least 30 mv below the f b voltage of the master channel. when the trk voltage of the slave channel drops to a level that i s below the minimum on time condition, the slave channel operates in pulse skip mode while keeping the output regulated and tracked to the master channel. in addition , when trk or fb drops below the pgood undervoltage threshold, the pgood signal is tripped and becomes active low. figure 33 . ratiometric tracking figure 34 . example of a ratiometric tracking circuit pcb layout g uidlines the recommended board layout practices for the synchronous buck controller are described in the an - 1119 application note . master voltage slave voltage time voltage (v) 10594-039 ADP1853 fb s s t r k r bot 10k? r t o p 2 2.6 k ? 0.55v 0.55v 3 . 3v v out_master 1 . 8 v v out_slave r trkb 10k? r trkt 49.9k? c ss 20nf 10594-040
data sheet ADP1853 rev. 0 | page 25 of 28 t ypical o perating c ircuits figure 35 . 1 5 a ci rcuit operating in current mode m2 m1 v in = 12v to 18v l 22k? 1 2 3 4 5 6 7 8 9 10 17 18 19 20 12 13 14 15 agnd freq dl cs sw dh sync vin en vcco ADP1853 16 11 bst ss comp fb trk ramp pgood ilim clkout pgnd cin cout ep to vin to vcco 1f 2? 1f 20k? 32.4k? 16pf 390pf 0.1f 0.1f 348k? f sw = 600khz c in : os-con 150f/20v, 20sep150m, sanyo + cap cer 10f 25v x7r 1210, murata grm32dr71e106ka12 l: 1.8h wurth electronik we-hci 1050 744 325 180 m1: vishay siliconix sir462dp m2: vishay siliconix sir866dp c out : poscap 100f/6.3v sanyo 6tpe100mi + 2 cap cer 22f 10v x5r 1210 murata grm32er61a226ke20l 2.74k? 1.3k? 0.003? 2w vout 5v 15a 10594-041
ADP1853 data sheet rev. 0 | page 26 of 28 figure 36 . 25 a circuit operating in voltage mode m2 m1 v in = 9v to 15v l 100k? 1 2 3 4 5 6 7 8 9 10 17 18 19 20 12 13 14 15 agnd freq dl cs sw dh sync vin en vcco ADP1853 16 11 bst ss comp fb trk ramp pgood ilim clkout pgnd cin cout ep to vin to vcco 1f 2? 1f 32.4k? 21.5k? 75pf 1600pf 0.1f 0.1f f sw = 300khz c in : os-con 150f/20v, 20sep150m, sanyo + cap cer 10f 25v x7r 1210, murata grm32dr71e106ka12 l: 1h coilcraft ser1412-102me m1: infineon bsc052n03ls m2: infineon bsc0902ns c out : poscap 330f/6.3v sanyo 6tpe330mfl + cap cer 22f 10v x5r 1210 murata grm32er61a226ke20l 7.15k? 2.74k? vout 3.3v 25a 196k? 2k? 510pf 10594-042
data sheet ADP1853 rev. 0 | page 27 of 28 outline dimensions figure 37 . 20 - lead lead f rame chip scale package [lfcsp _w q] 4 mm 4 m m body, very very thin quad (cp - 20 - 10 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADP1853 a cpz -r7 ?40c to + 12 5c 20- lead lead fr ame chip scale package [lfcsp _wq ] cp -20-10 1 z = rohs compliant part. 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant t o jedec standards mo-220-wgg d. 061609-b b o t t o m v i e w t o p v i e w e x p o s e d p a d pin 1 indi ca t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indica t or 2.65 2.50 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 2 0 6 1 0 1 1 1 5 1 6 5
ADP1853 data sheet rev. 0 | page 28 of 28 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10594 - 0 - 5/12(0)

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