600 n-channel logic level enhancement mode field effect transistor features 600v , 5.7a , r ds(on) =1 @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-220f full-pak for through hole absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 30 v -pulsed i d 5.7 a i dm a drain-source diode forward current i s 5.7 a maximum power dissipation p d w operating and storage temperautre range t j ,t stg -55 to 150 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 2.5 65 /w c /w c ? @tc=25 c derate above 25 c 50 0.4 w/ c drain current-continuous s g d 6-132 preliminary 17 CEF10N6 to-220f s d g 6
electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit drain-source avalanche rating a off characteristics drain-source breakdown voltage bv dss v gs = 0v,i d = 250 a 600 v zero gate voltage drain current i dss v ds =600v,v gs =0v 100 a gate-body leakage i gss v gs =30v,v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d = 250 a 24 v drain-source on-state resistance r ds(on) v gs =10v, i d =5a 1.0 ? on-state drain current i d(on) v gs = 10v, v ds =10v 9 a s forward transconductance fs g v ds = 40v, i d =5a switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd =300v, i d = 10a, v gs =10v r gen =25 35 70 ns ns ns ns 90 170 170 255 120 180 total gate charge gate-source charge gate-drain charge q g q gs q gd v ds =480v, i d =10a, v gs =10v 55 70 nc nc nc fall time 6-133 single pulse drain-source avalanche energy maximum drain-source avalanche current e as i as v dd =50v, l=11.8mh a mj ? CEF10N6 r g =25 ? 10 500 22 0.75 10 9 4 6
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =10a 1.6 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. [ [ 4-134 figure 1. output characteristics i d , drain current(a) i d , drain current (a) b dynamic characteristics input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =25v, v gs =0v f =1.0mh z 1500 p f 125 p f p f 50 CEF10N6 figure 2. transfer characteristics v gs , gate-to-source voltage (v) 12 10 8 6 4 2 0 0246 810 12 v gs =10,9,8,7v v g s =5 v v gs =6v 6 0.1 1 2 4 6 10 8 25 c 150 c -55 c 1.v ds =40v 2.pulse test 10
4-135 with temperature figure 6. breakdown voltage variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) with drain current i ds , drain-source current (a) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) figure 5. gate threshold variation figure 7. transconductance variation figure 3. capacitance v ds , drain-to source voltage (v) c, capacitance (pf) CEF10N6 1.30 1.20 1.10 1.0 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 3 a figure 4. on-resistance variation with temperature t j , junction temperature( c) on-resistance(ohms) r ds(on) , r ds(on) , normalized -100 -50 0 50 100 200 2.2 1.9 1.6 1.3 1.0 0.7 0.4 v gs =10v i d =5a 150 20 10 0.1 1 0.4 0.6 0.8 1.2 1.0 v gs =0v ciss coss crss 1800 1500 1200 900 600 300 0 0 5 10 15 20 25 9 12 0 3 6 0 2 46 8 v ds =40v 6
6-136 figure 11. switching test circuit figure 12. switching waveforms t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width inverted transient thermal impedance square wave pulse duration (sec) figure 13. normalized thermal transient impedance curve r(t),normalized effective v dd r d v v r s v g gs in gen out l v gs , gate to source voltage (v) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) i d , drain current (a) CEF10N6 15 12 9 6 3 0 0204060 80 v ds =480v i d =5a 6 p dm t 1 t 2 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 d=0.5 0.1 0.05 0.02 0.01 single pulse 10 10 10 1 0 -1 10 -2 10 -3 10 -4 10 -5 10 -2 10 -1 10 0 0.2 10 10 10 10 0 10 10 3 2 1 10 1 t c =25 c single pulse tj=150 c dc -1 0 10ms 1 m s 10 0 3 s rd s (on ) li mit 100 ms
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