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publication# 080212 rev: c amendment: / 0 issue date: october 1999 am79578 subscriber line interface circuit distinctive characteristics programmable constant-resistance feed programmable loop-detect threshold on-chip switching regulator for low-power dissipation programmable current limit (clp) ground-key detector two-wire impedance set by single external impedance polarity reversal feature tip open state for ground-start lines test relay driver on-hook transmission high open circuit state (hoc) block diagram vtx qbat rd rdc vreg vbat c1 c2 c3 c4 e1 vcc input decoder and control two-wire interface switching regulator test relay driver ringout testout a (tip) hpa hpb da db l bgnd chs chclk agnd 21777a-001 signal transmission power-feed controller off-hook detector ground-key detector ring-trip detector vee det rsn b(ring) ring relay driver clp cas
2 am79578 data sheet ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. am79578 temperature range package type device name/description jc subscriber line interface circuit j = 32-pin plastic leaded chip carrier (pl 032) c=commercial (0 c to 70 c)* performance grade ?1 = 52 - polarity reversal ?2 = 63 - polarity reversal ?3 = 52 - no polarity reversal ?4 = 63 - no polarity reversal note: * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ?40 c to +85 c is guaranteed by characterization and periodic sampling of production units. am79578 ?1 valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on legerity?s products. valid combinations am79578 ?1 jc ?2 ?3 ?4
slic products 3 connection diagram top view am79578 notes: 1. pin 1 is marked for orientation. 2. tp is a thermal conduction pin tied to substrate (qbat). tp testout l c4 vbat qbat chs chclk e1 ringout bgnd b(ring) a(tip) db rdc 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 vcc clp cas c3 c2 det tp da rd hpb hpa vtx vee rsn agnd/dgnd vreg c1 21777a-002
4 am79578 data sheet pin descriptions pin names type description agnd/dgnd gnd analog and digital ground are connected internally to a single pin. a(tip) output output of a(tip) power amplifier. bgnd gnd battery (power) ground. b(ring) output output of b(ring) power amplifier. c3?c1 input decoder. ttl compatible. c3 is msb and c1 is lsb. c4 input ttl compatible. a logic low enables the driver. cas capacitor anti-saturation capacitor. filters reference voltage when operating in anti-saturation region. chclk input input to switching regulator (ttl compatible). frequency = 256 khz (nominal). chs input chopper stabilization. connection for external stabilization components. clp ? current limit programming. open = 30 ma current limit, short to vee = 50 ma current limit, a resistor to vee = 30?50 ma current limit, with a programmed feed of 400 ? , including two 20 ? fuse resistors. da input ring-trip negative. negative input to ring-trip comparator. db input ring-trip positive. positive input to ring-trip comparator. det output detector. when enabled, logic low indicates that the selected detector is tripped logic inputs c3?c1 and e1 select the detector. open-collector with a built-in 15 k ? pull-up resistor. e1 input e1 = high connects the ground-key detector to det , and e1 = low connects the off-hook or ring-trip detector to det . hpa capacitor high-pass filter capacitor. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter capacitor. b(ring) side of high-pass filter capacitor. l output switching regulator power transistor. connection point for filter inductor and anode of catch diode. has up to 60 v pulse waveform; isolated from sensitive circuits. you must keep the diode connections short because of the high currents and high di/dt. qbat battery quiet battery. filtered battery supply for the signal processing circuits. rd resistor detector resistor. threshold modification and filter point for the off-hook detector. rdc resistor dc feed resistor. connection point for the dc feed current programming network, which also connects to the receiver summing node (rsn). v rdc is negative for normal polarity and positive for reverse polarity. ringout output ring relay driver. open collector darlington pull down to bgnd. rsn input receiving summing node. the metallic current (ac and dc) between a(tip) and b(ring) = 1000 x the current into this pin. the networks that program receive gain, two-wire impedance, and feed current all connect to this node. this node is extremely sensitive. route the 256 khz chopper clock and switch lines away from the rsn node. testout output test relay driver. open collector darlington pull down. tp thermal thermal pin. connection for heat dissipation. internally connected to substrate (qbat). leave as open circuit or connected to qbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation. vbat battery battery supply. connected through an external protection diode. vcc power +5 v power supply. vee power ?5 v power supply. vreg input regulated voltage. provides negative power supply for power amplifiers, connection point for inductor, filter capacitor, and chopper stabilization. vtx output transmit audio. unity gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
slic products 5 absolute maximum ratings storage temperature . . . . . . . . . . . . ? 55 c to +150 c v cc with respect to agnd/dgnd . . . ? 0.4 v to +7.0 v v ee with respect to agnd/dgnd . . .+0.4 v to ? 7.0 v v bat with respect to agnd/dgnd . . +0.4 v to ? 70 v note: rise time of v bat (dv/dt) must be limited to 27 v/ s or less when q bat bypass = 0.33 f. bgnd with respect to agnd/dgnd . . . . . . . . . . . . . . . .+1.0 v to ? 3.0 v a(tip) or b(ring) to bgnd: continuous . . . . . . . . . . . . . . . . . . ? 70 v to +1.0 v 10 ms (f = 0.1 hz) . . . . . . . . . . . . . ? 70 v to +5.0 v 1 s (f = 0.1 hz) . . . . . . . . . . . . . . . ? 90 v to +10 v 250 ns (f = 0.1 hz) . . . . . . . . . . . . ? 120 v to +15 v current from a(tip) or b(ring) . . . . . . . . . . . . 150 ma voltage on ringout. . . . bgnd to 70 v above q bat voltage on testout. . . . bgnd to 70 v above q bat current through relay drivers . . . . . . . . . . . . . . 60 ma voltage on ring-trip inputs (da and db) . . . . . . . . . . . . . . . . . . . . vbat to 0 v current into ring-trip inputs . . . . . . . . . . . . . . . . . 10 ma peak current into regulator switch (l pin). . . . 150 ma switcher transient peak off voltage on l pin. . . . . . . . . . . . . . . . . . . . . . +1.0 v c4 ? c1, e1, chclk to agnd/dgnd . . . . . . . . . . . ? 0.4 v to vcc + 0.4 v maximum power dissipation, (see note). . . .t a = 70 c in 32-pin plcc package. . . . . . . . . . . . . . . 1.74 w note: thermal limiting circuitry on-chip will shut down the circuit at a junction temperature of about 165 c. the device should never be exposed to this temperature. operation above 145 c junction temperature may degrade device reliability. see the slic packaging considerations for more information. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature . . . . . . . . . . . . . . 0 c to +70 c* v cc . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 v to 5.25 v v ee . . . . . . . . . . . . . . . . . . . . . . . . ? 4.75 v to ? 5.25 v v bat . . . . . . . . . . . . . . . . . . . . . . . . . . ? 40 v to ? 58 v agnd/dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v bgnd with respect to agnd/dgnd . . . . . . . . . . . . ? 100 mv to +100 mv load resistance on vtx to ground . . . . . . 10 k ? min operating ranges define those limits between which the functionality of the device is guaranteed. * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of production units.
6 am79578 data sheet electrical characteristics note: * performance grade description test conditions (see note 1) min typ max unit note analog (v tx ) output impedance 3 ? analog (v tx ) output offset 0 c to +70 c ? 40 c to +85 c ? 40 ? 50 +40 +50 mv ? 4 analog (rsn) input impedance 300 hz to 3.4 khz 1 20 ? 4 longitudinal impedance at a or b 0 hz to 100 hz 35 overload level, z 2win = 600 ? 4-wire 2-wire ? 3.1 +3.1 vpk 2 transmission performance 2-wire return loss (see test circuit d) 300 hz to 500 hz 500 hz to 2.5 khz 2500 hz to 3.4 khz 26 26 20 db 4, 10 longitudinal balance (2-wire and 4-wire, see test circuit c) longitudinal to metallic l-t, l-4 200 hz to 1 khz ? 1, ? 3* normal polarity 0 c to 70 c ? 2, ? 4 normal polarity ? 40 c to +85 c ? 2, ? 4 reverse polarity ? 2, ? 4 52 63 58 54 db ? ? 4 ? 1 khz to 3.4 khz ? 1, ? 3* normal polarity 0 c to 70 c ? 2, ? 4 normal polarity ? 40 c to +85 c ? 2, ? 4 reverse polarity ? 2, ? 4 52 58 54 54 ? ? 4 ? longitudinal signal generation 4-l 300 hz to 800 hz 42 longitudinal current capability per wire active state hoc state 25 18 marms 4 insertion loss and balance return signal (2- to 4-wire, 4- to 2-wire, and 4- to 4-wire, see test circuits a and b) gain accuracy over temperature 0 dbm, 1 khz 0 c to 70 c ? 40 c to +85 c ? 0.15 ? 0.20 0 0 +0.15 +0.20 db ? 4 gain accuracy over frequency 300 hz to 3.4 khz 0 c to 70 c relative to 1 khz ? 40 c to +85 c ? 0.10 ? 0.15 +0.10 +0.15 ? 4 gain tracking +3 dbm to ? 55 dbm 0 c to 70 c relative to 0 dbm ? 40 c to +85 c ? 0.10 ? 0.15 +0.10 +0.15 ? 4 gain accuracy, on hook ? 0.50 +0.50 4 group delay 0 dbm, 1 khz 5.3 s 4, 12 total harmonic distortion (2- to 4-wire or 4- to 2-wire, see test circuits a and b) total harmonic distortion 0 dbm, 300 hz to 3.4 khz +9 dbm, 300 hz to 3.4 khz ? 64 ? 55 ? 50 ? 40 db harmonic distortion, long loop v bat = ? 50 v, r l = 1900 ? , vpk = 2.5 v ? 40 harmonic distortion, on hook v bat = ? 50 v, vpk = 500 mv ? 36 idle channel noise psophometric weighted noise 2-wire 4-wire ? 83 ? 78 dbmp
slic products 7 electrical characteristics (continued) description test conditions (see note 1) min typ max unit note single frequency out-of-band noise (see test circuit e) metallic 4 khz to 9 khz 9 khz to 1 mhz 256 khz and harmonics ? 76 ? 76 ? 57 dbm 4, 5, 9 4, 5, 9 4, 5 longitudinal 1 khz to 15 khz above 15 khz 256 khz and harmonics ? 70 ? 85 ? 57 4, 5, 9 4, 5, 9 4, 5 line characteristics (see figure 1) r feed = 400 ? apparent battery voltage active 50 v i l , long loops, active state v bat = ? 50 v, r l = 1900 ? 19 ma i l , tip open state 1.0 i l , open circuit state r l = 0 ? 1.0 open circuit voltage, active state v bat = ? 50 v, t a = 25 c 41.5 43 v open circuit voltage, hoc state v bat = ? 50 v v bat ? 2 7 fault current limit, i l lim (i ax + i bx ) a and b shorted to gnd 130 ma active current limit r clp = open, r l = 210 ? r clp = short to v ee , r l = 210 ? r clp = 170 to v ee , r l = 210 ? 25 45 35 30 50 40 35 55 45 power dissipation, normal polarity on hook, open circuit state 35 80 mw on hook, hoc state 135 250 on hook, active state 200 300 off hook, hoc state 500 750 off hook, active state 650 1000 supply currents v cc on-hook supply current open circuit hoc active 3.0 6.0 8.0 4.5 10.0 13.0 ma v ee on-hook supply current open circuit hoc active 1.0 2.3 3.0 2.3 3.7 6.0 v bat on-hook supply current open circuit hoc active 0.4 3.2 4.5 1.0 5.5 7.0
8 am79578 data sheet electrical characteristics (continued) description test conditions (see note 1) min typ max unit note power supply rejection ratio (v ripple = 50 mvrms) v cc 50 hz to 3.4 khz 30 45 db 6 3.4 khz to 50 khz 25 40 v ee 50 hz to 3.4 khz 25 40 3.4 khz to 50 khz 10 25 v bat 50 hz to 3.4 khz 30 45 3.4 khz to 50 khz 25 40 off-hook detector current threshold accuracy i det = 365/r d nominal ? 20 +20 % current threshold, tip open state i det = 712/r d ? 20 +20 ground-key detector thresholds, active state, (see test circuit f) ground-key resistance threshold b(ring) to gnd 2.0 5.0 10.0 k ? ground-key current threshold b(ring) to gnd 9 ma 8 midpoint to gnd 9 ring-trip detector input bias current ? 5 ? 0.05 a offset voltage source resistance 0 ? to 2 m ? ? 50 0 +50 mv 11 logic inputs (c4 ? c1, e1, and chclk) input high voltage 2.0 v input low voltage 0.8 input high current, except e1 ? 75 40 a input high current, e1 ? 75 45 input low current ? 0.4 ma logic output (det ) output low voltage i out = 0.8 ma 0.4 v output high voltage i out = ? 0.1 ma 2.4 relay driver outputs (ringout, testout) on voltage 25 ma sink 1.0 1.5 v off leakage 0.5 100 a
slic products 9 relay driver schematics notes: 1. unless otherwise noted, test conditions are bat = ? 52 v, v cc = +5 v, v ee = ? 5 v, r l = 600 ? , c hp = 0.22 f, r dc1 = r dc2 = 9 k ? , c dc = 0.2 f, r d = 51.1 k ? , no fuse resistors, two-wire ac output impedance, programming impedance (z t ) = 600 k ? resistive, receive input summing impedance (z rx ) = 300 k ? resistive. (see table 2 for component formulas.) series battery resistor = 22 ? . 2. overload level is defined when thd = 1%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that the two-wire ac load impedance matches the impedance programmed by z t . 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. these tests are performed with a longitudinal impedance of 90 ? and metallic impedance of 300 ? for frequencies below 12 khz and 135 ? for frequencies greater than 12 khz. these tests are extremely sensitive to circuit board layout. 6. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 7. the open circuit voltage will limit to 50 v typical at high battery voltages (|v bat | > 52 v). 8. ? midpoint ? is defined as the connection point between two 300 ? series resistors connected between a(tip) and b(ring). 9. fundamental and harmonics from 256 khz switch-regulator chopper are not included. 10. assumes the following z t network: 11. tested with 0 ? source impedance. 2 m ? is specified for system design purposes only. 12. group delay can be considerably reduced by using a z t network such as that shown in note 10 above. the network reduces the group delay to less than 2 s. the effect of group delay on linecard performance may be compensated by using the qslac ? or dslac ? device. ringout testout 21777a-003 vtx rsn 300 k ? 300 k ? 30 pf r t2 r t1
10 am79578 data sheet note: the hoc state offers higher open circuit voltage than the active state by disabling the anti-saturation circuitry. idle power dissipation in the hoc state is less than that in the active state. on-hook transmission is not supported in the hoc state below a | v bat | of 56 v. table 1. slic decoding det output state c3 c2 c1 two-wire status e1 = 0 e1 = 1 0 0 0 0 open circuit ring trip ring trip 1 0 0 1 ringing ring trip ring trip 2 0 1 0 active loop detector ground key 3 0 1 1 high open circuit (hoc) loop detector ground key 4 1 0 0 tip open loop detector ? 5 1 0 1 reserved ? ? 6 1 1 0 active polarity reversal loop detector ground key 7 1 1 1 hoc polarity reversal loop detector ground key table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from v rx to the rsn pin, z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the rdc pin. r dc1 and r dc2 are approximately equal. r d and c d form the network connected from rd to ? 5 v and i t is the threshold current between on-hook and off-hook. c cas is the regulator filter capacitor and f c is the desired filter cut-off frequency. z t 1000 z 2win 2r f ? () = z rx z l g 42l ----------- - 1000 z t ? z t 1000 z l 2r f + () + ----------------------------------------------------- ? = r dc1 r dc2 50 r feed 2r f ? () = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ? --------------------------------- ? = r d 365 i t -------- - c d 0.5 ms r d ---------------- - = , = c cas 1 3.4 10 5 f c ? ------------------------------ - =
slic products 11 dc feed characteristics 46.79939 46.93133 47.06396 47.10524 47.15931 47.19432 47.21877 47.23688 47.26178 47.28974 47.30491 47.31443 47.32079 47.32535 47.3287 47.33275 47.3356 47.33778 0 10 20 30 40 50 60 0 1020304050 vab (volts) 12 3 4 6 5 notes: 1. v bat = ? 50 v 2. v bat = ? 52 v 3. v bat = ? 56 v figure 1. dc feed characteristics 4. r clp = open 5. r clp = 170 k ? 6. r clp = v ee 21777a-004
12 am79578 data sheet test circuits vtx rsn agnd r t r rx v l v ab v ab r l rsn agnd vtx v rx r rx i l2-4 = ? 20 log (v tx / v ab ) a. two- to four-wire insertion loss i l4-2 = ? 20 log (v ab / v rx ) b. four- to two-wire insertion loss and balance return signal vtx rsn agnd r t r rx v rx s2 open, s1 closed: l-t long. bal. = ? 20 log (v ab / v l ) l-4 long. bal. = ? 20 log (v tx / v l ) brs = 20 log (v tx / v rx ) slic slic slic slic r l 2 b(ring) a (tip) b (ring) a(tip) v l s1 b (ring) a (tip) s2 1/ c << r l c s2 closed, s1 open: 4-l long. sig. gen. = 20 log (v l / v rx ) c. longitudinal balance r r v m z in 900 ? v s r t r rx b (ring) a (tip) rsn agnd vtx d. two-wire return loss test circuit note: z d is the desired impedance (e.g., the characteristic impedance of the line). r l = ? 20 log (2 v m / v s ) r t idc r l 2 r l 2 v l r l 2
slic products 13 test circuits (continued) 1/ c << 90 ? e. single-frequency noise slic b(ring) a(tip) 68 68 56 c c idc s m r l r l r e s e a(tip) b(ring) current feed or ground key f. ground-key detection v cc 6.2 k ? 15 pf a(tip) b(ring) g. loop-detector switching r l = 600 ? e1 h. ground-key switching r g = 2 k ? det ? ? ? a(tip) b(ring)
14 am79578 data sheet test circuits (continued) vcc vee +5 v ? 5 v r d rd agnd/ dgnd c1 c2 c3 c4 e1 det hpa hpb a(tip) b(ring) a(tip) b(ring) 2.2 nf 2.2 nf c hp bgnd testout ringout v tx vtx rsn v rx r rx r t cas c cas c dc r dc1 r dc2 rdc da db vbat bat r bat c bat clp clp r clp d 1 l l vreg r ch c ch1 c ch2 chs qbat 21777a-005 i. am79578 test circuit
slic products 15 physical dimensions pl032 revision summary revision a to revision b ? minor changes to the data sheet style and format were made to conform to legerity standards. in the pin description table, inserted/changed tp pin description to: ? thermal pin. connection for heat dissipation. internally connected to substrate (qbat). leave as open circuit or connected to qbat. in both cases, the tp pins can connect to an area of copper on the board to enhance heat dissipation. ? revision b to revision c ? the physical dimensions (pl032) were added to the physical dimensions section. ? deleted the ceramic dip and plastic dip packages and references to them. ? updated the pin description table to correct inconsistencies. .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
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notes: www.legerity.com
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the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with re- spect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specificati ons and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intelle ctual property rights is granted by this publication. except as set forth in legerity's standard terms and conditions of sale, legerity assumes no li ability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerit y's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 1999 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, dslac and qslac are trademarks of legerity, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies.
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