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le57d11 data sheet publication# 080676 rev: a version: 1.0 date: nov 16, 2001 preliminary dual slic dual subscriber line interface circuit le57d11 device applications ideal for low cost, high performance line card applications (co, dlc) meets requirements for countries such as: china, korea, japan, taiwan, and australia fulfills the following china specifications: gf002- 9002.1 features dual channel slic device with small footprint on-chip thermal management (tmg) feature in normal and reverse polarity control states: active (normal and reversal polarity), standby, and disconnect on-hook transmission low standby power ?39 v to ?58 v battery operation two-wire impedance set by single external impedance per channel fault detection device level thermal shutdown programmable constant-current feed (range tbd) programmable loop-detect threshold programmable ring-trip detect threshold only +5 v and battery supply required current gain = 500 ordering information 32-pin plcc 44-pin etqfp device performance grade LE57D111JC 32-pin plcc, 48 db polarity reversal le57d113jc 32-pin plcc, 48 db no polarity reversal le57d111tc 44-pin etqfp, 48 db polarity reversal le57d113tc 44-pin etqfp, 48 db no polarity reversal description the innovative le57d11 dual channel slic device was designed for high-density pots applications requiring a small footprint slic device with significant power savings. by combining the line interface of two channels into one slic device, the le57d11 device enables the design of a low cost, high performance, and fully programmable line interface for multiple country applications worldwide. the on-chip thermal management (tmg) feature allows for significantly reduced power dissipation on the device. another benefit is that it is offered in space-saving package types 44-pin etqfp and 32- pin plcc. the small footprint of the slic device allows designers to save board space, increasing the density of lines on the board. the le57d11 device is also designed to significantly reduce the number of external components required for line card design. legerity offers a range of compatible slac devices that perform the codec function in a line card. in particular, the legerity quad slac device combined with the le57d11 device provides a programmable line circuit that can be configured for varying requirements. related literature 080147 am79q02/021/031 quad slac data sheet 080753 le58ql02/021/031 qlslac ? data sheet 080748 le57d11 evaluation board user?s guide block diagram bgnd 1 a 2 (tip) hp 2 b 2 (ring) vtx 2 rsn 2 ch2 2-w interface ch1 2-w interface ch2 input decoder and control common bias off-hook detector ch2 power feed controller ch2 ring trip detector ch2 ring trip detector ch1 power feed controller ch1 off-hook detector ch1 ch2 fault detector ch1 fault detector signal transmission ch2 signal transmission ch1 ch1 input decoder and control tmg 2 cflt 2 c2 2 c1 2 det 2 cas iref det 1 c2 1 c1 1 cflt 1 tmg 1 a 1 (tip) hp 1 b 1 (ring) vtx 1 rsn 1 bgnd 2 vbat cdc 2 db 2 dac db 1 cdc 1 vcc agnd
preliminary 2 le57d11 data sheet table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 fault detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 two-wire interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 signal transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 power feed controller and common bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 input decoder and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 off-hook detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 ring-trip detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 environmental ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 electrical ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 transmission performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 crosstalk between channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 longitudinal capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 insertion loss and balance return signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 line characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 power supply rejection ratio, active normal state. . . . . . . . . . . . . . . . . . . . . . . .9 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 rfi rejection (see figure 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 logic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 ring-trip detector input (da, db). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 cflt1, cflt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 cflt toggle range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 loop detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 slic decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 user-programmable components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 dc feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 line card parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 pl032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 e tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
preliminary le57d11 data sheet 3 product description the le57d11 device is designed for long loop high-density pots applications requiring a power saving, small footprint slic. the le57d11 device increases line card density by integrating two slic devices into a single 32 pin package. this reduction in board space allows for higher density linecard, which allows for amortizing common hardware across more channels. the le57d11 device gives line card designers a simple control interface that supports four states: active, polarity reversal, stand by, and disconnect (ringing). the le57d11 device is low cost and high performance, providing key features required for pots markets requiring only loop start. the device includes a thermal management resistor option. block descriptions fault detector these blocks provide fault detection on a per channel basis for short to ground, short to battery, or certain ac faults. the le 57d11 device provides fault detection by having one fault detector in each channel. under fault conditions ? either a short to ground , a short to battery, or specified ac power cross faults ? the le57d11 device detects the longitudinal unbalance and trips the detector. once the detector is tripped, the cflt pin is pulled low and keeps toggling between vth1 and vth2 (refer figure 2) un til the fault is removed. an external 0.1f capacitor is connected between the cflt pin and agnd, which provides a fault trigger delay of about 4 ms (t1) and release delay of 24 ms (t2). during release delay, the affected channel is shutdown which sets tip and ring to a disconnect state. the trigger delay prevents short transients on tip and ring from triggering the channel shutdow n when a fault is not present. figure 1. fault detector figure 2. fault detection waveform bias shutdown control bias block fault release cflt tip v long ring v lb fault detector c flt release t 2 t 1 t 2 t 1 release v cflt time fault trigger fault trigger 5v v th1 v th2 t1 cflt v th1 v th2 ? () i trigger ----------------------------------------------------- =t2 cflt v th1 v th2 ? () i release ----------------------------------------------------- =
preliminary 4 le57d11 data sheet two-wire interface the two-wire interfaces provide dc current and send voice signals to a telephone apparatus connected to the line card with a two-wire line. the two-wire interface also receives the returning voice signals from the telephone transmitter. signal transmission the ac line voltage is sensed by a differential amplifier between the a i (tip) and hp i leads. the output of this amplifier is equal to the ac metallic components of the line voltages and is output at vtx i . the transmission circuit also contains a longitudinal feedback circuit to shunt longitudinal signals to a dc bias voltage. the longitudinal feedback does not affect metallic signals . power feed controller and common bias the power feed controllers have three sections: (1) the battery feed circuit, (2) the polarity reversal circuit, and (3) the co mmon bias circuit. the battery feed circuit regulates the amount of dc current and voltage supplied to the telephone over a wide ran ge of loop resistance. the polarity reversal circuit provides the capability to reverse the loop current for pay telephone key pad disable and other applications. the bias circuit provides a filtered reference voltage, which is offset from the subscriber lin e voltage, and a signal which sets the current limit. input decoder and control the input decoder and control block provides a means for a microprocessor or slac ic to control such system states as active, standby, disconnect (ringing), and polarity reversal. the input decoder and control block has ttl-compatible inputs, which set the operating states of the slic device. off-hook detector the most important loop monitoring function is off-hook detection. loop current is programmed for both channels by a single resistor. loop detect threshold is typically 1/3 of the programmed loop current in the active and reverse polarity states. ring-trip detector in the disconnect state, the ring-trip detector is active. while the db i pin is more negative than the dac pin, the det pin will be high to indicate on hook. when an off hook condition occurs, the db i pin becomes more positive than the dac pin, and the det pin will go low to indicate off hook during ringing (ring-trip) has been detected. the system implements the ringing state usin g external control of a ring relay in combination with the disconnect slic state, which enables the ring-trip detector.
preliminary le57d11 data sheet 5 connection diagrams note: 1. pin 1 is marked for orientation. 2. nc = no connect 3. e = exposed pad bgnd 1 b 1 (ring) a 1 (tip) db 1 dac vbat db 2 a 2 (tip) b 2 (ring) rsn 2 vtx 2 cflt 2 hp 2 tmg 2 bgnd 2 cdc 2 4 3 2 1 32 31 30 14 15 16 17 18 19 20 7 9 8 11 10 12 13 6 5 27 25 26 23 24 22 21 28 29 le57d11jc 32-pin plcc cdc 1 rsn 1 vtx 1 cflt 1 hp 1 tmg 1 det 1 c2 1 c1 1 agnd/ dgnd vcc cas iref c1 2 c2 2 det 2 le57d11tc 44-pin etqfp 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 44 43 42 41 40 39 38 37 36 35 34 5 6 7 8 9 10 11 4 3 2 1 a 1 (tip) b 1 (ring) bgnd 1 db 1 dac nc vbat db 2 a 2 (tip) b 2 (ring) bgnd 2 nc c1 1 c2 1 agnd vcc nc cas iref c1 2 c2 2 rsn 2 nc cdc 2 nc vtx 2 nc nc cflt 2 nc hp 2 tmg 2 rsn 1 cdc 1 nc vtx 1 nc nc cflt 1 nc hp 1 tmg 1 det 1 det 2
preliminary 6 le57d11 data sheet pin descriptions pin name type description a 1 (tip) input/output output of a (tip) power amplifier of channel 1. a 2 (tip) input/output output of a (tip) power amplifier of channel 2. agnd ground analog and digital ground. b 1 (ring) input/output output of b (ring) power amplifier of channel 1. b 2 (ring) input/output output of b (ring) power amplifier of channel 2. bgnd 1 ground battery (power) ground of channel 1 bgnd 2 ground battery (power) ground of channel 2. c1 1 input state decoder inputs of channel 1. c2 1 input c1 2 input state decoder inputs of channel 2. c2 2 input cas capacitor pin for capacitor to filter reference voltage when operating in anti-saturation region. cdc 1 capacitor dc feed filter capacitor and dc feed programming pin of channel 1. cdc 2 capacitor dc feed filter capacitor and dc feed programming pin of channel 2. cflt 1 input/output fault detector output of channel 1. connect a capacitor from cflt 1 to agnd to set fault detector timing. cflt 2 input/output fault detector output of channel 2. connect a capacitor from cflt 2 to agnd to set fault detector timing. dac input ring-trip negative of both channels. negative input to ring-trip comparator. db 1 input ring-trip positive of channel 1. positive input to ring-trip comparator. db 2 input ring-trip positive of channel 2. positive input to ring-trip comparator. det 1 output switch-hook/ring-trip detector output of channel1. logic low indicates that a detector is tripped. det 2 output switch-hook/ring-trip detector output of channel 2. logic low indicates that a detector is tripped. hp 1 capacitor connect high-pass filter capacitor from hp 1 to b 1 (ring). hp 2 capacitor connect high-pass filter capacitor from hp 2 to b 2 (ring). iref resistor connection for reference resistor that programs loop detector threshold and dc feed current of both channels. rsn 1 input receive summing node of channel 1. the metallic current (both ac and dc) between a 1 (tip) and b 1 (ring) is equal to 500 times the current into this pin. the networks that program receive gain and two-wire impedance of channel 1 connect to this node. rsn 2 input receive summing node of channel 2. the metallic current (both ac and dc) between a 2 (tip) and b 2 (ring) is equal to 500 times the current into this pin. the networks that program receive gain and two-wire impedance of channel 2 connect to this node. tmg 1 output thermal management of channel 1. external resistor connects from tmg 1 to vbat to offload power from the slic device. tmg 2 output thermal management of channel 2. external resistor connects from tmg2 to vbat to offload power from the slic device. vbat battery battery supply and connection to substrate. vcc power +5 v power supply. vtx 1 output transmit audio signal of channel 1. this output is a scaled version of the a and b metallic voltage. vtx also sources the two-wire input impedance programming network. vtx 2 output transmit audio signal of channel 2. this output is a scaled version of the a and b metallic voltage. vtx 2 also sources the two-wire input impedance programming network.
preliminary le57d11 data sheet 7 electrical characteristics absolute maximum ratings stresses greater than those listed under absolute maximum ratings can cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods can affect device reliability note: 1. thermal limiting circuitry on-chip will shut down the circuit at a junction temperature of about 165 o c. the device should never see this temperature, and operation above 145 o c junction temperature may degrade device reliability. see the slic packaging considerations for more information. 2. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above thes e limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges legerity guarantees the performance of this device over commercial (0 to 70 c) and industrial ( ? 40 to 85 c) temperature ranges by conducting electrical characterization over each range, and by conducting a production test with single insertion coupled to periodic sampling. these characterization and test procedures comply with section 4.6.2 of bellcore tr-tsy-000357 component reliability assurance requirements for telecommunications equipment. storage temperature ?55 to +150o c v cc with respect to agnd ?0.4 to +7.0 v v bat with respect to agnd: continuous 10 ms +0.4 to ?70 v +0.4 to ?75 v bgnd 1 , bgnd 2 with respect to agnd +3 to ?3 v a 1 (tip), a 2 (tip), b 1 (ring), b 2 (ring) to bgnd: continuous v bat to + 1 v 10 ms (f = 0.1 hz) ?70 to +5 v 1 s (f = 0.1 hz) ?80 to +8 v 250 ns (f = 0.1 hz) ?90 to +12 v current from a 1 (tip), a 2 (tip), b 1 (ring), b 2 (ring) 150 ma db 1 , db 2 , and dac inputs: voltage on ring-trip inputs v bat to 0 v current into ring-trip inputs 10 ma c1 1 , c2 1 , c1 2 , c2 2 , cflt 1 , cflt 2 input voltage ?0.4 to v cc + 0.4 v maximum power dissipation, continuous: t a = 70o c, no heat sink (see note) in 32-pin plcc package 1.7 w in 44-pin etqfp 3.3 w thermal data (junction to ambient): ja in 32-pin plcc package 43o c/w typ in 44-pin etqfp 22.7o c/w typ thermal data (junction to case): jc in 32-pin plcc package 16o c/w typ in 44-pin etqfp 9.2o c/w typ esd immunity/pin (human body model) 1.5 kv esd immunity/pin (charge device model) 1 kv
preliminary 8 le57d11 data sheet environmental ranges electrical ranges note: the operating ranges define those limits between which the functionality of the device is guaranteed. specifications transmission performance crosstalk between channels longitudinal capability (see figure 7.) ambient temperature ? 40 to 85 c v cc 4.75 to 5.25 v v bat ?39 to ?58 v db1, db2, and dac v bat to ?2 v agnd 0 v bgnd1, bgnd2 with respect to agnd ?100 to + 100 mv load resistance on vtx to ground 20 k ? minimum description test conditions (see note 1) min typ max unit note 2-wire return loss 200 hz to 3.4 khz (see figure 8) 26 db 1, 4 analog output (vtx) impedance 3 20 ? 4 analog (vtx) output offset voltage ?50 +50 mv overload level, 2-wire active state 2.5 vpk 2a overload level on hook, r lac = 600 ? 0.77 vrms 2b thd (total harmonic distortion) 0 dbm ?64 ?50 db 5 +7 dbm ?55 ?40 thd, on hook 0dbm, r lac = 600 ? ?36 db 5 description test conditions (see note 1) min typ max unit note crosstalk coupling loss f = 200 hz to 3.4 khz 80 db 4 description test conditions (see note 1) min typ max unit note longitudinal to metallic l-t, l-4 balance 200 hz to 3.4 khz, 0o c to +70o c 48 db 4 longitudinal signal generation 4-l 200 hz to 3.4 khz 40 longitudinal current per pin (a or b) active state (off hook) 8.5 20 marms 8 longitudinal impedance at a or b 0 to 100 hz 25 ?/ pin idle channel noise c-message, r l = 600 ? 712dbrnc4 psophometric, 600 ? ?83 ?78 dbmp
preliminary le57d11 data sheet 9 insertion loss and balance return signal (see figure 5 and figure 6.) line characteristics power supply rejection ratio, active normal state power dissipation supply currents battery = ? 48 v description test conditions (see note 1) min typ max unit note gain accuracy, 4- to 2-wire 0 dbm, 1 khz ?0.20 0 +0.20 db gain accuracy, 2- to 4-wire 0 dbm, 1 khz ?9.64 ?9.54 ?9.44 gain accuracy, 4- to 2-wire on hook ?0.35 +0.35 4 gain accuracy over frequency 300 to 3.4 khz relative to 1 khz ?0.15 +0.15 gain tracking +3 dbm to ?55 dbm relative to 0 dbm ?0.15 +0.15 gain tracking on hook 0 dbm to ?37 dbm +3 dbm to 0 dbm ?0.15 ?0.35 +0.15 +0.35 group delay 0 dbm, 1 khz 4 s 4, 7 description test conditions (see note 1) min typ max unit note i l , short loops, active state r ldc = 600 ? 26.4 30 33.6 ma i l , long loops, active state r ldc = 1930 ? , bat = ?42.75 v, t a = 25c 18 19 i l , accuracy, standby state 0.7i l i l 1.3i l i l , loop current, disconnect state r l = 0 100 a vab, open circuit voltage v bat = ?48 v +38.3 +40.3 v description test conditions (see note 1) min typ max unit note v cc 50 hz to 3.4 khzv ripple = 100 mv rms 30 40 db 5 v bat 50 hz to 3.4 khzv ripple = 500 mv pp 28 50 effective internal resistance cas pin to v bat 85 170 255 k ? 4 description test conditions (see note 1) min typ max unit note on hook, standby state (both stdby) 40 100 mw on hook, active state (active) 200 400 off hook, active state (active) r l = 300 ? , r tmg = 1600 ? 1400 2000 one channel, active/ one channel, stdby r l = 300 ? , r tmg = 1600 ? 720 1050 description test conditions (see note 1) min typ max unit note i cc , on-hook v cc supply current standby state (both stdby) 4.4 ma active state, bat = ?48 v (both active) 12.6 i bat , on-hook v bat supply current standby state (both stdby) 0.4 active state, bat = ?48 v (both active) 5.6 i l vbat 3v ? r l 5k + () ------------------------------ t a 25 c = , =
preliminary 10 le57d11 data sheet rfi rejection (see figure 9.) logic inputs (applies to c11, c12, c21, and c22.) logic output (applies to det1 , det2 , cflt1, and cflt2.) ring-trip detector input (applies to dac, db1, and db2.) cflt1, cflt2 cflt toggle range loop detector description test conditions min typ max unit note vtx1 or vtx2 f = .01 mhz to 100 mhz hf gen output = 1.5 vrms cax = cbx = 33 nf 1 mvrms 4 cax = cbx = 2.2 nf 3 description test conditions min typ max unit note v ih , input high voltage 2.0 v v il , input low voltage 0.8 i ih , input high current ?75 40 a i il , input low current ?400 description test conditions (see note 1) min typ max unit note v ol , output low voltage i out = 0.3 ma, 15 k ? to v cc 0.40 v v oh , output high voltage i out = ?0.1 ma, 15 k ? to v cc 2.4 description test conditions (see note 1) min typ max unit note bias current ?500 ?50 na offset voltage source resistance = 2 m ? ?50 0 +50 mv 6 description test conditions (see note 1) min typ max unit note sinking current (itrigger) 60 a sourcing current (irelease) 10 description test conditions (see note 1) min typ max unit note vth1 3.0 3.3 v vth2 0.8 1.1 description test conditions (see note 1) min typ max unit note off-hook threshold active 9 11 ma on-hook threshold active 8.5 10.5 off-hook threshold standby 4 6 on-hook threshold standby 3.8 5.8 hysteresis 0 2
preliminary le57d11 data sheet 11 note: 1. unless otherwise noted, test conditions are bat = ?52 v; v cc = +5 v; r l1 , r l2 = 600 ? ; r tmg1 , r tmg2 = 1600 ? ; no fuse resistors; c hp1 , c hp2 = 100 nf; c dc1 ,c dc2 = 1.5 f; c cas = 0.33 f; r ref =15 k; two-wire ac input impedance is a 600 ? resistance synthesized by the programming network shown below. figure 3. ac input impedance programming network 2. a. z when thd = 1%. b. overload level is defined when thd = 1.5%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that the two-wire, ac-load impedance matches the programmed impedance. 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 6. tested with 0 ? source impedance. 2 m ? is specified for system design only. 7. group delay can be greatly reduced by using a z t network such as that shown in note 1. the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on linecard performance also may be compensated for by synthesizing complex impedance with the qslac? or dslac? device. 8. minimum current level guaranteed not to cause a false loop detect. slic decoding (for x, channel = 1 or 2) state c2x c1x two-wire status detx output 0 0 0 disconnect ring-trip detector 1 0 1 active loop detector 2 1 1 polarity reversed loop detector 3 1 0 standby loop detector vtx r t1 = 41.7 k r t2 = 41.7 k c t1 = 120 pf r rx = 124 k v rx rsn
preliminary 12 le57d11 data sheet user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from vrx to rsn. z t is defined above, and g 42l is the desired receive gain. i loop is the desired loop current in the constant-current region. loop detect threshold is typically 1/3 of programmed loop current. c cas is the regulator filter capacitor and f c is the desired filter cut-off frequency. standby loop current (resistive region). thermal management equations (normal, active, and polarity reverse states) r tmg is connected from tmg to vbat and limits power within the slic in active and off-hook states. power dissipated in the tmg resistor, r tmg during active and off- hook states. power dissipated in the slic while in active state. z t 166.7 z 2win 2r f ? () = z rx z l g 42l ------------ - ? 500z t z t 166.7 z l 2r f + () + --------------------------------------------------------- = r ref 450 i loop --------------- = c dc 1.5 f = c cas 1 3.4 10 5 f c ? -------------------------------- = i standby v bat 3v ? 5000 ? r l + -------------------------------- = r tmg v bat 6v ? i loop -------------------------------- 70 ? ? p rtmg v bat 6v ? i l ? r l () ? () 2 r tmg 70 ? + () 2 --------------------------------------------------------------------- - r tmg ? = p slic v bat i l p rtmg ? r l i l () 2 0.12 w + ? ? =
preliminary le57d11 data sheet 13 dc feed characteristics load line (typical) vbat = -48v vbat = -38v vbat = -42v 1 2b 3a 3b on-hook off-hook 2a note: 1. constant current region: 2a. battery-independent anti-sat (off-hook): 2b. battery tracking anti-sat (on-hook): 3a. battery tracking anti-sat (off-hook): 3b. battery tracking anti-sat (on-hook): v ab1 i l r l ' 450 () r ref -------------- r l ' where r l ' r l 2r f + = , = = v ab2a 43.6 vi l r feed 88 ----------------- - ? = v ab2b v ab2a 3.5 ? = v ab3a v bat 1.8 i l r feed 240 ----------------- - ? ? = v ab3b v ab3a 0.33 v bat 10.8 + ? ? = r feed 26.7k internal = i swth 150 r ref -------------- = r ref 15 k =
preliminary 14 le57d11 data sheet figure 4. feed programming note: to choose the correct value for r dc , please contact the manufacturer. test circuits figure 5. two-to-four wire insertion loss figure 6. four-to-two wire insertion loss and balance return signals r l a (tip) b (ring) iref cdc slic a b i l rsn r dc c dc r ref slic vtx 1 agnd rsn 1 v ab r t r rx i l2-4 = 20 log(v tx / v ab ) r l 2 r l 2 v l vtx 2 rsn 2 a 1 , a 2 (tip) b 1 , b 2 (ring) slic agnd v ab r t r rx i l4-2 = 20 log(v ab / v rx ) brs = 20 log(v tx / v rx ) v rx r l a 1 , a 2 (tip) b 1 , b 2 (ring) vtx 1 vtx 2 rsn 1 rsn 2
preliminary le57d11 data sheet 15 figure 7. longitudinal balance figure 8. two-wire return loss test circuit figure 9. rfi test circuit slic agnd v ab r t r rx l-t long. bal. = 20 log(v ab / v l ) v rx r l 2 r l 2 v l v l s1 1 c r l << s2 l-4 long. bal. = 20 log(v tx / v l ) s2 open, s1 closed s2 closed, s1open 4-l long. sig. gen. = 20 log(v l / v rx ) c a 1 , a 2 (tip) b 1 , b 2 (ring) vtx 1 vtx 2 rsn 1 rsn 2 return loss = ?20 log (2v m / v s ) z d : the desired impedance; eg., the characteristic impedance of the line slic agnd r rx = 124 k c t = 120 pf r ta r tb v m v s r r 41.7 k 41.7 k z d = 600 300 300 z in = 600 a 1 , a 2 (tip) b 1 , b 2 (ring) vtx 1 vtx 2 rsn 1 rsn 2 hf gen l 1 l 2 200 ? 200 ? c 1 c 2 50 ? 50 ? rf 1 rf 2 c ax c bx slic under test 80% amplitude modulated modulation frequency = 1 khz 50 ? vtx 1 vtx 2 a 1 , a 2 (tip) b 1 , b 2 (ring)
preliminary 16 le57d11 data sheet figure 10. le57d11 test circuit db 1 hp 1 b 1 (ring) tmg 1 vbat tmg 2 db 2 dac a 2 (tip) hp 2 b 2 (ring) a 1 (tip) bgnd vcc agnd vtx 1 rsn 1 cflt 1 cdc 1 det 1 c1 1 c2 1 iref cas vtx 2 rsn 2 cflt 2 cdc 2 det 2 c1 2 c2 2 + 5 v db 1 c a1 tip 1 ring 1 c hp1 c b1 r tmg1 r tmg2 bat dvbh db 2 dac c a2 tip 2 c hp2 ring 2 c b2 vtx 1 vrx 1 c flt1 c dc1 r ref c cas vtx 2 vrx 2 r rx2 r t2 c flt2 c dc2 ch1 ch2 r t1 r rx1 le57d11 det 2 c1 2 c2 2 det 1 c1 1 c2 1
preliminary le57d11 data sheet 17 application circuit ring_source r r2 400 r r1 400 r sr3 909 k r sr4 1m c rt2 100 nf r sr1 909 k r sr2 1 m c rt1 100 nf r rth1 1 m dac c th 100 nf r rth2 909 k rs 1 db 1 db 2 rs 2 db 1 hp 1 b 1 (ring) tmg 1 vbat tmg 2 db 2 dac b 2 (ring) a 1 (tip) bgnd vcc agnd vtx 1 rsn 1 cflt 1 cdc 1 det 1 c1 1 c2 1 iref cas vtx 2 rsn 2 cflt 2 cdc 2 det 2 c1 2 c2 2 db 1 c a1 c hp1 r tmg1 r tmg2 bat dvbh db 2 vtx 1 vrx 1 c flt1 c dc1 r ref c cas vtx 2 vrx 2 r rx2 r t2 c flt2 c dc2 ch1 ch2 r t1 r rx1 + 5 v 2.2nf ring 1 2.2nf c b1 bat 2.2nf tip 2 ring 2 2.2nf c b2 bat dac r f1a 50 rr1 u2 c p1 100 nf rr1 r f1b 50 rs 1 100 nf 1.6 k 1.6 k c a2 r f2a 50 rr2 r f2b 50 rs 2 c hp2 100 nf c p2 100 nf hp 2 a 2 (tip) 83.3 k 124 k 100 nf 1.5 f 15 k 330 nf 83.3 k 124 k 100 nf 1.5 f u1 le57d11 rr1 u3 tip 1 r r2 det 1 c1 1 c2 1 det 2 c1 2 c2 2 battery ground analog ground digital ground
preliminary 18 le57d11 data sheet line card parts list the following list defines the parts and part values required to meet target specification limits for channel i of the line car d (i = 1,2). item quantity type value tol. rating comments note c a1 , c b1 , c a2 , c b2 4 capacitor (x7r) 2200 pf 20% 100 v c hp1 , c hp2 , c p1 , c p2 , c rt1 , c rt2 , c th 7 capacitor (x7r) 100 nf 20% 100 v c flt1 , c flt2 2 capacitor (x7r) 100 nf 20% 16 v c dc1 , c dc2 2 capacitor (x7r) 1.5 f 10% 16 v r f1a , r f1b, r f2a , r f2b 2 resistor hybrid 50 1% r ref 1 smt 15 k 1% 1/10 w r t1 , r t2 2 smt 83.3 k 1% 1/10 w r rx1 , r rx2 2 smt 124 k 1% 1/10 w dvbh 1 murs 120 (d0-41) diode r r1 , r r2 2 resistor hybrid 400 1% u2, u3 2 tisp61089 r rth1 , r sr2 , r sr4 3smt 1 m 1% 1/4 w r sr1 , r sr3 , r rth2 3 smt 909 k 1% 1/4 w u1 1 le57d11 r tmg1 r tmg2 2smt 1.6 k 1% 2 w c cas 1 capacitor (x7r) 330 nf 20% 50 v
preliminary le57d11 data sheet 19 physical dimensions pl032 dwg rev ah; 08/00
preliminary 20 le57d11 data sheet etqfp
preliminary le57d11 data sheet 21 the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descri ptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this pub lication. except as set forth in legerity's standard terms and conditions of sale, legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellect ual property right. legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 2001 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, are trademarks of legerity, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies.
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