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? semiconductor components industries, llc, 2001 february, 2001 rev. 2 1 publication order number: tl594/d tl594 precision switchmode pulse width modulation control circuit the tl594 is a fixed frequency, pulse width modulation control circuit designed primarily for switchmode power supply control. ? complete pulse width modulation control circuitry ? onchip oscillator with master or slave operation ? onchip error amplifiers ? onchip 5.0 v reference, 1.5% accuracy ? adjustable deadtime control ? uncommitted output transistors rated to 500 ma source or sink ? output control for pushpull or singleended operation ? undervoltage lockout maximum ratings (full operating ambient temperature range applies, unless otherwise noted.) rating symbol value unit power supply voltage v cc 42 v collector output voltage v c1 , v c2 42 v collector output current (each transistor) (note 1.) i c1 , i c2 500 ma amplifier input voltage range v ir 0.3 to +42 v power dissipation @ t a 45 c p d 1000 mw thermal resistance junctiontoambient (pdip) junctiontoair (tssop) junctiontoambient (soic) r q ja 80 140 135 c/w operating junction temperature t j 125 c storage temperature range t stg 55 to +125 c operating ambient temperature range tl594cd, cn, cdtb t a 25 to 85 c derating ambient temperature t a 45 c 1. maximum thermal limits must be observed. so16 d suffix case 751b http://onsemi.com tssop16 dtb suffix case 948f 1 16 pdip16 n suffix case 648 1 16 1 16 marking diagrams 1 16 tl594cn awlyww 1 16 tl594cd awlyww a = assembly location wl, l = wafer lot y = year ww, w = work week tl59 4dtb alyw 1 16 see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information http://onsemi.com pin connections c t r t ground c1 1 inv input c2 q2 e2 e1 1 0.1 v oscillator v cc 5.0 v ref (top view) noninv input inv input v ref output control v cc noninv input compen/pwn comp input deadtime control error amp + - 2 3 4 5 6 7 89 10 11 12 13 14 15 16 2 error amp + - q1
tl594 http://onsemi.com 2 recommended operating conditions characteristics symbol min typ max unit power supply voltage v cc 7.0 15 40 v collector output voltage v c1 , v c2 30 40 v collector output current (each transistor) i c1 , i c2 200 ma amplified input voltage v in 0.3 v cc 2.0 v current into feedback terminal l fb 0.3 ma reference output current l ref 10 ma timing resistor r t 1.8 30 500 k w timing capacitor c t 0.0047 0.001 10 m f oscillator frequency f osc 1.0 40 200 khz pwm input voltage (pins 3, 4, 13) 0.3 5.3 v electrical characteristics (v cc = 15 v, c t = 0.01 m f, r t = 12 k w , unless otherwise noted.) for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies, unless otherwise noted. characteristics symbol min typ max unit reference section reference voltage (i o = 1.0 ma, t a = 25 c) (i o = 1.0 ma) v ref 4.925 4.9 5.0 5.075 5.1 v line regulation (v cc = 7.0 v to 40 v) reg line 2.0 25 mv load regulation (i o = 1.0 ma to 10 ma) reg load 2.0 15 mv short circuit output current (v ref = 0 v) i sc 15 40 75 ma output section collector offstate current (v cc = 40 v, v ce = 40 v) i c(off) 2.0 100 m a emitter offstate current (v cc = 40 v, v c = 40 v, v e = 0 v) i e(off) 100 m a collectoremitter saturation voltage (note 2.) commonemitter (v e = 0 v, i c = 200 ma) emitterfollower (v c = 15 v, i e = 200 ma) v sat(c) v sat(e) 1.1 1.5 1.3 2.5 v output control pin current low state (v oc 0.4 v) high state (v oc = v ref ) i ocl i och 0.1 2.0 20 m a output voltage rise time commonemitter (see figure 13) emitterfollower (see figure 14) t r 100 100 200 200 ns output voltage fall time commonemitter (see figure 13) emitterfollower (see figure 14) t f 40 40 100 100 ns error amplifier section input offset voltage (v o (pin 3) = 2.5 v) v io 2.0 10 mv input offset current (v o (pin 3) = 2.5 v) i io 5.0 250 na input bias current (v o (pin 3) = 2.5 v) i ib 0.1 1.0 m a input common mode voltage range (v cc = 40 v, t a = 25 c) v icr 0 to v cc 2.0 v inverting input voltage range v ir(inv) 0.3 to v cc 2.0 v open loop voltage gain ( d v o = 3.0 v, v o = 0.5 v to 3.5 v, r l = 2.0 k w) a vol 70 95 db unitygain crossover frequency (v o = 0.5 v to 3.5 v, r l = 2.0 k w ) f c 700 khz phase margin at unitygain (v o = 0.5 v to 3.5 v, r l = 2.0 k w ) f m 65 deg. common mode rejection ratio (v cc = 40 v) cmrr 65 90 db power supply rejection ratio ( d v cc = 33 v, v o = 2.5 v, r l = 2.0 k w ) psrr 100 db output sink current (v o (pin 3) = 0.7 v) i o 0.3 0.7 ma output source current (v o (pin 3) = 3.5 v) i o + 2.0 4.0 ma 2. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as poss ible.
tl594 http://onsemi.com 3 electrical characteristics (v cc = 15 v, c t = 0.01 m f, r t = 12 k w , unless otherwise noted.) for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies, unless otherwise noted. characteristics symbol min typ max unit pwm comparator section (test circuit figure 11) input threshold voltage (zero duty cycle) v th 3.6 4.5 v input sink current (v pin 3 = 0.7 v) i i 0.3 0.7 ma deadtime control section (test circuit figure 11) input bias current (pin 4) (v pin 4 = 0 v to 5.25 v) i ib (dt) 2.0 10 m a maximum duty cycle, each output, pushpull mode (v pin 4 = 0 v, c t = 0.01 m f, r t = 12 k w ) (v pin 4 = 0 v, c t = 0.001 m f, r t = 30 k w ) dc max 45 48 45 50 % input threshold voltage (pin 4) (zero duty cycle) (maximum duty cycle) v th 0 2.8 3.3 v oscillator section frequency (c t = 0.001 m f, r t = 30 k w ) (c t = 0.01 m f, r t = 12 k w , t a = 25 c) (c t = 0.01 m f, r t = 12 k w , t a = t low to t high ) f osc 9.2 9.0 40 10 10.8 12 khz standard deviation of frequency* (c t = 0.001 m f, r t = 30 k w ) s f osc 1.5 % frequency change with voltage (v cc = 7.0 v to 40 v, t a = 25 c) d f osc ( d v) 0.2 1.0 % frequency change with temperature ( d t a = t low to t high , c t = 0.01 m f, r t = 12 k w ) d f osc ( d t) 4.0 % undervoltage lockout section turnon threshold (v cc increasing, i ref = 1.0 ma) t a = 25 c t a = t low to t high v th 4.0 3.5 5.2 6.0 6.5 v hysteresis tl594c,i tl594m v h 100 50 150 150 300 300 mv total device standby supply current (pin 6 at v ref , all other inputs and outputs open) (v cc = 15 v) (v cc = 40 v) i cc 8.0 8.0 15 18 ma average supply current (v pin 4 = 2.0 v, c t = 0.01 m f, r t = 12 k w , v cc = 15 v, see figure 11) 11 ma *standard deviation is a measure of the statistical distribution about the mean as derived from the formula, s n n = 1 s (x n x ) 2 n 1
tl594 http://onsemi.com 4 figure 1. representative block diagram figure 2. timing diagram capacitor c t feedback/pwm comp. deadtime control flip-flop clock input flip-flop q flip-flop q output q1 emitter output q2 emitter output control 6 r t c t 5 4 deadtime control oscillator 0.12v 0.7v 0.7ma + 1 - - + - + + 2 - d q ck - + + - 3.5v 4.9v 13 reference regulator q1 q2 8 9 11 10 12 v cc v cc 12 3 1516 14 7 error amp 1 feedback pwm comparator input ref. output gnd uv lockout flip- flop output control error amp 2 deadtime comparator pwm comparator q this device contains 46 active transistors.
tl594 http://onsemi.com 5 applications information description the tl594 is a fixedfrequency pulse width modulation control circuit, incorporating the primary building blocks required for the control of a switching power supply. (see figure 1.) an internallinear sawtooth oscillator is frequency programmable by two external components, r t and c t . the approximate oscillator frequency is determined by: f osc 1.1 r t ? c t for more information refer to figure 3. output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor c t to either of two control signals. the nor gates, which drive output transistors q1 and q2, are enabled only when the flipflop clockinput line is in its low state. this happens only during that portion of time when the sawtooth voltage is greater than the control signals. therefore, an increase in controlsignal amplitude causes a corresponding linear decrease of output pulse width. (refer to the timing diagram shown in figure 2.) the control signals are external inputs that can be fed into the deadtime control, the error amplifier inputs, or the feedback input. the deadtime control comparator has an effective 120 mv input offset which limits the minimum output deadtime to approximately the first 4% of the sawtoothcycle time. this would result in a maximum duty cycle on a given output of 96% with the output control grounded, and 48% with it connected to the reference line. additional deadtime may be imposed on the output by setting the deadtimecontrol input to a fixed voltage, ranging between 0 v to 3.3 v. the pulse width modulator comparator provides a means for the error amplifiers to adjust the output pulse width from the maximum percent ontime, established by the deadtime control input, down to zero, as the voltage at the feedback pin varies from 0.5 v to 3.5 v. both error amplifiers have a commonmode input range from 0.3 v to (v cc 2 v), and may be used to sense powersupply output voltage and current. the erroramplifier outputs are active high and are ored together at the noninverting input of the pulsewidth modulator comparator. with this configuration, the amplifier that demands minimum output on time, dominates control of the loop. functional table input/output controls output function f out f osc = grounded singleended pwm @ q1 and q2 1.0 @ v ref pushpull operation 0.5 when capacitor c t is discharged, a positive pulse is generated on the output of the deadtime comparator, which clocks the pulsesteering flipflop and inhibits the output transistors, q1 and q2. with the outputcontrol connected to the reference line, the pulsesteering flipflop directs the modulated pulses to each of the two output transistors alternately for pushpull operation. the output frequency is equal to half that of the oscillator. output drive can also be taken from q1 or q2, when singleended operation with a maximum ontime of less than 50% is required. this is desirable when the output transformer has a ringback winding with a catch diode used for snubbing. when higher outputdrive currents are required for singleended operation, q1 and q2 may be connected in parallel, and the outputmode pin must be tied to ground to disable the flipflop. the output frequency will now be equal to that of the oscillator. the tl594 has an internal 5.0 v reference capable of sourcing up to 10 ma of load current for external bias circuits. the reference has an internal accuracy of 1.5% with a typical thermal drift of less than 50 mv over an operating temperature range of 0 to 70 c. figure 3. oscillator frequency versus timing resistance 1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k 200 k 500 k 1.0 m r t, timing resistance ( w ) , oscillator frequency (hz) f osc c t = 0.001 m f v cc = 15 v 0.01 m f 0.1 m f figure 4. open loop voltage gain and phase versus frequency 1.0 10 100 1.0 k 10 k 100 k 1.0 m , open loop voltage gain (db) vol f, frequency (hz) a vol 0 20 40 60 80 100 120 140 160 180 , excess phase (degrees) f f v cc = 15 v d v o = 3.0 v r l = 2.0 k w a 500 k 100 k 10 k 1.0 k 500 120 110 100 90 80 70 60 50 40 30 20 10 0
tl594 http://onsemi.com 6 figure 5. percent deadtime versus oscillator frequency figure 6. percent duty cycle versus deadtime control voltage figure 7. emitterfollower configuration output saturation voltage versus emitter current 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 500 k 1.0 k 10 k 100 k 500 k f osc , oscillator frequency (hz) % dt, percent deadtime (each output) c t = 0.001 m f 0.01 m f 50 40 30 20 10 0 0 1.0 2.0 3.0 3.5 v dt , deadtime control voltage (iv) % dc, percent duty cycle (each output ) v cc = 15 v v oc = v ref 1.c t = 0.01 m f 1. r t = 10 k w 2.c t = 0.001 m f 1. r t = 30 k w 2 1 figure 8. commonemitter configuration output saturation voltage versus collector current 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 0 100 200 300 400 i e, emitter current (ma) , saturation voltage (v) ce(sat) v 0 100 200 300 400 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 i c , collector current (ma) , saturation voltage (v) ce(sat) v figure 9. standby supply current versus supply voltage 10 9.8 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 5.0 10 15 20 25 30 35 40 cc , supply current (ma) v cc , supply voltage (v) i figure 10. undervoltage lockout thresholds versus reference load current 6.0 5.5 5.0 4.5 4.0 0 5.0 10 15 20 25 30 35 40 th , undervoltage lockout threshold (v) i l , reference load curernt (ma) v turn on turn off
tl594 http://onsemi.com 7 figure 11. erroramplifier characteristics figure 12. deadtime and feedback control circuit figure 13. commonemitter configuration test circuit and waveform + + v in error amplifier under test feedback terminal (pin 3) other error amplifier v ref v cc = 15v 150 2w output 1 output 2 c1 e1 c2 e2 ref out gnd output control (+) (+) (-) (-) feedback deadtime error v cc test inputs 50k r t c t 150 2w figure 14. emitterfollower configuration test circuit and waveform r l 68 v c c l 15pf c e q each output transistor 15v 90% v cc 10% 90% 10% t r t f r l 68 v ee c l 15pf c e q each output transistor 15v 90% v ee 10% 90% 10% t r t f - - gnd
tl594 http://onsemi.com 8 figure 15. erroramplifier sensing techniques figure 16. deadtime control circuit figure 17. softstart circuit figure 18. output connections for singleended and pushpull configurations v o to output voltage of system r1 1 2 v ref r2 + error amp positive output voltage v o = v ref 1 + r 1 3 + 1 2 v ref r2 v o r1 negative output voltage - to output voltage of system error amp - v o = v ref r 1 r1 r2 output control output q r t c t d t v ref 4 5 6 0.001 30k r 1 r 2 max. % on time, each output 45 - 80 1 + output q v ref 4 d t c s r s output control single-ended q 1 q 2 q c 1.0 ma to 500 ma q e 2.4 v v oc v ref push-pull q 1 q 2 c 1 e 1 c 2 e 2 1.0 ma to 250 ma 1.0 ma to 250 ma output control 0 v oc 0.4 v c 1 e 1 c 2 e 2 r 2 r 2 3
tl594 http://onsemi.com 9 figure 19. slaving two or more control circuits figure 20. operation with v in > 40 v using external zener r t c t 6 5 v ref r t c t master v ref slave (additional circuits) r t c t 5 6 v in > 40v r s v z = 39v 1n975a v cc 5.0v ref 12 270 gnd 7 +v in = 8.0v to 20v 1 2 3 15 16 + - - + comp oc v ref dt c t r t gnd e 1 e 2 13144567910 1.0m 33k 0.01 0.01 v cc c 1 c 2 8 11 47 47 10 + 10k 4.7k 4.7k 15k tip 32 + t 1 1n4934 l 1 1n4934 240 + 50 35v 4.7k 1.0 22 k + +v o = 28v i o = 0.2a 12 all capacitors in m f tl594 0.001 50 35v 50 25v tip 32 test conditions results l1 35mh@03a line regulation v in = 10 v to 40 v 14 mv 0.28% l1 - 3.5 mh @ 0.3 a t1 - primary: 20t c.t. #28 awg load regulation v in = 28 v, i o = 1.0 ma to 1.0 a 3.0 mv 0.06% t1 primary: 20t c . t . #28 awg t1 - secondary: 12ot c.t. #36 awg t1 - co r e : f e rr o x cube 14 08 p-l 00 - 3c b output ripple v in = 28 v, i o = 1.0 a 65 mvpp p.a.r.d. t1 - core: ferroxcube 1408p - l00 - 3cb short circuit current v in = 28 v, r l = 0.1 w 1.6 a efficiency v in = 28 v, i o = 1.0 a 71% figure 21. pulse width modulated pushpull converter
tl594 http://onsemi.com 10 +v in = 10v to 40v tip 32a 1.0mh @ 2.0a +v o = 5.0v i o = 1.0a 50 10v + 5.1k mr850 0.1 150 5.1k 5.1k 47k 1.0m 0.1 3 2 1 14 15 16 comp - + - v ref + v cc c 1 c 2 50 50v 0.001 56 4137910 c t r t d.t. o.c. gnd e 1 e 2 + 47k + 500 10v 150 47 11 12 8 tl594 test conditions results line regulation v in = 8.0 v to 40 v 3.0 mv 0.01% load regulation v in = 12.6 v, i o = 0.2 ma to 200 ma 5.0 mv 0.02% output ripple v in = 12.6 v, i o = 200 ma 40 mvpp p.a.r.d. short circuit current v in = 12.6 v, r l = 0.1 w 250 ma efficiency v in = 12.6 v, i o = 200 ma 72% figure 22. pulse width modulated stepdown converter ordering information device operating temperature range package shipping tl594cd 25 to 85 c soic16 48 units/rail tl594cdr2 25 to 85 c soic16 2400 tape & reel tl594cn 25 to 85 c pdip16 25 units/rail tl594cdtb 25 to 85 c tssop16 96 units/rail tl594cdtbr2 25 to 85 c tssop16 2500 tape & reel
tl594 http://onsemi.com 11 package dimensions pdip16 n suffix case 64808 issue r min min max max inches millimeters dim a b c d f g h j k l m s 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. 2.54 bsc 1.27 bsc 0.100 bsc 0.050 bsc a b 18 9 16 f h g d 16 pl s c t seating plane k j m l ta 0.25 (0.010) m m 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 a b d 16pl k c g t seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m soic16 d suffix case 751b05 issue j
tl594 http://onsemi.com 12 package dimensions tssop16 dtb suffix case 948f01 issue o ??? ??? section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. tl594/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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