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? no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ? anyone purchasing any products described or contained herein for an above-mentioned use shall : 1) accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use : 2) not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ? information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. note : this product includes the iic bus interface circuit. if you intend to use the iic bus interface, please notify us of this in advance of our receiving your program rom code order. purchase of sanyo iic components conveys a license under the philips iic patents rights to use these components in an iic system, provided that the system conforms to the iic standard specification as defined by philips. trademarks iic is a trademark of philips corporation. this production is produced and sold by sanyo under license of the silicon storage technology inc. this catalog provides information as of december 2000. specifications and information herein are subject to change without notice. sanyo electric co., ltd. semiconductor company system-lsi div. system-microcomputer development dep. 1-1-1, sakata oizumi-machi, gunma, japan ver.1.00 system-lsi 2000-12-27 m.sato 1/23 8-bit single chip microcontroller preliminary LC86F3264A LC86F3264A 8-bit single chip microcontroller with on-chip 96k-byte flash memory (rom 64k-byte + cgrom 16k-byte + extended rom 16k-byte), on-chip 640-byte ram and 352 9 bit display ram overview the LC86F3264A is a cmos 8-bit single chip microcontroller with flash memory for the lc863200series. this microcontroller contains the following on-chip functional blocks: - cpu : operable at a minimum bus cycle time of 0.424s - on-chip rom capacity : 96k bytes flash memory program rom : 64k bytes cgrom : 16k bytes extended rom : 16k bytes - on-chip ram capacity : 640 bytes - display ram : 352 9 bits - closed-caption tv controller and the on-screen display controller - closed-caption data slicer - four channels 8-bit ad converter - three channels 7-bit pwm - two 16-bit timer/counters, 14-bit base timer - 8-bit synchronous serial interf ace circuit - iic-bus compliant serial interface circuit (multi-master type) - rom correct function - 16-source 10-vectored interrupt system - integrated system clock generator and display clock generator only one x ? tal oscillator (32.768khz) for pll reference is used for both generators all of the above functions are fabricated on a single chip. the program is rewritable by using the on-board writing system after the lsi has been installed on the application board.
LC86F3264A 2/23 ver.1.00 features (1) built-in flash memory : 96k bytes - program rom 64k bytes - character rom 16k bytes - extended rom 16k bytes - rewritable in page units 128 bytes / page - page erase / program cycle 100 cycle per page (2) built-in random access memory (ram) : 640 8 bits (including 128 bytes for rom correction function) 352 9 bits (for crt display) the LC86F3264A consists of 64k of rom space and 640 bytes of ram space. for this microcontroller, the usable program rom capacity and ram capacity are the same size for the mask rom version. mask rom versions compatible with the LC86F3264A program rom limit set for the LC86F3264A ram limit set for the LC86F3264A (including 128 bytes for the rom correction function) lc863264 65024 bytes 640 bytes lc863256 57344 bytes 640 bytes lc863248 49152 bytes 640 bytes lc863240 40960 bytes 640 bytes lc863232 32768 bytes 512 bytes lc863228 28672 bytes 512 bytes lc863224 24576 bytes 512 bytes lc863220 20480 bytes 512 bytes lc863216 16384 bytes 512 bytes (3) osd functions - screen display : 36 characters 16 lines (by software) - ram : 352 words (9 bits per word) display area : 36 words 8 lines control area : 8 words 8 lines - characters up to 252 kinds of 16 32 dot characters (4 characters including 1 test character are not programmable) each font can be divided into two parts and used as two fonts (ex. 16 16 dot character font 2) at least 111 characters need to be divide between a 1618 dot and 8 9 dot character font to display the caption fonts. - various character attributes character colors : 16 colors character background colors : 16 colors fringe / shadow colors : 16 colors full screen colors : 16colors rounding underline italic character (slanting) - attribute can be changed without spacing - vertical display start line number can be set for each row independently (rows can be overlapped) - horizontal display start position can be set for each row independently - horizontal pitch (9 - 16 dot) *1 and vertical pitch (1 - 32 dot) can be set for each row independently - different display modes can be set for each row independently caption ? text mode / osd mode 1 / osd mode 2 (quarter size) / simplified graphic mode - ten character sizes *1
LC86F3264A ver.1.00 3/23 horiz. vert. = (1 1), (1 2), (2 2), (2 4) (1.5 1), (1.5 2), (3 2), (3 4), (0.5 0.5), (0.75 0.5) - shuttering and scrolling on each row - simplified graphic display *1 note : range depends on display mode : refer to manual for details. (4) data slicer (ntsc) - line 21 closed caption data and xds data extraction (5) bus cycle time / instruction-cycle time bus cycle time instruction cycle time system clock oscillation oscillation frequency voltage 0.424s 0.848s internal vco (ref : x ? tal 32.768khz) 14.156mhz 4.5v to 5.5v 7.5s 15.0s internal rc 800khz 4.5v to 5.5v 183.1s 366.2s crystal 32.768khz 4.5v to 5.5v (6) ports - input / output ports : 5 ports (28 terminals) data direction programmable in nibble units : 1 port (8 terminals) (if the n-ch open drain output is selected by option, the corresponding port data can be read in output mode.) data direction programmable for each bit individually: 4 ports (20 terminals) (7) ad converter - 4-channels 8-bit ad converters (8) serial interfaces - iic-bus compatible serial interface (multi-master type) consists of a single built-in circuit with two i/o channels the two data lines and two clock lines can be short circuited internally. - synchronous 8-bit serial interface (9) pwm output - 3-channels 7-bit pwm (10) timer - timer 0 : 16-bit timer/counter with 2-bit prescaler + 8-bit built-in programmable prescaler mode 0 : two 8-bit timers with a programmable prescaler mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter mode 2 : 16-bit timer with a programmable prescaler mode 3 : 16-bit counter the resolution of timer is 1 tcyc. - timer 1 : 16-bit timer/pwm mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : variable bit pwm (9 to 16 bits) in mode 0/1, the resolution of timer1/pwm is 1 tcyc in mode 2/3, the resolution is selectable by program; tcyc or 1/2 tcyc - base timer
LC86F3264A 4/23 ver.1.00 generate every 500ms overflow for a clock application (using 32.768khz crystal oscillation for the base timer clock) generate every 976s, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768khz crystal oscillation for the base timer clock) clock for the base timer is selectable from 32.768khz crystal oscillation, system clock or programmable prescaler output of timer 0 (11) remote control receiver circuit (connected to the p73/int3/t0in terminal) - noise rejection function - polarity switching (12) watchdog timer external rc circuit is required interrupt or system reset is activated when the timer overflows (13) rom correction function max 128 bytes/2 address (14) interrupts - 16-source 10-vectored interrupts 1. external interrupt int0 2. external interrupt int1 3. external interrupt int2, timer/counter t0l (lower 8 bits) 4. external interrupt int3, base timer 5. timer/counter t0h (upper 8 bits) 6. timer t1h,t1l 7. sio0 8. data slicer 9. vertical synchronous signal interrupt ( vs ), scanning line, ad 10. iic, port 0 - interrupt priority control three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. low or high priority can be assigned to the interrupts from 3 to 10 listed above. for the external interrupt int0 and int1, high or highest priority can be set. (15) sub-routine stack level - a maximum of 128 levels (stack area is assigned on the internal ram) (16) multiplication/division instruction - 16 bits 8 bits (7 instruction cycle times) - 16 bits / 8 bits (7 instruction cycle times) (17) 3 oscillation circuits - built-in rc oscillation circuit used for the system clock - built-in vco circuit used for the system clock and osd clock - on-chip x ? tal oscillation circuit used for pll reference and the system clock and base timer clock (18) standby function - halt mode the halt mode is used to reduce the power dissipation. in this operation mode, the program execution is stopped. this mode can be released by the interrupt request signals or the system reset. - hold mode the hold mode is used to stop oscillations ; the rc (internal),vco, and the x ? tal oscillations. this mode can be released by the following conditions. ? pull the reset terminal ( res ) to low level. ? feed the selected level to either p70/int0 or p71/int1.
LC86F3264A ver.1.00 5/23 ? feed the port 0 interrupt condition (19) applicable mask rom version - lc863264 / lc863256/ lc863248 / lc863240 / lc863232 / lc863228 / lc863224 / lc863220 / lc863216 (20) package - dip42s - qip48e (21) development tools - evaluation chip: lc863096 - emulator: eva86000(main) + ecb863200(evaluation chip board) + pod863200(pod:dip42s) or pod863201(qip48e) write flash memory sanyo provides special services including writing data to flash memory and stamping. there is a charge for these services. please feel free to ask our sales persons for details.
LC86F3264A 6/23 ver.1.00 system block diagram alu acc psw rar ram iic timer 0 adc pwm cgrom vram base timer osd control circuit b register c register stack pointer port 0 watch dog timer timer 1 port 8 port 7 port 6 port 1 bus interface sio 0 rom correct control xram data slicer pc ce oe we d0-d7 a0-a16 interrupt control standby control clock generator x'tal rc vco pll ir pla flash memory control flash memory (96kb) int0 - 3 noise rejection filter
LC86F3264A ver.1.00 7/23 pin assignment ? dip42s 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 10 p16 vss xt1 xt2 vdd p07 p06 p05 p04 p03 p02 p01 p00 p73/int3/t0in p72/int2/t0in p71/int1 p70/int0 p84/an4 p85/an5 p87/an7 p86/an6 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 res vs hs p17/pwm p15/pwm3 p14/pwm2 p13/pwm1 i r g b bl p63/sclk1 p62/sda1 p61/sclk0 p60/sda0 p10/so0 p11/si0 p12/sck0 filt cvin ? qip48e 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 13 14 15 16 17 18 19 20 21 22 23 24 p15/pwm3 p16 p17/pwm vss xt1 xt2 vdd nc p84/an4 p85/an5 p86/an6 p87/an7 nc p14/pwm2 p13/pwm1 p12/sck0 p11/si0 p10/so0 nc p07 p06 p05 p04 p03 p02 p01 p00 nc p71/int1 p70/int0 p63/sclk1 p62/sda1 p61/sclk0 p60/sda0 nc i bl b g r hs vs nc cvin filt res p73/int3/t0in p72/int2/t0in
LC86F3264A 8/23 ver.1.00 pin description pin description table terminal i/o function description option flash memory mode (parallel input/ output mode) vss - negative power supply xt1 i input terminal for crystal oscillator xt2 o output terminal for crystal oscillator vdd - positive power supply res i reset terminal input to set up mode filt o filter terminal for pll address input a16 cvin i video signal input terminal vs i vertical synchronization signal input terminal input to set up mode hs i horizontal synchronization signal input terminal r o red (r) output terminal of rgb image output g o green (g) output terminal of rgb image output b o blue (b) output terminal of rgb image output address input a15 i o intensity ( i ) output terminal of rgb image output address input a13 bl o fast blanking control signal switch tv image signal and caption/ osd image signal address input a14 port 0 p00 - p07 i/o ?8-bit input/output port, input/output can be specified in nibble unit ?other functions hold release input interrupt input pull-up register present/ not present output format cmos/nch-od address input a0 to a7 port 1 ?8-bit input/output port input/output can be specified in a bit ?other functions p10 p11 p12 p13 p14 p15 p17 sio0 data output sio0 data input/bus input/output sio0 clock input/output pwm1 output pwm2 output pwm3 output timer1 (pwm) output p10 - p17 i/o output format cmos/nch-od data input/output d0 to d7 port 6 ?4-bit input/output port input/output can be specified for each bit ?other functions p60 p61 p62 p63 iic0 data i/o iic0 clock output iic1 data i/o iic1 clock output p60 - p63 i/o control signal ce control signal oe control signal we address input a12
LC86F3264A ver.1.00 9/23 terminal i/o function description option flash memory mode (parallel input/ output mode) port 7 ?4-bit input/output port input or output can be specified for each bit ?other function p70 p71 p72 p73 int0 input/hold release input/ nch-tr. output for watchdog timer int1 input/hold release input int2 input/timer 0 event input int3 input (noise rejection filter attached)/timer 0 event input interrupt receiver format, vector addresses address input a8 to a11 rising falling rising/ falling h level l level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h p70 p71 - p73 i/o int3 enable enable enable disable disable 1bh port 8 p84 - p87 i/o ?4-bit input/output port input or output can be specified for each bit ?other function ad converter input port (4 lines) nc - unused terminal leave open ? output form and existence of pull-up resistor for every port can be specified for each bit. ? programmable pull-up resister is always connected regardless of port option, cmos or n-ch open drain output in port 1. user options user options can be changed using flash memory data. a kind of option pin, circuits port 0 (specified in a bit) 1. input : without pull-up mos tr. output : n-channel open drain 2. input : with pull-up mos tr. output : cmos input/output form of input/output ports port 1 (specified in a bit) 1. input : with programmable pull-up mos tr. output : n-channel open drain 2. input : with programmable pull-up mos tr. output : cmos
LC86F3264A 10/23 ver.1.00 notice for use - input level of terminal res at power on terminal res must be held low for at least 200s after the supply voltage exceeds the power supply lower limit. power supply res vdd limit 0v more than 200?s -difference between the mask version and flash version(LC86F3264A) 1. the operation after release of reset : the mask version operates the program from the address 0 in the program counter as soon as detecting the h level on the reset port. the flash version operates the program from the address 0 in the program counter after setting the option. 2. current dissipation : the current dissipation of the flash version is bigger than that of the mask version. please refer to the latest semiconductor news. - conditions during reset and after release of reset port options are set using flash memory data. port options are set internally within approximately 3ms after logic high is applied to the reset terminal. the configuration of the port outputs change over the duration of this period. then the program counter is set to 0 and program execution begins. during reset, and in the few hundred milliseconds after reset is released, the port options on certain of the ports will not yet have been set. the conditions of the various ports during reset or on release of reset have been collected in the following table. please refer to it when analyzing circuits where these conditions apply. pins options condition during and on release of reset input : without pull up mos transistor output : n-channel open drain output -off input mode : high impedance p0 input : with pull up mos transistor output : cmos output-off during reset and in the first few hundred s after reset is released, the pull-up mos transistor is off. thereafter, set to input mode with pull-up mos tr. on input : with programmable pull up mos transistor output : n-channel open drain p1 input : with programmable pull up mos transistor output : cmos output-off input mode : pull up mos transistor off p6 no options output : n-channel open drain output -off input mode : high impedance p7 no options input : with programmable pull up mos transistor output : n-channel open drain (p70) cmos (p71 - p73) output-off input mode : pull up mos transistor off p8 no options input : with programmable pull up mos transistor output : cmos output-off input mode : pull up mos transistor off
LC86F3264A ver.1.00 11/23 on-board writing system the LC86F3264A has the on-board writing system. the program is renewable by using sanyo flash on-board system after the lsi has been installed on the application board. this system is composed of 4 types divided by the combination of the mode setting pin and communication pin. each type system has to connect the 6 pins (vdd, vss, res, communication pins ) with the interface board of sanyo flash on-board system. it is necessary that the pins to be used for the rewriting system should be able to be separated from the application board properly. the system type is selected by the option setting program (su86k.exe). types mode setting pin communication pins type1 res pin (high voltage(12v) applied) p00(data1),p01(data0),p02(clk) type2 res pin (high voltage(12v) applied) p00(data1),p60(data0),p61(clk) type3 p00 pin (high level voltage applied) p00(ena/data1),p01(data0),p02(clk) type4 p00 pin (high level voltage applied) p00(ena/data1),p60(data0),p61(clk) ? type 3 or 4 is selected : p00 is exclusive for the on-board system. this pin must always be pulled-down, so this pin can?t be used for other applications. please set p00 pin n-channel open drain output. option setting in the user program, ?0? is always set to the p00 latch (bit 0 in the port 0 latch (140h)) because the p0 interrupt must not be requested on the p00 pin . ? the loader program must be written into the rom to use on-board writing system. the loader program should be written into the rom before the lsi has been installed on the board by the the general purpose prom programs. when the option setting selects the this system to use, the loader program automatically links to the extended rom field(14000h-147ffh) on the user program linking. please ask to our sales persons before using on-board writing system. use of prom conversion board when reading or writing data to the LC86F3264A using our exclusive conversion board (w86f3264d, w86f3264q) general purpose prom programs can be used. (1) name of conversion boards - w86f3264d ? ? ? dip42s purpose - w86f3264q ? ? ? qip48e purpose (2) available prom programs the LC86F3264A does not support a silicon signature feature. do not use the feature (automatic device type selection) when programming this device. for the address range, 0 to 17fffh should be specified (fixed data ?00? is read if 1800h to 1ffffh is specified). single word write manufacture name of device version applicable device (code) data protection setting after write operation minato electronics model 1890a + ou-910 v4.1 sst co., ltd. 29ee010 (d734) protected ando af-9708 01.00 sst co., ltd. 29ee010 (47101) protected data i. o. chiplab v5.3 sst co., ltd. 29ee010 selectable
LC86F3264A 12/23 ver.1.00 write multiple words manufacture name of device version applicable device (code) data protection setting after write operation minato electronics model 1892 + type9102a v4.1 sst co., ltd. 29ee010 (d734) protected (3) notes when using the conversion board, all of the jumper sw must be set to the off position. if set to the on position, read/write operations will not perform correctly. (4) location of pin 1 pin 1 of the conversion board should be located as indicated below. w86f3264d : when viewing from the edge closest to jumper sw, pin 1 is located on the lower right of both the chip and conversion board. w86f3264q : when viewing from the edge closest to jumper sw, pin 1 of the chip is located on the upper right while pin 1 of the conversion board is located on the lower right. w86f3264d w86f3264q chip : pin1 pin1 pin1 set j um p er sw to off set jumper sw to off
LC86F3264A ver.1.00 13/23 1. absolute maximum ratings / vss=0v and ta=25c limits parameter symbol pins conditions vdd[v] min. typ. max. unit supply voltage vddmax vdd -0.3 +6.0 input voltage vi(1) ? res , hs , vs , cvin -0.3 vdd+0.3 output voltage vo(1) r, g, b, i, bl, filt -0.3 vdd+0.3 input/output voltage vio ?ports 0, 1, 6, 7, 8 -0.3 vdd+0.3 v ioph(1) ?ports 0, 1, 7, 8 ?cmos output ?for each pin. -4 peak output current ioph(2) r, g, b, i, bl ?cmos output ?for each pin. -5 ioah(1) ?ports 0, 1 the total of all pins. -20 ioah(2) ports 7, 8 the total of all pins. -10 high level output current total output current ioah(3) r, g, b, i, bl the total of all pins. -15 iopl(1) ports 0, 1, 6, 8 for each pin. 20 iopl(2) port 7 for each pin. 15 peak output current iopl(3) r, g, b, i, bl for each pin. 5 ioal(1) ports 0, 1 the total of all pins. 40 ioal(2) ports 6, 7, 8 the total of all pins. 30 low level output current total output current ioal(3) r, g, b, i, bl the total of all pins. 15 ma dip42s 850 maximum power dissipation pdmax qip48e ta=-10 to +70c 440 mw operating temperature range topr -10 +70 storage temperature range tstg -55 +125 c
LC86F3264A 14/23 ver.1.00 2. recommended operating range / ta= -10c to +70c, vss=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit vdd(1) 0.844s t cyc 0.852s 4.5 5.5 operating supply voltage range vdd(2) vdd 4s t cyc 400s 4.5 5.5 hold voltage vhd vdd rams and the registers data are kept in hold mode. 2.0 5.5 vih(1) port 0 (schumitt) output disable 4.5 - 5.5 0.6vdd vdd vih(2) ?ports 1,6 (schumitt) ?port 7 (schumitt) port input/interrupt ? hs , vs , res (schumitt) output disable 4.5 - 5.5 0.75vdd vdd vih(3) port 70 watchdog timer input output disable 4.5 - 5.5 vdd-0.5 vdd high level input voltage vih(4) ?port 8 port input output disable 4.5 - 5.5 0.7vdd vdd vil(1) port 0 (schumitt) output disable 4.5 - 5.5 vss 0.2vdd vil(2) ?ports 1,6 (schumitt) ?port 7 (schumitt) port input/interrupt ? hs , vs , res (schumitt) output disable 4.5 - 5.5 vss 0.25vdd vil(3) port 70 watchdog timer input output disable 4.5 - 5.5 vss 0.6vdd low level input voltage vil(4) port 8 port input output disable 4.5 - 5.5 vss 0.3vdd v cvin vcvin cvin 5.0 1vp-p -3db 1vp-p 1vp-p +3db vp-p * t cyc (1) ?all functions operationg 4.5 - 5.5 0.844 0.848 0.852 t cyc (2) ?ad converter operating ?osd and data slicer are not operating 4.5 - 5.5 0.844 30 operation cycle time tcyc(3) ?osd, ad converter and data slicer are not operating 4.5 - 5.5 0.844 400 s oscillation frequency range fmrc internal rc oscillation 4.5 - 5.5 0.4 0.8 3.0 mhz * vp-p : peak-to-peak voltage
LC86F3264A ver.1.00 15/23 3. electrical characteristics / ta= -10c to +70c, vss=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0, 1, 6, 7, 8, ?output disable ?pull-up mos tr. off ?vin=vdd (including the off- leak current of the output tr.) 4.5 - 5.5 1 high level input current iih(2) ? res ? hs , vs ?vin=vdd 4.5 - 5.5 1 iil(1) ports 0, 1, 6, 7, 8, ?output disable ?pull-up mos tr. off ?vin=vss (including the off- leak current of the output tr.) 4.5 - 5.5 -1 low level input current iil(2) ? res ? hs , vs vin=vss 4.5 - 5.5 -1 a voh(1) ?cmos output of ports 0,1,71-73,8 ioh=-1.0ma 4.5 - 5.5 vdd-1 high level output voltage voh(2) r, g, b, i, bl ioh=-0.1ma 4.5 - 5.5 vdd-0.5 vol(1) ports 0,1,71-73,8 iol=10ma 4.5 - 5.5 1.5 vol(2) ports 0,1,71-73,8 iol=1.6ma 4.5 - 5.5 0.4 vol(3) ?r, g, b, i, bl ?port 6 iol=3.0ma 4.5 - 5.5 0.4 vol(4) port 6 iol=6.0ma 4.5 - 5.5 0.6 low level output voltage vol(5) port 70 iol=1ma 4.5 - 5.5 0.4 v pull-up mos tr. resistance rpu ?ports 0, 1, 7, 8 voh=0.9vdd 4.5 - 5.5 13 38 80 k ? bus terminal short circuit resistance (scl0-scl1, sda0-sda1) rbs ?p60-p62 ?p61-p63 4.5 - 5.5 130 ? hysteresis voltage vhis ?ports 0, 1, 6, 7 ? res ? hs , vs output disable 4.5 - 5.5 0.1vdd input clump voltage vclmp cvin 5.0 2.3 2.5 2.7 v pin capacitance cp all pins ?f=1mhz ?every other terminals are connected to vss. ?ta=25c 4.5 - 5.5 10 pf
LC86F3264A 16/23 ver.1.00 4. serial input/output characteristics / ta= -10c to +70c, vss=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit cycle t ckcy (1) 2 low level pulse width t ckl (1) 1 input clock high level pulse width t ckh (1) ?sck0 ?sclk0 refer to figure 4. 4.5 - 5.5 1 cycle t ckcy (2) 2 low level pulse width t ckl (2) 1/2tckc y serial clock output clock high level pulse width t ckh (2) ?sck0 ?sclk0 ?use pull-up resistor (1k ? ) when nch open- drain output. ?refer to figure 4. 4.5 - 5.5 1/2tckc y t cyc data set up time t ick 0.1 serial input data hold time t cki si0 ?data set-up to sck0. ?data hold from sck0. ?refer to figure 4. 4.5 - 5.5 0.1 output delay time (using external clock) t cko(1) so0 4.5 - 5.5 7/12tcyc +0.2 serial output output delay time (using internal clock) t cko(2) so0 ?data hold from sck0. ?use pull-up resistor (1k ? ) when nch open- drain output. ?refer to figure 4. 4.5 - 5.5 1/3tcyc +0.2 s 5. iic input/output conditions / ta= -10c to +70c, vss=0v standard high speed parameter symbol min. max. min. max. unit scl frequency f scl 0 100 0 400 khz bus free time between stop - start t buf 4.7 - 1.3 - s hold time of start, restart condition t hd;sta 4.0 - 0.6 - s l time of scl t low 4.7 - 1.3 - s h time of scl t high 4.0 - 0.6 - s set-up time of restart condition t su;sta 4.7 - 0.6 - s hold time of sda t hd;dat 0 - 0 0.9 s set-up time of sda t su;dat 250 - 100 - ns rising time of sda, scl t r - 1000 20+0.1cb 300 ns falling time of sda, scl t f - 300 20+0.1cb 300 ns set-up time of stop condition t su;sto 4.0 - 0.6 - s refer to figure 10 (note) cb : total capacitance of all bus (unit : pf)
LC86F3264A ver.1.00 17/23 6. pulse input conditions / ta= -10c to +70c, vss=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) ?int0, int1 ?int2/t0in ?interrupt acceptable ?timer0-countable 4.5 - 5.5 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock is selected to 1tcyc.) ?interrupt acceptable ?timer0-countable 4.5 - 5.5 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock is selected to 16tcyc.) ?interrupt acceptable ?timer0-countable 4.5 - 5.5 32 tpih(4) tpil(4) int3/t0in (the noise rejection clock is selected to 64tcyc.) ?interrupt acceptable ?timer0-countable 4.5 - 5.5 128 t cyc tpil(5) res reset acceptable 4.5 - 5.5 200 high/low level pulse width tpih(6) tpil(6) hs , vs ?display position controllable (note) ?the active edge of hs and vs must be apart at least 1 t cyc . ?refer to figure 6. 4.5 - 5.5 8 s rising/falling time tthl ttlh hs refer to figure 6. 4.5 - 5.5 500 ns 7. ad converter characteristics / ta= -10c to + 70c, vss=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 8 bit absolute precision et (note 3) 1.5 lsb adcr2=0 (note 4) 16 conversion time tcad adcr2=1 (note 4) 32 t cyc analog input voltage range vain vss vdd v iainh vain=vdd 1 analog port input current iainl an4 - an7 vain=vss 4.5 ? 5.5 -1 a (note 3) absolute precision does not include quantizing error (1/2lsb). (note 4) conversion time is the time till the complete digital conversion value for analog input value is set to a register after the instruction to start conversion is sent.
LC86F3264A 18/23 ver.1.00 8. sample current dissipation characteristics / ta= -10c to +70c, vss=0v the sample current dissipation characteristics is the measurement result of sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. the currents through the output transistors and the pull-up mos transistors are ignored. limits parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) vdd ?fmx?tal=32.768khz x?tal oscillation ?system clock : vco for system ?vco for osd operating ?internal rc oscillation stops 4.5 - 5.5 31 49 ma current dissipation during basic operation (note 3) iddhalt(1) vdd ?halt mode ?fmx?tal=32.768khz x?tal oscillation ?vco for system stops ?system clock : vco for system, ? internal rc stops 4.5 - 5.5 7 11 ma iddhalt(2) vdd ?halt mode ?fmx?tal=32.768khz x?tal oscillation ?vco for system stops ?vco for osd stops ?system clock : internal rc 4.5 - 5.5 500 1200 current dissipation in halt mode (note 3) iddhalt(3) vdd ?halt mode ?fmx?tal=32.768khz x?tal oscillation ?vco for system stops ?vco for osd stops ?system clock : x?tal 4.5 - 5.5 60 200 a current dissipation in hold mode (note 3) iddhold vdd ?hold mode ?all oscillation stops. 4.5 - 5.5 0.05 20 a (note 3) the currents of the output transistors and the pull-up mos transistors are ignored.
LC86F3264A ver.1.00 19/23 recommended oscillation circuit and sample characteristics the sample oscillation circuit characteristics in the table below is based on the following conditions: ? recommended circuit parameters are verified by an oscillator manufacturer using a sanyo provided oscillation evaluation board. ? sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. recommended oscillation circuit and sample characteristics (ta = -10 to +70c) recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rf rd operating supply voltage range typ. max notes 32.768khz seiko epson c-002rx 18pf 18pf open 680k ? 4.5-5.5v 1.00s 1.50s notes the oscillation stabilizing time period is the time until the vco oscillation for the internal system becomes stable after the following conditions. (refer to figure 2.) 1. the vdd becomes higher than the minimum operating voltage after the power is supplied. 2. the hold mode is released. the sample oscillation circuit characteristics may differ applications. for further assistance, please contact with oscillator manufacturer with the following notes in your mind. ? since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. ? the above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10c to + 70c. for the use with the temperature outside of the range herein, or in the application requiring high reliability such as car products, please consult with oscillator manufacturer. ? when using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with sanyo sales personnel. since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. ? the distance between the clock i/o terminal (xt1 terminal xt2 terminal) and external parts should be as short as possible. ? the capacitors? vss should be allocated close to the microcontroller?s gnd terminal and be away from other gnd. ? the signal lines with rapid state change or with large current should be allocated away from the oscillation circuit. xt1 xt2 x'tal rd rf c2 c1 figure 1 recommended oscillation circuit
LC86F3264A 20/23 ver.1.00 power supply res internal rc resonator oscillation xt1, xt2 vco for system operation mode reset time tmsvco vdd vdd limit 0v stable instruction execution mode reset unfixed < reset time and oscillation stabilizing time. > hold release signal internal rc resonator oscillation xt1, xt2 operation mode vco for system instruction execution mode hold < hold release signal and oscillation stabilizing time. > valid tmsvco stable figure 2 oscillation stabilizing time
LC86F3264A ver.1.00 21/23 res vdd r res c res figure 3 reset circuit 0.5vdd < ac timing measurement point > tick tcki tckl tckh tckcy vdd 1k?? 50pf sb0 so0 si0 sck0 tcko < timing > < test load > figure 4 serial input / output test condition tpil tpih figure 5 pulse input timing condition - 1 (note) determine the c res , r res value to get more than 200s reset time.
LC86F3264A 22/23 ver.1.00 hs vs ttlh 0.75vdd 0.25vdd more than }1tcyc tpil(6) tpil(6) figure 6 pulse input timing condition - 2 hs c536 10k?? hs LC86F3264A figure 7 recommended interface circuit cvin coupling capacitor noise filter c-video 1000pf 200?? 1?f output impedance of c-video before noise filter should be less then 100 ? . figure 8 cvin recommended circuit
LC86F3264A ver.1.00 23/23 - filt + 1m?? 100?? 33000pf 2.2?f figure 9 filt recommended circuit (note) place filt parts on board as close to the microcomputer as possible. tr thd;sta thd;dat tlow thigh tf tsu;dat thd;sta tsu;sta tsp tsu;sto scl sr p sda tbuf p s s : start condition tsp : spike suppression standard mode : not exist p : stop condition high speed mode : less than 50ns sr : restart condition figure 10 iic timing ?2000 sanyo

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