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| maxim integrated products 1 general description the max5823/max5824/MAX5825 8-channel, low-power, 8-/10-/12-bit, voltage-output digital-to-analog converters (dacs) include output buffers and an internal 3ppm/c reference that is selectable to be 2.048v, 2.500v, or 4.096v. the max5823/max5824/MAX5825 accept a wide supply voltage range of 2.7v to 5.5v with extremely low power (6mw) consumption to accommodate most low-voltage applications. a precision external reference input allows rail-to-rail operation and presents a 100k i (typ) load to an external reference. the max5823/max5824/MAX5825 have an i 2 c-compatible, 2-wire interface that operates at clock rates up to 400khz. the dac output is buffered and has a low sup - ply current of less than 250 f a per channel and a low offset error of q 0.5mv (typ). on power-up, the max5823/ max5824/MAX5825 reset the dac outputs to zero or mid- scale based on the status of m/ z logic input, providing flexibility for a variety of control applications. the internal reference is initially powered down to allow use of an external reference. the max5823/max5824/MAX5825 allow simultaneous output updates using software load commands or the hardware load dac logic input ( ldac ). the max5823/max5824/MAX5825 feature a watchdog function which can be enabled to monitor the i/o inter - face for activity and integrity. a clear logic input ( clr ) allows the contents of the code and the dac registers to be cleared asynchronously and simultaneously sets the dac outputs to the program - mable default value. the max5823/max5824/MAX5825 are available in a 20-pin tssop and an ultra-small, 20-bump wlp package and are specified over the -40 n c to +125 n c temperature range. applications programmable voltage and current sources gain and offset adjustment automatic tuning and optical control power amplifier control and biasing process control and servo loops portable instrumentation benefits and features s eight high-accuracy dac channels ? 12-bit accuracy without adjustment ? 1 lsb inl buffered voltage output ? guaranteed monotonic over all operating conditions ? independent mode settings for each dac s three precision selectable internal references ? 2.048v, 2.500v, or 4.096v s internal output buffer ? rail-to-rail operation with external reference ? 4.5s settling time ? outputs directly drive 2k i loads s small 6.5mm x 4.4mm 20-pin tssop or ultra- small 2.5mm x 2.3mm 20-bump wlp package s wide 2.7v to 5.5v supply range s separate 1.8v to 5.5v v ddio power-supply input s fast 400khz i 2 c-compatible, 2-wire serial interface s pin-selectable power-on-reset to zero-scale or midscale dac output s ldac and clr for asynchronous dac control s three software-selectable power-down output impedances ? 1k i , 100k i , or high impedance 19-6185; rev 0; 2/12 ordering information appears at end of data sheet . functional diagram addr0 sda scl out0 buffer por watchdog timer v dd gnd dac control logic power-down ref out1 out2 out3 out4 out5 out6 out7 v ddio addr1 clr ldac irq m/z i 2 c serial interface 1ki 100ki code load clear/ reset (gate/ clear / reset) code register dac latch 8- /1 0- / 12-bit dac 1 of 8 dac channels internal reference/ external buffer max5823 max5824 MAX5825 for related parts and recommended products to use with this part, refer to: www.maxim-ic.com/max5823.related max5823/max5824/MAX5825 ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
maxim integrated products 2 v dd , v ddio to gnd ................................................ -0.3v to +6v out_, ref to gnd ....0.3v to the lower of (v dd + 0.3v) and +6v scl, sda, irq, m /z, ldac, clr to gnd ............. -0.3v to +6v addr_ to gnd ............................................ -0.3v to the lower of (v ddio + 0.3v) and +6v continuous power dissipation (t a = +70 n c) tssop (derate at 13.6mw/ n c above 70 n c) .............. 1084mw wlp (derate at 21.3mw/ n c above 70 n c) .................. 1700mw maximum continuous current into any pin .................... q 50ma operating temperature .................................... -40 n c to +125 n c storage temperature ....................................... -65 n c to +150 n c lead temperature (tssop only)(soldering, 10s) ........... +300 n c soldering temperature (reflow) .................................... +260 n c tssop junction-to-ambient thermal resistance ( ja ) ...... 73.8 n c/w junction-to-case thermal resistance ( jc ) .............. 20 n c/w wlp junction-to-ambient thermal resistance ( ja ) (note 2) ................................................................... 47 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . note 2: visit www.maxim-ic.com/app-notes/index.mvp/id/1891 for information about the thermal performance of wlp packaging. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) parameter symbol conditions min typ max units dc performance (note 4) resolution and monotonicity n max5823 8 bits max5824 10 MAX5825 12 integral nonlinearity (note 5) inl max5823 -0.25 q 0.05 +0.25 lsb max5824 -0.5 q 0.2 +0.5 MAX5825 -1 q 0.5 +1 differential nonlinearity (note 5) dnl max5823 -0.25 q 0.05 +0.25 lsb max5824 -0.5 q 0.1 +0.5 MAX5825 -1 q 0.2 +1 offset error (note 6) oe -5 q 0.5 +5 mv offset error drift q 10 f v/ n c gain error (note 6) ge -1.0 q 0.1 +1.0 %fs gain temperature coefficient with respect to v ref q 3.0 ppm of fs/ n c zero-scale error 0 +10 mv full-scale error with respect to v ref -0.5 +0.5 %fs ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 3 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) parameter symbol conditions min typ max units dac output characteristics output voltage range (note 7) no load 0 v dd v 2k i load to gnd 0 v dd - 0.2 2k i load to v dd 0.2 v dd load regulation v out = v fs /2 v dd = 3v q 10%, |i out | p 5ma 300 f v/ma v dd = 5v q 10%, |i out | p 10ma 300 dc output impedance v out = v fs /2 v dd = 3v q 10%, |i out | p 5ma 0.3 i v dd = 5v q 10%, |i out | p 10ma 0.3 maximum capacitive load handling c l 500 pf resistive load handling r l 2 k i short-circuit output current v dd = 5.5v sourcing (output shorted to gnd) 30 ma sinking (output shorted to v dd ) 50 dc power-supply rejection v dd = 3v q 10% or 5v q 10% 100 f v/v dynamic performance voltage-output slew rate sr positive and negative 1.0 v/ f s voltage-output settling time ? scale to ? scale, to p 1 lsb, max5823 2.2 f s ? scale to ? scale, to p 1 lsb, max5824 2.6 ? scale to ? scale, to p 1 lsb, MAX5825 4.5 dac glitch impulse major code transition (code x7ff to x800) 2 nv*s channel-to-channel feedthrough (note 8) internal reference 3.3 nv*s external reference 4.07 digital feedthrough midscale code, all digital inputs from 0v to v ddio 0.2 nv*s power-up time startup calibration time (note 9) 200 f s from power-down 50 f s ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 4 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) parameter symbol conditions min typ max units output voltage-noise density (dac output at midscale) external reference f = 1khz 90 nv/ hz f = 10khz 82 2.048v internal reference f = 1khz 112 f = 10khz 102 2.5v internal reference f = 1khz 125 f = 10khz 110 4.096v internal reference f = 1khz 160 f = 10khz 145 integrated output noise (dac output at midscale) external reference f = 0.1hz to 10hz 12 f v p-p f = 0.1hz to 10khz 76 f = 0.1hz to 300khz 385 2.048v internal reference f = 0.1hz to 10hz 14 f = 0.1hz to 10khz 91 f = 0.1hz to 300khz 450 2.5v internal reference f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 99 f = 0.1hz to 300khz 470 4.096v internal reference f = 0.1hz to 10hz 16 f = 0.1hz to 10khz 124 f = 0.1hz to 300khz 490 output voltage-noise density (dac output at full scale) external reference f = 1khz 114 nv/ hz f = 10khz 99 2.048v internal reference f = 1khz 175 f = 10khz 153 2.5v internal reference f = 1khz 200 f = 10khz 174 4.096v internal reference f = 1khz 295 f = 10khz 255 integrated output noise (dac output at full scale) external reference f = 0.1hz to 10hz 13 f v p-p f = 0.1hz to 10khz 94 f = 0.1hz to 300khz 540 2.048v internal reference f = 0.1hz to 10hz 19 f = 0.1hz to 10khz 143 f = 0.1hz to 300khz 685 2.5v internal reference f = 0.1hz to 10hz 21 f = 0.1hz to 10khz 159 f = 0.1hz to 300khz 705 4.096v internal reference f = 0.1hz to 10hz 26 f = 0.1hz to 10khz 213 f = 0.1hz to 300khz 750 ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 5 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) parameter symbol conditions min typ max units reference input reference input range v ref 1.24 v dd v reference input current i ref v ref = v dd = 5.5v 55 74 f a reference input impedance r ref 75 100 k i reference output reference output voltage v ref v ref = 2.048v, t a = +25 n c 2.043 2.048 2.053 v v ref = 2.5v, t a = +25 n c 2.494 2.5 2.506 v ref = 4.096v, t a = +25 n c 4.086 4.096 4.106 reference temperature coefficient (note 10) MAX5825a q 3 q 10 ppm/ n c max5823/max5824/MAX5825b q 10 q 25 reference drive capacity external load 25 k i reference capacitive load handling 200 pf reference load regulation i source = 0 to 500 f a 2 mv/ma reference line regulation 0.05 mv/v power requirements supply voltage v dd v ref = 4.096v 4.5 5.5 v all other options 2.7 5.5 i/o supply voltage v ddio 1.8 5.5 v supply current (note 11) i dd internal reference v ref = 2.048v 1.6 2 ma v ref = 2.5v 1.7 2.1 v ref = 4.096v 2.0 2.5 external reference v ref = 3v 1.6 2.0 v ref = 5v 1.9 2.5 power-down mode supply current i pd all dacs off, internal reference on 140 f a all dacs off, internal reference off, t a = -40 n c to +85 n c 0.7 2 all dacs off, internal reference off, t a = +125 n c 2 4 digital supply current i ddio static logic inputs, all outputs unloaded 1 f a digital input characteristics (scl, sda, addr0, addr1, ldac , clr, m /z ) input high voltage (note 11) v ih (all inputs except m/ z ) 2.2v < v ddio < 5.5v 0.7 x v ddio v 1.8v < v ddio < 2.2v 0.8 x v ddio v 2.7v < v dd < 5.5v (for m/ z ) 0.7 x v dd ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 6 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) parameter symbol conditions min typ max units input low voltage (note 11) v il (all inputs except m/ z ) 2.2v < v ddio < 5.5v 0.3 x v ddio v 1.8v < v ddio < 2.2v 0.2 x v ddio v 2.7v < v dd < 5.5v (for m/ z ) 0.3 x v dd input leakage current i in v in = 0v or v ddio , all inputs except m/ z (note 11) q 0.1 q 1 f a v in = 0v or v dd , for m/ z (note 11) input capacitance (note 10) c in 10 pf hysteresis voltage v h 0.15 v addr_ pullup/pulldown strength r pu , r pd (note 12) 30 50 90 k i digital output (sda, irq ) output low voltage v ol i sink = 3ma 0.2 v output inactive leakage i off irq only, see i in for sda q 0.1 q 1 f a output inactive capacitance c off irq only, see c in for sda 10 pf watchdog timer characteristics watchdog timer period t wdosc v dd = 3v, t a = +25c 0.95 1 1.05 ms watchdog timer period supply drift v dd = 2.7v to 5.5v, t a = +25c 0.6 %/v watchdog timer period temperature drift v dd = 3v 0.0375 %/c i 2 c timing characteristics (scl, sda, ldac , clr ) scl clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 f s hold time repeated for a start condition t hd;sta 0.6 f s scl pulse width low t low 1.3 f s scl pulse width high t high 0.6 f s setup time for repeated start condition t su;sta 0.6 f s data hold time t hd;dat 0 900 ns data setup time t su;dat 100 ns sda and scl receiving rise time t r 20 + c b /10 300 ns ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 7 figure 1. i 2 c serial interface timing diagram electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) note 3: limits are 100% production tested at t a = +25 n c and/or t a = +125 n c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are at t a = +25 n c and are not guaranteed. note 4: dc performance is tested without load, v ref = v dd . note 5: linearity is tested with unloaded outputs to within 20mv of gnd and v dd . note 6: gain and offset calculated from measurements made at code 30 and 4065 with v ref = v dd . note 7: subject to zero- and full-scale error limits and v ref settings. note 8: measured with all other dac outputs at midscale with one channel transitioning 0 to full scale. note 9: on power-up, the device initiates an internal 200s (typ) calibration sequence. all commands issued during this time will be ignored. note 10: guaranteed by design. note 11: all channels active at v fs , unloaded. static logic inputs with v il = v gnd and v ih = v ddio for all inputs . note 12: unconnected conditions on the addr_ inputs are sensed through a resistive pullup and pulldown operation; for proper operation, addr_ inputs must be connected to v ddio , gnd, or left unconnected with minimal capacitance. parameter symbol conditions min typ max units sda and scl receiving fall time t f 20 + c b /10 300 ns sda transmitting fall time t f 20 + c b /10 250 ns setup time for stop condition t su;sto 0.6 f s bus capacitance allowed c b v dd = 2.7v to 5.5v 10 400 pf pulse width of suppressed spike t sp 50 ns clr removal time prior to a recognized start t clrsta 100 ns clr pulse width low t clpw 20 ns ldac pulse width low t ldpw 20 ns ldac fall to sclk rise hold t ldh 400 ns t su;sto t r t sp t hd;sta t su;sta t f t high t hd;dat t low t clpw t clrsta t ld h t ldpw t hd;sta t f s s s r p sd a sc l cl r ld ac t su;dat t f t buf ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 8 typical operating characteristics (MAX5825, 12-bit performance, t a = +25c, unless otherwise noted.) inl vs. code max5823 toc01 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load inl vs. code max5823 toc02 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load dnl vs. code max5823 toc03 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load dnl vs. code max5823 toc04 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load inl and dnl vs. supply voltage max5823 toc05 supply voltage (v) error (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 max inl v dd = v ref 1.0 -1.0 2.7 5.5 max dnl min dnl min inl inl and dnl vs. temperature max5823 toc06 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (lsb) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 max inl v dd = v ref = 3v max dnl min dnl min inl offset and zero-scale error vs. supply voltage max5823 toc07 supply voltage (v) error (mv) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.7 5.5 zero-scale error offset error v ref = 2.5v (external) no load offset and zero-scale error vs. temperature max5823 toc08 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (mv) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 v ref = 2.5v (external) no load offset error (v dd = 5v) offset error (v dd = 3v) zero-scale error full-scale error and gain error vs. supply voltage max5823 toc09 supply voltage (v) error (%fs) 5.1 4.7 3.9 4.3 3.5 3.1 -0.016 -0.012 -0.008 -0.004 0 0.004 0.008 0.012 0.016 v ref = 2.5v (external) no load 0.020 -0.020 2.7 5.5 full-scale error gain error ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 9 typical operating characteristics (continued) (MAX5825, 12-bit performance, t a = +25c, unless otherwise noted.) full-scale error and gain error vs. temperature max5823 toc10 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (%fsr) -0.05 0 0.05 0.10 -0.10 v ref = 2.5v (external) no load gain error (v dd = 3v) gain error (v dd = 5v) full-scale error supply current vs. temperature max5823 toc11 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 supply current (ma) 1.2 1.4 1.6 2.0 1.8 1.0 v ref (external) = v dd = 5v v dd = v ddio v dac_ = full scale all dacs enabled no load v ref (internal) = 4.096v, v dd = 5v v ref (internal) = 2.5v, v dd = 5v v ref (internal) = 2.048v, v dd = 5v v ref (external) = v dd = 3v supply current vs. supply voltage max5823 toc12 supply voltage (v) supply current (ma) 5.1 4.7 3.9 4.3 3.5 3.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 2.7 5.5 v dd = v ddio v dac_ = full scal e all dacs enabled no load v ref (internal) = 4.096v v ref (internal) = 2.5v v ref (internal) = 2.048v v ref = 2.5v (external) power-down mode supply current vs. supply voltage max5823 toc13 supply voltage (v) power-down supply current (a) 5.1 4.7 4.3 3.9 3.5 3.1 0.4 0.8 1.2 1.6 2.0 0 2.7 5.5 t a = -40c t a = +25c t a = +85c t a = +125c v dd = v ddio v ref = 2.5v (external) power-down mode with hi-z no load i vdd vs. code max5823 toc14 code (lsb) supply current (ma) 3584 3072 2560 2048 1536 1024 0.4 0.8 1.2 1.6 2.0 0 512 0 4096 v dd = 5v, v ref = 4.096v v dd = v ref = 3v v dd = 5v, v ref = 2.048v v dd = 5v, v ref = 2.5v v dd = v ref = 5v no load i ref (external) vs. code max5823 toc15 code (lsb) reference current ( a) 3584 3072 2560 2048 1536 1024 10 20 30 40 50 60 0 512 0 4096 v dd = v ref no load v ref = 5v v ref = 3v max5823 toc16 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3.75s 1/4 scale to 3/4 scal e max5823 toc17 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3/4 scale to 1/4 scal e 4.3s ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 10 ultra-small, quad channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 typical operating characteristics (continued) (MAX5825, 12-bit performance, t a = +25c, unless otherwise noted.) max5823 toc18 trigger pulse 5v/div 1 lsb change (midcode transition 0x800 to 0x7ff) glitch impulse = 2nv*s zoomed v out 1.25mv/div 2s/div major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5823 toc19 2s/div trigger pulse 5v/div zoomed v out 1.25mv/div 1 lsb change (midcode transition 0x7ff to 0x800) glitch impulse = 2nv*s v out vs. time transient exiting power-down max5823 toc20 dac output 500mv/div 10s / div v scl 5v/div 0v 36th edge 0v v dd = 5v, v ref = 2.5v external power-on reset to 0v max5823 toc21 v out 2v/div 20s / div v dd 2v/div 0v 0v v dd = v ref = 5v 10ki load to v dd channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, no load) max5823 toc22 4s / div v dac0 5v/div no load v dac4 0.585 lsb/div no load transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.3nv*s channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v, t a = +25n c, no load) max5823 toc23 4s / div v dac0 5v/div no load v dac4 0.585 lsb/div no load transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 2.6nv*s maxim integrated products 11 ultra-small, quad channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 typical operating characteristics (continued) (MAX5825, 12-bit performance, t a = +25c, unless otherwise noted.) channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, r l = 2ki , c l = 200pf) max5823 toc24 4s / div v dac0 5v/div loaded v dac4 0.585 lsb/div no load transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 4.07nv*s max5813 toc25 v dac0 5v/div loaded v dac4 0.585 lsb/div no load 4s/div channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, r l = 2ki , c l = 200pf) transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.3nv*s max5823 toc26 20ns/div digital feedthrough (v dd = v ref = 5v, r l = 10ki ) v dac_ 2mv/div digital crosstalk = 0.2nv*s static dac midscale output load regulation max5823 toc27 i out (ma) dv out (mv) 50 40 20 30 -10 0 10 -20 -8 -6 -4 -2 0 2 4 6 8 10 -10 -30 60 v dd = v ref v dd = 5v v dd = 3v output current limiting max5823 toc28 i out (ma) d v out (mv) 60 50 30 40 -10 0 10 20 -20 -400 -300 -200 -100 0 100 200 300 400 500 -500 -30 70 v dd = v ref v dd = 5v v dd = 3v headroom at rails vs. output current max5823 toc29 i out (ma) v out (v) 9 8 6 7 2 3 4 5 1 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 0 01 0 v dd = 5v, sourcing v dd = 3v, sourcing v dd = 3v and 5v sinking v dd = v ref dac = full scale noise-voltage density vs. frequency (dac at midscale) max5823 toc30 frequency (hz) noise-voltage density (nv/ hz) 10k 1k 50 100 150 200 250 300 350 0 100 100k v dd = 5v, v ref = 2.5v internal v dd = 5v, v ref = 2.048v internal v dd = 5v, v ref = 3.5v (external) v dd = 5v, v ref = 4.096v internal maxim integrated products 12 typical operating characteristics (continued) (MAX5825, 12-bit performance, t a = +25c, unless otherwise noted.) 0.1hz to 10hz output noise, external reference (v dd = 5v, v ref = 4.5v) max5823 toc31 2v/div midscale unloaded v p-p = 12v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.048v) max5823 toc32 2v/div midscale unloaded v p-p = 13v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.5v) max5823 toc33 2v/div midscale unloaded v p-p = 15v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 4.096v) max5823 toc34 2v/div midscale unloaded v p-p = 16v 4s /div v ref drift vs. temperature max5823 toc35 temperature drift (ppm / c) percent of population (%) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 5 10 15 20 25 30 0 0 v dd = 2.7v v ref = 2.5v (internal) box method reference load regulation max5823 toc36 reference output current (a) dv ref (mv) 450 400 350 300 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 -1.0 0 500 v ref = 2.048v, 2.5v, and 4.096v v dd = 5v internal reference supply current vs. input logic voltage (v dd = 3v) max5823 toc37 input logic voltage (v) supply current (a) 4 3 2 1 200 400 600 800 1000 1200 1400 1600 1800 2000 0 05 v ddio = 5v v ddio = 3v v ddio = 1.8v sda , scl, clr, and ldac swept from 0v to v ddio and v ddio to 0v ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 13 ultra-small, quad channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 typical operating characteristics (continued) (MAX5825, 12-bit performance, t a = +25c, unless otherwise noted.) watchdog timer period histogram max5823 toc38 frequency (hz) percent of population (%) 4 6 8 10 12 14 0 2 990 992 994 996 998 1000 1002 1004 1006 1008 1010 1012 v dd = 3v watchdog timer frequency vs. supply voltage max5823 toc39 supply voltage (v) watchdog timer frequency (hz) 5.1 4.7 4.3 3.9 3.5 3.1 980 985 990 995 1000 1005 975 2.7 5.5 watchdog timer frequency vs. temperature max5823 toc40 temperature (c) watchdog timer frequency (hz) 110 95 65 80 -10 5 20 35 50 -25 920 930 940 950 960 970 980 990 1000 1010 910 -40 125 v dd = 3v maxim integrated products 14 pin description pin configurations pin name function tssop wlp 1 d3 ref reference voltage input/output 2 d2 dac0 dac channel 0 voltage output 3 d1 dac1 dac channel 1 voltage output 4 c1 dac2 dac channel 2 voltage output 5 c2 dac3 dac channel 3 voltage output 6 b2 dac4 dac channel 4 voltage output 7 b1 dac5 dac channel 5 voltage output 8 a1 dac6 dac channel 6 voltage output 9 a2 dac7 dac channel 7 voltage output 10 b3 v dd analog supply voltage 11 a3 v ddio digital supply voltage 12 a4 addr1 i 2 c address selection input bit 1 13 a5 addr0 i 2 c address selection input bit 0 14 b5 scl i 2 c serial data clock input 15 b4 sda i 2 c serial data bus input/output 16 c5 irq active-low open drain interrupt output. irq low indicates watchdog timeout. 17 c4 clr active-low asynchronous dac clear input 18 d5 ldac active-low asynchronous dac load input 19 d4 gnd ground 20 c3 m/ z dac output reset selection. connect m/ z to gnd for zero-scale and connect m/ z to v dd for midscale. 20 19 18 17 16 15 14 1 2 3 4 5 6 7 m/z gnd ldac clr dac2 dac1 dac0 ref top view max5823 max5824 MAX5825 irq sda scl dac5 dac4 dac3 13 12 11 8 9 10 addr0 addr1 v ddio v dd dac7 dac6 tssop + top view clr dac2 sda dac5 addr1 dac6 max5823/max5824/MAX5825 + 1 2 34 a dac3 m/z dac4 v dd dac7 v ddio b c wlp d irq scl addr0 5 gnd dac1 dac0 ref ldac ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 15 detailed description the max5823/max5824/MAX5825 are 8-channel, low- power, 8-/10-/12-bit buffered voltage-output dacs. the 2.7v to 5.5v wide supply voltage range and low-power consumption accommodates most low-power and low- voltage applications. the devices present a 100k i load to the external reference. the internal output buffers allow rail-to-rail operation. an internal voltage reference is available with software selectable options of 2.048v, 2.500v, or 4.096v. the devices feature a fast 400khz i 2 c- compatible interface. the max5823/max5824/MAX5825 include a serial-in/parallel-out shift register, internal code and dac registers, a power-on-reset (por) circuit to initialize the dac outputs to zero scale (m/ z = 0) or midscale (m/ z = 1), and control logic. clr is available to asynchronously clear the dac out - puts to a user-programmable default value, independent of the serial interface. ldac is available to simultane - ously update selected dacs on one or more devices. the max5823/max5824/MAX5825 also feature user- configurable interface watchdog, with status indicated by the irq output. dac outputs (out_) the max5823/max5824/MAX5825 include internal buf - fers on all dac outputs, which provide improved load regulation for the dac outputs. the output buffers slew at 1v/ f s (typ) and drive as low as 2k i in parallel with 500pf. the analog supply voltage (v dd ) determines the maximum output voltage range of the devices since it powers the output buffers. under no-load conditions, the output buffers drive from gnd to v dd , subject to offset and gain errors. with a 2k load to gnd, the output buf - fers drive from gnd to within 200mv of v dd . with a 2k load to v dd , the output buffers drive to within 200mv of gnd and v dd . the dac ideal output voltage is defined by: out ref n d vv 2 = where d = code loaded into the dac register, v ref = reference voltage, n = resolution. internal register structure the user interface is separated from the dac logic to minimize digital feedthrough. within the serial interface is an input shift register, the contents of which can be routed to control registers, individual, or multiple dacs as determined by the user command. within each dac channel there is a code register followed by a dac latch register (see the detailed functional diagram ). the contents of the code register hold pending dac output settings which can later be loaded into the dac registers. the code register can be updated using both code and code_load user com - mands. the contents of the dac register hold the current dac output settings. the dac register can be updated directly from the serial interface using the code_load commands or can upload the current contents of the code register using load commands or the ldac logic input. the contents of both code and dac registers are main - tained during power-down states, so that when the dacs are powered on, they return to their previously stored output settings. any code or load commands issued during power-down states continue to update the register contents. once the device is powered up, each dac channel can be independently programmed with a desired return value using the return command. this becomes the value the code and dac registers will use in the event of any watchdog, clear or gate activity, as selected by the default command. hardware clr operations and sw_clear commands return the contents of all code and dac registers to their user-selected defaults. sw_reset commands will reset code and dac register contents to their m/ z selected initial codes. a sw_gate state can be used to momen - tarily hold selected dac outputs in their default posi - tions. the contents of code and dac registers can be manipulated by watchdog timer activity, enabling a variety of safety features. internal reference the max5823/max5824/MAX5825 include an internal precision voltage reference that is software selectable to be 2.048v, 2.500v, or 4.096v. when an internal reference is selected, that voltage is available on the ref output for other external circuitry (see the typical operating circuits ) and can drive loads down to 25k i . ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 16 external reference the external reference input has a typical input impedance of 100k i and accepts an input voltage from +1.24v to v dd . apply an external voltage between ref and gnd to use an external reference. the max5823/max5824/MAX5825 power up and reset to external reference mode. visit www.maxim-ic.com/products/references for a list of available external voltage-reference devices. m/ z input the max5823/max5824/MAX5825 feature a pin select - able dac reset state using the m/ z input. upon a power- on reset, all code and dac data registers are reset to zero scale (m/ z = gnd) or midscale (m/ z = v dd ). m/ z is referenced to v dd (not v ddio ). in addition, m/ z must be valid at the time the device is powered upconnect m/ z directly to v dd or gnd. load dac ( ldac ) input the max5823/max5824/MAX5825 feature an active-low asynchronous ldac logic input that allows dac outputs to update simultaneously. connect ldac to v ddio or keep ldac high during normal operation when the device is controlled only through the serial interface. drive ldac low to update the dac outputs with data from the code registers. holding ldac low causes the dac registers to become transparent and code data is passed through to the dac registers immediately updat - ing the dac outputs. a software config command can be used to configure the ldac operation of each dac independently. clear ( clr ) input the max5823/max5824/MAX5825 feature an asynchro - nous active-low clr logic input that simultaneously sets all selected dac outputs to their programmable default states. driving clr low clears the contents of both the code and dac registers and also ignores any on-going i 2 c command which modifies registers associ - ated with a dac configured to accept clear operations. to allow a new i 2 c command, drive clr high, satisfy - ing the t clrsta timing requirement. a software config command can be used to configure the clear operation of each dac independently. watchdog feature the max5823/max5824/MAX5825 feature an interface watchdog timer with programmable timeout duration. this monitors the i/o interface for activity and integrity. if the watchdog is enabled, the host processor must write a valid command to the device within the timeout period to prevent a timeout. if the watchdog is allowed to timeout, selected dac outputs are returned to the programmable default state, protecting the system against control faults. by default, all watchdog features are disabled; users wishing to activate any watchdog feature must configure the device accordingly. individual dac channels can be configured using the config command to accept the watchdog alarm and to gate, clear, or hold their out - puts in response to an alarm. a watchdog refresh event and watchdog behavior upon timeout is defined by a programmable safety level using the wdog_config command. irq output the max5823/max5824/MAX5825 feature an active-low open-drain interrupt output indicating to the host when a watchdog timeout has occurred. figure 2. i 2 c start, repeated start, and stop conditions scl sda ss rp valid start, repeated start, and stop pulses ps p sp p s invalid start/s top pulse pairings-all will be recognized as starts ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 17 interface power supply (v ddio ) the max5823/max5824/MAX5825 feature a separate supply input (v ddio ) for the digital interface (1.8v to 5.5v). connect v ddio to the i/o supply of the host pro - cessor. i 2 c serial interface the max5823/max5824/MAX5825 feature an i 2 c-/ smbus k -compatible, 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl enable communication between the max5823/ max5824/MAX5825 and the master at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the max5823/max5824/MAX5825 by transmitting the proper slave address followed by the command byte and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted to the max5823/ max5824/MAX5825 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the max5823/max5824/MAX5825 must transmit the proper slave address followed by a series of nine scl pulses for each byte of data requested. the max5823/ max5824/MAX5825 transmit data on sda in sync with the master-generated scl pulses. the master acknowl - edges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowledge, and a stop condition. sda operates as both an input and an open-drain output. a pullup resistor, typically 4.7k i is required on sda. scl oper - ates only as an input. a pullup resistor, typically 4.7k i , is required on scl if there are multiple masters on the bus, or if the single master has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the max5823/ max5824/MAX5825 from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. the max5823/max5824/MAX5825 can accom - modate bus voltages higher than v ddio up to a limit of 5.5v; bus voltages lower than v ddio are not recom - mended and may result in significantly increased inter - face currents. the max5823/max5824/MAX5825 digital inputs are double buffered. depending on the command issued through the serial interface, the code register(s) can be loaded without affecting the dac register(s) using the write command. to update the dac registers, either drive the ldac input low to simultaneously update all dac outputs, or use the software load command. i 2 c start and stop conditions sda and scl idle high when the bus is not in use. a mas - ter initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high ( figure 2 ). a start condition from the master signals the beginning of a transmission to the max5823/max5824/MAX5825. the master termi - nates transmission and frees the bus, by issuing a stop condition. the bus remains active if a repeated start condition is generated instead of a stop condition. i 2 c early stop and repeated start conditions the max5823/max5824/MAX5825 recognize a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. transmissions ending in an early stop condition will not impact the internal device settings. if the stop occurs during a readback byte, the transmission is terminated and a later read mode request will begin transfer of the requested register data from the beginning (this applies to combined format i 2 c read mode transfers only), interface verification mode transfers will be corrupted. see figure 2 . table 1. i 2 c slave address lsbs smbus is a trademark of intel corp. addr1 addr0 a3 a2 a1 a0 v ddio v ddio 1 1 1 1 v ddio n.c. 1 1 1 0 v ddio gnd 1 1 0 0 n.c. v dd 1 0 1 1 n.c. n.c. 1 0 1 0 n.c. gnd 1 0 0 0 gnd v ddio 0 0 1 1 gnd n.c. 0 0 1 0 gnd gnd 0 0 0 0 ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 18 figure 3. i 2 c acknowledge figure 4. i 2 c single register write sequence i 2 c slave address the slave address is defined as the seven most sig - nificant bits (msbs) followed by the r/ w bit. see figure 4 . the three most significant bits are 001 with the 4 lsbs determined by addr1 and addr0 as shown in table 1 . setting the r/ w bit to 1 configures the max5823/ max5824/MAX5825 for read mode. setting the r/ w bit to 0 configures the max5823/max5824/MAX5825 for write mode. the slave address is the first byte of informa - tion sent to the max5823/max5824/MAX5825 after the start condition. the max5823/max5824/MAX5825 has the ability to detect an unconnected (n.c.) state on the addr_ inputs for additional address flexibility; if disconnecting the addr_ inputs, be certain to minimize all loading on the addr_ inputs (i.e. provide a landing for addr_, but do not allow any board traces). i 2 c broadcast address a broadcast address is provided for the purpose of updating or configuring all max5823/max5824/MAX5825 devices on a given i 2 c bus. all max5823/max5824/ MAX5825 devices acknowledge and respond to the broadcast device address 00101000, regardless of the state of the address pins. the broadcast mode is intend - ed for use in write mode only (as indicated by r/ w = 0 in the address given). i 2 c acknowledge in write mode, the acknowledge bit (ack) is a clocked 9th bit that the max5823/max5824/MAX5825 use to hand - shake receipt of each byte of data as shown in figure 3 . the max5823/max5824/MAX5825 pull down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccess - ful data transfer, the bus master will retry communication. in read mode, the master pulls down sda during the 9th clock cycle to acknowledge receipt of data from the max5823/max5824/MAX5825. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not-acknowledge is sent when the master reads the final byte of data from the max5823/max5824/ MAX5825, followed by a stop condition. i 2 c command byte and data bytes a command byte follows the slave address. a command byte is typically followed by two data bytes unless it is the last byte in the transmission. if data bytes follow the command byte, the command byte indicates the address of the register that is to receive the following two data bytes. the data bytes are stored in a temporary register and then transferred to the appropriate register during the ack periods between bytes. this avoids any glitch - ing or digital feedthrough to the dacs while the interface is active. 1 scl start condition sda 29 clock pulse for acknowledgment acknowledge not acknowledge scl a 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 start sda write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) 21 22 23 stop 7 6 5 4 3 2 1 a 0 ack. generated by max5823/max5824/ MAX5825 command executed a3 a2 a1 a0 w 1 0 0 a ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 19 figure 5. multiple register write sequence (standard i 2 c protocol) figure 6. standard i 2 c register read sequence i 2 c write operations a master device communicates with the max5823/ max5824/MAX5825 by transmitting the proper slave address followed by command and data words. each transmit sequence is framed by a start or repeated start condition and a stop condition as described above. each word is 8 bits long and is always followed by an acknowledge clock (ack) pulse as shown in the figure 4 and figure 5 . the first byte contains the address of the max5823/max5824/MAX5825 with r/ w = 0 to indicate a write. the second byte contains the register (or command) to be written and the third and fourth bytes contain the data to be written. by repeating the register address plus data pairs (byte #2 through byte #4 in figure 4 and figure 5 ), the user can perform multiple register writes using a single i 2 c command sequence. there is no limit as to how many registers the user can write with a single command. the max5823/max5824/ MAX5825 support this capability for all user-accessible write mode commands. combined format i 2 c readback operations each readback sequence is framed by a start or repeated start condition and a stop condition. each word is 8 bits long and is followed by an acknowledge clock pulse as shown in figure 6 . the first byte contains the address of the max5823/max5824/MAX5825 with r/ w = 0 to indicate a write. the second byte contains the register that is to be read back. there is a repeated start condition, followed by the device address with r/ w = 1 to indicate a read and an acknowledge clock. the master has control of the scl line but the max5823/ max5824/MAX5825 take over the sda line. the final two bytes in the frame contain the register data readback followed by a stop condition. if additional bytes beyond those required to readback the requested data are pro - vided, the max5823/max5824/MAX5825 will continue to readback ones. readback of the wdog command (b[23:20] = 0001) is directly supported, confirming the current watchdog timeout selection, mask status, and safety level. scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 start sda write address byte #1: i 2 c slave address write command1 byte #2: command1 byte (b[23:16]) write data1 byte #3: data1 high byte (b[15:8]) 21 0 0 1 a3 a2 a1 a0 22 23 stop 7 6 5 4 3 2 1a 0 write data1 byte #4: data1 low byte (b[7:0]) 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 21 22 23 7 6 5 4 3 2 1a 0 additional command and data pairs (3 byte blocks) command1 executed commandn executed byte #5: commandn byte (b[23:16]) byte #6: datan high byt e (b[15:8]) byte #7: datan low byt e (b[7:0]) ack. generated by max5823/max5824/ MAX5825 a read data byte #4: data1 high byte (b[15:8]) read data byte #5: data1 low byte (b[15:8]) repeated start read address byte #3: i 2 c slave address write address byte #1: i 2 c slave address write command1 byte #2: command1 byte ack. generated by max5823/max5824/ MAX5825 ack. generated by i 2 c master a a start stop scl sda 00 1a 3a 2a 1a 0w aa 0 0n 0 01 a3 a2 a1 a0 ra d ddd dd dd dddddddd ~a a nn nnn ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 20 readback of individual return registers is supported for return commands (b[23:20] = 0111). for this com - mand, which supports a dac address, the requested channel return register content will be returned, along with the selected dac address. if all dacs are selected, readback will begin with return0 content and will progress through the remaining dac channels. the return_all (b[23:16] = 11000011) command behaves identically to the return command with all dacs selected. readback of individual code registers is supported for the code commands (b[23:20] = 1000). for this com - mand, which supports a dac address, the requested channel code register content will be returned, along with the selected dac address. if all dacs are select - ed, readback will begin with code0 content and will progress through the remaining dac channels. the code_all (b[23:16] = 11000000) command behaves identically to the code command with all dacs selected. readback of individual dac registers is supported for all load commands (b[23:20] = 1001, 1010, 1011). for these commands, which support a dac address, the requested dac register content will be returned, along with the selected dac address. if all dacs are selected, readback will begin with dac0 content and will progress through the remaining dac channels. the load_all and code_all_load_all commands (b[23:16] = 11000001 and 11000010, respectively) behave identi - cally to the load command with all dacs selected. modified readback of the power register is supported for the power command (b[23:20] = 0100). the power status of each dac is reported in locations b[7:0], with a 1 indicating the dac is powered down and a zero indi - cating the dac is operational (see table 2 ). readback of all other registers is not directly supported. all requests to read unsupported registers reads back the devices current watchdog timer status (wd:0 = nor - mal, 1 = timed out), reference setting (ref[2:0]), and clr condition, along with the device revision (b[10:8] = 001) and part id (b[7:0]) in the format as shown in table 2 . interface verification i 2 c readback operations while the max5823/max5824/MAX5825 support stan - dard i 2 c readback of selected registers, it is also capable of functioning in an interface verification mode. this mode is accessed any time a readback operation follows an executed write mode command. in this mode, the last executed three-byte command is read back in its entirety. this behavior allows verification of the interface. sample command sequences are shown in figure 7 . the first command transfer is given in write mode with r/ w = 0 and must be run to completion to qualify for interface verification readback. there is now a stop/ table 2. standard i 2 c user readback data command byte (request) readback data high byte readback data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 x x x x wdog timeout selection[11:4] timeout selection[3:0] wdm wl[1:0] 0 0 1 0 0 x x x x 0 0 0 0 0 0 0 0 pw7 pw6 pw5 pw4 pw3 pw2 pw1 pw0 0 1 1 1 dac selection returnn[11:4] returnn[3:0] addressn[3:0] 1 0 0 0 dac selection coden[11:4] coden[3:0] addressn[3:0] 1 0 0 1 dac selection dacn[11:4] dacn[3:0] addressn[3:0] 1 0 1 0 dac selection dacn[11:4] dacn[3:0] addressn[3:0] 1 0 1 1 dac selection dacn[11:4] dacn[3:0] addressn[3:0] 1 1 0 0 0 0 0 0 code0[11:4] code0[3:0] address0[3:0] 1 1 0 0 0 0 0 1 dac0[11:4] dac0[3:0] address0[3:0] 1 1 0 0 0 0 1 0 dac0[11:4] dac0[3:0] address0[3:0] 1 1 0 0 0 0 1 1 return0[11:4] return0[03:0] address0[3:0] all other commands (MAX5825) wd ref[2:0] clr rev_id [2:0] (001) 1 0 0 0 0 0 0 0 all other commands (max5824) 1 0 1 0 0 0 0 0 all other commands (max5823) 1 0 0 1 0 0 0 0 ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 21 table 3. format dac data bit positions figure 7. interface verification i 2 c register read sequences part b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 max5823 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x max5824 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x MAX5825 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9 a 8 sda 0 0 1 a3 a2 a1 a0 22 23 7 6 5 4 3 2 1 a 0 r ~a pointer updated (qualifies for combined read back) command executed (qualifies for interface read back) scl sda command executed (qualifies for interface read back) pointer updated (qualifies for combined read back) 21 a w2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 1a 3a 2a 1a 02 2 23 76 54 32 1a 0 21 start stop write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) start stop write address byte #1: i 2 c slave address read command byte #2: command byte (b[23:16]) read data byte #3: data high byte (b[15:8]) read data byte #4: data low byte (b[7:0]) start repeated start write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byte (b[15:8]) write data byte #4: data low byte (b[7:0]) stop write address byte #1: i 2 c slave address read command byte #2: command byte (b[23:16]) read data byte #3: data high byte (b[15:8]) read data byte #4: data low byte (b[7:0]) ack. generated by max5823/max5824/MAX5825 ack. generated by i 2 c master a2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 1a 3a 2a 1a 02 2 23 76 54 32 10 21 a r2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 1a 3a 2a 1a 02 2 23 76 54 32 1~ a 0 21 a a ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 22 start pair or repeated start condition required, fol - lowed by the readback transfer with r/ w = 1 to indicate a read and an acknowledge clock from the max5823/ max5824/MAX5825. the master still has control of the scl line but the max5823/max5824/MAX5825 take over the sda line. the final three bytes in the frame contain the command and register data written in the first transfer presented for readback, followed by a stop condition. if additional bytes beyond those required to readback the requested data are provided, the max5823/max5824/ MAX5825 will continue to readback ones. it is not necessary for the write and read mode transfers to occur immediately in sequence. i 2 c transfers involv - ing other devices do not impact the max5823/max5824/ MAX5825 readback mode. toggling between readback modes is based on the length of the preceding write mode transfer. combined format i 2 c readback operation is resumed if a write command greater than two bytes but less than four bytes is supplied. for commands writ - ten using multiple register write sequences, only the last command executed is read back. for each command written, the readback sequence can only be completed one time; partial and/or multiple attempts to readback executed in succession will not yield usable data. i 2 c compatibility the max5823/max5824/MAX5825 are fully compatible with existing i 2 c systems. scl and sda are high-imped - ance inputs; sda has an open drain which pulls the data line low to transmit data or ack pulses. figure 8 shows a typical i 2 c application. i 2 c user-command register map this section lists the user-accessible commands and registers for the max5823/max5824/MAX5825. table 4 provides detailed information about the command registers. figure 8. typical i 2 c application circuit c addr0 addr1 scl sda scl sda addr0 addr1 +5v scl sda max5823 max5824 MAX5825 max5823 max5824 MAX5825 ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 23 table 4. i 2 c commands summary command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description configuration and software commands wdog 0 0 0 1 x x x` x timeout selection[11:4] timeout selection[3:0] wd_mask safety level 00: low 01: med 10: high 11: max x updates watchdog settings and safety levels ref 0 0 1 0 0 ref pow- er 0 = dac 1 = on ref mode 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.1v x x x x x x x x x x x x x x x sets the reference operating mode. ref power (b18): 0 = internal reference is only powered if at least one dac is powered. 1 = internal reference is always powered. sw_gate_clr 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 removes any existing gate condition sw_gate_set 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 initiates a gate condition wd_refresh 0 0 1 1 0 0 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 refreshes the watchdog timer wd_reset 0 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 resets the watchdog timeout alarm status and refreshes the watchdog timer sw_clear 0 0 1 1 0 1 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 executes a software clear (all code and dac registers cleared to their default values) sw_reset 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 executes a software reset (all code, dac, and control registers returned to their power-on reset values) power 0 1 0 0 0 0 0 0 dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 power mode 00 = normal 01 = pd 1k w 10 = pd 100k w 11 = pd hi-z x x x x x x sets the power mode of the selected dacs (dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) config 0 1 0 1 0 0 0 0 dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 wdog config- uration 00: dis 01: gate 10: clr 11: hold gate_enb ldac_enb clear_enb x x x configures selected dac watchdog, gate, load, and clear operations. dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 24 table 4. i 2 c commands summary (continued) command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description default 0 1 1 0 0 0 0 0 dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 default values: 000: m/ z 001: zero 010: mid 011: full 100: return 101+: no effect sets the default code settings for selected dacs. note: dacs in return mode programmable return codes. (dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) dac commands returnn 0 1 1 1 dac selection return register data[11:4] return register data[3:0] x x x x writes data to the selected return register(s) coden 1 0 0 0 dac selection code register data[11:4] code register data[3:0] x x x x writes data to the selected code register(s) loadn 1 0 0 1 dac selection x x x x x x x x x x x x x x x x transfers data from the selected code registers to the selected dac register(s) coden_ load_all 1 0 1 0 dac selection code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the selected code register(s) while updating all dac registers coden_loadn 1 0 1 1 dac selection code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the selected code register(s) while updating selected dac register(s) code_all 1 1 0 0 0 0 0 0 code register data[11:4] code register data[3:0] x x x x writes data to all code registers load_all 1 1 0 0 0 0 0 1 x x x x x x x x x x x x x x x x updates all dac latches with current code register data code_all load_all 1 1 0 0 0 0 1 0 code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the all code registers while updating all dac registers return_all 1 1 0 0 0 0 1 1 return register data[11:4] returnregister data[3:0] x x x x writes data to all return registers no operation commands no operation 1 1 0 0 0 1 x x x x x x x x x x x x x x x x x x these commands will have no effect on the device, but will refresh the watchdog timer if safety level is set to low 1 1 0 0 1 0 x x x x x x x x x x x x x x x x x x 1 1 0 0 1 1 x x x x x x x x x x x x x x x x x x reserved commands: any commands not specifically listed above are reserved for maxim internal use only. ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 25 table 5. dac selection returnn command the return command (b[23:20] = 0111) sets the pro - grammable default return value. this value is used for all future watchdog, clear, and gate operations when ret is selected for the dac using the default com - mand. issuing this command with dac_address set to all dacs will program the value for all return registers and is equivalent to return_all. note: this command is inaccessible when a watchdog timeout has occurred if the watchdog timer is configured for safety level = high or max. coden command the coden command (b[23:20] = 1000) updates the code register contents for the selected dac(s). changes to the code register content based on this command will not affect dac outputs directly unless the ldac input is in a low state or the dac latch has been configured as transparent using the config command. issuing this command with dac_address set to all dacs will program the value for all code registers and is equivalent to code_all. loadn command the loadn command (b[23:20] = 1001) updates the dac register content for the selected dac(s) by upload - ing the current contents of the selected code register(s) into the selected dac register(s). channels for which code content has not been modified since the last load or ldac operation will not be updated to reduce digital crosstalk. issuing this command with dac_address set to all dacs will update the contents of all dac registers and is equivalent to load_all. coden_loadn command the coden_loadn command (b[23:20] = 1011) updates the code register contents for the selected dac(s) as well as the dac register content of the select - ed dac(s). channels for which code content has not been modified since the last load or ldac operation will not be updated to reduce digital crosstalk. issuing this command with dac_address set to all dacs is equivalent to the code_all_load_all command. coden_load_all command the coden_load_all command (b[23:20] = 1010) updates the code register contents for the selected dac(s) as well as the dac register content of all dacs. channels for which code content has not been modified since the last load or ldac operation will not be updat - ed to reduce digital crosstalk. issuing this command with dac_address set to all dacs will update the code and dac register contents of all dacs and is equivalent to code_all_load_all. note this command by defini - tion will modify at least one code register; to avoid this use the load command with dac_address set to all dacs or the load_all command. code_all command the code_all command (b[23:16] = 1100_0000) updates the code register contents for all dacs. load_all command the load_all command (b[23:16] = 1100_0001) updates the dac register content for all dacs by upload - ing the current contents of the code registers to the dac registers. code_all_load_all command the code_all_load_all command (b[23:16] = 1100_0010) updates the code register contents for all dacs as well as the dac register content of all dacs. return_all command the return_all command (b[23:16] = 1100_0011) updates the return register contents for all dacs. no_op commands command all unused commands in the space (b[23:16] = 1100_ x1xx or 1100_1xxx) have no effect on the device, but will refresh the watchdog timer (if active) with the safety level set to low. b19 b18 b17 b16 dac selected 0 0 0 0 dac0 0 0 0 1 dac1 0 0 1 0 dac2 0 0 1 1 dac3 0 1 0 0 dac4 0 1 0 1 dac5 0 1 1 0 dac6 0 1 1 1 dac7 1 x x x all dacs ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 26 wdog command the wdog command (b[23:20] = 0001) updates the watchdog timeout settings and safety levels for the device. timeout thresholds are selected in 1ms incre - ments (1ms to 4095ms are available). the wd_mask bit can be used to mask the irq operation in response to the watchdog status, if wd_mask = 1, watchdog alarms will not assert irq . the watchdog alarm status (wd bit) can be polled using the available i 2 c status readback com - mands regardless of wd_mask settings. a write to this register will not reset a previously triggered watchdog alarm (use the wd_reset command for this purpose). the watchdog timer refresh and timeout behavior is defined by the programmable safety level below. available safety levels (wl[1:0]): low (00): watchdog timer will refresh with the execution of any valid user mode command or no-op. any success - ful slave address acknowledge qualifies to restart the watchdog timer (run to the ninth scl edge), regardless of the command which follows. issuing hardware clr or ldac falling edge will also refresh the watchdog timer. a triggered watchdog alarm does not prevent writes to any register. ldac and clr inputs still function after a watchdog timeout event. medium (01): a wd_refresh command must be execut - ed in order to refresh the watchdog timer. other commands as well as ldac or clr activity do not refresh the watch - dog timer. a triggered watchdog alarm does not prevent writes to any register. ldac and clr inputs still function after a watchdog timeout event. high (10): a wd_refresh command must be executed to refresh the watchdog timer. other commands as well as ldac or clr activity do not refresh the watchdog timer. a triggered watchdog alarm prevents execution of all power, ref, config, default, and return commands. ldac and clr inputs still function after a watchdog timeout event. max (11): a wd_refresh command must be executed to refresh the watchdog timer. other commands, as well as ldac or clr activity, do not refresh the watchdog timer. a triggered watchdog alarm prevents execution of all power, ref, config, default, and return com - mands. ldac and clr are gated and do not function after a watchdog timeout event. table 7. watchdog safety level protection * unless otherwise affected by watchdog hold or clr configurations as set by the config command. see the config register definition for details. table 6. wdog command format watchdog safety level any command refreshes wdt clr / ldac refreshes wdt swreset plus wdrfrs refreshes wdt all registers accessible after wdt timeout* clr / ldac affect dac registers after wdt timeout* 00 (low) x x x x x 01 (med) x x x 10 (high) x x 11 (max) x b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 x x x x c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 wdm wl1 wl0 x wdog command dont care timeout selection[11:4] timeout selection[3:0] wd_mask wdog safety level: 00: low 01: med 10: high 11: max dont care default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x command byte data high byte data low byte ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 27 table 8. ref command format ref command the ref command (b[23:20] = 0010) updates the global reference setting used for all dac channels. if an internal reference mode is selected, bit rf2 (b18) defines the reference power mode. if rf2 is set to zero (default), the reference will be powered down any time all dac chan - nels are powered down (i.e. the device is in standby mode). if rf2 is set to one, the reference will remain pow - ered even if all dac channels are powered down, allow - ing continued operation of external circuitry (note in this mode the low current shutdown state is not available). this command is inaccessible when a watchdog timeout has occurred and the watchdog timer is configured with a safety level of high or max. sw_gate_clr command the sw_gate_clr command (b[23:0] = 0011_0000_ 1001_0110_0011_0000) will remove any existing gate condition initiated by a previous sw_gate_set comand. sw_gate_set command the sw_gate_set command (b[23:0] = 0011_0001_ 1001_0110_0011_0000) will initiate a gate condition. any dacs configured with gtb = 0 (see the config command section) will have their outputs held at the selected default value until the gate condition is later removed by a subsequent sw_gate_clr command. while in gate mode, the code and dac registers con - tinue to function normally and are not reset (unless reset by a watchdog timeout). wd_refresh command the wd_refresh command (b[23:0] = 0011_0010_ 1001_0110_0011_0000) will refresh the watchdog timer. this is the only command which will refresh the watch - dog timer if the device is configured with a safety level of medium, high, or max. use this command to prevent the watchdog timer from timing out. wd_reset command a wd_reset command (b[23:0] = 0011_0011_ 1001_0110_0011_0000) will reset the watchdog interrupt (timeout) status and refresh the watchdog timer. use this command to reset the irq timeout condition after the watchdog timer has timed out. any dacs impacted by an existing timeout condition will return to normal operation. sw_clear command a software clear command (b[23:0] = 0011_0100_ 001_0110_0011_0000) will clear the contents of the code and dac registers to the default state for all channels configured with clb = 0 (see config command). sw_reset command a software reset command (b[23:0] = 0011_0101_ 1001_0110_0011_0000) will reset all code, dac, and configuration registers to their defaults (including power, default, config, wdog, and ref regis - ters), simulating a power-on reset. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 0 rf2 rf1 rf0 x x x x x x x x x x x x x x x x ref command reserved 0 = dac controlled 1 = always on ref mode: 00: ext 01: 2.5v 10: 2.0v 11: 4.0v dont care dont care default value 0 0 0 x x x x x x x x x x x x x x x x command byte data high byte data low byte ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 28 power command the power command (b[23:20] = 0100) updates the power mode settings of the selected dacs. dacs that are not selected do not update their power settings in response to the command. the new power setting is determined by bits pd[1:0] (b[7:6]) while the affected dac(s) are selected using b[15:8]). if all dacs are pow - ered down and the rf2 bit is not set, the device enters a standby mode (all analog circuitry is disabled). this command is inaccessible when a watchdog timeout has occurred and the watchdog timer is configured with a safety level of high or max. available power modes (pd[1:0]): normal (00): dac channel is active (default), pd 1k (01): power down with 1k termination to gnd, pd 100k (10): power down with 100k termination to gnd, pd hi-z (11): power down with high-impedance output. config command the config command (b[23:16] = 0101) updates the watchdog, gate, load, and clear mode settings of the selected dacs. dacs which are not selected do not update their settings in response to the command. the new mode settings to be written are determined by bits b[7:3] while the affected dac(s) are selected by b[15:8]. this command is inaccessible when a watchdog timeout has occurred and the watchdog timer is configured with a safety level of high or max. watchdog configuration: wdog config settings are written by wc[1:0] (b[7:6]): disable (wc = 00): watchdog timeout does not affect the operation of the selected dac. gate (wc = 01): dac code is gated to default value in response to watchdog timeouts. unless otherwise prohibited by the watchdog safety level, ldac , clr , and write operations to the code and dac registers are accepted but will not be reflected on the dac output until the watchdog timeout status is reset. clr (wc = 10): code and dac register contents are cleared to default value in response to watchdog time - outs. all writes to code and dac registers are ignored and ldac or clr input activity has no effect until the watchdog timeout status is reset, regardless of watchdog safety level. hold (wc = 11): dac code is held at its previously programmed value in response to watchdog time-out. all writes to dac and code registers are ignored and ldac or clr input activity has no effect until the watch - dog timeout status is reset, regardless of watchdog safety level. note: for the watchdog to timeout and have an impact, the function must first be enabled and configured using the wdog command. table 9. power command format b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 0 0 0 7 6 5 4 3 2 1 0 pd1 pd0 x x x x x x power command reserved dac selection power mode: 00 = normal 01 = 1k w 10 = 100k w 11 = hi-z dont care default value : 1 1 1 1 1 1 1 1 0 0 x x x x x x command byte data high byte data low byte ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 29 table 10. config command format gate configuration: the dac gate setting is written by gtb (b5); gate operation is as follows: gtb = 0: enables software gating function (default), dac outputs are gated to their default settings as long as the device remains in gate mode (set by sw_gate_ set and removed by sw_gate_clr). gtb = 1: disable software gating function, dac outputs are not impacted by gate mode. load configuration: the ldac_enb setting is written by ldb (b4); ldac_enb operation is as follows: ldb = 0: dac latch is operational, enabling ldac and load functions (default). ldb = 1: dac latch is transparent, the code register content controls the dac output directly. clear configuration: clear_enb setting is written by clb (b3); clear_enb operation is as follows: clb = 0: clear input and command functions impact the dac (default), clearing code and dac registers to their default value. clb = 1: clear input and command functions have no effect on the dac. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 0 0 0 0 7 6 5 4 3 2 1 0 wc1 wc0 gtb ldb clb x x x config command reserved dac selection wdog config: 00: disable 01: gate 10: clr 11: hold gate_enb ldac_enb clear_enb dont care default value 1 1 1 1 1 1 1 1 0 0 0 0 0 x x x command byte data high byte data low byte ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 30 default command the default command (b[23:20] = 0110) selects the default value for selected dacs. dacs which are not selected do not update their default settings in response to the command. these default values are used for all future watchdog, clear, and gate operations. the new default setting is determined by bits df[2:0] (b[7:5]) while the affected dac(s) are selected using b[15:8]. this command is inaccessible when a watchdog timeout has occurred and the watchdog timer is configured with a safety level of high or max. note the selected default values do not apply to resets initiated by sw_reset commands or supply cycling, both of which return all dacs to the values determined by the m/ z input and reset this register to m/ z mode. available default values (df[2:0]): m/ z (000): dac channel defaults to value as selected by the m/ z input (default). zero (001): dac channel defaults to zero scale. mid (010): dac channel defaults to midscale. full (011): dac channel defaults to full scale. return (100): dac channel defaults to the value pro - grammed by the return command. no effect (101, 110, 111): dac channel default behavior is unchanged. table 11. default command format b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 0 0 0 0 0 7 6 5 4 3 2 1 0 df2 df1 df0 x x x x x default command reserved dac selection default values: 000: m/ z 001: zero 010: mid 011: full 100: return 101+: no effect dont care default value 1 1 1 1 1 1 1 1 0 0 0 x x x x x command byte data high byte data low byte ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 31 applications information power-on reset (por) when power is applied to v dd and v ddio , the dac out - put is set to zero scale. to optimize dac linearity, wait until the supplies have settled and the internal setup and calibration sequence completes (200 f s, typ). power supplies and bypassing considerations bypass v dd and v ddio with high-quality ceramic capac - itors to a low-impedance ground as close as possible to the device. minimize lead lengths to reduce lead induc - tance. connect the gnd to the analog ground plane. layout considerations digital and ac transient signals on gnd can create noise at the output. connect gnd to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the max5823/max5824/MAX5825 gnd. carefully layout the traces between channels to reduce ac cross-coupling. do not use wire-wrapped boards and sockets. use shielding to minimize noise immunity. do not run analog and digital signals parallel to one another, especially clock signals. avoid routing digi - tal lines underneath the max5823/max5824/MAX5825 package. definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl p 1 lsb, the dac guarantees no missing codes and is monotonic. if the magnitude of the dnl r 1 lsb, the dac output may still be monotonic. offset error offset error indicates how well the actual transfer func - tion matches the ideal transfer function at a single point. typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a transition, until the dac output settles to the new output value within the converters specified accuracy. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse a major carry transition occurs at the midscale point where the msb changes from low to high and all other bits change from high to low, or where the msb changes from high to low and all other bits change from low to high. the duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. although all bits change, larger steps may lead to larger glitch energy. the digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 32 detailed functional diagram out0 out1 buffer 0 channel 0 dac control logic dac channel 0 dac channel 1 power-down 1ki 100ki code load clear/ reset gate/ clear / reset code register 0 dac latch 0 8- /1 0- /1 2- bit dac0 addr0 sda scl v ddio addr1 clr ldac i 2 c serial interface control logic ref r in 100ki internal/external reference (user option) max5823 max5824 MAX5825 v dd gnd irq out7 buffer 7 channel 7 dac control logic dac channel 7 power-down 1ki 100ki code load clear/ reset gate/ clear / reset code register 7 dac latch 7 8- /1 0- /1 2- bit dac7 out2 dac channel 2 out3 dac channel 3 out4 dac channel 4 out5 dac channel 5 out6 dac channel 6 watchdog timer m/z por ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 33 typical operating circuits dac c sda scl addr0 clr irq m/z addr1 note: unipolar operating circuit, one channel shown out gnd ldac v ddio v dd ref 100nf 100nf 4.7f r pu = 5ki r pu = 5ki r pu = 5ki max5823 max5824 MAX5825 dac c sda scl addr0 clr irq m/z addr1 out gnd ldac v ddio v dd ref 100nf 100nf 4.7f r pu = 5ki r pu = 5ki r pu = 5ki r1 r2 r1 = r2 max5823 max5824 MAX5825 note: bipolar operating circuit, one channel shown ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim integrated products 34 ordering information note: all devices are specified over the -40c to +125c temperature range. +denotes a lead(pb)Cfree/rohs-compliant package. *future productcontact factory for availability. t = tape and reel. chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package resolution (bit) max5823 aup+* -40c to +125c 20 tssop 8 max5824 aup+* -40c to +125c 20 tssop 10 MAX5825 aaup+ -40c to +125c 20 tssop 12 MAX5825awp+t* -40c to +125c 20 wlp 12 MAX5825baup+* -40c to +125c 20 tssop 12 package type package code outline no. land pattern no. 20 tssop u20+1 21-0066 90-0116 20 wlp w202c2+1 21-0059 refer to application note 1891 ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 35 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/12 initial release ultra-small, octal channel, 8-/10-/12-bit buffered output dacs with internal reference and i 2 c interface max5823/max5824/MAX5825 |
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