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br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 1/14 1k, 2k, 4k, bit eeproms for direct connection to serial ports br9010-w / br9010f-w / br9010fv-w / br9010rfv-w / br9010rfvm-w br9020-w / br9020f-w / br9020fv-w / br9020rfv-w / br9020rfvm-w br9040-w / br9040f-w / br9040fv-w / br9040rfv-w / br9040rfvm-w the br90xx series are serial eeproms that can be connected directly to a serial port and can be erased and written electrically. writing and reading is perfomed in word units, using four types of operation commands. communication occurs through cs, sk, di, and do pins, wc pin control is used to initiate a write disabled state, enabling these eeproms to be used as one-time roms. during writing operation is checked via the internal status check. z z z z application general-purpose z features 1) br9010-w / f-w / fv-w / rfv-w / rfvm-w (1k bit) : 64 words 16bit br9020-w / f-w / fv-w / rfv-w / rfvm-w (2k bit) : 128words 16bit br9040-w / f-w / fv-w / rfv-w / rfvm-w (4k bit) : 256words 16bit 2) single power supply. 3) serial data i/o. 4) self-timed programming cycle with auto-erase. 5) low supply current. active (5v) : 2ma (max.) standby (5v) : 3 a (max.) (cmos input) 6) noise filter on the sk pin. write protection when the supply is low. 7) write protection by wc pin. 8) space saving dip8/sop8/ssop-b8/msop8pin packages. 9) 100,000 erase/ write cycles endurance. 10) provide 10 years of date retention. 11) easy connection to serial port. 12) ?ffffh? stored in all address on shipped.
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 2/14 z z z z block diagram 16bit 16bit cs r / b wc sk di do 6bit br9010 7bit br9020 8bit br9040 6bit br9010 7bit br9020 8bit br9040 command decode control clock generation write disable power supply voltage detector high voltage generator address decoder r / w amplifier address buffer command register data register 1,024bit br9010 2,048bit br9020 4,096bit br9040 eeprom array z z z z terminal function 3 4 5 6 7 8 1 2 1 2 3 4 5 6 7 8 cs sk di do gnd wc r / b v cc br90xx-w/rfv-w/rfvm-w br90xxf-w/fv-w pin no. pin name chip select input serial date clock input serial date input (op code, address) ground (0v) write control input ready/ busy status output power supply serial date output function
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 3/14 z z z z absolute maximum ratings (ta = 25 c) parameter symbol limits unit ? 0.3 + 7.0 v mw 800 ? 1 450 ? 2 300 ? 3 dip8 ssop-b8 sop8 msop8 310 ? 4 ? 65 + 125 c ? 40 + 85 c v cc pd tstg topr ? ? 0.3 v cc + 0.3 v ? 1 degradation is done at 8.0mw/ ? c for operation above ta=25 ? c ? 2 degradation is done at 4.5mw/ ? c for operation above ta=25 ? c ? 3 degradation is done at 3.0mw/ ? c for operation above ta=25 ? c ? 4 degradation is done at 3.1mw/ ? c for operation above ta=25 ? c supply voltage power dissipation storage temperature operating temperature terminal voltage br9010-w, br9020-w, br9040-w br9010f-w, br9020f-w, br9040f-w br9010fv-w, br9010rfv-w, br9020fv-w, br9020rfv-w, br9040fv-w, br9040rfv-w br9010rfvm-w, br9020rfvm-w, br9040rfvm-w z z z z recommended operating condition (ta = 25 c) parameter symbol min. typ. max. unit v cc ? 5.5 v 2.0 2.7 ? 5.5 v v in 0 ? v cc v supply voltage write read input voltage
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 4/14 z z z z electrical characteristics unless otherwise specified ( ta =? 40~ + 85 c, v cc = 2.7v~5.5v) parameter min. typ. max. unit conditions ? i ol =2.1ma i oh = ? 0.4ma di pin di pin cs, sk, wc pin cs, sk, wc pin v in =0v v cc ? ? ? ? ? ? ? ? ? ? ? ? symbol v il1 v ih1 v il2 v ih2 v ol v oh i li i lo i cc1 i cc2 i sb f sk ? 0.7 v cc ? 0.8 v cc 0 v cc ? 0.4 ? 1 ? 1 ? ? ? ? v v v v v v a a ma ma a mhz 0.3 v cc ? 0.2 v cc ? 0.4 v cc 2 1 3 2 1 1 v out =0v v cc , cs=v cc cs, sk, di, wc=v cc , do, r / b=open f sk =2mhz, te / w=10ms (write) f sk =2mhz (read) input low voltage 1 input high voltage 1 input low voltage 2 input high voltage 2 output low voltage output high voltage input leakage current output leakage current operating current standby current clock frequency unless otherwise specified ( ta =? 40~ + 85 c, v cc = 2.7v~3.3v) parameter min. typ. max. unit conditions ? i ol =100 a i oh = ? 100 a di pin di pin cs, sk, wc pin cs, sk, wc pin v in =0v v cc ? ? ? ? ? ? ? ? ? ? ? ? symbol v il1 v ih1 v il2 v ih2 v ol v oh i li i lo i cc1 i cc2 i sb f sk ? 0.7 v cc ? 0.8 v cc 0 v cc ? 0.4 ? 1 ? 1 ? ? ? ? v v v v v v a a ma ma a mhz 0.3 v cc ? 0.2 v cc ? 0.4 v cc 1.5 0.5 2 2 1 1 v out =0v v cc , cs=v cc cs, sk, di, wc=v cc , do, r / b=open f sk =2mhz, te / w=10ms (write) f sk =2mhz (read) input low voltage 1 input high voltage 1 input low voltage 2 input high voltage 2 output low voltage output high voltage input leakage current output leakage current operating current standby current clock frequency
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 5/14 z z z z ac operation characteristics ( ta =? 40~ + 85 c, v cc = 2.7~5.5v) parameter symbol min. typ. max. unit t css 100 ?? ns t csh 100 ?? ns t wch 100 ?? ns t dis 100 ?? ns t dih ?? 150 ns t pd1 ?? 150 ns t pd0 ?? 10 ms t e / w 250 ?? ns t cs ?? 150 ns t sv 0 ? 150 ns t oh 230 ?? ns t wh 230 ?? ns t wl 0 ?? ns 0 ?? ns t wcs chip select setup time clock high time clock low time clock high to output ready/busy status data in setup time data in hold time delay to output high delay to output low self-timed program cycle minimum chip select high time data output disable time( from cs) chip select hold time write control setup time write control hold time
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 6/14 z z z z i / o circuit (1) input circuit di cs int. sk cs int. cs reset int. wc (2) output circuit oe int. do r/b
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 7/14 z z z z operating (1) instruction code 1010 1000 a0 a1 a2 a3 a4 a5 ( a6) ? 2 (a7) ? 1 a0 a1 a2 a3 a4 a5 ( a6) ? 2 (a7) ? 1 1010 0100 1010 0011 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d0 d1 ? d14 d15 (read data) d0 d1 ? d14 d15 (write data) 1010 0000 read write write enable (wen) write disable (wds) address and data must be transferred from lsb. br9020-w/f-w/fv-w/rfv-w/rfvm-w ? 1 = "0" br9010-w/f-w/fv-w/rfv-w/rfvm-w ? 1, 2 = "0" instruction start bit op code address data ? means either v ih or v il synchronous data input output timing cs sk di do wc t dis t dih t css t pd t oh t csh t cs t pd t wl t wh input data is clocked into the di pin on the rising edge of the clock sk output data is clocked out on the falling edge of the sk clock. the wc pin does not have any affect on the read, wen and wds operations. between instructions, cs must be brought high for greater than the minimum of t cs . if cs is maintained low, the next instruction isn't detected. fig.1
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 8/14 (2) write enable / disable high or low fig.2 1 1 high-z h sk cs di do r / b wc l h l h l h 01 000 48 enable = 11 disable = 00 12 16 1) when power is first applied, the device has been held in a reset status, with respect to the write enable, in the same way the write disable (wds) instruction is executed. before the write instruction is executed, the device must be received the write enable (wen) instruction. once the device is done, the device remains programmable until the write disable (wds) instruction is executed or the supply is removed from the device. 2) it is unnecessary to add the clock after 16 th clock. if the device is recieved the clock, the device ignores the clock. 3) as both of the enable and disable instructions don?t depend on the status of the wc pin, the state of wc isn?t cared during the instruction. 4) the instruction is recognized after the rising edge of 8 th clock for the address following 8 clocks for the opcode, but the specified address isn?t cared during the instructions.
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 9/14 (3) read cycle high or low fig.3 br9010-w / f--w / fv-w / rfv-w / rfvm-w 1 4 81632 1 high-z h sk cs di do wc l h l h l 01 1 0000 a0 a5 0 0 d0 d15 d15 d0 high-z standby t cs t oh r / b h read data (n) read data (n+1) high or low fig.4 br9020-w / f-w / fv-w / rfv-w / rfvm-w 1 4 8163248 1 high-z h sk cs di do r / b wc l h l h l h 01 1 0000 a0 a6 0 d0 read data (n) read data (n+1) d15 d15 d0 high-z standby t cs t oh high or low fig.5 br9040-w / f-w / fv-w / rfv-w / rfvm-w 1 4 81632 1 high-z h sk cs di do r / b wc l h l h l h 01 1 0 000 a0 a6 a7 d0 read data (n) read data (n+1) d15 d15 d0 high-z standby t cs t oh 1) on the falling edge of 16 th clock, the data stored in the specified address (n) is clocked out of the do pin. the output do is toggled after the internal propagation t pdo or t pd1 on the falling edge of sk. during t pd0 or t pd1, the data is the previous data or unstable, and to take in the data, t pd is needed. (refer to fig.1 synchronous data input output timing.) 2) the data stored in the next address is clocked out of the device on the falling edge of 32nd clock. the data stored in the upper address every 16 clocks is output sequentially by the continual sk input. also the read operation is reset by cs high.
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 10/14 (4) write cycle fig.6 br9010-w / f-w / fv-w / rfv-w / rfvm-w 14 8 1632 1 high-z high-z h sk cs di do wc l h l h l h l 01 0 0 1 00 00 a0 a5 d0 d15 t wch t wcs t cs r / b h t sv t e/w fig.7 br9020-w / f-w / fv-w / rfv-w / rfvm-w r / b h t sv 14 8 1632 1 high-z high-z h sk cs di do wc l h l h l h l 01 0 0100 0 a0 a6 d0 d15 t wch t e/w t wcs t cs fig.8 br9040-w / f-w / fv-w / rfv-w / rfvm-w r / b h t sv 14 8 1632 1 high-z high-z h sk cs di do wc l h l h l h l 01 0 0 1 0 0 a0 a6 a7 d0 d15 t wch t e/w t wcs t cs
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 11/14 1) during the write instruction , cs must be brought low. however once the write operation started, cs may be either high or low. but in the case of connecting the wc pin to the cs pin. cs and wc must be brought low during programming cycle.(if the wc pin is brought high during the write cycle, the write operation is halted. in that case, the data of the specified address is not guaranteed. it is necessary to rewrite it.) 2) after the r / b pin changed busy to ready, once cs is brought high, then cs keep low ,which means the status of being able to accept an instruction. the device can take in the input from sk and di, but in the case of keeping cs low without being brought high once, the input is canceled until being cs high once. 3) at the rising edge of 32 nd clock, the r / b pin will be driven low after the specified time delay (tsv). 4) during programming, r / b is tied to low by the device (on the rising edge of sk taken in the last data (d15), internal timer starts and automatically finished after the data of memory cell is written spending te / w. sk could be either high or low at the time. 5) after input write instruction, also the do pin will be able to show the status of r / b, in the case that cs is falling from high to low while sk is tied to low. (refer to ready / busy status in the next page.) (5) ready / busy status (on the r / b pin, the do pin) 1)the do pin outputs the ready / busy status of the internal part, which shows whether the device is ready to receive the next instruction or not. (high or low) after the write instruction is completed, if cs is brought from high to low while sk is low, the do pin outputs the internal status. (the r / b pin may be no connection. 2) when written to the memory cell, r / b status is output after tsv spent from the rising edge of 32 th clock on sk. r / b =low : under writing after spending te / w operating the internal timer, the device automatically finishes writing. during te / w, the memory array is accessed and any instruction is not received. r / b=high : ready auto programming has been completed. the device is ready to receive the next instruction. fig.9 r / b status output timing sk cs di do ready ready ready busy t pd t oh busy write instruction clock r / b high-z high-z
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 12/14 (6) about the direct connection between the di and do pins the device can be used with the di pin connected to the do pin directly. but when the ready / busy status is output, be careful about the bus conflict on the port of the controller. z z z z attention to use (1) power on / off 1) the cs is brought high during power?up and power?down. 2) this device is in active state while cs is low. 3) the extraordinary function or data collapse may occur in that condition because of noise etc, if power?up and power? down is done with cs brought low. in order to prevent above errors from happening, keep cs high during power-up and power-down. (good example) cs is brought high during power?up and power-down. please take more than 10ms between power?up and power-off, or the internal circuit is not always reset. (bad example) cs is brought low during power?up and power-down. the cs pin is always low in this case, the noise may force the device to make malfunction or inadvertent write. it sometimes occurs in the case that the cs pin is hi-z. v cc v cc gnd v cc gnd cs good bad fig.10 (2) noise rejection 1) sk noise if sk line has a lot of noise for rising time of sk, the device may recognize the noise as a clock and then clock will be shifted. 2) wc noise if wc line has noise during write cycle (te / w), there may be a chance to deny the programming. 3) vcc noise it recommended that capacitor is put between vcc and gnd to prevent these case, since it is possible to occur malfunction by the effect of noise or surge on power line.
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 13/14 (3) instruction mode cancel 1) read instruction 32 clocks start bit 4 bit 4 bit 8 bit 16 bit it is possible to be canceled for any timing. data do d15 opcode address sk cs di do wc high or low fig.11 how to cancel : cs is brought high. 2) write instruction 32 clocks start bit 4 bit c 4 bit 8 bit 16 bit do d15 opecode address data sk cs di r / b wc t e / w d b a fig.12 how to cancel a cs is brought high to cancel the instruction, and wc may be either high or low. b in case that wc is brought high for a moment, or cs is brought high, the write instruction is canceled, the data of the specified address is not changed. c when wc is brought high, or the device is powered down (but the latter way is not recommended), the instruction is canceled but the specified data is not guaranteed. send the instruction again. d when cs is brought high during r/b high, the device is reset and ready to receive a next instruction. note : the document may be strategic technical data subject to cocom regulations.
br9010-w / f-w / fv-w / rfv-w / rfvm-w / br9020-w / f-w / fv-w / memory ic rfv-w / rfvm-w / br9040-w / f-w / fv-w / rfv-w / rfvm-w 14/14 z z z z external dimensions (units : mm) dip8 ssop-b8 msop8 sop8 5 4 8 1 0.1 6.4 0.3 4.4 0.2 3.0 0.2 0.22 0.1 1.15 0.1 0.65 (0.52) 0.15 0.1 0.3min. 0.1 0.3min. 0.15 0.1 0.4 0.1 0.11 6.2 0.3 4.4 0.2 5.0 0.2 85 4 1 1.27 1.5 0.1 0.1 4 1 5 8 2.9 0.1 0.475 0.65 4.0 0.2 0.6 0.2 0.29 0.15 2.8 0.1 0.75 0.05 0.08 0.05 0.9max. 0.08 s 0.08 m 0.145 + 0.05 ? 0.03 0.22 + 0.05 ? 0.04 0.5 0.1 3.2 0.2 3.4 0.3 85 14 9.3 0.3 6.5 0.3 0.3 0.1 0.51min. 2.54 0 ~ 15 7.62 br9010-w, br9020-w, br9040-w br9010f-w, br9020f-w, br9040f-w br9010fv-w, br9010rfv-w br9020fv-w, br9020rfv-w br9040fv-w, br9040rfv-w br9010rfvm-w, br9020rfvm-w, br9040rfvm-w

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