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1 file number 2785.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hsp43891 digital filter the hsp43891 is a video-speed digital filter (df) designed to efficiently implement vector operations such as fir digital filters. it is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. each filter cell contains a 9x9 twos complement multiplier, three decimation registers and a 26-bit accumulator. the output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8-bits. the hsp43891 has a maximum sample rate of 30mhz. the effective multiply-accumulate (mac) rate is 240mhz. the hsp43891 df can be configured to process expanded coefficient and word sizes. multiple dfs can be cascaded for larger filter lengths without degrading the sample rate or a single df can process larger filter lengths at less than 30mhz with multiple passes. the architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. in practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. the df provides for 8-bit unsigned or 9-bit twos complement arithmetic, independently selectable for coefficients and signal data. each df ?lter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1 / 2 , 1 / 3 or 1 / 4 the input sample rate. these registers also provide the capability to perform 2-d operations such as matrix multiplication and nxn spatial correlations/convolutions for image processing applications. features ? eight filter cells ? 0mhz to 30mhz sample rate ? 9-bit coef?cients and signal data ? 26-bit accumulator per stage ? filter lengths over 1000 taps ? expandable coefficient size, data size and filter length ? decimation by 2, 3 or 4 applications ? 1-d and 2-d fir filters ? radar/sonar ? digital video ? adaptive filters ? echo cancellation ? complex multiply-add - sample rate converters block diagram ordering information part number temp. range ( o c) package pkg. no. hsp43891vc-20 0 to 70 100 lead mqfp q100.14x20 hsp43891vc-25 0 to 70 100 lead mqfp q100.14x20 hsp43891vc-30 0 to 70 100 lead mqfp q100.14x20 hsp43891jc-20 0 to 70 84 lead plcc n84.1.15 hsp43891jc-25 0 to 70 84 lead plcc n84.1.15 hsp43891jc-30 0 to 70 84 lead plcc n84.1.15 hsp43891gc-20 0 to 70 85 pin cpga g85.a HSP43891GC-25 0 to 70 85 pin cpga g85.a hsp43891gc-30 0 to 70 85 pin cpga g85.a cin0 - 8 df filter cell 7 cout0 - 8 erase dcm0 - 1 dienb cienb coenb mux reset 26 adr0, adr1, adr2 clk reset shadd senbh senbl output stage v cc v ss din0 - din8 sum0 - 25 3 9 df filter cell 6 26 9 df filter cell 5 26 9 df filter cell 4 26 9 df filter cell 3 26 9 df filter cell 2 26 9 df filter cell 1 26 9 df filter cell 0 26 9 9 5 5 2 26 26 2 9 5 clk adro - 2 data sheet may 1999
2 pinout 85 pin grid array (pga) 84 lead plastic leaded chip carrier (plcc) a b c d e f g h j k l coenb reset din7 v cc din6 din3 din0 cin8 v cc v cc cout7 erase din1 din2 cienb cin7 cin6 cin4 cout5 cout6 align pin dienb din5 din4 cin5 cin3 cin2 v cc cin1 cin0 senbl cout3 cout4 cout1 v ss cout2 v ss cout0 shadd adr2 dcm0 clk sum0 v cc v ss sum1 sum3 sum2 sum5 sum4 adr0 sum25 v cc sum7 v ss sum16 sum17 sum20 senbh sum24 v ss v cc sum19 v ss sum15 sum12 sum10 sum8 sum6 sum9 sum11 v ss sum13 v cc sum14 sum18 sum21 sum22 sum23 dcm1 2 17 3 4 5 6 8 9 10 11 v ss cout8 din8 adr1 hsp43891 bottom view pins up dcm1 sum23 sum22 sum21 sum18 sum14 sum13 sum11 sum9 v ss v cc sum20 sum17 sum16 sum7 adr0 sum5 sum4 adr2 dcm0 clk v ss cout0 shadd sum1 sum3 sum2 sum0 v cc v ss cin2 v cc cout3 cout4 align pin a b c d e f g h j k l 1234 567891011 adr1 sum25 v cc v ss v ss v cc v ss senbh sum24 sum19 sum15 sum12 sum10 sum8 sum6 cin1 cin0 senbl cout1 v ss cout2 cout5 cout6 dienb din5 din4 cin5 cin3 v cc v ss din0 din3 din6 din7 v ss coenb v cc reset cin8 v cc cin4 cin6 cin7 cienb din2 din1 erase cout7 din8 cout8 top view pins down hsp43891 v ss 111098765432184838281807978777675 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 hsp43891 top view sum22 sum18 sum16 sum15 sum14 sum13 sum12 sum11 sum23 sum21 sum20 sum19 sum17 cout6 cout7 cout8 din8 din7 din6 din5 din4 din3 din2 v cc v ss v cc v ss sum10 sum9 sum8 sum7 sum1 sum2 sum3 sum4 sum5 sum6 v ss v cc cin4 cin3 cin2 cin0 sum0 v ss cin1 v cc cin5 v ss cin7 cin6 senbl din1 din0 cin8 v cc v cc v ss dienb reset coenb erase addr2 dcm0 addr1 sum25 clk cout0 shadd cout2 dcm1 sum24 cout1 v ss v cc addr0 v ss v ss cout3 cout4 cout5 v cc cienb senbh hsp43891
3 100 lead mqfp top view pinout (continued) 99 98 97 96 95 94 93 91 89 87 85 84 83 81 82 86 88 90 92 100 79 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 cienb cin8 v cc cin6 v ss cin7 din0 reset dienb din8 din7 din5 din4 din3 din2 din1 din6 erase cout5 v cc v cc cout6 v ss v ss coenb v cc v cc cout7 cout4 cout8 v cc v ss v ss sum17 sum16 v cc sum15 sum14 sum13 sum12 sum18 sum11 v ss sum24 v ss v ss sum23 sum22 v cc v cc sum21 sum20 sum19 dcm1 sum10 sum9 nc sum8 sum7 sum6 32 33 34 35 36 37 38 40 42 44 46 47 48 50 49 45 43 41 39 31 v cc v ss v ss sum5 sum4 sum3 sum2 sum1 sum0 v ss v ss senbl cin0 cin1 v cc cin2 cin3 cin4 cin5 v ss v cc v cc sum25 v ss v ss cout3 cout2 cout1 cout0 shadd clk addr2 dcm0 v ss v ss addr1 addr0 v cc v cc senbh hsp43891
4 pin description symbol pin number type name and function v cc b1, j1, a3, k4, l7, a10, f10, d11 +5 power supply input. v ss a1, f1, e2, k3, k6, l9, a11, f11, j11 power supply ground input. clk g3 i the clk input provides the df system sample clock. the maximum clock frequency is 30mhz. din0-8 a5-8, b5-7, c6, c7 i these nine inputs are the data sample input bus. nine-bit data samples are synchronously loaded through these pins to the x register of each ?lter cell of the df simultaneously. the dienb signal en- ables loading, which is synchronous on the rising edge of the clock signal. the data samples can be either 9-bit twos complement or 8-bit unsigned values. for 9-bit twos com- plement values, din8 is the sign bit. for 8-bit unsigned values, din8 must be held at logical zero. dienb c5 i a low on this input enables the data sample input bus (din0-8) to all the ?lter cells. a rising edge of the clk signal occurring while dienb is low will load the x register of every ?lter cell with the 9-bit value present on din0-8. a high on this input forces all the bits of the data sample input bus to zero; a rising clk edge when dienb is high will load the x register of every ?lter cell with all zeros. this signal is latched inside the device, delaying its effect by one clock internal to the device. therefore it must be low during the clock cycle immediately preceding presentation of the desired data on the din0-8 inputs. de- tailed operation is shown in later timing diagrams. cin0-8 a9, b9-11, c10, c11, d10, e9, e10 i these nine inputs are used to input the 9-bit coef?cients. the coef?cients are synchronously loaded into the c register of ?lter cell0 if a rising edge of clk occurs while cienb is low. the cienb signal is delayed by one clock as discussed below. the coef?cients can be either 9-bit twos complement or 8-bit unsigned values. for 9-bit twos comple- ment values, cin8 is the sign bit. for 8-bit unsigned values, cin8 must be held at logical zero. align pin c3 used for aligning chip on socket or printed circuit board. this pin must be left as a no connect in circuit. cienb b8 i a low on this input enables the c register of every ?lter cell and the d (decimation) registers of every ?lter cell according to the state of the dcm0-1 inputs. a rising edge of the clk signal occurring while cienb is low will load the c register and appropriate d registers with the coef?cient data present at their inputs. this provides the mechanism for shifting coef?cients from cell to cell through the device. a high on this input freezes the contents of the c register and the d registers, ignoring the clk signal. this signal is latched and delayed by one clock internal to the df. therefore it must be low during the clock cycle immediately preceding presentation of the desired coef?cient on the cin0-8 inputs. detailed operation is shown in later timing diagrams. cout0-8 b2, b3, c1, d1, e1, c2, d2, f2, e3 o these nine three-state outputs are used to output the 9-bit coef?cients from ?lter cell7. these outputs are enabled by the coenb signal low. these outputs may be tied to the cin0-8 inputs of the same df to recirculate to coef?cients, or they may be tied to the cin0-8 inputs of another df to cascade dfs for longer ?lter lengths. coenb a2 i a low on the coenb input enables the cout0-8 outputs. a high on this input places all these outputs in their high impedance state. dcm0-1 l1, g2 i these two inputs determine the use of the internal decimation registers as follows: dcm1 dcm0 decimation function 0 0 decimation registers not used 0 1 one decimation register is used 1 0 two decimation registers are used 1 1 three decimation registers are used the coef?cients pass from cell to cell at a rate determined by the number of decimation registers used. when no decimation registers are used, coef?cients move from cell to cell on each clock. when one decimation register is used, coef?cients move from cell to cell on every other clock, etc. these signals are latched and delayed by one clock internal to the device. hsp43891
5 functional description the digital filter processor (df) is composed of eight ?lter cells cascaded together and an output stage for combining or selecting ?lter cell outputs (see block diagram). each ?lter cell contains a multiplier-accumulator and several registers (figure 1). each 9-bit coef?cient is multiplied by a 9-bit data sample, with the result added to the 26-bit accumulator contents. the coef?cient output of each cell is cascaded to the coef?cient input of the next cell to its right. df filter cell a 9-bit coef?cient (cin0-8) enters each cell through the c register on the left and exits the cell on the right as signals cout0-8. with no decimation, the coef?cient moves directly from the c register to the output, and is valid on the clock following its entrance. when decimation is selected the coef?cient exit is delayed by 1, 2 or 3 clocks by passing through one or more decimation registers (d1, d2 or d3). the combination of d registers through which the coef?cient passes is determined by the state of dcm0 and dcm1. the output signals (cout0-8) are connected to the cin0-8 inputs of the next cell to its right. the coenb input signal enables the cout0-8 outputs of the right most cell to the cout0-8 pins of the device. the c and d registers are enabled for loading by cienb. loading is synchronous with clk when cienb is low. note that cienb is latched internally. it enables the register for loading after the next clk following the onset of cienb low. actual loading occurs on the second clk following the onset of cienb low. therefore cienb must be low during the clock cycle immediately preceding presentation of the coef?cient on the cin0-8 inputs. in most basic fir operations, cienb will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. when cienb is high, the coef?cients are frozen. the c and d registers are cleared synchronously under control of reset, which is latched and delayed exactly like cienb. the output of the c register (c0-8) is one input to 9 x 9 multiplier. the other input to the 9 x 9 multiplier comes from the output of the x register. this register is loaded with a data sample from the device input signals din0-8 discussed above. the x register is enabled for loading by dienb. loading is synchronous with clk when dienb is low. note that dienb is latched internally. it enables the register for loading after the next clk following the onset of dienb low. actual loading occurs on the second clk following the onset of dienb low; therefore, dienb must be low during the clock sum0-25 f9, g9-g11, h10, h11, j2, j5-j7, j10, k2, k5, k7-k11, l2-l6, l8, l10, l11 o these 26 three-state outputs are used to output the results of the internal ?lter cell computations. indi- vidual ?lter cell results or the result of the shift and add output stage can be output. if an individual ?lter cell result is to be output, the adr0-2 signals select the ?lter cell result. the shadd signal determines whether the selected ?lter cell result or the output stage adder result is output. the signals senbh and senbl enable the most signi?cant and least signi?cant bits of the sum0-25 result respectively. both senbh and senbl may be enabled simultaneously if the system has a 26-bit or larger bus. however individual enables are provided to facilitate use with a 16-bit bus. senbh k1 i a low on this input enables result bits sum16-25. a high on this input places these bits in their high impedance state. senbl e11 i a low on this input enables result bits sum0-15. a high on this input places these bits in their high im- pedance state. adr0-2 g1, h1, h2 i these three inputs select the one cell whose accumulator will be read through the output bus (sum0- 25) or added to the output stage accumulator. they also determine which accumulator will be cleared when erase is low. these inputs are latched in the df and delayed by one clock internal to the device. if adr0-2 remains at the same address for more than one clock, the output at sum0-25 will not change to re?ect any subsequent accumulator updates in the addressed cell. only the result available during the ?rst clock, when adr0-2 selects the cell, will be output. this does not hinder normal operation since the adr0-2 lines are changed sequentially. this feature facilitates the interface with slow memories where the output is required to be ?xed for more than one clock. shadd f3 i the shadd input controls the activation of the shift and add operation in the output stage. this signal is latched on chip and delayed by one clock internal to the device. detailed explanation is given in the df output stage section. reset a4 i a low on this input synchronously clears all the internal registers, except the cell accumulators it can be used with erase to also clear all the accumulators simultaneously. this signal is latched in the df and delayed by one clock internal to the device. erase b4 i a low on this input synchronously clears the cell accumulator selected by the adr0-2 signals. if reset is also low simultaneously, all cell accumulators are cleared. pin description (continued) symbol pin number type name and function hsp43891
6 cycle immediately preceding presentation of the data sample on the din0-8 inputs. in most basic fir operations, dienb will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. when dienb is high, the x register is loaded with all zeros. the multiplier is pipelined and is modeled as a multiplier core followed by two pipeline registers, mreg0 and mreg1 (figure 1). the multiplier output is sign extended and input as one operand of the 26-bit adder. the other adder operand is the output of the 26-bit accumulator. the adder output is loaded synchronously into both the accumulator and the treg. the treg loading is disabled by the cell select signal, celln, where n is the cell number. the cell select is decoded from the adr0-2 signals to generate the treg load enable. the cell select is inverted and applied as the load enable to the treg. operation is such that the treg is loaded whenever the cell is not selected. therefore, treg is loaded every clock except the clock following cell selection. the purpose of the treg is to hold the result of a sum-of- products calculation during the clock when the accumulator is cleared to prepare for the next sum-of-products calculation. this allows continuous accumulation without wasting clocks. the accumulator is loaded with the adder output every clock unless it is cleared. it is cleared synchronously in two ways. when reset and erase are both low, the accumulator is cleared along with all other registers on the device. since erase and reset are latched and delayed one clock internally, clearing occurs on the second clk following the onset of both erase and reset low. the second accumulator clearing mechanism clears a single accumulator in a selected cell. the cell select signal, celln, decoded from adr0-2 and the erase signal enable clearing of the accumulator on the next clk. the erase and reset signals clear the df internal registers and states as follows: the df output stage the output stage consists of a 26-bit adder, 26-bit register, feedback multiplexer from the register to the adder, an output multiplexer and a 26-bit three-state driver stage (figure 2). the 26-bit output adder can add any ?lter cell accumulator result to the 18 most signi?cant bits of the output buffer. this result is stored back in the output buffer. this operation takes place in one clock period. the eight lsbs of the output buffer are lost. the ?lter cell accumulator is selected by the adr0-2 inputs. the 18 msbs of the output buffer actually pass through the zero mux on their way to the output adder input. the zero mux is controlled by the shadd input signal and selects either the output buffer 18 msbs or all zeros for the adder input. a low on the shadd input selects zero. a high on the shadd input selects the output buffer msbs, thus, activating the shift-and-add operation. the shadd signal is latched and delayed by one clock internally. erase reset clearing effect 1 1 no clearing occurs, internal state remains same. 10 reset only active, all registers except ac- cumulators are cleared, including the inter- nal pipeline registers. 01 erase only active, the accumulator whose address is given by the adr0-2 in- puts is cleared. 0 0 both reset and erase active, all accu- mulators as well as all other registers are cleared. hsp43891
7 figure 1. hsp43891 df filter cell clk cin0-8 c0-8 ld clr c reg clk ld clr d1 reg ld clr d2 reg clk ld clr d3 reg d0-8 c0-8 three-state buffers on cell 7 only cout0-8 coenb 0 mux 1 1 0 mux clk din0-8 ld clr x reg reset.d dienb.d cienb.d dcm0.d reset.d dcm1.d clk mreg0 clr c multi- plier core x p0-17 x0-8 reset.d sign extension adder mreg1 clr 0-17 acc clr clk acc0-25 acc.d0-25 erase.d celln t reg ld aout0-25 d q celln clk latches dcm1 dcm0 reset dienb cienb adr0 adr1 adr2 erase clk dcm1.d dcm0.d reset.d dienb.d cienb.d adr0.d adr1.d adr2.d erase.d adr1 adr2 adr0 de- coder cell 0 cell 1 cell 7 hsp43891
8 the 26 least signi?cant bits (lsbs) from either a cell accumulator or the output buffer are output on the sum0-25 bus. the output mux determines whether the cell accumulator selected by adr0-2 or the output buffer is output to the bus. this mux is controlled by the shadd input signal. control is based on the state of the shadd during two successive clocks; in other words, the output mux selection contains memory. if shadd is low during a clock cycle and was low during the previous clock, the output mux selects the contents of the ?lter cell accumulator addressed by adr0-2. otherwise the output mux selects the contents of the output buffer. if the adr0-2 lines remain at the same address for more than one clock, the output at sum0-25 will not change to re?ect any subsequent accumulator updates in the addressed cell. only the result available during the ?rst clock when adr0-2 selects the cell will be output. this does not hinder normal fir operation since the adr0-2 lines are changed sequentially. this feature facilitates the interface with slow memories where the output is required to be ?xed for more than one clock. the sum0-25 output bus is controlled by the senbh and senbl signals. a low on senbl enables bits sum0-15. a low on senbh enables bits sum16-25. thus, all 26 bits can be output simultaneously if the external system has a 26-bit or larger bus. if the external system bus is only 16 bits, the bits can be enabled in two groups of 16 and 10 bits (sign extended). df arithmetic both data samples and coef?cients can be represented as either 8-bit unsigned or 9-bit twos complement numbers. the 9x9 bit multiplier in each cell expects 9-bit twos complement operands. the binary format of 8-bit twos complement is shown below. note that if the most signi?cant or sign bit is held at logical zero, the 9-bit twos complement multiplier can multiply 8-bit unsigned operands. only the upper (positive) half of the twos complement binary range is used. the multiplier output is 18 bits and the accumulator is 26 bits. the accumulator width determines the maximum possible number of terms in the sum of products without over?ow. the maximum number of terms depends also on the number system and the distribution of the coef?cient and data values. then maximum numbers of terms in the sum products are: for practical fir ?lters, the coef?cients are never all near maximum value, so even larger vectors are possible in practice. basic fir operation a simple, 30mhz 8-tap ?lter example serves to illustrate more clearly the operation of the df. the sequence table (table 1) shows the results of the multiply accumulate in each cell after each clock. the coef?cient sequence, c n , enters the df on the left and moves from left to right through the cells. the data sample sequence, x n , enters the df from the top, with each cell receiving the same sample simultaneously. each cell accumulates the sum of products for one output point. eight sums of products are calculated simultaneously, but staggered in time so that a new output is available every system clock. 26 0-18 output reset.d sign ext cell result mux 3 cell results 26 0 26 1 26 6 26 7 adr0.d - adr2.d 18 8 18-25 18 (lsbs) 0-17 26 + buffer clk 26 26 26 output mux 10 26 3-state buffer 26 sum0-25 18 mux zero 01 0s 0-17 8-25 18 msbs shifted 8 bits to right 2 senbl senbh clk clr d q reset.d clk clr d q reset.d shadd shadd.d figure 2. hsp43891 dfp output stage number system maximum # of terms 8-bit 9-bit two unsigned vectors 1032 n/a two twos complement vectors ? two positive vectors 2080 1032 ? negative vectors 2047 1024 ? one positive and one negative vector 2064 1028 one unsigned 8-bit vector and one twos complement vector ? positive twos complement vector 1036 1032 ? negative twos complement vector 1028 1028 hsp43891
9 table 1. hsp43891 30mhz, 8-tap fir filter sequence clk cell 0 cell 1 cell 2 cell 3 cell 4 cell 5 cell 6 cell 7 sum/clr 0c 7 x x 0 000---- - 1+c 6 x x 1 c 7 x x 1 00---- - 2+c 5 x x 2 +c 6 x x 2 c 7 x x 2 0---- - 3+c 4 x x 3 +c 5 x x 3 +c 6 x x 3 c 7 x x 3 ---- - 4+c 3 x x 4 +c 4 x x 4 +c 5 x x 4 +c 6 x x 4 c 7 x x 4 --- - 5+c 2 x x 5 +c 3 x x 5 +c 4 x x 5 +c 5 x x 5 +c 6 x x 5 c 7 x x 5 -- - 6+c 1 x x 6 +c 2 x x 6 +c 3 x x 6 +c 4 x x 6 +c 5 x x 6 +c 6 x x 6 c 7 x x 6 -- 7+c 0 x x 7 +c 1 x x 7 +c 2 x x 7 +c 3 x x 7 +c 4 x x 7 +c 5 x x 7 +c 6 x x 7 c 7 x x 7 cell 0 (y 7 ) 8c 7 x x 8 +c 0 x x 8 +c 1 x x 8 +c 2 x x 8 +c 3 x x 8 +c 4 x x 8 +c 5 x x 8 +c 6 x x 8 cell 1 (y 8 ) 9+c 6 x x 9 c 7 x x 9 +c 0 x x 9 +c 1 x x 9 +c 2 x x 9 +c 3 x x 9 +c 4 x x 9 +c 5 x x 9 cell 2 (y 9 ) 10 +c 5 x x 10 +c 6 x x 10 c 7 x x 10 +c 0 x x 10 +c 1 x x 10 +c 2 x x 10 +c 3 x x 10 +c 4 x x 10 cell 3 (y 10 ) 11 +c 4 x x 11 +c 5 x x 11 +c 6 x x 11 c 7 x x 11 +c 0 x x 11 +c 1 x x 11 +c 2 x x 11 +c 3 x x 11 cell 4 (y 11 ) 12 +c 3 x x 12 +c 4 x x 12 +c 5 x x 12 +c 6 x x 12 c 7 x x 12 +c 0 x x 12 +c 1 x x 12 +c 2 x x 12 cell 5 (y 12 ) 13 +c 2 x x 13 +c 3 x x 13 +c 4 x x 13 +c 5 x x 13 +c 6 x x 13 c 7 x x 13 +c 0 x x 13 +c 1 x x 13 cell 6 (y 13 ) 14 +c 1 x x 14 +c 2 x x 14 +c 3 x x 14 +c 4 x x 14 +c 5 x x 14 +c 6 x x 14 +c 7 x x 14 +c 0 x x 14 cell 7 (y 14 ) 15 +c 0 x x 15 +c 1 x x 15 +c 2 x x 15 +c 3 x x 15 +c 4 x x 15 +c 5 x x 15 +c 6 x x 15 c 7 x x 15 cell 0 (y 15 ) x 15 . . . x 9 , x 8 , x 7 . . . x 1 , x 0 c 0 . . . c 6 , c 7 , c 0 . . . c 6 , c 7 hsp43891 . . . y 15 , y 14 . . . y 8 , y 7 sample data in (x n ) 30mhz clock 3-bit counter y 2 y 1 y 0 +5v d0-d8 system reset erase adr2 adr1 adr0 v cc shadd senbh senbl din0-8 dienb clk cin0-8 cienb dcm1 dcm0 reset erase v ss coenb cout0-8 sum0-25 26 sum out (y n ) 9 nc hsp43891 9 ram/rom 9 x 8 coeff. a 2 a 1 a 0 9 figure 3. hsp43891 30mhz, 8-tap fir filter application schematic hsp43891
10 detailed operation of the df to perform a basic 8-tap, 9-bit coef?cient, 9-bit data, 30mhz fir ?lter is best understood by observing the schematic (figure 3) and timing diagram (figure 4). the internal pipeline length of the df is four (4) clock cycles, corresponding to the register levels creg (or xreg), mreg0, mreg1, and treg (figures 1 and 2). therefore, the delay from presentation of data and coef?cients at the din0-8 and cin0-8 inputs to a sum appearing at the sum0-25 output is: k + td, where k = ?lter length and td = 4, the internal pipeline delay of the df. after the pipeline has ?lled, a new output sample is available every clock. the delay to last sample output from last sample input is td. the output sums, y n , shown in the timing diagram are derived from the sum-of-products equation. y n = 7 s k0 = c k x nk C c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 7 c 6 c 5 01234567891011121314151617181920 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 x 17 x 18 012345670 y 7 y 8 y 9 y 10 y 11 y 12 y 13 y 14 clk reset erase din0-8 dienb cin0-8 cienb adr0-2 sum0-25 shadd senbl senbh dcm0-1 0 figure 4. hsp43891 30mhz, 8-tap fir filter timing +5v adr1 adr0 adr2 v cc shadd senbh senbl din0-8 dienb clk cin0-8 cienb dcm1 dcm0 reset erase v ss coenb cout0-8 sum0-25 26 sum out 9 nc hsp43891 9 (y n ) +5v 26 9 9 9 30mhz clock q q c d sample data in (x n ) 9x16 coeff ram/rom a 0 a 1 a 2 a 3 d0-d8 clk y 0 y 1 y 2 y 3 reset 4-bit ctr system reset adr1 adr0 adr2 v cc shadd senbh senbl din0-8 dienb clk cin0-8 cienb dcm1 dcm0 reset erase v ss coenb cout0-8 sum0-25 hsp43891 df1 df0 figure 5. hsp43891 30mhz, 16-tap fir filter cascade application schematic hsp43891
11 extended fir filter length filter lengths greater that eight taps can be created by either cascading together multiple df devices or reusing a single device. using multiple devices, an fir ?lter of over 1000 taps can be constructed to operate at a 30mhz sample rate. using a single device clocked at 30mhz, an fir ?lter of over 500 taps can be constructed to operate at less than a 30mhz sample rate. combinations of these two techniques are also possible. cascade con?guration to design a ?lter length l > 8, l/8 dfs are cascaded by connecting the cout0-8 outputs of the (i)th df to the cin0- 8 inputs of the (i+1)th df. the din0-8fs inputs and sum0-25 outputs of all the dfs are also tied together. a speci?c example of two cascaded dfs illustrates the technique (figure 5). timing (figure 6) is similar to the simple 8-tap fir, except the erase and senbl/ senbh signals must be enabled independently for the two dfs in order to clear the correct accumulators and enable the sum0-25 output signals at the proper times. table 2. clk cell 0 cell 1 cell 2 cell 3 cell 4 cell 5 cell 6 cell 7 sum/clr 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 c 15 x x 0 +c 14 x x 1 +c 13 x x 2 +c 12 x x 3 +c 11 x x 4 +c 10 x x 5 +c 9 x x 6 +c 8 x x 7 +c 7 x x 8 +c 6 x x 9 +c 5 x x 10 +c 4 x x 11 +c 3 x x 12 +c 2 x x 13 +c 1 x x 14 +c 0 x x 15 0 0 0 0 0 0 0 c 15 x x 8 +c 14 x x 9 +c 13 x x 10 +c 12 x x 11 +c 11 x x 12 +c 10 x x 13 +c 9 x x 14 +c 8 x x 15 +c 7 x x 16 +c 6 x x 17 +c 5 x x 18 +c 4 x x 19 +c 3 x x 20 +c 2 x x 21 +c 1 x x 22 +c 0 x x 23 0 0 0 0 0 c 15 x x 1 c 0 x x 16 0 0 0 0 0 0 0 +c 15 x x 9 c 0 x x 23 0 0 0 0 0 c 15 x x 2 c 0 x x 17 0 0 0 0 0 0 0 +c 15 x x 10 c 0 x x 25 0 0 0 0 0 c 15 x x 3 +c 14 x x 4 +c 13 x x 5 +c 12 x x 6 +c 11 x x 7 +c 10 x x 8 +c 9 x x 9 +c 8 x x 10 +c 7 x x 11 +c 6 x x 12 +c 5 x x 13 +c 4 x x 14 +c 3 x x 15 +c 2 x x 16 +c 1 x x 17 +c 0 x x 18 0 0 0 0 0 0 0 +c 15 x x 11 c 0 x x 26 0 - - - - c 15 x x 4 c 0 x x 19 0 0 0 0 0 0 0 +c 15 x x 12 c 0 x x 27 - - - - - c 15 x x 5 c 0 x x 20 0 0 0 0 0 0 0 +c 15 x x 12 - - - - - - c 15 x x 6 c 0 x x 21 0 0 0 0 0 0 0 +c 15 x x 14 - - - - - - - c 15 x x 7 +c 14 x x 8 +c 13 x x 9 +c 12 x x 10 +c 11 x x 11 +c 10 x x 12 +c 9 x x 13 +c 8 x x 14 +c 7 x x 15 +c 6 x x 16 +c 5 x x 17 +c 4 x x 18 +c 3 x x 19 +c 2 x x 20 +c 1 x x 21 +c 0 x x 22 0 0 0 0 0 0 0 c 15 x x 15 +c 14 x x 16 +c 13 x x 17 +c 12 x x 18 +c 11 x x 19 +c 10 x x 20 +c 9 x x 21 +c 8 x x 22 +c 7 x x 23 +c 6 x x 24 +c 5 x x 25 +c 4 x x 26 +c 3 x x 27 - - - - - - - - - - - - - - - cell 0 (y 15 ) cell 1 (y 16 ) cell 2 (y 17 ) cell 3 (y 18 ) cell 4 (y 19 ) cell 5 (y 20 ) cell 6 (y 21 ) cell 7 (y 22 ) - - - - - - - - - - - - - - - cell 0 (y 23 ) cell 1 (y 24 ) cell 2 (y 25 ) cell 3 (y 26 ) cell 4 (y 27 ) data sequence input x 30 . . . x 9 , x 8 , x 22 . . . x 1 , x 0 coefficient sequence input c 0 . . . c 14 , c 15 , 0 . . . c 0 . . . c 14 , c 15 hsp43891 . . . 0, y 30 . . . y 23 , 0. . . 0, y 22 . . . y 15 , 0. . . 0 hsp43891
12 single df con?guration using a single df, a ?lter of length l>8 can be constructed by processing in l/8 passes, as illustrated in table 2, for a 16-tap fir. each pass is composed of tp = 7 + l cycles and computes eight output samples. in pass i, the sample with indices i*8 to i*8 +(l-1) enter the din0-8 inputs. the coef?cients c 0 - c l - 1 enter the cin0-8 inputs, followed by seven zeros. as these zeros are entered, the result samples are output and the accumulators reset. initial ?ling of the pipeline is not shown in this sequence table. filter outputs can be put through a fifo to even out the sample rate. extended coef?cient and data sample word size the sample and coef?cient word size can be extended by utilizing several dfs in parallel to get the maximum sample rate or a single df with resulting lower sample rates. the technique is to compute partial products of 9 x 9 and combine these partial products by shifting and adding to obtain the ?nal result. the shifting and adding can be accomplished with external adders (at full speed) or with the dfs shift-and-add mechanism contained in its output stage (at reduced speed). decimation/resampling the hsp43891 df provides a mechanism for decimating by factors of 2, 3, or 4. from the df ?lter cell block diagram (figure 1), note the three d registers and two multiplexers in the coef?cient path through the cell. these allow the coef?cients to be delayed by 1, 2, or 3 clocks through the cell. the sequence table (table 3) for a decimate-by-two ?lter illustrates the technique (internal cell pipelining ignored for simplicity). detailed timing for a 30mhz input sample rate, 15mhz output sample rate (i.e., decimate-by-two), 16-tap fir ?lter, including pipelining, is shown in figure 7. this ?lter requires only a single hsp43891 df. hsp43891
13 figure 6. hsp43891 16-tap 30mhz filter timing using two cascaded hsp43891s c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 01234567891011121314151617181920 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 x 17 x 18 012345670 clk reset df0 din0-8 cin0-8 cienb adr0-2 df0 shadd df0 dcm0-1 y n c k x nk C k0 = 15 ? = sum0-25 df1 sum0-25 0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 x 19 x 20 x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 30 x 31 x 32 x 33 x 34 x 35 x 36 x 37 12345670 erase df1 erase c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 15 c 14 c 13 c 12 c 11 c 10 123 y 15 y 16 y 17 y 18 y 19 y 20 y 21 y 22 y 31 y 32 y 33 y 23 y 24 y 25 y 26 y 27 y 28 y 29 y 30 senbl/h df1 senbl/h hsp43891
14 table 3. hsp43891 16-tap decimate-by-two fir filter sequence; 30mhz in, 15mhz out clk cell 0 cell 1 cell 2 cell 3 cell 4 cell 5 cell 6 cell 7 sum/clr 6c 15 x x 0 0000000 - 7+c 14 x x 1 0000000 - 8+c 13 x x 2 c 15 x x 2 000000 - 9+c 12 x x 3 +c 14 x x 3 000000 - 10 +c 11 x x 4 +c 13 x x 4 c 15 x x 4 00000 - 11 +c 10 x x 5 +c 12 x x 5 +c 14 x x 5 00000 - 12 +c 9 x x 6 +c 11 x x 6 +c 13 x x 6 c 15 x x 6 0000 - 13 +c 8 x x 7 +c 10 x x 7 +c 12 x x 7 +c 14 x x 7 0000 - 14 +c 7 x x 8 +c 9 x x 8 +c 11 x x 8 +c 13 x x 8 c 15 x x 8 000 - 15 +c 6 x x 9 +c 8 x x 9 +c 10 x x 9 +c 12 x x 9 +c 14 x x 9 000 - 16 +c 5 x x 10 +c 7 x x 10 +c 9 x x 10 +c 11 x x 10 +c 13 x x 10 c 15 x x 10 00 - 17 +c 4 x x 11 +c 6 x x 11 +c 8 x x 11 +c 10 x x 11 +c 12 x x 11 +c 14 x x 11 00 - 18 +c 3 x x 12 +c 5 x x 12 +c 7 x x 12 +c 9 x x 12 +c 11 x x 12 +c 13 x x 12 c 15 x x 12 0- 19 +c 2 x x 13 +c 4 x x 13 +c 6 x x 13 +c 8 x x 13 +c 10 x x 13 +c 12 x x 13 +c 14 x x 13 0- 20 +c 1 x x 14 +c 3 x x 14 +c 5 x x 14 +c 7 x x 14 +c 9 x x 14 +c 11 x x 14 +c 13 x x 14 c 15 x x 14 - 21 +c 0 x x 15 +c 2 x x 15 +c 4 x x 15 +c 6 x x 15 +c 8 x x 15 +c 10 x x 15 +c 12 x x 15 +c 14 x x 15 cell0 (y 15 ) 22 c 15 x x 16 +c 1 x x 16 +c 3 x x 16 +c 5 x x 16 +c 7 x x 16 +c 9 x x 16 +c 11 x x 16 +c 13 x x 16 - 23 +c 14 x x 17 +c 0 x x 17 +c 2 x x 17 +c 4 x x 17 +c 6 x x 17 +c 8 x x 17 +c 10 x x 17 +c 12 x x 17 cell1 (y 17 ) 24 +c 13 x x 18 c 15 x x 18 +c 1 x x 18 +c 3 x x 18 +c 5 x x 18 +c 7 x x 18 +c 9 x x 18 +c 11 x x 18 - 25 +c 12 x x 19 +c 14 x x 19 +c 0 x x 19 +c 2 x x 19 +c 4 x x 19 +c 6 x x 19 +c 8 x x 19 +c 10 x x 19 cell2 (y 19 ) 26 +c 11 x x 20 +c 13 x x 20 c 15 x x 20 +c 1 x x 20 +c 3 x x 20 +c 5 x x 20 +c 7 x x 20 +c 9 x x 20 - 27 +c 10 x x 21 +c 12 x x 21 +c 14 x x 21 +c 0 x x 21 +c 2 x x 21 +c 4 x x 21 +c 6 x x 21 +c 8 x x 21 cell3 (y 21 ) 28 +c 9 x x 22 +c 11 x x 22 +c 13 x x 22 c 15 x x 22 +c 1 x x 22 +c 3 x x 22 +c 5 x x 22 +c 7 x x 22 - 29 +c 8 x x 23 +c 10 x x 23 +c 12 x x 23 +c 14 x x 23 +c 0 x x 23 +c 2 x x 23 +c 4 x x 23 +c 6 x x 23 cell4 (y 23 ) 30 +c 7 x x 24 +c 9 x x 24 +c 11 x x 24 +c 13 x x 24 +c 15 x x 24 +c 1 x x 24 +c 3 x x 24 +c 5 x x 24 - 31 +c 6 x x 25 +c 8 x x 25 +c 10 x x 25 +c 12 x x 25 +c 14 x x 25 +c 0 x x 25 +c 2 x x 25 +c 4 x x 25 cell5 (y 25 ) 32 +c 5 x x 26 +c 7 x x 26 +c 9 x x 26 +c 11 x x 26 +c 13 x x 26 +c 15 x x 26 +c 1 x x 26 +c 3 x x 26 - 33 +c 4 x x 27 +c 6 x x 27 +c 8 x x 27 +c 10 x x 27 +c 12 x x 27 +c 14 x x 27 +c 0 x x 27 +c 2 x x 27 cell6 (y 27 ) 34 +c 3 x x 28 +c 5 x x 28 +c 7 x x 28 +c 9 x x 28 +c 11 x x 28 +c 13 x x 28 +c 15 x x 28 +c 1 x x 28 - 35 +c 2 x x 29 +c 4 x x 29 +c 6 x x 29 +c 8 x x 29 +c 10 x x 29 +c 12 x x 29 +c 14 x x 29 +c 0 x x 29 cell7 (y 29 ) 36 +c 1 x x 30 +c 3 x x 30 +c 5 x x 30 +c 7 x x 30 +c 9 x x 30 +c 11 x x 30 +c 13 x x 30 c 15 x x 30 - 37 +c 0 x x 31 +c 2 x x 31 +c 4 x x 31 +c 6 x x 31 +c 8 x x 31 +c 10 x x 31 +c 12 x x 31 +c 14 x x 31 cell8 (y 31 ) data sequence input . . . x 2 , x 1 , x 0 coefficient sequence input . . . c 15 , c 0 . . . c 13 , c 14 , c 15 hsp43891 . . . y 19 , - ,y 17 , - , y 15 hsp43891
15 c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 01234567891011121314151617181920 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 x 17 x 18 0123 clk reset din0-8 dienb cin0-8 cienb adr0-2 df0 shadd dcm0-1 sum0-25 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 x 19 x 20 x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 30 x 31 x 32 x 33 x 34 x 35 x 36 x 37 45670 erase c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 c 15 c 14 c 13 c 12 c 11 c 10 1 y 15 y 17 y 19 y 21 y 31 y 33 y 23 y 25 y 27 y 29 senbl senbh figure 7. hsp43891 16-tap decimate-by-two fir filter timing; 30mhz in, 15mhz out hsp43891
16 absolute maximum ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output voltage . . . . . . . . . . . . . . . . .gnd -0.5v to v cc +0.5v maximum storage temperature. . . . . . . . . . . . . . . . -65 o c to 150 o c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 junction temperature plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c cpga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5 temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) mqfp package . . . . . . . . . . . . . . . . . . . . 47 n/a plcc package. . . . . . . . . . . . . . . . . . . . . 37 n/a cpga package . . . . . . . . . . . . . . . . . . . . 34.66 7.78 typical package power dissipation at 70 o c mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7w plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2w cpga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.88w gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17763 (plcc mqfp lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions min max units power supply current i ccop v cc = max, clk frequency 20mhz (notes 2, 4) - 140 ma standby power supply current i ccsb v cc = max (note 4) - 500 m a input leakage current i i v cc = max, input = 0v or v cc -10 10 m a output leakage current i o v cc = max, input = 0v or v cc -10 10 m a logical one input voltage v ih v cc = max 2.0 - v logical zero input voltage v il v cc = min - 0.8 v logical one output voltage v oh i oh = -400 m a, v cc = min 2.6 - v logical zero output voltage v ol i ol = 2ma, v cc = min - 0.4 v clock input high v ihc v cc = max 3.0 - v clock input low v ilc v cc = min - 0.8 v input capacitance plcc c in clk frequency 1mhz all measurements referenced to gnd, t a = 25 o c (note 3) -10pf cpga -15pf output capacitance plcc c out -10pf cpga -15pf notes: 2. operating supply current is proportional to frequency. typical rating is 7ma/mhz. 3. controlled via design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. 4. output load per test load circuit and c l = 40pf. hsp43891
17 test load circuit ac electrical speci?cations v cc = 5v, 5%, t a = 0 o c to 70 o c parameter symbol test conditions -20 (20mhz) -25 (25.6mhz) -30 (30mhz) units min max min max min max clock period t cp 50-39-33-ns clock low t cl 20-16-13-ns clock high t ch 20-16-13-ns input setup t is 16-14-13-ns input hold t ih 0-0-0-ns clk to coefficient output delay t odc -24-20-18ns output enable delay t oed -20-15-15ns output disable delay t odd note 5 - 20 - 15 - 15 ns clk to sum output delay t ods -27-25-21ns output rise t or note 5 - 6-6-6ns output fall t of note 5 - 6-6-6ns note: 5. controlled by design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. dut equivalent circuit 1.5v i ol i oh ? c l (note) includes stray and jig capacitance s 1 note: switch s 1 open for i ccsb and i ccop tests. hsp43891
18 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 waveforms figure 8. clock ac parameters note: input includes:din0-7, cin0-7, dienb, cienb, erase, re- set, dcm0-1, adr0-1, tcs, tcci, shadd figure 9. input setup and hold figure 10. sum0-25, cout0-8, output delays figure 11. rise and fall times figure 12. output enable, disable timing note: ac testing: inputs are driven at 3.0v for a logic 1 and 0.0v for a logic 0. input and output timing measurements are made at 1.5v for both a logic 1 and 0. clk is driven at 4.0v and 0v and measured at 2.0v. figure 13. ac testing input, output waveform t cl clk 2.0v 2.0v 2.0v t cp t ch t ih 0.0v clk 2.0v input ? 1.5v 1.5v 3.0v 0.0v 4.0v t is clk 1.5v t odc , t ods sum0-25 cout0-8 2.0v output t or t of 2.0 0.8 output 1.3v 1.7v 1.5v t oed 1.5v 1.5v enable t odd 1.5v 3.0v 0.0v input 1.5v device under test hsp43891

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