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| ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?d e t 3 9 d o 1 2 ? 2 1 3 5 ? f f q s p n 2 ?? eg??? ) g j q t * ! 2 9 1 . 2 0 2 9 1 . 3 [ j t p 0 j f d ! 2 1 2 2 9 . 4 ?]2 e ) t i b . 2 * |? .0b?z?] ?? ?@ ? 5 4 3 ?| a ? ? @}k ? ??? ? [ f q s p n 6 ^ ? ? e t 3 9 d o 1 2 ???|? ? | 7 5 ? ? i -0 - ?*e| j 3 d [ t n c v t u n 0? { > e t 3 9 d o 1 2 ?r0gi 6?u# g t n c v t ? s ?? h { > ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` b q d c |?? e s | hj?$0 ???hz ? e ??$0 l] ??r ^|? *? b?ee ;?$?z? ? ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` v ? 2 1 3 5 ? f f q s p n @ j? 5 3 6 7 ?| ? |n h t i b . 2 [:? t i b . 2 ! n b d ? f f q s p n @ -? a??? ??? ? t??? f q s p n y+ ) ??? 2 ? 1 * ? v 7? ?@ ?? [r 2 7 1 ??z n b d | ? ? ? @ 3 -?b|?| 7 5 ?? i?z t| ??vp?y@?? \ y $4 h ? , 3 6 dt?z 3 1 1 - 1 1 1 _v(k ? j 3 d [ t n c v t 0?r { ># ? - ? } 2 1 1 l i { [ 5 1 1 l i { ! j 3 d0gt ? { >[ m ?? , 6 / 6 w 1 ? ?+ *?? , 2 / 7 3 w ? , 6 / 6 w . 5 1 d ? , 9 6 d ? 9[ m t p q v? e t 3 9 d o 1 2 r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n ________________________________________________________________ maxim integrated products 1 sop 2 7 n.c. ad1 18v cc ad0 scl n.c. 3 6 sda gnd 4 5 ds28cn01 top view + ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` [ m|? ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ? g? rev 2; 11/09 ta5^ak ?t ?|iaa| -@? !i?|yei tg?? ?[i???4|? |l ^at ? ? % ? ? g?? e n b y j n ?>i|f? 2 1 9 1 1 ! 9 6 3 ! 2 3 5 : ! )?| *l * 2 1 9 1 1 ! 2 6 3 ! 2 3 5 : ! ) | *l * t 7 n b y j n ||a?6? d i j o b / n b y j n . j d / d p n k ?t ?vt + -,? ) q c * 0 o ] s p i t *e| v? u ! > ! rt? part temp range pin-package ds28cn01u-a00+ -40c to +85c 8 sop ds28cn01u-a00+t -40c to +85c 8 sop ?o ?+? 5?k ?t ?|" ? t n c v t 5 j o u f m ! d p s q /|* e t 3 9 d o 1 2 r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n 2 _______________________________________________________________________________________ k ?t ?vt absolute maximum ratings electrical characteristics (t a = -40c to +85c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground.........-0.5v to +6v maximum current on any pin ...........................................20ma operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-55c to +125c soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units supply voltage v cc 1.62 5.50 v standby current i ccs bus idle, v cc = +5.5v 5.5 a operating current i cca bus active at 400khz, v cc = +5.5v 500 a power-up wait time t poip (note 2) 5 s eeprom v cc 2.0v 10 programming time t prog v cc < 2.0v 45 ms programming current i prog v cc = +5.5v 1.2 ma at +25c 200,000 endurance (notes 3, 4, 5) n cy at +85c 50,000 data retention (notes 6, 7, 8) t dr at +85c 40 years sha-1 engine sha-1 computation time t csha see full version of the data sheet. ms sha-1 computation current i lcsha see full version of the data sheet. ma scl, sda, ad1, ad0 pins (notes 9, 10) v cc 2.0v -0.3 0.3 v cc low-level input voltage v il v cc < 2.0v -0.3 0.25 v cc v v cc 2.0v 0.7 v cc v ccmax + 0.3v high-level input voltage v ih v cc < 2.0v 0.8 v cc v ccmax + 0.3v v v cc 2.0v 0.05 v cc hysteresis of schmitt trigger inputs (note 2) v hys v cc < 2.0v 0.1 v cc v v cc 2.0v 0.4 low-level output voltage at 4ma sink current, open drain v ol v cc < 2.0v 0.2 v cc v e t 3 9 d o 1 2 note 1: specifications at -40c are guaranteed by design and characterization only and not production tested. note 2: guaranteed by design, characterization, and/or simulation only and not production tested. note 3: this specification is valid for each 8-byte memory row. note 4: write-cycle endurance is degraded as t a increases. note 5: not 100% production tested; guaranteed by reliability monitor sampling. note 6: data retention is degraded as t a increases. note 7: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. note 8: eeprom writes can become nonfunctional after the data retention time is exceeded. long-time storage at elevated tem- peratures is not recommended; the device can lose its write capability after 10 years at +125c or 40 years at +85c. note 9: all values are referred to v ih(min) and v il(max) levels. note 10: see figure 3. note 11: c b = total capacitance of one bus line in pf. if mixed with high-speed-mode devices, faster fall times according to i 2 c bus specification v2.1 are allowed. electrical characteristics (continued) (t a = -40c to +85c.) (note 1) r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n _______________________________________________________________________________________ 3 k ?t ?vt parameter symbol conditions min typ max units v cc 2.0v 20 + 0.1c b 250 output fall time from v ih(min) to v il(max) with a bus capacitance from 10pf to 400pf (notes 2, 11) t of v cc < 2.0v 20 + 0.1c b 300 ns pulse width of spikes that are suppressed by the input filter t sp (note 2) 50 ns input current with an input voltage between 0.1v cc and 0.9v ccmax i i (note 12) -10 +10 a input capacitance c i (note 2) 10 pf scl clock frequency f scl (note 13) 400 khz bus timeout t timeout cm bit = 1 (note 13) 25 75 ms hold-time (repeated) start condition; after this period, the first clock pulse is generated t hd:sta (note 14) 0.6 s v cc 2.7v 1.3 v cc 2.0v 1.5 low period of the scl clock (note 14) t low v cc < 2.0v 1.9 s high period of the scl clock t high (note 14) 0.6 s setup time for a repeated start condition t su:sta (note 14) 0.6 s v cc 2.7v 0.3 0.9 v cc 2.0v 0.3 1.1 data hold time (notes 15, 16) t hd:dat v cc < 2.0v 0.3 1.5 s data setup time t su:dat (notes 2, 14, 17) 100 ns setup time for stop condition t su:sto (note 14) 0.6 s bus free time between a stop and start condition t buf (note 14) 1.3 s capacitive load for each bus line c b (notes 2, 14) 400 pf e t 3 9 d o 1 2 note 12: the ds28cn01 does not obstruct the sda and scl lines if v cc is switched off. note 13: the minimum scl clock frequency is limited by the bus timeout feature. if the cm bit is 1 and scl stays at the same logic level or sda stays low for this interval, the ds28cn01 behaves as though it has sensed a stop condition. note 14: system requirement. note 15: the ds28cn01 provides a hold time of at least 300ns for the sda signal (referred to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 16: the master can provide a hold time of 0ns minimum when writing to the device. this 0ns minimum is guaranteed by design, characterization, and/or simulation only, and not production tested. note 17: a fast-mode i 2 c bus device can be used in a standard-mode i 2 c bus system, but the requirement t su:dat 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250 = 1250ns (according to the standard-mode i 2 c bus specification) before the scl line is released. r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n 4 _______________________________________________________________________________________ k ?t ?vt 1 ad0 2 ad1 3, 7 n.c. 4 gnd 5 sda 6 scl 8 v cc ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` .? e t 3 9 d o 1 2 r?r j 3 d 0 t n c v t { > 2 l ? t i b . 2 ?] f f q s p n @2 ?|? i? 1 vd ? , h0 - j 3 d { >2*e y+ t y+ ? 0g ? - s { >- j 3 d # y+$ ? t n c v t y+ y 5 ?3??[ m?? 2 7 e t 3 9 d o 1 2 {?4#? ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` h ?+= z e t 3 9 d o 1 2|v 7 ?0 - j 3 d 0 t n c v t r { > <? ?? e t 3 9 d o 1 2 |@ [ @ ?? y4|v p%? e ?p= z.g??l rsk ? t ?| w+ [vw+ ] j r0g { > r { >0 -k ?# ) t e b * [ ?g s ) t d m * ?r0g t e b [ t d m 5w6r#0 -? o? {uu??? 1y ?r0g t e b [ t d m ?? ?3 {u# | hr ?5 ' ? 5 t ? ? 52 x# ?*e y+k ?|r h -i 2 1 1 l c q t y+ -i 5 1 1 l c q t e t 3 9 d o 1 2 - ?+??d y? y+ #? ?k ?| h??c? ? {ck ?| h? {c <?0g| ha? ?? ? <?| h5- h e t 3 9 d o 1 2 ?- h electrical characteristics (continued) (t a = -40c to +85c.) (note 1) ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` [ m? [ m a ? h??r?[ m v? - h????-??? b \ 2 ; 1 ^|?? {? h o e t e b t d m t w d d h??r?[ m v? - h????-??? b \ 4 ; 3 ^|?? {? h o e t e b t d m t w d d ? { ??? j 3 d 0 t n c v t w6rk ?# ?[ m?0 - ? o? { w d d j 3 d 0 t n c v t r ?r? ?[ m?0 - ? o? { w d d ??r? e t 3 9 d o 1 2 r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n _______________________________________________________________________________________ 5 ds28cn01 i 2 c/smbus function control memory and sha-1 engine control mac comparator mac output buffer 8-byte write buffer 64-bit unique number sha-1 engine secret memory register page user eeprom 4 pages of 32 bytes scl v cc sda ad_ ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` 1 vd -?? 0 16 ? ? ?#]? 7 h?? y [#? h$c|-?? e t 3 9 d o 1 2 0b|-?? ed 2 -??5-?? 0 16 ?|] j e t 3 9 d o 1 2 -??| 4 ???? 2 1 2 c[ m b e 1 | ] ? ???? b 1 [ b 2 |? b e 2 v <? b 3 [ b 4 |? b e 1 [ b e 2 -2 {? h o e w d d t d m t t e b- 2 ?z??[ m ? ????|b b 1 ? b 4 ?$b[ m| ????? ?| h -?? 0 16 ?|" ?? ) s 0 w *?ck ? 16?? 1 ??k ? s- ? ?u- ? )vw+ y+ *?? 2 k ? s-- ??u ? )w+ y+ * 1 a6 msb 0 a5 1 a4 ad1 a3 7-bit slave address a2 a1 ad0 a0 r/w determines read or write 4-level pin states (see the slave address/direction byte section) d 2 / ! -?? ad1 a3 a2 ad0 a1 a0 gnd 0 0 gnd 0 0 v cc 0 1 v cc 0 1 scl 1 0 scl 1 0 sda 1 1 sda 1 1 - 2 / ! [ m? ???|b k ?t ?vt e t 3 9 d o 1 2 r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n 6 _______________________________________________________________________________________ sda scl idle 1C7 8 9 1C7 8 9 1C7 8 9 start condition stop condition repeated start slave address r/w ack ack data ack/ nack data msb first msb lsb msb lsb repeated if more bytes are transferred d 3 / ! j 3 d 0 t n c v t og ?d j 3 d 0 t n c v t og ??i# 9 c?k ?r ?? t d m <? # 7 ? t u b s u [ t u p q h@ ?? t u b s u [ t u p q h? .0 - t e b r| ?kk ?2 ?p+ ?e ?" ?i? ? ? ? ? bj ?# ?- ?|4[?k ?re .? ?#? ?3 t e b ????i t d m ? | t e b "$ ??5 t u b s u t t u p q hog? ? d 3 ?,. ? ed 4 # 9 t ; ?? t e b [ t d m 9% ] ?? ?3 t u b s u h ? ?- h ?rk ?r ??? t u b s u h t d m ? ?3 t e b - ?3"$???3 s? t u b s u h t u p q h ? ???- h? .|k ?r ??? t u p q h t d m ? ?3 t e b -??3"$? ?3 s ? t u p q h ? ? t u b s u h ? ? t u b s u 0??w+??|vw+|/ 3? ? ? i|@???(k ?r ?f ? ? -2'? ? t u b s u h-,?ir ?f ? a t?(d|k ?r? ? t u b s u h|? 0 ?| t u b s u h?5y ??| t u p q h k ??i t u b s u [ t u p q h?j t e b |"$? ? t d m ??3e .?s t d m ?3e .2 g| p a . [? . ) t d m ]? ? u i e ; e b u t d m ? ? u t v ; e b u l ed 4 * t e b k ??????i ??k ?b ? t? t d m t|? ?k ??$? {c h vw+r? ? ??; 9 t e b2?z? t d m ? ???| p a . )"c? u t v ; e b u , u s ed 4 * v?w+- h? t d m t ]? s t e b ?|k ???$ k ???i t d m t|? ??i ?? ??| t d m ? tt jks- hk ? ??| ? k ?t ?vt - hbj 0???||- h ?cu ??? b jg s ?? ? ?bj?$ | ? t- h?%bj ? te .3 t e b o???3@?b j ?? ?3e .*?? t e b ???|??3 p a ? . u t v ; e b u [ u i e ; e b u ? e? ?bj -- h?sk ? ? ?cu ??? bjg s ?? ? ?bj?$ | ? t bj ??%bj ? te .3 t e b o???3 @?bj ?? ?3e .*?? t e b ???|?? 3 p a ? . u t v ; e b u [ u i e ; e b u ? e? - h?bj i h ??i 7 y+ tw5 t i b . 2 [:u? t u??r f f q s p n vw+ - h? {c t ?k ?z?= z e t 3 9 d o 1 2? a t {c|? \ ? y ?rbj ?b|bj ? t? ?3e .' t e b ?? ?3.? ?l rsk ?t ?|| w + [vw+ ] j| e ? e t 3 9 d o 1 2 ybj|= z ??bj ? ?u? {ck ? ???w+? ?iuz | ??$b|bj ? t? ?3e . s t e b ?? ?3 tybj-- h {cu|k ?|" ? ?+?0b- h+? ?k ??? ? t u p q h k ?@ [ @ ? ?] j )t jd 5d 6 [- 3 *|.? ?l er s|k ?t ? w+ [vw+ ?] j y ? f f q s p n |vw+2 @t j- 4 ?- 2 4 ?|.g??l ers|k ?t ? e t 3 9 d o 1 2 r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n _______________________________________________________________________________________ 7 scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low d 4 / ! j 3 d 0 t n c v t ?d k ?t ?vt e t 3 9 d o 1 2 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` t i b . 2 ?] j ? t i b . 2 |? v?]2 e*e t i b . 2 a m%am -- o j t u ?6.g??l ers| k ?t ? ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` bg? t e b [ t d m ? o? e t 3 9 d o 1 2 | t e b 5 ' ? 5r? ? o? )l e ?o ?+? 5 *# ] ?3?? e t 3 9 d o 1 2 ?3 t d m +?r? )? ?1 *p% ? -20 - r? o? | ' ? 5 0 ? ? 5r tnt+rq? t d m ? o? s q |mc ? ? j 3 d *- h? w p m ? , 1 / 5 w ? ??a c 4 n b ? t n c v t *eg , 1 / 5 w ?? 5 n b |a? ??s ?+?1 *? e t 3 9 d o 1 2 ? w p m ? , 1 / 5 w ?ac? 5 n b ? z? v ? ?? o? |"c?? s q n j o > ) w d d . 1 / 5 w * 0 5 n b "m ?+?1? , 6 / 6 w ? o? "c?? 2 / 3 8 6 l d 7|| n j o j n v n s q n#, ?? o? "c?2 ?+ )? o *?1|$ ? = z ? j 3 d ;? o?1- 4 1 & ? 8 1 &| -? .?c ?? . t ] ."m#?? d c > 5 1 1 q g"m ? .y - 4 1 1 o t #?? .s"m?? ? \ ?|?? d c "m? ??? s q n b y > 4 1 1 o t 0 ) d c y m o ) 8 0 4 * *#??? 5 1 1 q g "m? o? ? 9 9 6 ? ? x? .?*2 5 1 1 q g |#??? 9 9 6 ? o? ? ?? , 6 / 6 w g| s q n j o ?p% ?j ? 1 e ?? \ ? ?+?1 |"c? o? ) n j o j n v n s q n# *m ? ? 4 1 1 o t |? .b|#??"? ??d 7?,| n b y j n v n m p b e n# ??i? o?1? , 5 w t ?? c?? 5 1 1 q g |"m #??#?? ?cu 4 1 1 q g ?8 ]s ?+? 1 *? ??1b|? o? ? e n j o j n v n s q n# r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n 8 _______________________________________________________________________________________ k ?t ?vt minimum r p ( ) load (pf) pullup voltage (v) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1200 600 1000 500 800 400 600 300 400 200 200 100 0 0 minimum r p maximum load at minimum r p fast mode d 7 / ! j 3 d y+|? o? ? n# e t 3 9 d o 1 2 r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n _______________________________________________________________________________________ 9 k ?t ?vt r p r p v cc c sda to additional devices scl v cc gnd sda scl ad1 ad0 v cc gnd ds28cn01 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?o ?+? 5 v? o v? i am s 8 sop u8+3 21-0036 ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` v?g? ??" | v?jpg? [ fdz ?? china.maxim-ic.com/packages ??@ v? i|| , $ t . ?-, s p i t ? v?d| -t :y4|?? oc v?d? v?? s p i t ?? e t 3 9 d o 1 2 r t i b . 2 [:| 2 l ? j 3 d 0 t n c v t ! f f q s p n k ?t ?vt n b y j n y n b y j n ?-2j|? \? 5' ? y ?? - n b y j n ? ?? \ . ??? \0| ? ??- t ? [ ?|z ? 10 _____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products n b y j n 5 n b y j n ! j o u f h s b u f e ! q s p e v d u t - ! j o d / |?* 0 6/07 1 4/09 2 11/09 3 n b y j n ? ?0 ? 9 4 3 9 g( ?v i 2 1 1 1 9 4 ? e? ?? 9 1 1 ! 9 2 1 ! 1 4 2 1 ? ?? 1 2 1 . 7 3 2 2 6 2 : : ^? 1 2 1 . 7 3 2 2 6 3 : : ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ?? ?% ??(k ???e ? ? ? "?t pgd y?|k ?t ? ]] ? f m f d u s j d b m ! d i b s b d u f s j t u j d t |?# ?* ? d n ! c j u ! > ! 2 h |
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