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LTC6410-6 1 64106fa features applications description low distortion, low noise differential if ampli er with con gurable input impedance the ltc ? 6410-6 is a low distortion, low noise differential if ampli? er with con? gurable input impedance designed for use in applications from dc to 1.4ghz. the LTC6410-6 has 6db of voltage gain. the LTC6410-6 is an excellent choice for interfacing active mixers to saw ? lters. it fea- tures an active input termination that allows a customized input impedance for an optimum interface to differential active mixers. this feature provides additional power gain because of the impedance conversion and improved noise performance when compared to traditional 50 interface circuits. the LTC6410-6 drives a differential 50 load directly with low distortion, which is suitable for driving saw ? lters and other 50 signal chain blocks. the LTC6410-6 operates on 3v or 5v supplies. it comes in a compact 16-lead 3mm 3mm qfn package and operates over a C40c to 85c temperature range. post mixer gain block (140mhz if) n 1.4ghz C3db bandwidth n fixed voltage gain of 6db (50 system) n con? gurable input impedance allows: simple interface to active mixers improved noise performance n wide 2.8v to 5.25v supply range n low distortion: 36dbm oip3 (70mhz) 33dbm oip3 (140mhz) 31dbm oip3 (300mhz) n low noise: 11db nf (50 z in ) 8db nf (200 z in ) n differential inputs and outputs n self-biasing inputs/outputs n shutdown mode n minimal support circuitry required n 16-lead 3mm 3mm 0.8mm qfn package n post-mixer gain block n saw filter interface/buffering n differential if signal chain gain block n differential line driver/receiver 2-tone spectrum analyzer plot l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. typical application 0.1f 12pf 12pf 0.1f 680pf 24nh 82nh system oip3 = 29dbm at 1900mhz system nf = 15db at 1900mhz 82nh 24nh lt5527 mixer 1760mhz lo LTC6410-6 64106 ta01a Cterm Cin +in +term Cout shdn v bias v + v C 5v 5v +out 18pf 18pf frequency (mhz) 130 output power (dbm) C40 C20 0 146 64106 ta01b C60 C80 C50 C30 C10 C70 C90 C100 134 132 138 136 142 144 148 140 150
LTC6410-6 2 64106fa absolute maximum ratings total supply voltage (v + to v ? ) ................................5.5v ampli? er input current (dc) (+in, ?in, +term, ?term) .............................10ma ampli? er input power (ac) (+in, ?in, +term, ?term) .............................18dbm input current (v bias , shdn n s n s s n shdn nn s nn s s s n nn nd nn d sd s ndns n ns d d s nd d d snd ds d nd snn s s nd sn sh s nd d s nd n s nnn dhss dnsh nd n dsn nn d d d n d d d n d dsn s shdn n n
LTC6410-6 3 64106fa 3v dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, shdn = 2v, +in is shorted to +term, Cin is shorted to Cterm, v bias = 1.5v, +in = Cin = 1.5v, input source resistance (r s ) is 25 on each input (50 differential), r l = 50 from +out to Cout, unless otherwise noted. v bias is de? ned as the voltage on the v bias pin. v outcm is de? ned as (+out + Cout)/2. v incm is de? ned as (+in + Cin)/2. v indiff is de? ned as (+in C Cin). v outdiff is de? ned as (+out C Cout). see dc test circuit schematic. symbol parameter conditions min typ max units tc v os input offset voltage drift l C0.3 v/c v osincm common mode offset voltage v outcm C v incm l C40 C50 13 40 50 mv mv a v internal voltage gain 2.7 v/v i vrmin input common mode voltage range, (min) l 1.0 v i vrmax input common mode voltage range, (max) l 2.0 v r indiff differential input resistance v indiff = 100mv (note 4) l 40 30 58 80 100 x indiff differential input reactance f = 100mhz 1 pf r incm input common mode resistance 1000 cmrr common mode rejection ratio v bias = 1.5v, +in = Cin = 1v to 2v, ( 6 v outdiff /gain) l 45 60 db r odiff differential output resistance v outdiff = 100mv (note 4) l 17 13 22 38 47 x outdiff differential output reactance f = 100mhz 10 nh r outcm common mode output resistance 7 bias voltage control (v bias pin) g cm common mode gain v bias = 1.2v to 1.8v (+in and Cin ? oating), 6 v outcm /(0.6v) l 0.7 0.6 0.86 1.0 1.0 v/v v/v v ocmmin output common mode voltage adjustment range, (min) l 1.0 1.2 v v ocmmax output common mode voltage adjustment range, (max) l 1.8 2.0 v v oscm output common mode offset voltage v outcm C v bias l C200 C400 100 300 400 mv mv r vocm v bias input resistance l 2.4 2.0 3.0 3.6 4.0 k k c vbias v bias input capacitance 3pf shdn pin v il shdn input low voltage l 0.8 1.0 v v ih shdn input high voltage l 1.8 2 v i il shdn input low current shdn = 0.8v l C200 C85 0 a i ih shdn input high current shdn = 2v l C150 C30 0 a power supply v s operating range l 2.8 5.25 v i s supply current l 104 130 140 ma ma i s shdn supply current in shutdown shdn = 0.8v l 35 ma psrr power supply rejection ratio v + = 2.8v to 5.25v, v bias = +in = Cin = v + /2 l 73 100 db
LTC6410-6 4 64106fa the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 5v, v C = 0v, shdn = 3v, +in is shorted to +term, Cin is shorted to Cterm, v incm = v bias = 2.5v, +in = Cin = 2.5v, input source resistance (r s ) is 25 on each input (50 differential), r l = 50 from +out to Cout, unless otherwise noted. v bias is de? ned as the voltage on thev bias pin. v outcm is de? ned as (+out + Cout)/2. v incm is de? ned as (+in + Cin)/2. v indiff is de? ned as (+in C Cin). v outdiff is de? ned as (+out C Cout). see dc test circuit schematic. 5v dc electrical characteristics symbol parameter conditions min typ max units g diff differential gain (low frequency s21) v in = 0.2v l 5 4.7 6.1 6.7 7.0 db db v swingdiff differential output voltage swing v outdiff , v in = 4v l 4.1 3.5 4.8 v p-p v p-p v swingmin output swing low single-ended +out, Cout, v in = 4v l 1.1 1.4 1.6 v v v swingmax output swing high single-ended +out, Cout, v in = 4v l 3.2 3.0 3.5 v v i s supply current l 125 150 160 ma ma shdn pin v il shdn input low voltage l 1.8 2.0 v v ih shdn input high voltage l 2.8 3 v i il shdn input low current shdn = 1.8v l C300 C110 0 a i ih shdn input high current shdn = 3v l C200 C60 0 a ac electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, shdn = 2v, +in is shorted to +term, Cin is shorted to Cterm, v incm = v bias = 1.5v, input source resistance (r s ) is 25 on each input (50 differential), r l = 50 from +out to Cout, +in and Cin are ac-coupled, unless otherwise noted. v bias is de? ned as the voltage on thev bias pin. v outcm is de? ned as (+out + Cout)/2. v incm is de? ned as (+in + Cin)/2. v indiff is de? ned as (+in C Cin). v outdiff is de? ned as (+out C Cout). symbol parameter conditions min typ max units C3dbbw C3db bandwidth v indiff = C10dbm 1 1.4 ghz 0.1dbbw bandwidth for 0.1db flatness v indiff = C10dbm 150 mhz 0.5dbbw bandwidth for 0.5db flatness v indiff = C10dbm 300 mhz sr slew rate 1.5 v/ns t s 1% settling time 1% settling for a 1v p-p v outdiff step 3 ns t on turn-on time shdn = 0v to 3v, +out and Cout within 10% of final values 30 ns t off turn-off time shdn = 3v to 0v, +out and Cout within 10% of final values 30 ns common mode voltage control (v bias pin) C3dbbwcm common mode small-signal C3db bandwidth 0.2v p-p at v bias , measured v outcm 1 ghz srcm common mode slew rate 100 v/s noise/harmonic performance input/output characteristics 10mhz signal hd2 second harmonic distortion v outdiff = 0dbm C85 dbc hd3 third harmonic distortion v outdiff = 0dbm C71 dbc
LTC6410-6 5 64106fa ac electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, shdn = 2v, +in is shorted to +term, Cin is shorted to Cterm, v incm = v bias = 1.5v, input source resistance (r s ) is 25 on each input (50 differential), r l = 50 from +out to Cout, +in and Cin are ac-coupled, unless otherwise noted. v bias is de? ned as the voltage on thev bias pin. v outcm is de? ned as (+out + Cout)/2. v incm is de? ned as (+in + Cin)/2. v indiff is de? ned as (+in C Cin). v outdiff is de? ned as (+out C Cout). symbol parameter conditions min typ max units im3 third order intermodulated distortion f1 = 9.5mhz, f2 = 10.5mhz, v outdiff = 0dbm/tone C72 dbc f1 = 9.5mhz, f2 = 10.5mhz, v outdiff = C5dbm/tone C81 dbc f1 = 9.5mhz, f2 = 10.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v C66 dbc oip3 output third-order intercept f1 = 9.5mhz, f2 = 10.5mhz, v outdiff = 0dbm/tone 36 dbm f1 = 9.5mhz, f2 = 10.5mhz, v outdiff = C5dbm/tone 36 dbm f1 = 9.5mhz, f2 = 10.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v 33 dbm p1db output 1db compression point 12.8 dbm nf noise figure z in = 50 (note 5) z in = 200 11 8 db db 70mhz signal hd2 second harmonic distortion v outdiff = 0dbm C85 dbc hd3 third harmonic distortion v outdiff = 0dbm C69 dbc im3 third order intermodulated distortion f1 = 69.5mhz, f2 = 70.5mhz, v outdiff = 0dbm/tone C72 dbc f1 = 69.5mhz, f2 = 70.5mhz, v outdiff = C5dbm/tone C79 dbc f1 = 69.5mhz, f2 = 70.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v C72 dbc oip3 output third-order intercept f1 = 69.5mhz, f2 = 70.5mhz, v outdiff = 0dbm/tone 36 dbm f1 = 69.5mhz, f2 = 70.5mhz, v outdiff = C5dbm/tone 35 dbm f1 = 69.5mhz, f2 = 70.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v 36 dbm p1db output 1db compression point 12.8 dbm nf noise figure z in = 50 (note 5) z in = 200 11 8 db db 140mhz signal hd2 second harmonic distortion v outdiff = 0dbm C80 dbc hd3 third harmonic distortion v outdiff = 0dbm C62 dbc im3 third order intermodulated distortion f1 = 139.5mhz, f2 = 140.5mhz, v outdiff = 0dbm/tone C62 dbc f1 = 139.5mhz, f2 = 140.5mhz, v outdiff = C5dbm/tone C70 dbc f1 = 139.5mhz, f2 = 140.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v C66 dbc f1 = 130mhz, f2 = 150mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v C66 C56 dbc oip3 output third-order intercept f1 = 139.5mhz, f2 = 140.5mhz, v outdiff = 0dbm/tone 31 dbm f1 = 139.5mhz, f2 = 140.5mhz, v outdiff = C5dbm/tone 30 dbm f1 = 139.5mhz, f2 = 140.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v 33 dbm f1 = 130mhz, f2 = 150mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v 28 33 dbm p1db output 1db compression point 12.8 dbm
LTC6410-6 6 64106fa ac electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, shdn = 2v, +in is shorted to +term, Cin is shorted to Cterm, v incm = v bias = 1.5v, input source resistance (r s ) is 25 on each input (50 differential), r l = 50 from +out to Cout, +in and Cin are ac-coupled, unless otherwise noted. v bias is de? ned as the voltage on thev bias pin. v outcm is de? ned as (+out + Cout)/2. v incm is de? ned as (+in + Cin)/2. v indiff is de? ned as (+in C Cin). v outdiff is de? ned as (+out C Cout). note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6410c-6/ltc6410i-6 is guaranteed functional over the operating temperature range of C40c to 85c. note 3: the ltc6410c-6 is guaranteed to meet speci? ed performance from 0c to 70c. it is designed, characterized and expected to meet speci? ed performance from C40c and 85c but is not tested or qa symbol parameter conditions min typ max units nf noise figure z in = 50 (note 5) z in = 200 11 7 db db 240mhz signal hd2 second harmonic distortion v outdiff = 0dbm C66 dbc hd3 third harmonic distortion v outdiff = 0dbm C52 dbc im3 third order intermodulated distortion f1 = 239.5mhz, f2 = 240.5mhz, v outdiff = 0dbm/tone C54 dbc f1 = 239.5mhz, f2 = 240.5mhz, v outdiff = C5dbm/tone C63 dbc f1 = 239.5mhz, f2 = 240.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v C64 dbc oip3 output third-order intercept f1 = 239.5mhz, f2 = 240.5mhz, v outdiff = 0dbm/tone 27 dbm f1 = 239.5mhz, f2 = 240.5mhz, v outdiff = C5dbm/tone 27 dbm f1 = 239.5mhz, f2 = 240.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v 32 dbm p1db output 1db compression point 12.8 dbm nf noise figure z in = 50 (note 5) z in = 200 11 8 db db 380mhz signal hd2 second harmonic distortion v outdiff = 0dbm C57 dbc hd3 third harmonic distortion v outdiff = 0dbm C45 dbc im3 third order intermodulated distortion f1 = 379.5mhz, f2 = 380.5mhz, v outdiff = 0dbm/tone C51 dbc f1 = 379.5mhz, f2 = 380.5mhz, v outdiff = C5dbm/tone C64 dbc f1 = 379.5mhz, f2 = 380.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v C60 dbc oip3 output third-order intercept f1 = 379.5mhz, f2 = 380.5mhz, v outdiff = 0dbm/tone 26 dbm f1 = 379.5mhz, f2 = 380.5mhz, v outdiff = C5dbm/tone 27 dbm f1 = 379.5mhz, f2 = 380.5mhz, v outdiff = 0dbm/tone, v cc = 5v, v bias = 2.5v, shdn = 3v 30 dbm p1db output 1db compression point 10.8 dbm nf noise figure z in = 50 (note 5) z in = 200 12 8 db db sampled at these temperatures. the lt6410i-6 is guaranteed to meet speci? ed performance from C40c to 85c. note 4: this parameter is pulse tested. note 5: e n can be calculated from z in = 50 nf with the formula: e n = (10 nf 10 ?1)4kt50 where k = boltzmanns constant and t = absolute temperature
LTC6410-6 7 64106fa typical performance characteristics output third order intercept vs frequency third order intermodulation distortion vs frequency vs power third order intermodulation distortion vs temperature output 1db compression vs frequency output third order intercept vs frequency output 1db compression vs frequency distortion vs common mode voltage output third order intercept vs frequency (z in = 200 ) third order intermodulation distortion vs frequency vs power (z in = 200 ) frequency (mhz) 0 oip3 (dbm) 32 34 36 400 64106 g01 30 28 22 100 200 300 50 150 250 350 26 24 40 38 v + = 3v v C = 0v z in = 50 r l = 50 v bias = 1.5v p out = 0dbm frequency (mhz) 0 oip3 (dbm) 32 34 36 400 64106 g02 30 28 22 100 200 300 50 150 250 350 26 24 38 v + = 3v v C = 0v z in = 200 r l = 50 v bias = 1.5v p out = 0dbm output power (dbm) C5 C100 third order imd (dbc) C90 C70 C60 C50 0 C30 C2.5 0 64106 g03 C80 C20 C10 C40 2.5 5 380mhz 240mhz 30mhz 10mhz 70mhz 140mhz v + = 3v v C = 0v z in = 50 r l = 50 output power (dbm) C5 C90 third order imd (dbc) C70 C60 C50 0 C30 C2.5 0 64106 g04 C80 C20 C10 C40 2.5 5 380mhz 10mhz v + = 3v v C = 0v z in = 200 r l = 50 v bias = 1.5v 240mhz 140mhz 70mhz 30mhz temperature (c) C50 third order imd (dbc) C60.0 C55.0 150 64106 g05 C65.0 C70.0 0 50 100 C25 25 75 125 C50.0 C62.5 C57.5 C67.5 C52.5 v + = 3v v C = 0v z in = 50 r l = 50 freq = 139.5mhz, 140.5mhz p out = 0dbm v bias = 1.5v frequency (mhz) 0 p1db compression (dbm) 15 16 17 400 64106 g06 14 13 10 100 200 300 50 150 250 350 12 11 19 18 z in = 50 v + = 3v v C = 0v v bias = 1.5v frequency (mhz) 0 oip3 (dbm) 34 36 38 300 64106 g07 32 30 100 200 50 350 150 250 400 28 26 40 v + = 5v v C = 0v z in = 50 r l = 50 v bias = 2.5v p out = 0dbm frequency (mhz) 0 p1db compression (dbm) 15 16 17 400 64106 g08 14 13 10 100 200 300 50 150 250 350 12 11 19 18 v + = 5v v C = 0v v bias = 2.5v v bias (v) 1.2 oip3 (dbm) 15 20 25 1.5 1.7 64106 g09 10 5 0 1.3 1.4 1.6 30 35 40 1.8 v + = 3v v C = 0v z in = 50 r l = 50 freq = 139.5mhz, 140mhz p out = 0dbm
LTC6410-6 8 64106fa typical performance characteristics differential input return loss vs frequency on a smith chart (s11) small-signal transient large-signal transient overdrive recovery differential output return loss vs frequency on a smith chart (s22) differential gain vs frequency (s21) differential input return loss vs frequency (s11) differential output return loss vs frequency (s22) differential reverse isolation vs frequency (s12) frequency (mhz) C4 differential gain (db) 8 10 C6 C8 6 0 4 2 C2 1 100 1000 64106 g10 C10 10 v + = 3v v C = 0v z in = 50 frequency (mhz) C10 differential input return loss (db) 0 C15 C20 C5 1 100 1000 64106 g11 C25 10 v + = 3v v C = 0v z in = 50 frequency (mhz) C10 differential output return loss (db) 0 C15 C20 C5 1 100 1000 64106 g12 C25 10 v + = 3v v C = 0v z in = 50 frequency (mhz) C35 differential reverse isolation (db) C5 0 C40 C45 C10 C25 C15 C20 C30 1 100 1000 64106 g13 C50 10 v + = 3v v C = 0v z in = 50 1mhz 64106 g14 freq = 1mhz to 2ghz v + = 3v v C = 0v 1ghz 100mhz 64106 g15 1ghz freq = 1mhz to 2ghz v + = 3v v C = 0v 100mhz 1mhz 1.58 1.54 1.50 output voltage (v) 1.46 1.42 0 2.5 5 7.5 time (ns) 64106 g16 10 15 1.9 1.7 1.5 output voltage (v) 1.3 1.1 0 2.5 5 7.5 time (ns) 64106 g17 10 15 2.3 1.9 1.5 output voltage (v) 1.1 0.7 0 5 10 15 time (ns) 64106 g18 20 25
LTC6410-6 9 64106fa typical performance characteristics noise figure vs frequency vs z in turn-on time turn-off time spectrum analyzer 2-tone group delay and phase vs frequency cmrr vs frequency dc test circuit schematic frequency (mhz) 10 0 noise figure (db) 5.0 10.0 15.0 20.0 100 1000 64106 g19 25.0 2.5 7.5 12.5 17.5 22.5 v + = 3v v C = 0v z in = 50 z in = 100 z in = 400 z in = 200 2.0 1.5 1.0 0.5 0 0 100 200 time (ns) 64106 g20 300 400 500 2 0 voltage (v) C2 Cout +out shdn 2.0 1.5 1.0 0.5 0 0 0 100 200 time (ns) 64106 g21 300 400 500 2 voltage (v) C2 Cout +out shdn 0 10 20 30 40 50 output power (dbm) 60 70 80 90 100 67.5 68.5 69.5 70.5 frequency (mhz) 71.5 72.5 64106 g22 frequency (mhz) 10 group delay (ns) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 phase (deg) 90 45 0 C45 C90 C135 C180 C225 C270 C315 C360 100 1000 10000 64106 g23 group delay phase v + = 3v v C = 0v z in = 50 frequency (mhz) cmrr (db) 100 90 80 70 60 50 40 30 20 10 0 1 100 1000 10000 64106 g24 10 v + = 3v v C = 0v z in = 50 r l = 50 LTC6410-6 64106 tc Cterm Cin +in Cin +in +term Cout v + v + v + v + 3 5 8 10 v C v C v C v C 1 4 9 12 v + v C +out 7 6 Cout +out v outdiff = +out C Cout v outcm = +out + Cout 2 shdn v bias 13 14 15 16 11 2 shdn v bias 25 25 v indiff = +in C Cin v incm = +in + Cin 2
LTC6410-6 10 64106fa pin functions v C (pins 1, 4, 9, 12, 17): negative power supply (normally tied to ground). all 5 pins must be tied to the same voltage. v C maybe tied to a voltage other than ground as long as the voltage between v + and v C is 2.8v to 5.5v. if the v C pins are not tied to ground, bypass each with 680pf and 0.1f capacitors as close to the package as possible. v bias (pin 2): this pin sets the input and output com- mon mode voltage by driving the +in and Cin through a buffer with a high output resistance of 1k. if the part is ac-coupled at the input, the v bias will set the v incm and therefore the v outcm voltage. if the part is dc-coupled at the input, v bias should be left ? oating. internal resistors bias v bias to 1.4v on a 3v supply. v + (pins 3, 5, 8, 10): positive power supply. all 4 pins must be tied to the same voltage. split supplies are pos- sible as long as the voltage between v + and v C is 2.8v to 5.5v. bypass capacitors of 680pf and 0.1f as close to the part as possible should be used between supplies. +out, Cout (pins 6, 7): outputs. these pins each have internal series termination resistors forming a differential output resistance. shdn (pin 11): this pin is internally pulled high by a typi- cally 30k resistor to v + . by pulling this pin low the supply current will be reduced to typically 3ma. see dc electrical characteristics table for the speci? c logic levels. Cterm (pin 13): negative input termination. when tied directly to Cin, it provides an active 50 differential ter- mination when +term is also tied directly to +in. Cin (pin 14): negative input. this pin is normally tied to Cterm, the input termination pin. if ac-coupled, this pin will self bias by v bias . +in (pin 15): positive input. this pin is normally tied to +term, the input termination pin. if ac-coupled, this pin will self bias by v bias . +term (pin 16): positive input termination. when tied directly to +in, it provides an active 50 differential ter- mination when Cterm is also tied directly to Cin. exposed pad (pin 17): v C . the exposed pad must be soldered to the pcb metal. block diagram 64106 bd Cin +in 1k 1k 6.4k v + v C v bias r ext (opt) r ext (opt) c ext (opt) c ext (opt) r o 11 r o 11 Cout +out 5.7k r t 110 r t 110 + C + C +term Cin +in 0.1f Cterm +1 a v = 2.7v/v
LTC6410-6 11 64106fa applications information introduction the LTC6410-6 is a low noise differential high speed ampli? er. by default, the LTC6410-6 has 6db voltage gain and is designed to operate with 50 differential input and output impedances. by changing (r ext ), alternative con- ? gurations provide input resistances of up to 400, with correspondingly lower noise ? gure and higher power gain. the block diagram shows the basic circuit along with key external components while table 1 provides con? guration information. if the input is ac-coupled, the v bias pin sets the input common mode voltage and therefore the output common mode voltage. input impedance LTC6410-6 has been designed with very ? exible input termination circuitry. by default, with the termination pins connected directly to the inputs, the input impedance is 58, see the block diagram. internally, there is 110 between each input and the opposite output (r t ). divid- ing the resistor by the internal noise gain of 2.7 + 1 = 3.7, 29.5 input impedance is created (59 differential ). in parallel with the 2k common mode resistance, a total of 58 differential input impedance is achieved. this method of termination is used to provide lower noise ? gure through the use of feedback which reduces the effective noise of the termination resistor. by adding additional resistance in series with the termination pins, higher input impedances can be obtained (see table 1). the optimum impedance for minimizing the noise ? gure of the LTC6410-6 is close to 400. because the ampli? er is inherently a voltage ampli? er, the difference between the impedance at the input and the output adds additional power gain as can be seen in table 1. these higher impedance levels can be useful in interfacing with active mixers which can have output impedance of 400 and beyond. input and output common mode bias the LTC6410-6 is internally self-biased through the v bias pin (see the block diagram). therefore the LTC6410-6 can be ac-coupled with no external biasing circuitry. the output will have approximately the same common mode voltage as the input. in the case of a dc-coupled input connection, the input dc common mode voltage will also set the output com- mon mode voltage. note that a voltage divider is formed between the v bias buffer output and the dc input source impedance. the v bias pin has an internal voltage divider which will self bias to approximately 1.4v on a 3v supply (0.47 ? v supply ). an external capacitor of 0.1f to ground is recommended to bypass the pin. the resistance of the pin is 3k. see distortion vs common mode graph. for increased common mode accuracy, the +term and Cterm pins can be ac-coupled to the inputs with capaci- tors (c ext ). this coupling prevents the feedback from the termination resistance from creating additional dc com- mon mode voltage error. the g cm and v oscm of the dc electrical characteristics table re? ect the less accurate dc-coupled scenario. the termination inputs are part of a high speed feedback loop. the physical length of the termination loop (r ext and c ext ) must be minimized to maintain stability and minimize gain peaking. gain internally, the LTC6410-6 has a voltage gain of 2.7v/v. the default source and load resistances in most of the data sheet are assumed to be 50 differential. due to the input and output resistance of the LTC6410-6 being 58 and 22 respectively, the overall voltage gain in a 50 system is 6db (2v/v). other source and load resistances will produce different gains due to the resistive dividers. figure 1 is a system diagram for calculating gain. figure 1 r in 64106 f01 r s r load LTC6410-6 r out 22 v s
LTC6410-6 12 64106fa applications information therefore the differential voltage gain can be calculated as follows: voltage gain = 2? r in r in + r s ? 2.7 ? r l r l + r out the following is an example of the 50 gain calculation: voltage gain = 2? 58 58+50 ? 2.7 ? 50 50 + 22 = 2.0v/v = 6.0db the part also can be used with different input impedances providing no additional voltage gain, but a higher power gain. for example, the calculation for a 100 input impedance shows the effect of an impedance conversion. the voltage gain is calculated as follows: voltage gain = 2? 83 83+100 ? 2.7 ? 50 50 + 22 = 1.7v/v = 4.6db however the power gain is: power g a in = 2? 83 83+100 ? 2.7 ? 50 50 + 22 ? 2 2 = 5.8mw/mw = 7.6db output impedance the LTC6410-6 is designed to drive a differential load of 50 with a total differential output resistance of 22. while the LTC6410-6 can source and sink approximately 50ma, large dc output current should be avoided. to test the part on traditional 50 test equipment, ac coupling or balun transformers (or both) may be necessary at the input and output. supply rails inductance in the supply path can severely effect the per- formance of the LTC6410-6. therefore it is recommended that low inductance bypass capacitors are installed very close to the part. 680pf and 0.1f sized capacitors are recommended. additionally, the exposed pad of the part must be connected to v C for low inductance and low thermal resistance. failure to provide a low impedance supply at high frequencies can cause oscillations and increased distortion. shdn the shdn pin self-biases to v + through a 30k resistor. the pin must be pulled below 0.8v in order to shut down the part. applications circuits the graphs on the following page are examples of the four differential input resistances used on the dc1103a demo board with balun transformers for interfacing with the 50 single-ended measurement equipment. table 1. input impedance differential source resistance ( ) (r s ) external termination resistor ( ) (r ext ) effective differential input impedance ( ) (r in ) differential load resistance ( ) output resistance ( ) power gain (db) voltage gain (source and load resistance as stated (v/v) nf at 10mhz (db) 50 0 58 50 22 6.0 2.0 11 100 49.9 83 50 22 7.6 1.7 9 200 249 177 50 22 10.9 1.8 7 400 750 377 50 22 14.2 1.8 6 2000 open 2000 50 22 21.5 1.9 C
LTC6410-6 13 64106fa applications information z in = 200 , t1 = wbc4-14l, t2 = etc1-1-13 z in = 400 , t1 = wbc8-1l, t2 = etc1-1-13 z in = 50 , t1 = etc1-1-13, t2 = etc1-1-13 z in = 100 , t1 = wbc2-1tl, t2 = etc1-1-13 0.1f z in = 50 in out 64106 ta03a t1 0.1f 1:1 t2 1:1 Cin Cterm +in Cout +out +term LTC6410-6 0.1f 49.9 49.9 z in = 100 in out 64106 ta03a t1 0.1f 1:2 t2 1:1 Cin Cterm +in Cout +out +term LTC6410-6 frequency (mhz) 10 C15 gain and noise figure (db) C5 5 100 1000 10000 64106 ta02b C35 C25 C45 25 15 noise figure s21 s22 s11 s12 z in = 50 v cc = 3v frequency (mhz) 10 C15 gain and noise figure (db) C5 5 100 1000 10000 64106 ta03b C35 C25 C45 25 15 noise figure s21 s22 s11 s12 z in = 100 v cc = 3v 0.1f 249 249 z in = 200 in out 64106 ta04a t1 0.1f 1:4 t2 1:1 Cin Cterm +in Cout +out +term LTC6410-6 0.1f 750 750 z in = 400 in out 64106 ta05a t1 0.1f 1:8 t2 1:1 Cin Cterm +in Cout +out +term LTC6410-6 frequency (mhz) 10 C15 gain and noise figure (db) C5 5 100 1000 10000 64106 ta04b C35 C25 C45 25 15 noise figure s21 s22 s11 s12 z in = 200 v + = 3v v C = 0v frequency (mhz) 10 C15 gain and noise figure (db) C5 5 100 1000 10000 64106 ta05b C35 C25 C45 25 15 noise figure s21 s22 s11 s12 z in = 400 v + = 3v v C = 0v
LTC6410-6 14 64106fa applications information demoboard dc1103a top silkscreen typical application the schematic above shows a typical signal chain applica- tion with the LTC6410-6 in combination with a 140mhz center frequency 24mhz bandwidth saw ? lter. without the LTC6410-6, the attenuation of the saw would be C11.5db. the networks between the LTC6410-6 and the saw ? lter, and after the saw ? lter are for proper impedance matching. saw filter application saw filter application the differential output of the LTC6410-6 allows differential driving of the saw ? lter without the need for a transformer. the differential nature of the LTC6410-6 allows for ease of use in differential signal chains, and may reduce the need for transformers. frequency (mhz) 90 s21 (db) C40 C20 0 170 64106 ta08 C60 C50 C30 C10 C70 110 100 130 120 150 160 180 140 190 Cterm Cin +in +term Cout v + v C +out 0.1f 0.1f 12.4 15pf 47nh *coilcraft 0805cs LTC6410-6 64106 ta07 47nh* 120nh* 3v 12.4 15pf sawtek 854923
LTC6410-6 15 64106fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) 3.00 p 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 p 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 bottom viewexposed pad 1.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 1 pin 1 notch r = 0.20 typ or 0.25 s 45 o chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 p 0.05 3.50 p 0.05 0.70 p 0.05 0.00 C 0.05 (ud16) qfn 0904 0.25 p 0.05 0.50 bsc package outline
LTC6410-6 16 64106fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0908 rev a ? printed in usa related parts typical application part number description comments lt1993-2 800mhz differential ampli? er/adc driver a v = 2v/v, nf = 12.3db, oip3 = 38dbm at 70mhz lt1993-4 900mhz differential ampli? er/adc driver a v = 4v/v, nf = 14.5db, oip3 = 40dbm at 70mhz lt1993-10 700mhz differential ampli? er/adc driver a v = 10v/v, nf = 12.7db, oip3 = 40dbm at 70mhz lt5514 ultralow distortion if ampli? er/adc driver digitally controlled gain output ip3 47dbm at 100mhz lt5522 600mhz to 2.7ghz high signal level downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 single-ended rf and lo ports, r out = 400 lt5524 low power, low distortion adc driver with digitally programmable gain 450mhz bandwidth, 40dbm oip3, 4.5db to 27db gain control lt5525 high linearity, low power downconverting mixer single-ended 50 rf and lo ports, 17.6dbm iip3 at 1900mhz, i cc = 28ma lt5526 high linearity, low power downconverting mixer 3v to 5.3v supply, 16.5dbm iip3, 100khz to 2ghz rf, nf = 11db, i cc = 28ma, C65dbm lo-rf leakage lt5527 400mhz to 3.7ghz high signal level downconverting mixer cg = 2.3db at 1900mhz, iip3 = 23.5dbm at 1900mhz, 440mw, r out = 415 lt5557 400mhz to 3.8ghz high signal level downconverting mixer cg = 2.9db at 1950mhz, iip3 = 24.7dbm at 1950mhz, 300mw, r out = 560 ltc6400-20 1.8ghz low noise, low distortion adc driver for 300mhz if a v = 20db, z in = 200, i s(max) = 105ma at 25c ltc6401-20 1.4ghz low noise, low distortion adc driver for 140mhz if a v = 20db, z in = 200, i s(max) = 62ma at 25c lt6402-6 300mhz differential ampli? er/adc driver a v = 6db, e n = 3.8nv/ hz at 20mhz, 150mw lt6402-12 300mhz differential ampli? er/adc driver a v = 12db, e n = 2.6nv/ hz at 20mhz, 150mw lt6402-20 300mhz differential ampli? er/adc driver a v = 20db, e n = 1.9nv/ hz at 20mhz, 150mw lt6411 650mhz differential adc driver/dual selectable gain ampli? er 3300v/s slew rate, 16ma current consumption, selectable gain: a v = C1, 1, 2 demoboard dc1103a schematic v C v C shdn r6 0 r16 10 LTC6410-6 r8 0 r7 0 r5 0 c1 0.1f c2 0.1f c31 0.1f jp1 en ds 17 1 12 11 10 9 c18 0.1f c25 opt t1 maba-007159- 000000 c26 (1) c32 0.1f c17 680pf c13 0.1f 64106 ta06 c12 680pf r19 opt r15 (1) 234 v cc Cterm Cin +in +term v + Cout +out v + 13 14 15 16 8 7 6 5 v + v cc v cc v C v C v C v bias v + tp1 shdn j2 +in j1 Cin c33 (1) tp4 v bias c7 0.1f r20 opt r21 (1) r23 0 r24 0 tp5 gnd tp2 v cc 2.8v to 5.5v v cc c11 (1) c4 0.1f c30 0.1f j4 Cout j5 +out j7 test out c16 (1) c34 (1) c22 opt c3 (1) t2 maba-007159- 000000 c19 opt c20 opt t3 maba-007159- 000000 t4 maba-007159- 000000 c28 0.1f c6 0.1f c29 0.1f note: unless otherwise specified (1) not populated c5 0.1f j6 test in tp3 gnd r22 (1) c15 1f c14 4.7f

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