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1 1994fb lt1994 low noise, low distortion fully differential input/ output ampli er/driver the lt ? 1994 is a high precision, very low noise, low distor- tion, fully differential input/output ampli? er optimized for 3v, single-supply operation. the lt1994s output common mode voltage is independent of the input common mode voltage, and is adjustable by applying a voltage on the v ocm pin. a separate internal common mode feedback path provides accurate output phase balancing and reduced even-order harmonics. this makes the lt1994 ideal for level shifting ground referenced signals for driving dif- ferential input, single-supply adcs. the lt1994 output can swing rail-to-rail and is capable of sourcing and sinking up to 85ma. in addition to the low distortion characteristics, the lt1994 has a low input referred voltage noise of 3nv/hz. this part maintains its performance for supply voltages as low as 2.375v. it draws only 13.3ma of supply current and has a hardware shutdown feature that reduces current consumption to 225a. the lt1994 is available in an 8-pin msop or 8-pin dfn package. n differential input a/d converter driver n single-ended to differential conversion n differential ampli? cation with common mode translation n rail-to-rail differential line driver/receiver n low voltage, low noise, differential signal processing n fully differential input and output n wide supply range: 2.375v to 12.6v n rail-to-rail output swing n low noise: 3nv/hz n low distortion, 2v p-p , 1mhz: C94dbc n adjustable output common mode voltage n unity-gain stable n gain-bandwidth: 70mhz n slew rate: 65v/s n large output current: 85ma n dc voltage offset <2mv max n open-loop gain: 100v/mv n low power shutdown n 8-pin msop or 3mm 3mm dfn package a/d preampli? er: single-ended input to differential output with common mode level shifting lt1994 driving an ltc1403a-1 1mhz sine wave, 8192 point fft plot typical application description l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features applications 1994 ta01 24.9 3v 0.1f 24.9 47pf 499 499 499 499 3v 10f 10f 0.1f v in 2v p-p v ocm = 1.5v gnd v dd a in C a in + v ref conv sd0 sck 50.4mhz ltc1403a-1 + C C + lt1994 v ocm frequency (mhz) 0 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 differential output magnitude (db) 0 0.35 0.70 1994 ta01b 1.40 1.05 f sample = 2.8msps f in = 1.001mhz input = 2v p-p , single ended sfdr = 93db
lt1994 2 1994fb total supply voltage (v + to v C ) ..............................12.6v input voltage (note 2) ............................................... v s input current (note 2) ..........................................10ma input current (v ocm , shdn ) ................................10ma v ocm , shdn .............................................................. v s output short-circuit duration (note 3) ............ inde? nite operating temperature range (note 4) lt1994c ............................................... C40c to 85c lt1994i ................................................ C40c to 85c lt1994h ............................................ C40c to 125c lt1994mp.......................................... C55c to 125c speci? ed temperature range (note 5) lt1994c ................................................... 0c to 70c lt1994i ................................................ C40c to 85c lt1994h ............................................ C40c to 125c lt1994mp.......................................... C55c to 125c junction temperature ........................................... 150c storage temperature range ................... C65c to 150c order information lead free finish tape and reel part marking* package description specified temperature range lt1994cdd#pbf lt1994cdd#trpbf lbqm 8-lead (3mm 3mm) plastic dfn 0c to 70c lt1994idd#pbf lt1994idd#trpbf lbqm 8-lead (3mm 3mm) plastic dfn C40c to 85c lt1994hdd#pbf lt1994hdd#trpbf lbqm 8-lead (3mm 3mm) plastic dfn C40c to 125c lt1994mpdd#pbf lt1994mpdd#trpbf ldxq 8-lead (3mm 3mm) plastic dfn C55c to 125c lt1994cms8#pbf lt1994cms8#trpbf ltbqn 8-lead plastic msop 0c to 70c lt1994ims8#pbf lt1994ims8#trpbf ltbqn 8-lead plastic msop C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ top view dd package 8-lead (3mm s 3mm) plastic dfn 5 6 7 8 4 3 2 1 in C v ocm v + out + in + shdn v C out C t jmax = 150c, ja = 43c/w exposed pad (pin 9) is gnd, must be soldered to v C 1 2 3 4 in C v ocm v + out + 8 7 6 5 in + shdn v C out C top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 140c/w pin configuration absolute maximum ratings (note 1)
3 1994fb lt1994 symbol parameter conditions c/i grades h/mp grades units min typ max min typ max v osdiff differential offset voltage (input referred) v s = 2.375v, v icm = v s /4 v s = 3v v s = 5v v s = 5v l l l l 2 2 2 3 2 2 2 3 mv mv mv mv v osdiff / t differential offset voltage drift (input referred) v s = 2.375v, v icm = v s /4 v s = 3v v s = 5v v s = 5v 3 3 3 3 v/c v/c v/c v/c i b input bias current (note 6) v s = 2.375v, v icm = v s /4 v s = 3v v s = 5v v s = 5v l l l l C45 C45 C45 C45 C18 C18 C18 C18 C3 C3 C3 C3 C45 C45 C45 C45 C18 C18 C18 C18 C3 C3 C3 C3 a a a a i os input offset current (note 6) v s = 2.375v, v icm = v s /4 v s = 3v v s = 5v v s = 5v l l l l 0.2 0.2 0.2 0.2 2 2 3 4 0.2 0.2 0.2 0.2 2 2 3 4 a a a a r in input resistance common mode differential mode 700 4.5 700 4.5 k k c in input capacitance differential 2 2 pf e n differential input referred noise voltage density f = 50khz 3 3 nv/ hz i n input noise current density f = 50khz 2.5 2.5 pa/ hz e nvocm input referred common mode output noise voltage density f = 50khz, v ocm shorted to ground 15 15 nv/ hz v icmr (note 7) input signal common mode range v s = 3v v s = 5v l l 0 C5 1.75 3.75 0 C5 1.75 3.75 v v cmrri (note 8) input common mode rejection ratio (input referred) v icm / v osdiff v s = 3v, v icm = 0.75v l 55 85 55 85 db cmrrio (note 8) output common mode rejection ratio (input referred) v ocm / v osdiff v s = 5v, v ocm = 2v l 65 85 65 85 db psrr (note 9) differential power supply rejection ( v s / v osdiff ) v s = 3v to 5v l 69 105 69 105 db psrrcm (note 9) output common mode power supply rejection ( v s / v oscm ) v s = 3v to 5v l 45 70 45 70 db g cm common mode gain (v outcm / v ocm ) v s = 2.5v l 1v/v common mode gain error 100 ? (g cm C 1) v s = 2.5v l C0.15 1 % bal output balance ( v outcm / v outdiff ) v outdiff = 2v single-ended input differential input l l C65 C71 C46 C50 C65 C71 C46 C50 db db v oscm common mode offset voltage (v outcm C v ocm ) v s = 2.375v, v icm = v s /4 v s = 3v v s = 5v v s = 5v l l l l 2.5 2.5 2.5 2.5 25 25 30 40 2.5 2.5 2.5 2.5 25 25 30 40 mv mv mv mv electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v cm = v ocm = v icm = mid-supply, v shdn = open, r i = r f = 499 , r l = 800 to a mid-supply voltage (see figure 1) unless otherwise noted. v s is de? ned (v + C v C ). v outcm is de? ned as (v out + + v out C )/2. v icm is de? ned as (v in + + v in C )/2. v outdiff is de? ned as (v out + C v out C ). v indiff is de? ned as (v in + C v in C ).
lt1994 4 1994fb symbol parameter conditions c/i grades h/mp grades units min typ max min typ max v oscm / t common mode offset voltage drift v s = 2.375v, v icm = v s /4 v s = 3v v s = 5v v s = 5v 5 5 5 5 5 5 5 5 v/c v/c v/c v/c v outcmr (note 7) output signal common mode range (voltage range for the v ocm pin) v s = 3v, 5v l v C + 1.1 v + C 0.8 v C + 1.1 v + C 0.8 v r invocm input resistance, v ocm pin l 30 40 60 30 40 60 k v mid voltage at the v ocm pin v s = 5v l 2.45 2.5 2.55 2.45 2.5 2.55 v v out output voltage, high, either output pin (note 10) v s = 3v, no load v s = 3v, r l = 800 v s = 3v, r l = 100 l l l 70 90 200 140 175 400 70 90 200 140 175 400 mv mv mv v s = 5v, no load v s = 5v, r l = 800 v s = 5v, r l = 100 l l l 150 200 900 325 450 2400 150 200 900 325 450 2400 mv mv mv output voltage, low, either output pin (note 10) v s = 3v, no load v s = 3v, r l = 800 v s = 3v, r l = 100 l l l 30 50 125 70 90 250 30 50 125 70 90 250 mv mv mv v s = 5v, no load v s = 5v, r l = 800 v s = 5v, r l = 100 l l l 80 125 900 180 250 2400 80 125 900 180 250 2400 mv mv mv i sc output short-circuit current, either output pin (note 11) v s = 2.375v, r l = 10 v s = 3v, r l = 10 v s = 5v, r l = 10 v s = 5v, v cm = 0v, r l = 10 l l l l 25 30 40 45 35 40 65 85 10 15 40 45 35 40 65 85 ma ma ma ma sr slew rate v s = 5v, v out + = C v out C = 1v v s = 5v, v cm = 0v, v out + = C v out C = 1.8v l l 50 50 65 65 85 85 50 50 65 65 85 85 v/s v/s gbw gain-bandwidth product (f test = 1mhz) v s = 3v, t a = 25c v s = 5v, v cm = 0v, t a = 25c l l 58 58 70 70 58 58 70 70 mhz mhz distortion v s = 3v, r l = 800 , f in = 1mhz, v out + C v out C = 2v p-p differential input 2nd harmonic 3rd harmonic single-ended input 2nd harmonic 3rd harmonic C99 C96 C94 C108 C99 C96 C94 C108 dbc dbc dbc dbc t s settling time v s = 3v, 0.01%, 2v step v s = 3v, 0.1%, 2v step 120 90 120 90 ns ns a vol large-signal voltage gain v s = 3v 100 100 db v s supply voltage range l 2.375 12.6 2.375 12.6 v i s supply current v s = 3v v s = 5v v s = 5v l l l 13.3 13.9 14.8 18.5 19.5 20.5 13.3 13.9 14.8 20.0 20.5 21.5 ma ma ma i shdn supply current in shutdown v s = 3v v s = 5v v s = 5v l l l 0.225 0.375 0.7 0.8 1.75 2.5 0.225 0.375 0.7 0.8 1.75 2.5 ma ma ma electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v cm = v ocm = v icm = mid-supply, v shdn = open, r i = r f = 499 , r l = 800 to a mid-supply voltage (see figure 1) unless otherwise noted. v s is de? ned (v + C v C ). v outcm is de? ned as (v out + + v out C )/2. v icm is de? ned as (v in + + v in C )/2. v outdiff is de? ned as (v out + C v out C ). v indiff is de? ned as (v in + C v in C ).
5 1994fb lt1994 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the inputs are protected by a pair of back-to-back diodes. if the differential input voltage exceeds 1v, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. note 4: the lt1994c/lt1994i are guaranteed functional over the operating temperature range C40c to 85c. the lt1994h is guaranteed functional over the operating temperature range C40c to 125c. the lt1994mp is guaranteed functional over the operating temperature range C55c to 125c. note 5: the lt1994c is guaranteed to meet speci? ed performance from 0c to 70c. the lt1994c is designed, characterized, and expected to meet speci? ed performance from C40c to 85c but is not tested or qa sampled at these temperatures. the lt1994i is guaranteed to meet speci? ed performance from C40c to 85c. the lt1994h is guaranteed to meet speci? ed performance from C40c to 125c. the lt1994mp is guaranteed to meet speci? ed performance from C55c to 125c. note 6: input bias current is de? ned as the average of the input currents ? owing into pin 1 and pin 8 (in C and in + ). input offset current is de? ned as the difference of the input currents ? owing into pin 8 and pin 1 (i os = i b + C i b C ). note 7: input common mode range is tested using the test circuit of figure 1 (r f = r i ) by applying a single ended 2v p-p , 1khz signal to v inp (v inm = 0), and measuring the output distortion (thd) at the common mode voltage range limits listed in the electrical characteristics table, and con? rming the output thd is better than C40db. the voltage range for the output common mode range (pin 2) is tested using the test circuit of figure 1 (r f = r i ) by applying a 0.5v peak, 1khz signal to the v ocm pin 2 (with v inp = v inm = 0) and measuring the output distortion (thd) at v outcm with v ocm biased 0.5v from the v ocm pin range limits listed in the electrical characteristics table, and con? rming the thd is better than C40db. note 8: input cmrr is de? ned as the ratio of the change in the input common mode voltage at the pins in + or in C to the change in differential input referred voltage offset. output cmrr is de? ned as the ratio of the change in the voltage at the v ocm pin to the change in differential input referred voltage offset. note 9: differential power supply rejection (psrr) is de? ned as the ratio of the change in supply voltage to the change in differential input referred voltage offset. common mode power supply rejection (psrrcm) is de? ned as the ratio of the change in supply voltage to the change in the common mode offset, v outcm C v ocm . note 10: output swings are measured as differences between the output and the respective power supply rail. note 11: extended operation with the output shorted may cause junction temperatures to exceed the 150c limit and is not recommended. electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v + = 3v, v C = 0v, v cm = v ocm = v icm = mid-supply, v shdn = open, r i = r f = 499 , r l = 800 to a mid-supply voltage (see figure 1) unless otherwise noted. v s is de? ned (v + C v C ). v outcm is de? ned as (v out + + v out C )/2. v icm is de? ned as (v in + + v in C )/2. v outdiff is de? ned as (v out + C v out C ). v indiff is de? ned as (v in + C v in C ). symbol parameter conditions c/i grades h/mp grades units min typ max min typ max v il shdn input logic low v s = 3v to 5v l v + C 2.1 v + C 2.1 v v ih shdn input logic high v s = 3v to 5v l v + C 0.6 v + C 0.6 v r shdn shdn pull-up resistor v s = 2.375v to 5v 40 55 75 40 55 75 k t on turn-on time v shdn 0.5v to 3v 1 1 s t off turn-off time v shdn 3v to 0.5v 1 1 s
lt1994 6 1994fb output impedance vs frequency output balance vs frequency differential power supply rejection vs frequency differential input referred voltage offset vs temperature common mode voltage offset vs temperature input bias current and input offset current vs temperature gain bandwidth vs temperature frequency response vs supply voltage frequency response vs load capacitance typical performance characteristics temperature (c) C50 C750 differential v os (v) C500 C250 0 250 500 C25 02550 1994 g01 75 100 v s = 3v v cm = 1.5v v ocm = 1.5v four typical units temperature (c) C50 C2.5 common mode voltage offset (mv) 0 2.5 5.0 7.5 C25 02550 1994 g02 75 100 v s = 3v v cm = 1.5v v ocm = 1.5v four typical units temperature (c) C50 C30 input bias current (a) C25 C20 C15 C10 C25 02550 1994 g03 C1.0 input offset current (a) C0.5 0 0.5 1.0 75 100 i os , v s = 3v i b , v s = 3v i b , v s = 5v i os , v s = 5v temperature (c) C50 66 gain bandwidth (mhz) 72 71 70 69 68 67 C25 02550 1994 g04 75 100 v s = 3v v s = 5v frequency (mhz) 0.1 gain (db) 2 1 0 C1 C2 1 10 100 1994 g05 r f = r i = 499 v s = 2.5v v s = 5v v s = 5v v s = 3v frequency (mhz) 0.1 gain (db) 2 1 0 C1 C2 1 10 100 1994 g06 r f = r i = 499 5pf from each output to ground 25pf from each output to ground v s = 2.5v v s = 3v frequency (mhz) 0.1 0.1 z out out + , out C () 1 10 100 1 10 100 1994 g07 v s = 3v r f = r i = 499 frequency (hz) output balance (db) C30 C40 C50 C60 C70 C80 C90 1995 g08 differential input single-ended input v s = 3v $ v outcm $ v outdiff 1k 10k 100k 1m 10m 100m frequency (hz) differential psrr (db) 110 100 80 60 40 20 90 70 50 30 10 0 1995 g09 v s = 3v v + supply v C supply $ v s $ v osdiff 1k 10k 100k 1m 10m 100m
7 1994fb lt1994 frequency (hz) 10 input referred voltage noise density (nv/hz) 1k 100k 1m 100 10k 1995 g12 1 10 100 input current noise density (pa/hz) 1 10 100 v s = 3v t a = 25c e n i n input common mode rejection vs frequency common mode output power supply rejection vs frequency input noise vs frequency differential distortion vs input amplitude (single-ended input) differential distortion vs input common mode level typical performance characteristics 1k 10k 100k 1m 10m 100m frequency (hz) input cmrr (db) 100 90 80 70 60 50 30 40 1995 g10 v s = 3v $ v icm $ v osdiff v s = p 5v frequency (mhz) 0.1 1 10 100 common mode psrr (db) 60 50 30 40 20 10 0 1995 g11 v s = 3v $ v s $ v osocm v + supply v C supply differential distortion vs frequency v in (v p-p ) 1 C110 C100 distortion hd2, hd3 (db) C90 C80 C70 C60 2 34 1994 g13 5 v s = 3v f in = 1mhz r f = r i = 499 r l = 800 v ocm = mid-supply 2nd, v cm = v C 3rd, v cm = v C 3rd, v icm = 1.5v 2nd, v icm = 1.5v input common mode dc bias, in C or in + pins (v) 0 C110 C100 distortion hd2, hd3 (db) C90 C80 C70 C40 C50 C60 1.0 1.5 0.5 2.0 1994 g14 2.5 v s = 3v v in = 2v p-p (single ended) f in = 1mhz r f = r i = 499 r l = 800 v ocm = mid-supply 3rd 2nd frequency (hz) C110 C100 distortion (db) C90 C80 C70 C40 C50 C60 1994 g15 v s = 3v v in = 2v p-p (single ended) f in = 1mhz r f = r i = 499 r l = 800 v ocm = mid-supply v icm = mid-supply 3rd 2nd 100k 1m 10m slew rate vs temperature 2v step response settling temperature (c) C50 60 slew rate (v/s) 62 64 66 68 C25 02550 1994 g16 75 100 v s = 3v v s = 5v r f = r i = 499 25ns/div v out = v out + C v out C (0.5v/div) settle voltage error (2mv/div) 1994 g17 v out C0.1% error v s = 3v r f = r i = 499 +0.1% error
lt1994 8 1994fb large-signal step response output with large input overdrive supply current vs supply voltage supply current vs shdn voltage supply current vs shdn voltage shdn pin current vs shdn pin voltage shutdown supply current vs supply voltage small-signal step response typical performance characteristics 20ns/div 20mv/div 1994 g18 25pf load 0pf load out + out C v s = 3v r f = r i = 499 v in = 100mv p-p , single ended 100ns/div 0.5v/div 1994 g19 out + out C v in = 3v p-p single ended v s = 3v r f = r i = 499 v cm = v C 2s/div 0.5v/div 1994 g20 out + out C v in = 10v p-p single ended v s = 3v r f = r i = 499 supply voltage (v) 0 0 total supply current (ma) 5 10 15 20 2.5 5.0 7.5 10.0 1994 g21 12.5 t a = C40c t a = 85c t a = 25c t a = 70c t a = 0c shdn pin voltage = v + shdn pin voltage (v) 0 0 total supply current (ma) 4 8 12 16 1.0 2.0 1.5 0.5 2.5 1994 g23 3.0 t a = C40c t a = 85c t a = 25c t a = 70c t a = 0c v s = 3v shdn pin voltage (v) 0 0 total supply current (ma) 4 8 12 16 1.0 2.0 1.5 0.5 2.5 1994 g23 3.0 t a = C40c t a = 85c t a = 25c t a = 70c t a = 0c v s = 3v shdn pin voltage (v) 0 C30 shdn pin current (a) C20 C10 0 1.0 2.0 1.5 0.5 2.5 1994 g24 3.0 t a = C40c t a = 85c t a = 25c t a = 0c v s = 3v t a = 70c supply voltage (v) 0 0 shutdown supply current (a) 250 500 750 1000 5.0 10.0 7.5 2.5 1994 g25 12.5 t a = C40c t a = 85c t a = 25c
9 1994fb lt1994 in + , in C (pins 1, 8): noninverting and inverting input pins of the ampli? er, respectively. for best performance, it is highly recommended that stray capacitance be kept to an absolute minimum by keeping printed circuit connections as short as possible, and if necessary, strip- ping back nearby surrounding ground plane away from these pins. v ocm (pin 2): output common mode reference voltage. the v ocm pin is the midpoint of an internal resistive volt- age divider between the supplies, developing a (default) mid-supply voltage potential to maximize output signal swing. v ocm has a thevenin equivalent resistance of approximately 40k and can be overdriven by an external voltage reference. the voltage on v ocm sets the output common mode voltage level (which is de? ned as the av- erage of the voltages on the out + and out C pins). v ocm should be bypassed with a high quality ceramic bypass capacitor of at least 0.1f (unless connected directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differen- tial noise by impedance mismatches both externally and internally to the ic. v + , v C (pins 3, 6): power supply pins. for single-supply applications (pin 6 grounded) it is recommended that high quality 1f and 0.1f ceramic bypass capacitors be placed from the positive supply pin (pin 3) to the negative supply pin (pin 6) with minimal routing. pin 6 should be directly tied to a low impedance ground plane. for dual power supplies, it is recommended that high quality, 0.1f ceramic capacitors are used to bypass pin 3 to ground and pin 6 to ground. it is also highly recommended that high quality 1f and 0.1f ceramic bypass capacitors be placed across the power supply pins (pins 3 and 6) with minimal routing. out + , out C (pins 4, 5): output pins. each pin can drive approximately 100 to ground with a short-circuit current limit of up to 85ma. each ampli? er output is designed to drive a load capacitance of 25pf. this basically means the ampli? er can drive 25pf from each output to ground or 12.5pf differentially. larger capacitive loads should be decoupled with at least 25 resistors from each output. shdn (pin 7): when pin 7 ( shdn ) is ? oating or when pin 7 is directly tied to v + , the lt1994 is in the normal operating mode. when pin 7 is pulled a minimum of 2.1v below v + , the lt1994 enters into a low power shutdown state. refer to the shdn pin section under applications information for a description of the lt1994 output imped- ance in the shutdown state. pin functions
lt1994 10 1994fb functional description the lt1994 is a small outline, wideband, low noise and low distortion fully-differential ampli? er with accurate output-phase balancing. the lt1994 is optimized to drive low voltage, single-supply, differential input ana- log-to-digital converters (adcs). the lt1994s output is capable of swinging rail-to-rail on supplies as low as 2.5v, which makes the ampli? er ideal for converting ground referenced, single-ended signals into v ocm referenced differential signals in preparation for driving low voltage, single-supply, differential input adcs. unlike traditional op amps which have a single output, the lt1994 has two outputs to process signals differentially. this allows for two times the signal swing in low voltage systems when compared to single-ended output ampli? ers. the balanced differential nature of the ampli? er also provides even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). the lt1994 can be used as a single-ended input to differential output ampli? er, or as a differential input to differential output ampli? er. the lt1994s output common mode voltage, de? ned as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by applying a voltage on the v ocm pin. if the pin is left open, there is an internal resistive voltage divider, which develops a potential halfway between the v + and v C pins. the v ocm pin will have an equivalent thevenin equivalent resistance of 40k, and a thevenin equivalent voltage of half supply. whenever this pin is not hard tied to a low impedance ground plane, it is recommended that a high quality ceramic capacitor is used to bypass the v ocm pin to a low impedance ground plane (see layout considerations in this document). the lt1994s internal common mode feedback path forces accurate output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the v ocm pin. vv vv outcm ocm out out == + + ? 2 the outputs (out + and out C ) of the lt1994 are capable of swinging rail-to-rail. they can source or sink up to approximately 85ma of current. each output is rated to drive approximately 25pf to ground (12.5pf differentially). higher load capacitances should be decoupled with at least 25 of series resistance from each output. input pin protection the lt1994s input stage is protected against differential input voltages that exceed 1v by two pairs of back-to- back diodes that protect against emitter base breakdown of the input transistors. in addition, the input pins have steering diodes to either power supply. if the input pair is overdriven, the current should be limited to under 10ma to prevent damage to the ic. the lt1994 also has steering diodes to either power supply on the v ocm , and shdn pins (pins 2 and 7) and if exposed to voltages that exceed either supply, they too should be current limited to under 10ma. shdn pin if the shdn pin (pin 7) is pulled 2.1v below the positive supply, an internal current is generated that is used to power down the lt1994. the pin will have the thevenin equivalent impedance of approximately 55k to v + . if the pin is left unconnected, an internal pull-up resistor of 120k will keep the part in normal active operation. care should be taken to control leakage currents at this pin to under 1a to prevent leakage currents from inadvertently putting the lt1994 into shutdown. in shutdown, all biasing current sources are shut off, and the output pins out + and out C will each appear as open collectors with a nonlinear capacitor in parallel, and steering diodes to either supply. because of the nonlinear capacitance, the outputs still have the ability to sink and source small amounts of transient current if exposed to signi? cant voltage transients. the inputs (in + and in C ) have anti-parallel diodes that can conduct if voltage transients at the input exceed 1v. the inputs also have steering diodes to either supply. the turn-on and turn-off time between the shutdown and active states are on the order of 1s but depends on the circuit con? guration. applications information
11 1994fb lt1994 general ampli? er applications as levels of integration have increased and, correspond- ingly, system supply voltages decreased, there has been a need for adcs to process signals differentially in order to maintain good signal-to-noise ratios. these adcs are typically supplied from a single-supply voltage that can be as low as 2.5v and will have an optimal common mode input range near mid-supply. the lt1994 makes interfac- ing to these adcs trivial, by providing both single-ended to differential conversion as well as common mode level shifting. figure 1 shows a general single-supply application with perfectly matched feedback networks from out + and out C . the gain to v outdiff from v inm and v inp is: vvv r r vv outdiff out out f i inp inm = () + ??? ? note from the above equation that the differential output voltage (v out + C v out C ) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. this makes the lt1994 ideally suited pre-ampli? cation, level shifting, and conversion of single-ended signals to differential output signals in preparation for driving differential input adcs. effects of resistor pair mismatch figure 2 shows a circuit diagram that takes into consid- eration that real world resistors will not perfectly match. assuming in? nite open-loop gain, the differential output relationship is given by the equation: vvv r r v vv outdiff out out f i indiff avg icm avg ocm =?+ ? + ?? ?? ?, ? where: r f is the average of r f1 and r f2 , and r i is the average of r i1 and r i2 . avg is de? ned as the average feedback factor (or gain) from the outputs to their respective inputs: avg i if i if r rr r rr = + + + ? ? ? ? ? ? 1 2 2 22 1 11 ? ? is de? ned as the difference in feedback factors: = ++ r rr r rr i if i if 2 22 1 11 ? figure 1. test circuit figure 2. real-world application v ocm 0.1f 1994 f01 r i r f r l v + 0.1f 0.1f v cm v shdn v inm v inp v outcm 3 7 6 8 1 2 5 4 v C v out + v in C v out C v in + r bal r bal 0.1f r i r f r l + C C + lt1994 v ocm 1994 f02 r i2 r f2 r l v s v shdnb v inm v inp + C C + 3 7 6 8 1 2 5 4 lt1994 v ocm v ocm v out + v in C v out C v in + 0.1f 0.1f r i1 r f1 r l shdn applications information
lt1994 12 1994fb v icm is de? ned as the average of the two input voltages, v inp and v inm (also called the input common mode voltage): vvv icm inp inm =+ () 1 2 ? and v indiff is de? ned as the difference of the input voltages: v indiff = v inp C v inm when the feedback ratios mismatch ( ? ), common mode to differential conversion occurs. setting the differential input to zero (v indiff = 0), the de- gree of common mode to differential conversion is given by the equation: vvv vv v outdiff out out icm ocm avg indiff z $ C C? C b b 0 in general, the degree of feedback pair mismatch is a source of common mode to differential conversion of both signals and noise. using 1% resistors or better will provide about 28db of common mode rejection. using 0.1% resistors will provide about 48db of common mode rejection. a low impedance ground plane should be used as a reference for both the input signal source and the v ocm pin. a direct short of v ocm to this ground plane or bypassing the v ocm with a high quality 0.1f ceramic capacitor to this ground plane will further mitigate against common mode signals from being converted to differential. input impedance and loading effects the input impedance looking into the v inp or v inm input of figure 1 depends on whether or not the sources v inp and v inm are fully differential. for balanced input sources (v inp = Cv inm ), the input impedance seen at either input is simply: r inp = r inm = r i for single-ended inputs, because of the signal imbalance at the input, the input impedance actually increases over the balanced differential case. the input impedance looking into either input is: rr r r rr inp inm i f if == + ? ? ? ? ? ? ? ? ? ? ? ? 1 1 2 ?? input signal sources with non-zero output impedances can also cause feedback imbalance between the pair of feedback networks. for the best performance, it is recommended that the sources output impedance be compensated for. if input impedance matching is required by the source, r1 should be chosen (see figure 3): r rr rr inm s inm s 1 = ? ? according to figure 3, the input impedance looking into the differential amp (r inm ) re? ects the single-ended source case, thus: r r r rr inm i f if = + ? ? ? ? ? ? ? ? ? ? ? ? 1 1 2 ?? r2 is chosen to balance r1||r s : r rr rr s s 2 1 1 = + ? figure 3. optimal compensation for signal-source impedance 1994 f03 r i r f r s v s + C C + lt1994 r i r f r2 = r s || r1 r1 chosen so that r1 || r inm = r s r2 chosen to balance r1 || r s r1 r inm applications information
13 1994fb lt1994 input common mode voltage range the lt1994s input common mode voltage (v icm ) is de? ned as the average of the two input voltages, v in + , and v in C . it extends from v C to approximately 1.25v below v + . the input common mode range depends on the circuit con- ? guration (gain), v ocm and v cm (refer to figure 4). for fully differential input applications, where v inp = Cv inm , the common mode input is approximately: v vv v r rr v r rr icm in in ocm i if cm f fi = + + ? ? ? ? ? ? + + ? ? ? ? ? ? + ? ? ? 2 with singled-ended inputs, there is an input signal com- ponent to the input common mode voltage. applying only v inp (setting v inm to zero), the input common voltage is approximately: v vv v r rr v r rr vr rr icm in in ocm i if cm f fi inp f fi = + + ? ? ? ? ? ? + + ? ? ? ? ? ? + + ? ? ? ? ? ? + ? ? ?? 2 2 output common mode voltage range the output common mode voltage is de? ned as the aver- age of the two outputs: vv vv outcm ocm out out == + + ? 2 the v ocm sets this average by an internal common mode feedback loop which internally forces v out + = Cv out C . the output common mode range extends from approximately 1.1v above v C to approximately 0.8v below v + . the v ocm pin sits in the middle of an 80k to 80k voltage divider that sets the default mid-supply open-circuit potential. in single-supply applications, where the lt1994 is used to interface to an adc, the optimal common mode input range to the adc is often determined by the adcs refer- ence. if the adc makes a reference available for setting the input common mode voltage, it can be directly tied to the v ocm pin, but must be capable of driving a 40k equivalent resistance that is tied to a mid-supply potential. if an external reference drives the v ocm pin, it should still be bypassed with a high quality 0.1f capacitor to a low impedance ground plane to ? lter any thermal noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals. noise considerations the lt1994s input referred voltage noise is on the order of 3nv/ hz . its input referred current noise is on the order of 2.5pa/ hz . in addition to the noise generated by the ampli? er, the surrounding feedback resistors also contribute noise. the output noise generated by both the ampli? er and the feedback components is given by the equation: e e r r ir e r r e no ni f i nf nri f i nrf = + ? ? ? ? ? ? ? ? ? ? ? ? + () + ? ? ? ? ? ? ? ? ? ? ? ? + ??? ?? ? 12 22 2 2 2 2 figure 4. circuit for common mode range v cm 1994 f04 r i r f r l v s v shdnb v inm v inp + C C + 3 7 6 8 1 2 5 4 lt1994 v ocm v ocm v out + v in C v out C v in + 0.1f r i r f r l shdn applications information
lt1994 14 1994fb a plot of this equation and a plot of the noise generated by the feedback components are shown in figure 6. the lt1994s input referred voltage noise contributes the equivalent noise of a 560 resistor. when the feedback network is comprised of resistors whose values are less than this, the lt1994s output noise is voltage noise dominant (see figure 6): ee r r no ni f i + ? ? ? ? ? ? ?1 feedback networks consisting of resistors with values greater than about 10k will result in output noise which is ampli? er current noise dominant. eir no n f 2? ? lower resistor values always result in lower noise at the penalty of increased distortion due to increased loading of the feedback network on the output. higher resistor values will result in higher output noise, but improved distortion due to less loading on the output. figure 6 shows the noise voltage that will appear differ- entially between the outputs. the common mode output noise voltage does not add to this differential noise. for optimum noise and distortion performance, use a dif- ferential output con? guration. power dissipation considerations the lt1994 is housed in either an 8-lead msop package ( ja = 140c/w or an 8-lead dd package ( ja = 43c/w). the lt1994 combines high speed and large output current with a small die and small package so there is a need to be sure the die temperature does not exceed 150c. in the 8-lead msop , lt1994 has its v C lead fused to the frame so it is possible to lower the package thermal impedance by connecting the v C pin to a large ground plane or metal trace. metal trace and plated through holes can be used to spread the heat generated by the device to the backside of the pc board. for example, an 8-lead msop on a 3/32" fr-4 board with 540mm 2 of 2oz. copper on both sides of the pc board tied to the v C pin can drop the ja from 140c/w to 110c/w (see table 1). the underside of the dd package has exposed metal (4mm 2 ) from the lead frame where the die is attached. this provides for the direct transfer of heat from the die junction to the printed circuit board to help control the maximum operating junction temperature. the dual-in-line pin arrangement allows for extended metal beyond the ends of the package on the topside (component side) of a circuit board. table 1 summarizes for the msop package, the thermal resistance from the die junction-to-ambient that can be obtained using various amounts of topside, and backside metal (2oz. copper). on multilayer boards, further reductions can be obtained using additional metal on inner pcb layers connected through vias beneath the package. figure 6. lt1994 output spot noise vs spot noise contributed by feedback network alone r f = r i (k) 0.1 1 output noise (nv/hz) 10 100 110 1994 f06 total (amplifier + feedback network) output noise feedback network noise alone 1994 f05 r i2 r f2 v s /2 Cv s /2 + C C + 3 7 6 8 1 2 5 4 lt1994 v ocm e nri2 2 r i1 r f1 e ncm 2 e no 2 i nC 2 e nri1 2 e ni 2 e nrf2 2 e nrf1 2 i n+ 2 figure 5. noise analysis applications information
15 1994fb lt1994 in general, the die temperature can be estimated from the ambient temperature t a , and the device power dis- sipation p d : t j = t a + + p d ? ja the power dissipation in the ic is a function of the supply voltage, the output voltage, and the load resistance. for fully differential output ampli? ers at a given supply voltage (v cc ), and a given differential load (r load ), the worst- case power dissipation p d(max) occurs at the worst-case quiescent current (i q(max) = 20.5ma) and when the load current is given by the expression: i v r load cc load = the worst-case power dissipation in the lt1994 at i v r load cc load = is: pviii r v r vi dmax cc load q max load load cc load cc qmax () () () =+ () =+ 2 2 2 2 ?? ? ? ?? example: a lt1994 is mounted on a circuit board in a msop-8 package ( ja = 140c/w), and is running off of 5v supplies driving an equivalent load (external load plus feedback network) of 75 . the worst-case power that would be dissipated in the device occurs when: p v r vi v v dmax cc load cc qmax () () =+ =+ 2 2 2 5 75 25 ?? ? ? ?. . 17 5 0 54 ma w = the maximum ambient temperature the 8-lead msop is allowed to operate under these conditions is: t a = t jmax C p d ? ja = 150c C (0.54w) ? (140c/w) = 75c to operate the device at higher ambient temperature, connect more copper to the v C pin to reduce the thermal resistance of the package as indicated in table 1. table 1. lt1994 msop package thermal resistivity copper area topside (mm 2 ) copper area backside (mm 2 ) thermal resistance (junction-to-ambient) 00 140 30 0 135 100 0 130 100 100 120 540 540 110 layout considerations because the lt1994 is a high speed ampli? er, it is sensitive to both stray capacitance and stray inductance. compo- nents connected to the lt1994 should be connected with as short and direct connections as possible. a low noise, low impedance ground plane is critical for the highest performance. in single-supply applications, high quality surface mount 1f and 0.1f ceramic bypass capacitors with minimum pcb trace should be used directly across the power supplies v + to v C . in split supply applications, high quality surface mount 1f and 0.1f ceramic bypass capacitors should be placed across the power supplies v + to v C , and individual high quality surface mount 0.1f bypass capacitors should be used from each supply to ground with direct (short) connections. any stray parasitic capacitance to ground at the summing junctions, in + and in C should be kept to an absolute mini- mum even if it means stripping back the ground plane away from any trace attached to this node. this becomes especially true when the feedback resistor network uses resistor values >500 in circuits with r f = r i . excessive peaking in the frequency response can be mitigated by adding small amounts of feedback capacitance around rf (2pf to 5pf). always keep in mind the differential nature of the lt1994, and that it is critical that the output impedances seen by both outputs (stray or intended) should be as bal- anced and symmetric as possible. this will help preserve the natural balance of the lt1994, which minimizes the generation of even order harmonics, and preserves the rejection of common mode signals and noise. it is highly recommended that the v ocm pin be either hard tied to a low impedance ground plane (in split supply applications) or bypassed to ground with a high quality applications information
lt1994 16 1994fb 0.1f ceramic capacitor in single-supply applications. this will help prevent thermal noise from the internal 80k - 80k voltage divider (25nv/ hz ) and other exter- nal sources of noise from being converted to differential noise due to mismatches in the feedback networks. it is also recommended that the resistive feedback networks be comprised of 1% resistors (or better) to enhance the output common mode rejection. this will also prevent v ocm input referred common mode noise of the common mode ampli? er path (which cannot be ? ltered) from being converted to differential noise, degrading the differential noise performance. applications information simplified schematic 1994 ss01 v + shdn 120k q4 i 1 q3 i 1 55k v + v C out + v + v C v + v C v ocm v C v + v C v + v + v + v C bias adjust shutdown circuit cm adjust 80k 80k q11 q12 q5 q6 q8 i 4b out + v + out C q7 i 3 bias r1 4k r2 4k c m2 C + out C v + v C v + v C bias adjust q9 q10 c m1 in C v + v C in + v + v C C + v + q1 q2 d2 i2 gm 2b gm 2a d1 d4 d3 i 4a
17 1994fb lt1994 differential 1st order lowpass filter maximum C3db frequency (f 3db ) 2mhz stopband attenuation: C6db at 2 ? f 3db and 14db at 5 ? f 3db example: the speci? ed C3db frequency is 1mhz gain = 4 1. using f 3db = 1000khz, c11 abs = 400pf 2. nearest standard 5% value to 400pf is 390pf and c11 = c12 = 390pf 3. using f 3db = 1000khz, c11 = 390pf and gain = 4, r21 = r22 = 412 and r11 = r12 = 102 (nearest 1% value) differential 2nd order butterworth lowpass filter maximum C3db frequency (f 3db ) 1mhz stopband attenuation: C12db at 2 ? f 3db and C28db at 5 ? f 3db typical applications + C C + v + 0.1f 3 7 6 8 1 2 5 4 r21 c11 r12 r11 r22 c12 0.1f v in C v in + lt1994 v out C v out + 1994 ta03 component calculation: r11 = r12, r21 = r22 f mhz and gain mhz f db db 3 3 2 2 ? 1. calculate an absolute value for c11 (c11 abs ) using a speci? ed C3db frequency c f c inpfandf inkhz abs db abs db 11 410 11 5 3 3 = ? () 2. select a standard 5% capacitor value nearest the absolute value for c11 3. calculate r11 and r21 using the standard 5% c11 value, f 3db and desired gain r11 and r21 equations (c11 in pf and f 3db in khz) r cf r r gain db 21 159 2 10 11 11 21 6 3 = = .? ? + C C + v + 0.1f 3 7 6 8 1 2 5 4 r32 r31 c21 r12 r11 0.1f c11 v in C v in + lt1994 v out C v out + 1994 ta04 r22 r21 c22 component calculation: r11 = r12, r21 = r22, r31 = r32, c21 = c22, c11 = 10 ? c21, r1 = r11, r2 = r21, r3 = r31, c2 = c21 and c1 = c11 1. calculate an absolute value for c2 (c2 abs ) using a speci? ed C3db frequency c f c inpfandf inkhz note abs db abs db 2 410 2 5 3 3 = ? ()(2 2) 2. select a standard 5% capacitor value nearest the absolute value for c2 (c1 = 10 ? c2)
lt1994 18 1994fb 3. calculate r3, r2 and r1 using the standard 5% c2 value, the speci? ed f 3db and the speci? ed passband gain (gn) f mhz and gain or gain mhz f db db 3 3 188 1 ?? . r1, r2 and r3 equations (c2 in pf and f 3db in khz) r gn gn c f 3 1 121 1 131 0 127 10 12 8 3 = () () + () .? .?. ? ? ?? d db db note r rc f r r gn () .? ?? 1 2 1 266 10 32 1 2 15 2 3 2 = = example: the speci? ed C3db frequency is 1mhz gain = 1 1. using f 3db = 1000khz, c2 abs = 400pf 2. nearest standard 5% value to 400pf is 390pf and c21 = c22 = 390pf and c11 = 3900pf 3. using f 3db = 1000khz, c2 = 390pf and gain = 1, r1 = 549 , r2 = 549 and r3 = 15.4 (nearest 1% values). r11 = r21 = 549 , r21 = r22 = 549 and r31 = r32 = 15.4 . note 1: the equations for r1, r2, r3 are ideal and do not account for the ? nite gain bandwidth product (gbw) of the lt1994 (70mhz). the maximum gain is set by the c1/c2 ratio (which for convenience is set equal to ten). note 2: the calculated value of a capacitor is chosen to produce input resistors less than 600 . if a higher value input resistance is required then multiply all resis- tor values and divide all capacitor values by the same number. a single-ended to differential voltage conversion with source impedance matching and level shifting 1994 ta05 + C C + v + v t 0.1f 3 7 6 8 1 2 5 4 r s 50 374 50 54.9 402 402 402 0.1f v in v in lt1994 v ocm v out + v out C v ocm C 0.25v v ocm + 0.25v v out C v out + v ocm 0 1 C1 v t 0 typical applications
19 1994fb lt1994 package description dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.38 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.115 typ 2.38 p 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd) dfn 1203 0.25 p 0.05 2.38 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.50 bsc 0.675 p 0.05 3.5 p 0.05 package outline 0.25 p 0.05 0.50 bsc msop (ms8) 0307 rev f 0.53 p 0.152 (.021 p .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.1016 p 0.0508 (.004 p .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 o C 6 o typ detail a detail a gauge plane 12 3 4 4.90 p 0.152 (.193 p .006) 8 7 6 5 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc
lt1994 20 1994fb ? linear technology corporation 2005 lt 0309 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts rfid receiver front-end, 1khz < C3db bw < 2mhz (baseband gain = 5) part number description comments lt ? 1167 precision, instrumentation amp single gain set resistor: g = 1 to 10,000 lt1806/lt1807 single/dual low distortion rail-to-rail amp 325mhz, 140v/s slew rate, 3.5nv/ hz noise lt1809/lt1810 single/dual low distortion rail-to-rail amp 180mhz, 350v/s slew rate, shutdown lt1990 high voltage gain selectable differential amp 250v common mode, micropower, gain = 1, 10 lt1991 precision gain selectable differential amp micropower, pin selectable gain = C13 to 14 ltc1992/ltc1992-x fully differential input/output ampli? ers programmable gain or fixed gain (g = 1, 2, 5, 10) lt1993-2/-4/-10 low distortion and noise, differential in/out fixed gain (g = 2, 4, 10) lt1995 high speed gain selectable differential amp 30mhz, 1000v/s, pin selectable gain = C7 to 8 lt1996 precision, 100a, gain selectable differential amp pin selectable gain = 9 to 117 ltc6403 low noise, low power fully differential amp 11ma supply current ltc6404-1/ltc6404-2 ltc6404-4 600mhz ac precision fully differential amp available h-grade (C40c to 125c) lt6600-2.5/-5/-10/-15/-20 differential amp and lowpass, chebyshev filter filter cutoff = 2.5mhz, 5mhz, 10mhz, 15mhz or 20mhz typical application 0.1f 120pf 120pf 1994 ta02 5v 3 6 8 2 7 1 4 5 0.1f 120pf 120pf 140 140 1k 1k 1f 82pf 82pf 1f 5v i out lt1994 5v 3 6 *coilcraft 0603hp 8 2 7 1 4 5 0.1f 140 140 1k 1k 1f 82pf 10pf 10pf 270h* 10pf 10pf 82pf 1f q out lt1994 0.1f 5v 5v 270h* 270h* 270h* lo buffers 0/90 rf amp lt5575 rf rf amp lpf lpf i out + i out C q out + q out C i mixer q mixer lo

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