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ml2724 2.4ghz low-if 1.5mbps fsk transceiver final datasheet general descripti o n the ml2 724 is a fully in tegrated 1.5 m bps frequ e n cy shift keyed (fsk) tra n sceiver that o perate s in t he unlicen sed 2 . 4ghz ism frequ en cy ba nd. the devi c e has been o p timized fo r digital co rd less teleph o ne appli c ation s and i n cl ude s all the f r equ e n cy g ene ratio n , receive a nd t r an smit fun c ti ons. a u tomat i cally a d ju ste d filters eli m in ate me cha n i cal tu ning. clo s e d lo op modulatio n eliminate s freque ncy d r ift and perm i ts pra c tically u n limited tx duration. the tran smi tter gene rate s a 3 d bm fsk output sign al. the 1.5m bp s data rate permits data spreadin g , su ch as direc t sequenc e spread s pec trum (dsss) modulation, whi c h imp r o v es rang e. the d ual co nversi on l o w -if receiver ha s all of the sen s itivity and sele ctivity advantag es of a tradition al su per-hete r odyne witho u t requi rin g co stly, bulky exter nal filters, while p r ovidi ng the integratio n advantag es of direct con v ersio n . the pha se lo cked l oop (p ll) synthe si zer i s com p let e ly integrate d , in cludi ng the voltage co ntrolled o scill ator (vco ), tunin g ci rc uits, a n d vco r e s o n a tor. thi s all o w s the ml 2724 to be used in fre quen cy hopp ed sp re ad spe c tru m (f hss) applications. the ml 272 4 contai ns i n ternal volta g e regul ation. it also contain s pl l a n d tran smitter co nfiguration regi sters. th e device can be pl aced i n a lo w po wer stand by mod e for cu rrent se nsitive a p p licatio ns. it is packa ged in a 32tqfp. pin configuration ordering information p a rt # te m p ra nge p a ck a g e spec m l 2 7 2 4 d h - 1 0 o c to + 6 0 o c 32 pin tqfp 7mm x 7m m ds2724-f-01 features complete 2.4ghz fsk transc eiver - high d a ta rat e (1.5mb ps ) - -90dbm sensi t ivity (dsss modulation) - 3dbm output power (differential, typical) clo s ed l oop tx modulatio n low if recei v er: no external if filters required. fully integrat ed frequ en cy synthe sizer: - no extern al reso nator req u ired. sigma-delta fra c tional -n t w o-po rt modu lator automatic filt er alignment - no man u fact uring a d ju stm ents re qui red. no extern al d a ta slicer co mpone nts req u ired control outpu ts co rre ctly seque nce and control pa 3-wi re control interface analog rssi output appli c ations 2.4ghz fsk data tran sce i vers - digital cordl e ss t e leph one s - wirel e s s pc periph eral s - wirel e s s ga me cont rolle r s vcca rvl o tx o b tx o gnd r xm x2 gnd r xm x gnd r f rxi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 xc e n rxo n pa o n e n da t a cl k ao u t v s s fr e f rvpl l qpo gn dpl l v vr eg rvvco v t une gn d do ut v dd di n rvdm d rss i rvq m i f v bg gn dd md - wirel e s s stre aming me dia block diagram fi l t er a li g n m e n t pl l di v i d e r t x o/ t x ob 2. 4 g h z ou t p u t qu a d r a t u r e do w n m i x e r s q u a d ra t u re di v i d e r 1. 6 gh z vc o p l l lo op fi l t e r do u t re c e i v e d a t a ou t di n tra n s m i t d a t a i n re f . di v i d e r co n t r o l r e gi s t er s se r i a l co n t r o l b u s rs si p. d . fr e f f r eq ue nc y re f e re n c e mo de co n t ro l pa r a l l e l co n t r o l l i n e s di v i d e by 2 tw o - p o r t mo du l a to r f to v r ssi rx i 2. 4 g h z r e c e i v e i n pu t te s t m u x tp c pa o n rx o n xc e n da t a cl k en vt u n e qp o tra n s m i t mix e r b a nd ga p 2 a out ds272 4-f - 0 1 april 2003
ml2724 ds272 4-f - 0 1 final data sheet april 2003 2 table of contents general des cription ............................................................................................................ ............................... 1 pin config uration.............................................................................................................. ................................... 1 ordering in formation ........................................................................................................................................ 1 features....................................................................................................................... ............................................ 1 applicat ions................................................................................................................... ......................................... 1 block diagram .................................................................................................................. ...................................... 1 table of contents.............................................................................................................. .................................. 2 change log .............................................................................................................................................................. 2 simplified applicat ions diagram................................................................................................ ..................... 3 electrical cha racteris tics..................................................................................................... ........................ 4 pin descri ptions ............................................................................................................... ..................................... 7 functional d escription ......................................................................................................... .......................... 12 modes of o peration ............................................................................................................. ............................. 13 data inte rface ................................................................................................................. .................................... 15 control interfaces and re gister desc riptio ns .................................................................................. 1 7 data inte rfaces ................................................................................................................ .................................. 22 graphs..................................................................................................................................................................... 24 physical dimensions ( inches/millimeters ) ................................................................................................ 25 warranty ............................................................................................................................................................... 25 change log version date author changes/comments ds2724-f-01 4/23/03 mlj orig inate final datasheet
ml2724 simplified applications diagram b a seb a n d ic rx i pa o n do ut di n r ssi fr e f cl k, da t a , en xc en , r x o n 2 vc c a v t une qp o pa 3 t/ r swi t c h a n t e nna ln a ao u t m l 272 4 3 pa o n rx i 17 14 r vvc o tx o tx o 21 ba t t e r y an d p r ot e c t i on c i rcu it s en da t a cl k r ssi 9 fr e f 7 ao u t 32 do u t 28 5 4 6 30 din 1 xc en 2 rx o n 15 v t une 11 qp o tx o b tx o b 22 33n f 220n f 15 0 ? . 26 vb g 22 0nf f i g u r e 1: t y p i cal ml 2724 a p p lication dia g ram ds272 4-f - 0 1 final data sheet april 2003 3
ml2724 electri c al characteristi cs absolute m a xi mum ratings absolute ma ximum rating s a r e tho s e values beyo n d which the device could be pe rman e n tly dama g e d . ab solute maximum rati ngs a r e st re ss rating s only and functio n a l device o p e r ation is n o t implied. vcca, vdd ...................................................................................................................... .......................................... 5.5 v j u nc tion temperature ........................................................................................................... ................................... 150c storage tem perat ure ra nge...................................................................................................... ................ -65c to 150c lead temperature (s ol deri ng, 10s) .............................................................................................. ........................... 260c operating conditions normal temper ature range ....................................................................................................... .................. -10c to 60c vcca range ..................................................................................................................... .............................. 2.7v to 4.5v vdd range ...................................................................................................................... ............................... 2.7v to 3.3v therm a l re si st an ce ( ja ) .............................................................................................................................. ......... 70c/w unle ss otherwise spe c ifie d, vcca=v dd=3.3v, t a =25 c, f ref =6.144m hz, data rate =1.536 mbps, 13k hz loop filter a s sho w n in fig u re 1. s y m b o l p a r a m e ter c o n d i t i o n s m i n t y p m a x u n i t s power consumption v c c a a n a l og su ppl y ( v c c a ) 2 . 7 3 . 3 3 . 8 v v d d d i g i t a l sup p l y voltag e vdd pi n (vcc a vdd al w a ys) 2 . 7 v c c a v v bg b a n d ga p volta g e vbg pin 26, i o =0 a 1 . 2 3 v i st b y supp l y c u rrent, st andby mode dc su p p l y con nected, xcen lo w 10 120 a i rx supp l y c u rrent, receive mode rx ch ai n activ e , data be ing r e ceiv ed 55 76 ma i tx supp l y c u rrent, t r ansmit mode p out = 3dbm 50 76 ma synthesizer f c carrier freq ue n c y ran ge 2.4 2.485 ghz f cha nne l spac i ng 204 8 khz i p char ge pump sink/sourc e cur r ent + / -5.5 ma n phase n o is e at t x o 1.2mhz 3mhz >7 mhz close d lo op, lo op filter ba nd w i dth 13khz (se e figure 1 ) -95 -115 -125 dbc/hz t fh lock time for chan nel s w itc h f r om en asserted to rx va lid data(r x ), or p a on high (t x) 1 c h an ne l 5 c h an ne l s f u ll ra nge 110 185 250 125 220 300 s s s t tx 2 r x lock time for t x /r x rxon h i g h to vali d r x data 70 120 s t rx2 t x lock time for r x /t x rxon l o w to paon high 63 75 s t w ake lock up time fr om standb y xce n hi gh to vali d r x data, xce n l o w pe ri od >1 20 se co nd s 2 4 0 3 2 5 s ds272 4-f - 0 1 final data sheet april 2003 4
ml2724 s y m b o l p a r a m e ter c o n d i t i o n s m i n t y p m a x u n i t s f fref refere nce sig n a l frequ enc y 6.144 12.28 8 m h z mhz v fref refere nce sig n a l in put lev e l 6.144m hz or 1 2 .288m hz sine w a v e , capacitiv el y co upl ed 2 . 0 v c c a v pp receiver z in receiv er in put impe danc e f c= 2445m hz 2.2+ j0 ? nf receiv er no ise figure f c= 244 5 m h z 1 6 . 5 d b dr rx data rate f sk modulati o n, f dev = + / -512k h z 1 . 5 3 6 m b p s s input sensitiv ity < 12. 5% cer a t 1.536mchi p /s < 10e-3 ber at 1.536mb p s - 8 2 - 9 0 -81 d b m dbm bw rx b a n d w i d t h 3db ban d w i dth 7 7 0 k h z p im ax maximum r x rf input < 12.5% cer a t 1.536mchi p /s < 10e-3 ber at 1.536mb/s +5 -4 d b m dbm i ip3 receiv er input ip3 t e st tones 2 and 4 cha n n e ls a w a y -15 dbm lo leaka ge at rxi -60 dbm irr mixer image r e jecti on rati o meas ur ed at 3. 5mhz offset 35 db adjac ent cha n nel re jectio n -80dbm w a nte d sign al < 1 0 -3 ber sing le 2gf sk modu lated i n te rferer w i t h a 1.5mhz ?20 dbc ba nd w i dth 1 channel a w a y 2 channels a w a y 3 or mor e channels a w ay 6 31 36 db db db if f i lters f ifc if filter center frequ enc y after au tomatic f ilter alignm ent 1.024 mhz bw if if filter 3db band w i dth after automatic f ilter alignm ent 140 5 khz limiter, a g c , a nd fm de modul a t or t ovld recov e r y from overl oad f r om + 15dbm at input 5 12 s e b / n o f o r 10 -3 ber 10.5 db co-ch a n nel re j e ction, 10 -3 ber -80 dbm, mod u late d w i th 1.536m bps gf sk, bt = 0 .5, prbs data 1 0 . 5 d b v odc quiesce nt voltage @ aout 1.1 v v opk output voltag e s w i ng aout 0.55 1.1 v pp v ol aout open-dr ain vo ltag e i o = 100 a, t p c mode 0 . 4 v rssi perform a n ce t r r ssi rssi rise time no signal to -15dbm i n to the if mixer 20 pf loa d , 20 % to 80% 4.5 s t fr ssi rssi fall time, < -15dbm to no signal into the if mix e r 20 pf loa d , 20 % to 80% 3.0 s g rs mid r s s i sensitivit y (v - 40db m ? v -60 d b m ) / 2 0 d b 2 8 3 6 4 2 m v / d b v rs mx rssi maxim u m voltage see f i gur e 3 1.8 2.3 v v rs md rssi midran ge voltage -40 dbm into r x i 1.4 1.7 2.0 v ds272 4-f - 0 1 final data sheet april 2003 5
ml2724 s y m b o l p a r a m e ter c o n d i t i o n s m i n t y p m a x u n i t s v rs mn rssi minimum voltage no sig nal i n to rxi 75 mv v rs mxc rssi maxim u m voltage (cl i p ped) -10 dbm into r x i 1.6 1.95 v tr a n smit rf mixer p ose output po w e r, singl e en de d t r xo or t r xob, f c = 2 .445 ghz -3 1 5 dbm p odif o u t p u t po w e r, differenti a l p ( t rx o,t rx ob) , f c = 2 .445 ghz -1 3 6 dbm z ou t output imped a n ce t r xo or t r xob, f c = 2 . 4 4 5 g h z 1 2 + j 0 ? tr a n smit m o dul a t ion f de v modu latio n de viatio n, @2.4ghz 200 us of conse c utive ?1 ?s or ?0 ?s 500 512 524 khz f os modu latio n cen t er frequenc y offset 50us after r x on lo w -50 + 50 khz tr a n smit da t a filter bw tx t r ansmit data f ilter band w i dt h 3db ban d w i dth 1.4 mhz t x s p u r i o u s image - 2 5 -20 d b c dbc interf a c e l ogic leve ls inputs (di n , xcen , rxon, d a t a , clk, en) v ih input hig h volta ge (never e x c eed vdd) 0. 7 5 * v dd v d d v v il input lo w vo lta ge 0 0. 2 5 * v d d v i b input bias c u rrent -5 0 5 a c in input cap a citan c e (measur ed at 1 m hz) 4 pf outputs ( d out, p a o n ) v oh dout high vol t age i o = 0 . 1 m a v d d - 0 . 4 v v ol dout lo w v o lt age i o = - 0 . 1 m a 0 . 4 v i o dout sink/source current 0.1 ma v oh paon output h i gh vo ltag e sour ci ng 0.5 m a vdd-0.4 v v ol paon output l o w v o lta ge si nki ng 0.5 ma 0.4 v i o paon source/ s ink curre nt 0.5 ma 3 wire seri a l bus timing t r clk in put rise time 15 ns t f clk in put fall ti me 15 ns t ck c l k per i o d 5 0 ns t ew c l k pu lse w i d t h 1 0 0 ns t l dela y from l a st clk falli ng e d ge 15 ns t se en setu p tim e to ig nore ne xt rising c l k 1 5 ns t s d a t a -to-clk s e t u p t i m e 1 5 ns t h d a t a -to-clk hol d t i m e see f i g u r e 4 1 5 ns ds272 4-f - 0 1 final data sheet april 2003 6
ml2724 pin descriptions pin sign a l na me i / o f u n c t i o n di a g r a m power & gr ound 8 vss gnd digital ground. ground for digital i/o circuits an d co ntrol lo gic. n/ a 10 rvpll pw r pll sup p l y . d c po w e r supp l y deco upl in g poi nt for the pll divid e rs, phas e detector , and charg e p u mp. t h is pin is co nn ecte d to the output of the regu lator a nd to the pll su pp lies. t here must be a 22 0 n f capacitor to groun d from this pin to decou pl e (b yp ass) nois e and to stab iliz e the regul ator. see pin 1 1 be l o w . 12 gndpll gnd ground for t he pll div i ders, p hase detector, an d charg e pum p. n/ a 13 vvreg pw r dc po w e r s u p p l y i nput to the vco voltag e reg u lat o r. must be connecte d to rvqmif (pin 27) or rvdmd ( p in 2 9 ) via deco upl in g net w o rk. n/ a 14 rvvco pw r dc po w e r sup p l y dec ou pli ng poi nt for the vco. connect ed to the outp u t of the vco regul ator. a 220nf cap a c itor must be tied b e t w e e n this pin a nd g r oun d to deco upl e (b yp ass) nois e an d to stabiliz e the regu lator. n/ a 16 gnd gnd dc gro und for vco and lo ci rcuits. n/ a 18 gndrf gnd ground retur n fo r the rece ive rf input and t r ansmit rf output. ( p in 2 4 ) ( p in 8 ) vs s g n drf rx i vc c a 0. 7v vc c a vs s 4k 17 18 8 24 19 gndr xm x gnd sign al gro u n d for the rece ive mixers. n/ a 20 gndr xm x2 gnd sign al gro u n d for the rece ive mixers. n/ a 23 rvlo pw r dc po w e r sup p l y dec ou pli ng poi nt for the lo chai n. con nected to the o u tput of a regu lator. a 22 0nf capac itor must be tied bet w e en this p i n and gr ou nd to deco u p l e (b ypass) n o ise and to stab iliz e the regu lator. n/ a ds272 4-f - 0 1 final data sheet april 2003 7
ml2724 pin sign a l na me i / o f u n c t i o n di a g r a m 24 vcca pw r dc po w e r sup p l y i nput to vol t age reg u lators a n d unreg ulat ed lo ads: 2.7 to 3.8v. vcca is the main (or m a ster) ana log vc c pi n. t here must be capac itors to groun d from this pin to deco upl e (b yp ass) supp l y noi se. n/ a 25 gnddmd gnd dc gro und to if, demodul ato r , and data slicer circuits. n/ a 27 rvqmif pw r dc po w e r sup p l y dec ou pli ng poi nt for quadratur e mi xer a nd if filter circuits. a 220 nf capac itor must be tied bet w e e n this pin a nd gr oun d to deco u p le (b yp ass) nois e an d to stabil i ze the re gu lator. n/ a 29 rvdmd pw r dc po w e r sup p l y dec ou pli ng poi nt for if , demo dul ator, and d a ta slic e r circuits. a 220 nf capac itor must be tied bet w e e n this pin a nd gr oun d to deco u p le (b yp ass) nois e an d to stabil i ze the re gu lator. n/ a 31 vdd pw r dc po w e r sup p l y in put to the interface logic and c ontr o l reg i sters. t h is supp l y is not conn ected i n terna l l y to an y other supp l y pin, b u t its voltage mus t be less than or eq ua l to the vcca su ppl y a nd greater tha n 2. 7v. a capacitor must be tied bet w e e n this pin a nd gr ou nd to deco upl e (b yp ass) nois e . n/ a tr a n smit/receive 17 rxi i (analo g ) receiv e rf input. nomin a l i m ped ance at 244 5 mhz is 2.6-j2.6 w i t h a si mple matchin g net w o rk requ ired for optimum nois e figure. t h is in put con n e c ts to the base of a n np n transistor an d shou ld b e ac coup led. g n drf ( p in 2 4 ) ( p in 8 ) vs s rx i vc c a 0. 7v vc c a vs s 4k 17 18 8 24 21 t x o o (analo g ) t x rf open-co llector o u tput. t h is output requ ires a dc path to vcca. ds272 4-f - 0 1 final data sheet april 2003 8
ml2724 pin sign a l na me i / o f u n c t i o n di a g r a m 22 t x ob o (analo g ) compl e me ntar y t x rf open- collect or output. t h is output requir e s a dc path to vcca. f o r single- end ed o u tp ut app licati ons, th is pin sh oul d b e conn ected to a dumm y l o a d that incl ud es a dc path to v cca. tx o b tx o gn d r f 18 21 22 da t a 7 a o u t a (anal o g ) multi-func ti on output. in anal og outp u t mode this is o u t put drives an off chip data slic er. in t r ansmit po w e r control mode this is a n open dr ai n out put, w h ich is pull ed l o w w hen the t p c bi t is serial register # 1 , is clear. t r ansition s on t p c are s y nchr oniz ed to the fall ing edge of rxon. in an al og test modes this pin a nd the rssi outpu t become test access poi nts controll e d b y th e seria l control bus. 31 vss vdd 100 ? 7 a out 8 tp q mu x vss 8 tp c mu x tp c a out mu x 30 din i (cmos) t r ansmit data input. drives the transmit puls e sha p in g circuits. seria l digit a l dat a on this pi n bec omes f sk modul ation on the t r ansmit rf output. t he logic timi ng on this pi n cont rols data timi ng . internal circuits determ i ne the mod u l a tion devi a tion. t h is is a standar d c m os input referenc ed to vdd and vss. see pin 1 bel o w . 32 dout o (cmos) serial dig i tal o u tput after dem odu latio n , chip rate filter in g and ce nter d a ta slici ng. a cmos level output (vss to vdd) w i th control l ed sl e w rates. a lo w dr ive outp u t desi gne d to dri v e a pcb trace and a cmos logic i n put w h i l e g ener ating minima l rf i. in digita l test modes this pi n becom es a test access port co ntroll ed b y the seria l contr o l bus. 31 vss vd d 25 0 ? 32 do ut 8 ds272 4-f - 0 1 final data sheet april 2003 9
ml2724 pin sign a l na me i / o f u n c t i o n di a g r a m mode control a nd int e rf a c e lines 1 xce n i (cmos) enab les the b a ndg ap refer enc e and voltag e reg u lat o rs w h e n hig h . cons umes onl y l eaka ge c u rrent in st andby mode w h e n lo w . t h is is a cmos inp u t, and the thresho l ds are referenc ed to vdd an d vss. 2 r x o n i ( c m o s ) tx/rx control input. switche s the transceive r b e twee n tra n smit and receive mo des. ci rcuits are pow ere d up a nd sig nal pat hs reconfigu r e d according to the operating mo de. this i s a cmos input, and the thresh old s are referen c ed to vdd and vs s. 1 vss xcen vdd rxon din 2 30 31 8 3 paon o (cmos) pa control out put. enabl es th e off-chip pa at the correct times in a t r ansmit slot. goes hig h w h e n transmit rf is present at t x o; goes l o w 5 s befor e transmit rf is removed from t x o. has interlock logic to shut dow n the pa if the pl l does n o t lock. 31 vss vd d 3 pao n 8 9 f r ef i input for the 12 .288 mhz or 6. 144 mhz referenc e frequ enc y. t h is inpu t is used as the refere nc e freque nc y f o r the pll and as a c a li br ation freq ue nc y for the on- chip filters. an ac-cou ple d sin e or squar e w a ve s ource dr ives thi s self- bias ed in put. 9 vss fre f vcc a 24 8 40 k 40 k ds272 4-f - 0 1 final data sheet april 2003 10
ml2724 pin sign a l na me i / o f u n c t i o n di a g r a m 11 qpo o char ge pump output of the phase detector. t h is is connecte d to the ext e rna l pll l o op filter. 10 vss rv p l l 11 qp o 8 15 vt une i vco t uning v o ltag e in put from the pll loo p filter. t h is pin is ver y se n s itive to nois e cou p li ng and l eak age cu rrents. 24 vs s v cca 3.7 k 15 v t une 8 1.2 5 v 26 vbg o band ga p deco upl e volta ge. deco upl ed to groun d w i th a 220 nf capac itor. n/ a 28 rssi o buffered an alo g rssi output w i t h a nomi nal se nsiti v it y of 35mv/d b . in analo g test modes, this pin an d the a o ut output becom e test access poi nts controll ed b y the seria l contr o l bus. 24 vs s vc c a 100 ? 28 r ssi 8 tp i mu x r ssi mu x r ssi op am p ds272 4-f - 0 1 final data sheet april 2003 11
ml2724 pin sign a l na me i / o f u n c t i o n di a g r a m seri a l bus sign a l s 4 en i (cmos) contro l bus en abl e. enab le pi n for the three- w i r e seri al contro l bus that sets the oper ating fre q u enc y an d pro g r a mmabl e optio ns. t he control re gisters are loa d e d on a lo w - t o -hi g h transitio n of the sig nal. serial c ontrol b u s data is ig nor ed w h en this sign al is hi gh. t h is is a cmos input, and the thr e sh olds ar e refere nced to vdd and vss. 5 dat a i (cmos) serial c ontro l bus data. 16- b i t w o r d s, w h ich i n cl ude progr ammin g d a ta and th e t w o- bit ad dress of a control, register. t h is is a cmos inp u t, and the thre shol ds are referenc ed to vdd and vss. 6 clk i (cmos) serial c ontrol b u s data is cloc ked in o n the risin g ed ge w h en en is l o w . t h is is a cmos input; the thresh ol ds are referenc ed to vdd and vss. 31 vs s vd d 5.5k 4 en 8 1.7p 5 da t a 6 cl k functional descri ption the ml2 724 is a fully integrate d 1.5m bps frequ en cy shift keyed (fsk) tran sceiver th at operate s in th e unlicen sed 2.4gh z ism f r equ en cy ba n d . the device ha s be en opt imized fo r dig i tal co rdle ss t e leph one app lication s a nd i n clu d e s all the frequ en cy gene ration, receive a nd transmit fun c ti ons fo r a ra w data rate of 1.5mbp s. thi s high d a ta rate allow s for data spreading, such as dire ct sequence spread spectrum (dsss) modulation, which im proves range. the ml2724 receiver a r ch itecture i s a dual co nversi on l o w if, whi c h ha s all of the sen s itivity and se lectivity adva n tage s of a traditional su per-hete r ody ne re ceive r w i thout requi rin g co stly, bulky external filters. fi l t e r a l i gn me nt pll di v i de r tx o / tx o b 2. 4 g h z ou t p u t q u adr atur e dow n mi x e r s q u adr atur e di v i de r 1.6 g h z vco p ll lo op fi l t er do u t rec e i v e da ta ou t di n t r an s m i t d a ta i n ref . di v i d e r co nt r o l r e gis t er s se r i a l co nt r o l b u s rssi p. d . fr e f f r equ enc y ref e r e n c e mo de c ontr o l pa r a l l e l co n t r o l l i n e s di v i de by 2 tw o - p o r t mo du l a to r f to v r ssi rx i 2. 4 g h z rec e i v e i npu t te s t m u x tp c pao n rx o n xc en dat a clk en v t une qp o tra n s m i t mi x e r b a ndga p 2 a ou t f i g u r e 2: ml 2 724 in tern al b l o ck diag ram ds272 4-f - 0 1 final data sheet april 2003 12
ml2724 the r f mixe r do wn -conve r ts the 2.4g h z rf in put signal to th e first intermediat e freq uen cy (if), wh ere it i s filtere d to remove adja c ent ch ann el signal s. an a c tive image rej e ct mixer con v erts thi s si g nal do wn to a low if freq u ency, w h e r e the data i s l i mited, filtere d , and d e mo dulated. thi s architec tu re provide s all the ben efits of dire ct co nversi on to baseba nd w h ile maintainin g the stability and ro bu stne ss of a tra d itional supe r-he terodyne. a single synt hesi z e r is u s ed for both th e receiver an d the fsk transmitter. th e pha se lo cked loop (p ll) is compl e tel y integrate d , includi ng the voltage control l ed oscillato r (vco ), tuning circuits, and vco re so nat or. in receive mode , the ml272 4 is a dual conve r si on lo w if re ceiver. no e x tern al saw filters ar e r e quired . the integrate d im age reje ct m i xer give s su fficient rej e cti on in this chann el. all chann el filteri ng a nd dem odulatio n i s perfo rmed u s ing active filters, w h ich ar e automatical ly aligned. a matched bit rate filter and a data slice r follow the demod ulato r . the sli c ed d a t a is provide d at the dout pin, and the analo g data i s availabl e at aout. in tran smit mod e , the ml27 24 gen erate s a 2.4 g h z o u tput u s ing the t r an smit mixer. an auto-align e d tran smit d a ta filter and m o dulation com pen sation circuit results i n an a d ju stm ent-fre e tra n s mitter. th e vco i s mo d u lated by the transmit data , which i s pu t through a sigma - d e lta fractio nal -n p ll en suri ng modulatio n a c cura cy. this modulation occurs w h ile the pha se lo cked lo op is cl ose d , thus all o win g pr actically infinite transmit or re ceive times wi th excellent freque ncy accuracy and stability. a 3dbm fsk-mod u lated diffe re ntial sig nal i s output at th e txo/txob pins at the 2.4gh z carri e r freq uen cy. the i n tegrate d pll freq ue ncy synthe sizer i n clu d e s a fully int egrate d vc o, p r e s caler, pha se d e tector a nd charg e pump. the referen c e freq uen cy i s g ene rated from the in co ming sign al at the f r ef pin, w h ich ca n be eithe r 6 . 144mh z or 12.288m h z . the lo op filte r is external t o allo w cu sto m ers to opti m ize th eir loo p ba nd width t o their sy ste m ?s lo ck time and i n -band pha se noi se requi rem ents. thi s freq ue ncy-a g ile syn t hesi z er all o ws the ml2 7 24 to be u s e d in freq uen cy hopp ed spre ad spe c trum (fhss ) ap plicatio ns wit h nomin al chann el spaci ng of 2.04 8 m hz. ca rrie r freque ncy i s prog ram m ed via the config uration regist ers an d 3 - wi re serial interf ace. the vc o tan k circuit (ind ucto r a n d vara cto r) i s fully integrated. qp o rvvco 220nf 150 : 33nf vtune examp l e 13 k h z l o o p filter modes of operation there are th ree key mod e s of ope ration : ? standby: all circuits po wered do wn, except the control interface (static cmo s ) ? receive: re ceiver circuits active ? transmit : modulate d r f output from ic the two op e r ational m o d e s are re c e ive and transmit, c ontrolle d by rxon. xce n is the chip enable/di sab l e control pin, w h ich sets the part in ope rat i onal or sta ndby mod e s. the relation ship bet wee n the parallel control lines and the mod e of operation of the ic is given in table 1 . x c e n r x o n m o d e f u n c t i o n 0 x st andby contro l interfac es active, all ot her circuits p o w e r e d do w n 1 1 r e c e i v e receiv er t i m e s l o t 1 0 t r ansmit t r ansmit t i m e s l o t t a b l e 1: mo d e s o f op eratio n ds272 4-f - 0 1 final data sheet april 2003 13
ml2724 mode cont rol the m l27 24 is i n tend ed for use in tdd an d t d ma radio s in battery -po w ered equi p m ent. to mi nimize po we r con s um ption it is desig ned to switch rap i dly from a lo w po we r mod e (stan d by) to an active mode. the ml272 4 ca n also ma ke a quick tran sition from re cei v e to tran smi t for td d o p e ration. p r ior to tran smitting o r re ceivi ng, time sho u ld be allo wed fo r the pll to lock and fo r the filters to ali gn. whe n the ml272 4 is o perate d in si n g le-ca rrie r td d mod e , the lo i s autom atically shifte d by th e se cond (lo w ) if freque ncy w h en the devi c e is swit ched betw een re ceive and transmit modes . ml272 4 carri e r freque ncy can be ch ang ed (hop ped ) at any time , b u t is u s u a lly chang ed b e tw een tran smission s. c a rrie r freque ncy (chann el) i s m odified in the ml272 4 by writing a corresp ondi ng n e w value to t he pll fre q u ency regi ster (re g iste r 1) recei v e the ml 272 4 use s a dou bl e-conve r si on sup e r-hete r o d yne receiv e r with a nomin al se co nd if of 1.024 m h z. the si gnal flow in rece ive mode is f r om the rf i n put, throug h an rf do wn -conve r si on m i xer and i n teg r ated if filter, image reje ct quad ratu re m i xer, integrate d low if filter, hard limite r , frequen cy to voltage con v erter, and d a ta filter to th e aout pin and data sli c er wh ere the digital nr z d a ta is avail a b l e at th e do ut pin. a 20 db ste p ag c extend s th e dynamic rang e of the receiver. the ml2 724 receive ch ain is a lo w if receiver u s ing advan ce d integrated radio techniq u e s to elimina t e external if filters and mi nimize exte rn al rf filter requireme nts. the pr e c i s io n filtering an d demod ulati on circuit s gi ve improved perfo rman ce over co nventi onal ra dio de sign s usi ng e x ternal filters while p r ovidin g integratio n comp arable to advanced dire ct conve r sion radio d e s ign s . receive signal str e ngth i n dication (rssi) rssi is an indicatio n of field stren g th. it can be u s e d to cont rol tran smit pow er to con s erve bat tery life or it may be used to determin e if a given cha nnel is o c cupi ed. see figure 3. figure 3 : rss i volta g e v s . input sig n a l l e v e l automatic filter alignment whe n the ml272 4 is pla c ed in rec e ive mode, it automatical ly tunes all the intern al filters u s ing t he refe ren c e freque ncy fro m the fref pin. wh en th e chi p is po w e red up (vd d first applie d), the tunin g informatio n i s reset to mi d- range. this self-calibration sets: discri minato r cente r freq ue ncy if filter center frequen cy an d band width ds272 4-f - 0 1 final data sheet april 2003 14
ml2724 ? re ceiver d a ta low-pa ss filter ban dwi d th ? tran smit data low-p a ss filter band width transmit mode in transmi t mode, th e pll is clo s e d to eliminate f r equ en cy drift . a two-p o rt modulato r m o dulate s both t he vc o an d the fra c tional -n pll. t he vco i s di rectl y modulated with f iltere d f sk transmit d a ta. the pl l is d r iven by a sigm a-d e lta modulato r , w h ich e n sure s that the pll follow s the me an frequ en cy of the modula t ed vco. the tran smit modulatio n fil t er is autom a t ically tuned durin g eve r y receive time, alleviating the ne ed fo r prod uctio n alignme n t. asserting rxo n enabl es th e ml272 4. the risi ng edg e of xcen triggers a comp lete calib ratio n of all the on- chip filter s, w h ich ta ke s u p to 256 p s, w h ich en sures the modul ation filters are aligne d to p r event un wa n t ed sp urio us emission s. pll programming & channel selection the m l272 4 pll is prog ra mmed via co ntrol r egi ster 2 to the set r f ce nter f r eq uen cy of op eration of the radio. th e pl l doe s not nee d to be (thou gh it can be ) reprogramm ed bet w een receive an d transmit modes. n o minal ch ann e l sep a ratio n is 2.048mh z , allowin g for o v er 40 non -o verlappi ng ch annel s in any given locatio n . with care ful planning, cha nnel s ca n be program med i n 1 024 khz ste p s a s l ong as care i s exe r cised t o in su re th at two ra dio li nks will not sh are spe c tru m at a n y one time. the equatio n to dete r min e ch ann el cent er frequ en cy from the ml 2 724 co ntrol registe r wo rd is: f c = chq < 0:11>* 1 .024 m h z standby mode in standby mode, the ml272 4 tran sceiver is po we red do wn. th e only circuits active are th e control interface s , whi c h are digital c m os to minimize po we r consumption. the se rial co ntrol interfa c e and co ntrol registe r s rema in pow ere d u p and will a c ce pt and retain prog ram m ing data a s lon g as the digital sup p ly is p r e s ent. whe n exi t ing stan dby mode, the device may n eed to be kep t in receive mode for up to 256 p s to allow for filter self-calibration. test m o de the r f to di gital functio n a lity of the ml272 4 requ ires sp ec i a l test mo de circuitry for i c prod uctio n te st and ra dio debu gging. a test registe r , acce ssibl e via the 3-wi re seri al inte rfa c e, co ntrol s the test multip lexers. (se e table 15 ). data interface there are tw o control interface s : co nt rol a nd serial. control interface the co ntrol in terface provid es imme diate control a nd monitori ng of the ml272 4. input sig nal s inclu de: ? xcen: tran sceiver e nable. places the ml2724 i n standby or active (wh en asserte d ) mo des. ? rxon : re ceive on. place s an act i ve ml2724 i n re ceive mo de wh en a s serted. ? fref: referen c e fre quen cy input output sig nal s incl ude: ? rssi: re ceived sig nal strength i ndicator: indi cate s the po wer of the received sig nal ? paon: external pow e r amplifier c ontrol pin serial interf ace a 3-wire se ri al interface (en, data, clk) is used for pr o g rammi ng the ml27 24 config uration regi sters, whi c h co ntrol device mod e , pin fun c tion s, pll and referen c e divi ders, inte rnal test m ode s, and filter ali gnment. dat a w o rd s are ds272 4-f - 0 1 final data sheet april 2003 15
ml2724 entere d be gi nning with th e msb (?bi g -endia n ?). the word is divided into a le a d ing 14 -bit d a ta field follo wed by a 2-b i t address field. when the a ddre s s field has be en de cod ed the de stination regi ster is lo ade d on the risin g edge of en. pro v iding le ss tha n 16 bits of da ta w i l l result in unpredictable behav i or w h en en goes high. data an d clo ck sign als a r e ignored w h en en is hig h . when en is low, data on the data pin is clo c ke d into a shift regi ster on th e risi ng e dge of the clk pi n. this info rm ation is lo ade d into the target co ntrol re gister wh en e n go es hi gh. this seri al int e rface bu s is similar to th at comm only f ound on pl l device s . it can be effici en tly progra m m ed by either byte or 1 6 -bit wo rd o r ie nte d se rial bu s hard w a r e. t h e data l a tch e s a r e im plem ented in cm os and u s e minimal p o w e r whe n the bu s is in active. refer to fi gure 4 and t able 2: 3-wi re bus timi ng cha r a c teri stics fo r timing and regi ster prog ram m ing illustration s. s y m b o l p a r a m e t e r m i n t y p m a x u n i t bus cl oc k (c lk) t r clk input rise time 15 ns t f clk input fall time 15 ns t ck c l k p e r i o d 5 0 n s en a b le (en) t ew minimum pulse w i dth 100 ns t l dela y fr om last clk rising edge 15 ns t se set up time to ignore ne xt rising clk 15 ns bus d a t a ( d a t a ) t s data to clock set up time 15 ns t h data to clock hold time 15 ns t a b l e 2: 3-w i r e bu s t i min g ch ara c teristic s t s t r t f t ew t t l ms b t h ck clk da ta en da t a ad d r e s s ls b f i g u r e 4: serial bu s t i ming fo r a d d r ess a n d data pro g r ammin g ds272 4-f - 0 1 final data sheet april 2003 16
ml2724 control interfaces and re gister descri ptions register information a 3-wi re se ri al data in put bus set s the ml272 4?s t r a n sceive r pa ra meters an d p r og ram s the pll ci rcuits. entering 16-b i t words i n to th e ml27 24 se rial inte rface perfo rms pro g rammi ng. t h ree 16 -bit re gisters a r e p a rtitioned su ch that 14 bits are de dicate d for data to prog ram the operatio n a nd two bi ts i dentify the registe r add re ss. the cont ents of these regi sters can not be rea d b a ck via this b u s. the thre e reg i sters are: r e g i st e r 0: pll config uration r e g i st e r 1: cha nnel f r eq uen cy data r e g i st e r 2: internal test access figure 5 sh o w s a regi ster map. ta ble 3 throu gh t abl e 5 p r ov ide d e tailed di agra m s of th e reg i ster org ani za tion: table 3 and tabl e 4 outline the pll co nfiguration and chan nel frequ en cy registe r s, an d table 5 di splays the filter tuning an d test mode reg i ster. res. db 1 3 ms b b1 5 db 1 2 b1 4 db 1 1 b1 3 db 1 0 b1 2 db 9 b1 1 db 8 b1 0 db 7 b9 db 6 b8 db 5 b7 db 4 b6 db 3 b5 db 2 b4 db 1 b3 db 0 b2 ad r 1 b1 ad r 0 b0 res. re s . r es. rclp lv lo re s . tx m tp c tx c w r es. ao u t rd 0 qp p 0 0 res. db 1 3 ms b b1 5 db 1 2 b1 4 db 1 1 b1 3 db 1 0 b1 2 db 9 b1 1 db 8 b1 0 db 7 b9 db 6 b8 db 5 b7 db 4 b6 db 3 b5 db 2 b4 db 1 b3 db 0 b2 ad r 1 b1 ad r 0 b0 res. ch q 1 1 ch q 1 0 ch q 9 ch q 8 ch q 7 ch q 6 ch q 5 ch q 4 ch q 3 ch q 2 ch q 1 ch q 0 0 1 res. db 1 3 ms b b1 5 db 1 2 b1 4 db 1 1 b1 3 db 1 0 b1 2 db 9 b1 1 db 8 b1 0 db 7 b9 db 6 b8 db 5 b7 db 4 b6 db 3 b5 db 2 b4 db 1 b3 db 0 b2 ad r 1 b1 ad r 0 b0 res. re s . r es. res. res. re s . res. dtm 2 dtm 1 dt m 0 at m 2 at m 1 at m 0 1 0 figure 5 : conf igura t ion re gi s t e r ma p ds272 4-f - 0 1 final data sheet april 2003 17
ml2724 n a m e d e s c r i p t i o n d e f i n i t i o n r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d set all bits to 0 (zero) rclp rssi clip disable 0: rssi clipped to 1.9v at ?15db m 1: rssi not clipped lvlo lo w voltage loc kout 0: paon u ndisturbed 1: paon d e -asserted fo r vcca< 2 .65v. reset on rxon high reserved reserved set to 0 txm tx rf output m ode 0: tx rf outp ut alw a ys on in tx mode 1: tx rf outp ut follow s paon si gnal tpc transmit po w e r control 0: aou t pin pulled to grou nd 1: aou t pin high impedance txcw transmit test m ode 0: fsk modulatio n in transmit mo de 1: cw (no mo dulation in transmit mode) reserved reserved set to 0 aout analog output 0: aou t pin is transmit power c ontrol 1: aou t pin is analog data out rd0 reference frequ enc y select 0: 6.144mhz no minal reference f r equenc y 1: 12.288mhz no minal reference f r equenc y (pr e fer r ed) qpp pll charg e pum p polarit y 0: for fc < fr ef, charge pum p sour ces current 1: for fc < fr ef, charge pum p sinks current adr1 msb address bit adr1=0 adr0 lsb address bit adr0=0 ta ble 3 : re gis t e r 0 -- pll c onfi gura t ion re gis t e r n a m e d e s c r i p t i o n d e f i n i t i o n reserved reserved set all bits to 0 (zero) chq1 1 chq1 0 chq9 chq8 chq7 chq6 chq5 chq4 chq3 chq2 chq1 chq0 channel f r eque ncy select bits divide ratio=f c /1.024 adr1 msb address bit adr1=0 adr0 lsb address bit adr0=1 ta ble 4 : re gis t e r 1 ? cha nne l fre que nc y re gis t e r ds272 4-f - 0 1 final data sheet april 2003 18
ml2724 n a m e d e s c r i p t i o n d e f i n i t i o n reserved reserved reserved reserved reserved reserved reserved reserved reserved set all bits to 0 (zero) dtm2 dtm1 dtm0 digital test cont rol bits see table 16 atm2 atm 1 atm 0 analog test con t rol bits see table 15 adr1 msb address bit adr1=0 adr0 lsb address bit adr0=1 t a b l e 5: reg i ster 2 ? t est m o d e reg i ster po wer-on state on pow e r up , a l l re g i s t e r b i ts a r e c l ea r e d to th e de fa u l t va l u e o f 0 (z er o) . po w e r up is d e f i n e d as oc cu rr i n g wh en vdd ! 2.0v. the regi ste r de fault values a r e valid upo n pow er up. control register bit descri ptions adr<1:0>, all registers, bit s 0-1 addre ss bits: th e ad r < 1:0 > bits are the lea s t-si gnifica nt bits of each re gister. each reg i ster i s divide d into a data field and an address field. the data field is the leadi ng field, whil e the last two bits clocke d into the regi ster are always the add re ss f i eld. w hen e n go es hig h , the add re ss f i eld is de co d ed an d the a ddre s sed de stination regi ster i s lo aded. the la st 16 bits cl ocke d i n to the serial bus are l o a ded into th e regi ster. clo c king i n less t han 1 6 bits result s in a potentially incorrect ent ry into the registe r . res (reserved), al l regi ster s res e rv ed bits: th ese bits are re se rved. the s e bit s m u st be cle a re d to 0s (ze r o s ) for n o rm al o peratio n. w h en po we r i s reset, all of the regi sters? d a ta fields are clea red to 0 s (ze r o s ). qpp - register 0, bit 2 charge pump polarit y : this bit set s the cha r ge p u m p pola r ity to sink o r so urce curre n t. for a majority of applicatio ns, this bit i s cl ea red (qpp=0). for appli c ati ons wh ere an external i n ve rting am plifier is u s e d in th e loop filte r , this bit i s set to chan ge the charge pu mp polarity (see table 6 ) . qpp pll ch a r ge pump pol a rity 0 f c > f ref T ? cha r ge pum p sinks current. 1 f c > f ref T ? cha r ge pum p sour ces current. t a b l e 6: pl l ch arg e pu mp po larity ds272 4-f - 0 1 final data sheet april 2003 19
ml2724 rd0 - register 0, bit 3 ref e ren ce div i de: thi s bit sets th e refe re nce divider f r om the f r ef pin to th e referen c e inp u t of the p l l pha se/freq ue ncy dete c tor t o either 9 o r 18 (see ta ble 7). r d 0 r e f e r e n c e division fref xt a l freq pll ref freq 0 9 6 . 1 4 4 m h z 682.6 7 k h z 1 1 8 12.28 8 m h z 682.6 7 k h z ta ble 7 : re fe re nc e fre que ncy se le c t ao ut - regist er 0, bit 4 analog outp ut mod e : t h i s bit chan ge s the functio n of the aou t pin bet wee n an an alog dat a output to transmit pow e r control (see t able 8). a o ut a o ut pin function 0 t r ansmit po w e r control 1 data f ilter ana l og output ta ble 8 : a o ut fu nc tio n se le c t txcw - regist er 0, bit 6 transmit co ntinuous wav e : this bit produ ce s a contin uou s w a ve (c w) tra n smitter o u tp ut for prod uct test when rxon i s low (se e tabl e 9). t x c w t r a n smit m o dul a t i o n 0 f sk modulati o n 1 cw ? no mod u lati on t a b l e 9: t r an smit mo du lation mod e tpc - register 0, bit 7 transmit po w e r co ntrol : when th e aout bit is lo w, this bit co ntrols th e stat e of the open -drain outp u t pin. although this bit can b e cha nge d at any time, the aout pin o n l y chang es state at the falling edg e of r x on (see t a ble 10). tpc tpc pin st a t e 0 h i g h imp eda nc e 1 pull ed to grou nd t a b l e 10: t p c pin state txm - register 0, bit 8 transmit m o de: t h is bit control s the t x rf b u ffer state timing m ode. it must be reset to 0 for no rmal op eration (see table 11 ). txm txrf buffer beh a v ior 0 rf output al w a y s on i n t x mode 1 rf output follo w s paon ta ble 1 1 : txm mode ds272 4-f - 0 1 final data sheet april 2003 20
ml2724 lvlo - regist er 0, bit 10 lo w v o ltag e lock ou t: t he lvlo bit enabl es a tra n smit lo w voltage lo ck out latch, whi c h shuts off the transmitte r by de-a s se rting the paon out put. this latch is set if the s upply voltage dro p s b e low 2.65v an d is re set wh en the rxo n control input goe s high (se e table 12 ). lvlo p a on beh a v i o r 0 p a o n undistu r b e d 1 paon de-asse rted w h e n vcc a < 2 .65v, reset by rx o n high. t a b l e 12: l v lo op eratio n rclp - regist er 0, bit 11 rssi clip enable: the rc lp bit di sable s the rs si clipping ci rcuit r y. with rc lp low, t he rssi out put voltage i s clipp ed to a maximum of about 2.0v at ?10dbm. wit h rc lp high, the rssi is not clippe d. (see table 1 3 ). r c l p r s s i beh a vi o r 0 rssi output cli ppe d to a ma xi mum of ~ 1 .9v at ?15dbm 1 rssi output no t clippe d t a b l e 13: rcl p op eratio n chq <11: 0> - regi ster 1, bit s 2-13 chan nel fre quency sele ction: th ese bits set the rf ca rrie r freque ncy fo r t he tra n sceive r (se e ta ble 14). with a 6.144m hz o r 12.288m h z cl ock at the fref pin, the chann el freque ncy value is calcul ated by multiplying the chq valu e by 1.024. the re comm ende d o pera t ing ra nge value of the ch q i s fro m 2,346 to 2, 424. th ese bits mu st b e prog ram m ed to a valid cha nnel freq uen cy before xce n is a s serted. b15 b14 b13 t o b2 b1 b0 0 0 chq - pll div ide r a tio 0 1 ta ble 1 4 : ma in di v i der the divide ratio is cal c ul ate d as f c /1.024 whe r e f c is the cha nnel fre quen cy in mh z. f c = 1 .024 * ch q ds272 4-f - 0 1 final data sheet april 2003 21
ml2724 atm<2:0> - regist er 2, bits 2-4 analog te st mode: t he te st mode sele cted is d e scri bed in tabl e 15. the pe rfo r man c e of th e ml272 4 is not spe c ified in the s e te st mode s. alth ough pri m aril y intende d fo r ic te st a n d deb ug, they also can hel p in debu ggi ng the ra dio system. th e default (p ow e r-u p) state of these bits i s atm<2: 0 > =<0,0,0>. w hen a non -zero value i s w r itte n to the field, the rssi and aout pin s becom e ana log test acce ss p o rt s, giving acce ss to the outputs of key sign al pro c essin g stage s in the transceive r . duri ng no rma l operat io n, atm<2:0 > mu st be set to al l zero s. at m 2 a t m 1 at m 0 r s s i ao u t 0 0 0 rssi set b y aout bit 0 0 1 no co nnect no co nnect 0 1 0 i if filter outp ut q if filter out put 0 1 1 q if filter ? ve output q if filter + ve output 1 0 0 i if filter ? ve output i if filter + ve output 1 0 1 data f ilter + ve output data filter ? ve output 1 1 0 i if limiter outputs q if limiter outputs 1 1 1 1.67v volt age refere n c e vco modul atio n port input ta ble 1 5 : a n a l og te s t contr o l bits dtm <2:0> - regist er 2, bits 5-7 digital tes t mode: t he dtm < 2:0 > bi t functions are described i n table 1 6 . the pe rform ance of the ml272 4 is n o t spe c ified in t hese te st mo des. alth oug h p r ima r ily int ende d for ic test an d d e b ug, they al so ca n h e lp i n debu gging th e radio system. the default (po w e r up) state of these bits is dt m<2:0>=<0,0,0>. when a no n-zero value is written t o these fields, the d o ut a nd pao n pi ns become a digital te st a c cess port fo r key digital sign als i n th e tran sceiver. duri ng no rma l operatio n, d t m<2:0 > mu st be set to al l zero s. d t m 2 d t m 1 d t m 0 p a o n d o u t 0 0 0 pa control data out 0 0 1 pa control agc s w itch st ate 0 1 0 pa control pll mai n divi d er output 0 1 1 pa control pll refer enc e divider outp ut 1 0 0 s ? d modul ati on lsb sigma ? d e lta modu latio n msb ta ble 1 6 : digi ta l te s t control bits data interfaces baseband interface: din & dout the di n an d do ut pin s are di gital c m os sig nal s that corre s p ond to fsk modulatio n of the ca rrie r freque ncy. the ml272 4 is de sign ed to ope rate a s an f sk transceiv er in t he 2.4 g h z ism ban d. the frequ e n cy deviation and tran smit filtering is det ermin ed in th e transceive r . data on the din pin is filtered a nd pre s ente d to the transmit tw o-port mod u lato r. there i s no re-timing of the bits, so th e transmitted fsk data takes its timing from the input data. in the receive chain, fsk demodulation, data filtering, an d data sli c ing ta ke pl ace in th e ml27 24, an d the digital d a ta is o u tput on the do ut pin. bit and word rate timing re cove ry are pe rforme d off chip. th e data filter output is availa ble on the ao ut pin for u s e with an opti onal extern al data sli c er. ds272 4-f - 0 1 final data sheet april 2003 22
ml2724 rssi & fref fref (pin 9) is the ma ster referen c e freque ncy fo r the tr an scei ver. it suppli e s the freq u ency referen c e fo r the r f cha nnel fre q uen cy and th e filter tuning . the fref pin is a cm os input wit h internal bi a s ing resi sto r s. it can be a c cou p led to si ne or sq ua re wave so urce. the fref in put c an al so be driven by a cmos logi c output. the freque ncy o f the fref inp u t is limited to one of: 6.144 mhz o r 12.2 8 8 mh z. the r e ceive d signal stre ngth indi cato r (rssi) pin sup p lie s a v o ltage p r op ortional to the logarith m of the re ceive d pow er l e vel. it is no rmally con n e c ted to the in put of a lo w spe ed adc and is u s ed du ring chann el scann ing to dete c t clea r chan ne ls on whi c h the radi o ma y transmit. it can al so be u s ed to set tran smit pow er to o p timize p o w e r con s um ption while mai n tai n ing an a c ce ptable bit erro r rate (be r ). pa control output s (paon & aout) the paon (pa control ) is a cmos o u tput that cont rols a n option a l off-chi p rf pa. it outputs a logi c hig h wh en the p a sho u ld be e n abled a nd a l ogic lo w at all other times. this outp u t is inhibited w h e n the pll fails to lock. aout (pin 7) normally sup p lies the a nal og (not data - sliced) d a ta o u tput, but it can also be co nfigure d as a n open -d rain output for t r a n smit p o w e r control. thi s mode i s controlled by the tpc bit in re gister 0. thi s bit ca n be chang ed at a n y time, but the aout pin will not chang e mode until the beginni ng o f the next transmit slot, triggered by a falling edg e on rxon (see f i gure 6 and table 17 fo r details). in anal og te st mode s the r ssi and ao u t pin s be com e an alog te st acce ss po rts that allo w the user to o b se rve inte rnal sign als in the ml272 4. t1 t2 t3 t4 rxon paon output from trfo s y m b o l p a r a m e t e r time/ s t 1 rxon fal l i ng e dge to paon ri sing e d g e 62.5 t 2 rxon ris i ng e dge to pl l freque nc y shift 6.5 t 3 rxon ris i ng e dge to receiv e mode 70 t 4 rxon ris i ng e dge to paon falli ng e d g e < 0.1 figure 6 : po w e r a m plifie r inte rfac e ta ble 1 7 : po w e r a m plifie r timing rf interface: rxi & txo/txob the rxi rece ive input (pi n 17) a nd the txo/txob d i fferent ial tra n smit outp u ts (pin s 21 and 22) a r e th e only rf i/o pins. t he rxi pin req u ire s a sim p le i m p edan ce matching netw o rk for optim um i nput n o ise fig u re. the tx o/txob pin s requi re a mat c hin g net wo rk for maximu m po wer outp u t into the rf pow er amp. i f a sin g le e n d ed outp u t is p r eferred, th e sign al from the txo pin can be match ed to the po wer am p an d the txob o u tput ca n b e shu n ted to a pow er su pply throug h a du mmy load. the rf inp u t and output gro und (pi n 18) must have a dire ct con n e c tion to the rf groun d plane, and the rf p o we r su pply pins mu st be decoupl ed to the same g r o und pla ne a s clo s e to the d e vice a s po ssible. ds272 4-f - 0 1 final data sheet april 2003 23
ml2724 performance graphs fi gure 7 : outp ut po w e r (sing l e ende d) v s . fre quenc y f i g u re 8: rx se ns iti v ity (12 . 5% ber) v s . freque nc y -1 4 -1 2 -1 0 -8 -6 -4 -2 0 240 1. 00 2417 . 8 0 24 34. 6 0 245 1. 40 246 8. 20 24 85. 0 0 mh z db 2. 7 v 3. 3 v 4. 5 v -2 5 -2 0 -1 5 -1 0 -5 0 240 1. 0 0 241 7. 8 0 243 4. 6 0 245 1. 4 0 246 8. 2 0 248 5. 0 0 mh z db 2. 7v 3. 3v 4. 5v fig u re 9 : i nput re turn l o s s v s . fre que ncy a nd volt a g e figure 1 0 : out put ma tc h (se ) v s . fre que ncy a nd volta g e -1 -0 . 8 -0 . 6 -0 . 4 -0 . 2 0 0. 2 0. 4 0. 6 0. 8 1 - 800 - 600 - 400 - 200 0 20 0 40 0 60 0 80 0 0. 000 0. 200 0. 400 0. 600 0. 800 1. 000 1. 200 1. 400 1. 600 1. 800 1570 1577 1584 159 1 1597 1604 161 1 161 8 162 5 163 2 163 8 164 5 165 2 165 9 1666 1673 167 9 1686 1693 1700 fig u r e 11: tx eye diag ra m f i g u r e 12: vco t u n i ng vo ltag e v s . f r eq u e n c y ds272 4-f - 0 1 final data sheet april 2003 24
ml2724 physi cal di mensio ns ( inches/millimeters ) 0.048 m a x ( 1 .20 m a x ) se a t i n g pl a n e 0.354 b s c ( 9 .00 b s c ) 0.276 b s c ( 7 .00 b s c) 1 0.276 b s c ( 7 .00 b s c ) 0.354 b s c ( 9 .00 b s c) 9 25 17 0.032 b s c ( 0 .8 bs c) pi n 1 i d 0 . 012 - 0.0 1 8 ( 0 .29 - 0.45) 0.037 - 0.0 4 1 ( 0 .95 - 1.05) 0.018 - 0.0 3 0 ( 0 .45 - 0.75) 0.003 - 0.0 0 8 ( 0 .09 - 0.20) 0 o - 8 o warranty micro linea r make s no repre s e n tation s or w a rranti e s with re sp ect to the accuracy, utility, or complet ene ss of th e conte n ts of t h is p ubli c atio n and re se rves the rig h t to ma ke cha n ges to specifi c ation s a nd prod uct de scription s at a n y time without notice. no li cen s e, exp r e ss or impli e d , by estoppel or othe rwi s e, to any pa tents or othe r intelle ctual prop erty rig h ts is g r ante d b y this docum ent. the ci rcu i ts c ontai ned in this do cum ent are offe re d as p o ssible application s only. particul ar uses o r a pplication s may invalidate some of the spe c ification s and/or p r od uct de scriptio ns contain ed herei n. the custome r is u r ged to perfo rm its own e n g inee ring review befo r e de cidin g on a p a rticul ar a ppli c ation. micro linea r a s sum e s n o liability what soeve r , and disclaim s any expr e s s o r impli ed warra n ty, rel a ting to sale and/or u s e of micro line ar prod uct s in cl uding lia bility or wa rrantie s rel a ti ng to mercha ntabili ty, fi tness fo r a particula r purp o se, or infringe ment of any intellectual p r op erty right. micro linea r produ cts a r e not d e sig ned fo r u s e in me dical , life saving, or life sustai ning application s . if th i s do cu me n t i s ? a d v anc e ? , i t s c o n t en ts de scr i b e a mic r o l i nea r p r od uct th at is cu rrentl y unde r deve l opment. al l detailed spe c i f ication s incl u d ing pin outs and ele c tri c al spe c ificatio n s may be cha nged without notice. if this document i s ?prelimi nary ? , its co ntents are b a sed o n ear ly silico n measurement s. typical dat a is rep r e s ent ative of the p r odu ct but i s subj ect to ch ange without notice. pin o u t and me ch anical dim e n s ion s a r e fin a l. prelimina r y docum ents sup e rsed e a ll advance d o cuments a nd all previou s prelimina r y versi o n s . if thi s docume n t is ?final ?, its conte n ts are based o n a cha r a c teri ze d prod uct, an d it is believ ed to be a c curate at the t i me of publi c ation. final data she e ts sup e rsed e a l l previou s ly pu blish ed versio ns. thi s do cu ment is final. ? 2003 mi cro linear co rpo r ation. all righ ts re serve d . all other trad emarks are th e prop erty of their re sp ecti ve owne rs. produ cts de scrib e d he rein may b e cov e red by one or mo re of the follo wing u.s. pate n ts: 4,89 7,611; 4,964,0 26; 5,027,11 6; 5 , 281,862; 5, 283,48 3; 5,4 18,502; 5,5 0 8 ,570; 5,51 0 , 727; 5,523, 940; 5,54 6,0 17; 5,559,4 7 0 ; 5,565,7 61; 5,592,12 8; 5 , 594,376; 5, 652,47 9; 5,6 61,427; 5,6 6 3 ,874; 5,67 2 , 959; 5,689, 167; 5,71 4,8 97; 5,717,7 9 8 ; 5,742,1 51; 5,747,97 7; 5 , 754,012; 5, 757,17 4; 5,7 67,653; 5,7 7 7 ,514; 5,79 3 , 168; 5,798, 635; 5,80 4,9 50; 5,808,4 5 5 ; 5,811,9 99; 5,818,20 7; 5 , 818,669; 5, 825,16 5; 5,8 25,223; 5,8 3 8 ,723; 5.84 4 , 378; 5,844, 941. japa n: 2,598,94 6; 2,619,29 9; 2,704,17 6; 2,821,71 4. other patent s are pendi ng. ds272 4-f - 0 1 final data sheet april 2003 25
ml2724 ds272 4-f - 0 1 final data sheet april 2003 26 micro linear cor poration 2050 concou rse drive san jose, ca 95 131 tel: (408 ) 433- 52 00 fax: (408 ) 432- 0 295 www.microlinear. c om united s t ate s asia 35 pinehurst avenue room d, 28/ f., block 81 nashua, nh 0 3 0 62 tsun king road shatin, n.t., tel: (603 ) 888- 13 26 hong kong fax: (603 ) 888- 4 239 tel: 852-26 3485 85 e- mail: grazier.m a rk@microlinear. c om fax: 8 52-27 7582 84 e- m a i l : chan.sand y @ microlinear. c om euro pe japan 102 lesbourn e r oad, 1-17-8 hasega wa building reigate surr e y r h 2 7jx england hamamatsu-cho minato-ku, tel: 44 1737 2 2 4 599 tok y o 10 5-001 3 fax: 4 4 1737 2 2 4599 tel: 3-3438 -1651 e- mail: hopson.martin@microlinear.com e- m a i l : y a mashita.takao@microlinear.com

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