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m32c/80 group single-chip 16/32-bit cmos microcomputer page 1 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r rej03b0038-0110 rev.1.10 nov. 01, 2005 1. overview the m32c/80 group microcomputer is a single-chip control unit that utilizes high-performance silicon gate cmos technology with the m32c/80 series cpu core. the m32c/80 group is available in 100-pin plastic molded lqfp/qfp package. with a 16-mbyte address space, this microcomputer combines advanced instruction manipulation capabili- ties to process complex instructions by less bytes and execute instructions at higher speed. it incorporates a multiplier and dmac adequate for office automation, communication devices and industrial equipments and other high-speed processing applications. the m32c/80 group is romless device. use the m32c/80 group in microprocessor mode after reset. 1.1 applications audio, cameras, office equipment, communications equipment, portable equipment, etc.
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 2 p u o r g 0 8 / c 2 3 m 1.2 performance overview table 1.1 lists performance overview of the m32c/80 group. table 1.1 m32c/80 group performance item performance cpu basic instructions 108 instructions minimum instruction execution time 31.3 ns ( f(bclk)=32 mhz, v cc1 =4.2 to 5.5 v ) 41.7 ns ( f(bclk)=24 mhz, v cc1 =3.0 to 5.5 v ) operating mode single-chip mode, memory expansion mode, microprocessor mode memory space 16 mbytes memory capacity see table 1.2 peripheral i/o port 47 i/o pins (when using 16-bit bus) and 1 input pin function multifunction timer timer a: 16 bits x 5 channels, timer b: 16 bits x 6 channels three-phase motor control circuit intelligent i/o communication function 2 channels serial i/o 5 channels clock synchronous serial i/o, clock asynchronous serial i/o, iebus (1) , i 2 c bus (2) a/d converter 10-bit a/d converter: 1 circuit, 10 channels d/a converter 8 bits x 2 channels dmac 4 channels dmac ii can be activated by all peripheral function interrupt sources immediate transfer, operation and chain transfer function crc calculation circuit crc-ccitt x/y converter 16 bits x 16 bits watchdog timer 15 bits x 1 channel (with prescaler) interrupt 34 internal sources and 8 external sources, 5 software sources interrupt priority level: 7 clock generation circuit 4 circuits main clock oscillation circuit (*), sub clock oscillation circuit (*), on-chip oscillator, pll frequency synthesizer (*)equipped with a built-in feedback resistor oscillation stop detect function main clock oscillation stop detect circuit electrical supply voltage v cc1 =4.2 to 5.5 v, v cc2 =3.0 to v cc1 (f(bclk)=32 mhz) charact- v cc1 =3.0 to 5.5 v, v cc2 =3.0 to v cc1 (f(bclk)=24 mhz) eristics power consumption 22 ma (v cc1 =v cc2 =5 v, f(bclk)=32 mhz) 17 ma (v cc1 =v cc2 =3.3 v, f(bclk)=24 mhz) 10 a (v cc1 =v cc2 =3.3 v, f(bclk)=32 khz, in wait mode) operating ambienttemperature C20 to 85 o c, C40 to 85 o c(optional) package 100-pin plastic molded lqfp/qfp notes: 1. iebus is a trademark of nec electronics corporation. 2. i 2 c bus is a trademark of koninklijke philips electronics n. v. all options are on a request basis.
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 3 p u o r g 0 8 / c 2 3 m 1.3 block diagram figure 1.1 shows a block diagram of the m32c/80 group microcomputer. figure 1.1 m32c/80 group block diagram r0h r0l r1h r1l r2 r3 a0 a1 fb sb flg intb isp usp pc svf svp vct multiplier m32c/80 series cpu core clock generating circuit x in - x out x cin - x cout on-chip oscillator pll frequency synthesizer a/d converter 1 circuit standard: 8 inputs maximum: 10 inputs uart/ clock synchronous serial i/o 5 channels x/y converter 16 bits x 16 bits crc calcilation circuit (ccitt) x 16 +x 12 +x 5 +1 timer (16 bits) timer a: 5 channels timer b: 6 channels three-phase motor control circuit watchdog timer (15 bits) d/a converter 8 bits x 2 channels peripheral functions ram memory port p0 8 port p6 8 port p7 8 dmac dmacii intelligent i/o communication function 2 channels < v cc2 > port p8 7 p8 5 port p9 8 port p10 8 < v cc1 > port p1 8 port p2 8 port p3 8 port p4 8 port p5 8 (1) (2) (1) (1) (1) (1) notes: 1. ports p0 to p5 function as bus control pins when using memory expansion mode or microprocessor mode. 2. port p1 functions as i/o port when the microcomputer is placed in memory expansion mode or microprocessor mode and all external data buses are selected as 8-bit buses.
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 4 p u o r g 0 8 / c 2 3 m figure 1.2 product numbering system 1.4 product information table 1.2 lists the product information. figure 1.2 shows the product numbering system. table 1.2 m32c/80 group as of november, 2005 package type: fp = package prqp0100jb-a (100p6s-a) gp = package plqp0100kb-a (100p6q-a) memory type: s = romless version m 3 0 8 0 0 s a g p - b l m32c/80 group m16c family ram capacity, pin count, etc on-chip boot loader r e b m u n e p y te p y t e g a k c a p m o r y t i c a p a c m a r y t i c a p a c s k r a m e r 0 3 ma s 0 0 8p g) a - q 6 p 0 0 1 ( a - b k 0 0 1 0 p q l p ? k 8 s s e l m o r 0 3 ma s 0 0 8p f) a - s 6 p 0 0 1 ( a - b j 0 0 1 0 p q r p 0 3 ma s 0 0 8p gl b -) a - q 6 p 0 0 1 ( a - b k 0 0 1 0 p q l p h t i w s s e l m o r r e d a o l t o o b p i h c - n o 0 3 ma s 0 0 8p fl b -) a - s 6 p 0 0 1 ( a - b j 0 0 1 0 p q r p
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 5 p u o r g 0 8 / c 2 3 m 1.5 pin assignment figures 1.3 and 1.4 show pin assignments (top view). figure 1.3 pin assignment 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 m32c/80 group srxd4 / sda4 / txd4 / anex1 / p9 6 clk4 / anex0 / p9 5 ss4 / rts4 / cts4 / tb4 in / da1 / p9 4 ss3 / rts3 / cts3 / tb3 in / da0 / p9 3 srxd3 / sda3 / txd3 / tb2 in / p9 2 stxd3 / scl3 / rxd3 / tb1 in / p9 1 clk3 / tb0 in / p9 0 byte cnvss x cin / p8 7 x cout / p8 6 reset x out vss x in vcc1 nmi / p8 5 int2 / p8 4 int1 / p8 3 int0 / p8 2 u / ta4 in / p8 1 isrxd0 / u / ta4 out / p8 0 isclk0 / ta3 in / p7 7 istxd0 / ta3 out / p7 6 isrxd1 / w / ta2 in / p7 5 isclk1 / w / ta2 out / p7 4 istxd1 / ss2 / rts2 / cts2 / v / ta1 in / p7 3 clk2 / v / ta1 out / p7 2 stxd2 / scl2 / rxd2 / ta0 in / tb5 in / p7 1 srxd2 / sda2 / txd2 / ta0 out / p7 0 p4 4 / cs3 / a 20 p4 5 / cs2 / a 21 p4 6 / cs1 / a 22 p4 7 / cs0 / a 23 p5 0 / wrl / wr p5 1 / wrh / bhe p5 2 / rd p5 3 / clk out / bclk / ale p5 4 / hlda / ale p5 5 / hold p5 6 / ale p5 7 / rdy p6 0 / cts0 / rts0 / ss0 p6 1 / clk0 p6 2 / rxd0 / scl0 / stxd0 p6 3 / txd0 / sda0 / srxd0 p6 4 / cts1 / rts1 / ss1 p6 5 / clk1 p6 6 / rxd1 / scl1 / stxd1 p6 7 / txd1 / sda1 / srxd1 p1 0 / d 8 p1 1 / d 9 p1 2 / d 10 p1 3 / d 11 p1 4 / d 12 p1 5 / d 13 / int3 p1 6 / d 14 / int4 p1 7 / d 15 / int5 p2 0 / a 0 ( / d 0 ) p2 1 / a 1 ( / d 1 ) p2 2 / a 2 ( / d 2 ) p2 3 / a 3 ( / d 3 ) p2 4 / a 4 ( / d 4 ) p2 5 / a 5 ( / d 5 ) p2 6 / a 6 ( / d 6 ) p2 7 / a 7 ( / d 7 ) vss p3 0 / a 8 ( / d 8 ) vcc2 p3 1 / a 9 ( / d 9 ) p3 2 / a 10 ( / d 10 ) p3 3 / a 11 ( / d 11 ) p3 4 / a 12 ( / d 12 ) p3 5 / a 13 ( / d 13 ) p3 6 / a 14 ( / d 14 ) p3 7 / a 15 ( / d 15 ) p4 0 / a 16 p4 1 / a 17 p4 2 / a 18 p4 3 / a 19 d 7 / p0 7 d 6 / p0 6 d 5 / p0 5 d 4 / p0 4 d 3 / p0 3 d 2 / p0 2 d 1 / p0 1 d 0 / p0 0 ki 3 / an 7 / p10 7 ki 2 / an 6 / p10 6 ki 1 / an 5 / p10 5 ki 0 / an 4 / p10 4 an 3 / p10 3 an 2 / p10 2 an 1 / p10 1 avss an 0 / p10 0 v ref avcc rxd4 / ad trg / p9 7 stxd4 / scl4 / < v cc2 > < v cc1 > note: 1. p7 0 and p7 1 are ports for the n-channel open drain output. prqp0100jb-a (100p6s-a)
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 6 p u o r g 0 8 / c 2 3 m figure 1.4 pin assignment 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 30 29 28 27 26 76 77 78 79 80 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 m32c/80 group ss4 / rts4 / cts4 / tb4 in / da1 / p9 4 ss3 / rts3 / cts3 / tb3 in / da0 / p9 3 srxd3 / sda3 / txd3 / tb2 in / p9 2 stxd3 / scl3 / rxd3 / tb1 in / p9 1 clk3 / tb0 in / p9 0 byte cnvss x cin / p8 7 x cout / p8 6 reset x out vss x in vcc1 nmi / p8 5 int2 / p8 4 int1 / p8 3 int0 / p8 2 u / ta4 in / p8 1 isrxd0 / u / ta4 out / p8 0 isclk0 / ta3 in / p7 7 istxd0 / ta3 out / p7 6 isrxd1 / w / ta2 in / p7 5 isclk1 / w / ta2 out / p7 4 istxd1 / ss2 / rts2 / cts2 / v / ta1 in / p7 3 p4 2 / a 18 p4 3 / a 19 p4 4 / cs3 / a 20 p4 5 / cs2 / a 21 p4 6 / cs1 / a 22 p4 7 / cs0 / a 23 p5 0 / wrl / wr p5 1 / wrh / bhe p5 2 / rd p5 3 / clk out / bclk / ale p5 4 / hlda / ale p5 5 / hold p5 6 / ale p5 7 / rdy p6 0 / cts0 / rts0 / ss0 p6 1 / clk0 p6 2 / rxd0 / scl0 / stxd0 p6 3 / txd0 / sda0 / srxd0 p6 4 / cts1 / rts1 / ss1 p6 5 / clk1 p6 6 / rxd1 / scl1 / stxd1 p6 7 / txd1 / sda1 / srxd1 p7 0 / ta0 out / txd2 / sda2 / srxd2 p7 1 / ta0 in / tb5 in / rxd2 / scl2 / stxd2 p7 2 / ta1 out / v / clk2 p1 3 / d 11 p1 4 / d 12 p1 5 / d 13 / int3 p1 6 / d 14 / int4 p1 7 / d 15 / int5 p2 0 / a 0 ( / d 0 ) p2 1 / a 1 ( / d 1 ) p2 2 / a 2 ( / d 2 ) p2 3 / a 3 ( / d 3 ) p2 4 / a 4 ( / d 4 ) p2 5 / a 5 ( / d 5 ) p2 6 / a 6 ( / d 6 ) p2 7 / a 7 ( / d 7 ) vss p3 0 / a 8 ( / d 8 ) vcc2 p3 1 / a 9 ( / d 9 ) p3 2 / a 10 ( / d 10 ) p3 3 / a 11 ( / d 11 ) p3 4 / a 12 ( / d 12 ) p3 5 / a 13 ( / d 13 ) p3 6 / a 14 ( / d 14 ) p3 7 / a 15 ( / d 15 ) p4 0 / a 16 p4 1 / a 17 d 10 / p1 2 d 9 / p1 1 d 8 / p1 0 d 7 / p0 7 d 6 / p0 6 d 5 / p0 5 d 4 / p0 4 d 3 / p0 3 d 2 / p0 2 d 1 / p0 1 d 0 / p0 0 ki 3 / an 7 / p10 7 ki 2 / an 6 / p10 6 ki 1 / an 5 / p10 5 ki 0 / an 4 / p10 4 an 3 / p10 3 an 2 / p10 2 an 1 / p10 1 avss an 0 / p10 0 v ref avcc stxd4 / scl4 / rxd4 / ad trg / p9 7 srxd4 / sda4 / txd4 / anex1 / p9 6 clk4 / anex0 / p9 5 < v cc2 > < v cc2 > < v cc1 > < v cc1 > note: 1. p7 0 and p7 1 are ports for the n-channel open drain output. plqp0100kb-a (100p6q-a)
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 7 p u o r g 0 8 / c 2 3 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 byte cnv ss x cin x cout reset x out v ss x in v cc1 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p4 7 p4 6 p4 5 p4 4 nmi int2 int1 int0 tb4 in tb3 in tb2 in tb1 in tb0 in ta4 in /u ta4 out /u ta3 in ta3 out ta2 in /w ta2 out /w ta1 in /v ta1 out /v tb5 in /ta0 in ta0 out txd4/sda4/srxd4 clk4 cts4/rts4/ss4 cts3/rts3/ss3 txd3/sda3/srxd3 rxd3/scl3/stxd3 clk3 cts2/rts2/ss2 clk2 rxd2/scl2/stxd2 txd2/sda2/srxd2 txd1/sda1/srxd1 rxd1/scl1/stxd1 clk1 cts1/rts1/ss1 txd0/sda0/srxd0 rxd0/scl0/stxd0 clk0 cts0/rts0/ss0 anex1 anex0 da1 da0 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 rdy ale hold hlda/ale clk out /bclk/ale rd wrh/bhe wrl/wr cs0/a 23 cs1/a 22 cs2/a 21 cs3/a 20 package pin no fp gp control pins port timer pins uart pins bus control pins analog pins interrupt pins intelligent i/o pins isrxd0 isclk0 istxd0 isrxd1 isclk1 istxd1 table 1.3 pin characteristics
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 8 p u o r g 0 8 / c 2 3 m table 1.3 pin characteristics (continued) 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 v cc2 v ss av ss av cc p4 3 p4 2 p4 1 p4 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p10 7 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p9 7 an 7 an 6 an 5 an 4 an 3 an 2 an 1 an 0 v ref ad trg a 19 a 18 a 17 a 16 a 15 (/d 15 ) a 14 (/d 14 ) a 13 (/d 13 ) a 12 (/d 12 ) a 11 (/d 11 ) a 10 (/d 10 ) a 9 (/d 9 ) a 8 (/d 8 ) a 7 (/d 7 ) a 6 (/d 6 ) a 5 (/d 5 ) a 4 (/d 4 ) a 3 (/d 3 ) a 2 (/d 2 ) a 1 (/d 1 ) a 0 (/d 0 ) d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 int5 int4 int3 ki 3 ki 2 ki 1 ki 0 rxd4/scl4/stxd4 fp gp package pin no control pins port timer pins uart pins bus control pins analog pins interrupt pins intelligent i/o pins
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 9 p u o r g 0 8 / c 2 3 m apply 3.0 to 5.5 v to both v cc1 and v cc2 pins. apply 0 v to the v ss pin. v cc1 v cc2 (1) supplies power for the a/d converter. connect the av cc pin to v cc1 and the av ss pin to v ss the microcomputer is in a reset state when "l" is applied to the ____________ reset pin connect this pin to v cc1 switches the data bus in external memory space 3. the data bus is 16 bits long when the this pin is held "l" and 8 bits long when the this pin is held "h". set it to either one. inputs and outputs data (d 0 to d 7 ) while accessing an external memory space with separate bus inputs and outputs data (d 8 to d 15 ) while accessing an external memory space with 16-bit separate bus outputs address bits (a 0 to a 22) outputs inversed address bit a23 inputs and outputs data (d 0 to d 7 ) and outputs 8 low-order address bits (a 0 to a 7 ) by time-sharing while accessing an external memory space with multiplexed bus inputs and outputs data (d 8 to d 15 ) and outputs 8 middle-order address bits (a 8 to a 15 ) by time-sharing while accessing an external memory space with multiplexed bus ______ ______ output cs0 to cs3 that are chip-select signals specifying an external space _______ ________ ______ ________ _____ _______ ________ outputs wrl, wrh, (wr, bhe) and rd signals. wrl and wrh ______ _______ can be switched with wr and bhe by program ________ _________ _____ wrl, wrh and rd are selected: if external data bus is 16 bits wide, data is writtenn to an even _______ address when wrl is held "l". ________ data is written to an odd address when wrh is held "l". _____ data is read when rd is held "l". ______ ________ _____ wr, bhe and rd are selected ______ data is written to external memory space when wr is held "l". _____ data is read when rd is held "l". ________ an odd address is accessed when bhe is held "l". ______ ________ _____ select wr, bhe and rd for an external 8-bit data bus ale is a signal latching address __________ the microcomputer is placed in a hold state while the hold pin is held "l" outputs an "l" siganl while the microcomputer is placed in a hold state bus is placed in a wait state while the rdy pin is held "l" v cc1, v cc2 v ss av cc av ss ____________ reset cnv ss byte d 0 to d 7 d 8 to d 15 a 0 to a 22 ______ a 23 a 0 /d 0 to a 7 /d 7 a 8 /d 8 to a 15 /d 15 ______ ______ cs0 to cs3 ________ ______ wrl/wr _________ ________ wrh/bhe _____ rd ale __________ hold __________ hlda ________ rdy power supply analog power supply input reset input cnv ss external data bus width select input bus control pins i i i i i i/o i/o o o i/o i/o o o o i o i - v cc1 v cc1 v cc1 v cc1 v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 supply signal name pin name i/o type description voltage 1.6 pin description table 1.4 pin description i: input o: output i/o: input and output note: 1. in this manual, hereafter, v cc refers to v cc1 unless otherwise noted.
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 10 p u o r g 0 8 / c 2 3 m x in x out x cin x cout bclk clk out _______ _______ int0 to int2 _______ _______ int3 to int5 _______ nmi _____ _____ ki 0 to ki 3 ta0 out to ta4 out ta0 in to ta4 in tb0 in to tb5 in __ __ u, u, v, v, __ w, w _________ cts0 to _________ cts4 _________ rts0 to _________ rts4 clk0 to clk4 rxd0 to rxd4 txd0 to txd4 sda0 to sda4 scl0 to scl4 stxd0 to stxd4 srxd0 to srxd4 ______ _______ ss0 to ss4 main clock input main clock output sub clock input sub clock output bclk output clock output ______ int interrupt input _______ nmi interrupt input key input interrupt timer a timer b three-phase motor control output serial i/o i 2 c mode serial i/o special function v cc1 v cc1 v cc1 v cc1 v cc2 v cc2 v cc1 v cc2 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 i o i o o o i i i i/o i i o i o i/o i o i/o i/o i i i i/o pins for the main clock generation circuit. connect a ceramic resonator or crystal oscillator between x in and x out . to apply external clock, input the clock from x in and leave x out open i/o pins for a sub clock oscillation circuit. connect a crystal oscillator between x cin and xcout. to apply external clock, input the clock from x cin and leave x cout open outputs bclk signal outputs clock having thesame frequency as f c , f 8 , or f 32 ______ input pins for the int interrupt _______ input pin for the nmi interrupt input pins for the key input interrupt i/o pins for the timer a0 to a4 (ta0 out is a pin for the n-channel open drain output.) input pins for the timer a0 to a4 input pins for the timer b0 to b5 output pins for the three-phase motor control timer input pins for data transmission control output pins for data reception control inputs and outputs the transfer clock inputs serial data outputs serial data (txd2 is a pin for the n-channel open drain output.) inputs and outputs serial data (sda2 is a pin for for the n- channel open drain output.) inputs and outputs the transfer clock (scl2 is a pin for the n- channel open drain output.) outputs serial data when slave mode is selected (sda2 is a pin for the n-channel open drain output.) inputs serial data when slave mode is selected input pins to control serial i/o special function supply signal name pin name i/o type description voltage table 1.4 pin description (continued) i: input o: output i/o: input and output
6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 1. overview page 11 p u o r g 0 8 / c 2 3 m v ref an 0 to an 7 ___________ ad trg anex0 anex1 da0, da1 isclk0 isclk1 istxd0 istxd1 isrxd0 isrxd1 p0 0 to p0 7 (1) p1 0 to p1 7 (2) p2 0 to p2 7 (1) p3 0 to p3 7 (1) p4 0 to p4 7 (1) p5 0 to p5 7 (1) p6 0 to p6 7 p7 0 to p7 7 p9 0 to p9 7 p10 0 to p10 7 p8 0 to p8 4 , p8 6 , p8 7 p8 5 reference voltage input a/d converter d/a converter intelligent i/o communication function i/o port - v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc1 v cc2 v cc1 v cc1 v cc1 applies reference voltage for the a/d converter and d/a converter analog input pins for the a/d converter input pin for an external a/d trigger extended analog input pin for the a/d converter and output pin in external op-amp connection mode extended analog input pin for the a/d converter output pin for the d/a converter inputs and outputs clock for the intelligent i/o communication fucntion outputs data for the intelligent i/o communication fucntion inputs data for the intelligent i/o communication fucntion i/o ports fro cmos. each port can be programmed for nput or output under the control of the direction register. an input port can be set, by program, for a pull-up resistor available or for no pull-up resistor available in 4-bit units i/o ports having equivalent functions to p0 (p7 0 and p7 1 are ports for the n-channel open drain output.) i/o ports having equivalent functions to p0 _______ _______ shares a pin with nmi. nmi input state can be got by reading p8 5 i i i i/o i o i/o o i i/o i/o i/o i supply signal name pin name i/o type description voltage table 1.5 pin description (continued) i: input o: output i/o: input and output notes: 1. ports p0 to p5 function as bus control pins when using memory expansion mode or microprocessor mode. they cannot be used as i/o ports. 2. port p1 functions as i/o port when the microcomputer is placed in memory expansion mode or microprocessor mode and all external data buses are selected as 8-bit buses.
page 12 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 2. central processing unit (cpu) 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the register bank is comprised of 8 registers (r0, r1, r2, r3, a0, a1, sb and fb) out of 28 cpu registers. two sets of register banks are provided. figure 2.1 cpu register b23 r0h r0l r1h r1l r2 r3 b31 r2 r3 a0 a1 sb fb usp isp intb pc high-speed interrupt registers b15 b0 b23 svf svp vct dmac-associated registers b7 b0 b23 dmd0 dct0 dct1 b15 drc0 drc1 dma0 dma1 dmd1 dra0 dra1 data register (1) address register (1) static base register (1) frame base register (1) user stack pointer interrupt stack pointer interrupt table register program counter flag save register pc save register vector register dma mode register dma transfer count register dma transfer count reload register dma memory address register dma sfr address register dma memory address reload register note: 1. the register bank is comprised of these registers. two sets of register banks are provided. general registers b15 b0 b15 b0 carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved space processor interrupt priority level reserved space flg flag register ipl u i o b s z d c b7 b8 dsa0 dsa1
page 13 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 2. central processing unit (cpu) 2.1 general registers 2.1.1 data registers (r0, r1, r2 and r3) r0, r1, r2 and r3 are 16-bit registers for transfer, arithmetic and logic operations. r0 and r1 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r0 can be combined with r2 to be used as a 32-bit data register (r2r0). the same applies to r1 and r3. 2.1.2 address registers (a0 and a1) a0 and a1 are 24-bit registers for a0-/a1-indirect addressing, a0-/a1-relative addressing, transfer, arith- metic and logic operations. 2.1.3 static base register (sb) sb is a 24-bit register for sb-relative addressing. 2.1.4 frame base register (fb) fb is a 24-bit register for fb-relative addressing. 2.1.5 program counter (pc) pc, 24 bits wide, indicates the address of an instruction to be executed. 2.1.6 interrupt table register (intb) intb is a 24-bit register indicating the starting address of an relocatable interrupt vector table. 2.1.7 user stack pointer (usp), interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are 24 bits wide each. the u flag is used to switch between usp and isp. refer to 2.1.8 flag register (flg) for details on the u flag. set usp and isp to even addresses to execute an interrupt sequence efficiently. 2.1.8 flag register (flg) flg is a 16-bit register indicating a cpu state. 2.1.8.1 carry flag (c) the c flag indicates whether carry or borrow has occurred after executing an instruction. 2.1.8.2 debug flag (d) the d flag is for debug only. set to "0". 2.1.8.3 zero flag (z) the z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0". 2.1.8.4 sign flag (s) the s flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".
page 14 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 2. central processing unit (cpu) 2.1.8.5 register bank select flag (b) the register bank 0 is selected when the b flag is set to "0". the register bank 1 is selected when this flag is set to "1". 2.1.8.6 overflow flag (o) the o flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0". 2.1.8.7 interrupt enable flag (i) the i flag enables a maskable interrupt. interrupt is disabled when the i flag is set to "0" and enabled when the i flag is set to "1". the i flag is set to "0" when an interrupt is acknowledged. 2.1.8.8 stack pointer select flag (u) isp is selected when the u flag is set to "0". usp is selected when this flag is set to "1". the u flag is set to "0" when a hardware interrupt is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.1.8.9 processor interrupt priority level (ipl) ipl, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. if a requested interrupt has greater priority than ipl, the interrupt is enabled. 2.1.8.10 reserved space when writing to a reserved space, set to "0". when reading, its content is indeterminate. 2.2 high-speed interrupt registers registers associated with the high-speed interrupt are as follows: - flag save register (svf) - pc save register (svp) - vector register (vct) 2.3 dmac-associated registers registers associated with dmac are as follows: - dma mode register (dmd0, dmd1) - dma transfer count register (dct0, dct1) - dma transfer count reload register (drc0, drc1) - dma memory address register (dma0, dma1) - dma sfr address register (dsa0, dsa1) - dma memory address reload register (dra0, dra1)
page 15 3. memory 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 3. memory figure 3.1 shows a memory map of the m32c/80 group. the m32c/80 group provides 16-mbyte address space addressed from 000000 16 to ffffff 16 . the fixed interrupt vectors are allocated from address ffffdc 16 to ffffff 16 . it stores the starting ad- dress of each interrupt routine. the internal ram is allocated from address 000400 16 to higher. for example, a 8-kbyte internal ram is allocated from address 000400 16 to 0023ff 16 . besides storing data, it becomes stacks when the subrou- tine is called or an interrupt is acknowledged. sfrs, consisting of control registers for peripheral functions such as i/o port, a/d converter, serial i/o, timers, is allocated from address 000000 16 to 0003ff 16 . all blank spaces within sfrs are reserved and cannot be accessed by users. the special page vector table is addressed from fffe00 16 to ffffdb 16 . it is used for the jmps instruc- tion and jsrs instruction. refer to the renesas publication m32c/80 series software manual for details. in microprocessor mode, some spaces are reserved and cannot be accessed by users. sfrs internal ram reserved space external space brk instruction overflow undefined instruction ffffff 16 nmi 000000 16 000400 16 0023ff 16 010000 16 ffffff 16 special page vector table address match watchdog timer (1) reset note: 1. watchdog timer interrupt and oscillation stop detection interrupt share vectors. ffffdc 16 fffe00 16 figure 3.1 memory map
page 16 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 0000 16 0001 16 0002 16 0003 16 0004 16 processor mode register (1) pm0 0000 0011 2 (cnvss pin ="h") 0005 16 processor mode register 1 pm1 00 16 0006 16 system clock control register 0 cm0 0000 1000 2 0007 16 system clock control register 1 cm1 0010 0000 2 0008 16 0009 16 address match interrupt enable register aier 00 16 000a 16 protect register prcr xxxx 0000 2 xxxx 1000 2 (byte pin ="l") 000b 16 external data bus width control register ds xxxx 0000 2 (byte pin ="h") 000c 16 main clock division register mcd xxx0 1000 2 000d 16 oscillation stop detection register cm2 00 16 000e 16 watchdog timer start register wdts xx 16 000f 16 watchdog timer control register wdc 000x xxxx 2 0010 16 0011 16 address match interrupt register 0 rmad0 000000 16 0012 16 0013 16 processor mode register 2 pm2 00 16 0014 16 0015 16 address match interrupt register 1 rmad1 000000 16 0016 16 0017 16 0018 16 0019 16 address match interrupt register 2 rmad2 000000 16 001a 16 001b 16 001c 16 001d 16 address match interrupt register 3 rmad3 000000 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 pll control register 0 plc0 0001 x010 2 0027 16 pll control register 1 plc1 000x 0000 2 0028 16 0029 16 address match interrupt register 4 rmad4 000000 16 002a 16 002b 16 002c 16 002d 16 address match interrupt register 5 rmad5 000000 16 002e 16 002f 16 x: indeterminate blank spaces are reserved. no access is allowed. note: 1. the pm01 and pm00 bits in the pm0 register maintain values set before reset, even after software reset or watch- dog timer reset has been performed. 4. special function registers (sfrs)
page 17 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 address match interrupt register 6 rmad6 000000 16 003a 16 003b 16 003c 16 003d 16 address match interrupt register 7 rmad7 000000 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 external space wait control register 0 ewcr0 x0x0 0011 2 0049 16 external space wait control register 1 ewcr1 x0x0 0011 2 004a 16 external space wait control register 2 ewcr2 x0x0 0011 2 004b 16 external space wait control register 3 ewcr3 x0x0 0011 2 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 18 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 dma0 interrupt control register dm0ic xxxx x000 2 0069 16 timer b5 interrupt control register tb5ic xxxx x000 2 006a 16 dma2 interrupt control register dm2ic xxxx x000 2 006b 16 uart2 receive /ack interrupt control register s2ric xxxx x000 2 006c 16 timer a0 interrupt control register ta0ic xxxx x000 2 006d 16 uart3 receive /ack interrupt control register s3ric xxxx x000 2 006e 16 timer a2 interrupt control register ta2ic xxxx x000 2 006f 16 uart4 receive /ack interrupt control register s4ric xxxx x000 2 0070 16 timer a4 interrupt control register ta4ic xxxx x000 2 0071 16 uart0/uart3 bus conflict detect interrupt control register bcn0ic/bcn3ic xxxx x000 2 0072 16 uart0 receive/ack interrupt control register s0ric xxxx x000 2 0073 16 a/d0 conversion interrupt control register ad0ic xxxx x000 2 0074 16 uart1 receive/ack interrupt control register s1ric xxxx x000 2 0075 16 intelligent i/o interrupt control register 0 iio0ic xxxx x000 2 0076 16 timer b1 interrupt control register tb1ic xxxx x000 2 0077 16 intelligent i/o interrupt control register 2 iio2ic xxxx x000 2 0078 16 timer b3 interrupt control register tb3ic xxxx x000 2 0079 16 intelligent i/o interrupt control register 4 iio4ic xxxx x000 2 007a 16 int5 interrupt control register int5ic xx00 x000 2 007b 16 007c 16 int3 interrupt control register int3ic xx00 x000 2 007d 16 007e 16 int1 interrupt control register int1ic xx00 x000 2 007f 16 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 0087 16 0088 16 dma1 interrupt control register dm1ic xxxx x000 2 0089 16 uart2 transmit /nack interrupt control register s2tic xxxx x000 2 008a 16 dma3 interrupt control register dm3ic xxxx x000 2 008b 16 uart3 transmit /nack interrupt control register s3tic xxxx x000 2 008c 16 timer a1 interrupt control register ta1ic xxxx x000 2 008d 16 uart4 transmit /nack interrupt control register s4tic xxxx x000 2 008e 16 timer a3 interrupt control register ta3ic xxxx x000 2 008f 16 uart2 bus conflict detect interrupt control register bcn2ic xxxx x000 2 x: indeterminate blank spaces are reserved. no access is allowed.
page 19 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 0090 16 uart0 transmit /nack interrupt control register s0tic xxxx x000 2 0091 16 uart1/uart4 bus conflict detect interrupt control register bcn1ic/bcn4ic xxxx x000 2 0092 16 uart1 transmit/nack interrupt control register s1tic xxxx x000 2 0093 16 key input interrupt control register kupic xxxx x000 2 0094 16 timer b0 interrupt control register tb0ic xxxx x000 2 0095 16 intelligent i/o interrupt control register 1 iio1ic xxxx x000 2 0096 16 timer b2 interrupt control register tb2ic xxxx x000 2 0097 16 intelligent i/o interrupt control register 3 iio3ic xxxx x000 2 0098 16 timer b4 interrupt control register tb4ic xxxx x000 2 0099 16 009a 16 int4 interrupt control register int4ic xx00 x000 2 009b 16 009c 16 int2 interrupt control register int2ic xx00 x000 2 009d 16 009e 16 int0 interrupt control register int0ic xx00 x000 2 009f 16 exit priority control register rlvl xxxx 0000 2 00a0 16 interrupt request register 0 iio0ir 0000 000x 2 00a1 16 interrupt request register 1 iio1ir 0000 000x 2 00a2 16 interrupt request register 2 iio2ir 0000 000x 2 00a3 16 interrupt request register 3 iio3ir 0000 000x 2 00a4 16 interrupt request register 4 iio4ir 0000 000x 2 00a5 16 00a6 16 00a7 16 00a8 16 00a9 16 00aa 16 00ab 16 00ac 16 00ad 16 00ae 16 00af 16 00b0 16 interrupt enable register 0 iio0ie 00 16 00b1 16 interrupt enable register 1 iio1ie 00 16 00b2 16 interrupt enable register 2 iio2ie 00 16 00b3 16 interrupt enable register 3 iio3ie 00 16 00b4 16 interrupt enable register 4 iio4ie 00 16 00b5 16 00b6 16 00b7 16 00b8 16 00b9 16 00ba 16 00bb 16 00bc 16 00bd 16 00be 16 00bf 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 20 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 00c0 16 00c1 16 00c2 16 00c3 16 00c4 16 00c5 16 00c6 16 00c7 16 00c8 16 00c9 16 00ca 16 00cb 16 00cc 16 00cd 16 00ce 16 00cf 16 00d0 16 00d1 16 00d2 16 00d3 16 00d4 16 00d5 16 00d6 16 00d7 16 00d8 16 00d9 16 00da 16 00db 16 00dc 16 00dd 16 00de 16 00df 16 00e0 16 00e1 16 00e2 16 00e3 16 00e4 16 00e5 16 00e6 16 00e7 16 00e8 16 xxxx xxxx 2 si/o receive buffer register 0 g0rb 00e9 16 xxx0 xxxx 2 00ea 16 transmit buffer/receive data register 0 g0tb/g0dr xx 16 00eb 16 00ec 16 receive input register 0 g0ri xx 16 00ed 16 si/o communication mode register 0 g0mr 00 16 00ee 16 transmit output register 0 g0to xx 16 00ef 16 si/o communication control register 0 g0cr 0000 x011 2 x: indeterminate blank spaces are reserved. no access is allowed.
page 21 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 00f0 16 data compare register 00 g0cmp0 xx 16 00f1 16 data compare register 01 g0cmp1 xx 16 00f2 16 data compare register 02 g0cmp2 xx 16 00f3 16 data compare register 03 g0cmp3 xx 16 00f4 16 data mask register 00 g0msk0 xx 16 00f5 16 data mask register 01 g0msk1 xx 16 00f6 16 communication clock select register ccs xxxx 0000 2 00f7 16 00f8 16 xx 16 receive crc code register 0 g0rcrc 00f9 16 xx 16 00fa 16 00 16 transmit crc code register 0 g0tcrc 00fb 16 00 16 00fc 16 si/o expansion mode register 0 g0emr 00 16 00fd 16 si/o expansion receive control register 0 g0erc 00 16 00fe 16 si/o special communication interrupt detect register 0 g0irf 00 16 00ff 16 si/o expansion transmit control register 0 g0etc 0000 0xxx 2 0100 16 0101 16 0102 16 0103 16 0104 16 0105 16 0106 16 0107 16 0108 16 0109 16 010a 16 010b 16 010c 16 010d 16 010e 16 010f 16 0110 16 0111 16 0112 16 0113 16 0114 16 0115 16 0116 16 0117 16 0118 16 0119 16 011a 16 011b 16 011c 16 011d 16 011e 16 011f 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 22 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 0120 16 0121 16 0122 16 0123 16 0124 16 0125 16 0126 16 0127 16 0128 16 xxxx xxxx 2 si/o receive buffer register 1 g1rb 0129 16 xxx0 xxxx 2 012a 16 transmit buffer/receive data register 1 g1tb/g1dr xx 16 012b 16 012c 16 receive input register 1 g1ri xx 16 012d 16 si/o communication mode register 1 g1mr 00 16 012e 16 transmit output register 1 g1to xx 16 012f 16 si/o communication control register 1 g1cr 0000 x011 2 0130 16 data compare register 10 g1cmp0 xx 16 0131 16 data compare register 11 g1cmp1 xx 16 0132 16 data compare register 12 g1cmp2 xx 16 0133 16 data compare register 13 g1cmp3 xx 16 0134 16 data mask register 10 g1msk0 xx 16 0135 16 data mask register 11 g1msk1 xx 16 0136 16 0137 16 0138 16 xx 16 receive crc code register 1 g1rcrc 0139 16 xx 16 013a 16 00 16 transmit crc code register 1 g1tcrc 013b 16 00 16 013c 16 si/o expansion mode register 1 g1emr 00 16 013d 16 si/o expansion receive control register 1 g1erc 00 16 013e 16 si/o special communication interrupt detection register 1 g1irf 00 16 013f 16 si/o expansion transmit control register 1 g1etc 0000 0xxx 2 0140 16 0141 16 0142 16 0143 16 0144 16 0145 16 0146 16 0147 16 0148 16 0149 16 014a 16 014b 16 014c 16 014d 16 to 02af 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 23 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 02b1 16 02b2 16 02b3 16 02b4 16 02b5 16 02b6 16 02b7 16 02b8 16 02b9 16 02ba 16 02bb 16 02bc 16 02bd 16 02be 16 02bf 16 02c0 16 xx 16 x0 register y0 register x0r,y0r 02c1 16 xx 16 02c2 16 xx 16 x1 register y1 register x1r,y1r 02c3 16 xx 16 02c4 16 xx 16 x2 register y2 register x2r,y2r 02c5 16 xx 16 02c6 16 xx 16 x3 register y3 register x3r,y3r 02c7 16 xx 16 02c8 16 xx 16 x4 register y4 register x4r,y4r 02c9 16 xx 16 02ca 16 xx 16 x5 register y5 register x5r,y5r 02cb 16 xx 16 02cc 16 xx 16 x6 register y6 register x6r,y6r 02cd 16 xx 16 02ce 16 xx 16 x7 register y7 register x7r,y7r 02cf 16 xx 16 02d0 16 xx 16 x8 register y8 register x8r,y8r 02d1 16 xx 16 02d2 16 xx 16 x9 register y9 register x9r,y9r 02d3 16 xx 16 02d4 16 xx 16 x10 register y10 register x10r,y10r 02d5 16 xx 16 02d6 16 xx 16 x11 register y11 register x11r,y11r 02d7 16 xx 16 02d8 16 xx 16 x12 register y12 register x12r,y12r 02d9 16 xx 16 02da 16 xx 16 x13 register y13 register x13r,y13r 02db 16 xx 16 02dc 16 xx 16 x14 register y14 register x14r,y14r 02dd 16 xx 16 02de 16 xx 16 x15 register y15 register x15r,y15r 02df 16 xx 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 24 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 02e0 16 x/y control register xyc xxxx xx00 2 02e1 16 02e2 16 02e3 16 02e4 16 uart1 special mode register 4 u1smr4 00 16 02e5 16 uart1 special mode register 3 u1smr3 00 16 02e6 16 uart1 special mode register 2 u1smr2 00 16 02e7 16 uart1 special mode register u1smr 00 16 02e8 16 uart1 transmit/receive mode register u1mr 00 16 02e9 16 uart1 bit rate register u1brg xx 16 02ea 16 xx 16 uart1 transmit buffer register u1tb 02eb 16 xx 16 02ec 16 uart1 transmit/receive control register 0 u1c0 0000 1000 2 02ed 16 uart1 transmit/receive control register 1 u1c1 0000 0010 2 02ee 16 xx 16 uart1 receive buffer register u1rb 02ef 16 xx 16 02f0 16 02f1 16 02f2 16 02f3 16 02f4 16 uart4 special mode register 4 u4smr4 00 16 02f5 16 uart4 special mode register 3 u4smr3 00 16 02f6 16 uart4 special mode register 2 u4smr2 00 16 02f7 16 uart4 special mode register u4smr 00 16 02f8 16 uart4 transmit/receive mode register u4mr 00 16 02f9 16 uart4 bit rate register u4brg xx 16 02fa 16 xx 16 uart4 transmit buffer register u4tb 02fb 16 xx 16 02fc 16 uart4 transmit/receive control register 0 u4c0 0000 1000 2 02fd 16 uart4 transmit/receive control register 1 u4c1 0000 0010 2 02fe 16 xx 16 uart4 receive buffer register u4rb 02ff 16 xx 16 0300 16 timer b3, b4, b5 count start flag tbsr 000x xxxx 2 0301 16 0302 16 xx 16 timer a1-1 register ta11 0303 16 xx 16 0304 16 xx 16 timer a2-1 register ta21 0305 16 xx 16 0306 16 xx 16 timer a4-1 register ta41 0307 16 xx 16 0308 16 three-phase pwm control register 0 invc0 00 16 0309 16 three-phase pwm control register 1 invc1 00 16 030a 16 three-phase output buffer register 0 idb0 xx11 1111 2 030b 16 three-phase output buffer register 1 idb1 xx11 1111 2 030c 16 dead time timer dtt xx 16 030d 16 timer b2 interrupt generation frequency set counter ictb2 xx 16 030e 16 030f 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 25 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 0310 16 xx 16 timer b3 register tb3 0311 16 xx 16 0312 16 xx 16 timer b4 register tb4 0313 16 xx 16 0314 16 xx 16 timer b5 register tb5 0315 16 xx 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 timer b3 mode register tb3mr 00xx 0000 2 031c 16 timer b4 mode register tb4mr 00xx 0000 2 031d 16 timer b5 mode register tb5mr 00xx 0000 2 031e 16 031f 16 external interrupt request source select register ifsr 00 16 0320 16 0321 16 0322 16 0323 16 0324 16 uart3 special mode register 4 u3smr4 00 16 0325 16 uart3 special mode register 3 u3smr3 00 16 0326 16 uart3 special mode register 2 u3smr2 00 16 0327 16 uart3 special mode register u3smr 00 16 0328 16 uart3 transmit/receive mode register u3mr 00 16 0329 16 uart3 bit rate register u3brg xx 16 032a 16 xx 16 uart3 transmit buffer register u3tb 032b 16 xx 16 032c 16 uart3 transmit/receive control register 0 u3c0 0000 1000 2 032d 16 uart3 transmit/receive control register 1 u3c1 0000 0010 2 032e 16 xx 16 uart3 receive buffer register u3rb 032f 16 xx 16 0330 16 0331 16 0332 16 0333 16 0334 16 uart2 special mode register 4 u2smr4 00 16 0335 16 uart2 special mode register 3 u2smr3 00 16 0336 16 uart2 special mode register 2 u2smr2 00 16 0337 16 uart2 special mode register u2smr 00 16 0338 16 uart2 transmit/receive mode register u2mr 00 16 0339 16 uart2 bit rate register u2brg xx 16 033a 16 xx 16 uart2 transmit buffer register u2tb 033b 16 xx 16 033c 16 uart2 transmit/receive control register 0 u2c0 0000 1000 2 033d 16 uart2 transmit/receive control register 1 u2c1 0000 0010 2 033e 16 xx 16 uart2 receive buffer register u2rb 033f 16 xx 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 26 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m x: indeterminate blank spaces are reserved. no access is allowed. note: 1. the tcspr register maintains values set before reset, even after software reset or watchdog timer reset has been performed. address register symbol value after reset 0340 16 count start flag tabsr 00 16 0341 16 clock prescaler reset flag cpsrf 0xxx xxxx 2 0342 16 one-shot start flag onsf 00 16 0343 16 trigger select register trgsr 00 16 0344 16 up/down flag udf 00 16 0345 16 0346 16 xx 16 timer a0 register ta0 0347 16 xx 16 0348 16 xx 16 timer a1 register ta1 0349 16 xx 16 034a 16 xx 16 timer a2 register ta2 034b 16 xx 16 034c 16 xx 16 timer a3 register ta3 034d 16 xx 16 034e 16 xx 16 timer a4 register ta4 034f 16 xx 16 0350 16 xx 16 timer b0 register tb0 0351 16 xx 16 0352 16 xx 16 timer b1 register tb1 0353 16 xx 16 0354 16 xx 16 timer b2 register tb2 0355 16 xx 16 0356 16 timer a0 mode register ta0mr 00 16 0357 16 timer a1 mode register ta1mr 00 16 0358 16 timer a2 mode register ta2mr 00 16 0359 16 timer a3 mode register ta3mr 00 16 035a 16 timer a4 mode register ta4mr 00 16 035b 16 timer b0 mode register tb0mr 00xx 0000 2 035c 16 timer b1 mode register tb1mr 00xx 0000 2 035d 16 timer b2 mode register tb2mr 00xx 0000 2 035e 16 timer b2 special mode register tb2sc xxxx xxx0 2 035f 16 count source prescaler register (1) tcspr 0xxx 0000 2 0360 16 0361 16 0362 16 0363 16 0364 16 uart0 special mode register 4 u0smr4 00 16 0365 16 uart0 special mode register 3 u0smr3 00 16 0366 16 uart0 special mode register 2 u0smr2 00 16 0367 16 uart0 special mode register u0smr 00 16 0368 16 uart0 transmit/receive mode register u0mr 00 16 0369 16 uart0 bit rate register u0brg xx 16 036a 16 xx 16 uart0 transmit buffer register u0tb 036b 16 xx 16 036c 16 uart0 transmit/receive control register 0 u0c0 0000 1000 2 036d 16 uart0 transmit/receive control register 1 u0c1 0000 0010 2 036e 16 xx 16 uart0 receive buffer register u0rb 036f 16 xx 16
page 27 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 dma0 request source select register dm0sl 0x00 0000 2 0379 16 dma1 request source select register dm1sl 0x00 0000 2 037a 16 dma2 request source select register dm2sl 0x00 0000 2 037b 16 dma3 request source select register dm3sl 0x00 0000 2 037c 16 xx 16 crc data register crcd 037d 16 xx 16 037e 16 crc input register crcin xx 16 037f 16 0380 16 xxxx xxxx 2 a/d0 register 0 ad00 0381 16 0000 0000 2 0382 16 xx 16 a/d0 register 1 ad01 0383 16 xx 16 0384 16 xx 16 a/d0 register 2 ad02 0385 16 xx 16 0386 16 xx 16 a/d0 register 3 ad03 0387 16 xx 16 0388 16 xx 16 a/d0 register 4 ad04 0389 16 xx 16 038a 16 xx 16 a/d0 register 5 ad05 038b 16 xx 16 038c 16 xx 16 a/d0 register 6 ad06 038d 16 xx 16 038e 16 xx 16 a/d0 register 7 ad07 038f 16 xx 16 0390 16 0391 16 0392 16 0393 16 0394 16 a/d0 control register 2 ad0con2 xx0x xxx0 2 0395 16 a/d0 control register 3 ad0con3 xxxx x000 2 0396 16 a/d0 control register 0 ad0con0 00 16 0397 16 a/d0 control register 1 ad0con1 00 16 0398 16 d/a register 0 da0 xx 16 0399 16 039a 16 d/a register 1 da1 xx 16 039b 16 039c 16 d/a control register dacon xxxx xx00 2 039d 16 039e 16 039f 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 28 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 function select register d1 psd1 x0xx xx00 2 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 function select register c3 psc3 x0xx xxxx 2 03ae 16 03af 16 function select register c psc 00x0 0000 2 03b0 16 function select register a0 ps0 00 16 03b1 16 function select register a1 ps1 00 16 03b2 16 function select register b0 psl0 00 16 03b3 16 function select register b1 psl1 00 16 03b4 16 function select register a2 ps2 00x0 0000 2 03b5 16 function select register a3 ps3 00 16 03b6 16 function select register b2 psl2 00x0 0000 2 03b7 16 function select register b3 psl3 00 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 03c0 16 port p6 register p6 xx 16 03c1 16 port p7 register p7 xx 16 03c2 16 port p6 direction register pd6 00 16 03c3 16 port p7 direction register pd7 00 16 03c4 16 port p8 register p8 xx 16 03c5 16 port p9 register p9 xx 16 03c6 16 port p8 direction register pd8 00x0 0000 2 03c7 16 port p9 direction register pd9 00 16 03c8 16 port p10 register p10 xx 16 03c9 16 03ca 16 port p10 direction register pd10 00 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 x: indeterminate blank spaces are reserved. no access is allowed.
page 29 4. special function registers (sfrs) 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m address register symbol value after reset 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 pull-up control register 2 pur2 00 16 03db 16 pull-up control register 3 pur3 00 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 port p0 register (1) p0 xx 16 03e1 16 port p1 register (1) p1 xx 16 03e2 16 port p0 direction register (1) pd0 00 16 03e3 16 port p1 direction register (1) pd1 00 16 03e4 16 port p2 register (1) p2 xx 16 03e5 16 port p3 register (1) p3 xx 16 03e6 16 port p2 direction register (1) pd2 00 16 03e7 16 port p3 direction register (1) pd3 00 16 03e8 16 port p4 register (1) p4 xx 16 03e9 16 port p5 register (1) p5 xx 16 03ea 16 port p4 direction register (1) pd4 00 16 03eb 16 port p5 direction register (1) pd5 00 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 pull-up control register 0 pur0 00 16 03f1 16 pull-up control register 1 pur1 xxxx 0000 2 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port control register pcr xxxx xxx0 2 x: indeterminate blank spaces are reserved. no access is allowed. note: 1. pins, functioning as bus control pins, cannot be selected as i/o ports.
page 30 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m 5. electrical characteristics table 5.1 absolute maximum ratings l o b m y sr e t e m a r a pn o i t i d n o ce u l a vt i n u v 1 c c v , 2 c c e g a t l o v y l p p u sv 1 c c v a = c c 0 . 6 o t 3 . 0 - v v 2 c c e g a t l o v y l p p u s-v o t 3 . 0 - 1 c c v v a c c e g a t l o v y l p p u s g o l a n av 1 c c v a = c c 0 . 6 o t 3 . 0 - v v i e g a t l o v t u p n iv n c , t e s e r s s 6 p , e t y b , 0 6 p - 7 7 p , 2 7 p - 7 , 8 p 0 8 p - 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 v , f e r x , n i v o t 3 . 0 - 1 c c 3 . 0 +v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 , 4 p 0 4 p - 7 5 p , 0 5 p - 7 v o t 3 . 0 - 2 c c 3 . 0 + 7 p 0 7 p , 1 0 . 6 o t 3 . 0 - v o e g a t l o v t u p t u o6 p 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 x , t u o v o t 3 . 0 - 1 c c 3 . 0 +v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 , 4 p 0 4 p - 7 5 p , 0 5 p - 7 v o t 3 . 0 - 2 c c 3 . 0 + 7 p 0 7 p , 1 0 . 6 o t 3 . 0 - d pn o i t a p i s s i d r e w o p c 5 2 = r p o t0 0 5w m r p o te r u t a r e p m e t t n e i b m a g n i t a r e p o / 5 8 o t 0 2 - 5 8 o t 0 4 - ) 1 ( c g t s te r u t a r e p m e t e g a r o t s 0 5 1 o t 5 6 -c : e t o n 5 8 o t 0 4 - f o e g n a r e r u t a r e p m e t f i e c i f f o s e l a s r u o t c a t n o c . 1 . d e r i u q e r s i c
page 31 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m table 5.2 recommended operating conditions (v cc1 = v cc2 =3.0v to 5.5v at topr=?20 to 85 o c unless otherwise specified) l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t. x a m v 1 c c v , 2 c c v ( e g a t l o v y l p p u s 1 c c v 2 c c )0 . 30 . 55 . 5v v a c c e g a t l o v y l p p u s g o l a n a v 1 c c v v s s e g a t l o v y l p p u s 0v v a s s e g a t l o v y l p p u s g o l a n a 0v v h i ) " h " ( h g i h t u p n i e g a t l o v 2 p 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 v 8 . 0 2 c c v 2 c c v 6 p 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 7 ) 3 ( 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 x , n i , v n c , t e s e r s s e t y b , v 8 . 0 1 c c v 1 c c 7 p 0 7 p , 1 v 8 . 0 1 c c 0 . 6 0 p 0 0 p - 7 1 p , 0 1 p - 7 ) e d o m p i h c - e l g n i s n i (v 8 . 0 2 c c v 2 c c 0 p 0 0 p - 7 1 p , 0 1 p - 7 ) e d o m r o s e c o r p o r c i m d n a e d o m n o i s n a p x e y r o m e m n i ( v 5 . 0 2 c c v 2 c c v l i ) " l " ( w o l t u p n i e g a t l o v p2 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 0v 2 . 0 2 c c v 6 p 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 ) 3 ( 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 x , n i , v n c , t e s e r s s e t y b , 0v 2 . 0 1 c c 0 p 0 0 p - 7 1 p , 0 1 p - 7 ) e d o m p i h c - e l g n i s n i (0v 2 . 0 2 c c 0 p 0 0 p - 7 1 p , 0 1 p - 7 ) e d o m r o s e c o r p o r c i m d n a e d o m n o i s n a p x e y r o m e m n i ( 0v 6 1 . 0 2 c c i ) k a e p ( h o h g i h t u p t u o k a e p t n e r r u c ) " h " ( ) 2 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 , 6 p 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 0 . 0 1 -a m i ) g v a ( h o t u p t u o e g a r e v a t n e r r u c ) " h " ( h g i h ) 1 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 , 6 p 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 0 . 5 -a m i ) k a e p ( l o w o l t u p t u o k a e p t n e r r u c ) " l " ( ) 2 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 , 6 p 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 0 . 0 1a m i ) g v a ( l o w o l t u p t u o e g a r e v a t n e r r u c ) " l " ( ) 1 ( 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 5 p , 0 5 p - 7 , 6 p 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 0 . 5a m : s e t o n . s m 0 0 1 s i t n e r r u c t u p t u o e g a r e v a n e h w s e u l a v l a c i p y t . 1 i l a t o t . 2 ) k a e p ( l o 8 p , 2 p , 1 p , 0 p r o f 6 8 p , 7 . s s e l r o a m 0 8 e b t s u m 0 1 p d n a , 9 p , i l a t o t ) k a e p ( l o 8 p d n a , 7 p , 6 p , 5 p , 4 p , 3 p r o f 0 8 p o t 4 . s s e l r o a m 0 8 e b t s u m i l a t o t ) k a e p ( h o . s s e l r o a m 0 4 - e b t s u m 2 p d n a , 1 p , 0 p r o f i l a t o t ) k a e p ( h o 8 p r o f 6 8 p , 7 . s s e l r o a m 0 4 - e b t s u m 0 1 p d n a , 9 p , i l a t o t ) k a e p ( h o . s s e l r o a m 0 4 - e b t s u m 5 p d n a , 4 p , 3 p r o f i l a t o t ) k a e p ( h o 8 p d n a , 7 p , 6 p r o f 0 8 p o t 4 . s s e l r o a m 0 4 - e b t s u m . 3v h i v d n a l i 8 p r o f e c n e r e f e r 7 8 p n e h w s e i l p p a 7 . t r o p t u p n i e l b a m m a r g o r p a s a d e s u s i 8 p n e h w y l p p a t o n s e o d t i 7 x s a d e s u s i n i c .
page 32 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m table 5.2 recommended operating conditions (continued) (v cc1 =v cc2 =3.0v to 5.5v at topr=?0 to 85 o c unless otherwise specified) l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. p y t. x a m ( f k l c b )y c n e u q e r f n o i t a r e p o u p cv 1 c c v 5 . 5 o t 2 . 4 =02 3z h m v 1 c c v 5 . 5 o t 0 . 3 =04 2z h m x ( f n i )y c n e u q e r f t u p n i k c o l c n i a mv 1 c c v 5 . 5 o t 2 . 4 =02 3z h m v 1 c c v 5 . 5 o t 0 . 3 =04 2z h m x ( f n i c )y c n e u q e r f k c o l c b u s 8 6 7 . 2 30 5z h k ( f g n i r ) ( y c n e u q e r f r o t a l l i c s o p i h c - n o5 2 = r p o t) c 5 . 012 z h m ( f l l p )y c n e u q e r f k c o l c l l pv 1 c c v 5 . 5 o t 2 . 4 =0 12 3z h m v 1 c c v 5 . 5 o t 0 . 3 =0 14 2z h m t ) l l p ( u s r e z i s e h t n y s y c n e u q e r f l l p e z i l i b a t s o t e m i t t i a wv 1 c c v 0 . 5 =5s m v 1 c c v 3 . 3 =0 1s m
page 33 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics v cc1 =v cc2 =5v table 5.3 electrical characteristics (v cc1 =v cc2 =4.2 to 5.5v, v ss =0v at topr= ?0 to 85 o c, f(bclk)=32mh z unless otherwise specified) l o b m y sr e t e m a r a pn o i t i d n o c d r a d n a t s t i n u . n i m. p y t. x a m v h o ) " h " ( h g i h t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 i h o a m 5 - = v c c - 2 0 . 2 v c c 2 v 6 p 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 - 9 p 7 0 1 p , 0 0 1 p - 7 i h o a m 5 - = v c c - 1 0 . 2 v c c 1 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 i h o 0 0 2 - = a v c c - 2 3 . 0 v c c 2 v 6 p 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 - 9 p 7 0 1 p , 0 0 1 p - 7 i h o 0 0 2 - = a v c c - 1 3 . 0 v c c 1 x t u o i h o a m 1 - =0 . 3v c c 1 v x t u o c r e w o p h g i h d e i l p p a d a o l o n5 . 2v r e w o p w o l d e i l p p a d a o l o n6 . 1 v l o ) " l " ( w o l t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 i l o a m 5 =0 . 2v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 i l o 0 0 2 = a5 4 . 0v x t u o i l o a m 1 =0 . 2v x t u o c r e w o p h g i h d e i l p p a d a o l o n0v r e w o p w o l d e i l p p a d a o l o n0 v + t v - - t s i s e r e t s y h 0 a t , y d r , d l o h n i 4 a t - n i 0 b t , n i 5 b t - n i , d a , 5 t n i - 0 t n i g r t , 4 k l c - 0 k l c , 4 s t c - 0 s t c , 0 a t t u o 4 a t - t u o , 4 d x r - 0 d x r , 3 i k - 0 i k , i m n , 4 a d s - 0 a d s , 4 l c s - 0 l c s 2 . 00 . 1v t e s e r2 . 08 . 1v i h i ) " h " ( h g i h t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 x , n i v n c , t e s e r , s s e t y b , v i v 5 =0 . 5 a i l i ) " l " ( w o l t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 9 p , 0 9 p - 7 , 0 1 p 0 0 1 p - 7 x , n i v n c , t e s e r , s s e t y b , v i v 0 =0 . 5 - a r p u l l u p e c n a t s i s e r p u - l l u p 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 v i v 0 =0 20 47 6 1k ? f r n i x e c n a t s i s e r k c a b d e e fx n i 5 . 1m ? f r n i c x e c n a t s i s e r k c a b d e e fx n i c 5 1m ? v m a r e g a t l o v y b d n a t s m a re d o m p o t s n i0 . 2v i c c t n e r r u c y l p p u s r e w o p, e d o m p i h c - e l g n i s n i t f e l e r a s n i p t u p t u o s n i p r e h t o d n a n e p o v o t d e t c e n n o c e r a s s . , e v a w e r a u q s , z h m 2 3 = ) k l c b ( f n o i s i v i d o n 2 20 6a m , e d o m t i a w n i , z h k 2 3 = ) k l c b ( f c 5 2 = r p o t 0 1 a , s p o t s k c o l c e l i h w5 2 = r p o tc 8 . 05 a , s p o t s k c o l c e l i h w5 8 = r p o tc 0 2 a
page 34 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics v cc1 =v cc2 =5v l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m -n o i t u l o s e rv f e r v = 1 c c 0 1s t i b l n ir o r r e y t i r a e n i l n o n l a r g e t n iv f e r v = 1 c c v = 2 c c v 5 = n a 0 n a o t 7 ,, 0 x e n a 1 x e n a 3 b s l b s l p m a - p o l a n r e t x e e d o m n o i t c e n n o c 7 b s l b s l l n dr o r r e y t i r a e n i l n o n l a i t n e r e f f i d 1 b s l -r o r r e t e s f f o 3 b s l -r o r r e n i a g 3 b s l r r e d d a l r e d d a l r o t s i s e rv = f e r v 1 c c 80 4k ? t v n o c e m i t n o i s r e v n o c t i b - 0 1 ) 2 , 1 ( 6 0 . 2 s t v n o c e m i t n o i s r e v n o c t i b - 8 ) 2 , 1 ( 5 7 . 1 s t p m a s e m i t g n i l p m a s ) 1 ( 8 8 1 . 0 s v f e r e g a t l o v e c n e r e f e r 2v 1 c c v v a i e g a t l o v t u p n i g o l a n a 0v f e r v : s e t o n x ( f e d i v i d . 1 n i p e e k o t , z h m 6 1 g n i d e e c x e f i , ) . s s e l r o z h m 6 1 t a y c n e u q e r f d a . n o i t c n u f d l o h d n a e l p m a s e h t g n i s u h t i w . 2 l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m -n o i t u l o s e r 8s t i b -y c a r u c c a e t u l o s b a 0 . 1% t u s e m i t p u t e s 3 s r o e c n a t s i s e r t u p t u o 40 10 2k ? i f e r v t n e r r u c t u p n i y l p p u s r e w o p e c n e r e f e r) 1 e t o n (5 . 1a m : e t o n g n i e b t o n , r e t r e v n o c a / d e h t f o ) 1 , 0 = i ( r e t s i g e r i a d e h t . r e t r e v n o c a / d e n o g n i s u n e h w t n e m e r u s a e m . 1 0 0 " o t t e s s i , d e s u 6 1 . d e d u l c x e s i r e t r e v n o c d / a e h t n i r e d d a l r o t s i s e r e h t . " i f e r v v o n ( " 0 " o t t e s s i r e t s i g e r 1 n o c 0 d a e h t n i t i b t u c v e h t f i n e v e s w o l f f e r . ) n o i t c e n n o c table 5.4 a/d conversion characteristics (v cc1 =v cc2 =av cc =v ref =4.2 to 5.5v, vss= av ss = 0v at topr=?0 to 85 o c, f(bclk) = 32mh z unless otherwise specified) table 5.5 d/a conversion characteristics (v cc1 =v cc2 =v ref =4.2 to 5.5v, v ss =av ss= 0v at topr=20 to 85 o c, f(bclk) = 32mh z unless otherwise specified)
page 35 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics v cc1 =v cc2 =5v l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m 1 c a t ) b d - d r ( ) d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 1 c a t ) b d - d a ( ) d r a d n a t s s c , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 2 c a t ) b d - d r ( ) s u b d r x e l p i t l u m e h t h t i w e c a p s a g n i s s e c c a n e h w , d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 2 c a t ) b d - d a ( ) s u b d e x e l p i t l u m e h t h t i w e c a p s a g n i s s e c c a n e h w , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n u s t ) k l c b - b d ( e m i t p u t e s t u p n i a t a d 6 2s n u s t ) k l c b - y d r ( e m i t p u t e s t u p n i y d r 6 2s n u s t ) k l c b - d l o h ( e m i t p u t e s t u p n i d l o h 0 3s n h t ) b d - d r ( e m i t d l o h t u p n i a t a d 0s n h t ) y d r - k l c b ( e m i t d l o h t u p n i y d r 0s n h t ) d l o h - k l c b ( e m i t d l o h t u p n i d l o h 0s n d t ) a d l h - k l c b ( e m i t y a l e d t u p t u o a d l h 5 2s n : e t o n a t r e s n i . s e l c y c s u b l a n r e t x e d n a y c n c e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 ( f , y c n e u q e r f n o i t a r e p o e h t r e w o l r o e t a t s t i a w k l c b . e v i t a g e n s i e u l a v d e t a l u c l a c e h t f i , ) l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c te m i t e l c y c t u p n i k c o l c l a n r e t x e 5 2 . 1 3s n w t ) h ( h t d i w ) " h " ( h g i h t u p n i k c o l c l a n r e t x e 5 7 . 3 1s n w t ) l ( h t d i w ) " l " ( w o l t u p n i k c o l c l a n r e t x e 5 7 . 3 1s n r te m i t e s i r k c o l c l a n r e t x e 5s n f te m i t l l a f k c o l c l a n r e t x e 5s n timing requirements (v cc1 =v cc2 =4.2 to 5.5v, v ss =0v at topr=?0 to 85 o c unless otherwise specified) table 5.6 external clock input table 5.7 memory expansion mode and microprocessor mode t ac1(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (if external bus cycle is a + b , m=(bx2)+1) t ac2(ad C db) = f (bclk) x 2 C 35 10 x p 9 [ns] (if external bus cycle is a + b , p={(a+b-1)x2}+1) C 35 10 x n 9 [ns] (if external bus cycle is a + b , n=a+b) f (bclk) t ac1(ad C db) = t ac2(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (if external bus cycle is a + b , m=(bx2)-1)
page 36 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics v cc1 =v cc2 =5v l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 1s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 4s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 4s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 2s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) p u ( i a t t u o e m i t e l c y c t u p n i 0 0 0 2s n w t ) h p u ( i a t t u o h t d i w ) " h " ( h g i h t u p n i 0 0 0 1s n w t ) l p u ( i a t t u o h t d i w ) " l " ( w o l t u p n i 0 0 0 1s n u s t ) n i t - p u ( i a t t u o e m i t p u t e s t u p n i 0 0 4s n h t ) p u - n i t ( i a t t u o e m i t d l o h t u p n i 0 0 4s n timing requirements (v cc1 =v cc2 =4.2 to 5.5v, v ss =0v at topr=?0 to 85 o c unless otherwise specified) table 5.8 timer a input (count source input in event counter mode) table 5.9 timer a input (gate input in timer mode) table 5.10 timer a input (external trigger input in one-shot timer mode) table 5.11 timer a input (external trigger input in pulse width modulation mode) table 5.12 timer a input (counter increment/decrement input in event counter mode)
page 37 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics v cc1 =v cc2 =5v l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i ) e g d e e n o n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 1s n w t ) h b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w ) " h " ( h g i h t u p n i 0 4s n w t ) l b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w ) " l " ( w o l t u p n i 0 4s n c t ) b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 2s n w t ) h b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w ) " h " ( h g i h t u p n i 0 8s n w t ) l b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w ) " l " ( w o l t u p n i 0 8s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i mx a m c t ) d a ( d a g r t ) r e g g i r t r o f d e r i u q e r ( e m i t e l c y c t u p n i 0 0 0 1s n w t ) l d a ( d a g r t h t d i w ) " l " ( w o l t u p n i 5 2 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) k c ( e m i t e l c y c t u p n i i k l c 0 0 2s n w t ) h k c ( h t d i w ) " h " ( h g i h t u p n i i k l c 0 0 1s n w t ) l k c ( h t d i w ) " l " ( w o l t u p n i i k l c 0 0 1s n d t ) q - c ( e m i t y a l e d t u p t u o i d x t 0 8s n h t ) q - c ( e m i t d l o h i d x t 0s n u s t ) c - d ( e m i t p u t e s t u p n i i d x r 0 3s n h t ) q - c ( e m i t d l o h t u p n i i d x r 0 9s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m w t ) h n i ( h t d i w ) " h " ( h g i h t u p n i i t n i 0 5 2s n w t ) l n i ( h t d i w ) " l " ( w o l t u p n i i t n i 0 5 2s n timing requirements (v cc1 = v cc2 = 4.2 to 5.5v, v ss = 0v at topr = ?0 to 85 o c unless otherwise specified) table 5.13 timer b input (count source input in event counter mode) table 5.14 timer b input (pulse period measurement mode) table 5.15 timer b input (pulse width measurement mode) table 5.16 a/d trigger input table 5.17 serial i/o _______ table 5.18 external interrupt inti input
page 38 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics v cc1 =v cc2 =5v l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u . n i m. x a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 3 -s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 3 -s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d r - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 5 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 5 -s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 2 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n w t ) r w ( h t d i w t u p t u o r w ) 2 e t o n (s n t d(db C wr) = f (bclk) C 20 [ns] t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t w(wr) = f (bclk) x 2 10 x n 9 C 15 [ns] 1. values can be obtained from the following equations, according to bclk frequency. 2. values can be obtained from the following equations, according to bclk frequency and external bus cycles. (if external bus cycle is a + b , n=(bx2)-1) 10 x m 9 (if external bus cycle is a + b , m= b) notes: see figure 5.1 switching characteristics (v cc1 = v cc2 = 4.2 to 5.5v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.19 memory expansion mode and microprocessor mode (when accessing external memory space)
page 39 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics v cc1 =v cc2 =5v l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u . n i m. x a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 3 -s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 3 -s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d r - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 5 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 5 -s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 2 e t o n (s n h t (- r w) b d ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n d t ) e l a - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o l a n g i s e l a 8 1s n h t ) e l a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s e l a 5 -s n d t ) e l a - d a ( ) d r a d n a t s s s e r d d a ( e m i t y a l e d t u p t u o l a n g i s e l a ) 3 e t o n (s n h t ) d a - e l a ( ) d r a d n a t s s s e r d d a ( e m i t d l o h t u p t u o l a n g i s e l a ) 4 e t o n (s n z d t ) d a - d r ( e m i t t r a t s t a o l f t u p t u o s s e r d d a 8s n t d(db C wr) = 10 x m 9 C 25 [ns] (if external bus cycle is a + b , m= (bx2)-1) t h(rd C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(rd C cs) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t d(ad C ale) = f (bclk) x 2 9 C 20 [ns] (if external bus cycle is a + b , n= a) t h(ale C ad) = f ( bclk ) x 2 9 C 10 [ns] (if external bus cycle is a + b , n= a) f (bclk) x 2 1. values can be obtained from the following equations, according to bclk frequency. 2. values can be obtained from the following equations, according to bclk frequency and external bus cycle. 3. values can be obtained from the following equations, according to bclk frequency and external bus cycle. 10 x m 10 x n 4. values can be obtained from the following equations, according to bclk frequency and external bus cycle. 10 x n notes: see figure 5.1 switching characteristics (v cc = 4.2 to 5.5v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.20 memory expansion mode and microprocessor mode (when accessing an external memory space with the multiplexed bus)
page 40 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics v cc1 =v cc2 =5v p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf figure 5.1 p0 to p10 measurement circuit
page 41 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m figure 5.2 v cc1 =v cc2 =5v timing diagram (1) bclk rd 18ns.max -5ns.min hi-z db 0ns.min 0ns.min t su(db-bclk) t d(bclk-rd) 26ns.min (1) csi t d(bclk-cs) 18ns.max (1) adi t h(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min bhe tcyc t d(bclk-ad) 0ns.min t ac1(ad-db) (2) wr,wrl, wrh 18ns.max -5ns.min bclk csi t d(bclk-cs) 18ns.max adi t d(bclk-ad) 18ns.max -3ns.min -3ns.min tcyc bhe dbi t d(bclk-wr) t h(wr-db) (3) t d(db-wr) =(tcyc x m-20)ns.min (if external bus cycle is a +b , m=b) t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min ( if external bus c y cle is a +1 bus cycle) [ write timing ] (1 +1 bus cycle) note: 3. varies with operation frequency: measurement conditions: ? v cc1 =v cc2 =4.2 to 5.5v ? input high and low voltage: v ih =2.5v, v il =0.8v ? output high and low voltage: v oh =2.0v, v ol =0.8v memory expansion mode and microprocessor mode (when accessing an external memory space) notes: 1. values guaranteed only when the microcomputer is used independently. a maximum of 35ns is guaranteed for t d(bclk-ad) +t su(db-bclk) . 2. varies with operation frequency: t ac1(rd-db) =(tcyc/2 x m-35)ns.max (if external bus cycle is a + b , m=(b x 2)+1) t ac1(ad-db) =(tcyc x n-35)ns.max (if external bus cycle is a + b , n=a+b) t d(db-wr) (3) tcyc= 10 f (bclk) 9
page 42 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m figure 5.3 v cc1 =v cc2 =5v timing diagram (2) bclk csi adi rd -5ns.min bhe adi /dbi 26ns.min t d(bclk-rd) t su(db-bclk) t ac2(rd-db) t dz(rd-ad) 8ns.max ale t d(bclk-ale) 18ns.max t d(bclk-cs) t d(ad-ale) t h(ale-ad) t h(bclk-rd) t h(rd-ad) t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) t h(bclk-ale) tcyc memory expansion mode and microprocessor mode (when accessing an external memory space with the multiplexed bus) -5ns.min bclk csi adi bhe adi /dbi wr,wrl, wrh t h(wr-cs) ale t h(bclk-wr) t d(db-wr) 18ns.max t ac2(ad-db) [ read timing ] (2 +2 bus cycle) address (1) (1) (1) t d(ad-ale) =(tcyc/2 x n-20)ns.min (if external bus cycle is a + b , n=a) t h(ale-ad) =(tcyc/2 x n-10)ns.min (if external bus cycle is a + b , n=a) t h(rd-ad) =(tcyc/2-10)ns.min, t h(rd-cs) =(tcyc/2-10)ns.min t ac2(rd-db) =(tcyc/2 x m-35)ns.max (if external bus cycle is a + b , m=(b x 2)-1) t ac2(ad-db) =(tcyc/2 x p-35)ns.max (if external bus cycle is a + b , p={(a+b-1) x 2}+1) note: 1. varies with operation frequency: data input address (1) [ write timing ] (2 +2 bus cycle) address data output address (2) (2) t d(ad-ale) =(tcyc/2 x n - 20)ns.min (if external bus cycle is a + b , n=a) t h(ale-ad) =(tcyc/2 x n -10)ns.min (if external bus cycle is a + b , n=a) t h(wr-ad) =(tcyc/2-10)ns.min, t h(wr-cs) =(tcyc/2-10)ns.min, t h(wr-db) =(tcyc/2-10)ns.min t d(db-wr) =(tcyc/2 x m-25)ns.min ( if external bus c y cle is a ? v cc1 =v cc2 =4.2 to 5.5v ? input high and low voltage: v ih =2.5v, v il =0.8v ? output high and low voltage: v oh =2.0v, v ol =0.8v vcc 1 =vcc 2 =5v -3ns.min (1) t h(bclk-ad) -3ns.min 0ns.min (1) 18ns.max -5ns.min 18ns.max 18ns.max t h(wr-db) (2) t h(bclk-ad) -3ns.min t h(wr-ad) 18ns.max t d(bclk-wr) 18ns.max t d(bclk-ad) t d(ad-ale) (2) t d(bclk-cs) 18ns.max t d(bclk-ale) -5ns.min t h(bclk-ale) tcyc (2) t h(bclk-cs) -3ns.min t h(ale-ad) (2) tcyc= 10 f (bclk) 9
page 43 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m t su(d C c) tai in input tai out input in event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) tw (tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) t h(t in C up) t su(up C t in ) tai in input (when counting on the falling edge) tai in input (when counting on the rising edge) tai out input (counter increment/ decrement input) inti input ad trg input vcc 1 =vcc 2 =5v nmi input 2 cpu clock cycles + 300ns or more ("l" width) 2 cpu clock cycles + 300ns or more figure 5.4 v cc1 =v cc2 =5v timing diagram (3)
page 44 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m t h(bclk C hold) t su(hold C bclk) t d(bclk C hlda) t d(bclk C hlda) hi C z measurement conditions ? v cc1 =v cc2 =4.2 to 5.5v ? input high and low voltage: v ih =4.0v, v il =1.0v ? output high and low voltage: v oh =2.5v, v ol =2.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 rdy input t su(rdy C bclk) t h(bclk C rdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) vcc 1 =vcc 2 =5v figure 5.5 v cc1 =v cc2 =5v timing diagram (4)
page 45 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics v cc1 =v cc2 =3.3v p u o r g 0 8 / c 2 3 m table 5.21 electrical characteristics (v cc1 =v cc2 =3.0 to 3.6v, v ss =0v at topr = 20 to 85 o c, f(bclk)=24mh z unless otherwise specified) l o b m y sr e t e m a r a pn o i t i d n o c d r a d n a t s t i n u . n i m. p y t. x a m v h o ) " h " ( h g i h t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 i h o a m 1 - =v 2 c c 6 . 0 -v 2 c c v 6 p 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 8 p , 7 9 p , 0 - 9 p 7 0 1 p , 0 0 1 p - 7 v 1 c c 6 . 0 -v 1 c c v x t u o i h o a m 1 . 0 - =7 . 2v 1 c c v x t u o c r e w o p h g i h d e i l p p a d a o l o n5 . 2v r e w o p w o l d e i l p p a d a o l o n6 . 1v v l o ) " l " ( w o l t u p t u o e g a t l o v 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 - 4 p 7 5 p , 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 4 , 8 p 6 8 p , 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 i l o a m 1 =5 . 0v x t u o i l o a m 1 . 0 =5 . 0v x t u o c r e w o p h g i h d e i l p p a d a o l o n0v r e w o p w o l d e i l p p a d a o l o n0v v + t v - - t s i s e r e t s y h 0 a t , y d r , d l o h n i 4 a t - n i 0 b t , n i 5 b t - n i , d a , 5 t n i - 0 t n i g r t - 0 k l c , 4 s t c - 0 s t c , 0 a t , 4 k l c t u o 4 a t - t u o - 0 d x r , 3 i k - 0 i k , i m n , 4 a d s - 0 a d s , 4 l c s - 0 l c s , 4 d x r 2 . 00 . 1v t e s e r2 . 08 . 1v i h i ) " h " ( h g i h t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 - 4 p 7 5 p , 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 x , n i v n c , t e s e r , s s , e t y b v i v 3 =0 . 4 a i l i ) " l " ( w o l t u p n i t n e r r u c 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 - 4 p 7 5 p , 0 5 p - 7 6 p , 0 6 p - 7 7 p , 0 7 p - 7 8 p , 0 8 p - 7 , 9 p 0 9 p - 7 0 1 p , 0 0 1 p - 7 x , n i v n c , t e s e r , s s , e t y b v i v 0 =0 . 4 - a r p u l l u p e c n a t s i s e r p u - l l u p 0 p 0 0 p - 7 1 p , 0 1 p - 7 2 p , 0 2 p - 7 3 p , 0 3 p - 7 4 p , 0 4 p - 7 , 5 p 0 5 p - 7 6 p , 0 6 p - 7 7 p , 2 7 p - 7 8 p , 0 8 p - 4 8 p , 6 , 8 p 7 9 p , 0 9 p - 7 0 1 p , 0 0 1 p - 7 v i v 0 =0 40 70 0 5k ? f r n i x e c n a t s i s e r k c a b d e e fx n i 0 . 3m ? f r n i c x e c n a t s i s e r k c a b d e e fx n i c 0 . 0 3m ? v m a r e g a t l o v y b d n a t s m a re d o m p o t s n i0 . 2v i c c y l p p u s r e w o p t n e r r u c : n o i t i d n o c t n e m e r u s a e m , e d o m p i h c - e l g n i s n i n e p o t f e l e r a s n i p t u p t u o e r a s n i p r e h t o d n a v o t d e t c e n n o c s s . , e v a w e r a u q s , z h m 4 2 = ) k l c b ( f n o i s i v i d o n 7 15 3a m , e d o m t i a w n i , z h k 2 3 = ) k l c b ( f 5 2 = r p o tc 0 1 a , s p o t s k c o l c e l i h w5 2 = r p o tc 8 . 05 a , s p o t s k c o l c e l i h w5 8 = r p o tc 0 5 a
page 46 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics v cc1 =v cc2 =3.3v p u o r g 0 8 / c 2 3 m table 5.22 a/d conversion characteristics (v cc1 =v cc2 =av cc =v ref = 3.0 to 3.6v, v ss =av ss =0v at topr = 20 to 85 o c, f(bclk) = 24mh z unless otherwise specified) table 5.23 d/a conversion characteristics ( v cc1 =v cc2 = v ref =3.0 to 3.6v, v ss =av ss = 0v at topr = 20 to 85 o c, f(bclk) = 24mh z unless otherwise specified) l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m -n o i t u l o s e rv f e r v = 1 c c 0 1s t i b l n ir o r r e y t i r a e n i l n o n l a r g e t n i) t i b - 8 ( h & s o nv 1 c c v = 2 c c v = f e r v 3 . 3 =2 b s l l n dr o r r e y t i r a e n i l n o n l a i t n e r e f f i d) t i b - 8 ( h & s o n1 b s l -r o r r e t e s f f o) t i b - 8 ( h & s o n2 b s l -r o r r e n i a g) t i b - 8 ( h & s o n2 b s l r r e d d a l r e d d a l r o t s i s e rv f e r v = 1 c c 0 . 80 4k ? t v n o c e m i t n o i s r e v n o c t i b - 8 ) 2 , 1 ( 1 . 6 s v f e r e g a t l o v e c n e r e f e r 3 . 3v 1 c c v v a i e g a t l o v t u p n i g o l a n a 0v f e r v d l o h d n a e l p m a s : h & s : s e t o n x ( f e d i v i d . 1 n i p e e k o t , z h m 0 1 g n i d e e c x e f i , ) . s s e l r o z h m 0 1 t a y c n e u q e r f d a . e l b a l i a v a t o n h & s . 2 l o b m y sr e t e m a r a pn o i t i d n o c t n e m e r u s a e m d r a d n a t s t i n u . n i m. p y t. x a m -n o i t u l o s e r 8s t i b -y c a r u c c a e t u l o s b a 0 . 1% t u s e m i t p u t e s 3 s r o e c n a t s i s e r t u p t u o 40 10 2k ? i f e r v t n e r r u c t u p n i y l p p u s r e w o p e c n e r e f e r) 1 e t o n (0 . 1a m : e t o n g n i e b t o n , r e t r e v n o c a / d e h t f o ) 1 , 0 = i ( r e t s i g e r i a d e h t . r e t r e v n o c a / d e n o g n i s u n e h w s t l u s e r t n e m e r u s a e m . 1 0 0 " o t t e s s i , d e s u 6 1 . d e d u l c x e s i r e t r e v n o c d / a e h t n i r e d d a l r o t s i s e r e h t . " i f e r v v o n ( " 0 " o t t e s s i r e t s i g e r 1 n o c 0 d a e h t n i t i b t u c v e h t f i n e v e s w o l f f e r . ) n o i t c e n n o c
page 47 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics v cc1 =v cc2 =3.3v p u o r g 0 8 / c 2 3 m timing requirements (v cc1 =v cc2 = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.24 external clock input table 5.25 memory expansion mode and microprocessor mode l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c te m i t e l c y c t u p n i k c o l c l a n r e t x e 1 4s n w t ) h ( h t d i w ) " h " ( h g i h t u p n i k c o l c l a n r e t x e 8 1s n w t ) l ( h t d i w ) " l " ( w o l t u p n i k c o l c l a n r e t x e 8 1s n r te m i t e s i r k c o l c l a n r e t x e 5s n f te m i t l l a f k c o l c l a n r e t x e 5s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m 1 c a t ) b d - d r ( ) d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 1 c a t ) b d - d a ( ) d r a d n a t s s c , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 2 c a t ) b d - d r ( ) s u b d e x e l p i t l u m e h t h t i w e c a p s a g n i s s e c c a n e h w , d r a d n a t s d r ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n 2 c a t ) b d - d a ( ) s u b d e x e l p i t l u m e h t h t i w e c a p s a g n i s s e c c a n e h w , d r a d n a t s d a ( e m i t s s e c c a t u p n i a t a d ) 1 e t o n (s n u s t ) k l c b - b d ( e m i t p u t e s t u p n i a t a d 0 3s n u s t ) k l c b - y d r ( e m i t p u t e s t u p n i y d r 0 4s n u s t ) k l c b - d l o h ( e m i t p u t e s t u p n i d l o h 0 6s n h t ) b d - d r ( e m i t d l o h t u p n i a t a d 0s n h t ) y d r - k l c b ( e m i t d l o h t u p n i y d r 0s n h t ) d l o h - k l c b ( e m i t d l o h t u p n i d l o h 0s n d t ) a d l h - k l c b ( e m i t y a l e d t u p t u o a d l h 5 2s n : e t o n a t r e s n i . s e l c y c s u b l a n r e t x e d n a y c n c e u q e r f k l c b o t g n i d r o c c a , s n o i t a u q e g n i w o l l o f e h t m o r f d e n i a t b o e b n a c s e u l a v . 1 ( f , y c n e u q e r f n o i t a r e p o e h t r e w o l r o e t a t s t i a w k l c b . e v i t a g e n s i e u l a v d e t a l u c l a c e h t f i , ) t ac1(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (if external bus cycle is a + b , m=(bx2)+1) t ac2(ad C db) = f (bclk) x 2 C 35 10 x p 9 [ns] (if external bus cycle is a + b , p={(a+b-1)x2}+1) C 35 10 x n 9 [ns] (if external bus cycle is a + b , n=a+b) f (bclk) t ac1(ad C db) = t ac2(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (if external bus cycle is a + b , m=(bx2)-1)
page 48 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics v cc1 =v cc2 =3.3v p u o r g 0 8 / c 2 3 m timing requirements (v cc1 =v cc2 = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.26 timer a input (count source input in event counter mode) table 5.27 timer a input (gate input in timer mode) table 5.28 timer a input (external trigger input in one-shot timer mode) table 5.29 timer a input (external trigger input in pulse width modulation mode) table 5.30 timer a input (counter increment/decrement input in event counter mode) l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 1s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 4s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 4s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) a t ( i a t n i e m i t e l c y c t u p n i 0 0 2s n w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m w t ) h a t ( i a t n i h t d i w ) " h " ( h g i h t u p n i 0 0 1s n w t ) l a t ( i a t n i h t d i w ) " l " ( w o l t u p n i 0 0 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) p u ( i a t t u o e m i t e l c y c t u p n i 0 0 0 2s n w t ) h p u ( i a t t u o h t d i w ) " h " ( h g i h t u p n i 0 0 0 1s n w t ) l p u ( i a t t u o h t d i w ) " l " ( w o l t u p n i 0 0 0 1s n u s t ) n i t - p u ( i a t t u o e m i t p u t e s t u p n i 0 0 4s n h t ) p u - n i t ( i a t t u o e m i t d l o h t u p n i 0 0 4s n
page 49 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics v cc1 =v cc2 =3.3v p u o r g 0 8 / c 2 3 m timing requirements (v cc1 =v cc 2 = 3.0 to 3.6v, v ss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.31 timer b input (count source input in event counter mode) table 5.32 timer b input (pulse period measurement mode) table 5.33 timer b input (pulse width measurement mode) table 5.34 a/d trigger input table 5.35 serial i/o _______ table 5.36 external interrupt inti input l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i ) e g d e e n o n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 1s n w t ) h b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w ) " h " ( h g i h t u p n i 0 4s n w t ) l b t ( i b t n i ) e g d e e n o n o d e t n u o c ( h t d i w ) " l " ( w o l t u p n i 0 4s n c t ) b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( e m i t e l c y c t u p n i 0 0 2s n w t ) h b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w ) " h " ( h g i h t u p n i 0 8s n w t ) l b t ( i b t n i ) s e g d e h t o b n o d e t n u o c ( h t d i w ) " l " ( w o l t u p n i 0 8s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) b t ( i b t n i e m i t e l c y c t u p n i 0 0 4s n w t ) h b t ( i b t n i h t d i w ) " h " ( h g i h t u p n i 0 0 2s n w t ) l b t ( i b t n i h t d i w ) " l " ( w o l t u p n i 0 0 2s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) d a ( d a g r t ) r e g g i r t r o f d e r i u q e r ( e m i t e l c y c t u p n i 0 0 0 1s n w t ) l d a ( d a g r t h t d i w ) " l " ( w o l t u p n i 5 2 1s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m c t ) k c ( e m i t e l c y c t u p n i i k l c 0 0 2s n w t ) h k c ( h t d i w ) " h " ( h g i h t u p n i i k l c 0 0 1s n w t ) l k c ( h t d i w ) " l " ( w o l t u p n i i k l c 0 0 1s n d t ) q - c ( e m i t y a l e d t u p t u o i d x t 0 8s n h t ) q - c ( e m i t d l o h i d x t 0s n u s t ) c - d ( e m i t p u t e s t u p n i i d x r 0 3s n h t ) q - c ( e m i t d l o h t u p n i i d x r 0 9s n l o b m y sr e t e m a r a p d r a d n a t s t i n u . n i m. x a m w t ) h n i ( h t d i w ) " h " ( h g i h t u p n i i t n i 0 5 2s n w t ) l n i ( h t d i w ) " l " ( w o l t u p n i i t n i 0 5 2s n
page 50 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics v cc1 =v cc2 =3.3v p u o r g 0 8 / c 2 3 m l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u . n i m. x a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d r - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 3 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 0s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 2 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n w t ) r w ( h t d i w t u p t u o r w ) 2 e t o n (s n t d(db C wr) = f (bclk) 10 x m 9 C 20 [ns] (if external bus cycle is a + b , m=b) t h(wr C db) = f (bclk) x 2 10 9 C 20 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t w(wr) = f (bclk) x 2 10 x n 9 C 15 [ns] (if external bus cycle is a + b , n=(b x 2)-1) notes: 1. values can be obtained from the following equations, according to bclk frequency. 2. values can be obtained from the following equations, according to bclk frequency and external bus cycles. see figure 5.1 switching characteristics (v cc1 =v cc2 =3.0 to 3.6v, vss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.37 memory expansion mode and microprocessor mode (when accessing external memory space)
page 51 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics v cc1 =v cc2 =3.3v p u o r g 0 8 / c 2 3 m switching characteristics (v cc1 = v cc2 = 3.0 to 3.6v, vss = 0v at topr = 20 to 85 o c unless otherwise specified) table 5.38 memory expansion mode and microprocessor mode (when accessing an external memory space with the multiplexed bus) l o b m y sr e t e m a r a p t n e m e r u s a e m n o i t i d n o c d r a d n a t s t i n u . n i m. x a m d t ) d a - k l c b ( e m i t y a l e d t u p t u o s s e r d d a 8 1s n h t ) d a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o s s e r d d a 0s n h t ) d a - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n h t ) d a - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o s s e r d d a ) 1 e t o n (s n d t ) s c - k l c b ( e m i t y a l e d t u p t u o l a n g i s t c e l e s - p i h c 8 1s n h t ) s c - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c 0s n h t ) s c - d r ( ) d r a d n a t s d r ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n h t ) s c - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o l a n g i s t c e l e s - p i h c ) 1 e t o n (s n d t ) d r - k l c b ( e m i t y a l e d t u p t u o l a n g i s d r 8 1s n h t ) d r - k l c b ( e m i t d l o h t u p t u o l a n g i s d r 3 -s n d t ) r w - k l c b ( e m i t y a l e d t u p t u o l a n g i s r w 8 1s n h t ) r w - k l c b ( e m i t d l o h t u p t u o l a n g i s r w 0s n d t ) r w - b d ( ) d r a d n a t s r w ( e m i t y a l e d t u p t u o a t a d ) 2 e t o n (s n h t ) b d - r w ( ) d r a d n a t s r w ( e m i t d l o h t u p t u o a t a d ) 1 e t o n (s n d t ) e l a - k l c b ( ) d r a d n a t s k l c b ( e m i t y a l e d t u p t u o l a n g i s e l a 8 1s n h t ) e l a - k l c b ( ) d r a d n a t s k l c b ( e m i t d l o h t u p t u o l a n g i s e l a 2 -s n d t ) e l a - d a ( ) d r a d n a t s s s e r d d a ( e m i t y a l e d t u p t u o l a n g i s e l a ) 3 e t o n (s n h t ) d a - e l a ( ) d r a d n a t s s s e r d d a ( e m i t d l o h t u p t u o l a n g i s e l a ) 4 e t o n (s n z d t ) d a - d r ( e m i t t r a t s t a o l f t u p t u o s s e r d d a 8s n t d(db C wr) = 10 x m 9 C 25 [ns] (if external bus cycle is a + b , m=(b+2)-1) t h(rd C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(rd C cs) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C db) = f (bclk) x 2 10 9 C 20 [ns] t d(ad C ale) = f (bclk) x 2 10 x n 9 C 20 [ns] (if external bus cycle is a + b , n=a) t h(ale C ad) = f (bclk) x 2 10 x n 9 C 10 [ns] (if external bus cycle is a + b , n=a) f (bclk) x 2 notes: 1. values can be obtained by the following equations, according to blck frequency. 2. values can be obtained by the following equations, according to blck frequency and external bus cycles. 3. values can be obtained by the following equations, according to blck frequency and external bus cycles. 4. values can be obtained by the following equations, according to blck frequency and external bus cycles. see figure 5.1
page 52 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m figure 5.6 v cc1 =v cc2 =3.3v timing diagram (1) bclk rd 18ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-rd) 30ns.min (1) t ac1(rd-db) (2) csi t d(bclk-cs) 18ns.max (1) adi 18ns.max (1) t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) t ac1(ad-db) (2) wr,wrl, wrh 18ns.max 0ns.min bclk csi 18ns.max adi 18ns.max 0ns.min 0ns.min tcyc bhe dbi t d(bclk-wr) t h(bclk-rd) t h(rd-db) t h(rd-ad) t su(db-bclk) t h(rd-cs) 0ns.min t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) (3) t d(db-wr) (3) t h(wr-db) (3) t h(wr-ad) (3) [read timing] (1 + 1 bus cycles) [write timing] (1 + 1 bus cycles) memory expansion mode and microprocessor mode (when accessing an external memory space) t w(wr) (3) vcc 1 =vcc 2 =3.3v notes: 1. values guaranteed only when the microcomputer is used independently. a maximum of 35ns is guaranteed for t d(bclk-ad) +t su(db-bclk) . 2. varies with operation frequency. t ac1(rd-db) =(tcyc/2 x m-35)ns.max (if external bus cycle is a + b , m=(b x 2) + 1) t ac1(ad-db) =(tcyc x n-35)ns.max (if external bus cycle is a + b , n = a + b) t d(db-wr) =(tcyc x m-20)ns.min (if external bus cycle is a + b , m=b) t h(wr-db) =(tcyc/2-20)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min (if external bus cycle is a + b , n=(bx2)-1) note: 3. varies with operation frequency. measurement conditions ? v cc 1 =v cc 2 =3.0 to 3.6v ? input high and low voltage: v ih =1.5v, v il =0.5v ? output high and low voltage: v oh =1.5v, v ol =1.5v tcyc= 10 f (bclk) 9
page 53 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics bclk csi adi rd -3ns.min bhe adi /dbi 30ns.min t d(bclk-rd) t su(db-bclk) t dz(rd-ad) 8ns.max ale t d(bclk-ale) 18ns.max t d(ad-ale) t h(ale-ad) t h(bclk-rd) t h(rd-ad) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) t h(bclk-ale) tcyc memory expansion mode and microprocessor mode (when accessing external memory space and using the multiplexed bus) 0ns.min bclk csi adi bhe adi /dbi wr,wrl, wrh ale t h(bclk-wr) 18ns.max t ac2(ad-db) [ read timing ] (2 +2 bus cycles) address (1) (1) (1) (1) (1) t d(ad-ale) =(tcyc/2 x n-20)ns.min (if external bus cycle is a + b , n=a) t h(ale-ad) =(tcyc/2 x n-10)ns.min (if external bus cycle is a + b , n=a) t h(rd-ad) =(tcyc/2-10)ns.min, t h(rd-cs) =(tcyc/2-10)ns.min t ac2(rd-db) =(tcyc/2 x m-35)ns.max (if external bus cycle is a + b , m=(b x 2)-1) t ac2(ad-db) =(tcyc/2 x p-35)ns.max (if external bus cycle is a + b , p={(a+b-1) x 2}+1) note: 1. varies with operation frequency: (1) [ write timing ] (2 +2 bus cycles) address address t d(ad-ale) =(tcyc/2 x n - 20)ns.min (if external bus cycle is a + b , n=a) t h(ale-ad) =(tcyc/2 x n -10)ns.min (if external bus cycle is a + b , n=a) t h(wr-ad) =(tcyc/2-10)ns.min, t h(wr-cs) =(tcyc/2-10)ns.min, t h(wr-db) =(tcyc/2-20)ns.min t d(db-wr) =(tcyc/2 x m-25)ns.min (if external bus cycle is a + b , m=(b x 2)-1) note: 2. varies with operation frequency: measurement conditions: ? v cc 1 =v cc 2 =3.0 to 3.6v ? input high and low voltage: v ih =1.5v, v il =0.5v ? output high and low voltage: v oh =1.5v, v ol =1.5v vcc 1 =vcc 2 =3.3v 18ns.max t d(bclk-wr) t h(wr-ad) (2) t h(bclk-ad) 0ns.min data output t h(ale-ad) -2ns.min t d(bclk-ale) t h(bclk-ale) 18ns.max 18ns.max 0ns.min t h(wr-cs) t d(ad-ale) t d(bclk-cs) t d(bclk-ad) t h(bclk-cs) t d(db-wr) t h(wr-db) tcyc (2) (2) (2) (2) (2) 18ns.max 18ns.max 18ns.max 0ns.min 0ns.min t ac2(rd-db) -2ns.min t d(bclk-cs) t h(rd-db) t h(bclk-ad) 0ns.min data input address tcyc= 10 f (bclk) 9 figure 5.7 v cc1 =v cc2 =3.3v timing diagram (2)
page 54 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r 5. electrical characteristics p u o r g 0 8 / c 2 3 m figure 5.8 v cc1 =v cc2 =3.3v timing diagram (3) t su(d C c) tai in input tai out input in event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) t h(t in C up) t su(up C t in ) tai in input (when counting on falling edge) tai in input (when counting on rising edge) tai out input (counter increment/ decrement input) inti input ad trg input vcc 1 =vcc 2 =3.3v nmi input 2 cpu clock cycles + 300ns or more ("l" width) 2 cpu clock cycles + 300ns or more
page 55 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m 5. electrical characteristics figure 5.9 v cc1 =v cc2 =3.3v timing diagram (4) measurement conditions: ? v cc1 =v cc2 =3.0 to 3.6v ? input high and low voltage: v ih =2.4v, v il =0.6v ? output high and low voltage: v oh =1.5v, v ol =1.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 rdy input t su(rdy C bclk) t h(bclk C rdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) hi C z t h(bclk C hold) t su(hold C bclk) t d(bclk C hlda) t d(bclk C hlda) vcc 1 =vcc 2 =3.3v
page 56 6 5 f o 5 0 0 2 , 1 0 . v o n 0 1 . 1 . v e r 0 1 1 0 - 8 3 0 0 b 3 0 j e r p u o r g 0 8 / c 2 3 m package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e package dimensions 0.8 0.5 0.825 0.575 z e z d b p a 1 h e h d y 0.10 e 0.65 c 0 10 l 0.4 0.6 0.8 0 0.1 0.2 a 3.05 16.5 16.8 17.1 22.5 22.8 23.1 a 2 2.8 e 13.8 14.0 14.2 d 19.8 20.0 20.2 reference symbol dimension in millimeters min nom max 0.25 0.3 0.4 0.13 0.15 0.2 p-qfp100-14x20-0.65 1.6g mass[typ.] 100p6s-a prqp0100jb-a renesas code jeita package code previous code y index mark 100 81 80 51 50 31 30 1 f * 2 * 1 * 3 z e z d e b p a h d d e h e c detail f a 1 a 2 l include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2.
revision history rev. date description page summary m32c/80 group datasheet a-1 0.10 sep., 02 new document C 0.11 sep., 02 table 1.1.1 can deleted 3 0.12 nov., 02 table 1.1.1 4.2 to 5.5v --> 3.0 to 5.5v "3.0 to 3.6v (f(xin)=20mhz without software wait)" deleted "26ma (f(xin)=20mhz without software wait,vcc=3.3v)" deleted 3 1. overview changed 1.2 performance outline changed 1.3 block diagram added 1.5 pin assignments changed table 1.3 pin characteristics for 100-pin package changed 1.6 pin description added 2. central processing unit (cpu) added 3. memory added 4. special function registers (sfr) added 0.30 aug., 02 C all pages words standardized: on-chip oscillator, a/d converter and d/a converter overview 2, 3 ? table 1.1 and 1.2 m32c/80 group performance "when using 16-bit bus" added to i/o ports "option" deleted from serial i/o, i 2 c bus, and iebus "voltage detection circuit" added value added to "power consumption" "flash memory" added 4 ? 1.3 block diagram description deleted 5 ? figure 1.2 rom/ram capacity deleted ? table 1.3 m32c/85 group note1 deleted 11 ? table 1.5 pin description note 1 added to i/o ports memory 23 ? chapter description modified ? figure 3.1 memory map modified sfr 16- ? "x: nothing is assigned" modified to "x: indeterminate" ? "?: indeterminate modified to "x: indeterminate" ? "users cannot use any symbols with *" deleted ? register names, symbols, value after reset of addresses 0017 16 , 001b 16 , 001f 16 , 002b 16 , 002f 16 , 004c 16 , and 004d 16 deleted ? value after reset in the pm0 register revised 16 ? note 3 deleted 29 ? note 1 added to addresses 03e0 16 to 03eb 16 0.40 jun., 04 1.00 nov., 04
revision history rev. date description page summary m32c/80 group datasheet a-2 electrical characteristics 30- ? this capter added all pages package code chnaged: 100p6q-a to plqp0100kb-a and 100p6s-a to prqp0100jb-a overview 1 ? note that the m32c/80 group is romless device added 2 ? table 1.1 m32c/80 group performance item "hdlc data processing" changed to "intelligent i/o communication function"; item "flash memory" deleted 3 ? figure 1.1 m32c/80 group block diagram notes 1 and 2 added 9 ? table 1.4 pin description supply voltage for analog power supply input modi- ______ fied "-" to "v cc1 "; description for cnv ss changed; supply voltage for int inter- rupt input modified; note for i/o ports added memory 15 ? figure 3.1 memory map disgram changed; note added special function registers (sfrs) 16 ? note 2 deleted 17 ? values after reset in the rmad6 and rmad7 registers modified 19 ? value after reset in the rlvl register modified 20 ? value after reset in the g0rb register modified 21 ? values after reset in the g0emr, g0erc, and g0irf registers modified 26 ? value after reset in the tcspr register modified; note 1 added 27, 28 ? register names, symbols, and value after reset of addresses 0392 16 and 03ac 16 deleted 28 ? value after reset in the psc register modified electrical characteristics 30- ? ports p11 to p15 deleted 32 ? table 5.2 recpmmended operating conditions f (bclk) standard added 33 ? table 5.3 electrical characteristics max. standard for i cc modified 34 ? table 5.4 a/d conversion characteristics an0 0 to an0 7 deleted from " inl " row 35 ? table 5.7 memory expansion mode and microprocessor mode expressions on note 1 corrected 41 ? figure 5.2 v cc1 =v cc2 =5v timing diagram (1) expression for tcyc added; note 3 corrected 42 ? figure 5.3 v cc1 =v cc2 =5v timing diagram (2) expression for tcyc added; notes 1 and 2 corrected 46 ? table 5.22 a/d conversion characteristics min. standard for v ref modified 47 ? table 5.25 memory expansion mode and microprocessor mode expres- sions on note 1 corrected 52 ? figure 5.6 v cc1 =v cc2 =3.3v timing diagram (1) expression for tcyc added; note 3 corrected 1.10 nov., 05
revision history rev. date description page summary m32c/80 group datasheet a-3 53 ? figure 5.7 v cc1 =v cc2 =3.3v timing diagram (2) expression for tcyc added; notes 1 and 2 corrected
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> 2-796-3115, fax: <82> 2-796-2145 renesas technology malaysia sdn. bhd. unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 200 5. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .3.0

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