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F81485 jan, 2012 v0.11p F81485 5v low power rs-485 interface transceiver release date: jan, 2012 version: v0.11p
F81485 jan, 2012 v0.11p F81485 datasheet revision history version date page revision history v0.10p 2011/12 - preliminary v0.12p 2012/01 - made clarification and correction update top marking specification update differential input threshold spec. please note that all data and specificat ions are subject to change without not ice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for us e in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. cust omers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify fintek for any damages resulting from such improper use or sales.
F81485 jan, 2012 v0.11p table of content 1 general de scripti on ........................................................................................................... ...................................... 4 2 feature list ............................................................................................................................... ............................... 4 3 pin confi gurati on ............................................................................................................. ........................................ 5 4 pin descr iption ............................................................................................................... ......................................... 5 5 electrical charac teristics request ............................................................................................ .............................. 7 6 ordering info rmati on .......................................................................................................... ................................... 10 7 top marking s pecificat ion ..................................................................................................... ................................ 10 8 package s pec. ................................................................................................................. ..................................... 11 9 application circui t ........................................................................................................... ....................................... 12
F81485 jan, 2012 v0.11p 4 1 general description the F81485 is a cmos design, features with sing le 5 v power supply, and low power differential bus/line transceiver suitable for the multipoi nt data transmission eia standard rs485 and rs422 applications. the extended common-mode range is ? 7 v to +12 v. both the driver and the receiver can be enabled independently. the driver and receiver feature three-state out puts, with the driver outputs maintaining high impedance over the entire common-mode range. excessive power dissipation caused by the bus contention or faults is prevented by a thermal shutdown circuit which forces the driver outputs into a high impedance state. the receiver contains a fail-safe feature that results in a logic high output state if the inputs ar e unconnected (floating). up to 32 transceivers can be connected simultaneously on a bus, but only one driver should be enabled at any time. the F81485 features extremely fast switching speeds. minimal driver propagation delays permit transmission at data rates up to 5 mbps while low skew minimizes emi interference. all inputs and outputs contain protection against esd; all driver outputs feature high source and sink current capability. an epitaxial layer is used to guard against latch-up. 2 feature list z single 5v supply z meets eia rs-485 standard z high speed, low power bicmos z -7v to 12v bus common-mode range permits z 7v ground difference between devices on the bus z esd 8kv contact z thermal shutdown protection z driver maintains high impedance in three-state or with the power off z 70mv typical input hysteresis z driver propagation delay: 10 ns typical z receiver propagation delay: 15 ns typical z high-z outputs with power off z pin compatible with the adm485, sp485 z 8 pin sop packaging
F81485 jan, 2012 v0.11p 5 3 pin configuration ro di de 1 2 3 4 8 7 6 5 b re a gnd vcc F81485 r d 4 pin description in t o 4 - ttl level input pin. - output pin with 4ma driver. p - power. 4.1. power pin pin pin name type description 5 gnd p gnd. 8 vcc p 4.75v< vcc < 5.25v power supply voltage input. 4.2. transceiver pin pin name type description 1 ro o 4 receiver output. when enable d (re# is low), then if a > b by 200 mv, ro is high. a < b by 200 mv, ro is low. 2 re# in t active low receiver output enable pin. a low level enables the receiver output, ro. a high level places it in a high impedance state. 3 de in t active high driver output enable. a high level enables the driver differential outputs, a and b. the chip will function as a line driver. a low level places it in a high impedance state. the chip will function as a line receiver.
F81485 jan, 2012 v0.11p 6 4 di in t driver input. when the driver is enabled (de is high), a logic low on di forces a low and b high, while a logic high on di forces a high and b low. 6 a i/o non-inverting receiver input a/driver output a. 7 b i/o inverting receiver input b/driver output b. transmitting inputs line outputs re# de di conditio n b a x 1 1 no fault 0 1 x 1 0 no fault 1 0 x 0 x x z z x 1 x fault z z receiving inputs ouptuts re# de a-b r 0 0 0.2v 1 0 0 0.2v 0 0 0 inputs open 1 1 0 x z
F81485 jan, 2012 v0.11p 7 5 electrical characteristics request 5.1 absolute maximum ratings parameter rating unit vcc 12 v input voltage logic -0.3 to vcc +0.5 v drivers -0.3 to vcc +0.5 v receivers 15 output voltage logic -0.3 to vcc +0.5 v drivers 15 v receivers -0.3 to vcc +0.5 storage tempreature -65 to +150 c lead temperature (soldering, 10s) +300 c power disspation 500 mw note: exposure to conditions beyond those listed under absol ute maximum ratings may adversely affect the life and reliability of the device test condition: vcc = 5v 5.2 driver section test condition: vcc = 5v parameter symbol min. typ. max unit conditions supply voltage 4.75 5.25 v supply current 900 a no load operating temperature 0 70 c parameter symbol min. typ. max unit conditions dc characteristics differential output voltage gnd vcc v unloaded, r= 2 vcc v with load, r = 50 ? (rs422) 1.5 vcc v with load, r = 27 ? (rs485) differential output voltage for complimentary states 0.2 v r = 27 ? or r = 50 ? output voltage 3 v r = 27 ? or r = 50 ? input high voltage 2.0 v applies to de, di, re# input low voltage 0.8 v applies to de, di, re# input current 10 a applies to de, di, re# driver short current 35 250 ma vout = high, -7v vo +12v 35 250 ma vout = low, -7v vo +12v
F81485 jan, 2012 v0.11p 8 5.3 receiver section test condition: vcc = 5v parameter symbol min. typ. max unit conditions ac characteristics maximum data rate 5 mbps re# = 5v, de = 5v driver input to output 20 30 60 ns t plh ; r diff = 54 ? , c l1 = c l2 = 100pf 20 30 60 ns t phl ; r diff = 54 ? , c l1 = c l2 = 100pf driver skew 5 10 ns t skew = ? t dplh - t dphl ? driver rise or fall time 3 15 40 ns 10% to 90%, r diff = 54 ? , c l1 = c l2 = 100pf driver enable to output high 40 70 ns c l1 = 100pf driver enable to output low 40 70 ns c l1 = 100pf driver disable time from low 40 70 ns c l1 = 15pf driver disable time from high 40 70 ns c l1 = 15pf parameter symbol min. typ. max unit conditions dc characteristics differential input threshold -300 +0 mv -7v v cm +12v input hysteresis 10 mv v cm = 0v output voltage high 3.5 v i o = -4ma, v id = +200mv output voltage low 0.4 v i o = +4ma, v id = - 200mv output current 1 a 0.4v vo 2.4v, re# = -5v input resistance 12 15 k -7v v cm +12v input current (a,b), v in = 12v +1.0 ma de = 0v, v cc = 0v or 5.25v, v in = 12v input current (a,b), v in = - 7v -0.8 ma de = 0v, v cc = 0v or 5.25v, v in = -7v short circuit current 7 95 ? ma 0v v cm v cc
F81485 jan, 2012 v0.11p 9 parameter symbol min. typ. max unit conditions ac characteristics maximum data rate 5 mbps re# = 0v, de = 0v receiver input to output 60 90 200 ns t plh ; r diff = 54 ? , c l1 = c l2 = 100pf 60 90 200 ns t phl ; r diff = 54 ? , c l1 = c l2 = 100pf receiver skew 13 ns t skew = ? t dplh - t dphl ? receiver enable to output low 20 50 ns c rl = 15pf receiver enable to output high 20 50 ns c rl = 15pf receiver disable time from low 20 50 ns c rl = 15pf receiver disable time from high 20 50 ns c rl = 15pf
F81485 jan, 2012 v0.11p 10 6 ordering information 7 top marking specification the version identification is shown as the bold red characters. please refer to below for detail: part number package type production flow F81485s 8-sop green package commercial, 0 c to +70 c 2 n d line: assembly plant code (x) + assembled year code (x) + week code (xx) + fintek internal code (xx) + ic version (x) where a means version a, b means version b, ? : pin 1 identifier 1 s t line: fintek logo 2 n d line: device name ? F81485s, where s means 8-sop package 3 r d line: wafer fab code (xxxx?xx) F81485s xxxxxx.x xxxxxxx
F81485 jan, 2012 v0.11p 11 8 package spec. 8-sop package
F81485 jan, 2012 v0.11p 12 9 application circuit rs-485 interface host tx/rx tx_data rx_data recei ve_en drive_en F81485 tit le size document number rev date: sheet of F81485 a b 11 friday , nov ember 18, 2011 c 1.0uf 5v re de ro di b vcc a gnd 1 2 3 4 5 6 7 8 d r mode selecti on 0 0 rs485 recieve /re de m ode 1 0 dis_rs485 0 1 rs485 loopback 1 1 rs485 drive

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