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?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b huf76121d3, huf76121d3s 20a, 30v, 0.023 ohm, n-channel, logic level ultrafet power mosfets these n-channel power mosfets are manufactured using the innovative ultrafet process. this advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. it was designed for use in applications where power ef?iency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low- voltage bus switches, and power management in portable and battery-operated products. formerly developmental type ta76121. features logic level gate drive 20a, 30v ultra low on-resistance, r ds(on) = 0.023 ? temperature compensating pspice model temperature compensating saber model thermal impedance spice model thermal impedance saber model peak current vs pulse width curve uis rating curve related literature - tb334, ?uidelines for soldering surface mount components to pc boards symbol packaging jedec to-251aa jedec to-252aa ordering information part number package brand huf76121d3 to-251aa 76121d huf76121d3s to-252aa 76121d note: when ordering, use the entire part number. add the suf? t to obtain the to-252aa variant in tape and reel, e.g., HUF76121D3ST. d g s drain (flange) drain source gate drain (flange) gate source data sheet december 2001
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b absolute maximum ratings t c = 25 o c, unless otherwise speci?d units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16 v drain current continuous (t c = 25 o c, v gs = 10v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 4.5v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 20 20 20 figure 4 a a a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as figures 6, 17, 18 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 0.6 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t a = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 12) 30 - - v zero gate voltage drain current i dss v ds = 25v, v gs = 0v - - 1 a v ds = 25v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 16v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 11) 1 - 3 v drain to source on resistance r ds(on) i d = 20a, v gs = 10v (figure 9, 10) - 0.017 0.023 ? i d = 20a, v gs = 5v (figure 9) - 0.021 0.030 ? i d = 20a, v gs = 4.5v (figure 9) - 0.023 0.033 ? thermal specifications thermal resistance junction to case r jc (figure 3) - - 1.66 o c/w thermal resistance junction to ambient r ja to-251aa, to-252aa - - 100 o c/w switching specifications (v gs = 4.5v) turn-on time t on v dd = 15v, i d ? 20a, r l = 0.75 ? , v gs = 4.5v, r gs = 11.0 ? (figures 15, 21, 22) - - 275 ns turn-on delay time t d(on) -18-ns rise time t r - 165 - ns turn-off delay time t d(off) -18-ns fall time t f -40-ns turn-off time t off - - 87 ns huf76121d3, huf76121d3s
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b switching specifications (v gs = 10v) turn-on time t on v dd = 15v, i d ? 20a, r l = 0.75 ? , v gs = 10v, r gs = 12.0 ? (figures 16, 21, 22) - - 85 ns turn-on delay time t d(on) -6-ns rise time t r -50-ns turn-off delay time t d(off) -45-ns fall time t f -45-ns turn-off time t off - - 135 ns gate charge specifications total gate charge q g(tot) v gs = 0v to 10v v dd = 15v, i d ? 20a, r l = 0.75 ? i g(ref) = 1.0ma (figures 14, 19, 20) -2430nc gate charge at 5v q g(5) v gs = 0v to 5v - 13 16 nc threshold gate charge q g(th) v gs = 0v to 1v - 1.0 1.2 nc gate to source gate charge q gs - 2.40 - nc gate to drain ?iller?charge q gd - 7.40 - nc capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 13) - 850 - pf output capacitance c oss - 465 - pf reverse transfer capacitance c rss - 100 - pf electrical speci?ations t a = 25 o c, unless otherwise speci?d (continued) parameter symbol test conditions min typ max units source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 20a - - 1.25 v reverse recovery time t rr i sd = 20a, di sd /dt = 100a/ s--58ns reverse recovered charge q rr i sd = 20a, di sd /dt = 100a/ s--70nc typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 175 0 5 10 15 20 25 25 50 75 100 125 150 175 i d , drain current (a) t c , case temperature ( o c) v gs = 10v v gs = 4.5v huf76121d3, huf76121d3s
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b figure 3. normalized maximum transient thermal impedance figure 4. peak current capability figure 5. forward bias safe operating area note: refer to fairchild application notes an9321 and an9322. figure 6. unclamped inductive switching capability typical performance curves (continued) 0.01 0.1 1 2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 z jc , normalized thermal impedance single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 t, rectangular pulse duration (s) 10 100 1000 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 10v i dm , peak current (a) t, pulse width (s) v gs = 5v transconductance may limit current in this region 1 10 100 1 10 100 500 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c 100 s 10ms 1ms limited by r ds(on) area may be operation in this bv dss max = 30v 1 10 100 0.001 0.01 0.1 1 10 100 300 i as , avalanche current (a) t av , time in avalanche (ms) t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] starting t j = 25 o c starting t j = 150 o c huf76121d3, huf76121d3s
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b figure 7. transfer characteristics figure 8. saturation characteristics figure 9. source to drain on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature typical performance curves (continued) 175 o c 0 15 30 45 60 75 01 345 2 i d , drain current (a) v gs , gate to source voltage (v) -55 o c 25 o c v dd = 15v pulse duration = 80 s duty cycle = 0.5% max 0 15 30 45 60 75 012345 i d , drain current (a) v ds , drain to source voltage (v) v gs = 4v v gs = 3v v gs = 3.5v v gs = 4.5v v gs = 10v v gs = 5v pulse duration = 80 s duty cycle = 0.5% max 15 20 25 30 35 246810 v gs , gate to source voltage (v) r ds(on) , on-state resistance (m ? ) i d = 20a i d = 1a i d = 10a pulse duration = 80 s duty cycle = 0.5% max 0.8 1.0 1.2 1.4 1.6 -80 -40 0 40 80 120 160 0.6 normalized drain to source t j , junction temperature ( o c) on resistance pulse duration = 250 s, v gs = 10v, i d = 20a 0.8 1.0 1.2 -80 -40 0 40 80 120 160 0.6 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 a 1.0 1.1 1.2 -80 -40 0 40 80 0.12k 0.16k 1.0 t j , junction temperature ( o c) i d = 250 a normalized drain to source breakown voltage huf76121d3, huf76121d3s
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b figure 13. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an7260. figure 14. gate charge waveforms for constant gate current figure 15. switching time vs gate resistance figure 16. switching time vs gate resistance test circuits and waveforms figure 17. unclamped energy test circuit figure 18. unclamped energy waveforms typical performance curves (continued) 0 300 600 900 1200 0 5 10 15 20 25 30 c, capacitance (pf) v ds , drain to source voltage (v) c iss c oss c rss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 0 2 4 6 8 10 0 5 10 15 20 25 v gs , gate to source voltage (v) v dd = 15v q g , gate charge (nc) i d = 20a i d = 10a i d = 1a waveforms in descending order: 0 100 200 300 400 0 1020304050 r gs , gate to source resistance ( ? ) v gs = 4.5v, v dd = 15v, i d = 20a, r l = 0.75 ? t r t f t d(on) switching time (ns) t d(off) 0 50 100 150 200 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) vgs = 10v, v dd = 15v, i d = 20a, r l = 0.75 ? t r t d(off) t f t d(on) t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 huf76121d3, huf76121d3s
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b figure 19. gate charge test circuit figure 20. gate charge waveforms figure 21. switching time test circuit figure 22. switching time waveform test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(tot) v gs = 10v v ds v gs i gref) 0 0 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 huf76121d3, huf76121d3s
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b pspice electrical model .subckt huf76121d 2 1 3 ; rev may 1998 ca 12 8 1.3e-9 cb 15 14 1.25e-9 cin 6 8 7.5e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 33.4 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 2.4e-9 lsource 3 7 3.14e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 2.6e-3 rgate 9 20 4 rldrain 2 5 10 rlgate 1 9 24 rlsource 3 7 31.4 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 12.5e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*155),4))} .model dbodymod d (is = 3.5e-13 rs = 8.7e-3 trs1 = 2.2e-3 trs2 = 2e-6 cjo = 1.34e-9 tt = 2.8e-8 m = 0.4 xti = 4.3 n = 0.95 ikf = 3.7 ) .model dbreakmod d (rs = 1.3e-1 trs1 = 2e-3 trs2 = -2e-5) .model dplcapmod d (cjo = 7.7e-10 is = 1e-30 n = 10 m = 0.63) .model mmedmod nmos (vto = 1.9 kp = 3.5 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 4) .model mstromod nmos (vto = 2.23 kp = 55 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.64 kp = 0.1 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 40 rs = 0.1) .model rbreakmod res (tc1 = 9.7e-4 tc2 = 0) .model rdrainmod res (tc1 = 2e-2 tc2 = 2.4e-5) .model rslcmod res (tc1 = 5e-3 tc2 = 8e-6) .model rsourcemod res (tc1 = 0 tc2 = 0) .model rvthresmod res (tc = -1.9e-3 tc2 = -5.5e-6) .model rvtempmod res (tc1 = -1.2e-3 tc2 = 1e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -5.5 voff= -3) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -3 voff= -5.5) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -1 voff= 1.8) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 1.8 voff= -1) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf76121d3, huf76121d3s
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b saber electrical model rev may 1998 template huf76121d n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 3.5e-13, xti = 4.3, cjo = 1.34e-9, tt = 2.8e-8, n = 0.95, m = 0.4) d..model dbreakmod = () d..model dplcapmod = (cjo = 7.7e-10, is = 1e-30, n = 10, m = 0.63) m..model mmedmod = (type=_n, vto = 1.9, kp = 3.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.23, kp = 55, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.64, kp = 0.1, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -3) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -5.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1, voff = 1.8) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 1.8, voff = -1) c.ca n12 n8 = 1.3e-9 c.cb n15 n14 = 1.25e-9 c.cin n6 n8 = 7.5e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 2.4e-9 l.lsource n3 n7 = 3.14e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 0 res.rdbody n71 n5 = 8.7e-3, tc1 = 2.2e-3, tc2 = 2e-6 res.rdbreak n72 n5 = 1.3e-1, tc1 = 2e-3, tc2 = -2e-5 res.rdrain n50 n16 = 2.6e-3, tc1 = 2e-2, tc2 = 2.4e-5 res.rgate n9 n20 = 4 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 24 res.rlsource n3 n7 = 31.4 res.rslc1 n5 n51 = 1e-6, tc1 = 5e-3, tc2 = 8e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 12.5e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.2e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -5.5e-6 spe.ebreak n11 n7 n17 n18 = 33.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/155))** 4)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 huf76121d3, huf76121d3s
?001 fairchild semiconductor corporation huf76121d3, huf76121d3s rev. b spice thermal model rev may 1998 huf76121d ctherm1 th 6 1.1e-3 ctherm2 6 5 2.5e-3 ctherm3 5 4 3.2e-3 ctherm4 4 3 8.5e-3 ctherm5 3 2 4.0e-2 ctherm6 2 tl 2.2 rtherm1 th 6 1.8e-3 rtherm2 6 5 1.5e-2 rtherm3 5 4 2.4e-1 rtherm4 4 3 4.5e-1 rtherm5 3 2 3.4e-1 rtherm6 2 tl 7.0e-2 saber thermal model saber thermal model huf76121d template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.1e-3 ctherm.ctherm2 6 5 = 2.5e-3 ctherm.ctherm3 5 4 = 3.2e-3 ctherm.ctherm4 4 3 = 8.5e-3 ctherm.ctherm5 3 2 = 4.0e-2 ctherm.ctherm6 2 tl = 2.2 rtherm.rtherm1 th 6 = 1.8e-3 rtherm.rtherm2 6 5 = 1.5e-2 rtherm.rtherm3 5 4 = 2.4e-1 rtherm.rtherm4 4 3 = 4.5e-1 rtherm.rtherm5 3 2 = 3.4e-1 rtherm.rtherm6 2 tl = 7.0e-2 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case huf76121d3, huf76121d3s
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?

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