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low cost, low power, true rms-to-dc converter ad8436 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features computes true rms value instantly accuracy: 10 v 0.5% of reading wide dynamic input range 100 v rms to 3 v rms (8.5 v p-p) full-scale input range larger inputs with external scaling wide bandwidth: 1 mhz for ?3 db (300 mv) 65 khz for additional 1% error zero converter dc output offset no residual switching products specified at 300 mv rms input accurate conversion with crest factors up to 10 low power: 300 a typical at 2.4 v fast settling at all input levels high-z fet separately powered input buffer r in 10 12 , c in 2 pf precision dc output buffer wide supply range dual: 2.4 v to 18 v single: 4.8 v to 36 v small size: 4 mm 4 mm package esd protected functional block diagram vee cav g vcc ignd out ibufgn rms ibufout ibufin+ sum 8k ? 100k ? 16k ? 100k ? ognd 10k? 10k ? fet op amp 10pf ibufin? obufout obufin+ obufin? 16k ? dc buffer ad8436 ? + rms core ? + ccf 10033-001 figure 1. general description the ad8436 is a new generation, translinear precision, low power, true rms-to-dc converter that is loaded with options. it computes a precise dc equivalent of the rms value of ac waveforms, including complex patterns such as those generated by switchmode power supplies and triacs. its accuracy spans a wide range of input levels (see figure 2 ) and temperatures. the ensured accuracy of 0.5% and 10 v output offset result from the latest analog devices, inc., technology. the crest factor error is <0.5% for cf values between 1 and 10. the ad8436 delivers instant true rms results at less cost than misleading peak, averaging, or digital solutions. there is no programming expense or processor overhead to consider, and the 4 mm 4 mm package easily fits into those tight applications. on-board buffer amplifiers enable the widest range of options for any rms-to-dc converter available, regardless of cost. for minimal applications, only a single external averaging capacitor is required. the built-in high impedance fet buffer provides an interface for external attenuators, frequency compensation, or driving low impedance loads. a matched pair of internal resistors enables an easily configurable gain-of-two or more, extending the usable input range even lower. the low power, precision input buffer makes the ad8436 attractive for use in portable multi- meters and other battery-powered applications. the precision dc output buffer offers extremely low offset voltages, thanks to bias current cancellation. unlike digital solutions, the ad8436 has no switching circuitry limiting performance at high or low amplitudes (see figure 2 ). a usable response of <100 v and >3 v extends the dynamic range with no external scaling, accommodating the most demanding low signal conditions. 1mv 10mv 1v 100mv ad8436 greater input dynamic range 100v 3v ? solution 10033-002 figure 2. usable dynamic range of the ad8436 vs. ? the ad8436 operates from single or dual supplies of 2.4 v (4.8 v) to 18 v (36 v). a and j grades are available in a compact 4 mm 4 mm, 20-lead chip-scale package. the operating temperature ranges are ?40c to 125c and 0c to 70c.
ad8436 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 4 ? thermal resistance ...................................................................... 4 ? esd caution.................................................................................. 4 ? pin configuration and function descriptions............................. 5 ? typical performance characteristics ............................................. 6 ? test circuits........................................................................................9 ? theory of operation ...................................................................... 10 ? overview ..................................................................................... 10 ? applications information .............................................................. 12 ? using the ad8436....................................................................... 12 ? ad8436 evaluation board.. ....................................................... 16 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 18 ? revision history 7/11revision 0: initial version
ad8436 rev. 0 | page 3 of 20 specifications e in = 300 mv ac (rms), frequency = 1 khz sinusoidal, ac-coupled, v s = 5 v, t a = 25c, c avg = 10 f, unless otherwise specified. table 1. parameter test conditions/comments min typ max unit rms core conversion error default conditions 10 ? 0.5 0 0 10 + 0.5 v/% rdg vs. temperature ?40c < t < 125 c 0.006 %/c vs. rail voltage 2.4 v to 18 v 0.013 %/v input offset voltage dc-coupled ?500 0 +500 v output offset voltage default cond itions, ac-coupled input 0 v vs. temperature ?40 c < t < 125c 0.3 v/c dc reversal error dc-coupled, v in = 300 mv 0.5 2 % nonlinearity e in = 10 mv to 300 mv ac (rms) 0.05 % crest factor error additional error 1 < cf < 10 ccf = 0.1 f ?0.5 +0.5 % peak input voltage ?v s ? 0.7 +v s + 0.7 v input resistance 7.92 8 8.08 k frequency response v in = 300 mv rms 1% additional error 65 khz 3 db bandwidth 1 mhz settling time 0.1% rising/falling 148/341 ms 0.01% rising/falling 158/350 ms output resistance 15.68 16 16.32 k supply current no input 325 400 a input buffer signal voltage swing g = 1 input ac- or dc-coupled ?v s +v s v output ac-coupled to pin rms ?v s + 0.2 +v s ? 0.2 mv offset voltage ?1 0 +1 mv input bias current 50 pa input resistance 10 12 frequency response 0.1 db 950 khz 3 db bandwidth 2.1 mhz supply current 100 160 200 a optional gain resistor ?9.9 +10 +10.1 k gain error g = 1 0.05 % output buffer offset voltage connected to pin out ?200 0 +200 v input current 3 na output voltage swing ?v s + 0.0005 +v s ? 1 v gain error 0.003 0.01 % supply current 40 70 a supply voltage dual 2.4 18 v single 4.8 36 v
ad8436 rev. 0 | page 4 of 20 absolute maximum ratings table 2. parameter rating supply voltage 18 v internal power dissipation 18 mw input voltage v s output short-circuit duration indefinite differential input voltage +v s and ?v s temperature operating range ?40c to +125c storage range ?65c to +125c lead soldering (60 sec) 300c esd rating 2 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit cp-20-10 lfcsp without thermal pad 86 c/w cp-20-10 lfcsp with thermal pad 48 c/w esd caution
ad8436 rev. 0 | page 5 of 20 pin configuration and fu nction descriptions 16 20 15 10 6 ad8436 top view (not to scale) 11 pin 1 indicator vee cavg v c c obufout ignd obufin+ obufin? obufv+ out dnc notes 1. dnc = do not connect. do not connect to this pin. 2 . the exposed pad should not be connected. ibufgn dnc ibufout ibufin+ su m ibuf v + rms ccf ognd ibufin? 1 5 10033-003 figure 3. pin configuration, top view table 4. pin function descriptions pin no. mnemonic description 1 dnc do not connect. used for factory test. 2 rms ac input to the rms core. 3 ibufout output connection for the fet input buffer amplifier. 4 ibufinC inverting input to the fet input buffer amplifier. 5 ibufin+ noninverting input to the fet input buffer amplifier. 6 ibufgn optional 10 k precision gain resistor. 7 dnc do not connect. used for factory test. 8 ognd internal 16 k current-to-voltage resistor. connect to ground for voltage output at pin 9; leave unconnected for current output at pin 9. 9 out voltage or current output of the rms core. 10 vee negative supply rail. 11 ignd half supply node. leave open for single-supply operation. 12 obufin+ noninverting input of the optional precision output buffer. obufin+ is typically connected to out. 13 obufin? inverting input of the optional precision outp ut buffer. obufin? is typically connected to obufout. 14 obufout low impedance output for adc or other loads. 15 obufv+ power pin for the output buffer. 16 ibufv+ power pin for the input buffer. 17 vcc positive supply rail for the rms core. 18 ccf connection for crest factor capacitor. 19 cavg connection for averaging capacitor. 20 sum summing amplifier input node. an external re sistor can be connected for custom scaling. ep dnc exposed pad. the exposed pad should not be connected.
ad8436 rev. 0 | page 6 of 20 typical performance characteristics t a = 25c, v s = 5 v, c avg = 10 f, 1 khz sine wave, unless otherwise indicated. input level (v rms) 1v 100 1k frequency (hz) 100k 10k 10mv 5v 100v 100mv 1mv 5m 1m 50 50v ? 3db bw 10033-004 figure 4. rms core frequency response (see figure 20 ) ? 3db bw v s = 2.4v 10033-005 1v 100 1k frequency (hz) 100k 10k 10mv 5v 100v 100mv 1mv 5m 1m 50 50v input level (v rms) figure 5. rms core frequency response with v s = 2.4 v (see figure 20 ) ? 3db bw v s = 15v 10033-006 input level (v rms) 1v 100 1k frequency (hz) 100k 10k 10mv 5v 100v 100mv 1mv 5m 1m 50 50v figure 6. rms core frequency response with v s = 15 v (see figure 20 ) ? 3db bw v s = 4.8v 10033-007 input level (v rms) 1v 100 1k frequency (hz) 100k 10k 10mv 5 v 100v 100mv 1mv 5m 1m 50 50v figure 7. rms core frequency response with v s = +4.8 v (see figure 21 ) gain (db) 12 100 1k frequency (hz) 100k 10k 0 15 3 9 6 5m 1m ?15 ?12 ?3 ?9 ?6 e in = 3.5mv rms 10033-008 figure 8. input buffer, small signal bandwidth at 0 db and 6 db gain gain (db) 12 100 1k frequency (hz) 100k 10k 0 15 3 9 6 5m 1m ?15 ?12 ?3 ?9 ?6 e in = 300mv rms 10033-009 figure 9. input buffer, large signal bandwidth at 0 db and 6 db gain
ad8436 rev. 0 | page 7 of 20 gain (db) 12 100 1k frequency (hz) 100k 10k 0 15 3 9 6 5m 1m ?15 ?12 ?3 ?9 ?6 e in = 3.5mv rms 10033-010 figure 10. output buffer, small signal bandwidth 20 supply voltage (v) 8 4 26 14 1210 0.3 0.5 0.4 0 ?0.1 cavg = 10f 8 samples normalized error (%) 0 ?0.3 ?0.4 ?0.2 0.2 0.1 ?0.5 1816 10033-011 figure 11. additional error vs. supply voltage input level (v rms) 46 supply voltage (v) 10 8 0.8 2.0 1.2 0.4 1412 2 0 16 18 0 1.6 10033-012 figure 12. core input voltage for 1% error vs. supply voltage additional error (% of reading) crest factor ratio 2 0 5 6 4 0 810 10 ? 5 ? 10 cavg = 10f cavg = 10f ccf = 0.1f p w = 100s 10033-013 figure 13. crest factor error vs. cres t factor for cavg and cavg and ccf capacitor combinations additional error (% of reading) temperature (c) 25 0 0.50 0.25 0.75 75 50 0 100 125 1.00 ?25 ?50 ? 0.50 ? 0.25 ? 0.75 ? 1.00 10033-014 figure 14. additional conversion error vs. temperature supply current (ma) 2.5 0.5 1.0 input voltage (v rms) 2.0 1.5 1.5 0.5 2.0 1.0 0 0 v s = 2.4v v s = 15v v s = 5v 10033-015 figure 15. rms core suppl y current vs. input for v s = 2.4 v, 5 v, and 15 v
ad8436 rev. 0 | page 8 of 20 bias current (pa) temperature (c) 25 0 70 60 80 75 50 0 100 125 90 ? 25 ? 50 40 50 30 20 10 ? 10 10033-016 figure 16. fet input buffer bias current vs. temperature input offset voltage (v) temperature (c) 25 0 500 250 750 75 50 0 100 125 1000 ? 500 ? 250 ? 750 ? 1000 ? 25 ? 50 10033-018 figure 17. input offset voltage of fet buffer vs. temperature input offset voltage (v) temperature (c) 25 0 100 250 150 50 75 50 0 100 125 200 ? 100 ? 250 ? 150 ? 50 ? 200 ? 25 ? 50 10033-019 figure 18. output buffer v os vs. temperature 1khz 300mv rms burst input time (50ms/div) 1khz 1mv rms burst input 300mv dc out 1mv dc out cavg = 10f 0v 0v 0v 0v 10033-020 figure 19. transition times with 1 khz burst at two input levels (see theory of operation section)
ad8436 rev. 0 | page 9 of 20 test circuits precision dmm signal source out rms +5v 10f ac-in monitor precision dmm 4.7f vee cav vcc 100k? 100k? 16k ? ognd ?5v ignd rms core 10033-021 figure 20. core response test circuit using dual supplies precision dmm signal source out rms 4.80v 10f ac-in monitor precision dmm 4.7f 4.7f vee cav vcc 100k ? 100k ? 16k? ognd ignd rms core 10033-022 figure 21. core response test circuit using a single supply function generator precision dmm out rms +5 v 10 f ac-in monitor precision dmm 4.7f vee cav vcc 100k ? 100k ? 16k ? ognd ?5v ignd rms core 10033-023 figure 22. crest factor test circuit
ad8436 rev. 0 | page 10 of 20 theory of operation overview the ad8436 is an implicit function rms-to-dc converter that renders a dc voltage dependent on the rms (heating value) of an ac voltage. in addition to the basic converter, this highly integrated functional circuit block includes two fully independent, optional amplifiers, a standalone fet input buffer amplifier and a precision dc output buffer amplifier (see figure 1 ). the rms core includes a precision current responding full-wave rectifier and a log-antilog transistor array for current squaring and square rooting to imple- ment the classic expression for rms (see equation 1). for basic applications, the converter requires only an external capacitor, for averaging (see figure 30 ). the optional on-board amplifiers offer utility and flexibility in a variety of applications without incurring additional circuit board footprint. for lowest power, the amplifier supply pins are left unconnected. why rms? the rms value of an ac voltage waveform is equal to the dc voltage providing the same heating power to a load. a common measure- ment technique for ac waveforms is to rectify the signal in a straightforward way using a diode array of some sort, resulting in the average value. the average value of various waveforms (sine, square, and triangular, for example) varies widely; true rms is the only metric that achieves equivalency for all ac waveforms. see table 5 for non-rms-responding circuit errors. the acronym rms means root-mean-square and reads as follows: the square root of the average of the sum of the squares of the peak values of any waveform. rms is shown in the following equation: (1) for additional information, select section i of the 2 nd edition of the analog devices rms-to-dc applications guide . rms core the core consists of a voltage-to-current converter (precision resistor), absolute value, and translinear sections. the translinear section exploits the properties of the bipolar transistor junctions for squaring and root extraction (see figure 23 ). the external capacitor (cavg) provides for averaging the product. figure 19 shows that there is no effect of signal input on the transition times, as seen in the dc output. although the rms core responds to input voltages, the conversion process is current sensitive. if the rms input is ac-coupled, as recommended, there is no output offset voltage, as reflected in table 1 . if the rms input is dc-coupled, the input offset voltage is reflected in the output and can be calibrated as with any fixed error. v? ac in v+ out + ? v + 5k? cavg absolute value circuit v-to-i 16k ? 10033-024 figure 23. rms core block diagram table 5. general ac parameters waveform type (1 v p-p) crest factor rms value reading of an average value circuit calibrated to an rms sine wave error (%) sine 1.414 0.707 0.707 0 square 1.00 1.00 1.11 11.0 triangle 1.73 0.577 0.555 ?3.8 noise 3 0.333 0.295 rectangular 2 0.5 0.278 ?11.4 pulse 10 0.1 0.011 ?44 scr ?89 dc = 50% 2 0.495 0.354 ?28 dc = 25% 4.7 0.212 0.150 ?30
ad8436 rev. 0 | page 11 of 20 the 16 k resistor in the output converts the output current to a dc voltage that can be connected to the output buffer or to the circuit that follows. the output appears as a voltage source in series with 16 k. if a current output is desired, the resistor connection to ground is left open and the output current is applied to a subsequent circuit, such as the summing node of a current summing amplifier. thus, the core has both current and voltage outputs, depending on the configuration. for a voltage output with 0 source impedance, use the output buffer. the offset voltage of the buffer is 25 v or 50 v, depending on the grade. fet input buffer referring to figure 1 , the input resistance of the ad8436 is 8 k, and a voltage source input is preferred. the optional input buffer is a wideband jfet input amplifier that minimally loads non-0 sources, such as a tapped resistor attenuator or voltage sensor. although the input buffer consumes only 150 a, the supply is pinned out and left unconnected to reduce power where needed. optional matched 10 k input and feedback resistors are provided on chip. consult the applications information section to learn how these resistors can be used. the 3 db bandwidth of the input buffer is 2.7 mhz at 10 mv rms input and approximately 1.5 mhz at 1 v rms. the amplifier gain and bandwidth are sufficient for applications requiring modest gain or response enhancement to a few hundred kilohertz (khz), if desired. configurations of the input buffer are discussed in the applications information section. precision output buffer the precision output buffer is a bipolar input amplifier, laser trimmed to cancel input offset voltage errors. as with the input buffer, the supply current is very low (<50 a, typically), and the power can be disconnected for power savings if the buffer is not needed. be sure that the noninverting input is also disconnected from the core output (out) if the buffer supply pin is discon- nected. although the input current of the buffer is very low, a laser-trimmed 16 k resistor, connected in series with the inverting input, offsets any self-bias offset voltage. the output buffer can be configured as a single or two-pole low- pass filter using circuits shown in the applications information section. residual output ripple is reduced, without affecting the converted dc output. as the response approaches the low frequency end of the bandwidth, the ripple rises, dependent on the value of the averaging capacitor. figure 26 shows the effects of four combinations of averaging and filter capacitors. although the filter capacitor reduces the ripple for any given frequency, the dc error is unaffected. of course, a larger value averaging capacitor can be selected, at a larger cost. the advantage of using a low-pass filter is that a small value of filter capacitor, in conjunction with the 16 k output resistor, reduces ripple and permits a smaller averaging capacitor, effecting a cost savings. the recommended capacitor values for operation to 40 hz are 10 f for averaging and 3.3 f for filter. dynamic range the ad8436 is a translinear rms-to-dc converter with exceptional dynamic range. although accuracy varies slightly more at the extreme input values, the device still converts with no spurious noise or dropout. figure 24 is a plot of the rms/dc transfer function near zero voltage. unlike processor or other solutions, residual errors at very low input levels can be disregarded for most applications. output voltage (mv dc) input voltage (mv dc) 30 20 10 0 0 30 20 10 ?10 ?20 ?30 ? or other digital solutions cannot work at zero volts ad8436 solution 10033-025 figure 24. dc transfer function near zero
ad8436 rev. 0 | page 12 of 20 applications information using the ad8436 this section describes the power supply and feature options, as well as the function and selection of averaging and filter capacitor values. averaging and filtering options are shown graphically and apply to all circuit configurations. averaging capacitor consid erationsrms accuracy typical ad8436 applications require only a single external capacitor (cavg) connected to the cavg pin (see figure 30 ). the function of the averaging capacitor is to compute the mean (that is, average value) of the sum of the squares. averaging (that is, integration) follows the absolute value circuit, where the polarity of negative input current components is reversed (rectified) prior to squaring. the mean value is the average value of the squared input voltage over several input waveform periods. the rms error is directly affected by the number of periods averaged, as is the resultant peak-to-peak ripple. the result of the conversion process is a dc component and a ripple component whose frequency is twice that of the input. the rms conversion accuracy depends on the value of cavg, so the value selected need only be large enough to average enough periods at the lowest frequency of interest to yield the required rms accuracy. figure 27 is a plot of rms error vs. frequency for various averaging capacitor values. for figure 27 , the additional error was 0.001% at 40 hz using a 10 f metalized polyester capacitor. larger values yield diminished returns because the settling time increases with negligible improvement in rms accuracy. to us e figure 27 , determine the minimum operating frequency and accuracy of the application and then find the suggested capacitor value on the chart. for example, for C0.5% rms at 100 hz, the capacitor value is 1 f. post conversion ripple reduction filter input rectification included in the ad8436 introduces a residual ripple component that is dependent on the value of cavg and twice the input signal frequency. for sampling applications such as a high resolution adc, the ripple component may cause one or more lsbs to cycle, and low value display numerals to flash. ripple is reduced by increasing the value of the averaging capacitor, or by postconversion filtering. ripple reduction following conversion is far more efficient because the ripple average value has been converted to its rms value. capacitor values for post- conversion filtering are significantly less than the equivalent averaging capacitor value for the same level of ripple reduction. this approach requires only a single capacitor connected to the out pin (see figure 25 ). the capacitor value correlates to the simple frequency relation of ? r-c, where r is fixed at 16 k. out 16k? ognd core clpf dc output 9 8 10033-026 figure 25. simple one-pole post conversion filter as seen in figure 26 , cavg alone determines the rms error, and clpf serves purely to reduce ripple. figure 26 shows a constant rms error for clpf values of 0.33 f and 3.3 f; only the ripple is affected. rms error (%) frequency (hz) 1 0 100 1k ?1 ?2 10 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?10 cavg = 10f clpf = 0.33f or 3.3f cavg = 1f clpf = 0.33f or 3.3f 10033-027 figure 26. rms error vs. frequency for two values of cavg and clpf (compare the effects of cavg and clpf, and note that clpf does not affect rms error result.) c onversion e r ror (%) 1k frequency (hz) 100 ?0.5 ?1.5 0 ?1.0 10 ?2.0 47f 10f cavg = 0.22f 1f 2.2f 0.47f 4.7f 22f 10033-028 figure 27. conversion error vs. frequency for various values of cavg
ad8436 rev. 0 | page 13 of 20 for simplicity, figure 28 shows ripple vs. frequency for four combinations of cavg and clpf ripple error (v p-p) input frequency (hz) 1 0.0001 100 1k 10 0.001 0.01 0.1 cavg = 1f, clpf = 0.33f cavg = 10f, clpf = 3.3f cavg = 10f, clpf = 0.33f cavg = 1f, clpf = 3.3f ac input = 300mv rms 10033-029 figure 28. residual ripple voltage for various filter configurations figure 29 shows the effects of averaging and post-rms filter capacitors on transition and settling times using a 10-cycle, 50 hz, 1 second period burst signal input to demonstrate time- domain behavior. in this instance, the averaging capacitor value was 10 f, yielding a ripple value of 6 mv rms. a postconversion capacitor (clpf) of .068 f reduced the ripple to 1 mv rms. an averaging capacitor value of 82 f reduced the ripple to 1 mv but extended the transition time (and cost) significantly. input 50hz 10 cycle burst 400mv/div time (100ms/div) cavg = 82f cavg = 10f for both plots, but red plot has no low-pass filter, green plot has clpf = 68nf 100mv/div 10033-030 figure 29. effects of various filter options on transition times capacitor construction although tolerant of most capacitor styles, rms conversion accuracy can be affected by the type of capacitor that is selected. capacitors with low dc leakage yield best all around performance, and many sources are available. metalized polyester or similar film styles are best, as long as the temperature range is appropriate. for practical applications such as the rms-to-dc function in dmms or power monitoring circuits, surface mount tantalums are the best over-all choice. basic core connections many applications require only a single external capacitor for averaging. a 10 f capacitor is more than adequate for acceptable rms errors at line frequencies and below. the signal source sees the input 8 k voltage-to-current conversion resistor at pin 2 (rms); thus, the ideal source impedance is a voltage source (0 source impedance). if a non-zero signal source impedance cannot be avoided, be sure to account for any series connected voltage drop. an input coupling capacitor must be used to realize the near-zero output offset voltage feature of the ad8436 . select a coupling capacitor value that is appropriate for the lowest expected operating frequency of interest. as a rule of thumb, the input coupling capacitor can be the same as or half the value of the averaging capacitor because the time constants are similar. for a 10 f averaging capacitor, a 4.7 f or 10 f tantalum capacitor is a good choice (see figure 30 ). vee cavg vcc out rms ognd +5v 10f ?5v ignd cav g ad8436 19 2 11 10 8 9 17 4.7f or 10f 10033-031 figure 30. basic applications circuit using a capacitor for high crest factor applications the ad8436 contains a unique crest factor feature. crest factor is often overlooked when considering the requirements of rms- to-dc converters, but it is very important when working with signals with spikes or high peaks. the crest factor is defined as the ratio of peak voltage to rms. see table 5 for crest factors for some common waveforms. vee cavg ccf vcc out rms ognd +5v 10f ?5v ignd cav g 0.1f ccf ad8436 19 18 2 11 10 8 9 17 4.7f or 10f 10033-032 figure 31. connection for additional crest factor performance crest factor performance is mostly applicable for unexpected waveforms such as switching transients in switchmode power supplies. in such applications, most of the energy is in these peaks and can be destructive to the circuitry involved, although the average ac value can be quite low. figure 13 shows the effects of an additional crest factor capacitor of 0.1 f and an averaging capacitor of 10 f. the larger capacitor serves to average the energy over long spaces between pulses, while the ccf capacitor charges and holds the energy within the relatively narrow pulse.
ad8436 rev. 0 | page 14 of 20 using the fet input buffer the on-chip fet input buffer is an uncommitted fet input op amp used for driving the 8 k i-to-v input resistor of the rms core. pin 3, pin 4, and pin 5 are the i/o, pin 6 is an optional connection for gain in the input buffer, and and pin 16 connects power to the buffer (see figure 3 and table 4 for location and description). connecting pin 16 to the positive rail is the only power connection required because the negative rail is internally connected. because the input stage is a fet and the input impedance must be very high to prevent loading of the source, a large value (10 m) resistor must be connected from midsupply at pin 11 (ignd) to pin 5 (ibufin+) to prevent the input gate from floating high. for unity gain, connect pin 3 (ibufout) to pin 4 (ibufin?). for a gain of 2, connect pin 6 (ibufgn) to ground. see figure 8 and figure 9 for large and small signal responses at the two built-in gain options. the offset voltage of the input buffer is 500 v, depending on grade. a capacitor connected between the buffer output pin 3 (ibufout) and pin 2 (rms) is recommended so that the input buffer offset voltage does not contribute to the overall error. select the capacitor value for least minimum error at the lowest operating frequency. figure 32 is a schematic showing internal components and pin connections. ibufout ibufin+ ibufin? ? + ibufgn 10k ? 10k ? 10pf 6 5 4 3 2 rms 10f 0.47f 10m ? 11 ignd 16 ibufv+ 10033-033 figure 32. connecting the fet input buffer capacitor coupling at the input and output of the fet buffer is recommended to avoid transferring the buffer offset voltage to the output. although the fet input impedance is extremely high, the 10 m centering resistor connected to ignd must be taken into account when selecting an input capacitor value. this is simply an impedance calculation using the lowest desired frequency, and finding a capacitor value based on the least attenuation desired. because the 10 k resistors are closely matched and trimmed to a high tolerance, the input buffer gain can be increased to several hundred with an external resistor connected to pin 4 (ibufin?). the bandwidth diminishes at the typical rate of a decade per 20 db of gain, and the output voltage range is constrained. the small signal response, as shown in figure 8 , serves as a guide. as an example, suppose one wanted to detect small input signals at power line frequencies? an external 10 resistor connected from pin 4 to ground sets the gain to 101 and the 3 db bandwidth to ~30 khz, which is more than adequate for amplifying power line frequencies. using the output buffer the ad8436 output is a precision op amp that is optimized for dc operation. figure 33 shows a block diagram of the basic amplifier and i/o pins. the amplifier is intended for noninverting operation only; note that the 16 k resistor, in series with the inverting input of the amplifier, is used to balance the bias current of the noninverting amplifier. as with the input fet buffer, the amplifier positive supply is pinned out separately for power sensitive applications. in normal circumstances, the buffers are connected to the same supply as the core. figure 34 shows the signal connections to the output buffer. note that the input offset voltage contribution by the bias currents are balanced by equal value series resistors, resulting in near zero offset voltage. obufout obufin+ obufin? 16k ? output buffer ? + 10033-034 figure 33. output buffer block diagram out 16k ? 16k ? ognd obufout obufin+ obufin? ? + core ibias 9 8 ibias 14 13 12 10033-035 figure 34. basic output buffer connections for applications requiring ripple suppression in addition to the single-pole output filter described previously, the output buffer is configurable as a two-pole sallen-key filter using two external resistors and two capacitors. at just over 100 khz, the amplifier has enough bandwidth to function as an active filter for low frequencies such as power line ripple. for a modest savings in cost and complexity, the external 16 k feedback resistor can be omitted, resulting in slightly higher v os (80 v). 16k ? 16k ? 16k ? 16k ? ognd obufout obufin+ obufin? ? + core c 8 14 13 12 9 out 10033-036 2c figure 35. output buffer amplifier conf igured as a two-pole, sallen-key low-pass filter
ad8436 rev. 0 | page 15 of 20 ignd 4.7f rms 10 f 0.47f vee cav vcc ognd 2 11 10 19 8 9 17 10m ? 4 5 3 ibufout ibufin+ ibufin? out ad8436 4.7f 10033-039 configure the output buffer as shown in figure 36 to invert the dc output. out 16k ? 16k ? ognd obufout obufin+ obufin? core 32.4k ? 8 14 12 13 9 ? + 10033-037 figure 36. inverting output configuration current output option if a current output is required, connect the current output, out (pin 9), to the destination load. to maximize precision, provide a means for external calibration to replace the internal trimmed resistor, which is bypassed. this configuration is useful for conve- nient summing of the ad8436 result with another voltage, or for polarity inversion. figure 38. connections for single supply operation recommended application figure 39 shows a circuit for a typical application for frequencies as low as power line, and above. the recommended averaging, crest factor and lpf capacitor values are 10 f, 0.1 f and 3.3 f. refer to the using the output buffer section if additional low-pass filtering is required. cavg out rms 8k? 16k ? 16k ? 15k ? ognd core ccf 2 9 8 18 19 do not connect for current output 2k ? (optional) ? + direction of dc output current inverted dc voltage output 10033-038 a c in v cc vee dc out 10m ? vee cavg vcc obufout ignd obufin+ obufin? obufv+ out dnc ibufin? ibufout ibufin+ sum ibufv+ 1 4 3 2 5 87 69 12 11 10 16 15 14 13 10f 0.47f ognd ibufgn ccf 10f + 19 18 17 20 dnc rms 3.3f 0.1f ad8436 10033-040 figure 37. connections for current output showing voltage inversion single supply connections for single supply operation are shown in figure 38 and are similar to those for dual power supply when the device is ac-coupled. the analog inputs are all biased to half the supply voltage, but the output remains referred to ground because the output of the ad8436 is a current source. an additional bypass connection is required at pin 11 (ignd) to suppress ambient noise. figure 39. typical application circuit
ad8436 rev. 0 | page 16 of 20 ad8436 evaluation board the ad8436 -evalz provides a platform to evaluate ad8436 performance. the board is fully assembled, tested and ready to use after the power and signal sources are connected. figure 45 is a photograph of the board. signal connections are located on the primary and secondary sides, with power and ground on the inner layers. figure 40, figure 41, figure 42, figure 43, and figure 44 illustrate the various design details of the board, including a basic layout and copper patterns. these figures are useful for reference for application designs. a word about using the ad8436 evaluation board the ad8436-evalz offers many options, without sacrificing simplicity. the board is tested and shipped with a 10 f averaging capacitor (cavg), 3.3 f low-pass filter capacitor (c8) and a 0.1 f (copt) capacitor to optimize crest factor performance. to evaluate minimum cost applications, remove c8 and copt. the functions of the five switches are listed in table 6. table 6. switch function core_buffer selects core or input for the input signal incoup selects ac or dc coupling to the core sdcout selects the output buffer or the core output at the dcout bnc. ibuf_vcc enable or disables the input buffer obuf_vcc enable or disa bles the output buffer all the i/os are provided with test points for easy monitoring with test equipment. the input buffer gain default is unity; for 2 gain, install a 0603 0 resistor at position r5. for higher ibuf gains, remove the 0 resistor at position rfbh (there is an internal 10 k resistor from the obuf_out to ibufin?) and install a smaller value resistor in position rfbl. a 100 resistor establishes a gain of 100. single supply operation requires removal of resistor r6 and installing a 0.1 f capacitor in the same position for noise decoupling. 10033-041 figure 40. assembly of the ad8436 -evalz 10033-042 figure 41. ad8436 -evalz primary side copper 10033-043 figure 42. ad8436 -evalz secondary side copper 10033-044 figure 43. ad8436 -evalz power plane 10033-045 figure 44. ad8436 -evalz ground plane
ad8436 rev. 0 | page 17 of 20 10033-046 figure 45. photograph of the ad8436 -evalz tsum a c in tacin + v (red) vcc vee *components in gray are not factory installed. rfbh 0 ? rfbl dni gnd5 gnd4 gnd3 gnd2 dc out tibufout tibfin+ r1 1m ? vee cavg vcc obuf out ignd obuf in+ obuf in? obuf v+ out dnc ibufin? ibufout ibufin+ sum ibuf v+ 1 4 3 2 5 87 69 12 11 10 16 15 14 13 tcave c3 0.1f core buf core buf tobfout gnd1 c4 0.1f c2 10f 50v ?40c to +125c c1 10f 50v ?40c to +125c + tdcout gnd6 sdcout cin 10f dc ac c5 0.47f trmsin tibfin? tognd tiout tignd r3 4.99k ? r4 4.99k ? c7 0.22f c6 0.47f tobufin+ tobufin? tobufv+ tibufv+ en en r8 0 ? r7 0 ? r6 0 ? obuf_vcc dis ibuf_vcc dis core_buf tbufgn ognd ibufgn dnc ad8436 cave 10f + vee ?v (grn) + 19 18 17 20 incoup dnc rms r5 0 ? r2 0 ? c38 3.3f topt copt 0.1f 10033-047 figure 46. evaluation board schematic
ad8436 rev. 0 | page 18 of 20 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd. 061609-b bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.65 2.50 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 47. 20-lead lead frame chip scale package [lfcsp_wq] (cp-20-10) dimensions shown in inches ordering guide model 1 temperature range package description package option ad8436acpz-r7 ?40c to +125c 20-lead lead frame chip scale [lfcsp_wq] cp-20-10 AD8436ACPZ-RL ?40c to +125c 20-lead lead frame chip scale [lfcsp_wq] cp-20-10 ad8436acpz-wp ?40c to +125c 20-lead lead frame chip scale [lfcsp_wq] cp-20-10 ad8436jcpz-r7 0c to +70c 20-lead lead frame chip scale [lfcsp_wq] cp-20-10 ad8436jcpz-rl 0c to +70c 20-lead lead frame chip scale [lfcsp_wq] cp-20-10 ad8436jcpz-wp 0c to +70c 20-lead lead frame chip scale [lfcsp_wq] cp-20-10 ad8436-evalz evaluation board 1 z = rohs compliant part.
ad8436 rev. 0 | page 19 of 20 notes
ad8436 rev. 0 | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10033-0-7/11(0)

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