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IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 1 high voltage led lighting driver with three level power sequencing general description IS31LT3938 led driver ic is a peak current detection buck converter which operates in constant off time mode. it operates over a very wide input voltage supply range of 10vdc to 450vdc or 110vac/220vac. IS31LT3938 incorporates the special feature of three power sequencing levels by detecting off-on cycles of the main power switch. when the switch is cycled within a 4 second period (typical) the device automatically switches the power level to the next step. as a result, the input and output power of the luminaire may be adjusted depending on the desired amount of illumination and/or power consumption. there are multiple power levels that the engineer may configure, 2 steps or 3 steps, via the external pins dim1 and dim2. IS31LT3938 can also realize led dimming using an external pwm signal. it can accept a pwm signal from 0% to 100% duty cycle. the led current may also be adjusted linearly by applying an analog input voltage in the range of 0.5v to 2.5v. IS31LT3938 adopts a peak current mode control architecture, which eliminates the need for any additional loop compensation while maintaining a good degree of constant output current regulation. features ? user configurable power sequencing levels ? 3% output current accuracy ? over current, temperature protection and short circuit protection ? high efficiency (typical up to 95%) ? higher mos drive voltage ? wide input voltage range: 10vdc~450vdc or 85vac~ 265vac ? linear and pwm dimming ? very few external components applications ? dc/dc or ac/dc constant current led driver ? signal and decorative lighting ? backlight led driver typical application circuit gate cs adj toff vin dim1 dim2 gnd fuse ac input led+ led- r ext r cs q1 c in r in c1 d5 l1 c3 d1 d2 d3 d4 switch k is3938 copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifi cation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, produc ts or services described herein. customers are advised to obtain the latest version of this device specification before relying on any publish ed information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fail ure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or eff ectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfac tion, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 2 pin configuration package pin configurations sop-8 pin description pin name pin number description dim1 1 these two pins configure the power sequencing levels as follows: dim1=?floating?dim2=?floating?, no dimming (100% only) dim1=?floating?dim2=?gnd? , 100%-30%-100% dim1=?gnd?dim2=?floating?, 100%-50%-100% dim1=?gnd?dim2=?gnd?, 100%-50%-20%-100% dim2 2 adj 3 linear and pwm dimming input pin. linear dimming range: 0.5v to 2.5v. if v adj < 0.5v, gate output is off. if 0.5v v adj 2.5v, v csth = v adj /10. if v adj > 2.5v, v csth = 0.25v. when the pin is floating, there is an internal pull up to 4.5v (typical) and v csth = 0.25v. recommended pwm dimming frequency range: 200hz -1khz. gnd 4 ground pin. all internal currents return through this pin. gate 5 this pin connects to the external nmos?s gate cs 6 current detect pin, uses an external resistor to sense the peak inductor current. toff 7 this pin sets the off time for the switch by connecting a resistor between this pin and gnd. vin 8 10v ? 450v supply voltage is connected to this pin via an external resistor. it is internally clamped and must be bypassed using a capacitor to gnd. ordering information industrial range: -40c to +85c order part no. package qty/reel IS31LT3938?grls2-tr sop-8, lead-free 2500
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 3 absolute maximum ratings parameter range unit vin pin to gnd -0.3 - 13.0 v dim1,dim2,cs, adj, gate, toff pin to gnd -0.3 - 6.0 v vin pin input current (note1) 10 ma operating junction temperature(t a =t j ) -40 - 125 o c junction temperature -40 - 150 o c device storage temperature -65 - 150 o c esd human body model 2000 v stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditio ns is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. electrical characteristics (the specifications are at ta=25c and v indc =20v (note2) , r in =10k, unless otherwise noted) (note3) symbol parameter conditions min typ max unit v indc input dc supply voltage range supply voltage connected to vin via an appropriate resistor 10 450 v v clamp vin pin clamp voltage 8 9 10 v uvlo undervoltage lockout vin falling 7 v uvlo uvlo hysteresis 1.6 v i in quiescent current vin=v clamp , gate floating 450 600 ua i in,uv input current in uvlo vin= uvlo 200 300 ua v csth current sense threshold adj=5v 245 250 255 mv t blank current sense blanking time v cs =v csth +50mv 500 ns toff off time r ext =250k ? 10 us v adj (note 4) pwm input voltage high threshold 2.5 v pwm input voltage low threshold 0.5 v linear dimming input voltage range 0.5 2.5 v tr gate rises from 0.1*vclamp to 0.9*vclamp c gate =1nf 50 80 ns tf gate falls from 0.9*vclamp to 0.1*vclamp c gate =1nf 50 80 ns t p over temperature protection threshold 150 o c t p over temperature protection hysteresis 20 o c v ocp over current protection cs voltage threshold adj=5v 0.4 v toff _reset over current protection toff delay time 2.8 4 5.2 ms t max maximum switch off time for power level sequencing 4 s note1: beyond the input current range, vin pin may not clamp at 9v(typical). note 2: v indc is the input voltage. when v indc >9v, input voltage connected to vin pin should via a appropriate resistor. note 3: production testing of the chip is performed at 25 c. functional operation of the chip and parameters specified are guaranteed by design, characterization and process control in other temperature note 4: when v adj > 2.5v, i out is 100% output current. when v adj < 0.5v, i out is shutdown. when 0.5v v adj 2.5v, i out is linear dimming.
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 4 application information IS31LT3938 is a peak current control led driver ic. it does not require any high side current sensing nor the design of any closed loop control, yet provides a very accurate constant led drive current. IS31LT3938 includes an input allowing either a pwm or an analog dimming signal. an external resistor connected to the toff pin determines the internal oscillator?s constant off time. the off time adds to the on time, controlled by the internal switching control logic, to set the oscillation frequency. the inductor current increases when the switch is on. this current also flows through the external current sense resistor r cs , and when the voltage across r cs reaches the current sense threshold, v csth or 1/10 of the adj input voltage, whichever is lower, the switch turns off. the current through the inductor will continue to flow through the leds, but will decrease linearly during the switch off time. after the programmed off-time, the switch will turn on again. a short blanking time of 500ns (typical) is implemented to block the voltage spike encountered across r cs , caused by the parasitic capacitance of the switch discharging. after the blanking time the control logic again compares the cs input voltage to the current sense threshold. choose the acceptable level of ripple current coefficient, k then calculate the value of the current sense resistor: led csth cs i k v r ) 2 / 1 ( ? ? v csth : if v adj < 0.5v, gate output is off. if 0.5v v adj 2.5v, v csth = v adj /10. if v adj > 2.5v, v csth = 0.25v. when adj pin is floating, there is an internal pull up to 4.5v (typical) and v csth = 0.25v. k: acceptable current ripple coefficient, the recommended value range is 1~1.8 a constant off-time peak current control scheme can easily operate at duty cycles greater than 0.5 and also gives inherent input voltage rejection making the led current almost insensitive to input voltage variations. input voltage regulation the vin pin is internally clamped to 9v (typical). when supplying a voltage larger than 9v, an external resistor must be used between the input voltage and the vin pin. bypass the vin pin using a low esr capacitor to provide a high frequency path to gnd. the current required by the device is 0.45ma plus the switching current of the external switch. the switching frequency of the external nmos affects the amount of current required, as does the nmos?s gate charge requirement (found on the nmos data sheet). s g in f q ma i ? ? ? 45 . 0 in the above equation, f s is the switching frequency, q g is the external nmos gate charge (from the nmos datasheet). current detection the cs pin input voltage is internally provided to 2 comparators. one of the comparators uses an internal 250mv reference, while the other uses a scaled value of the adj pin voltage. the outputs of the comparators are ored, thus causing the lower of the 2 thresholds to trigger the switch control logic. at the moment the switch control logic changes the gate signal to low, the toff timer is started. the external switch will remain off for the length of time programmed, and once the toff time is expired, the switch control logic again toggles the gate signal, this time from low to high, and the external switch turns on. as the external switch turns on, the parasitic capacitance on the drain of the switch must discharge through the switch channel causing a spike of current which can be quite large, but only lasts for a very short period of time. to prevent this current from causing a false triggering of the current sense comparators, the signal is blocked from the internal comparators for 500ns (typical). in some special cases, the 500ns blanking time may not be sufficient to prevent false triggering of the cs threshold logic. under these circumstances, an additional rc filter may be added to the cs input pin to help filter the voltage spike. careful layout of the pcb to minimize parasitic capacitance, trace resistance and inductance greatly aid in the elimination of false triggering.
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 5 oscillator IS31LT3938?s toff pin controls the off time of the internal oscillator. oscillator off time is determined by the following equation: ext r s toff ? ? ? ? 12 10 40 ) ( r ext resistor connected between toff and gnd switchable power levels IS31LT3938 detects the external switch action of the main power switch, and can automatically adjust the level of the output current based on the action of the main power switch. the action of the external power switch can be divided into two types. the first is ?normal switch operation? wherein the switch is toggled from on to off, remaining off for longer than 4 seconds (typical). the other is ?power sequencing action? wherein the switch is toggled from on to off and back on within 4 seconds (typical). when the device experiences normal switch operation, it merely powers on in the first state, 100%, when the power switch is toggled to on, and the device turns off when the external power switch is changed to off. power sequencing output current levels are configured by connecting the dim1 and dim2 pins as indicated in the table below dim1 dim2 power sequencing levels floating floating no power sequencing floating gnd 2 levels 100%-30%-100% gnd floating 2 levels 100%-50%-100% gnd gnd 3 levels 100%-50%-20%-100% when operating the power switch normally the device will always power up at 100% output current. the operation of the power switch and the configuration of the dim1 and dim2 pins control the power sequencing process as follows 1. when dim1 and dim2 pins are both floating, there is no switchable power levels, and the output current is 100% of the programmed value when the power is on. 2. when dim1 is floating and dim2 is gnd, the output current is a) 100% at power on. b) the first power sequencing action causes the current to change to 30%. c) a second power sequencing action causes the current to return to 100%. d) a third power sequencing action has the same effect as the first power sequencing action. e) subsequent power sequencing actions causes the cycle to continue. 3. when dim1 is gnd and dim2 is floating, the dimming sequence is as described in (2) above, except that the current sequence is 100%-50%-100%. 4. when both dim1 and dim2 are connected to gnd, the dimming sequence is as described in (2) above, except that the current sequence is 100%-50%-20%-100%. if the switch is operated normally, that is, switched on once after being in the off position for a long time, or if both the dim1 and dim2 pins are floating, then the output current always starts up at the initial value of 100%. note: because the main power switch is used to initiate the power sequencing function, the device must have a large enough external capacitor on vin to maintain device operation for 4 seconds. linear dimming an external voltage, 0.5v to 2.5v, connected to the adj pin can adjust the led current. two possible situations where this might be used are if it is not possible to change the value of r cs to obtain the desired value of led current, an external voltage reference can be connected to the adj pin to adjust the voltage sense level across r cs , equivalent to changing the value of r cs . connecting a resistor between the vin and adj pin, then connecting a thermistor from the adj pin to gnd can adjust the led current based on temperature, thus realizing the temperature compensation feature.
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 6 pwm dimming pwm dimming may be realized by applying a low frequency pwm waveform to the adj pin. when the pwm signal is low, less than 0.5v, the IS31LT3938 remains off when the pwm signal is high, greater than 2.5v, the driver is enabled and operates normally. the pwm signal does not shut down other circuit blocks of the device, thus the response to the pwm signal is relatively fast, and primarily determined by the rise and fall time of the inductor current. to disable pwm dimming, leave the adj pin floating.
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 7 application example input voltage in v = 220v dc output vo=40v 12 x 1w leds in series, vf=3.3v i led =0.35a no power sequencing levels 1. vin power supply circuit vin supply current is given by: s g in f q ma i ? ? ? 45 . 0 assuming i in =1ma, then ? ? ? ? ? ? k i vin vin r in in 211 1 9 220 choose two 430k ? /0.5w in parallel for the resistor lifetime consideration. choose c in : 10uf/25v ceramic capacitor. 2. constant off time toff off time is given by ext r s toff ? ? ? ? 12 10 40 ) ( to decide the off time, assume the desired switching frequency is 50khz(period time t=20us), and the duty cycle: % 18 . 18 220 40 ? ? ? vin vo d the duty cycle is decided by the ratio of the output voltage and input voltage, then toff: us us d t toff 36 . 16 %) 18 . 18 1 ( 20 ) 1 ( ? ? ? ? ? ? ? , so r ext =409k ? , choose the closest resistor, r ext =390k ? , the actual toff=15.6us(because the actual toff is smaller than theoretical toff, the operating frequency will be little higher than 50khz). 3. current sense resistor r cs the ripple current: led ripple i k i ? ? , k is the ripple current coefficient, the recommended value range is 1~1.8. the peak current : led ripple led peak i k i i i ? ? ? ? ? ? ? ? ? ? ? 2 1 2 because of adj pin floating, v csth =0.25v . assuming a typical value for k of 1.8. the current sense resistor is given by ? 376 . 0 35 . 0 2 8 . 1 1 25 . 0 2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? led csth peak csth cs i k v i v r choose r cs =0.38 ? and 1% precision. 4. inductor l1 the inductance of inductor l1 is dependent on the led current, in this case 350ma. we have already chosen toff=15.6us, thus: mh i k t v i t v l led off o ripple off o 1 35 . 0 8 . 1 10 6 . 15 40 6 ? ? ? ? ? ? ? ? ? ? ? where i ripple is the design target for ripple current. note: the saturation of inductor must be higher than the peak current. 5. freewheeling diode (d5) and nmos (q1) choose q1 to have a voltage rating at least as large as the peak voltage of the maximum input voltage with approximately 50% margin. vin v nmos ? ? ? 2 % 150 the current through the nmos is based on the peak led current, choose fet current rating with 50% margin. peak nmos i i ? ? % 150 thus, choose 600v, 2a, nmos, such as: 2n60 the diode ratings are equal to that of the nmos, q1. note: the diode must be a superfast recovery diode and the reverse recovery time (t rr ) should be less than 50ns. thus, choose 600v, 1a, superfast recovery diode, such as: es1j, sf18
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 8 appendix: typical application circuit of dc voltage input
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 9 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. classification profile
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 10 tape and reel information
IS31LT3938 preliminary integrated silicon solution, inc. ? www.issi.com r0.1, 04/25/2012 11 package information sop-8 3 d f n d j h 2 x w o l q h ' u d z l q j ' % 6 &

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