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AN11275 sgpio on the lpc4300 rev. 1 ? 7 november 2012 application note document information info content keywords sgpio, lpc4300, pwm abstract a guide how to set up and use sgpio on the lpc4300 series
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. appl ication note rev. 1 ? 7 november 2012 2 of 20 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com revision history rev date description 1 2012110 7 initial revision.
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 3 of 20 1. introduction t his application note explains the basics o f sgpio , how to work with it and what is possible. it also includes a simple example that emulates pwm via sgpio , designed for engineers that haven't worked with sgpio and need something to get started. the example generates one pwm signal per sgpio slice , giving a maximum of 16 extra pwm channels. these channels are 5 - bit pwm channels that can be fully on or off with an adjustable frequency. the code is tested on the keil mcb4300 with keil 4.53 .
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 4 of 20 2. what is sgpio? serial gpio is a new digital configurable peripheral available on the lpc43xx devices from nxp . with sgpio it is possible to create serial data protocols with very little cpu load compared to bit banging. sgpio ?s basic building block is slice. the slice i s the hardware part that handles the data processing when sending or receiving data . t here are a total of 16 sgpio slices and 16 sgpio io pins in the sgpio interface. fig 1 shows the basic components inside a slice. a slice basically consists of a 32 - bit fifo (main register reg in fig 1 ) that i s used to clock data in or out, a shadow register (reg_ss register in fig 1 ) for setting up the output data or receiving the input data , a 12- bit d own counter to generate the shift clock and an 8 - bit down counter to control the nu mber of bits shifted in or out. fig 1. block diagram of a single slice the slice?s shift clock can be sourced from the sgpio peripheral clock (sgpio_clock). please refer to fig 2 below to understand sgpio_clock ?s base clock, and section 5.1 for more sgpio_clock setup.
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 5 of 20 at every sgpio_clock, the 12 - bit down counter (count in fig 1 ) counts down by 1. when this 12 - bit down counter (count) reaches zero, a data bit is shifted in or out of the fifo (main register reg). then count is reloaded with the value in the preset register. therefore, the value in the preset register determines the shift clock speed. frequency (shift clock) = frequency (sgpio_clock) / (preset+1) each slice includes an 8- bit down counter (register pos in fig 1 ) that control s the number of bits shifted in or out of the slice. every time the count register reaches zero a data bit is shifted in or out of the fifo and the pos register decrements by 1. when the pos register reaches zero it is reloaded with the value in pos_preset and the main register reg and its shadow register (reg_ss)?s contents get exchanged. for an output slice new data is written to the shadow register and when the slice is done se nding the data in the main buffer the two buffers get exchanged. for an input slice new data is clocked in the main buffer and when the slice is done collecting the data in the main buffer the two buffers get exchanged. hence, to exchange the main register and the shadow register every m bit the pos_preset should be set up as m - 1. to exchange the content every k*32 bit pos_preset should be 0x20 * k ? 1. this setting should be used when k slices are concatenated. tip 1: t he pos register is divided into two parts, the pos counter and the pos counter?s preset value. please refer to table 222 in the user manual for details. tip 2: an sgpio pin is not the same as an sgpio slice ; a pin number is not equal to a slice number! a slice connects to an sgpio pin using a pin mux. because of this one slice can be connected to multiple pins and multiple slices can be concatenated to one sgpio pin. an sgpio slice can be connected to 1, 2, 4 or 8 sgpio pins. up to eight slices can be concatenated to input or output through one sgpio pin. fig 2. table 209 of the user manual, sgpio clocking and power control fig 3. table 22 2 of the user manual, position register
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 6 of 20 tip 3: the slices are identified by letter a to letter p. slice a is the first slice, slice b is the second slice and so on. 3. sgpio usage sgpio can be used to "emulate" serial protocols in those case s when an additional spi/i2c/uart is needed. sgpio can also be used to create fast serial and parallel protocols like pwm, e.g., reading in parallel data from a camera module and display/vga generation. the max speed of a clock signal that can be generated with sgpio is half the clock speed of the cpu. therefore, the absolute max speed of the sgpio_clock is 102 mh z when using the maximum 204 mh z cpu clock. a complex example for a 7.1 soundcard can be downloaded from http://lpcware.com/content/project/lpc4350 - hitex - board - getting - started - guide it connects to a computer via usb and uses sgpio to send audio data from usb to four stereo i2s dac s. a simple example that creates a pwm signal is provided with this document. 4. register descriptions sgpio is an extremely flexible peripheral. with that flexibility a lot of options are possible, but it also means there are a lot of registers to set up . the registers are divided in four groups: 1. registers for slice/sgpio pin multiplexing control 2. registers for slice operation control (double buffering and shift clock control) 3. registers for interrupt spec ific settings 4. registers for sgpio pin control note: the following information is meant to accompany and expand on chapter 18.6 of the user manual, which provides an explanation of all available register settings in the sgpio. 4.1 slice/sgpio pin multiplexing r egisters for this group of registers, replace ?x? with the correct number for the slice. 0 for slice a, 1 for slice b, 2 for slice c and so on. 4.1.1 out_mux_cfgx the out_mux_cfg register is used to set up the output mode of the slice and how many i/o pins are u sed in an output slice. it is possible for one sgpio slice to use 1, 2, 4 or 8 i/o pins. bit s 3:0 control how many pins are used in the different slice output configurations or whether the corresponding pin is for shift clock output or gpio output.
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 7 of 20 bit s 6:4 determine how the output enable is controlled. the output enable can be controlled by the gpio_oenreg register or by a different slice according to the confi guration above. the output states include low or high in active mode or tri - state when disabled. in the following table the output pin multiplexing can be found . fig 4. table 212 of the user manual, output pin multiplexer configuration register out_mux_cfg
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 8 of 20 this table can be found on page 353/354 of the user manual rev 1.3. for example, when sgpio pin 1 is used in 1 - bit mode the corresponding slice is slice i. 4.1.2 sgpio_mux_cfgx with the sgpio_mux_cfg register the clock and concatenate settings can be changed. bit 11 is used to enable slice concatenation. when this bit is high the sgpio slice will send the data in the main register , exchange the data and shadow register , and send the data in the main register again. if this bit is low it will stop after the first exchange. to use an external pin as shift clock bit 0 should be 1 and the clock pin can be selected with bit s 2:1 ; sgpio pin 8, 9 10 and 11 can be used as an external clock input. with bit s 13:12 it is possible to concatenate multiple slices to create a bigger fifo buffer according to the following table. for example, i f slice a is chosen as an input slice and a 4 slice big fifo buffer is used the buffer will look like this: 1. after the fifo from a is shifted, the fifo of slice i follow s. 2. a fter s lice i the fifo of slice e follows . 3. a fter slice e the fifo of slice j follows. 4. after slice j is complete , the main registers of slice a, i, e, j are exchanged with their own shadow registers. 5. the input then starts from slice a again, followed by slic e i, e, j. note: in the programming code the data registers of s lice a, i, e and j should all be handled and should be seen as one big 12 8- bit fifo buffer. fig 5. table 213 from the user manual, sgpio output pin multiplexing and corresponding slice letter
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 9 of 20 4.1.3 slice_mux_cfgx with the slice_mux_cfg register , a couple of settings can be used . when using the data match interrupt bit 0 has to be high. when using data match mode, the slice?s shadow register should hold the pattern to be matched. in addition, when data match is enabled the m ain register and the shadow register will not exchange when fifo is done with input or output data. with bit 2 the clock input can be chosen ; 0 for the internal clock and 1 to use an external clock. it works only when this bit and sgpio_mux_cfg are set to use an external clock. with bits 5:4 the input bit match interrupt mode can be sele cted: 0b00 for rising edge, fig 6. fig 38. f rom the user manual, concatenation interconnections
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 10 of 20 0b01 for falling edge , 0b10 for low level , 0b11 for high level. with bits 6:7 the amount of bits that are shifted out per clock can be chosen. when a slice has multiple i/o pins this va lue has to be set accordingly: 0b00 for 1 bit, 0b01 for 2 bits, 0b10 for 4 bits or 0b11 for 8 bit s per clock. 4.2 slice operation control registers 4.2.1 regx this is the data register . a s long as a slice is enabled it will shift a data bit in or out at every shift clock. data is right shifted, data is shifted in at bit 31 and data is shifted out from bit 0. 4.2.2 reg_ssx this is the shadow register for the data. every time a slice is done with sending or receiving data it exchanges the data and shadow register. this way the shadow register can be read or written at any time. 4.2.3 presetx with the presetx register the sgpio_clock can be divided down to a lower speed. to calculate the value for this register the following formula is used: presetx value = (sgpio_clock speed / shift clock speed) ? 1. when a 1. 5 mh z clock speed is required for a slice and a 12 mh z sgpio clock is used the correct presetx value is (12/1.5) ? 1 = 7. 4.2.4 posx each position register contains the position counter for one slice: pos0 to pos15 contain the counter for slice a (register 0) to slice p (register 15). this register controls when the shadow register reg_ss content is exchanged with main register reg. it has [15:8] as the pos_preset value and [7:0] as the current data bit pos counter. at each data bit shift , pos decrements by 1. when pos reaches zero, pos is restored with its pos_preset value. this should be 31 when the main register and the shadow register exchange aft er all 32 bits of data have shifted in or out. but when concatenating k slices this value should be (0x20 * k - 1). for example, when concatenating 4 slices and every slice needs to shift in or out all of i ts 32 - bit data, posx should be (32 * 4 - 1) = 127. please refer to fig 3 for some more details for this register. tip 4. before a slice is started (using ctrl_enable), pos should be set to the pos_preset value. 4.2.5 mask_a, mask_h, mask_i, mask_p the mask registers are used for the ?on pattern match? interrupts. with some slices it is possible to mask the data for the pattern match interrupts. slices a, h, i and p support this function. every bit that is 1 in this register will be masked. if this register contains the value 0b00001111 the first 4 bits will be masked for the pattern interrupt. see chapter 6 , sgpio interrupts for more information.
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 11 of 20 4.2.6 ctrl_enable with the ctrl_enable register set to 1 for a particular bit the corresponding slice?s 12 - bit count down counter or external shift clock is started to provide the data shift clock for the slice. 4.2.7 ctrl_disable with the ctrl_disable register set to 1 for a particular bit the corresponding slice?s count clocks or external shift clock is disabled. when this register i s set, it synchronously disables the posx counter when posx counter reaches a zero count. the ctrl_disabled register is not cleared at that time: it remains set. tip 5 . when starting countx (by setting ctrl_enable), this register should be set after countx is started with register ctrl_enable. 4.3 sgpio interrupt specific registers fo r these interrupt specific registers, replace the x with the correct number for the interrupt. 0 for shift clock; 1 for main register and shadow register exchange; 2 for data pattern match and 3 for input bit match. 4.3.1 clr_en_x this register is used to disable interrupts. slice interrupts can be disabled by writing a 1 to the register. for example, if a 1 is written to bit 2 the interrupt for slice c will be disabled. 4.3.2 set_en_x this register is used to enable interrupts. slice interrupts can be enabled by writing a 1 to the register. if, for example, a 1 is written to bit 3 the interrupt for slice d will be enabled. 4.3.3 enable_x reading out this register will return what slices have their interrupts enabled. if this register contains the value 0b1001 that means slice a and d have the interrupts enabled. 4.3.4 status_x reading out this register will return on which slices an interrupt has happened. it is possible that an interrupt happens on multiple slices at the same time. if this register contains the value 0b1000100 interrupts happened on slice c and g. 4.3.5 ctr_stat_x this register is used to clear the interrupt state. it is recommended to clear all interrupt states after handling the interrupts otherwise the value in the status_x register will also contain old interrupt states. 4.3.6 set_stat_x this register is used to set interrupt states. when a 1 is written to bit 0 it will look like an interrupt happened on slice a. this register can be used for code testing. 4.4 sgpio pin control registers these registers are used to control sgpio pin status. gpio_inreg, gpio_outreg and gpio_oenreg are sgpio pin based. this means that they control sgpio pins and not slices. if a 1 is written to bit 2 this will effect sgpio pin 2 and not slice c.
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 12 of 20 4.4.1 gpio_inreg with this register the sgpio pins can be made an input. when a 1 is written to bit 2 sgpio pin 2 will be an input. note: the sgpio pin must be made an input with the pinmux too. see chapter 15 of the user manual from the lpc4300 for more information about the pinmux. note: c oncatenate cannot be set to self loop when using an sgpio pin as input. 4.4.2 gpio_outreg with this register the sgpio pins can be made an output. when a 1 is written to bit 3 sgpio pin 3 will be an output. 4.4.3 gpio_oenreg with the gpio_oenreg register an sgpio output pin can be enabled. an sgpio pin must be enabled in order to work. when a 1 is written to bit 3 sgpio pin 3 will be enabled. to disable an sgpio pin a 0 has to be written to the corresponding bit. 5. steps to get sgpio working to get sgpio up and running : 1. select the right c lo ck 2. set up the registers, slices used, io pins used, concatenate slices, etc. 3. set up the interrupts 4. handle interrupts and data 5.1 selecting the right clock signal first the clock speed has to be selected. by default sgpio uses the irc, which runs at 12 mhz. other clock sources can be selected too; by selecting pll1 sgpio can run on the same clock speed as the lpc4300. in the pwm example the following line of code can be found in lpc43xx_cgu.c: irc: lpc_cgu - >base_periph_clk = (0x1 << 24); pll1: lpc_cgu - >bas e_periph_clk = (0 x9 << 24); for more information, see page 105 of the lpc4300 user manual . 5.2 set up the registers after knowing how many sgpio pins are going to be used , and how they will be used , the registers can be set up. the registers that need to be set up are out_mux_cfgx, sgpio_mux_cfgx, slice_mux_cfgx, presetx, countx, posx, regx and reg_ssx. the first three registers control most of the slice settings such as: number of slices concatenated, number of sgpio pins per slice, input or output, what clo ck is used etc. depending on the interrupts used to handle the data the interrupt registers must be set up too. also in the pinmux the io pins must be set up as sgpio pin and as input or output. to start sgpio the clock signals must be enabled . this is d one by setting bits 15 and 12 in the ctrl_enabled register. an example how to set up the sgpio registers for i2s use can be found in the user manual on page 376 to 379.
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 13 of 20 5.3 set up interrupts the interrupt description can be found in chapter 6 of this document. 5.4 handling data when everything is set up and sgpio is running the data still needs to be handled. what to do with the incoming and outgoing data is up to the user and depends on the application. when emulating a bus protocol like uart, spi or i2c the prot ocol itself has to be made by software. d ata arrives in 32 - bit blocks. uart uses 10 - bit blocks (start bit, 8- bit data, stop bit) and spi and i2c use 8- bit blocks. this translation has to be made in software and is different per bus protocol. when using sgpio to communicate with a camera module or some other parallel bus the same story applies. speeds over 40 mhz are doable and cpu load can be lowered by concatenating slices. when using 4 or 8- bit wide busses it is recommended to concatenate 2, 4 or 8 slice s for a larger buffer. if the buffer is 32 - bit and an 8- bit bus is used the buffer is full in just 4 sgpio clock cycles. when 8 slices are concatenated a 256 - bit buffer is created and it takes 32 sgpio clock cycles to fill this buffer, a much lower cpu loa d. 6. sgpio interrupts there are four interrupt methods available for sgpio, they are: 1. on shift clock 2. on data exchange clock 3. on data pattern match 4. on input bit match (rising/falling edge, high/low level) 6.1 on shift clock when enabled through set_en, this interrupt occur s every time countx equals 0. this normally happens every time 1 data bit is clocked out or in of a n sgpio slice and can be cpu intensive. the registers used for this interrupt are: ? clr_en_0 ? set_en_0 ? enable_0 ? status_0 ? ctr_status_0 ? set_status_0 6.2 on data exchange (swap) clock when enabled through set_en, this interrupt will occur every time the data between the data register (regx) and the shadow register (reg_ssx) is exchanged. this interrupt can be used to place new data in the shadow register, at the next exchange (and interrupt) the new data will be loaded in the data register and new data can be put in the shadow register. the registers used for this interrupt are: ? clr_en_1 ? set_en_1 ? enable_1
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 14 of 20 ? status_1 ? ctr_status_1 ? set_status_1 6.3 on data pattern match it is possible to interrupt when a certain pattern is clocked in or out. slices a, i, h and p also support mask functionality for the pattern match interrupt. the pattern match interrupt can be used to look for certain data when making a logic or data analyzer. to use this interrupt, bit 0 from register slice_mux_cfgx must be high. the pattern can be up to 32 - bit long and should program in reg_ss register. if the data in the data register matches the data in the shadow register an interrupt will happen. as long as this interrupt is enabled and bit 0 in slice_mux_cfgx is high the data register and shadow register will not swap. the registers used for this interrupt are: ? clr_en_2 ? set_en_2 ? enable_2 ? status_2 ? ctr_status_2 ? set_status_2 6.4 on input bit match wh en enabled through set_en, it is possible to interrupt on a low or high level or on a falling or rising edge on the input data bit. the registers used for this interrupt are: ? clr_en_3 ? set_en_3 ? enable_3 ? status_3 ? ctr_status_3 ? set_status_3 6.5 using interrupts u sing the interrupts is more or less the same for all 4. enabling/disabling the interrupts is done with the set_en and clr_en register. if, for example, bit 7 is high then the interrupt for slice h is enabled/disabled. reading out the interrupts is done via the status register. setting/clearing interrupts is done by writing to the set_stat and ctr_stat register. to handle an interrupt you have to find out what slice caused the interrupt, run the actual code and clear the interrupt. for example, a piece of code to handle a data exchange clock interrupts on slice p: void sgpio_irqhandler ( void) //handles all sgpio interrupts
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 15 of 20 { uint32_t tempvar = 0 ; //temp variable to store interrupts tempvar = lpc_sgpio -> status_1; //read data exchange interrupt register if( tempvar & 0x8000) //if a capture clock interrupt on the sgpio slice 15 happened... { //code to send new data or handle data should be placed here } lpc_sgpio -> ctr_status_1 = 0xffff; //clear the interrupts } 7. pwm e xample an example is provided that uses spgio to create pwm signals, a flowchart of this example can be found on the next page. every sgpio pin can be used as an extra pwm pin in this way. the duty cycle and frequency can be changed on the fly. as one slice has a 32 - bit fifo b uffer there are only 33 pwm duty cycles possible, so essentially it's a 5 - bit pwm that can be fully on or fully off. when concatenating slices a bigger precision can be reached but to make this example simple this is not implemented. a slice is used as o utput a nd the pwm data is loaded in the reg and reg_ss data registers. after that the slice only has to repeat the data in the reg register. when the pwm duty cycle is changed the value in the reg_ss register will be updated twice. this is because every 32 clock cycles the reg and reg_ss register is swapped. if the data is only written in the reg_ss register once only half of the time the pwm output would be correct and half of the time it would be the old value. when the command is executed to edit a pwm value the interrupts are switched on. when the next swap between reg and reg_ss occurs the new data is loaded into the reg_ss register. when another data swap occurs this happens again. after this the interrupts are switched off and the pwm duty cycle is changed. a flowchart of this can be found on the next page. as the example uses internal clock (count) and enables with oenreg and each pwm channel uses only one output slice, out_mux_cfg, slice_mux_cfg are 0. the data in the reg register has to be repeated so sgpio_mux_cfg bit 11 is set high. this means the slice is in self loop mode and will repeat the data in the reg register. the clock speed is dependent of what the user wants so it is calculated and then stored in the preset register. as we exchange the reg and reg_ss registers every 32 bit , the pos_preset is 0x1f. when the sgpio slice is set up as a pwm pin the frequency can be specified by the user. the code calculates the correct divider preset setting by the following formula. pwm frequency * 32 = sgp io_clock / (preset +1) note the ?* 32? in the above equation, this is because the pwm signal frequency is 32 times of the shift clock frequency.
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 16 of 20 fig 7. flowchart of the code when changing a pwm value
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 17 of 20 7.1 how to use the sgpio pwm library the sgpio pwm library has four commands: ? void sgpiopwminit( void); ? void sgpiopwmchaninit( uint32_t freq, uint8_t channel); ? void sgpiopwmvalue( uint8_t value, uint8_t channel); ? uint8_t sgpiopwmstatus(); sgpiopwminit initializes sgpio for pwm use. it disables all interrupts, makes all sgpio slices an output and enables all sgpio clocks. this command should be executed before the other commands are used. sgpiopwmchaninit is the command to initialize an sgpio slice for pwm use. it can also be used to change the pwm frequency at any moment but can cause a small hiccup in the pwm signal. ?freq? is the desired pwm frequency in hertz. the maximum frequency is the core clock divided by 64 (because the shift clock frequency is 32 times of the pwm frequency). as it uses a divider the actual speed will be an approximate of the given frequency. ?channel? is the sgpio slice that should be adjusted. this command has to be executed before the sgpiopwmvalue works. sgpiopwmvalue is use d to change the pwm duty cycle of any slice. as it is a 5 - bit pwm that can be fully on or off there are 33 values. 0 is a 0% duty cycle, 33 is a 100% duty cycle and 16 is ~47% duty cycle. channel is the sgpio slice that should be adjusted. after adjusting the duty cycle of a slice the command sgpiopwmstatus can be used to check if the adjusting is done so another slice can be adjusted. if it returns 0 adjusting is done and the sgpiopwmvalue can be used again. before an io pin can be used as sgpio pin the co rrect setup has to be loaded in the pinmux. the settings possible per io pin can be found in chapter 14, lpc43xx pin configuration in the user manual. for example, to use p0_0 as sgpio pin function 3 (sgpio0) has to be selected. the correct command for thi s is: scu_pinmux( 0x0, 0 , md_pln, func3); the example code uses p1.1, p2.6 and p2.8 to show some effects on a rgb led. to see this effect a common anode rgb led should be connected to p1.1, p2.6 and p2.8.
nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 18 of 20 8. conclusion sgpio is a very flexible peripheral that can be used to emulate a lot of serial and parallel busses, but can also be used to generate signals or to read in signals. nxp provides examples for emulating i2c, spi and generating pwm signals. with these examples it will be easier to get started with sgpio and use it for a custom application or to solve a shortage of peripherals. because it is possible to emulate peripherals on a lot of io ports this can make pcb design easier and make the lpc43xx more flexible for power creeps where in other cases a new microcontroller would have been necessary. combined with other new peripherals like the state configurable timer, spifi flash and the m0 coprocessor it makes the lpc43xx a flexible and powerful microcontroller that is easy to work with.
propert y name. error! unknown document property name. error! unknown document property nxp semiconductors AN11275 sgpio on the lpc4300 AN11275 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012 . all rights reserved. application note rev. 1 ? 7 november 2012 19 of 20 9. legal information 9.1 definitions draft ? the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such i nformation. 9.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or complete ness of such information and shall have no liability for the consequences of use of such information. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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nxp semiconductors AN11275 sgpio on the lpc4300 please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'legal information'. ? nxp b.v. 2012 . all rights reserved. for more information, visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 7 november 2012 document identifier: AN11275 10. contents 1. introduction ......................................................... 3 2. what is sgpio? ................................................... 4 3. sgpio usage ........................................................ 6 4. register descri ptions .......................................... 6 4.1 slice/sgpio pin multiplexing registers ............... 6 4.1.1 out_mux_cfgx .............................................. 6 4.1.2 sgpio_mux_cfgx .......................................... 8 4.1.3 slice_mux_cfgx ........................................... 9 4.2 slice operation control registers ....................... 10 4.2.1 regx ............................................................... 10 4.2.2 reg_ssx ......................................................... 10 4.2.3 presetx ......................................................... 10 4.2.4 posx ................................................................ 10 4.2.5 mask_a, mask_h, mask_i, mask_p .......... 10 4.2.6 ctrl_enable ................................................ 11 4.2.7 ctrl_disable ............................................... 11 4.3 sgpio interrupt specific registers .................... 11 4.3.1 clr_en_x ....................................................... 11 4.3.2 set_en_x ....................................................... 11 4.3.3 enable_x ....................................................... 11 4.3.4 status_x ....................................................... 11 4.3.5 ctr_stat_x ................................................... 11 4.3.6 set_stat_x ................................................... 11 4.4 sgpio pin co ntrol registers .............................. 11 4.4.1 gpio_inreg ................................................... 12 4.4.2 gpio_outreg ............................................... 12 4.4.3 gpio_oenreg ............................................... 12 5. steps to get sgpio working ............................. 12 5. 1 selecting the right clock signal ......................... 12 5.2 set up the registers .......................................... 12 5.3 set up interrupts ............................................... 13 5.4 handling data ................................................... 13 6. sgpio inter rupts ............................................... 13 6.1 on shift clock .................................................... 13 6.2 on data exchange (swap) clock ....................... 13 6.3 on data pattern match ..................................... 14 6.4 on input bit match ............................................ 14 6.5 using interrupts ................................................ 14 7. pwm example .................................................... 15 7.1 how to use the sgpio pwm library ................ 17 8. conclusion ......................................................... 18 9. legal informati on .............................................. 19 9.1 definitions ........................................................ 19 9.2 disclaimers ....................................................... 19 9.3 trademarks ...................................................... 19 10. contents ............................................................. 20

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