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rev 1.0 data sheet no. pd60336 IRMCK371 sensorless motor control ic for appliances features ? mce tm (motion control engine) - hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet ac motor ? support induction motor sensorless foc control ? supports both interior and surface permanent magnet motors ? built-in hardware peripheral for single shunt current feedback reconstruction ? no external current or voltage sensing operational amplifier required ? three/two-phase space vector pwm ? analog output (pwm) ? embedded 8-bit high speed microcontroller (8051) for flexible i/o and man-machine control ? jtag programming port for emulation/debugger ? serial communication interface (uart) ? i 2 c/spi serial interface ? watchdog timer with independent analog clock ? three general purpose timers/counters ? two special timers: periodi c timer, capture timer ? internal ?one-time progr ammable? (otp) memory and internal ram for final production usage ? pin compatible with irmcf371, ram version ? 1.8v/3.3v cmos product summary maximum crystal frequency 60 mhz maximum internal clock (sysclk) frequency 128 mhz maximum 8051 clock frequency 33 mhz sensorless control computation time 11 sec typ mce tm computation data range 16 bit signed 8051 otp program memory 64k bytes mce program and data ram 8k bytes gatekill latency (digital filtered) 2 sec pwm carrier frequency counter 16 bits/ sysclk a/d input channels 4 a/d converter resolution 12 bits a/d converter conversion speed 2 sec 8051 instruction execution speed 2 sysclk analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6k bps number of i/o (max) 13 package (lead-free) qfp48 operating temperature -40c ~ 85c description IRMCK371 is a high performance otp based motion control ic designed primarily for appliance applications. IRMCK371 is designed to achieve low cost and high per formance control solutions for advanced inverterized appliance motor control. IRMCK371 contains two computation engi nes. one is motion control engine (mce tm ) for sensorless control of permanent magnet motors; the other is an 8-bit hi gh-speed microcontroller (8051). both com putation engines are integrated into one monolithic chip. the mce tm contains a collection of control elements such as proportional plus integral, vector rotator, angle estimator, multiply/divide, low loss svpwm, single shunt ifb. t he user can program a moti on control algorithm by connecting these control elements using a graphic compiler. key components of the sensorless control algor ithms, such as the angle estimator, are provided as comple te pre-defined control blocks implemented in hardware. a unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. the 8051 microcontroller performs 2-cycle instruction execution (16mi ps at 33mhz). the mce and 8051 microcontroller are connected via dual port ram to process signal monitoring and command input. an advanced graphic compiler for the mce tm is seamlessly integrated into the matlab/simulink environment, while third party jtag bas ed emulator tools are s upported for 8051 developments. IRMCK371 comes with a small qfp48 pin lead-free package..
IRMCK371 www.irf.com ? 2007 international rectifier 2 table of contents 1 overview ....................................................................................................................... ............. 5 2 IRMCK371 block diagram and main functions......................................................................... 6 3 pinout......................................................................................................................... ................ 8 4 input/output of IRMCK371....................................................................................................... .. 9 4.1 8051 peripheral interface group ....................................................................................... 10 4.2 motion peripheral interface group .................................................................................... 10 4.3 analog interface group ..................................................................................................... 11 4.4 power interface group ...................................................................................................... 11 4.5 test interface group ......................................................................................................... 11 5 application connections ........................................................................................................ .. 12 6 dc characteristics ............................................................................................................. ...... 13 6.1 absolute maximum ratings............................................................................................... 13 6.2 system clock frequency and power consumption .......................................................... 13 6.3 digital i/o dc characteristics............................................................................................ 14 6.4 pll and oscillator dc characteristics............................................................................... 14 6.5 analog i/o dc characteristics .......................................................................................... 15 6.6 under voltage lockout dc characteristics........................................................................ 15 6.7 aref characteristics ........................................................................................................ 15 7 ac characteristics ............................................................................................................. ...... 16 7.1 pll ac characteristics ..................................................................................................... 16 7.2 analog to digital converter ac characteristics................................................................. 17 7.3 op amp ac characteristics .............................................................................................. 17 7.4 sync to svpwm and a/d conversion ac timing ........................................................... 18 7.5 gatekill to svpwm ac timing ..................................................................................... 19 7.6 interrupt ac timing ........................................................................................................... 19 7.7 i 2 c ac timing.................................................................................................................... 20 7.8 spi ac timing.................................................................................................................. . 21 7.8.1 spi write ac timing .................................................................................................... 21 7.8.2 spi read ac timing................................................................................................... 22 7.9 uart ac timing............................................................................................................... 23 7.10 capture input ac timing ........................................................................................... 24 7.11 jtag ac timing ............................................................................................................ 25 7.12 otp programming timing ............................................................................................. 26 8 i/o structure.................................................................................................................. ........... 27 9 pin list ....................................................................................................................... .............. 30 10 package dimensions ............................................................................................................ 32 11 part marking information ...................................................................................................... 33 12 order information .............................................................................................................. ... 33
IRMCK371 www.irf.com ? 2007 international rectifier 3 table of figures figure 1. typical application block diagram using IRMCK371..................................................... 5 figure 2. IRMCK371 internal block diagram................................................................................. 6 figure 3. IRMCK371 pin configuration.......................................................................................... 8 figure 4. input/output of IRMCK371 ............................................................................................ . 9 figure 5. application connection of IRMCK371 .......................................................................... 12 figure 6. clock frequency vs. power consumption.................................................................... 13 figure 7 crystal oscillator circuit........................................................................................... ....... 16 figure 8 voltage droop of sample and hold................................................................................. 17 figure 9 sync to svpwm and a/d conversion ac timing ....................................................... 18 figure 10 gatekill to svpwm ac timing ............................................................................... 19 figure 11 interrupt ac timing ................................................................................................. .... 19 figure 12 i 2 c ac timing .............................................................................................................. 20 figure 13 spi write ac timing................................................................................................. .... 21 figure 14 spi read ac timing .................................................................................................. ... 22 figure 15 uart ac timing ...................................................................................................... ... 23 figure 16 capture input ac timing......................................................................................... 24 figure 17 jtag ac timing...................................................................................................... .... 25 figure 18 otp programming timing ........................................................................................... 26 figure 19 all digital i/o except motor pwm output......................................................................... 27 figure 20 reset, gatekill i/o .................................................................................................. 27 figure 21 analog input ......................................................................................................... .......... 28 figure 22 analog operational amplifier output and aref i/o structure....................................... 28 figure 23 vpp programming pin i/o structure .......................................................................... 28 figure 24 vss, avss and pllvss pin structure .......................................................................... 29 figure 25 vdd1, vdd2, avdd and pllvdd pin structure ........................................................... 29 figure 26 xtal0/xtal1 pins structure ....................................................................................... 29
IRMCK371 www.irf.com ? 2007 international rectifier 4 table of tables table 1. absolute maximum ratings ........................................................................................... 13 table 2. system clock frequency ............................................................................................... 13 table 3. digital i/o dc characteristics ....................................................................................... . 14 table 4. pll dc characteristics ............................................................................................... .. 14 table 5. analog i/o dc characteristics ....................................................................................... 15 table 6. uvcc dc characteristics .............................................................................................. . 15 table 7. aref dc characteristics .............................................................................................. 15 table 8. pll ac characteristics............................................................................................... ... 16 table 9. a/d converter ac characteristics ................................................................................. 17 table 10. current sensing op amp amp ac characteristics...................................................... 17 table 11. sync ac characteristics ............................................................................................ 18 table 12. gatekill to svpwm ac timing ............................................................................... 19 table 13. interrupt ac timing................................................................................................. ..... 19 table 14. i 2 c ac timing .............................................................................................................. 20 table 15. spi write ac timing ................................................................................................. ... 21 table 16. spi read ac timing.................................................................................................. .. 22 table 17. uart ac timing ...................................................................................................... ... 23 table 18. capture ac timing .................................................................................................. 24 table 19. jtag ac timing ...................................................................................................... .... 25 table 20. otp programming timing ........................................................................................... 26 table 21. pin list ............................................................................................................ ............. 31
IRMCK371 www.irf.com ? 2007 international rectifier 5 1 overview IRMCK371 is a new international rectifier int egrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance motor control applications. unlike a traditional microcontroller or dsp, the IRMCK371 provides a built-in closed loop sensorless control algorithm using the unique motion control engine (mce tm ) for permanent magnet motors. the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. IRMCK371 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the ic. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulink tm development environment. sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application schematic using the IRMCK371. irmcf371 is intended for development purpose and contains 48k bytes of ram, which can be loaded from external eeprom for 8051 program execution. for high volume production, IRMCK371 contains otp rom in place of program ram to reduce the cost. both IRMCK371 and IRMCK371 come in the same 48-pin qfp package with identical pin configuration to facilitate pc board layout and transition to mass production figure 1. typical application block diagram using IRMCK371
IRMCK371 www.irf.com ? 2007 international rectifier 6 2 IRMCK371 block diagram and main functions IRMCK371 block diagram is shown in figure 2. 8bit up address/data bus motion control bus figure 2. IRMCK371 internal block diagram IRMCK371 contains the following functions for sensorless ac motor control applications: ? motion control engine (mce tm ) o proportional plus integral block o low pass filter o differentiator and lag (high pass filter) o ramp o limit o angle estimate (sensorless control) o inverse clark transformation o vector rotator o bit latch o peak detect o transition o multiply-divide (signed and unsigned)
IRMCK371 www.irf.com ? 2007 international rectifier 7 o divide (signed and unsigned) o adder o subtractor o comparator o counter o accumulator o switch o shift o atan (arc tangent) o function block (any curve fitting, nonlinear function) o 16-bit wide logic operations (and, or, xor, not, negate) o mce tm program and data memory (6k byte). note 1 o mce tm control sequencer ? 8051 microcontroller o three 16-bit timer/counters o 16-bit periodic timer o 16-bit analog watchdog timer o 16-bit capture timer o up to 13 discrete i/os o four-channel 12-bit a/d ? one buffered channel for current sensing (0 ? 1.2v input) ? three unbuffered channels (0 ? 1.2v input) o jtag port (4 pins) o one channel of analog output (8-bit pwm) o uart o i 2 c/spi port o 64k byte program otp o 2k byte data ram. note 1 note 1: total size of ram is 8k byte including mce program, mce data, and 8051 data. different sizes can be allocated depending on applications.
IRMCK371 www.irf.com ? 2007 international rectifier 8 3 pinout 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 15 14 16 3 12 4 11 5 6 7 8 9 10 2 1 xtal0 xtal1 p1.1/rxd p1.2/txd vdd1 vss vdd2 p1.3/sync/sck p1.4/cap p2.1 34 35 36 33 46 37 45 38 44 43 42 41 40 39 47 48 vss vdd2 avdd avss ain0 aref p2.6/aopwm pwmuh pwmvh pwmwh pwmul pwmvl pwmwl gatekill vdd1 vss ifbo ifb+ ifb- pllvss pllvdd reset nc tck p5.3/tdi p5.2/tdo p5.1/tms sda/cs0 scl/so-si/vpp vss (top view) ain2 cmext p2.0/nmi ain1 p3.2/int0 p1.0/t2 p3.0/int2/cs1 13 vdd2 figure 3. IRMCK371 pin configuration
IRMCK371 www.irf.com ? 2007 international rectifier 9 4 input/output of IRMCK371 all i/o signals of IRMCK371 are shown in figure 4. all i/o pins are 3.3v logic interface except a/d interface pins. p1.2/txd p1.1/rxd p5.3/tdi tck p5.1/tsm pwmuh pwmul pwmvh pwmvl pwmwh pwmwl gatekill ifb+ ifb- ifbo ain0 ain1 pwm gate signal interface a/d interface discrete i/o jtag port p5.2/tdo rs232c interface xtal0 xtal1 crystal p2.6/aopwm d/a interface (pwm output) reset system reset ain2 avdd avss aref cmext vdd1 vdd2 vss digital power/ ground pllvdd pllvss pll power/ ground p1.3/sync/sck p1.4/cap p3.0/int2/cs1 scl/so-s/vppi sda/cs0 p1.0/t2 p2.1 p2.0/nmi p3.2/int0 i2c interface scl/so-s/vppi otp programming figure 4. input/output of IRMCK371
rev 1.0 4.1 8051 peripheral interface group uart interface p1.2/txd output, transmit data from IRMCK371, can be configured as p1.2 p1.1/rxd input, receive data to IRMCK371, can be configured as p1.1 discrete i/o interface p1.0/t2 input/output port 1.0, can be configured as timer 2 input p1.1/rxd input/output port 1.1, can be configured as rxd input p1.2/txd input/output port 1.2, can be configured as txd output p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock p1.4/cap input/output port 1.4, can be configured as capture timer input p2.0/nmi input/output port 2.0, can be configured as non-maskable interrupt input p2.1 input/output port 2.1 p3.0/int2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1 p3.2/int0 input/output port 3.2, can be configured as int0 input analog output interface aopwm output, pwm output 0, 8-bit resolution, configurable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset inout, system reset, needs to be pulled up to vdd1 but doesn?t require external rc time constant i 2 c/spi interface scl/so-si input/output, i 2 c clock output or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 p3.0/int2/cs1 input/output, int2 or spi chip select 1 p1.3/sync/sck input/output, sync output or spi clock, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom 4.2 motion peripheral interface group pwm pwmuh output, pwm phase u high side gate signal pwmul output, pwm phase u low side gate signal pwmvh output, pwm phase v high side gate signal pwmvl output, pwm phase v low side gate signal pwmwh output, pwm phase w high side gate signal pwmwl output, pwm phase w low side gate signal fault gatekill input, upon assertion, this negates all six pwm signals, programmable logic sense
IRMCK371 www.irf.com ? 2007 international rectifier 11 4.3 analog interface group avdd analog power (1.8v) avss analog power return aref 0.6v buffered output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected. ifb+ input, operational amplifier positive input for shunt resistor current sensing ifb- input, operational amplifier negative input for shunt resistor current sensing ifbo output, operational amplifier output for shunt resistor current sensing ain0 input, analog input channel 0 (0 ? 1.2v), typically configured for dc bus voltage input ain1 input, analog input channel 1 (0 ? 1.2v), needs to be pulled down to avss if unused ain2 input, analog input channel 2 (0 ? 1.2v), needs to be pulled down to avss if unused 4.4 power interface group vdd1 digital power for i/o (3.3v) vdd2 digital power for core logic (1.8v) vss digital common pllvdd pll power (1.8v) pllvss pll ground return 4.5 test interface group tstmod must be tied to vss, used only for factory testing. p5.1/tsm input/output port 5.1, configured as jtag port by default p5.2/tdo input/output port 5.2, configured as jtag port by default p5.3/tdi input/output port 5.3, configured as jtag port by default tck input, jtag test clock
IRMCK371 www.irf.com ? 2007 international rectifier 12 5 application connections typical application connection is shown in figure 5. all components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCK371. p1.2/txd p1.1/rxd p1.3/sync/sck xtal0 pwmuh pwmul pwmvh pwmvl pwmwh pwmwl gatekill host microcontroller (rs232c) digital i/o control system clock 4mhz crystal motor dc bus shunt resistor p2.6/aopwm0 analog output xtal1 p1.4/cap p3.0/int2/cs1 reset p5.3/tdi jtag control tclk p5.1/tsm p5.2/tdo 0.6v ifbc+ ifbc- ifbco other analog input (0-1.2v) avdd 1.8v avss vdd1 3.3v vdd2 1.8v vss cmext dc bus voltage optional external voltage reference (0.6v) pllvdd 1.8v pllvss scl/so-si sda/cs0 other communication (i 2 c or spi) pll logic rs232c i 2 c/spi port1 port2 reset pwm0 jtag interface low loss space vector pwm s/h 8051 cpu dual port memory (1kbyte) & mce memory (3kbyte) motion control modules motion control sequencer 12bit a/d & mux system clock local ram 4kbyte program otp rom (64kbyte) system reset watchdog timer timers aref port3 p1.0/t2 p2.1 p2.0/nmi p3.2/int0 port 5 ain0 ain1 ain2 scl/so-si otp programming 6.5v clock divider system clock power figure 5. application connection of IRMCK371
IRMCK371 www.irf.com ? 2007 international rectifier 13 6 dc characteristics 6.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage -0.3 v - 3.6 v respect to vss v dd2 supply voltage -0.3 v - 1.98 v respect to vss v ia analog input voltage -0.3 v - 1.98 v respect to avss v id digital input voltage -0.3 v - 3.65 v respect to vss t a ambient temperature -40 ? c - 85 ? c t s storage temperature -65 ? c - 150 ? c table 1. absolute maximum ratings caution: stresses beyond those listed in ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 6.2 system clock frequency and power consumption symbol parameter min typ max unit sysclk system clock 32 - 128 mhz 8051clk 8051 clock - - 32 mhz table 2. system clock frequency figure 6. clock frequency vs. power consumption power consumption 0 20 40 60 80 100 120 140 160 180 0 20406080100120140 mce frequency (mhz) power (mw) 1.8v 3.3v total power
IRMCK371 www.irf.com ? 2007 international rectifier 14 6.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v dd2 supply voltage 1.62 v 1.8 v 1.98 v recommended v il input low voltage -0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 3. digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so-si, sda/cs0 pins. (3) applied to p1.0/t2, p1.1/rxd, p1.2/txd, p1.3/sync/sck, p1.4/cap, p2.0/nmi, p2.1, p2.6/aopwm0, p3.0/int2/cs1, p3.2/int0, p5.1/tms, p5.2/tdo, p5.3/tdi, gatekill, pwmul, pwmuh, pwmvl, pwmvh, pwmwl, pwmwh pins. 6.4 pll and oscillator dc characteristics symbol parameter min typ max condition v pllvdd supply voltage 1.62 v 1.8 v 1.92 v recommended v il osc oscillator input low voltage v pllvss - 0.2* v pllvdd v pllvdd = 1.8 v (1) v ih osc oscillator input high voltage 0.8* v pllvdd v pllvdd v pllvdd = 1.8 v (1) table 4. pll dc characteristics note: (1) data guaranteed by design.
IRMCK371 www.irf.com ? 2007 international rectifier 15 6.5 analog i/o dc characteristics - op amp for current sensing (ifb+, ifb-, ifbo) c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v avdd supply voltage 1.71 v 1.8 v 1.89 v recommended v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k - 20 k requested between ifbo and ifb- op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 5. analog i/o dc characteristics note: (1) data guaranteed by design. 6.6 under voltage lockout dc characteristics unless specified, ta = 25 ? c, avdd (1.8v) symbol parameter min typ max condition uv cc+ uvcc positive going threshold 1) 1.53 v 1.66 v 1.71 v v dd1 = 3.3 v uv cc- uvcc negative going threshold 1.52 v 1.62 v 1.71 v v dd1 = 3.3 v uv cc h uvcc hysteresys - 40 mv - table 6. uvcc dc characteristics note: (1) data guaranteed by design. 6.7 aref characteristics c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v aref aref output voltage 495 mv 600 mv 700 mv v avdd = 1.8 v v o load regulation (v dc -0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 7. aref dc characteristics note: (1) data guaranteed by design.
IRMCK371 www.irf.com ? 2007 international rectifier 16 7 ac characteristics 7.1 pll ac characteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 8. pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m r 2 =10 c 1 =30pf c 2 =30pf figure 7 crystal oscillator circuit
IRMCK371 www.irf.com ? 2007 international rectifier 17 7.2 analog to digital converter ac characteristics unless specified, ta = 25 ? c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 9. a/d converter ac characteristics note: (1) data guaranteed by design. t hold voltage droop t sample s/h voltage input voltage figure 8 voltage droop of sample and hold 7.3 op amp ac characteristics - op amps for current sensing (ifb+, ifb-, ifbo) unless specified, ta = 25 ? c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/ sec - v avdd = 1.8 v, cl = 33 pf (1) op imp op input impedance - 10 8 ? - (1) t set settling time - 400 ns - v avdd = 1.8 v, cl = 33 pf (1) table 10. current sensing op amp amp ac characteristics note: (1) data guaranteed by design.
IRMCK371 www.irf.com ? 2007 international rectifier 18 7.4 sync to svpwm and a/d conversion ac timing sync iu,iv,iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 figure 9 sync to svpwm and a/d conversion ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0-6 analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 11. sync ac characteristics note: (1) ain1 through ain6 channels are converted once every 6 sync events
IRMCK371 www.irf.com ? 2007 international rectifier 19 7.5 gatekill to svpwm ac timing figure 10 gatekill to svpwm ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 12. gatekill to svpwm ac timing 7.6 interrupt ac timing figure 11 interrupt ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wint int0, int1 interrupt assertion time 4 - - sysclk t dint int0, int1 latency - - 4 sysclk table 13. interrupt ac timing
IRMCK371 www.irf.com ? 2007 international rectifier 20 7.7 i 2 c ac timing scl sda t i2st1 t i2st2 t i2wsetup t i2clk t i2whold t i2rsetup t i2rhold t i2clk t i2en1 t i2en2 figure 12 i 2 c ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 14. i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication.
IRMCK371 www.irf.com ? 2007 international rectifier 21 7.8 spi ac timing 7.8.1 spi write ac timing figure 13 spi write ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 15. spi write ac timing
IRMCK371 www.irf.com ? 2007 international rectifier 22 7.8.2 spi read ac timing figure 14 spi read ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 16. spi read ac timing
IRMCK371 www.irf.com ? 2007 international rectifier 23 7.9 uart ac timing txd rxd data and parity bit start bit t baud stop bit t uartfil figure 15 uart ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 17. uart ac timing note: (1) each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated.
IRMCK371 www.irf.com ? 2007 international rectifier 24 7.10 capture input ac timing figure 16 capture input ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 18. capture ac timing
IRMCK371 www.irf.com ? 2007 international rectifier 25 7.11 jtag ac timing tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms figure 17 jtag ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 19. jtag ac timing
rev 1.0 7.12 otp programming timing figure 18 otp programming timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t vps vpp setup time 10 - - nsec t vph vpp hold time 15 - - nsec table 20. otp programming timing
IRMCK371 www.irf.com ? 2007 international rectifier 27 8 i/o structure the following figure shows the motor pwm and digital i/o structure 100 6.0v 6.0v internal digital circuit low true logic vdd1 (3.3v) 70k pin vss figure 19 all digital i/o except motor pwm output the following figure shows reset and gatekill i/o structure. 100 6.0v 6.0v reset gatekill i/o vdd1 (3.3v) 70k pin vss figure 20 reset, gatekill i/o
IRMCK371 www.irf.com ? 2007 international rectifier 28 the following figure shows the analog input structure. 100 6.0v 6.0v analog input pin avss analog circuit avdd figure 21 analog input the following figure shows all analog operational amplifier output pins and aref pin i/o structure. 6.0v 6.0v analog output pin avss analog circuit 1.8v figure 22 analog operational amplifier output and aref i/o structure the following figure shows the vpp pin i/o structure 100 8.0v vpp input pin vss analog circuit figure 23 vpp programming pin i/o structure
rev 1.0 the following figure shows the vss, avss and pllvss pin structure figure 24 vss, avss and pllvss pin structure the following figure shows the vdd1, vdd2, avdd and pllvdd pin structure figure 25 vdd1, vdd2, avdd and pllvdd pin structure the following figure shows the xtal0 and xtal1 pins structure 6.0v 6.0v pin vdd1 vss figure 26 xtal0/xtal1 pins structure
IRMCK371 www.irf.com ? 2007 international rectifier 30 9 pin list pin number pin name internal pull-up /pull-down pin type description 1 xtal0 i crystal input 2 xtal1 o crystal output 3 p1.0/t2 i/o discrete programmable i/o or timer/counter 2 input 4 p1.1/rxd i/o discrete programmable i/o or uart receive input 5 p1.2/txd i/o discrete programmable i/o or uart transmit output 6 p1.3/sync/ sck i/o discrete programmable i/o or sync output or spi clock output 7 p1.4/cap i/o discrete programmable i/o or capture timer input 8 vdd2 p 1.8v digital power 9 vss p digital common 10 vdd1 p 3.3v digital power 11 p2.0/nmi i/o discrete i/o or non maskable interrupt 12 p2.1 i/o discrete i/o 13 p2.6/aopw m i/o discrete i/o or pwm digital output 14 vdd2 p 1.8v digital power 15 vss p digital common 16 ain0 i analog input channel 0, 0-1.2v range, needs to be pulled down to avss if unused 17 avdd p 1.8v analog power 18 avss p analog common 19 ain1 i analog input channel 1, 0-1.2v range, needs to be pulled down to avss if unused 20 cmext o unbuffered 0.6v output. capacitor needs to be connected. 21 aref o analog reference voltage output (0.6v) 22 ifb- i single shunt current sensing op amp input (-) 23 ifb+ i single shunt current sensing op amp input (+) 24 ifbo o single shunt current sensing op amp output 25 ain2 i analog input channel 2, 0-1.2v range, needs to be pulled down to avss if unused 26 vdd2 p 1.8v digital power 27 vss p digital common 28 vdd1 p 3.3v digital power 29 gatekill i pwm shutdown input, 2- sec digital filter, configurable either high or low true. 30 pwmwl 70 k ? pull up o pwm gate drive for phase w low side, configurable either high or low true 31 pwmwh 70 k ? pull up o pwm gate drive for phase w high side, configurable either high or low true
IRMCK371 www.irf.com ? 2007 international rectifier 31 pin number pin name internal pull-up /pull-down pin type description 32 pwmvl 70 k ? pull up o pwm gate drive for phase v low side, configurable either high or low true 33 pwmvh 70 k ? pull up o pwm gate drive for phase v high side, configurable either high or low true 34 pwmul 70 k ? pull up o pwm gate drive for phase u low side, configurable either high or low true 35 pwmuh 70 k ? pull up o pwm gate drive for phase u high side, configurable either high or low true 36 p3.0/int2/c s1 i/o discrete programmable i/o or external interrupt 2 input or spi chip select 1 37 p3.2/nint0 i/o discrete programmable i/o or external interrupt 0 input 38 vss p digital common 39 scl/so-si i/o i2c clock or spi data 40 sda/cs0 i/o i2c data or spi chip select 0 41 p5.1/tms i/o discrete i/o or jtag test mode select 42 p5.2/tdo i/o discrete i/o or jtag test data output 43 p5.3/tdi i/o discrete i/o or jtag test data input 44 tck i jtag test clock input 45 tstmod 58 k ? pull down i test mode input, must be tied to vss 46 reset i/o reset, low true, schmitt trigger input 47 pllvdd p 1.8v pll power 48 pllvss p pll ground table 21. pin list
IRMCK371 www.irf.com ? 2007 international rectifier 32 10 package dimensions
IRMCK371 www.irf.com ? 2007 international rectifier 33 11 part marking information 12 order information lead-free part in 48-lead qfp moisture sensitivity rating ? msl3 part number order quantities IRMCK371tr 2000 parts on tape and reel in dry pack IRMCK371ty 2500 parts on trays (160 parts per tray) in dry pack the lqfp-48 is msl3 qualified this product has been designed and qualified for the industrial level qualification standards can be found at www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252-7105 data and specifications subject to change wi thout notic e. 12/25/2007 www.irf.com

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