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ds04-21364-3e fujitsu semiconductor data sheet assp dual s erial input pll frequency synthesizer mb15f78sp n description the fujitsu mb15f78sp is a serial input phase locked loop (pll) frequency synthesizer with a 2550 mhz pres- caler and a 1200 mhz prescaler. a 32/33 or a 64/65 for the 2550 mhz prescaler, and a 16/17 or a 32/33 for the 1200 mhz prescaler can be selected for the prescaler that enables pulse swallow operation. the bicmos process is used , as a result a supply current is typically 5.5 ma at 2.7 v. the supply voltage range is from 2.4 v to 3.6 v. a refined charge pump supplies well-balanced output current with 1.5 ma and 6 ma select- able by serial data. the new package (bcc20) decreases an area of mb15f78sp more than 30 % comparing with the former bcc16 (for dual pll). mb15f78sp is ideally suited for wireless mobile communications, such as gsm. n features ? high frequency operatio : rx synthesizer : 2550 mhz max : tx synthesizer : 1200 mhz max ? low power supply voltage : v cc = 2.4 to 3.6 v ? ultra low power supply current : i cc = 5.5 ma typ. (v cc = vp = 2.7 v, ta = +25 c, sw tx = sw rx = 0, in tx/rx locking state) ? direct power saving function : power supply current in power saving mode ty p . 0 . 1 m a (v cc = vp = 2.7 v, ta = +25 c), max. 10 m a (v cc = vp = 2.7 v) ? software selectable charge pump current: 1.5 ma/6.0 ma typ. (continued) n packages 20-pin plastic tssop (fpt-20p-m06) 20-pad plastic bcc (lcc-20p-m04)
mb15f78sp 2 (continued) ? dual modulus prescaler : 2550 mhz prescaler (32/33 or 64/65 )/1200 mhz prescaler (16/17 or 32/33) ? 23-bit shift register ? serial input binary 14-bit programmable reference divider : r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 7-bit swallow counter : 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 ? built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit ? onCchip phase control for phase comparator ? built-in digital locking detector circuit to detect pll locking and unlocking ? operating temperature : ta = C40 to +85 c ? sireal data format compatible with mb15f08sl n n n n pin assignments osc in gnd fin tx xfin tx gnd tx v cctx ps tx vp tx do tx ld/fout clock data le fin rx xfin rx gnd rx v ccrx ps rx vp rx do rx 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd do tx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 19 18 17 20 gnd tx v cctx vp tx fin tx ps tx gnd rx le fin rx v ccrx ps rx xfin rx xfin tx osc in ld/fout do rx vp rx data clock (tssop-20) top view (bcc-20) top view (fpt-20p-m06) (lcc-20p-m04)
mb15f78sp 3 n n n n pin description pin no. pin name i/o descriptions tssop bcc 119osc in i the programmable reference divider input. tcx0 should be connected with a ac coupling capacitor. 220gnd ? ground for osc input buffer and the shift register circuit. 31fin tx i prescaler input pin for the tx-pll. connection to an external vco should be via ac coupling. 42xfin tx i prescaler complimentary input pin for the tx-pll section. this pin should be grounded via a capacitor. 53gnd tx ? ground for the tx-pll section. 64v cctx ? power supply voltage input pin for the tx-pll section(except for the charge pump circuit), the oscillator input buffer and the shift register. 75ps tx i power saving mode control for the tx-pll section. this pin must be set at l power-on. (open is prohibited.) ps tx = h ; normal mode / ps tx = l ; power saving mode 86vp tx ? power supply voltage input pin for the tx-pll charge pump. 97d otx o charge pump output for the tx-pll section. 10 8 ld/fout o lock detect signal output (ld)/phase comparator monitoring output (fout).the output signal is selected by lds bit in the serial data. lds bit = h ; outputs fout signal / lds bit = l ; outputs ld signal 11 9 d orx o charge pump output for the rx-pll section. 12 10 vp rx ? power supply voltage input pin for the rx-pll charge pump. 13 11 ps rx i power saving mode control for the rx-pll section. this pin must be set at l power-on. (open is prohibited.) ps rx = h ; normal mode / ps rx = l ; power saving mode 14 12 v ccrx ? power supply voltage input pin for the rx-pll section(except for the charge pump circuit). 15 13 gnd rx ? ground for the rx-pll section. 16 14 xfin rx i prescaler complimentary input pin for the rx-pll section. this pin should be grounded via a capacitor. 17 15 fin rx i prescaler input pin for the rx-pll. connection to an external vco should be via ac coupling. 18 16 le i load enable signal input(with the schmitt trigger circuit). when le is set h, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 17 data i serial data input(with the schmitt trigger circuit). a data is transferred to the corresponding latch(tx-ref. counter, tx-prog. counter, rx-ref.counter, rx-prog.counter) according to the control bit in a serial data. 20 18 clock i clock input for the 23-bit shift register (with a schmitt trigger circuit). one bit of data is shifted into the shift register on a rising edge of the clock.
mb15f78sp 4 n n n n block diagram ( ) clock data le ps rx xfin rx fin rx osc in fin tx ps tx fc tx sw tx lds v cctx gnd tx fp tx do tx ld tx t1 t2 t1 t2 fc rx sw rx lds do rx or ld / fout ld fr tx fr rx fp tx fp rx fr tx fr rx fp rx c n 1 c n 2 and v ccrx gnd rx vp rx ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 6 4 53 9 7 10 8 11 9 15 12 13 gnd ( ) 2 20 10 14 12 20 18 19 17 ( ) 18 16 13 11 16 14 17 15 1 19 3 1 xfin tx ( ) 4 2 7 5 vp tx ( ) 86 o : tssop ( ) : bcc i ntermittent mode control (tx-pll) prescaler (tx-pll) (16/17, 32/33) schmitt circuit 3 bit latch 7 bit latch 11 bit latch binary 7-bit swallowcounter tx-pll) binary 11-bit pro- grammable counter(tx-pll) phase comp. (tx-pll) charge pump (tx-pll). current switch lock det. (tx-pll) 2 bit latch 14 bit latch 1 bit latch binary 14-bit pro- grammable ref. counter(tx-pll) c/p setting counter selector latch selector 23-bit shift register prescaler (rx-pll) (32/33, 64/65) intermittent mode control (rx-pll) phase comp. (rx-pll) charge pump (rx-pll) current switch lock det. (rx-pll) 3 bit latch 7 bit latch 11 bit latch 2 bit latch 14 bit latch 1 bit latch schmitt circuit schmitt circuit binary 14-bit pro- grammable ref. counter(rx-pll) c/p setting counter binary 7-bit swallow counter (rx-pll) binary 11-bit programmable counter(rx-pll)
mb15f78sp 5 n n n n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. power supply voltage v cc - 0.5 4.0 v vp v cc 4.0 v input voltage v i - 0.5 v cc + 0.5 v output voltage ld / fout v o gnd v cc v do tx , do rx v dd gnd vp v storage temperature tstg - 55 + 125 c parameter symbol value unit min. typ. max. power supply voltage v cc 2.4 2.7 3.6 v vp v cc 2.7 3.6 v input voltage v i gnd ? v cc v operating temperature ta - 40 ?+ 85 c
mb15f78sp 6 n n n n electrical characteristics (continued) (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) parameter symbol condition value unit min. typ. max. power supply current i cctx * 1 tx pll ? 2.2 ? ma i ccrx * 2 rx pll ? 3.3 ? ma power saving current i pstx ps tx = ps rx = l ? 0.1 *8 10 m a i psrx ps tx = ps rx = l ? 0.1 * 8 10 m a operating frequency fin tx * 3 fin tx tx pll 50 ? 1200 mhz fin rx * 3 fin rx rx pll 400 ? 2550* 9 mhz osc in f osc ? 3 ? 40 mhz input sensitivity fin tx pfin tx tx pll, 50 w system - 15 ?+ 2 dbm fin rx pfin rx rx pll, 50 w system - 15 * 9 ?+ 2 dbm osc in v osc ? 0.5 ? v cc v p - p h level input voltage data, le, clock v ih schmitt trigger input 0.7 v cc + 0.4 ?? v l level input voltage v il schmitt trigger input ?? 0.3 v cc - 0.4 v h level input voltage ps tx ps rx v ih ? 0.7 v cc ?? v l level input voltage v il ? ?? 0.3 v cc v h level input current data le clock ps tx ps rx i ih * 4 ? - 1.0 ?+ 1.0 m a l level input current i il * 4 ? - 1.0 ?+ 1.0 m a h level input current osc in i ih ? 0 ?+ 100 m a l level input current i il * 4 ? - 100 ? 0 m a h level output voltage ld/fout v oh v cc = vp = 2.7 v , i oh = - 1 ma v cc - 0.4 ?? v l level output voltage v ol v cc = vp = 2.7 v , i ol = 1 ma ?? 0.4 v h level output voltage do tx do rx v doh v cc = vp = 2.7 v , i doh = - 0.5 ma vp - 0.4 ?? v l level output voltage v dol v cc = vp = 2.7 v , i dol = 0.5 ma ?? 0.4 v high impedance cutoff current do tx do rx i off v cc = vp = 2.7 v v off = 0.5 v to vp - 0.5 v ?? 2.5 na h level output current ld/fout i oh * 4 v cc = vp = 2.7 v ??- 1.0 ma l level output current i ol v cc = vp = 2.7 v 1.0 ?? ma
mb15f78sp 7 (continued) (v cc = 2.4 v to 3.6 v, ta = - 40 c to + 85 c) parameter symbol condition value unit min. typ. max. h level output current do tx do rx i doh * 4 v cc = vp = 2.7 v, v doh = vp/2, ta = + 25 c cs bit = h ?- 6.0 ? ma cs bit = l ?- 1.5 ? ma l level output current do tx do rx i dol v cc = vp = 2.7 v, v dol = vp/2, ta = + 25 c cs bit = h ? 6.0 ? ma cs bit = l ? 1.5 ? ma charge pump current rate i dol / i doh i domt * 5 v do = vp / 2 ? 3 ?% vs v do i dovd * 6 0.5 v v do vp - 0.5 v ? 10 ?% vs ta i dota * 7 - 40 c ta + 85 c, v do = vp / 2 ? 10 ?% *1 : fin tx = 910 mhz, fosc = 12.8 mhz, v cctx = vp tx = 2.7 v, sw tx = 0, ta = +25 c, in locking state. *2 : fin rx = 2500 mhz, fosc = 12.8 mhz, v ccrx = vp rx = 2.7 v, sw rx = 0, ta = +25 c, in locking state. *3 : ac coupling. 1000 pf capacitor is connected under the condition of minimum operating frequency. *4 : the symbol C (minus) means direction of current flow. *5 : v cc = vp = 2.7 v, ta = +25 c (||i 3 | C |i 4 ||) / [ (|i 3 | + |i 4 |) / 2 ] 100 (%) *6 : v cc = vp = 2.7 v, ta = +25 c (applied to each i dol , i doh ) [ (||i 2 | C |i 1 ||) / 2 ] / [ (|i 1 | + |i 2 |) / 2 ] 100 (%) *7 : v cc = vp = 2.7 v, ta = +25 c (applied to each i dol , i doh ) [ ||i do (+85 c) | C |i do (C40 c) || / 2 ] / [ (|i do (+85 c) | + |i do (C40 c) |) / 2 ] 100 (%) *8 : fosc = 12.8 mhz, v ccrx = vp rx = v cctx = vp tx = 2.7 v, ta = +25 c *9 : 2500 mhz to 2550 mhz, v cc = 2.7 v to 3.6 v, pfinmin = - 10 dbm i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 vp / 2 vp vp - 0.5 charge pump output voltage (v)
mb15f78sp 8 n n n n functional description 1. pulse swallow function f vco = [(p n) + a] f osc ? r f vco : output frequency of external voltage controlled oscillator (vco) p : preset divide ratio of dual modulus prescaler (16 or 32 for tx-pll, 32 or 64 for rx-pll) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127, a < n) f osc : reference oscillation frequency (osc in input frequency) r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) 2. serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of tx/rx-pll sec- tions, programmable reference dividers of tx/rx-pll sections are controlled individually. serial data of binary data is entered through data pin. on rising edge of clock, one bit of serial data is transferred into the shift register. on a rising edge of load enable signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. (1) shift register configuration the programmable reference counter for the tx-pll the programmable reference counter for the rx-pl the programmable counter and the swallow counter for the tx-pll the programmable counter and the swallow counter for the rx-pll cn1 0 1 0 1 cn2 0 0 1 1 (lsb) (msb) cs : charge pump currnet select bit r1 to r14 : divide ratio setting bits for the programmable reference counter (3 to 16,383) t1, 2 : test purpose bit cn1,2 : control bit x : dummy bits (set 0 or 1) note : data input with msb first. ? programmable reference counter data flow 1 2 3 4 5 6 7 8 9 10111213 14 15 16 17 18 1920212223 cn1 cn2 t1 t2 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 cs x x x x
mb15f78sp 9 (2) data setting ? binary 14-bit programmable reference counter data setting note : divide ratio less than 3 is prohibited. ? binary 11-bit programmable counter data setting note : divide ratio less than 3 is prohibited. ? binary 7-bit swallow counter data setting divide ratio r14r13r12 r11 r10 r9 r8 r7 r6r5r4r3r2r1 300000000000011 4 16383 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratio n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 3 00000000011 4 2047 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 divide ratio a7 a6 a5 a4 a3 a2 a1 0 0000000 1 127 0 1 0 1 0 1 0 1 0 1 0 1 1 1 (lsb) (msb) ? programmable counter a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) n1 to n11 : divide ratio setting bits for the programmable counter (3 to 2,047) lds : ld/fout signal select bit sw : divide ratio setting bit for the prescaler fc : phase control bit for the phase detector cn1, 2 : control bit note : data input with msb first. 1 2 3 4 5 67891011121314151617181920212223 cn1 cn2 lds sw fc a1 a2 a3 a4 a5 a6 a7 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 data flow
mb15f78sp 10 ? prescaler data setting ? test purpose bit setting ? phase comparator phase switching data setting z : high-impedance depending upon the vco and lpf polarity, fc bit should be set. divide ratio sw = h sw = l prescaler divide ratio tx-pll 16/17 32/33 prescaler divide ratio rx-pll 32/33 64/65 ? charge pump current setting ? ld/fout output select data setting current value cs ld/fout output signal lds 6.0 ma 1 fout signal 1 1.5 ma 0 ld signal 0 ld/fout pin state t1 t2 outputs fr tx .0 0 outputs fr rx .1 0 outputs fp tx .0 1 outputs fp rx .1 1 phase comparator input fc = h fc = l do tx /do rx do tx /do rx fr > fp h l fr < fp l h fr = fp z z (1) (2) (1) vco polarity fc = h (2) vco polarity fc = l note : give attention to the polarity for using active type lpf. max. lpf output voltage vco output frequency high
mb15f78sp 11 3. power saving mode (intermittent mode control circut) the intermittent mode control circuit reduces the pll power consumption. by setting the ps pins low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pins high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes: when power (v cc ) is first applied, the device must be in standby mode, ps tx = ps rx = low, for at least 1 m s. ps pins must be set at l for power-on status ps tx /ps rx pins normal mode h power saving mode l on off v cc clock data le ps tx ps rx (1) (2) (3) t v 3 1 m s t ps 3 100 ns (1) ps tx = ps rx = l (power saving mode) at power-on (2) set serial data 1 m s later after power supply remains stable (v cc > 2.2 v). (3) release power saving mode (ps tx , ps rx : l ? h) 100 ns later after setting serial data.
mb15f78sp 12 4. serial data input timing frequency multiplier setting is performed through a serial interface using the data pin, clock pin, and le pin. setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of the le signal. the following diagram shows the data input timing. lsb msb clock data le t 7 t 1 t 2 t 5 t 3 t 6 t 4 1st data 2nd data control bit invalid data note : le should be l when the data is transferred into the shift register. parameter min. typ. max. unit parameter min. typ. max. unit t 1 20 ?? ns t 5 30 ?? ns t 2 20 ?? ns t 6 100 ?? ns t 3 30 ?? ns t 7 100 ?? ns t 4 20 ?? ns
mb15f78sp 13 n n n n phase comparator output waveform fr tx / fr rx fp tx / fp rx ld do tx / do rx t wu t wl do tx / do rx h l l h z z ld output logic table note s: phase error detection range = C2 p to + 2 p pulses on do tx /do rx signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu > 2/fosc: e.g. t wu > 156.3 ns when fosc = 12.8 mhz t wu < 4/fosc: e.g. t wl < 312.5 ns when fosc = 12.8 mhz tx-pll section rx-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l (fc bit = high) (fc bit = low)
mb15f78sp 14 n n n n test circuit (for measuring input sensitivity fin/osc in ) 10987654321 11 12 13 14 15 16 17 18 19 20 s.g. s.g. s.g. 50 w 50 w 50 w 1000 pf 1000 pf 1000 pf 1000 pf 1000 pf 0.1 m f 0.1 m f 0.1 m f 0.1 m f v ccrx v cctx vp tx vp rx fout osc in clock data le gnd fin tx fin rx xfin rx xfin tx gnd tx gnd rx v cctx v ccrx ps tx ps rx vp tx vp rx do tx do rx ld/ fout note : the terminal number shows that of tssop-20 oscilloscope controller (divide ratio setting)
mb15f78sp 15 n typical characteristics 1. fin rx input sensitivity 2. fin tx input sensitivity 10 0 - 20 - 10 - 30 - 40 - 50 0 500 1000 1500 2000 2500 3000 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c spec input sensitivity pfin rx (dbm) input frequency fin rx (mhz) rx-pll input sensitivity vs. input frequency 10 0 - 20 - 10 - 30 - 40 - 50 0 200 400 600 800 1000 1200 1400 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = +25 c tx-pll input sensitivity vs. input frequency input frequency fin tx (mhz) input sensitivity pfin tx (dbm) spec
mb15f78sp 16 3. osc in input sensitivity 10 0 - 30 - 10 - 20 - 40 - 50 - 60 0 20 40 100 80 60 200 180 160 140 120 220 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c input sensitivity vs. input frequency input sensitivity v osc (dbm) input frequency f osc (mhz) spec
mb15f78sp 17 4. do output current (rx pll) 10.0 - 10.0 1.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 2.0 2.7 10.0 - 10.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 1.0 2.0 2.7 i do vs. v do charge pump output current i do (ma) charge pump output voltage v do (v) i do vs. v do charge pump output voltage v do (v) charge pump output current i do (ma) ? 1.5 ma mode ? 6.0 ma mode
mb15f78sp 18 5. do output current (tx pll) 10.0 - 10.0 0.0 ta = + 25 c v cc = vp = 2.7 v i dol i doh 0.0 1.0 2.0 2.7 10.0 - 10.0 1.0 ta = + 25 c v cc = vp = 2.7 v 0.0 i dol i doh 0.0 2.0 2.7 charge pump output voltage v do (v) charge pump output voltage v do (v) charge pump output current i do (ma) charge pump output current i do (ma) i do vs. v do i do vs. v do ? 1.5 ma mode ? 6.0 ma mode
mb15f78sp 19 6. fin input impedance 749.72 w - 841.66 w 50 mhz 32.047 w - 182.58 w 400 mhz 14.746 w - 84.391 w 800 mhz 1 : 2 : 3 : start 50.000 000 mhz stop 1 200.000 000 mhz 2 3 4 1 - 45.613 w 2.9077 pf 1 200.000 000 mhz 4 : - 11.723 w 314.47 w - 609.53 w 100 mhz 15.457 w - 64.836 w 1 ghz 15.612 w - 6.8101 w 2 ghz 1 : 2 : 3 : start 100.000 000 mhz stop 2 500.000 000 mhz 2 4 3 1 15.306 w 974.39 ph 2 500.000 000 mhz 4 : 24.681 w fin tx input impedance fin rx input impedance
mb15f78sp 20 7. osc in input impedance 12.448 k w - 10.978 k w 3 mhz 521.62 w - 3.3743 k w 20 mhz 133.38 w - 1.7066 k w 40 mhz 1 : 2 : 3 : start 3.000 000 mhz stop 100.000 000 mhz 4 1 - 679.06 w 2.3437 pf 100.000 000 mhz 4 : 34.313 w 2 3 osc in input impedance
mb15f78sp 21 n n n n reference information (for look-up time, phase noise and reference leakage) (continued) s.g. osc in fin vco d o lpf test circuit spectrum analyzer 2.0 k w 0.022 pf 27 k w 2200 pf 180 pf vavg 34 center span1.000 mhz 1.733000 ghz rbw 3.0 khz swp vbw 3.0 khz 280 ms d mkr - 73.67 db 200 khz 10 db / d mkr 200 khz - 73.67 db d s vavg 42 center span 50.00 khz 1.73300000 ghz rbw 100 hz swp vbw 100 hz 4.00 s d mkr - 53.33 db 14.75 khz 10 db / d mkr 14.75 khz - 53.33 db d s f vco = 1733 mhz k v = 44 mhz/v fr = 200 khz f osc = 13 mhz lpf v cc = 3.0 v v vco = 3.5 v ta = + 25 c cp : 6 ma mode ? pll reference leakage ? pll phase noise
mb15f78sp 22 (continued) 1.80300 ghz 1.70300 ghz - 2.189 ms 311 m s 500.0 m s / div 2.811 ms t 1 400 m st 2 800 m s d 400 m s 1.83300 ghz 1.73300 ghz 1.63300 ghz - 2.189 ms 311 m s 500.0 m s / div 2.811 ms t 1 400 m st 2 778 m s d 378 m s - 2.189 ms 311 m s 500.0 m s / div 2.811 ms t 1 400 m st 2 800 m s d 400 m s - 2.189 ms 311 m s 500.0 m s / div 2.811 ms t 1 400 m st 2 778 m s d 378 m s 1.803005250 ghz 1.803001250 ghz 1.802997250 ghz 1.90300 ghz 1.733004500 ghz 1.733000500 ghz 1.732996500 ghz ? pll lock-up time ? pll lock-up time 1733 mhz ? 1803 mhz within 1 khz lch ? hch 400 m s 1803 mhz ? 1733 mhz within 1 khz hch ? lch 378 m s
mb15f78sp 23 n application example 0.1 m f 18 17 20 19 16 15 14 13 12 11 34 12 5678910 1000 pf 1000 pf output 2.7 v mb15f78sp 1000 pf 1000 pf 1000 pf 2.7 v 0.1 m f 0.1 m f output lock det. vco lpf vco lpf tcxo do rx ps rx vp rx xfin rx gnd rx v ccrx fin rx le data clock do tx ps tx vp tx ld/fout v cctx fin tx xfin tx gnd tx osc in gnd 2.7 v 0.1 m f 2.7 v notes : clock, data, le : schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input). the terminal number shows that of tssop-20. from controller
mb15f78sp 24 n n n n usage precautions (1) v ccrx , vp rx , v cctx and vp tx must equal equal voltage. even if either rx-pll or tx-pll is not used, power must be supplied to both v ccrx , vp rx , v cctx and vp tx to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. n n n n ordering information part number package remarks MB15F78SPPFT 20-pin, plastic tssop (fpt-20p-m06) mb15f78sppv 20-pad, plastic bcc (lcc-20p-m04)
mb15f78sp 25 n n n n package dimensions (continued) c 1999 fujitsu limited f20026s-2c-2 6.50?.10(.256?004) * 4.40?.10 6.40?.20 (.252?008) (.173?004) * 0.10(.004) 0.65(.026) 0.24?.08 (.009?003) 1 10 20 11 "a" 0.17?.05 (.007?002) m 0.13(.005) details of "a" part 0~8 (.018/.030) 0.45/0.75 (0.50(.020)) 0.25(.010) (.041?002) 1.05?.05 (mounting height) 0.07 +0.03 ?.07 +.001 ?003 .003 (stand off) lead no. index dimensions in mm (inches) 20-pin plastic tssop (fpt-20p-m06) n ote 1 ) * : these dimensions do not include resin protrusion. note 2 ) pins width and pins thickness include plating thickness.
mb15f78sp 26 (continued) c 1999 fujitsu limited c20055s-1c-1 3.60?.10(.142?004) 11 16 16 11 16 1 6 3.40?.10 (.134?004) index area 0.05(.002) 0.80(.031)max (mounting height) 0.085?.04 (.003?002) (stand off) 0.25?.10 (.010?004) typ 0.50(.020) 3.00(.118)typ 2.80(.110)ref typ 0.50(.020) (.010?004) 0.25?.10 2.70(.106) typ "d" "b" "a" "c" 0.60?.10 (.024?004) 0.50?.10 (.020?004) details of "a" part (.020?004) 0.50?.10 0.30?.10 (.012?004) details of "b" part details of "c" part (.020?004) 0.50?.10 (.024?004) 0.60?.10 c0.20(.008) details of "d" part 0.40?.10 (.016?004) 0.30?.10 (.012?004) c 1999 fujitsu limited c20055s-1c-1 3.60?.10(.142?004) 11 16 16 11 16 1 6 3.40?.10 (.134?004) index area 0.05(.002) 0.80(.031)max (mounting height) 0.085?.04 (.003?002) (stand off) 0.25?.10 (.010?004) typ 0.50(.020) 3.00(.118)typ 2.80(.110)ref typ 0.50(.020) (.010?004) 0.25?.10 2.70(.106) typ "d" "b" "a" "c" 0.60?.10 (.024?004) 0.50?.10 (.020?004) details of "a" part (.020?004) 0.50?.10 0.30?.10 (.012?004) details of "b" part details of "c" part (.020?004) 0.50?.10 (.024?004) 0.60?.10 c0.20(.008) details of "d" part 0.40?.10 (.016?004) 0.30?.10 (.012?004) dimensions in mm (inches) 20-pad plastic bcc (lcc-20p-m04)
mb15f78sp fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0005 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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