? semiconductor components industries, llc, 2010 october, 2010 ? rev. 1 1 publication order number: nstb1005dxv5/d NSTB1005DXV5T1G dual common base-collector bias resistor transistors npn and pnp silicon surface mount transistors with monolithic bias resistor network the brt (bias resistor transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base ? emitter resistor. these digital transistors are designed to replace a single device and its external resistor bias network. the brt eliminates these individual components by integrating them into a single device. the nstb1005dxv5t1 contains two complementary brt devices are housed in the sot ? 553 package which is ideal for low power surface mount applications where board space is at a premium. features ? simplifies circuit design ? reduces board space ? reduces component count ? available in 8 mm, 7 inch tape and reel ? this is a pb ? free device maximum ratings (t a = 25 c unless otherwise noted, common for q 1 and q 2 , ? minus sign for q 1 (pnp) omitted) rating symbol value unit collector-base voltage v cbo 50 vdc collector-emitter voltage v ceo 50 vdc collector current i c 100 madc thermal characteristics characteristic (one junction heated) symbol max unit total device dissipation t a = 25 c (note 1) derate above 25 c (note 1) p d 357 2.9 mw mw/ c thermal resistance ? junction-to-ambient (note 1) r ja 350 c/w characteristic (both junctions heated) symbol max unit total device dissipation t a = 25 c (note 1) derate above 25 c (note 1) p d 500 4.0 mw mw/ c thermal resistance ? junction-to-ambient (note 1) r ja 250 c/w junction and storage temperature t j , t stg ? 55 to +150 c 1. fr ? 4 @ minimum pad marking diagram 45 q1 q2 r1 r1 r2 31 2 http://onsemi.com sot ? 553 case 463b uc m 1 5 1 5 uc = specific device code m = date code =pb ? free package device package shipping ? ordering information NSTB1005DXV5T1G sot ? 553 (pb ? free) 4000/tape & reel r2 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. (note: microdot may be in either location)
NSTB1005DXV5T1G http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit q1 transistor: pnp ? off characteristics collector ? base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector ? emitter cutoff current (v ce = 50 v, i b = 0) i ceo ? ? 500 nadc emitter ? base cutoff current (v eb = 6.0 v, i c = 0) i ebo ? ? 0.1 madc collector ? base breakdown voltage (i c = 10 a, i e = 0) v (br)cbo 50 ? ? vdc collector ? emitter breakdown voltage (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc on characteristics dc current gain h fe 80 140 ? collector ? emitter saturation voltage (i c = 10 ma, i e = 0.3 ma) v ce(sat) ? ? 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 3.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor r1 32.9 47 61.1 k resistor ratio r 1 /r 2 0.8 1.0 1.2 q2 transistor: npn ? off characteristics collector-base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector-emitter cutoff current (v cb = 50 v, i b = 0) i ceo ? ? 500 nadc emitter-base cutoff current (v eb = 6.0, i c = 0) i ebo ? ? 0.1 madc on characteristics collector-base breakdown voltage (i c = 10 a, i e = 0) v (br)cbo 50 ? ? vdc collector-emitter breakdown voltage (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc dc current gain (v ce = 10 v, i c = 5.0 ma) h fe 80 140 ? collector ? emitter saturation voltage (i c = 10 ma, i b = 0.3 ma) v ce(sat) ? ? 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor r1 33 47 61 k resistor ratio r1/r2 0.8 1.0 1.2 figure 1. derating curve 250 200 150 100 50 0 -50 0 50 100 150 t a , ambient temperature ( c) p d , power dissipation (milliwatts) r ja = 833 c/w
NSTB1005DXV5T1G http://onsemi.com 3 typical electrical characteristics ? pnp transistor v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain (normalized) figure 2. v ce(sat) versus i c 100 10 1 0.1 0.01 0.001 0 v in , input voltage (volts) t a =-25 c 25 c 1 2 3 4 5 6 7 8 9 10 figure 3. dc current gain figure 4. output capacitance figure 5. output current versus input voltage figure 6. input voltage versus output current 0.01 20 i c , collector current (ma) v ce(sat) , maximum collector voltage (volts) 0.1 1 0 40 50 1000 1 10 100 i c , collector current (ma) t a =75 c -25 c 100 10 0 i c , collector current (ma) 0.1 1 10 100 10 20 30 40 50 t a =-25 c 25 c 75 c 75 c i c /i b = 10 50 010203040 4 3 1 2 v r , reverse bias voltage (volts) c ob , capacitance (pf) 0 t a =-25 c 25 c 75 c 25 c v ce = 10 v f = 1 mhz l e = 0 v t a = 25 c v o = 5 v v o = 0.2 v
NSTB1005DXV5T1G http://onsemi.com 4 typical electrical characteristics ? npn transistor v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain figure 7. v ce(sat) versus i c 0246810 100 10 1 0.1 0.01 0.001 v in , input voltage (volts) t a =-25 c 75 c 25 c figure 8. dc current gain figure 9. output capacitance 100 10 1 0.1 010 203040 50 i c , collector current (ma) figure 10. output current versus input voltage 1000 10 i c , collector current (ma) t a =75 c 25 c -25 c 100 10 1 100 25 c 75 c 50 010203040 1 0.8 0.6 0.4 0.2 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) figure 11. input voltage versus output current 0 20 40 50 10 1 0.1 0.01 i c , collector current (ma) 25 c 75 c v ce(sat) , maximum collector voltage (volts) v ce = 10 v f = 1 mhz i e = 0 ma t a = 25 c v o = 5 v v o = 0.2 v i c /i b = 10 t a =-25 c t a =-25 c
NSTB1005DXV5T1G http://onsemi.com 5 package dimensions sot ? 553 xv5 suffix case 463b ? 01 issue b e m 0.08 (0.003) x b 5 pl a c ? x ? ? y ? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. d e y 12 3 4 5 l 1.35 0.0531 0.5 0.0197 mm inches scale 20:1 0.5 0.0197 1.0 0.0394 0.45 0.0177 0.3 0.0118 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h e dim a min nom max min millimeters 0.50 0.55 0.60 0.020 inches b 0.17 0.22 0.27 0.007 c d 1.50 1.60 1.70 0.059 e 1.10 1.20 1.30 0.043 e 0.50 bsc l 0.10 0.20 0.30 0.004 0.022 0.024 0.009 0.011 0.063 0.067 0.047 0.051 0.008 0.012 nom max 1.50 1.60 1.70 0.059 0.063 0.067 h e 0.08 0.13 0.18 0.003 0.005 0.007 0.020 bsc on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. nstb1005dxv5/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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