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for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 1 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter features ? high s peed modes (12-bit / 8-bit) quad channel mode: f s max = 160 / 250 m s p s dual channel mode: f s max = 320 / 500 m s p s s ingle channel mode: f s max = 640 / 1000 m s p s snr : 70 db, s fd r : 60/75 db [1] (12-bit 1ch mode) ? 8-bit modes described in hmcad1511 and hmcad1510 ? precision mode (14-bit) four channels up to 105 m s p s snr : 74 db, s fd r : 83 db @ 70 mhz snr : 72.5 db, s fd r : 78 db @ 140 mhz ? integrated cross point s witches with instantaneous switching ? internal low jitter programmable clock divider ? ultra low power dissipation 490 mw including i/ o at 12-bit 640 m s p s ? 0.5 s start-up time from s leep, 15 s from power down ? internal reference circuitry with no external components required ? coarse and fne gain control ? digital fne gain adjustment for each adc ? internal offset correction ? 1.8 v supply voltage ? 1.7 - 3.6 v cm os logic on control interface pins ? s erial l v d s output 12, 14, 16 and dual 8-bit modes available ? 7 x 7 mm 48 qf n package [1] including/ e xcluding interleaving s purs t ypical applications ? precision o scilloscopes ? s pectrum analyzers ? diversity r eceivers ? hi- e nd ultrasound ? communication t esting ? n on destructive t esting p in compatible parts HMCAD1520 is pin compatible and can be confg - ured to operate as hmcad1511 and hmcad1510, with functionality and performance as described in hmcad1511 and hmcad1510 datasheets. functional d iagram functional block diagram
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 2 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter g eneral d escription t he HMCAD1520 is a versatile high performance low power analog-to-digital converter (adc), with interleaving high s peed modes to increase sampling rate. integrated cross point s witches activate the input selected by the user. in s ingle channel mode, one of the four inputs can be selected as valid input to the single adc channel. in dual channel mode, any two of the four inputs can be selected to each adc channel. in quad channel mode and precision mode, any input can be assigned to any adc channel. an internal, low jitter and programmable clock divider makes it possible to use a single clock source for all opera - tional modes. t he HMCAD1520 is based on a proprietary structure, and employs internal reference circuitry, a serial control inter - face and a serial l v d s output data. data and frame synchronization clocks are supplied for data capture at the receiver. internal digital fne gain can be set separately for each adc to calibrate for gain errors. v arious modes and confguration settings can be applied to the adc through the serial control interface ( s pi). each channel can be powered down independently and output data format can be selected through this interface. a full chip idle mode can be set by a single external pin. r egister settings determine the exact function of this pin. HMCAD1520 is designed to interface easily with field programmable gate arrays (fpgas) from several vendors. e lectrical specifcations d c specifcations a v dd = d v dd = ov dd = 1.8 v , f s = 160 m s p s , quad channel 12-bit high s peed mode, 50% clock duty cycle, -1 dbf s 70 mhz input s ignal, 1x / 0 db digital gain (fine and coarse), unless o therwise n oted parameter description min typ max unit dc accuracy no missing codes guaranteed o ffset o ffset error after internal digital offset correction 1 l sb g abs gain error 6 %fs g rel gain matching between channels. 3 sigma value at worst case conditions 0.5 %fs dnl differential non linearity 0.2 l sb inl integral non linearity 0.6 l sb v cm,out common mode voltage output v a vdd /2 analog input v cm,in analog input common mode voltage v cm -0.1 v cm +0.2 v fsr differential input voltage full scale range 2 vpp c in,q differential input capacitance, quad channel mode 5 pf c in,d differential input capacitance, dual channel mode 7 pf c in,s differential input capacitance, single channel mode 11 pf power supply v a vdd analog s upply v oltage 1.7 1.8 2 v v d vdd digital and output driver supply voltage 1.7 1.8 2 v v ov dd digital cm os input s upply v oltage 1.7 1.8 3.6 v temperature t a o perating free-air temperature -40 85 c
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 3 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter ac specifcations C high speed modes a v dd = d v dd = ov dd = 1.8 v , 50% clock duty cycle, -1 dbf s 70 mhz input signal, gain = 1x, 12-bit output, rs d s output data levels, unless otherwise noted parameter description min typ max unit performance snr s ignal to noise r atio, excluding interleaving spurs single channel mode , f s = 640 msps 70 dbfs dual channel mode , f s = 320 msps 70 dbfs quad channel mode , f s = 160 m sps 70 dbfs sinad incl s ignal to n oise and distortion r atio, including interleaving spurs single channel mode , f s = 640 msps 58 dbfs dual channel mode , f s = 320 msps 58 dbfs quad channel mode , f s = 160 m sps 58 dbfs sinad excl s ignal to n oise and distortion r atio, excluding interleaving spurs single channel mode , f s = 640 msps 67 dbfs dual channel mode , f s = 320 msps 68 dbfs quad channel mode , f s = 160 m sps 68 dbfs sfdr incl s purious free dynamic r ange, including interleaving spurs single channel mode , f s = 640 msps 60 dbc dual channel mode , f s = 320 msps 60 dbc quad channel mode , f s = 160 m sps 60 dbc sfdr excl s purious free dynamic r ange, excluding interleaving spurs single channel mode , f s = 640 msps 75 dbc dual channel mode , f s = 320 msps 77 dbc quad channel mode , f s = 160 m sps 78 dbc hd2/3 worst of hd2/hd3 single channel mode , f s = 640 msps 75 dbc dual channel mode , f s = 320 msps 77 dbc quad channel mode , f s = 160 m sps 78 dbc enob e ffective number of bits single channel mode , f s = 640 msps 10.8 bits dual channel mode , f s = 320 msps 11.0 bits quad channel mode , f s = 160 m sps 11.0 bits x tlk,hs2 cross t alk dual ch mode. s ignal applied to 1 channel (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 = 71 mhz, f in0 = 70 mhz 70 dbc x tlk,hs4 cross t alk quad ch mode. s ignal applied to 1 channel (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 = 71 mhz, f in0 = 70 mhz 70 dbc power s upply s ingle ch: f s = 640 msps , dual ch: f s = 320 msps , quad ch: f s = 160 m sps . i a vdd analog s upply current 190 ma i d vdd digital and output driver s upply current 82 ma p a vdd analog power 342 mw
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 4 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter ac specifcations C high speed modes a v dd = d v dd = ov dd = 1.8 v , 50% clock duty cycle, -1 dbf s 70 mhz input signal, gain = 1x, 12-bit output, rs d s output data levels, unless otherwise noted parameter description min typ max unit p d vdd digital power 148 mw p tot t otal power dissipation 490 mw p pd power down mode dissipation 15 w p slp deep s leep mode power dissipation 66 mw p slpch power dissipation with all channels in sleep channel mode (light sleep) 121 mw p slpch_s a v power dissipation savings per channel off 92 mw analog input fpbw full power bandwidth 700 mhz clock inputs f smax max. conversion r ate in modes: msps s ingle / dual 640/320 quad channel 160 f smin min. conversion r ate in modes: msps s ingle / dual 120/60 quad channel 30 ac specifcations C p recision mode a v dd = d v dd = ov dd = 1.8 v , f s = 105 mhz, 50% clock duty cycle, -1 dbf s 70 mhz input signal, gain = 1x, dual 8-bit output, rs d s output data levels, unless otherwise noted parameter description min typ max unit performance snr s ignal to noise r atio f s = 80 msps 75 dbfs f s = 105 m sps 74 dbfs f s = 105 m sps , f in = 105 m sps 72.5 dbfs sinad s ignal to n oise and distortion r atio f s = 80 msps 73 dbfs f s = 105 m sps 72.5 dbfs f s = 105 m sps , f in = 105 m sps 71 dbfs sfdr s purious free dynamic r ange f s = 80 msps 85 dbc f s = 105 m sps 83 dbc f s = 105 m sps , f in = 105 m sps 78 dbc hd2 s econd order harmonic spur f s = 80 msps 90 dbc f s = 105 m sps 90 dbc f s = 105 m sps , f in = 105 m sps 80 dbc hd3 t hird order harmonic spur
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 5 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter ac specifcations C p recision mode a v dd = d v dd = ov dd = 1.8 v , f s = 105 mhz, 50% clock duty cycle, -1 dbf s 70 mhz input signal, gain = 1x, dual 8-bit output, rs d s output data levels, unless otherwise noted parameter description min typ max unit f s = 80 msps 85 dbc f s = 105 m sps 83 dbc f s = 105 m sps , f in = 105 m sps 78 dbc enob e ffective number of bits f s = 80 msps 11.8 bits f s = 105 m sps 11.8 bits f s = 105 m sps , f in = 105 m sps 11.5 bits x tlk cross t alk. s ignal applied to 1 channel (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 = 71 mhz, f in0 = 70 mhz 70 dbc power s upply i a vdd analog s upply current 229 ma i d vdd digital and output driver s upply current 106 ma p a vdd analog power 412 mw p d vdd digital power 191 mw p tot t otal power dissipation 603 mw p pd power down mode dissipation 15 w p slp deep s leep mode power dissipation 66 mw p slpch power dissipation with all channels in sleep channel mode (light sleep) 131 mw p slpch_s a v power dissipation savings per channel off 118 mw analog input fpbw full power bandwidth 700 mhz clock inputs f smax max. conversion r ate 105 msps f smin min. conversion r ate 15 msps d igital and switching specifcations a vdd = d vdd = ov dd = 1.8v , rsds output data levels, unless otherwise noted. parameter description min typ max unit clock inputs dc duty cycle, high speed modes 40 60 % high dc duty cycle, precision mode 30 70 % high compliance l vds supported up to 700 mbps l vpecl, s ine wave, cmos , l vds v ck,sine differential input voltage swing, sine wave clock input 1500 mvpp v ck,cmos v oltage input range cm os (clkn connected to ground) v ov dd v cm,ck input common mode voltage. keep voltages within ground and voltage of ov dd 0.3 v ov dd -0.3 v c ck differential input capacitance 3 pf logic inputs (cmos)
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 6 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter d igital and switching specifcations a vdd = d vdd = ov dd = 1.8v , rsds output data levels, unless otherwise noted. parameter description min typ max unit v hi high level input v oltage. v ov dd 3.0v 2 v v hi high level input v oltage. v ov dd = 1.7 v C 3.0v 0.8 v ov dd v v li low level input v oltage. v ov dd 3.0v 0 0.8 v v li low level input v oltage. v ov dd = 1.7 v C 3.0v 0 0.2 v ov dd v i hi high level input leakage current +/-10 a i li low level input leakage current +/-10 a c i input capacitance 3 pf data outputs compliance l vds / rsds v out differential output voltage, l vds 350 mv v out differential output voltage, rs ds 150 mv v cm o utput common mode voltage 1.2 v output coding default/optional o ffset binary/ 2s complement timing characteristics t a,hs aperture delay, high speed modes 1.5 ns t a,pm aperture delay, precision mode 1.4 ns t j,hs aperture jitter, all bits set to 1 in jitter_ctrl<7:0>, high speed modes 120 fsrms t j,hs aperture jitter, one bit set to 1 in jitter_ctrl<7:0>, high speed modes 160 fsrms t j,pm aperture jitter, all bits set to 1 in jitter_ctrl<7:0>, precision modes 75 fsrms t j,pm aperture jitter, one bit set to 1 in jitter_ctrl<7:0>, precision modes 130 fsrms t skew t iming skew between adc channels, high speed modes 2.5 psrms t su s tart up time from power down mode and deep s leep mode to active mode in s. s ee section clock frequency for details. 15 s t slpch s tart up time from s leep channel mode to active mode 0.5 s t ovr o ut of range recovery time 1 clock cycles t la tpm pipeline delay, precision speed mode 15 clock cycles t la thsmq pipeline delay, quad high speed mode 32 clock cycles t la thsmd pipeline delay, dual high speed mode 64 clock cycles t la thsms pipeline delay, single high speed mode 128 clock cycles lvds output timing characteristics t data lclk to data delay time (excluding programmable phase shift) 50 ps t p rop clock propagation delay. 6*t l vds +2.2 7*t l vds +3.5 7*t l vds +5.0 ns l vds bit-clock duty-cycle 45 55 % lclk cycle frame clock cycle-to-cycle jitter 2.5 % lclk cycle t edge data rise- and fall time 20% to 80% 0.7 ns t clkedge clock rise- and fall time 20% to 80% 0.7 ns
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 7 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter absolute maximum r atings applying voltages to the pins beyond those specifed in t able 1 could cause permanent damage to the circuit. t able 1: maximum voltage ratings pin reference pin rating a vdd a vss -0.3v to +2.3v d vdd d vss -0.3v to +2.3v ov dd a vss -0.3v to +3.9v a vss / d vss d vss / a vss -0.3v to +0.3v analog inputs and outputs a vss -0.3v to +2.3v clkx a vss -0.3v to +3.9v l vds outputs d vss -0.3v to +2.3v digital inputs d vss -0.3v to +3.9v t able 2 shows the maximum external temperature ratings. t able 2: maximum t emperature r atings o perating t emperature -40 to +85 oc s torage t emperature -60 to +150 oc maximum junction t emperature 110 oc t hermal r esistance ( rth) 29 oc/w s oldering profle qualifcation j- std-020 esd s ensivity hbm class 1c esd s ensivity cdm class iii e l e c trost a t ic sens i t i ve d ev ic e o b serve ha n dli n g p re cau t i ons s tresses above those listed under absolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 8 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter figure 1: pin diagram t able 3: p in d escriptions pin name description pin number # of pins a vdd analog power supply, 1.8 v 1, 36 2 csn chip select enable. active low 2 1 s da t a s erial data input 3 1 sclk s erial clock input 4 1 resetn r eset s pi interface. active low 5 1 pd power-down input. activate after applying power in order to initialize the adc correctly. alternatively use the s pi power down feature 6 1 d vdd digital and i/ o power supply, 1.8v 7, 30 2 d vss digital ground 8, 29 2 dp1a l vds channel 1a, positive output 9 1 dn1a l vds channel 1a, negative output 10 1 dp1b l vds channel 1b, positive output 11 1 dn1b l vds channel 1b, negative output 12 1 dp2a l vds channel 2a, positive output 13 1 dn2a l vds channel 2a, negative output 14 1 dp2b l vds channel 2b, positive output 15 1 dn2b l vds channel 2b, negative output 16 1
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 9 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 3: p in d escriptions pin name description pin number # of pins lclkp l vds bit clock, positive output 17 1 lclkn l vds bit clock, negative output 18 1 fclkp l vds frame clock (1x), positive output 19 1 fclkn l vds frame clock (1x), negative output 20 1 dp3a l vds channel 3a, positive output 21 1 dn3a l vds channel 3a, negative output 22 1 dp3b l vds channel 3b, positive output 23 1 dn3b l vds channel 3b, negative output 24 1 dp4a l vds channel 4a, positive output 25 1 dn4a l vds channel 4a, negative output 26 1 dp4b l vds channel 4b, positive output 27 1 dn4b l vds channel 4b, negative output 28 1 a vss2 analog ground domain 2 31 1 a vdd2 analog power supply domain 2, 1.8 v 32 1 ov dd digital cm os inputs supply voltage 33 1 clkn n egative differential input clock. 34 1 clkp positive differential input clock 35 1 in4 n egative differential input signal, channel 4 37 1 ip4 positive differential input signal, channel 4 38 1 a vss analog ground 39, 42, 45 3 in3 n egative differential input signal, channel 3 40 1 ip3 positive differential input signal, channel 3 41 1 in2 n egative differential input signal, channel 2 43 1 ip2 positive differential input signal, channel 2 44 1 in1 n egative differential input signal, channel 1 46 1 ip1 positive differential input signal, channel 1 47 1 v cm common mode output pin, 0.5*a vdd 48 1 start up i nitialization as part of the HMCAD1520 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. r eset can be done in one of two ways: 1. by applying a low-going pulse (minimum 20 ns) on the resetn pin (asynchronous). 2. by using the serial interface to set the rst bit high. internal registers are reset to default values when this bit is set. t he rst bit is self-reset to zero. when using this method, do not apply any low-going pulse on the resetn pin. power down cycling can be done in one of two ways: 1. by applying a high-going pulse (minimum 20 ns) on the pd pin (asynchronous). 2. by cycling the pd bit in register 0fhex to high (reg value 0200hex) and then low (reg value 0000hex).
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 10 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter r egister i nitialization t o set the HMCAD1520 in precision mode, the following registers must be changed from the default value. s uggested values are: address data function 0x31 0x0008 s ets HMCAD1520 in precision mode, clock divider to 1 0x53 0x0004 s ets the l v d s output in dual 8 bit mode serial i nterface t he HMCAD1520 confguration registers can be accessed through a serial interface formed by the pins s da t a (serial interface data), s clk (serial interface clock) and c sn (chip select, active low). t he following occurs when c sn is set low: ? s erial data are shifted into the chip ? at every rising edge of s clk, the value present at s da t a is latched ? s da t a is loaded into the register every 24th rising edge of s clk multiples of 24-bit words data can be loaded within a single active c sn pulse. if more than 24 bits are loaded into s da t a during one active c sn pulse, only the frst 24 bits are kept. t he excess bits are ignored. e very 24-bit word is divided into two parts: ? t he frst eight bits form the register address ? t he remaining 16 bits form the register data acceptable s clk frequencies are from 20mhz down to a few hertz. duty-cycle does not have to be tightly controlled. t iming d iagram figure 2 shows the timing of the serial port interface. t able 4 explains the timing variables used in fgure 2. c s n s c l k s d a t a t s t h t c s t c h i t h i t l o t c k t c h a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 figure 2: s erial port interface timing t able 4: serial p ort i nterface t iming d efnitions parameter description minimum value unit t cs s etup time between csn and sclk 8 ns t ch hold time between c sn and sclk 8 ns t hi sclk high time 20 ns t lo s clk low time 20 ns t ck s clk period 50 ns t s data setup time 5 ns t h data hold time 5 ns
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 11 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t iming d iagrams t l vd s d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n n n n n n n n n n n n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 a nalog input i nput c l oc k lcl k p lclk n f clk n f clk p dx na n - 4 n - 4 d 1 0 d 1 1 t pr o p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 dx n b n - 3 n - 3 d 1 0 d 1 1 n + 3 2 n + 3 4 n+33 n+31 n+35 figure 3: quad channel - l v d s timing 12-bit output t l vd s d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n n n n n n n n n n n n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 a n alog input inp u t c l o c k lclk p l cl k n f cl k n f c lk p n - 8 n - 8 d 1 0 d 1 1 t pr o p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 7 n - 7 d 1 0 d 1 1 n+64 n+68 n+66 n+62 n + 7 0 n + 6 9 n+67 n+65 n+63 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 6 n - 6 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 5 n - 5 d 1 0 d 1 1 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 dx 1 a / dx 3 a dx 1b / dx 3b dx 2 a / dx 4 a dx 2b / dx 4b figure 4: dual channel - l v d s timing 12-bit output
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 12 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t l vd s d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n n n n n n n n n n n n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 a n alog input inp u t c l o c k lclk p l cl k n f cl k n f c lk p d 1 0 d 1 1 t pr o p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 d 1 0 d 1 1 n+128 n+136 n + 1 32 n+124 n+140 n + 1 38 n + 1 34 n+130 n+126 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 d 1 0 d 1 1 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 dx 1 a dx 1b dx 2 a dx 2b d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n + 5 n + 5 n + 5 n + 5 n + 5 n + 5 n + 5 n + 5 n + 5 n + 5 n + 5 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 1 0 n - 1 0 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n + 7 n + 7 n + 7 n + 7 n + 7 n + 7 n + 7 n + 7 n + 7 n + 7 n + 7 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 9 n - 9 d 1 0 d 1 1 n + 6 n + 6 n + 6 n + 6 n + 6 n + 6 n + 6 n + 6 n + 6 n + 6 n + 6 dx 3 a dx 3b dx 4 a dx 4b n + 4 n + 4 n + 4 n + 4 n + 4 n + 4 n + 4 n + 4 n + 4 n + 4 n + 4 n - 1 1 n - 1 1 n - 1 2 n - 1 2 n - 1 3 n - 1 3 n - 1 4 n - 1 4 n - 1 5 n - 1 5 n - 1 6 n - 1 6 figure 5: s ingle channel - l v d s timing 12-bit output d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 n n n n n n n n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n + 1 5 n+16 a n alog inp u t i nput c l oc k l cl k n l cl k p f cl k n f clk p dx x x t l vd s t pr o p figure 6: precision - l v d s timing 14-bit output
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 13 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 d 1 4 d 1 5 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 d 1 4 d 1 5 n n n n n n n n n n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n + 1 5 n+16 a n alog inp u t i nput c l oc k l cl k n l cl k p f clk p f cl k n dx x x t l vd s t pr o p figure 7: precision - l v d s timing 16-bit output t l vd s d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 d 1 4 d 1 5 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 d 1 4 n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n + 1 5 n+16 a n alog input i nput c l oc k lclk p l c lk n f clk p f cl k n d x n a n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 t pr o p d 1 0 d 1 1 d 1 2 d 1 3 d 1 4 d 1 5 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n n n n n n n n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 dx nb n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 d 2 d 3 d 4 d 5 d 6 d 7 figure 8: precision - l v d s timing dual 8-bit output t l v d s t l v d s /2 d xx x t dat a lclk p lclk n figure 9: l v d s data timing
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 14 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 5: r egister map name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address rst * s elf-clearing software reset. inactive x 0x00 sleep4_ch <4:1> channel-specifc sleep mode for a quad channel setup. inactive x x x x 0x0f sleep2_ch <2:1> channel-specifc sleep mode for a dual channel setup. inactive x x sleep1_ch1 channel-specifc sleep mode for a single channel setup. inactive x sleep go to sleep-mode. inactive x pd go to power-down. inactive x pd_pin_cfg <1:0> confgures the pd pin function. pd pin confgured for power-down mode x x ilvds_lclk <2:0> l vds current drive programmability for lclkp and lclkn pins. 3.5 ma drive x x x 0x11 ilvds_frame <2:0> l vds current drive programmability for fclkp and fclkn pins. 3.5 ma drive x x x ilvds_dat <2:0> l vds current drive programmability for output data pins. 3.5 ma drive x x x en_lvds_ term e nables internal termination for l vds buffers. t ermination disabled x 0x12 term_lclk <2:0> programmable termination for lclk n and lclkp buffers. t ermination disabled 1 x x x term_frame <2:0> programmable termination for fclk n and fclkp buffers. t ermination disabled 1 x x x term_dat <2:0> programmable termination for output data buffers. t ermination disabled 1 x x x invert4_ch <4:1> channel specifc swapping of the analog input signal for a quad channel setup. ipx is positive input x x x x 0x24 invert2_ch <2:1> channel specifc swapping of the analog input signal for a dual channel setup. ipx is positive input x x invert1_ch1 channel specifc swapping of the analog input signal for a single channel setup. ipx is positive input x en_ramp e nables a repeating full-scale ramp pattern on the outputs. inactive x 0 0 0x25 dual_ custom_pat e nable the mode wherein the output toggles between two defned codes. inactive 0 x 0 single_ custom_pat e nables the mode wherein the output is a constant specifed code. inactive 0 0 x bits_custom1 <15:0> bits for the single custom pattern and for the frst code of the dual custom pattern. <0> is the l s b. 0x0000 x x x x x x x x x x x x x x x x 0x26
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 15 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 5: r egister map name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address bits_custom2 <15:0> bits for the second code of the dual custom pattern. 0x0000 x x x x x x x x x x x x x x x x 0x27 cgain4_ch1 <3:0> programmable coarse gain channel 1 in a quad channel setup. 1x gain x x x x 0x2a cgain4_ch2 <3:0> programmable coarse gain channel 2 in a quad channel setup. 1x gain x x x x cgain4_ch3 <3:0> programmable coarse gain channel 3 in a quad channel setup. 1x gain x x x x cgain4_ch4 <3:0> programmable coarse gain channel 4 in a quad channel setup. 1x gain x x x x cgain2_ch1 <3:0> programmable coarse gain channel 1 in a dual channel setup. 1x gain x x x x 0x2b cgain2_ch2 <3:0> programmable coarse gain channel 2 in a dual channel setup. 1x gain x x x x cgain1_ch1 <3:0> programmable coarse gain channel 1 in a s ingle channel setup. 1x gain x x x x jitter_ctrl <7:0> clock jitter adjustment. 160 fsrms x x x x x x x x 0x30 precision_ mode * e nable quad channel 14 bits precision mode. inactive x 0x31 high_speed_ mode * <2:0> e nable high speed mode, s ingle, dual or quad channel. high speed mode C quad channel x x x clk_divide <1:0> * defne clock divider factor: 1, 2, 4 or 8 divide by 1 x x coarse_ gain_cfg confgures the coarse gain setting x-gain enabled x 0x33 fne_gain_en e nable use of fne gain. disabled x fgain_ branch1 <6:0> programmable fne gain for branch1. 1x / 0db gain x x x x x x x 0x34 fgain_ branch2 <6:0> programmable fne gain for branch 2. 1x / 0db gain x x x x x x x fgain_ branch3 <6:0> programmable fne gain for branch 3. 1x / 0db gain x x x x x x x 0x35 fgain_ branch4 <6:0> programmable fne gain for branch 4. 1x / 0db gain x x x x x x x fgain_ branch5 <6:0> programmable fne gain for branch 5. 1x / 0db gain x x x x x x x 0x36 fgain_ branch6 <6:0> programmable fne gain for branch 6. 1x / 0db gain x x x x x x x fgain_ branch7 <6:0> programmable fne gain for branch 7. 1x / 0db gain x x x x x x x 0x37 fgain_ branch8 <6:0> programmable fne gain for branch 8. 1x / 0db gain x x x x x x x inp_sel_adc1 <4:0> input select for adc 1. s ignal input: ip1/ in1 x x x x x 0x3a inp_sel_adc2 <4:0> input select for adc 2. s ignal input: ip2/ in2 x x x x x
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 16 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 5: r egister map name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address inp_sel_adc3 <4:0> input select for adc 3. s ignal input: ip3/ in3 x x x x x 0x3b inp_sel_adc4 <4:0> input select for adc 4. s ignal input: ip4/ in4 x x x x x phase_ddr <1:0> controls the phase of the lclk output relative to data. 90 degrees x x 0x42 pat_deskew e nable deskew pattern mode. inactive 0 x 0x45 pat_sync e nable sync pattern mode. inactive x 0 btc_mode binary twos complement format for adc output data. s traight offset binary x 0x46 msb_frst s erialized adc output data comes out with ms b frst. l s b frst x adc_curr <2:0> adc current scaling. nominal x x x 0x50 ext_vcm_bc <1:0> v cm buffer driving strength control. nominal x x lvds_pd_ mode controls l vds power down mode high z-mode x 0x52 lvds_output_ mode <2:0> * s ets the number of l vds output bits. 12 bit x x x 0x53 low_clk_ freq * low clock frequency used. inactive x lvds_ advance advance l vds data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay l vds data bits and frame clock by one clock cycle inactive x 0 fs_cntrl <5:0> fine adjust adc full scale range 0% change x x x x x x 0x55 startup_ctrl <2:0> * controls start-up time. 000 x x x 0x56 undefned register addresses must not be written to; incorrect behavior may be the result. unused register bits (blank table cells) must be set to 0 when programming the registers. all registers can be written to while the chip is in power down. * t hese registers requires a power down cycle when written to ( s ee s tart up initialization).
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 17 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter r egister d escription software r eset name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address rst s elf-clearing software reset. inactive x 0x00 s etting the rst register bit to 1, restores the default value of all the internal registers including the rst register bit itself. modes of o peration name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address precision_mode e nable quad channel 14 bits precision mode. inactive x 0x31 high_speed_ mode <2:0> e nable high speed mode, s ingle, dual or quad channel. high speed mode C quad channel x x x clk_divide<1:0> defne clock divider factor: 1, 2, 4 or 8 divide by 1 x x t he HMCAD1520 has four main operating modes controlled by the register bits precision_mode and high_speed_ mode as defned in table 6. power down mode, as described in section s tartup initialization, must be activated after or during a change of operating mode to ensure correct operation. t he high speed modes all utilize interleaving to achieve high sampling speed. quad channel mode interleaves 2 adc branches, dual channel mode interleaves 4 adc branches, while single channel mode interleave all 8 adc branches. in precision mode interleaving is not required and each adc channel uses one adc branch only. t able 6: modes of o peration precision_ mode high_speed_mode <2:0> mode of operation description 0 0 0 1 s ingle channel 12-bit high speed mode s ingle channel by interleaving adc1to adc4 0 0 1 0 dual channel 12-bit high speed mode dual channel where channel 1 is made by interleaving adc1 and adc2, channel 2 by interleaving adc3 and adc4 0 1 0 0 quad channel 12-bit high speed mode quad channel where channel 1 corresponds to adc1, chan - nel2 to adc2, channel3 to adc3 and channel 4 to adc4 1 0 0 0 quad channel 14-bit precision mode quad channel where channel 1 corresponds to adc1, chan - nel2 to adc2, channel3 to adc3 and channel 4 to adc4 o nly one of the 4 bits should be activated at the same time. clk_divide<1:0> allows the user to apply an input clock frequency higher than the sampling rate. t he clock divider will divide the input clock frequency by a factor of 1, 2, 4, or 8, defned by the clk_divide<1:0> register. by setting the clk_divide<1:0> value relative to the channel_num<2:0> value, the same input clock frequency can be used for all settings on number of channels. e.g: when increasing the number of channels from 1 to 4, the maximum sampling rate is reduced by a factor of 4. by letting clk_divide<1:0> follow the channel_num<2:0> value, and change it from 1 to 4, the internal clock divider will provide the reduction of the sampling rate without changing the input clock frequency.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 18 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 7: clock d ivider factor clk_divide<1:0> clock divider factor s ampling rate (f s ) 00 (default) 1 input clock frequency / 1 01 2 input clock frequency / 2 10 4 input clock frequency / 4 11 8 input clock frequency / 8 i nput select name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address inp_sel_adc1 <4:0> input select for adc 1. s ignal input: ip1/in1 x x x x 0 0x3a inp_sel_adc2 <4:0> input select for adc 2. s ignal input: ip2/in2 x x x x 0 inp_sel_adc3 <4:0> input select for adc 3. s ignal input: ip3/in3 x x x x 0 0x3b inp_sel_adc4 <4:0> input select for adc 4. s ignal input: ip4/in4 x x x x 0 e ach adc is connected to the four input signals via a full fexible cross point switch, set up by inp_sel_adcx. in single channel mode, any one of the four inputs can be selected as valid input to the single adc channel. in dual channel mode, any two of the four inputs can be selected to each adc channel. in quad channel mode and precision mode, any input can be assigned to any adc channel. t he switching of inputs can be done during normal operation, and no additional actions are needed. t he switching will occur instantaneously at the end of each s pi command. t able 8: a d c i nput select inp_sel_adcx<4:0> selected input 0001 0 ip1/in1 0010 0 ip2/in2 0100 0 ip3/in3 1000 0 ip4/in4 other do not use c r o s s p o i n t s w i t c h ( a n a lo g m u x ) a d c 1 < 4 : 1 > i p 1 / i n 1 i n p _ s e l _ a d c 1 < 4 :1 > a d c 2 < 4 : 1 > i p 2 / i n 2 i n p _ s e l _ a d c 2 < 4 :1 > a d c 3 < 4 : 1 > i p 3 / i n 3 i n p _ s e l _ a d c 3 < 4 :1 > a d c 4 < 4 : 1 > i p 4 / i n 4 i n p _ s e l _ a d c 4 < 4 :1 > figure 10: adc input signals through cross point s witch
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 19 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter full-scale control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address fs_cntrl <5:0> fine adjust adc full scale range 0% change x x x x x x 0x55 t he full-scale voltage range of HMCAD1520 can be adjusted using an internal 6-bit dac controlled by the fs_cntrl register. changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. t his leads to a maximum range of 10% adjustment. t able 9 shows how the register settings correspond to the full-scale range. n ote that the values for full-scale range adjustment are approximate. t he dac is, however, guaranteed to be monotonous. t he full-scale control and the programmable gain features differ in two major ways: 1. t he full-scale control function is an analog, whereas the programmable gain is a digital function. 2. t he programmable gain function has much coarser gain steps and larger range compared to the full-scale control function. t able 9: r egister v alues with corresponding change in full-scale r ange fs_cntrl<5:0> full-scale range adjustment 111111 9.7 % 111110 9.4 % 100001 0.3 % 100000 0% 011111 -0.3 % 000001 ?9,7% 000000 ?10,0% current control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address adc_curr <2:0> adc current scaling. nominal x x x 0x50 ext_vcm_bc <1:0> v cm buffer driving strength control nominal x x t here are two registers that impact performance and power dissipation. t he adc_curr register scales the current consumption in the adc core. t he performance is guaranteed at the nomi - nal setting. lower power consumption can be achieved by reducing the adc_curr value, see table 10. t he impact on performance will depend on the adc sampling rate.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 20 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 10: a d c current control settings adc_curr<2:0> adc core current 100 -40% 101 -30% 110 -20% 111 -10% 000 (default) nominal 001 do not use 010 do not use 011 do not use t he ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the v cm pin. if this pin is not in use, the buffer can be switched off. if current is drawn from the v cm pin, the driving strength can be increased to keep the voltage on this pin at the correct level. t able 11: e xternal common mode v oltage buffer d riving strength ext_vcm_bc<1:0> vcm buffer driving strength [a] max current sinked/sourced from vcm pin with < 20 mv voltage change. 00 o ff (v cm foating) 01 (default) 20 10 400 11 700 start-up and clock jitter control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address startup_ctrl <2:0> controls start-up time '000' x x x 0x56 jitter_ctrl <7:0> clock jitter adjustment 160 fsrms x x x x x x x x 0x30 t o optimize start up time, a register is provided where the start-up time in clock cycles can be set. s ome internal cir - cuitry have start up times that are clock frequency independent. default counter values are set to accommodate these start up times at the maximum clock frequency (sampling rate). t his will lead to increased start up times at low clock frequencies. s etting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better ft the actual start up time, such that the start up time will be reduced. t he start up times from power down and sleep modes are changed by this register setting. if the clock divider is used (set to other than 1), the input clock frequency must be divided by the divider factor to fnd the correct clock frequency range (see table 7).
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 21 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 12: start- u p t ime control settings precision mode quad channel C high speed startup_ ctrl<2:0> clock fre - quency range [msps] startup delay [clock cycles] startup delay [s] startup_ ctrl<2:0> clock fre - quency range [msps] startup delay [clock cycles] startup delay [s] 100 80 - 125 1536 12.3 - 19.2 100 160 - 250 3072 12.3 C 19.2 000 50 - 80 992 12.4 - 19.8 000 100 - 160 1984 12.4 - 19.8 001 32,5 - 50 640 12.8 - 19.7 001 65 - 100 1280 12.8 - 19.7 010 20 - 32,5 420 12.9 - 21 010 40 - 65 840 12.9 - 21 011 15 - 20 260 13 - 17.3 011 30 - 40 520 13 - 17.3 other do not use - - other do not use - - dual channel C high speed single channel C high speed startup_ ctrl<2:0> clock fre - quency range [msps] startup delay [clock cycles] startup delay [s] startup_ ctrl<2:0> clock fre - quency range [msps] startup delay [clock cycles] startup delay [s] 100 320 - 500 6144 12.3 C 19.2 100 640 - 1000 12288 12.3 C 19.2 000 200 - 320 3968 12.4 - 19.8 000 400 - 640 7936 12.4 - 19.8 001 130 C 200 2560 12.8 - 19.7 001 260 - 400 5120 12.8 - 19.7 010 80 - 130 1680 12.9 - 21 010 160 - 260 3360 12.9 - 21 011 60 C 80 1040 13 - 17.3 011 120 - 160 2080 13 - 17.3 other do not use - - other do not use - - jitter_ctrl<7:0> allows the user to set a trade-off between power consumption and clock jitter. if all bits in the register is set low, the clock signal is stopped. t he clock jitter depends on the number of bits set to 1 in the jitter_ctrl<7:0> register. which bits are set high does not affect the result. t able 13: clock jitter p erformance number of bits to 1 in jitter_ctrl<7:0> clock jitter performance precision mode [fsrms] clock jitter performance high speed modes [fsrms] module current consumption [ma] 1 130 160 1 2 100 150 2 3 92 136 3 4 85 130 4 5 82 126 5 6 80 124 6 7 77 122 7 8 75 120 8 0 clock stopped clock stopped
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 22 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter lvd s o utput confguration and control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address lvds_output_ mode <2:0> s ets the number of l vds output bits. 12 bit x x x 0x53 low_clk_freq low clock frequency used. inactive x lvds_ advance advance l vds data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay l vds data bits and frame clock by one clock cycle inactive x 0 phase_ ddr<1:0> controls the phase of the lclk output relative to data. 90 degrees x x 0x42 btc_mode binary two's comple - ment format for adc output data. s traight offset binary x 0x46 msb_frst s erialized adc output data comes out with ms b frst. l s b frst x t he HMCAD1520 serial l v d s output has four different modes selected by the register lvds_output_mode as defned in table 14. power down mode, as described in section s tartup initialization, must be activated after or during a change in the number of output bits to ensure correct behavior. t able 14: n umber of bits in lvd s o utput lvds_output_mode <2:0> number of bits comment 000 8 bit 8 bit mode, up to 1 g s p s ( s ee hmcad1511 datasheet) 001 12 bit r ecommended setting for high s peed modes (default) 101 14 bit r ecommended setting up to 70 m s p s (precision mode) 011 16 bit 100 dual 8 bit r ecommended setting above 70 m s p s (precision mode) o ther do not use 12-bit l v d s mode is default for all operational modes. if another l v d s mode is to be used, the lvds_output_mode register setting must be changed accordingly. when 8-bit l v d s mode is used, the l s bs are truncated and the data output will have 8-bit resolution. s ee hmcad1511 and hmcad1510 for detailed description. when 14 or 16 bit l v d s output mode is selected the output data will be a 13 bit left justifed word flled up with 0s on the l s b side. t he different high speed modes uses the l v d s outputs as defned by table 15.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 23 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 15: high speed modes and u se of lvd s o utputs high speed modes/ channels lvds outputs used s ingle channel d1a, d1b, d2a, d2b, d3a, d3b, d4a, d4b dual channel, channel 1 d1a, d1b, d2a, d2b dual channel, channel 2 d3a, d3b, d4a, d4b quad channel, channel 1 d1a, d1b quad channel, channel 2 d2a, d2b quad channel, channel 3 d3a, d3b quad channel, channel 4 d4a, d4b for the 14-bit precision mode 14, 16 or dual 8-bit l v d s mode should be used. if the default 12-bit l v d s mode is used, the data output will be truncated to 12 bit. if the 16-bit l v d s mode is used the data output will be a 14-bit left justifed word flled up with 00 on the l s b side. if the dual 8-bit output mode is used the 8 most signifcant bit of the 14 bit data word will be available on the l v d s a output and the remaining 6 bit will be left justifed and flled up with 00 on the l v d s b output, see table 16. t able 16: p recision mode and u se of lvd s o utputs precision mode l v d s outputs used channel 1 - 12, 14, 16-bit output d1a (d1b will be in power down C high z) channel 1 - dual 8-bit output d1a, d1b channel 2 - 12, 14, 16-bit output d2a (d2b will be in power down C high z) channel 2 - dual 8-bit output d2a, d2b channel 3 - 12, 14, 16-bit output d3a (d3b will be in power down C high z) channel 3 - dual 8-bit output d3a, d3b channel 4 - 12, 14, 16-bit output d4a (d4b will be in power down C high z) channel 4 - dual 8-bit output d4a, d4b maximum data output bit-rate for the HMCAD1520 is 1 gb/s. t he maximum sampling rate for the different confgura - tions is given by table 17. t he sampling rate is set by the frequency of the input clock (f s ). t he frame-rate, i.e. the frequency of the fclk signal on the l v d s outputs, depends on the selected mode and the sampling frequency (f s ) as defned in table 18. t able 17: maximum sampling r ate vs n umber of o utput bits for d ifferent hmca d 1520 confgurations number of bits single channel high speed [msps] dual channel high speed [msps] quad channel high speed [msps] quad channel precision [msps] 8 1000 500 250 - 12 660 330 165 82.5 14 560 280 140 70 16 500 250 125 62.5 dual 8 - - - 125
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 24 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 18: o utput d ata frame r ate mode of operation frame-rate (fclk frequency) high speed, single channel f s / 8 high speed, dual channel f s / 4 high speed, quad channel f s / 2 precision mode f s if the HMCAD1520 device is used at a low sampling rate the register bit low_clk_freq has to be set to 1. s ee table 19 for when to use this register bit for the different modes of operation. t able 19: u se of r egister bit low_clk_freq mode of operation limit when low_clk_freq should be activated high speed, single channel f s < 240 mhz high speed, dual channel f s < 120 mhz high speed, quad channel f s < 60 mhz precision mode f s < 30 mhz t o ease timing in the receiver when using multiple HMCAD1520, the device has the option to adjust the timing of the output data and the frame clock. t he propagation delay with respect to the adc input clock can be moved one l v d s clock cycle forward or backward, by using lvds_delay and lvds_advance , respectively. s ee fgure 11 for details. n ote that lclk is not affected by lvds_delay or lvds_advance settings. d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 n n n n n n n n n n n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 i npu t c l oc k lclk p lclk n f clk p f cl k n d xx x d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 n n n n n n n n n n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 f clk p f cl k n d xx x d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 n n n n n n n n n n n n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 f clk p f c lk n d xx x lvds_delay = ' 1 ' : lvds_advance = ' 1 ' : default : t l vd s d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 t l vd s t l v d s t pr o p t pr o p t pr o p figure 11: l v d s output timing adjustment
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 25 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t he l v d s output interface of HMCAD1520 is a dd r interface. t he default setting is with the lclk rising and falling edge transitions in the middle of alternate data windows. t he phase for lclk can be programmed relative to the output frame clock and data bits using phase_ddr<1:0>. t he lclk phase modes are shown in fgure 12. t he default timing is identical to setting p hase_ddr<1:0>=10. f cl k n f cl k p lclk p lcl k n d xx < 1: 0> f cl k n f cl k p lclk p lclk n d xx < 1: 0> f clk n f clk p lclk p lclk n d x x < 1 :0 > f clk n f clk p l cl k p lclk n d x x < 1 :0 > p h ase _ ddr<1: 0>='00' (270 deg) p h ase _ ddr<1: 0>='10' (90 deg) p h ase _ ddr<1: 0>='01' (180 deg) p ha s e _ddr< 1 : 0 >=' 1 1 ' ( 0 de g ) figure 12: phase programmability modes for lclk t he default data output format is offset binary. t wos complement mode can be selected by setting the btc_mode bit to 1 which inverts the m s b. t he frst bit of the frame (following the rising edge of fclkp) is the l s b of the adc output for default settings. programming the msb_frst mode results in reverse bit order, and the m s b is output as the frst bit following the fclkp rising edge. lvd s d rive strength p rogrammability name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address ilvds_lclk <2:0> l vds current drive programmability for lclkp and lclkn pins. 3.5 ma drive x x x 0x11 ilvds_frame <2:0> l vds current drive programmability for fclkp and fclkn pins. 3.5 ma drive x x x ilvds_dat <2:0> l vds current drive program- mability for output data pins. 3.5 ma drive x x x t he current delivered by the l v d s output drivers can be confgured as shown in table 20. t he default current is 3.5ma, which is what the l v d s standard specifes. t he l v d s interface offers good robustness at the rs d s ( r educed s wing differential s ignaling), given a careful l v d s wire layout. using the 1.5ma rs d s will reduce the power consumption signifcantly compared to default 3.5ma l v d s . s etting the ilvds_lclk<2:0> register controls the current drive strength of the l v d s clock output on the lclkp and lclk n pins. s etting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the fclkp and fclk n pins. s etting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the d[8:1]p and d[8:1] n pins.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 26 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 20: lvd s o utput d rive strength for l c l k, fc l k and d ata ilvds_*<2:0> lvds drive strength 000 3.5 ma (default) 001 2.5 ma 101 1.5 ma ( rs d s ) 011 0.5 ma 100 7.5 ma 101 6.5 ma 110 5.5 ma 111 4.5 ma lvd s i nternal t ermination p rogrammability name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address en_lvds_term e nables internal termination for l vds buffers. t ermination disabled x 0x12 term_lclk <2:0> programmable termination for lclk n and lclkp buffers. t ermination disabled 1 x x x term_frame <2:0> programmable termination for fclk n and fclkp buffers. t ermination disabled 1 x x x term_dat <2:0> programmable termination for output data buffers. t ermination disabled 1 x x x t he off-chip load on the l v d s buffers may represent a characteristic impedance that is not perfectly matched with the pcb traces. t his may result in refections back to the l v d s outputs and loss of signal integrity. t his effect can be mitigated by enabling an internal termination between the positive and negative outputs of each l v d s buffer. internal termination mode can be selected by setting the en_lvds_term bit to 1. o nce this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. t able 21 shows how the internal termination of the l v d s buffers are programmed. t he values are typical values and can vary by up to 20% from device to device and across temperature. t able 21: lvd s o utput i nternal t ermination for l c l k, fc l k and d ata term_*<2:0> lvds internal termination 000 t ermination disabled 001 260 010 150 011 94 100 125 101 80 110 66 111 55
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 27 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter p ower mode control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address sleep4_ch <4:1> channel-specifc sleep mode for a quad channel setup. inactive x x x x 0x0f sleep2_ch <2:1> channel-specifc sleep mode for a dual channel setup. inactive x x sleep1_ch1 channel-specifc sleep mode for a single channel setup. inactive x sleep go to sleep-mode. inactive x pd go to power-down. inactive x pd_pin_cfg <1:0> confgures the pd pin function. pd pin confgured for power-down mode x x lvds_pd_ mode controls l vds power down mode high z-mode x 0x52 t he HMCAD1520 device has several modes for power management, from sleep modes with short start up time to full power down with extremely low power dissipation. t here are two sleep modes, both with the l v d s clocks (fclk, lclk) running, such that the synchronization with the receiver is maintained. t he frst is a light sleep mode (sleep*_ ch) with short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down. s etting sleep4_ch = 1 sets channel in a quad channel setup in sleep mode, setting sleep2_ch = 1 sets channel in a dual channel setup in sleep mode and at last setting sleep1_ch1 = 1 sets the adc channel in a s ingle channel setup in sleep mode. t his is a light sleep mode with short start up time. s etting sleep = 1, puts all channels to sleep, but keeps fclk and lclk running to maintain l v d s synchronization. t he start up time is the same as for complete power down. power consumption is signifcantly lower than for setting all channels to sleep by using the sleep*_channel register. s etting pd = 1 completely powers down the chip, including the band-gap reference circuit. s tart-up time from this mode is signifcantly longer than from the sleep*_channel mode. t he synchronization with the l v d s receiver is lost since lclk and fclk outputs are put in high-z mode. s etting pdn_pin_cfg<1:0> = x1 confgures the circuit to enter sleep channel mode (all channels off) when the pd pin is set high. t his is equal to setting all channels to sleep by using sleep*_ch. t he channels can not be powered down separately using the pd pin. s etting pdn_pin_cfg<1:0> = 10 confgures the circuit to enter (deep) sleep mode when the pd pin is set high (equal to setting sleep=1). when pdn_pin_cfg <1:0>= 00, which is the default, the circuit enters the power down mode when the pd pin is set high. t he lvds_pd_mode register confgures whether the l v d s data output drivers are powered down or kept alive in sleep and sleep channel modes. lclk and fclk drivers are not affected by this register, and are always on in sleep and sleep channel modes. if lvds_pd_mode is set low (default), the l v d s output is put in high z mode, and the driver is completely powered down. if lvds_pd_mode is set high, the l v d s output is set to constant 0, and the driver is still on during sleep and sleep channel modes.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 28 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter p rogrammable g ain name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address coarse_gain _cfg confgures the coarse gain setting x-gain enabled x 0x33 fne_gain_en e nable use of fne gain. disabled x cgain4_ch1 <3:0> programmable coarse gain channel 1 in a quad channel setup. 1x gain x x x x 0x2a cgain4_ch2 <3:0> programmable coarse gain channel 2 in a quad channel setup. 1x gain x x x x cgain4_ch3 <3:0> programmable coarse gain channel 3 in a quad channel setup. 1x gain x x x x cgain4_ch4 <3:0> programmable coarse gain channel 4 in a quad channel setup. 1x gain x x x x cgain2_ch1 <3:0> programmable coarse gain channel 1 in a dual channel setup. 1x gain x x x x 0x2b cgain2_ch2 <3:0> programmable coarse gain channel 2 in a dual channel setup. 1x gain x x x x cgain1_ch1 <3:0> programmable coarse gain channel 1 in a s ingle channel setup. 1x gain x x x x fgain_ branch1<6:0> programmable fne gain for branch1. 1x / 0db gain x x x x x x x 0x34 fgain_ branch2<6:0> programmable fne gain for branch 2. 1x / 0db gain x x x x x x x fgain_ branch3<6:0> programmable fne gain for branch 3. 1x / 0db gain x x x x x x x 0x35 fgain_ branch4<6:0> programmable fne gain for branch 4. 1x / 0db gain x x x x x x x fgain_ branch5<6:0> programmable fne gain for branch 5. 1x / 0db gain x x x x x x x 0x36 fgain_ branch6<6:0> programmable fne gain for branch 6. 1x / 0db gain x x x x x x x fgain_ branch7<6:0> programmable fne gain for branch 7. 1x / 0db gain x x x x x x x 0x37 fgain_ branch8<6:0> programmable fne gain for branch 8. 1x / 0db gain x x x x x x x t he device includes a digital programmable gain in addition to the full-scale control. t he programmable gain of each channel can be individually set using a four bit code, indicated as cgain*<3:0>. t he gain is confgured by the register cgain_cfg, when cgain_cfg equals 0 a gain in db steps is enabled as defned in table 22 otherwise if cgain_cfg equals 1 the gain is defned by table 23.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 29 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 22: g ain setting C db step cgain_cfg cgain*<3:0> implemented gain [db] 0 0000 0 0 0001 1 0 0010 2 0 0011 3 0 0100 4 0 0101 5 0 0110 6 0 0111 7 0 1000 8 0 1001 9 0 1010 10 0 1011 11 0 1100 12 0 1101 n ot used 0 1110 n ot used 0 1111 n ot used t able 23: g ain setting C x step cgain_cfg cgain*<3:0> implemented gain factor [x] 1 0000 1 1 0001 1.25 1 0010 2 1 0011 2.5 1 0100 4 1 0101 5 1 0110 8 1 0111 10 1 1000 12.5 1 1001 16 1 1010 20 1 1011 25 1 1100 32 1 1101 50 1 1110 not used 1 1111 not used t here is a digital fne gain implemented for each adc branch to adjust the fne gain errors between the branches. t he gain is controlled by fgain_branch* as defned in table 24. for the high speed interleaved modes, there will be no missing codes when using digital fne gain, due to higher resolution internally (1 bit). t o enable the fne gain function the register bit fne_gain_en has to be activated, set to 1.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 30 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 24: fine g ain setting fgain_branchx<6:0> arithmetic function implemented gain (x) gain (db) 0 1 1 1 1 1 1 o u t = (1 + 2 -8 + 2 -9 + 2- 10 + 2 -11 + 2 -12 + 2 -13 ) * i n 1.0077 0.0665 0 1 1 1 1 1 0 out = (1 + 2 -8 + 2 -9 + 2 -10 + 2 -11 + 2 -12 ) * in 1.0076 0.0655 0 1 1 1 1 0 1 out = (1 + 2 -8 + 2 -9 + 2 -10 + 2 -11 + 2 -13 ) * in 1.0074 0.0644 0 1 1 1 1 0 0 out = (1 + 2 -8 + 2 -9 + 2 -10 + 2 -11 ) * in 1.0073 0.0634 0 0 0 0 0 1 1 out = (1 + 2 -12 + 2 -13 ) * in 1.0004 0.0031 0 0 0 0 0 1 0 out = (1 + 2 -12 ) * in 1.0002 0.0021 0 0 0 0 0 0 1 out = (1 + 2 -13 ) * in 1.0001 0.0010 0 0 0 0 0 0 0 out = in 1.0000 0.0000 1 1 1 1 1 1 1 out = in 1.0000 0.0000 1 1 1 1 1 1 0 out = (1 - 2 -13 ) * in 0.9999 -0.0011 1 1 1 1 1 0 1 out = (1 - 2 -12 ) * in 0.9998 -0.0021 1 1 1 1 1 0 0 out = (1 - 2 -12 - 2 -13 ) * in 0.9996 -0.0032 1 0 0 0 0 1 1 out = (1 - 2 -8 - 2 -9 - 2 -10 - 2 -11 ) * in 0.9927 -0.0639 1 0 0 0 0 1 0 out = (1 - 2 -8 - 2 -9 - 2 -10 - 2 -11 - 2 -13 ) * in 0.9926 -0.0649 1 0 0 0 0 0 1 out = (1 - 2 -8 - 2 -9 - 2 -10 - 2 -11 - 2 -12 ) * in 0.9924 -0.0660 1 0 0 0 0 0 0 out = (1 - 2 -8 - 2 -9 - 2 -10 - 2 -11 - 2 -12 - 2 -13 ) * in 0.9923 -0.0670 analog i nput i nvert name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address invert4_ch <4:1> channel specifc swapping of the analog input signal for a quad channel setup. ipx is positive input x x x x 0x24 invert2_ch <2:1> channel specifc swapping of the analog input signal for a dual channel setup. ipx is positive input x x invert1_ch1 channel specifc swapping of the analog input signal for a s ingle channel setup. ipx is positive input x t he ipx pin represents the positive analog input pin, and i n x represents the negative (complementary) input. s etting the bits marked invertx_ch (individual control for each channel) causes the inputs to be swapped. i n x would then represent the positive input, and ipx the negative input.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 31 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter lvd s t est p atterns name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address en_ramp e nables a repeating full-scale ramp pattern on the outputs. inactive x 0 0 0x25 dual_ custom_pat e nable the mode wherein the output toggles between two defned codes. inactive 0 x 0 single_ custom_pat e nables the mode wherein the output is a constant specifed code. inactive 0 0 x bits_custom1 <15:0> bits for the single custom pattern and for the frst code of the dual custom pattern. <0> is the l s b. 0x0000 x x x x x x x x x x x x x x x x 0x26 bits_custom2 <15:0> bits for the second code of the dual custom pattern. 0x0000 x x x x x x x x x x x x x x x x 0x27 pat_deskew e nable deskew pattern mode. inactive 0 x 0x45 pat_sync e nable sync pattern mode. inactive x 0 t o ease the l v d s synchronization setup of HMCAD1520, several test patterns can be set up on the outputs. n ormal adc data are replaced by the test pattern in these modes. s etting en_ramp to 1 sets up a repeating full-scale ramp pattern on all data outputs. t he ramp starts at code zero and is increased 1l s b every clock cycle. it returns to zero code and starts the ramp again after reaching the full-scale code. a constant value can be set up on the outputs by setting single_custom_pat to 1, and programming the desired value in bits_custom1<15:0>. in this mode, bits_custom1<15:0> replaces the adc data at the output, and is controlled by l s b-frst and m s b-frst modes in the same way as normal adc data are. t he device may also be set up to alternate between two codes by programming dual_custom_pat to 1. t he two codes are the contents of bits_custom1<15:0> and bits_custom2<15:0>. s ince bit_custom*<15:0> is a 16 bit word there will be a truncation at the l s b side when using less than 16 bits in the l v d s output word. if 12-bit output is selected bit <15:4> will be used, if 14-bit output is used bit <15:2> will be used and if dual 8-bit is selected bit<15:8> will be put on the l v d s a output and bit <7:0> will be put on the l v d s b output. t wo preset patterns can also be selected: 1. deskew pattern: s et using pat_deskew, this mode replaces the adc output with a pattern consisting of alter - nating zeros and ones - m s b will be a zero. for a 12-bit output the pattern will be: 010101010101 2. s ync pattern: s et using pat_sync, the normal adc word is in this mode replaced by a fxed synchronization pattern where the output word is split in two and the upper part of the word is ones and the lower part is zeros. for a 12-bit output the pattern will be: 111111000000. n ote: o nly one of the above patterns should be selected at the same time.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 32 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t heory of o peration HMCAD1520 is a multi-mode high-speed, cm os adc, consisting of 8 adc branches, confgured in different channel modes, using interleaving to achieve high speed sampling. for all practical purposes, the device can be considered to contain 4 adcs. fine gain is adjusted for each of the eight branches separately. HMCAD1520 utilizes a l v d s output, described in r egister description, l v d s o utput confguration and control. t he clocks needed (fclk, lclk) for the l v d s interface are generated by an internal pll. t he HMCAD1520 operate from one clock input, which can be differential or single ended. t he sampling clocks for each of the four channels are generated from the clock input using a carefully matched clock buffer tree. internal clock dividers are utilized to control the clock for each adc during interleaving. t he clock tree is controlled by the mode of operations. HMCAD1520 uses internally generated references. t he differential reference value is 1 v . t his results in a differential input of ?1 v to correspond to the zero code of the adc, and a differential input of +1 v to correspond to the maximum code. t he adc employs a pipeline converter architecture. each pipeline s tage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes. HMCAD1520 operates from two sets of supplies and grounds. t he analog supply and ground set is identifed as a v dd and a vss , while the digital set is identifed by d v dd and d vss . interleaving effects and sampling order interleaving adcs will generate interleaving artifacts caused by gain, offset and timing mismatch between the adc branches. t he design of HMCAD1520 has been optimized to minimize these effects. it is not possible, though, to eliminate mismatch, such that additional compensation may be needed. t he internal digital fne gain control may be used to compensate for gain errors between the adc branches. due to the optimization of HMCAD1520 there is not a one- to-one correspondence between the sampling order, l v d s output order and the branch number. t ables 25, 26 and 27 give an overview of the corresponding branches, l v d s outputs and sampling order for the different high speed modes. t able 25: quad channel mode channel # sampling order lvds output fine gain branch 1 1 d1a 1 2 d1b 2 2 1 d2a 3 2 d2b 4 3 1 d3a 5 2 d3b 6 4 1 d4a 7 2 d4b 8 t able 26: d ual channel mode channel # sampling order lvds output fine gain branch 1 1 d1a 1 2 d1b 3 3 d2a 2 4 d2b 4 2 1 d3a 5 2 d3b 7 3 d4a 6 4 d4b 8 t able 27: single channel mode channel # sampling order lvds output fine gain branch 1 1 d1a 1 2 d1b 6 3 d2a 2 4 d2b 5 5 d3a 8 6 d3b 3 7 d4a 7 8 d4b 4 precision mode in precision mode the resolution of each adc channel is increased from 12 bits to 14 bits. in order to get the additional performance, the l v d s outputs have to be set up in 14, 16 or dual 8-bit confguration. when digital fne gain (registers 34-37hex) is used in precision mode, the mapping between adc channel and adc branch in table 28 should be used.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 33 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter t able 28: o verview of fine g ain u sage in p recision mode channel # lvds output fine gain branch 1 d1a, (d1b) 1 2 d2a, (d2b) 3 3 d3a, (d3b) 5 4 d4a, (d4b) 7 analog input t he analog input to HMCAD1520 is a switched capacitor track-and-hold amplifer optimized for differential operation. o peration at common mode voltages at mid supply is recommended even if performance will be good for the ranges specifed. the v cm pin provides a voltage suitable as common mode voltage reference. t he internal buffer for the v cm voltage can be switched off, and driving capabilities can be changed programming the ext_vcm_bc<1:0> register. trac k trac k trac k trac k ho l d ho l d i n x i p x figure 13: input confguration figure 13 shows a simplifed drawing of the input network. t he signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. t he resistors form a low pass flter with the capacitor, and values must therefore be determined by requirements for the application. dc-coupling figure 14 shows a recommended confguration for dc-coupling. n ote that the common mode input voltage must be controlled according to specifed values. preferably, the cm_ e x t output should be used as reference to set the common mode voltage. i p x inx c m _ ex t inpu t inpu t a m p li f i e r 43 ? 43 ? 33 p f figure 14: dc coupled input t he input amplifer could be inside a companion chip or it could be a dedicated amplifer. s everal suitable single ended to differential driver amplifers exist in the market. t he system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with HMCAD1520 input specifcations. detailed confguration and usage instructions must be found in the documentation of the selected driver, and the values given in fgure 14 must be varied according to the recommendations for the driver. ac-coupling i p x inx c m _ ex t inpu t 33 ? 33 ? r t 4 7 ? figure 15: t ransformer coupled input a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 15 shows a recommended confguration using a transformer. make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. t he bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 performance. t his type of transformer coupled input is the preferred confguration for high frequency signals as most differential amplifers do not have adequate performance at high frequencies.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 34 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are refected and will add to the input signal at the adc input. t his could reduce the adc performance. t o avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. i p x inx c m _ ex t 2 2 ? 2 2 ? 22 p f c i c i r c m r c m i nn x inp x figure 16: ac coupled input figure 16 shows ac-coupling using capacitors. r esistors from the cm_ e x t output, r cm, should be used to bias the differential input signals to the correct voltage. t he series capacitor, ci, form the high- pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. n ote that s tart up t ime from s leep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. clock input and jitter considerations t ypically high-speed adcs use both clock edges to generate internal timing signals. in HMCAD1520 only the rising edge of the clock is used. hence, input clock duty cycles between 30% and 70% are acceptable. t he input clock can be supplied in a variety of formats. t he clock pins are ac-coupled internally, hence a wide common mode voltage range is accepted. differential clock sources such as l v d s , l v p e cl or differential sine wave can be utilized. l v d s /l v p e cl clock signals must be appropriately terminated as close as possible to the adc clock input pins. for cm os inputs, the clk n pin should be connected to ground, and the cm os clock signal should be connected to clkp. cm os inputs are not recommended above 200mhz. for differential sine wave clock input the amplitude must be at least +/- 0.8 v pp. n o additional confguration is needed to set up the clock source format. t he quality of the input clock is extremely important for high-speed, high-resolution adcs. t he contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1. sn r jit t e r = 20 ? log 2 ? ? f i n ? t (1) where f i n is the signal frequency, and t is the total rms jitter measured in seconds. t he rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. t his can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifcations) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. t he jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with l v d s or l v p e cl clock with fast edges. cm os and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. lvds output frequencies t he relationship between l v d s bitrate and sampling frequency is: l v d s bitrate = f s / n b * n _lvds where: f s is the sampling frequency. n _lvds is number of output bits on the l v d s interface. n b is given by:
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 35 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter s ingle channel mode: 8 dual channel mode: 4 quad channel mode: 2 if the input clock divider is used f s is given by: f s = f_clk / clock divide factor t he lclk frequency is given by: f_lclk = l v d s bitrate/2 application u sage e xample t his section gives an overview on how HMCAD1520 can be used in an application utilizing all active modes with a single clock source. t he example assumes that a low jitter 500mhz clock source is applied. a differential clock should be used, and can be generated from a single ended low jitter crystal oscillator, using a transformer or balun in conjunction with ac-coupling to convert from single ended to differential signal. s ince the resolution is 12 bits in the high speed modes and 14 bits in precision mode, it will be an advantage to set the l v d s outputs to 14 or 16 bits to avoid changing the l v d s interface when going from one of the high speed modes to precision mode or vice versa. t he extra bits added in the l s b position of the transferred word can simply be removed in the receiver. in this example 14 bit l v d s is chosen. start-up initialization t he start-up sequence will be as follows: ? apply power ? apply reset ( resetn low, then high, or s pi com - mand 0x00 0x0001) ? s et power down (pd pin high or s pi command 0x0f 0x0200) ? s et 14bit l v d s output mode ( s pi command 0x53 0x0002) ? s et l v d s bit clock phase (phase_ddr, register 0x42)) if other than default must be used (depends on the receiver). ? s elect operating mode, for instance dual channel high speed mode, and clock divider factor ( s pi command 0x31 0x0102). ? s et active mode (pd pin low or s pi command 0x0f 0x0000) ? s elect analog inputs, for instance input 1 on chan - nel 1 and input 3 on channel 2 ( s pi commands 0x3a 0202 and 0x3b 0808) change mode when changing operational mode, power down must be activated due to internal synchronization routines. a typical mode change will then be like this: ? s et power down (pd pin high or s pi command 0x0f 0x0200) ? change mode to for example s ingle channel mode ( s pi command 0x31 0x0001) ? s et active mode (pd pin low or s pi command 0x0f 0x0000) ? s elect analog inputs, for instance input 1 ( s pi commands 0x3a 0202 and 0x3b 0202) t able 29 gives an overview of the operational modes in this example and the s pi commands to apply for each mode. t able 29: o verview of o perating modes and setup conditions operating mode sampling speed [msps] clock divider factor spi command for mode selection and clock divider s ingle channel 500 1 0x31 0x0001 dual channel 250 2 0x31 0x0102 quad channel 125 4 0x31 0x0204 quad channel precision 62.5 8 0x31 0x0308 select analog input when an operational mode is selected, the analog inputs can be changed on-the-fy. t o change analog input one merely have to apply the dedicated s pi commands. t he change will occur instantaneously at the end of each s pi command. t able 30: e xample of some analog i nput selections operating mode signal input selection spi commands single channel ip4/in4 0x3a 1010, 0x3b 1010 dual channel ch1: ip2/i n2 ch2: ip3/i n3 0x3a 0404, 0x3b 0808 quad channel ch1: ip4/i n4 ch2: ip3/i n3 ch3: ip2/i n2 ch4: ip1/i n1 0x3a 1008, 0x3b 0402 quad channel precision ch1: ip1/i n1 ch2: ip2/i n2 ch3: ip3/i n3 ch4: ip4/i n4 0x3a 0204, 0x3b 0810
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 36 HMCAD1520 v03.0711 hig h speed multi-mode 8/12/14-bit 1000/640/105 ms p s a/ d converter o utline d rawing t able 28: 7x7 mm qf n 48 p in ( lp 7) d imensions s ymbol millimeter inch min t yp max min t yp max a 0.8 0.9 1 0.031 0.035 0.039 a1 0 0.02 0.05 0 0.0008 0.002 a2 0.2 0.008 b 0.18 0.25 0.3 0.007 0.01 0.012 d 7.00 bsc 0.276 bsc d2 5.15 5.3 5.4 0.203 0.209 0.213 l 0.3 0.4 0.5 0.012 0.016 0.02 e 0.50 bsc 0.020 bsc f 0.2 0.008 p ackage i nformation part number package body material lead finish msl [1] package marking [2] HMCAD1520 r oh s -compliant low s tress injection molded plastic 100% matte s n level 2a had1520 xxxx [1] m s l, peak t emp: t he moisture sensitivity level rating classifed according to the j e d e c industry standard and to peak solder temperature. [2] proprietary marking xxxx, 4-digit lot number xxxx

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