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enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b revision: v1.10 date: ?a? 0?? ?01? ?a? 0?? ?01?
rev. 1.10 ? ?a? 0?? ?01? rev. 1.10 3 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu table of contents eates cpu features ......................................................................................................................... 6 peripheral features ................................................................................................................. 6 general description ......................................................................................... 7 selection table ................................................................................................. 7 block diagram .................................................................................................. 7 pin assignment ................................................................................................ 8 pin description .............................................................................................. 10 absolute ?aximum ratings .......................................................................... 1? d.c. characteristics ....................................................................................... 1? a.c. characteristics ....................................................................................... 14 adc characteristics ...................................................................................... 15 dac electrical characteristics ..................................................................... 15 power-on reset characteristics ................................................................... 15 s?stem architecture ...................................................................................... 16 clocking and pipelining ......................................................................................................... 16 program counter ................................................................................................................... 17 stack ..................................................................................................................................... 18 arithmetic and logic unit C alu ........................................................................................... 18 program ?emor? ........................................................................................... 19 structure ................................................................................................................................ 19 special vectors ..................................................................................................................... ?0 look-up table ........................................................................................................................ ?0 table program example ........................................................................................................ ?1 data ?emor? .................................................................................................. ?? structure ................................................................................................................................ ?? special purpose data ?emor? ............................................................................................. ?3 special function registers ........................................................................... ?4 indirect addressing registers C iar0 ? iar1 ......................................................................... ?4 ?emor? pointers C ?p0? ?p1 .............................................................................................. ?4 accumulator C acc ............................................................................................................... ?7 program counter low register C pcl .................................................................................. ?7 bank pointer C bp ................................................................................................................. ?7 status register C status .................................................................................................... ?8 input/output ports and control registers ............................................................................. ?9 s?stem control registers C ctrl0? ctrl1? ctrl? ........................................................... 30 wake-up function register C pawk ..................................................................................... 3? pull-high registers C papu ? pbpu? pcpu? pdpu? pepu? pfpu ....................................... 3? software co? register C sco?c ....................................................................................... 3?
rev. 1.10 ? ?a? 0?? ?01? rev. 1.10 3 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu oscillator ........................................................................................................ 32 s?stem oscillator overview .................................................................................................. 3? external cr?stal/resonator oscillator C hxt ........................................................................ 33 external rc oscillator C erc ............................................................................................... 33 internal rc oscillator C hirc ............................................................................................... 34 external 3?768hz cr?stal oscillator C lxt ........................................................................... 34 lxt oscillator low power function ...................................................................................... 35 internal low speed oscillator C lirc ................................................................................... 35 operating modes ........................................................................................... 36 ? ode t ?pes and selection .................................................................................................... 36 ?ode switching ..................................................................................................................... 37 standb? current considerations ........................................................................................... 37 wake-up ................................................................................................................................ 38 watchdog timer operation ................................................................................................... 39 reset and initialisation .................................................................................. 40 reset functions .................................................................................................................... 41 reset initial conditions ......................................................................................................... 43 input/output ports ......................................................................................... 46 pull-high resistors ................................................................................................................ 46 port a wake-up ..................................................................................................................... 46 i/o port control registers ..................................................................................................... 48 pin-shared functions ............................................................................................................ 49 pin remapping confguration ............................................................................................... 50 i/o pin structures .................................................................................................................. 50 programming considerations ................................................................................................ 5? timer/event counters ................................................................................... 52 confguring the timer/event counter input clock source .................................................... 5? timer registers C t ?r0? t?r1? t?r?l? t?r?h ............................................................... 53 timer control registers C t ?r0c? t?r1c? t?r?c ........................................................... 53 timer ?ode ........................................................................................................................... 57 event counter ?ode ............................................................................................................. 57 pulse width capture ?ode ................................................................................................... 58 prescaler ............................................................................................................................... 59 pfd function ........................................................................................................................ 59 i/o interfacing ........................................................................................................................ 60 programming considerations ................................................................................................ 60 timer program example ....................................................................................................... 61 time base ............................................................................................................................. 61 pulse width modulator .................................................................................. 62 pw? operation ..................................................................................................................... 63 6+? pw? ?ode .................................................................................................................... 63 7+1 pw? ?ode .................................................................................................................... 64 pw? output control ............................................................................................................. 65
rev. 1.10 4 ?a? 0?? ?01? rev. 1.10 5 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu analog to digital converter .......................................................................... 66 a/d overview ........................................................................................................................ 66 a/d converter data registers C adrl ? adrh ..................................................................... 66 a/d converter control registers C adcr ? acsr? ancsr1? ancsr0 ................................ 66 a/d input pins ....................................................................................................................... 7? summar? of a/d conversion steps ....................................................................................... 7? programming considerations ................................................................................................ 73 a/d transfer function ........................................................................................................... 73 a/d programming example ................................................................................................... 75 interrupts ........................................................................................................ 77 interrupt register .................................................................................................................. 77 interrupt operation ................................................................................................................ 79 interrupt priorit? ..................................................................................................................... 80 external interrupt ................................................................................................................... 81 timer/event counter interrupt ............................................................................................... 81 ?ulti-function interrupt .......................................................................................................... 81 programming considerations ................................................................................................ 8? lcd scom function ..................................................................................... 83 lcd operation ..................................................................................................................... 83 lcd bias control .................................................................................................................. 84 serial interface module C sim ....................................................................... 85 spi interface ......................................................................................................................... 85 spi registers ........................................................................................................................ 87 spi communication ............................................................................................................. 90 i ? c interface .......................................................................................................................... 9? i ? c registers ......................................................................................................................... 93 i ? c bus communication ........................................................................................................ 97 i ? c bus start signal ............................................................................................................... 98 slave address ....................................................................................................................... 98 i ? c bus read/write signal .................................................................................................... 99 i ? c bus slave address acknowledge signal ......................................................................... 99 i ? c bus data and acknowledge signal ................................................................................. 99 peripheral clock output .............................................................................. 101 peripheral clock operation ................................................................................................. 101 serial interface C spia ................................................................................. 102 spia interface operation .................................................................................................... 10? spia registers ..................................................................................................................... 104 spia communication .......................................................................................................... 106 spia bus enable/disable .................................................................................................... 108 spia operation ................................................................................................................... 108 low voltage detector C lvd ........................................................................ 110 lvd register ........................................................................................................................ 110 lvd operation ...................................................................................................................... 110
rev. 1.10 4 ?a? 0?? ?01? rev. 1.10 5 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu confguration options .................................................................................. 111 application circuit ........................................................................................ 112 instruction set ............................................................................................... 113 introduction .......................................................................................................................... 113 instruction timing ................................................................................................................. 113 ? oving and transferring data .............................................................................................. 113 arithmetic operations ........................................................................................................... 113 logical and rotate operations ............................................................................................. 114 branches and control transfer ............................................................................................ 114 bit operations ...................................................................................................................... 114 table read operations ........................................................................................................ 114 other operations .................................................................................................................. 114 instruction set summar? ...................................................................................................... 115 instruction defnition .................................................................................... 117 package information ................................................................................... 126 ? 8-pin skdip (300mil) outline dimensions ........................................................................ 1?6 ? 8-pin sop (300mil) outline dimensions ........................................................................... 1?7 ? 8-pin ssop (150mil) outline dimensions ......................................................................... 1?8 44-pin qfp (10mmx10mm) outline dimensions ................................................................ 1?9 5? -pin qfp (14mmx14mm) outline dimensions ................................................................ 130 64-pin lqfp (7mmx7mm) outline dimensions .................................................................. 131 reel dimensions ................................................................................................................. 13? carrier tape dimensions ..................................................................................................... 133
rev. 1.10 6 ?a? 0?? ?01? rev. 1.10 7 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu features cpu features ? operating voltage: f sys = 4mhz: 2.2v~5.5v f sys =8mhz: 3.0v~5.5v f sys =12mhz: 4.5v~5.5v ? up to 0.33s instruction cycle with 12mhz system clock at v dd = 5v ? idle/sleep mode and wake-up functions to reduce power consumption ? oscillator types: external high frequency crystal C hxt external rc C erc internal rc C hirc external low frequency crystal C lxt ? four operational modes: normal, slow, idle, sleep ? fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components ? watchdog timer function ? lirc oscillator function for watchdog timer ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 8-level subroutine nesting ? bit manipulation instruction ? low voltage reset function ? low voltage detect function ? wide range of available package types peripheral features ? up to 62 bidirectional i/o lines ? up to 16 channel 12-bit adc ? up to 4 channel 8-bit pwm ? single channel 12-bit dac ? serial interfaces module with dual spi and i 2 c interfaces ? single serial spi interface ? software controlled 4-scom lines lcd com driver with 1/2 bias ? external interrupt input shared with an i/o line ? t wo 8-bit programmable timer/event counter with overfow interrupt and prescaler ? single 16-bit programmable timer/event counter with overfow interrupt ? time-base function ? programmable frequency divider C pfd
rev. 1.10 6 ?a? 0?? ?01? rev. 1.10 7 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu general description the enhanced a/d mcus are a series of 8-bit high performance, risc architecture microcontrollers specifcally designed for a wide range of applications. the usual holtek microcontroller features of low power consumption, i/o fexibility, timer functions, oscillator options, power down and wake- up functions, watchdog timer and low voltage reset, combine to provide devices with a huge range of functional options while still maintaining a high level of cost effectiveness. the fully integrated system oscillator hirc, which requires no external components and which has three frequency selections, opens up a huge range of new application possibilities for these devices, some of which may include industrial control, consumer products, household appliances subsystem controllers, etc. selection table part no. program memory data memory i/o 8-bit timer 16-bit timer time base hirc (mhz) rtc (lxt) lcd scom ht46r068b 16kx16 51?x8 50 ? 1 1 4/8/1? 4 ht46r069b 3?kx16 10?4x8 6? ? 1 1 4/8/1? 4 part no. a/d pwm d/a interface pfd stack package ht46r068b 1?-bitx16 8-bitx4 1?-bitx1 spi/i ? c? spi 8 ?8skdip/sop/ssop 44/5?qfp ht46r069b 1?-bitx16 8-bitx4 1?-bitx1 spi/i ? c? spi 8 44/5?qfp 64lqfp note: "*" the oscillator is connected to the xt1/xt2 pins with tinypower tm design. block diagram the following block diagram illustrates the main functional blocks.

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rev. 1.10 8 ?a? 0?? ?01? rev. 1.10 9 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pin assignment pc 1 / an 5 pe 0 / an 8 pe 1 / an 9 pe ? / an 10 pe 3 / an 11 pe 4 / an 1? pe 5 / an 13 pe 6 / an 14 pe 7 / an 15 pg 0 pg 1 pd 0 / tc ? pd 1 / pw? 3 pc 4 / xt ? pa 7 / res pc 3 / pw? 1 pc ? / pw? ? pd 7 / sdo pd 6 / sdi / sda pd 5 / sck / scl pd 4 / scs pd 3 / pclk pd ? pf 7 pf 6 pf 5 p f 4 p f 3 p f ? p f 1 / s d i a p f 0 / s d o a p b 7 / s c k a p b 6 / s c s a p b 5 p b 4 p b 3 / s c o ? 3 p b ? / s c o ? ? p b 1 / s c o ? 1 p b 0 / s c o ? 0 p c 5 / x t 1 p a 6 / o s c 1 p a 5 / o s c ? v d d v s s p a 4 / p w ? 0 / t c 1 / a u d p a 3 / i n t / a n 3 p a ? / t c 0 / a n ? / v r e f p a 1 / p f d / a n 1 p a 0 / a n 0 p c 6 / a n 6 p c 7 / a n 7 p c 0 / a n 4 1 ? 3 4 5 6 7 8 9 10 11 1? 13 14 15 16 17 18 19 ?0 ?1 ?? 34 35 36 37 38 39 48 49 50 51 5? ?3 ?4 ?5 ?6 ?7 ?8 ?9 30 31 3? 33 40 41 4? 43 44 45 46 47 ht 46 r 068 b 52 qfp - a 1 ? 3 4 5 6 7 8 9 10 11 1? 13 14 15 16 17 18 19 ?0 ?1 ?? ?3 ?4 ?5 ?6 ?7 ?8 ?9 30 31 3? 33 34 35 36 37 38 39 40 41 4? 43 44 p c 5 / x t 1 p a 6 / o s c 1 p a 5 / o s c ? v d d v s s p a 4 / p w ? 0 / t c 1 / a u d p a 3 / i n t / a n 3 p a ? / t c 0 / a n ? / v r e f p a 1 / p f d / a n 1 p a 0 / a n 0 p c 6 / a n 6 pc 7 / an 7 pc 0 / an 4 pc 1 / an 5 pe 0 / an 8 pe 1 / an 9 pe ? / an 10 pe 3 / an 11 pe 4 / an 1? pe 5 / an 13 pe 6 / an 14 pe 7 / an 15 pc 4 / xt ? pa 7 / res pc 3 / pw? 1 pc ? / pw? ? pd 7 / sdo pd 6 / sdi / sda pd 5 / sck / scl pd 4 / scs pd 3 / pclk pd ? pf 1 / sdia p f 0 / s d o a p b 7 / s c k a p b 6 / s c s a p b 5 p b 4 p b 3 / s c o ? 3 p b ? / s c o ? ? p b 1 / s c o ? 1 p b 0 / s c o ? 0 p d 1 / p w ? 3 p d 0 / t c ? ht 46 r 068 b 44 qfp - a vss vdd pa 5 / osc ? pa 6 / osc 1 pc 5 / xt 1 pc 4 / xt ? pa 7 / res pc 3 / pw? 1 pc ? / pw? ? pd 3 / pck pd ? pb 5 pb 4 pb 3 / sco? 3 ?8 ?7 ?6 ?5 ?4 ?3 ?? ?1 ?0 19 18 17 16 15 1 ? 3 4 5 6 7 8 9 10 11 1? 13 14 pa 4 / pw? 0 / tc 1 / aud pa 3 / int pa ? / tc 0 pa 1 / pfd / an 1 pa 0 pc 6 pc 7 pc 0 pc 1 pd 0 / tc ? pd 1 / pw? 3 pb 0 / sco? 0 pb 1 / sco? 1 pb ? / sco? ? ht 46 r 068 b 28 skdip - a / ssop - a / sop - a
rev. 1.10 8 ?a? 0?? ?01? rev. 1.10 9 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu 1 ? 3 4 5 6 7 8 9 10 11 1? 13 14 15 16 17 18 19 ?0 ?1 ?? ?3 ?4 ?5 ?6 ?7 ?8 ?9 30 31 3? 33 34 35 36 37 38 39 40 41 4? 43 44 p c 5 / x t 1 p a 6 / o s c 1 p a 5 / o s c ? v d d v s s p a 4 / p w ? 0 / t c 1 / a u d p a 3 / i n t / a n 3 p a ? / t c 0 / a n ? / v r e f p a 1 / p f d / a n 1 p a 0 / a n 0 p c 6 / a n 6 pc 7 / an 7 pc 0 / an 4 pc 1 / an 5 pe 0 / an 8 pe 1 / an 9 pe ? / an 10 pe 3 / an 11 pe 4 / an 1? pe 5 / an 13 pe 6 / an 14 pe 7 / an 15 pc 4 / xt ? pa 7 / res pc 3 / pw? 1 pc ? / pw? ? pd 7 / sdo pd 6 / sdi / sda pd 5 / sck / scl pd 4 / scs pd 3 / pclk pd ? pf 1 / sdia p f 0 / s d o a p b 7 / s c k a p b 6 / s c s a p b 5 p b 4 p b 3 / s c o ? 3 p b ? / s c o ? ? p b 1 / s c o ? 1 p b 0 / s c o ? 0 p d 1 / p w ? 3 p d 0 / t c ? ht 46 r 069 b 44 qfp - a pc 1 / an 5 pe 0 / an 8 pe 1 / an 9 pe ? / an 10 pe 3 / an 11 pe 4 / an 1? pe 5 / an 13 pe 6 / an 14 pe 7 / an 15 pg 0 pg 1 pd 0 / tc ? pd 1 / pw? 3 pc 4 / xt ? pa 7 / res pc 3 / pw? 1 pc ? / pw? ? pd 7 / sdo pd 6 / sdi / sda pd 5 / sck / scl pd 4 / scs pd 3 / pclk pd ? pf 7 pf 6 pf 5 p f 4 p f 3 p f ? p f 1 / s d i a p f 0 / s d o a p b 7 / s c k a p b 6 / s c s a p b 5 p b 4 p b 3 / s c o ? 3 p b ? / s c o ? ? p b 1 / s c o ? 1 p b 0 / s c o ? 0 p c 5 / x t 1 p a 6 / o s c 1 p a 5 / o s c ? v d d v s s p a 4 / p w ? 0 / t c 1 / a u d p a 3 / i n t / a n 3 p a ? / t c 0 / a n ? / v r e f p a 1 / p f d / a n 1 p a 0 / a n 0 p c 6 / a n 6 p c 7 / a n 7 p c 0 / a n 4 1 ? 3 4 5 6 7 8 9 10 11 1? 13 14 15 16 17 18 19 ?0 ?1 ?? 34 35 36 37 38 39 48 49 50 51 5? ?3 ?4 ?5 ?6 ?7 ?8 ?9 30 31 3? 33 40 41 4? 43 44 45 46 47 ht 46 r 069 b 52 qfp - a pc 1 / an 5 pe 0 / an 8 pe 1 / an 9 pe ? / an 10 pe 3 / an 11 pe 4 / an 1? pe 5 / an 13 pe 6 / an 14 pe 7 / an 15 pg 0 pg 1 pg ? pg 3 pg 4 pg 5 pg 6 pc ? / pw? ? pd 7 / sdo pd 6 / sdi / sda pd 5 / sck / scl pd 4 / scs pd 3 / pclk pd ? ph 5 ph 4 ph 3 ph ? ph 1 ph 0 pf 7 pf 6 pf 5 p f 4 p f 3 p f ? p f 1 / s d i a p f 0 / s d o a p b 7 / s c k a p b 6 / s c s a p b 5 p b 4 p b 3 / s c o ? 3 p b ? / s c o ? ? p b 1 / s c o ? 1 p b 0 / s c o ? 0 p d 1 / p w ? 3 p d 0 / t c ? p g 7 p c 3 / p w ? 1 p a 7 / r e s p c 4 / x t ? p c 5 / x t 1 p a 6 / o s c 1 p a 5 / o s c ? v d d v s s p a 4 / p w ? 0 / t c 1 / a u d p a 3 / i n t / a n 3 p a ? / t c 0 / a n ? / v r e f p a 1 / p f d / a n 1 p a 0 / a n 0 p c 6 / a n 6 p c 7 / a n 7 p c 0 / a n 4 ht 46 r 069 b 64 qfp - a 1 ? 3 4 5 6 7 8 9 10 11 1? 13 ?0 ?1 ?? ?3 ?4 ?5 ?6 ?7 ?8 60 61 6? 63 64 ?9 30 31 3? 5? 53 54 55 56 57 58 59 14 15 16 43 44 45 46 47 48 36 37 38 39 40 41 4? 33 34 35 17 18 19 5? 53 54
rev. 1.10 10 ?a? 0?? ?01? rev. 1.10 11 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pin description pin name function opt i/t o/t descriptions pa0/an0 pa0 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. an0 ancsr0 an a/d channel 0 pa1/pfd/an1 pa1 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. pfd ctrl0 c?os pfd output an1 ancsr0 an a/d channel 1 pa ?/tc0/an?/vref pa ? papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. tc0 st external timer 0 clock input an? ancsr0 an a/d channel ? vref acsr an adc reference input pa3/intb/an3 pa3 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. intb st external interrupt input an3 ancsr0 an a/d channel 3 pa4/pw ?0/tc1/aud pa4 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. pw?0 ctrl0 c?os pw? output tc1 st external timer 1 clock input aud an dac output pa5/osc ? pa5 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. osc? co osc oscillator pin pa6/osc1 pa6 papu pawk st c?os general purpose i/o. register enabled pull-up and wake-up. osc1 co osc oscillator pin pa7/ res pa7 pawk st n?os general purpose i/o. register enabled wake-up. res co st reset input pb0/sco?0 pb0 pbpu st c?os general purpose i/o. register enabled pull-up sco?0 sco?c sco? software controlled 1/? bias lcd co? pb1/sco?1 pb1 pbpu st c?os general purpose i/o. register enabled pull-up sco?1 sco?c sco? software controlled 1/? bias lcd co? pb?/sco?? pb? pbpu st c?os general purpose i/o. register enabled pull-up sco?? sco?c sco? software controlled 1/? bias lcd co? pb3/sco?3 pb3 pbpu st c?os general purpose i/o. register enabled pull-up sco?3 sco?c sco? software controlled 1/? bias lcd co? pb4?pb5 pb4?pb5 pbpu st c?os general purpose i/o. register enabled pull-up pb6/ scsa pb6 pbpu st c?os general purpose i/o. register enabled pull-up scsa st spi slave select pb7/scka pb7 pbpu st c?os general purpose i/o. register enabled pull-up scka st c?os spi serial clock pc0/an4 pc0 pcpu st c?os general purpose i/o. register enabled pull-up. an4 ancsr0 an a/d channel 4 pc1/an5 pc1 pcpu st c?os general purpose i/o. register enabled pull-up. an5 ancsr0 an a/d channel 5 pc?/pw?? pc? pcpu st c?os general purpose i/o. register enabled pull-up. pw?? ctrl? c?os pw? output pc3/pw?1 pc3 pcpu st c?os general purpose i/o. register enabled pull-up. pw?1 ctrl0 c?os pw? output pc4/xt? pc4 pcpu st c?os general purpose i/o. register enabled pull-up. xt? co lxt low frequenc? cr?stal pin pc5/xt1 pc5 pcpu st c?os general purpose i/o. register enabled pull-up. xt1 co lxt low frequenc? cr?stal pin
rev. 1.10 10 ?a? 0?? ?01? rev. 1.10 11 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pin name function opt i/t o/t descriptions pc6/an6 pc6 pcpu st c?os general purpose i/o. register enabled pull-up . an6 ancsr0 an a/d channel 6 pc7/an7 pc7 pcpu st c?os general purpose i/o. register enabled pull-up. an7 ancsr0 an a/d channel 7 pd0/tc? pd0 pdpu st c?os general purpose i/o. register enabled pull-up . tc? st external timer ? clock input pd1/pw?3 pd1 pdpu st c?os general purpose i/o. register enabled pull-up . pw?3 ctrl? c?os pw? output pd? pd? pdpu st c?os general purpose i/o. register enabled pull-up . pd3/pclk pd3 pdpu st c?os general purpose i/o. register enabled pull-up . pclk c?os peripheral clock output pd4/ scs pd4 pdpu st c?os general purpose i/o. register enabled pull-up . scs st c?os spi slave select pd5/sck/scl pd5 pdpu st c?os general purpose i/o. register enabled pull-up . sck st c?os spi serial clock scl st n?os i ? c clock pd6/sdi/sda pd6 pdpu st c?os general purpose i/o. register enabled pull-up . sdi st spi data input sda st n?os i ? c data pd7/sdo pd7 pdpu st c?os general purpose i/o. register enabled pull-up . sdo c?os spi data output pe0/an8 pe0 pepu st c?os general purpose i/o. register enabled pull-up . an8 ancsr1 an a/d channel 8 pe1/an9 pe1 pepu st c?os general purpose i/o. register enabled pull-up . an9 ancsr1 an a/d channel 9 pe?/an10 pe? pepu st c?os general purpose i/o. register enabled pull-up . an10 ancsr1 an a/d channel 10 pe3/an11 pe3 pepu st c?os general purpose i/o. register enabled pull-up . an11 ancsr1 an a/d channel 11 pe4/an1? pe4 pepu st c?os general purpose i/o. register enabled pull-up . an1? ancsr1 an a/d channel 1? pe5/an13 pe5 pepu st c?os general purpose i/o. register enabled pull-up . an13 ancsr1 an a/d channel 13 pe6/an14 pe6 pepu st c?os general purpose i/o. register enabled pull-up . an14 ancsr1 an a/d channel 14 pe7/an15 pe7 pepu st c?os general purpose i/o. register enabled pull-up . an15 ancsr1 an a/d channel 15 pf0/sdoa pf0 pfpu st c?os general purpose i/o. register enabled pull-up . sdoa c?os spi data output pf1/sdia pf1 pfpu st c?os general purpose i/o. register enabled pull-up . sdia st spi data input pf?~pf7 pfn pfpu st c?os general purpose i/o. register enabled pull-up . pg0~pg7 pgn pgpu st c?os general purpose i/o. register enabled pull-up . ph0~ph5 phn phpu st c?os general purpose i/o. register enabled pull-up . vdd vdd pwr power suppl? vss vss pwr ground note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; co: confguration option st: schmitt trigger input; cmos: cmos output; an: analog input or output scom: software controlled lcd com hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator
rev. 1.10 1? ?a? 0?? ?01? rev. 1.10 13 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu absolute maximum ratings supply voltage ................................................................................................ v ss -0.3v to v ss +6.0v input voltage .................................................................................................. v ss -0.3v to v dd +0.3v i ol total .................................................................................................. 100ma total power dissipation ........................................................................................................ 500mw storage temperature .................................................................................................. -50 c to 125c operating temperature ................................................................................................ -40 c to 85 c i oh total ................................................................................................ -100ma note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4?hz ?.? 5.5 v f sys =8?hz 3.0 5.5 v f sys =1??hz 4.5 5.5 v i dd1 operating current (hxt ? hirc? erc) 3v no load? f sys =4?hz 0.8 1.? ma 5v 1.5 ?.?5 ma i dd? operating current (hxt ? hirc? erc) 3v no load? f sys =8?hz 1.4 ?.1 ma 5v ?.8 4.? ma i dd3 operating current (hxt ? hirc? erc) 5v no load? f sys =1??hz 4 6 ma i dd4 operating current (hirc + lxt ? slow ?ode) 3v no load? f sys =3?768hz (lxt on osc1/osc ?? lvr disabled ? lxtlp=1) 5 10 5v 1? ?4 3v no load? f sys =3?768hz (lxt on xt1/xt ?? lvr disabled ? lxtlp=1) 5 10 5v 10 ?0 i stb1 standb? current (lirc on? lxt off) 3v no load? s? stem halt 5 5v 10 i stb? standb? current (lirc off ? lxt off) 3v no load? s? stem halt 1 5v ? i stb3 standb? current (lirc off ? lxt on? lxtlp=1) 3v no load? s? stem halt (lxt on osc1/osc ?) 5 5v 10 3v no load? s? stem halt (lxt on xt1/xt ?) 3 5v 5 v il1 input low voltage for i/o ? tcn and int 0 0.3v dd v v ih1 input high voltage for i/o ? tcn and int 0.7v dd v dd v v il? input low voltage ( res ) 0 0.4v dd v v ih? input high voltage ( res ) 0.9v dd v dd v v lvr1 low voltage reset 1 v lvr =4.?v 3.98 4.? 4.4? v v lvr ? low voltage reset ? v lvr =3.15v ?.98 3.15 3.3? v v lvr3 low voltage reset 3 v lvr =?.1v 1.98 ?.1 ?.?? v
rev. 1.10 1? ?a? 0?? ?01? rev. 1.10 13 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu symbol parameter test conditions min. typ. max. unit v dd conditions v lvd1 low voltage detector voltage 1 v lvd = 4.4 v 4.1? 4.4 4.70 v v lvd ? low voltage detector voltage ? v lvd = 3.3 v 3.1? 3.3 3.50 v v lvd ? low voltage detector voltage 3 v lvd = 2.2 v ?.08 ?.? ?.3? v i ol1 i/o port sink current (pa ? pb? pc? pd? pe? pf ? pg? ph) 3v v ol =0.1v dd 4 8 ma 5v 10 ?0 ma i oh i/o port source current 3v v oh =0.9v dd -? -4 ma 5v -5 -10 ma i ol? pa7 sink current 5v v ol =0.1v dd ? 3 ma r ph pull-high resistance 3v ?0 60 100 n 5v 10 30 50 n i sco? sco? operating current 5v sco?c? isel[1:0]=00 17.5 ?5.0 3?.5 sco?c? isel[1:0]=01 35 50 65 sco?c? isel[1:0]=10 70 100 130 sco?c? isel[1:0]=11 140 ?00 ?60 v sco? v dd /? voltage for lcd co? 5v no load 0.475 0.500 0.5?5 v dd note: the standby current (i stb1 ~i stb3 ) and i dd4 are measured with all i/o pins in input mode and tied to v dd .
rev. 1.10 14 ?a? 0?? ?01? rev. 1.10 15 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu a.c. characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions f sys s?stem clock ?.?v~5.5v 3? 4000 khz 3.0v~5.5v 3? 8000 khz 4.5v~5.5v 3? 1?000 khz f hirc s?stem clock (hirc) 3v/5v ta= ?5 c -?% 4 +?% ?hz 3v/5v ta= ?5 c -?% 8 +?% ?hz 5v ta= ?5 c -?% 1? +?% ?hz 3v/5v ta=0~70 c -5% 4 +5% ?hz 3v/5v ta=0~70 c -5% 8 +5% ?hz 5v ta=0~70 c -5% 1? +5% ?hz ?.?v~3.6v ta=0~70 c -8% 4 +8% ?hz 3.0v~5.5v ta=0~70 c -8% 4 +8% ?hz 3.0v~5.5v ta=0~70 c -8% 8 +8% ?hz 4.5v~5.5v ta=0~70 c -8% 1? +8% ?hz ?.?v~3.6v ta=-40 c~85 c -1?% 4 +1?% ?hz 3.0v~5.5v ta=-40 c~85 c -1?% 4 +1?% ?hz 3.0v~5.5v ta=-40 c~85 c -1?% 8 +1?% ?hz 4.5v~5.5v ta=-40 c~85 c -1?% 1? +1?% ?hz f erc s?stem clock (erc) 5v ta= ?5 c? r=1?0 k* -?% 4 +?% ?hz 5v ta=0~70 c? r=1?0 k* -5% 4 +5% ?hz 5v ta=-40 c~85 c? r=1?0 k* -7% 4 +7% ?hz ?.?v~5.5v ta=-40 c~85 c? r=1?0 k* -11% 4 +11% ?hz f lxt s?stem clock (lxt) 3?768 hz t ti?er timer input frequenc ? (tcn) ?.?v~5.5v 0 4000 khz 3.0v~5.5v 0 8000 khz 4.5v~5.5v 0 1?000 khz f lirc lirc oscillator 3v 5 10 15 khz 5v 6.5 13 19.5 khz t res external reset low pulse width 1 s t sst s?stem start-up time period ? 1?8 t sys t sys t sys t int interrupt fulse width 1 s t lvr low voltage width to reset 0.?5 1 ? ms restd reset dela ? time 100 ms 1rwhw sys i sys i ddids dd dd i d d i d s dsd d dddyds
rev. 1.10 14 ?a? 0?? ?01? rev. 1.10 15 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu adc characteristics ta= ?5 c symbol parameter test conditions min. typ. max. unit v dd conditions dnl a/c differential non-linearit ? 3v t ad =0.5 s -? ? lsb 5v inl adc integral non-linearit? 3v t ad =0.5 s -4 4 lsb 5v i adc additional power consumption if a/d converter is used 3v 0.5 0.75 ma 5v 1.0 1.5 ma dac electrical characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v dac dac operating voltage ?.4 v i q dac q uiescent current 5v code= 0000h v ol =00h ? 3 ma i dac dac operating current 5v 1 khz sin wave? full-scale ( 8k sample rate ) 3 4.5 ma res resolution 1? bit v o output voltage level 0.01 0.99 v dd power-on reset characteristics ta= ?5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to ensure power-on reset 100 mv rrv dd v dd raising rate to ensure power-on reset 0.035 v/ms t por ? inimum time for v dd to remain at v por to e nsure power-on reset 1 ms
rev. 1.10 16 ?a? 0?? ?01? rev. 1.10 17 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility. clocking and pipelining the main system clock, derived from either a crystal/resonator or rc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? system clocking and pipelining
rev. 1.10 16 ?a? 0?? ?01? rev. 1.10 17 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is selected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register ht46r068b pc13~pc8 pcl7~pcl0 ht46r069b pc14~pc8 14 13 1? 8 7 0 program counter bp 5 bp 6 bank pointer(bp) the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section.
rev. 1.10 18 ?a? 0?? ?01? rev. 1.10 19 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data or program memory space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack.
device stack levels ht46r068b ht46r069b 8 if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.10 18 ?a? 0?? ?01? rev. 1.10 19 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu program memory the program memory is the location where the user code or program is stored. the device is supplied with one-time programmable, otp, memory where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the fexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. structure the program memory has a capacity of 16kx16/32kx16. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. device capacity banks ht46r068b 16kx16 0?1 ht46r069b 3?kx16 0~3 the devices have their program memory divided into a number of banks which are selected using the bank pointer register. the ht46r068b has its program memory divided into two banks, bank 0 and bank 1. the required bank is selected using bit 5 of the bp register. the ht46r069b has its program memory divided into four banks, from bank0 to bank3. the required bank is selected using bit 5 and bit 6 of the bp register.

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?? ? ? ? ?? ?
rev. 1.10 ?0 ?a? 0?? ?01? rev. 1.10 ?1 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu special vectors within the program memory, certain locations are reserved for special usage such as reset and interrupts. ? reset vector this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. ? external interrupt vector this vector is used by the external interrupt. if the external interrupt pin on the device receives an edge transition, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. the external interrupt active edge transition type, whether high to low, low to high or both is specifed in the ctrl1 register. ? timer/event 0/1/2 counter interrupt vector this internal vector is used by the timer/event counters. if a timer/event counter overflow occurs, the program will jump to its respective location and begin execution if the associated timer/event counter interrupt is enabled and the stack is not full. ? multi-function interrupt vector the multi-function interrupt vector is shared by several internal functions: a time base overfow, an spi/i 2 c or spia data transfer completion. the program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, tblp. this register defnes the lower 8-bit address of the look-up table. after setting up the table pointer, the table data can be retrieved from the current program memory page or last program memory page using the "tabrdc[m]" or "tabrdl[m]" instructions, respectively. when these instructions are executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as "0". the following diagram illustrates the addressing/data fow of the look-up table:

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rev. 1.10 ?0 ?a? 0?? ?01? rev. 1.10 ?1 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu table program example the accompanying example shows how the table pointer and table data is defned and retrieved from the device. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is "7f00h" which refers to the start address of the last page within the 32k program memory of the microcontrollers. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "7f06h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrdc [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrdl [m]" instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. instruction(s) table location b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc14 pc13 pc1? pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @? @1 @0 tabrdl [m] 1 1 1 1 1 1 1 @7 @6 @5 @4 @3 @? @1 @0 note: pc14~pc8: current program counter bits @7~@0: table pointer tblp bits for the ht46r068b, the table address location is 14 bits, i.e. from b13~b0 for the ht46r069b, the table address location is 15 bits, i.e. from b14~b0 table read program example tempr eg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a, 060h mov bp, a ; select the last bank of prog. memory mov a, 06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempregl ; data at prog. memory address "7f06" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at prog.memory address "7f06" transferred to tempreg2 and tblh ; in this example the data "1ah" is transferred to ; tempreg1 and data "0fh" to register tempreg2 ; the value "00h" will be transferred to the high byte register tblh : : org 7f00h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.10 ?? ?a? 0?? ?01? rev. 1.10 ?3 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram where special function registers are located. these registers have fxed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. device capacity banks ht46r068b 51?x8 0~3 ht46r069b 10?4x8 0~7 the two sections of data memory, the special purpose and general purpose data memory are located at consecutive locations. all are implemented in ram and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. the start address of the data memory for all devices is the address "00h". all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user program for both read and write operations. by using the "set [m].i" and "clr [m].i" instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory. for some devices, the data memory is subdivided into several banks, which are selected using a bank pointer. only data in bank 0 can be directly addressed, data in bank 1~bank 7 must be indirectly addressed.
rev. 1.10 ?? ?a? 0?? ?01? rev. 1.10 ?3 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

ht46r068b

ht46r069b data memory structure note: most of the data memory bits can be directly manipulated using the "set [m].i" and "clr [m].i" with the exception of a few dedicated bits. the data meomory can also be accessed through the memory pointer registers. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value "00h".
rev. 1.10 ?4 ?a? 0?? ?01? rev. 1.10 ?5 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory begins at the address "00h" and are mapped from bank 0 to bank 7. any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved and attempting to read data from these locations will return a value of "00h". indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointer, mp0 or mp1. acting as a pair, iar0 with mp0 and iar1 with mp1 can together access data from the data memory. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to indirectly address and track data. mp0 can only be used to indirectly address data in bank 0 while mp1 can be used to address data from bank 0 and bank 7. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. note that indirect addressing using mp1 and iar1 must be used to access any data in bank 1~bank 7 . the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. ht46r068b ht46r069b 00h iar0 iar0 01h ?p0 ?p0 0?h iar1 iar1 03h ?p1 ?p1 04h bp bp 05h acc acc 06h pcl pcl 07h tblp tblp 08h tblh tblh 09h wdts wdts 0ah status status 0bh intc0 intc0 0ch t?r0 t?r0 0dh t?r0c t?r0c 0eh t?r1 t?r1
rev. 1.10 ?4 ?a? 0?? ?01? rev. 1.10 ?5 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b ht46r069b 0fh t?r1c t?r1c 10h pa pa 11h pac pac 1?h papu papu 13h pawk pawk 14h pb pb 15h pbc pbc 16h pbpu pbpu 17h pc pc 18h pcc pcc 19h pcpu pcpu 1ah ctrl0 ctrl0 1bh ctrl1 ctrl1 1ch sco?c sco?c 1dh pw?1 pw?1 1eh intc1 intc1 1fh pw?0 pw?0 ?0h adrl adrl ?1h adrh adrh ??h adcr adcr ?3h acsr acsr ?4h ?fic ?fic ?5h pd pd ?6h pdc pdc ?7h pdpu pdpu ?8h pe pe ?9h pec pec ?ah pepu pepu ?bh pf pf ?ch pfc pfc ?dh pfpu pfpu ?eh ?fh 30h pw?? pw?? 31h ctrl? ctrl? 3?h 3ah 3bh pg pg 3ch pgc pgc 3dh pgpu pgpu 3eh ph 3fh phc 40h phpu 41h t?r?l t?r?l 4?h t?r?h t?r?h
rev. 1.10 ?6 ?a? 0?? ?01? rev. 1.10 ?7 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b ht46r069b 43h t?r?c t?r?c 44h pw?3 pw?3 45h 46h si?c0 si?c0 47h si?c1 si?c1 48h si?d si?d 49h si?a/si?c? si?a/si?c? 4ah spiac0 spiac0 4bh spiac1 spiac1 4ch spiad spiad 4dh ancsr0 ancsr0 4eh ancsr1 ancsr1 4fh 50h dal dal 51h dah dah 5?h vol vol 53h 54h lvdc lvdc .. 7fh genernal purpose data memor? 514 b?tes 4 banks (80h~ffh) 10?4 b?tes 8 banks (80h~ffh) indirect addressing program example data .section 'data' adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: 7hlsudslhhuhldlhhdsohdeyhuhihuhfhldhshflf 'dd0huduhh
rev. 1.10 ?6 ?a? 0?? ?01? rev. 1.10 ?7 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. bank pointer C bp in the ht46r068b and ht46r069b devices, the data memory is divided into several banks, from bank 0 to bank 7. a bank pointer is used to select the required data memory bank. only data in bank 0 can be directly addressed as data in bank 1~bank 7 must be indirectly addressed using memory pointer mp1 and indirect addressing register iar1. using memory pointer mp0 and indirect addressing register iar0 will always access data from bank 0, irrespective of the value of the bank pointer. memory pointer mp1 and indirect addressing register iar1 can indirectly address data in either bank 0 or bank 1~bank 7 depending upon the value of the bank pointer. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the idle/ sleep mode, in which case, the data memory bank remains unaffected. it should be noted that special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within either bank 0 or bank 1~bank 7. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. ? ht46r068b bit 7 6 5 4 3 2 1 0 name p?bp0 d?bp1 d?bp0 r/w r/w r/w r/w por 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 pmbp0 : program memory bank p oint 0: bank 0 1: bank 1 bit 4~2 unimplemented, read as "0" bit 1,0 dmbp1, dmbp0 : data memory ank p oint 00:bank 0 01:bank 1 10:bank 2 11:bank 3
rev. 1.10 ?8 ?a? 0?? ?01? rev. 1.10 ?9 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? ht46r069b bit 7 6 5 4 3 2 1 0 bp p?bp1 p?bp0 d?bp? d?bp1 d?bp0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 %lw xqlpsohphqwhguhdgdv %lw pmbp1, pmbp0 3urudp0hprudn3rlwhu dn dn dn dn lw xlpsohphwhguhdgdv lw dmbp2, dmbp1, dmbp0 dwd0hprudn3rlwhu dn dn dn dn dn dn dn dn status register C status 7klv elw uhjlvwhu frqwdlqv wkh ]hur dj = fduu dj & dx[loldu fduu dj & ryhurz dj 29 srzhu grzq dj 3) dqg zdwfkgrj wlphrxw dj 72 7khvh dulwkphwlforjlfdo rshudwlrq dqgvvwhppdqdjhphqwdjvduhxvhgwruhfrugwkhvwdwxvdqgrshudwlrqriwkh plfurfrqwuroohu :lwk wkh h[fhswlrq ri wkh 72 dqg 3) djv elwv lq wkh vwdwxv uhjlvwhu fdq eh dowhuhg e lqvwuxfwlrqv olnhprvwrwkhuuhjlvwhuv qgdwdzulwwhqlqwrwkhvwdwxvuhjlvwhuzlooqrwfkdqjhwkh 72 ru3)dj ,q dgglwlrq rshudwlrqv uhodwhg wr wkh vwdwxv uhjlvwhu pd jlyh gliihuhqw uhvxowv gxh wr wkh gliihuhqw lqvwuxfwlrq rshudwlrqv 7kh 72 dj fdq eh diihfwhg rqo e d vvwhp srzhuxs d :7 wlphrxw ru e h[hfxwlqj wkh &/5 :7 ru +/7 lqvwuxfwlrq 7kh 3) dj lv diihfwhg rqo e h[hfxwlqj wkh +/7ru&/5 :7lqvwuxfwlrqrugxulqjdvvwhp srzhuxs 7kh= 29 &dqg&djvjhqhudoouhhfwwkhvwdwxvriwkhodwhvwrshudwlrqv ,q dgglwlrq rq hqwhulqj dq lqwhuuxsw vhtxhqfh ru h[hfxwlqj d vxeurxwlqh fdoo wkh vwdwxv uhjlvwhu zloo qrw eh sxvkhg rqwr wkh vwdfn dxwrpdwlfdoo ,i wkh frqwhqwv ri wkh vwdwxv uhjlvwhuv duh lpsruwdqw dqg li wkh lqwhuuxsw urxwlqh fdq fkdqjh wkh vwdwxv uhjlvwhu suhfdxwlrqv pxvw eh wdnhq wr fruuhfwo vdyh lw 1rwhwkdwelwvariwkh 67786uhjlvwhuduherwkuhdgdeohdqgzulwhdeohelwv
rev. 1.10 ?8 ?a? 0?? ?01? rev. 1.10 ?9 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu input/output ports and control registers within the area of special function registers, the port pa, pb, etc data i/o registers and their associated control register pac, pbc, etc play a prominent role. these registers are mapped to specific addresses within the data memory as shown in the data memory table. the data i/o registers, are used to transfer the appropriate output or input data on the port. the control registers specifes which pins of the port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one fexible feature of these registers is the ability to directly program single bits using the "set [m].i" and "clr [m].i" instructions. the ability to change i/o pins from output to input and vice versa by manipulating specifc bits of the i/o control registers during normal program operation is a useful feature of these devices. ? status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x" unknown bit 7,6 unimplemented, read as "0" bit 5 to : watchdog time-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occured. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is not zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.10 30 ?a? 0?? ?01? rev. 1.10 31 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu system control registers C ctrl0, ctrl1, ctrl2 these registers are used to provide control over various internal functions. some of these include the pfd control, pwm control, certain system clock options, the lxt oscillator low power control, external interrupt edge trigger type, watchdog timer enable function, time base function division ratio, and the lxt oscillator enable control. ? ctrl0 register bit 7 6 5 4 3 2 1 0 name pcfg pfdcs pw?sel pw?c1 pw?c0 pfdc lxtlp clk?od r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 pcfg : i/o confguration 0: (pwm0/tc1)/int/pfd pin-shared with pa4/pa3/pa1 1: (pwm0/tc1)/int/pfd pin-shared with pb5/pb4/pb3 bit 6 pfdcs : pfd clock source 0: timer0 1: timer1 bit 5 pwmsel : pwm type selection 0: 6+2 1: 7+1 bit 4 pwmc1 : i/o or pwm1 0: i/o 1: pwm1 bit 3 pwmc0 : i/o or pwm0 0: i/o 1: pwm0 bit 2 pfdc : i/o or pfd 0: i/o 1: pfd bit 1 lxtlp : lxt oscillator low power control function 0: lxt oscillator quick start-up mode 1: lxt oscillator low power mode bit 0 clkmod : system clock mode selection. 0: high speed system clock 1: lxt system clock, high speed oscillator stopped note: if pwm0/1/2/3 output is selected by pwmc0/1/2/3 bit, f tp comes always from . (f tp is the clock source for timer0, time base and pwm)
rev. 1.10 30 ?a? 0?? ?01? rev. 1.10 31 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? ctrl1 register bit 7 6 5 4 3 2 1 0 name integ1 integ0 tbsel1 tbsel0 wdten3 wdten? wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 0 0 0 1 0 1 0 b i1 i dss d id d bs1 bs ds i 11 i i i d d d1 d id d yd dyd i d d d s d dd d d 11 dy ii 1 d dsd d 11 d dsd 11 ? ctrl2 register bit 7 6 5 4 3 2 1 0 name dacen pw?c3 pw?c? lxten r/w r/w r/w r/w r/w por 0 0 0 1 %lw da cen '&glvdeohhqdeohfrqwuro glvdeoh hqdeoh %lw xqlpsohphqwhguhdgdv %lw pw?c3 ??ru3:0frqwuro ?? 3:0rxwsxw %lw pw?c? ??ru3:0frqwuro ?? 3:0rxwsxw %lw a xqlpsohphqwhguhdgdv %lw lxten /7 ?vfloodwru rqriifrqwurodiwhuh[hfxwlrqri +/7 lqvwuxfwlrq /7 riilq?goh0rgh /7 rqlq?gohprgh
rev. 1.10 3? ?a? 0?? ?01? rev. 1.10 33 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu wake-up function register C pawk when the microcontroller enters the idle/sleep mode, various methods exist to wake the device up and continue with normal operation. one method is to allow a falling edge on the i/o pins to have a wake-up function. this register is used to select which port a i/o pins are used to have this wake-up function. pull-high registers C papu, pbpu, pcpu, pdpu, pepu, pfpu the i/o pins, if confgured as inputs, can have internal pull-high resistors connected, which eliminates the need for external pull-high resistors. this register selects which i/o pins are connected to internal pull-high resistors. software com register C scomc the pins pb0~pb3 on port b can be used as scom lines to drive an external lcd panel. to implement this function, the scomc register is used to setup the correct bias voltages on these pins. oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. system oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for other functions such as the watchdog timer, timer/event counter, time base etc. the system oscillator can be provided from a choice of three high speed oscillators, the hxt, erc or hirc oscillators, or a single low speed, lxt crystal oscillator. the lirc oscillator is used only as a watchdog timer clock source. type name freq. pins function external cr?stal hxt 400khz~1??hz osc1/ osc? high speed s?stem clock external rc erc 400khz~1??hz osc1 high speed s?stem clock internal highb speed rc hirc 4? 8 or 1??hz high speed s?stem clock external low speed cr?stal lxt 3?768hz xt1/ xt? low speed s?stem clock clock source for: watchdog ? time base? timer/event counters 0/1 clock/spi/spia internal low speed rc lirc 13khz watchdog timer clock
rev. 1.10 3? ?a? 0?? ?01? rev. 1.10 33 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu external crystal/resonator oscillator C hxt the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation. however, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specifcation.
? ? ?? crystal/resonator oscillator hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 1??hz 8pf 10pf 8?hz 8pf 10pf 4?hz 8pf 10pf 1?hz 100pf 100pf note: c1 and c? values are for guidance onl? . crystal recommended capacitor values external rc oscillator C erc using the erc oscillator only requires that a resistor, with a value between 24k and 1.5m, is connected between osc1 and v dd , and a capacitor is connected between osc and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no infuence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an external 120k resistor connected and with a 5v voltage power supply and temperature of 25 degrees, the oscillator will have a frequency of 4mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pa6, leaving pin pa5 free for use as a normal i/o pin. external rc oscillator erc
rev. 1.10 34 ?a? 0?? ?01? rev. 1.10 35 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25 degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pa5 and pa6 are free for use as normal i/o pins.
internal rc oscillator hirc external 32768hz crystal oscillator C lxt the lxt oscillator is used both as the slow system clock and also as a selectable source clock for some peripheral functions including the watchdog timer, time base, timer/event counters and spi functions. it must be frst enabled using a confguration option. to select the lxt oscillator to be the low speed system oscillator, the clkmod bit in the ctrl0 register should be set high. when a halt instruction is executed, the system clock is stopped, but the lxten bit in the ctrl2 register determines if the lxt oscillator continues running when the microcontroller powers down. setting the lxten bit high will enable the lxt to keep running after a halt instruction is executed and enable the lxt oscillator to remain as a possible clock source for the watchdog timer, the time-base and the timer/event counter 0/1. the lxt oscillator is implemented using a 32768hz crystal connected to pins xt1/xt2. however, for some crystals and to ensure oscillation and accurate frequency generation, it is normally necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specification. the external parallel feedback resistor, rp, may also be required.
rev. 1.10 34 ?a? 0?? ?01? rev. 1.10 35 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu
? ? ???? - external lxt oscillator - hxt lxt oscillator c1 and c2 values crystal frequency c1 c2 3?768hz 8pf 10pf note: 1. c1 and c? values are for guidance onl? . ?. r p =5?~10? is recommended. 32768hz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the ctrl0 register. lxtlp bit lxt mode 0 quick start 1 low-power after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low- power mode. internal low speed oscillator C lirc the lirc is a fully self-contained free running on-chip rc oscillator with a typical frequency of 13khz at 5v requiring no external components. when the device enters the idle/sleep mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the lirc can be disabled via a confguration option.
rev. 1.10 36 ?a? 0?? ?01? rev. 1.10 37 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu operating modes by using the lxt low frequency oscillator in combination with a high frequency oscillator, the system can be selected to operate in a number of different modes. these modes are normal, slow, idle and sleep. mode types and selection the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow oscillators, the device has the fexibility to optimise the performance/power ratio, a feature especially important in power sensitive portable applications. for these devices the lxt oscillator can run together with any of the high speed oscillators, namely the hxt, erc or the hirc. the clkmod bit in the ctrl0 register can be used to switch the system clock from the selected high speed oscillator to the low speed lxt oscillator. when the halt instruction is executed the lxt oscillator can be chosen to run or not using the lxten bit in the ctrl2 register.

? ? ?? ? ??

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6\vwhp&orfn&rq?jxudwlrqv for all devices, when the system enters the sleep or idle mode, the high frequency system clock will always stop running. the accompanying tables shows the relationship between the clkmod bit, the halt instruction and the high/low frequency oscillators. the clmod bit can change normal or slow mode. ? operating mode control halt instruction clkmod bit lxten bit high speed system clock xtal/irc/erc low speed system clock lxt operating mode not executed 0 x run on normal 1 x stop on slow executed x 1 stop on idle x 0 stop off sleep
rev. 1.10 36 ?a? 0?? ?01? rev. 1.10 37 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu mode switching the devices are switched between one mode and another using a combination of the clkmod bit in the ctrl0 register and the halt instruction. the clkmod bit chooses whether the system runs in either the normal or slow mode by selecting the system clock to be sourced from either a high or low frequency oscillator. the halt instruction forces the system into either the idle or sleep mode, depending upon whether the lxt oscillator is running or not. the halt instruction operates independently of the clkmod bit condition. when a halt instruction is executed and the lxt oscillator is not running, the system enters the sleep mode the following conditions exist: ? the system oscillator will stop running and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the lirc oscillator. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present condition. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the idle/sleep mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. if the configuration options have enabled the watchdog timer internal oscillator lirc then this will continue to run when in the idle/sleep mode and will thus consume some power. for power sensitive applications it may be therefore preferable to use the system clock source for the watchdog timer. the lxt, if confgured for use, will also consume a limited amount of power, as it continues to run when the device enters the idle mode. to keep the lxt power consumption to a minimum level the lxtlp bit in the ctrl0 register, which controls the low power function, should be set high.
rev. 1.10 38 ?a? 0?? ?01? rev. 1.10 39 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu wake-up after the system enters the idle/sleep mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on pa0 to pa7 ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt" instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. pins pa0 to pa7 can be setup via the pawuk register to permit a negative transition on the pin to wake-up the system. when a pa0 to pa7 pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set to "1" before entering the idle/sleep mode, then any future interrupt requests will not generate a wake-up function of the related interrupt will be ignored. no matter what the source of the wake-up event is, once a wake-up event occurs, there will be a time delay before normal program execution resumes. consult the table for the related time. wake-up source oscillator type erc, irc crystal external res t rsdt + t sst1 t rsdt + t sst? pa port t sst1 t sst? interrupt :'7?yhurz note: 1. t rstd (reset delay time), t sys (system clock) 2. t rstd is power-on delay, typical time=100ms 3. t sst1 = 2 or 128 t sys 4. t sst2 = 128 t sys wake-up delay time
rev. 1.10 38 ?a? 0?? ?01? rev. 1.10 39 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu watchdog timer the watchdog timer, also known as the wdt, is provided to inhibit program malfunctions caused by the program jumping to unknown locations due to certain uncontrollable external events such as electrical noise. watchdog timer operation it operates by providing a device reset when the watchdog timer counter overfows. note that if the watchdog timer function is not enabled, then any instructions related to the watchdog timer will result in no operation. setting up the various watchdog timer options are controlled via the confguration options and two internal registers wdts and ctrl1. enabling the watchdog timer can be controlled by both a confguration option and the wdten bits in the ctrl1 internal register in the data memory. confguration option ctrl1 register wdt function disable disable off disable enable on enable x on watchdog timer on/off control the watchdog timer will be disabled if bits wdten3~wdten0 in the ctrl1 register are written with the binary value 1010b and wdt confguration option is disable. this will be the condition when the device is powered up. although any other data written to wdten3~wdten0 will ensure that the watchdog timer is enabled, for maximum protection it is recommended that the value 0101b is written to these bits. the watchdog timer clock can emanate from three different sources, selected by configuration option. these are lxt, f sys /4, or lirc. it is important to note that when the system enters the idle/ sleep mode the instruction clock is stopped, therefore if the configuration options have selected f sys /4 as the watchdog timer clock source, the watchdog timer will cease to function. for systems that operate in noisy environments, using the lirc or the lxt as the clock source is therefore the recommended choice. the division ratio of the prescaler is determined by bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2. if the watchdog timer internal clock source is selected and with the ws0, ws1 and ws2 bits of the wdts register all set high, the prescaler division ratio will be 1:128, which will give a maximum time-out period. under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the idle/sleep mode, when a watchdog timer time- out occurs, the device will be woken up, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, which means a low level on the external reset pin, the second is using the clear watchdog timer software instructions and the third is when a halt instruction is executed. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by confguration option. the frst option is to use the single "clr wdt" instruction while the second is to use the two commands "clr wdt1" and "clr wdt2". for the frst option, a simple execution of "clr wdt" will clear the watchdog timer while for the second option, both "clr wdt1" and "clr wdt2" must both be executed to successfully clear the watchdog timer. note that for this second option, if "clr wdt1" is used to clear the watchdog timer, successive executions of this instruction will have no effect, only the execution of a "clr wdt2" instruction will clear the watchdog timer. similarly after the "clr wdt2" instruction has been executed, only a successive "clr wdt1" instruction can clear the watchdog timer.
rev. 1.10 40 ?a? 0?? ?01? rev. 1.10 41 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu
? ? ? ? ? ? ? ?? ?? - ? watchdog timer ? wdts register bit 7 6 5 4 3 2 1 0 name ws? ws1 ws0 r/w r/w r/w r/w por 1 1 1 %lwa xqlpsohphqwhguhdgdv %lwa ws2, ws1, ws0 :7 wlphrxwshulrgvhohfwlr 8 w :7 w :7 w :7 11 w :7 w :7 w :7 w :7 w :7 reset and initialisation uhvhw ixqfwlrq lv d ixqgdphqwdo sduw ri dq plfurfr qwuroohu hqvxulqj wkdw wkh ghylfh fdq eh vhw wr vrph suhghwhuplqhg frqglwlrq luuhvshfwlyh ri rxwvlgh sdudphwhuv 7kh prvw lpsruwdqw uhvhw frqglwlrq lv diwhu srzhu lv uvw dssolhg wr wkh plfurfrqwuroohu ,q wklv fdvh lqwhuqdo flufxlwu zloo hqvxuh wkdw wkh plfurfrqwuroohu diwhu d vkruw ghod zloo eh lq d zhoo ghilqhg vwdwh dqg uhdg wr h[hfxwh wkh uvw surjudp lqvwuxfwlrq iwhu wklv srzhurq uhvhw fhuwdlq lpsruwdqw lqwhuqdo uhjlvwhuv zloo eh vhw wr ghqhg vwdwhv ehiruh wkh surjudp frpphqfhv 2qh ri wkhvh uhjlvwhuv lv wkh 3urjudp &rxqwhu zklfkzlooehuhvhwwr]huriruflqjwkhplfurfrqwuroohu wrehjlqsurjudph[hfxwlrq iurpwkh orzhvw3urjudp0hprudgguhvv ,q dgglwlrq wr wkh srzhurq uhvhw vlwxdwlrqv pd dulvh zkhuh lw lv qhfhvvdu wr irufhixoo dsso d uhvhw frqglwlrq zkhq wkh plfurfrqwuroohu lv uxqqlqj 2qh h[dpsoh ri wklv lv zkhuh diwhu srzhu kdv ehhq dssolhg dqg wkh plfurfrqwuroohu lv douhdg uxqqlqj wkh 5(6 olqh lv irufhixoo sxoohg orz ,q vxfk d fdvh nqrzq dv d qrupdo rshudwlrq uhvhw vrph ri wkh plfurfrqwuroohu uhjlvwhuv uhpdlq xqfkdqjhg doorzlqj wkh plfurfrqwuroohu wr surfhhg zlwk qrupdo rshudwlrq diwhu wkh uhvhw olqh lv doorzhg wr uhwxuq kljk qrwkhu wsh ri uhvhw lv zkhq wkh :dwfkgrj 7lphu ryhurzv dqg uhvhwv wkh plfurfrqwuroohu oowshvriuhvhwrshudwlrqvuhvxowlq gliihuhqwuhjlvwhufrqglwlrqvehlqjvhwxs qrwkhu uhvhw h[lvwv lq wkh irup ri d /rz 9rowdjh 5hvhw /95 zkhuh d ixoo uhvhw vlplodu wr wkh 5(6 uhvhwlvlpsohphqwhglqvlwxdwlrqvzkhuhwkhsrzhuvxssoyrowdjhidoovehorzdfhuwdlqwkuhvkrog
rev. 1.10 40 ?a? 0?? ?01? rev. 1.10 41 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: ? power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. although the microcontroller has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer. power-on reset timing chart note: t rstd is power-on delay, typical time=100ms for most applications a resistor connected between v dd and the res pin and a capacitor connected between v ss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. external res circuit note: "*" it is recommended that this component is added esd protection. "**" it is recommended that this component is added in environments where power line noise is signifcant.
rev. 1.10 4? ?a? 0?? ?01? rev. 1.10 43 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu more information regarding external reset circuits is located in application note ha0075e on the holtek website. ? res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initiated from this point. res reset timing chart note: t rstd is power-on delay, typical time=100ms ? low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the lvr function is selected via a confguration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low supply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected via confguration options. low voltage reset timing chart note: t rstd is power-on delay, typical time=100ms ? watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out fag to will be set to "1". wdt reset during normal operation timing chart note: t rstd is power-on delay, typical time=100ms
rev. 1.10 4? ?a? 0?? ?01? rev. 1.10 43 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? watchdog time-out reset during idle/sleep mode the watchdog time-out reset during idle/sleep mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the to fag will be set to "1". refer to the a.c. characteristics for t sst details. wdt time-out reset during idle/sleep timing chart note: the t sst can be chosen to be either 128 or 2 clock cycles if the system clock source is provided by erc or hirc. the sst is 128 clock cycle for hxt or lxt. it is described in the following table: system clock source hirc erc hxt lxt none xt1/xt2 power on 1?8 hirc 1?8 hirc 1?8 erc 1?8 hxt normal ?ode wakeup ? hirc ? hirc ? erc 1?8 hxt slow ?ode wakeup x ? lxt x x sleep ?ode wakeup ? hirc 1?8 lxt ? erc 1?8 hxt reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the idle/sleep function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset u u res or lvr reset during normal or slow ?ode operation 1 u wdt time-out reset during normal or slow ?ode operation 1 1 wdt time-out reset during idle or sleep ?ode operation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset? wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack
rev. 1.10 44 ?a? 0?? ?01? rev. 1.10 45 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register ht46r068b ht46r069b power-on reset res or lvr reset (normal operation) res or lvr reset (idle/sleep) wdt time-out (normal operation) wdt time-out (idle/sleep) pcl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ?p0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u ?p1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u bp C C 0 C C C 0 0 C C 0 C C C 0 0 C C 0 C C C 0 0 C C 0 C C C 0 0 C C u C C C u u bp C 0 0 C C 0 0 0 C 0 0 C C 0 0 0 C 0 0 C C 0 0 0 C 0 0 C C 0 0 0 C u u C C u u u acc x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u tblp x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u tblh x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u wdts C C C C C 1 1 1 C C C C C 1 1 1 C C C C C 1 1 1 C C C C C 1 1 1 C C C C C u u u status C C 0 0 x x x x C C u u u u u u C C 0 1 u u u u C C 1 u u u u u C C 1 1 u u u u intc0 C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C u u u u u u u intc1 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C u u u C u u u ?fic C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C 0 0 0 C u u u C u u u t?r0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u t?r0c 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 u u u u u u u u t?r1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u t?r1c 0 0 0 0 1 C C C 0 0 0 0 1 C C C 0 0 0 0 1 C C C 0 0 0 0 1 C C C u u u u u C C C t?r?l x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u t?r?h x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u t?r?c 0 0 0 0 1 C C C 0 0 0 0 1 C C C 0 0 0 0 1 C C C 0 0 0 0 1 C C C u u u u u C C C pa 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pac 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pawk 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u papu C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C u u u u u u u pb 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pbc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pbpu 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u pc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pcc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pcpu 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u pd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pdc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pdpu 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u pe 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pec 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pepu 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u pf 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pfc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pfpu 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u pg C C C C C C 1 1 C C C C C C 1 1 C C C C C C 1 1 C C C C C C 1 1 C C C C C C u u pgc C C C C C C 1 1 C C C C C C 1 1 C C C C C C 1 1 C C C C C C 1 1 C C C C C C u u
rev. 1.10 44 ?a? 0?? ?01? rev. 1.10 45 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu register ht46r068b ht46r069b power-on reset res or lvr reset (normal operation) res or lvr reset (idle/sleep) wdt time-out (normal operation) wdt time-out (idle/sleep) pgpu C C C C C C 0 0 C C C C C C 0 0 C C C C C C 0 0 C C C C C C 0 0 C C C C C C u u pg 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pgc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pgpu 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u ph C C 1 1 1 1 1 1 C C 1 1 1 1 1 1 C C 1 1 1 1 1 1 C C 1 1 1 1 1 1 C C u u u u u u phc C C 1 1 1 1 1 1 C C 1 1 1 1 1 1 C C 1 1 1 1 1 1 C C 1 1 1 1 1 1 C C u u u u u u phpu C C 0 0 0 0 0 0 C C 0 0 0 0 0 0 C C 0 0 0 0 0 0 C C 0 0 0 0 0 0 C C u u u u u u ctrl0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u ctrl1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 u u u u u u u u ctrl? 0 C 0 0 C C C 1 0 C 0 0 C C C 1 0 C 0 0 C C C 1 0 C 0 0 C C C 1 u C u u C C C u sco?c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u pw?0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u pw?1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u pw?? x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u pw?3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u si?c0 1 1 1 0 0 0 0 C 1 1 1 0 0 0 0 C 1 1 1 0 0 0 0 C 1 1 1 0 0 0 0 C u u u u u u u C si?c1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u u si?d x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u si?a/ si?c? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u spiac0 1 1 1 C C C 0 1 1 1 1 C C C 0 1 1 1 1 C C C 0 1 1 1 1 C C C 0 1 u u u u u u u u spiac1 C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 u u u u u u u u spiad x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u dal 0 0 0 0 C C C C 0 0 0 0 C C C C 0 0 0 0 C C C C 0 0 0 0 C C C C u u u u C C C C dah 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u vol 0 0 0 0 C C C C 0 0 0 0 C C C C 0 0 0 0 C C C C 0 0 0 0 C C C C u u u u C C C C lvdc C C 0 0 C C C C C C 0 0 C C C C C C 0 0 C C C C C C 0 0 C C C C C C u u C C C C adrl x x x x C C C C x x x x C C C C x x x x C C C C x x x x C C C C u u u u C C C C adrh x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u adcr 0 1 C C 0 0 0 0 0 1 C C 0 0 0 0 0 1 C C 0 0 0 0 0 1 C C 0 0 0 0 u u C C u u u u acsr 1 1 C C 0 0 0 0 1 1 C C 0 0 0 0 1 1 C C 0 0 0 0 1 1 C C 0 0 0 0 u u C C u u u u ancsr0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u ancsr1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u
rev. 1.10 46 ?a? 0?? ?01? rev. 1.10 47 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. most pins can have either an input or output designation under user program control. additionally, as there are pull-high resistors and wake-up software confgurations, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a,[m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via a register known as papu, pbpu, pcpu, pdpu, pepu and pfpu located in the data memory. the pull-high resistors are implemented using weak pmos transistors. note that pin pa7 does not have a pull-high resistor selection. port a wake-up if the halt instruction is executed, the device will enter the idle/sleep mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the pa0~pa7 pins from high to low. after a halt instruction forces the microcontroller into entering the idle/sleep mode, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applications that can be woken up via external switches. note that pins pa0 to pa7 can be selected individually to have this wake-up feature using an internal register known as pawk, located in the data memory.
rev. 1.10 46 ?a? 0?? ?01? rev. 1.10 47 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pawk, pac, papu, pbc, pbpu, pcc, pcpu, pdc, pdpu, pec, pepu, pfc, pfpu register ? ht46r068b register name por bit 7 6 5 4 3 2 1 0 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk3 pawk ? pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac3 pac ? pac1 pac0 papu 00h papu6 papu5 papu4 papu3 papu ? papu1 papu0 pbc ffh pbc7 pbc6 pbc5 pbc4 pbc3 pbc? pbc1 pbc0 pbpu 00h pbpu7 pbpu6 pbpu5 pbpu4 pbpu3 pbpu? pbpu1 pbpu0 pcc ffh pcc7 pcc6 pcc5 pcc4 pcc3 pcc? pcc1 pcc0 pcpu 00h pcpu7 pcpu6 pcpu5 pcpu4 pcpu3 pcpu? pcpu1 pcpu0 pdc ffh pdc7 pdc6 pdc5 pdc4 pdc3 pdc? pdc1 pdc0 pdpu 00h pdpu7 pdpu6 pdpu5 pdpu4 pdpu3 pdpu? pdpu1 pdpu0 pec ffh pec7 pec6 pec5 pec4 pec3 pec? pec1 pec0 pepu 00h pepu7 pepu6 pepu5 pepu4 pepu3 pepu? pepu1 pepu0 pfc ffh pfc7 pfc6 pfc5 pfc4 pfc3 pfc? pfc1 pfc0 pfpu 00h pfpu7 pfpu6 pfpu5 pfpu4 pfpu3 pfpu? pfpu1 pfpu0 pgc ffh pgc1 pgc0 pgpu 00h pgpu1 pgpu0 8qlpsohphqwhguhdgdv pawkn 3 zdnhxsixfwlrhdeoh glvdeoh hdeoh pacn/pbcn/pccn/pdcn/pecn/pfcn/pgcn ,2wshvhohfwlr rxwsxw lsxw papun/pbpun/pcpun/pdpun/pepun/pfpun/pgpun 3xooklkixfwlrhdeoh glvdeoh hdeoh
rev. 1.10 48 ?a? 0?? ?01? rev. 1.10 49 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? ht46r069b register name por bit 7 6 5 4 3 2 1 0 pawk 00h pawk7 pawk6 pawk5 pawk4 pawk3 pawk ? pawk1 pawk0 pac ffh pac7 pac6 pac5 pac4 pac3 pac ? pac1 pac0 papu 00h papu6 papu5 papu4 papu3 papu ? papu1 papu0 pbc ffh pbc7 pbc6 pbc5 pbc4 pbc3 pbc? pbc1 pbc0 pbpu 00h pbpu7 pbpu6 pbpu5 pbpu4 pbpu3 pbpu? pbpu1 pbpu0 pcc ffh pcc7 pcc6 pcc5 pcc4 pcc3 pcc? pcc1 pcc0 pcpu 00h pcpu7 pcpu6 pcpu5 pcpu4 pcpu3 pcpu? pcpu1 pcpu0 pdc ffh pdc7 pdc6 pdc5 pdc4 pdc3 pdc? pdc1 pdc0 pdpu 00h pdpu7 pdpu6 pdpu5 pdpu4 pdpu3 pdpu? pdpu1 pdpu0 pec ffh pec7 pec6 pec5 pec4 pec3 pec? pec1 pec0 pepu 00h pepu7 pepu6 pepu5 pepu4 pepu3 pepu? pepu1 pepu0 pfc ffh pfc7 pfc6 pfc5 pfc4 pfc3 pfc? pfc1 pfc0 pfpu 00h pfpu7 pfpu6 pfpu5 pfpu4 pfpu3 pfpu? pfpu1 pfpu0 pgc ffh pgc7 pgc6 pgc5 pgc4 pgc3 pgc? pgc1 pgc0 pgpu 00h pgpu7 pgpu6 pgpu5 pgpu4 pgpu3 pgpu? pgpu1 pgpu0 phc 3fh phc5 phc4 phc3 phc? phc1 phc0 phpu 00h phpu5 phpu4 phpu3 phpu? phpu1 phpu0 8qlpsohphqwhguhdgdv pawkn 3 zdnhxsixfwlrhdeoh glvdeoh hdeoh pacn/pbcn/pccn/pdcn/pecn/pfcn/pgcn/phcn ,2wshvhohfwlr rxwsxw lsxw papun/pbpun/pcpun/pdpun/pepun/pfpun/pgpun/phpun 3xooklkixfwlrhdeoh glvdeoh hdeoh i/o port control registers (dfk 3ruw kdv lwv rzq frqwuro uhjlvwhu nqrzq dv 3& 3& 3&& 3& 3(& 3)& 3& 3+& zklfkfrqwurovwkhlqsxwrxwsxwfrqjxudwlrq :lwk wklvfrqwuro uhjlvwhuhdfk,2slqzlwkruzlwkrxw sxookljk uhvlvwruv fdq eh uhfrqiljxuhg gqdplfdoo xqghu vriwzduh frqwuro )ru wkh ,2 slq wr ixqfwlrq dv dq lqsxw wkh fruuhvsrqglqj elw ri wkh frqwuro uhjlvwhu pxvw eh zulwwhq dv d 7klv zloo wkhqdoorzwkhorjlfvwdwhriwkhlqsxwslqwrehgluhfwouhdgelqvwuxfwlrqv :khqwkhfruuhvsrqglqj elw ri wkh frqwuro uhjlvwhu lv zulwwhq dv d wkh ,2 slq zloo eh vhwxs dv d &026 rxwsxw ,i wkh slq lv fxuuhqwo vhwxs dv dq rxwsxw lqvwuxfwlrqv fdq vwloo eh xvhg wr uhdg wkh rxwsxw uhjlvwhu +rzhyhu lw vkrxog eh qrwhg wkdw wkh surjudp zloo lq idfw rqo uhdg wkh vwdwxv ri wkh rxwsxw gdwd odwfk dqg qrw wkh dfwxdoorjlfvwdwxvriwkhrxwsxwslq
rev. 1.10 48 ?a? 0?? ?01? rev. 1.10 49 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by confguration options while for others the function is set by application program control. ? external interrupt input the external interrupt pin, int, is pin-shared with an i/o pin. to use the pin as an external interrupt input the correct bits in the intc0 register must be programmed. the pin must also be setup as an input by setting the pac3 bit in the port control register. a pull-high resistor can also be selected via the appropriate port pull-high resistor register. note that even if the pin is setup as an external interrupt input the i/o function still remains. ? external timer/event counter input the timer/event counter pins, tc0, tc1 and tc2 are pin-shared with i/o pins. for these shared pins to be used as timer/event counter inputs, the timer/event counter must be confgured to be in the event counter or pulse width capture mode. this is achieved by setting the appropriate bits in the timer/event counter control register. the pins must also be setup as inputs by setting the appropriate bit in the port control register. pull-high resistor options can also be selected using the port pull-high resistor registers. note that even if the pin is setup as an external timer input the i/o function still remains. ? pfd output the pfd function output is pin-shared with an i/o pin. the output function of this pin is chosen using the ctrl0 register. note that the corresponding bit of the port control register, must setup the pin as an output to enable the pfd output. if the port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the pfd function has been selected. ? pwm outputs the pwm function whose outputs are pin-shared with i/o pins. the pwm output functions are chosen using the ctrl0 and ctrl2 registers. note that the corresponding bit of the port control registers, for the output pin, must setup the pin as an output to enable the pwm output. if the pins are setup as inputs, then the pin will function as a normal logic input with the usual pull-high selections, even if the pwm registers have enabled the pwm function. ? scom driver pinss pins pb0~pb3 on port b can be used as lcd com driver pins. this function is controlled using the scomc register which will generate the necessary 1/2 bias signals on these four pins. ? a/d inputs each device in this series has up to 16 inputs to the a/d converter. all of these analog inputs are pin-shared with i/o pins. if these pins are to be used as a/d inputs and not as i/o pins then the corresponding pcrn bits in the ancsr0 and ancsr1 registers, must be properly setup. there are no confguration options associated with the a/d converter. if chosen as i/o pins, then full pull-high resistor confguration options remain, however if used as a/d inputs then any pull-high resistor confguration options associated with these pins will be automatically disconnected.
rev. 1.10 50 ?a? 0?? ?01? rev. 1.10 51 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pin remapping confguration the pin remapping function enales the function pins p/tc, int and pd to e located on different port pins. it is important not to confuse the pin remapping function ith the pinshared function, these to functions have no interdependence. the pc it in the ctr register allos the three function pins p/tc, int and pd to e remapped to different port pins. after poer up, this it ill e reset to zero, hich ill defne the default port pins to hich these three functions ill e mapped. changing this it ill move the functions to other port pins. eamination of the pin names on the package diagrams ill reveal that some pin function names are repeated, this indicates a function pin that can e remapped to other port pins. if the pin name is racketed then this indicates its alternative location. pin names ithout rackets indicates its default location hich is the condition after poeron. pcfg bit status pcfg bit 0 1 pin ?apping (pw? 0/tc1)/pa4 int/pa3 pfd/pa1 [(pw?0/tc1)]/pb5 [int]/pb4 [pfd]/pb3 pin remapping i/o pin structures 7kh gldjudpv looxvwudwh wkh ,2 slq lqwhuqdo vwuxfwxuhv v wkh h[dfw orjlfdo frqvwuxfwlrq ri wkh ,2 slq pd gliihu iurp wkhvh gudzlqjv wkh duh vxssolhg dv d jxlgh rqo wr dvvlvw zlwk wkh ixqfwlrqdo xqghuvwdqglqjriwkh,2slqv

??? ?? ? ? ? generic input/output ports
rev. 1.10 50 ?a? 0?? ?01? rev. 1.10 51 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

? ? ? ? ? ?
pa7 nmos input/output port

? ? ? ?? ? ? ?

- ? - - ? - ?? ? ? pb input/output port
rev. 1.10 5? ?a? 0?? ?01? rev. 1.10 53 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, the i/ o data register and i/o port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register is frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
read modify write timing pins pa0 to pa7 each have a wake-up functions, selected via the pawk register. when the device is in the idle/sleep mode, various methods are available to wake the device up. one of these is a high to low transition of any of the these pins. single or multiple pins on port a can be setup to have this function. timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. the devices contain two 8-bit and one 16-bit timer. as the timers have three different operating modes, they can be confgured to operate as a general timer, an external event counter or as a pulse width capture device. the provision of an internal prescaler to the clock circuitry on gives added range to the timers. there are two types of registers related to the timer/event counters. the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the timer/event counter. the second type of associated register is the timer control register which defines the timer options and determines how the timer is to be used. the device can have the timer clock confgured to come from the internal clock source. in addition, the timer clock source can also be confgured to come from an external timer pin. confguring the timer/event counter input clock source the timer/event counter clock source can originate from various sources, an internal clock or an external pin. the internal clock source is used when the timer is in the timer mode or in the pulse width capture mode. for some timer/event counters, this internal clock source is frst divided by a prescaler, the division ratio of which is conditioned by the timer control register bits. an external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin tcn. depending upon the condition of the tneg bit, each high to low, or low to high transition on the external timer pin will increment the counter by one.
rev. 1.10 5? ?a? 0?? ?01? rev. 1.10 53 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu timer registers C tmr0, tmr1, tmr2l, tmr2h the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. these registers are known as tmr0, tmr1, tmr2l and tmr2h. the value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer/event counter or ffffh for the 16-bit timer/event counters, at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. note that to achieve a maximum full range count of ffh or ffffh, the preload register must frst be cleared to all zeros. it should be noted that after power-on, the preload registers will be in an unknown condition. note that if the timer/event counter is in an off condition and data is written to its preload register, this data will be immediately written into the actual counter. however, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overfow occurs. timer control registers C tmr0c, tmr1c, tmr2c the fexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. the timer control register is known as tmrnc. it is the timer control register together with its corresponding timer register that control the full operation of the timer/event counter. before the timer can be used, it is essential that the timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. to choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width capture mode, bits 7 and 6 of the timer control register, which are known as the bit pair tnm1/tnm0, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as tnon, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. bits 0~2 of the timer control register determine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as tneg. the tns bit selects the internal clock source.
? ? ? ? ? ? ? ? ? ? - ? ? ? ? ?? ? ? ? ? ? ? ? ? ? clock structure for timer/pwm/time base
rev. 1.10 54 ?a? 0?? ?01? rev. 1.10 55 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

? ?? ? ? ? ? -
? ? ? 8-bit timer/event counter 0 structure
? ? ? ?? ? - ? ? ? ? 8-bit timer/event counter 1 structure

?? ? ? ? ? - ? ? ? 16-bit timer/event counter 2 structure 0 ?ux pfd0 pfd1 pfd output pfdcs 1 note: if pwm0/pwm1/pwm2/pwm4 is enabled, then f tp comes from f sys (ignore t0s)
rev. 1.10 54 ?a? 0?? ?01? rev. 1.10 55 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? tmr0c register bit 7 6 5 4 3 2 1 0 name t0?1 t0?0 t0s t0on t0eg t0psc? t0psc1 t0psc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 0 0 0 %lw t0m1, t0m0 7lphu rshudwlrprghvhohfwlr rprghddlodeoh hhwfrxwhuprgh wlphuprgh sxovhzlgwkfdswxuhprgh lw t0s wlphuforfnvrxufh i ss /7 rvfloodwru 76 vhohfwv wkh forfn vrxufh iru i73 zklfk lv surlghg iru 7lphu wkh 7lphdvh dgwkh3:0,iwkh3:0lvhdeohgwkhi ss zlooehvhohfwhgrhuulglwkh 76 vhohfwlr lw t0on 7lphuhhw frxwhufrxwlhdeoh glvdeoh hdeoh lw t0eg hwfrxwhudfwlhhghvhohfwlr frxwrudlvlhgh frxwridoolhgh 3xovh :lgwk dswxuhdfwlhhghvhohfwlr vwduwfrxwlridoolhghvwrsrudlvlhgh vwduwfrxwlrudlvlhghvwrsridoolhgh lw t0psc2, t0psc1, t0psc0 7lphu suhvfdohuudwh vhohfwlr 7lphu lwhudoforfn i 73 i 73 i 73 i 73 i 73 i 73 i 73 i 73
rev. 1.10 56 ?a? 0?? ?01? rev. 1.10 57 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? tmr1c register bit 7 6 5 4 3 2 1 0 name t1?1 t1?0 t1s t1on t1eg r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 %lw t1m1, t1m0 7lphu rshudwlrprghvhohfwlr rprghddlodeoh hhwfrxwhuprgh wlphuprgh sxovhzlgwkfdswxuhprgh lw t1s wlphuforfnvrxufh i ss /7 rvfloodwru lw t1on 7lphuhhw frxwhufrxwlhdeoh glvdeoh hdeoh lw t1eg hwfrxwhudfwlhhghvhohfwlr frxwrudlvlhgh frxwridoolhgh 3xovh :lgwk dswxuhdfwlhhghvhohfwlr vwduwfrxwlridoolhghvwrsrudlvlhgh vwduwfrxwlrudlvlhghvwrsridoolhgh lw xlpsohphwhguhdgdv ? tmr2c register bit 7 6 5 4 3 2 1 0 name t??1 t??0 t?s t?on t?eg r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 %lw t2m 1, t2m0 7lphu rshudwlrprghvhohfwlr rprghddlodeoh hhwfrxwhuprgh wlphuprgh sxovhzlgwkfdswxuhprgh lw t2s wlphuforfnvrxufh i ss /7 rvfloodwru lw t2on 7lphuhhw frxwhufrxwlhdeoh glvdeoh hdeoh lw t2eg hwfrxwhudfwlhhghvhohfwlr frxwrudlvlhgh frxwridoolhgh 3xovh :lgwk dswxuhdfwlhhghvhohfwlr vwduwfrxwlridoolhghvwrsrudlvlhgh vwduwfrxwlrudlvlhghvwrsridoolhgh lw xlpsohphwhguhdgdv
rev. 1.10 56 ?a? 0?? ?01? rev. 1.10 57 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu to choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width capture mode, bits 7 and 6 of the timer control register, which are known as the bit pair tnm1/tnm0, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as tnon, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. bits 0~2 of the timer control register determine the division ratio of the input clock prescaler. the prescaler bit settings have no effect if an external clock source is used. if the timer is in the event count or pulse width capture mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as tneg. the tns bit selects the internal clock source if used. timer mode in this mode, the timer/event counter can be utilised to measure fxed time intervals, providing an internal interrupt signal each time the timer/event counter overfows. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating ?ode bit7 bit6 select bits for the timer ?ode 1 0 in this mode the internal clock is used as the timer clock. the timer input clock source is either f sys , f sys /4 or the lxt oscillator. however, this timer clock source is further divided by a prescaler, the value of which is determined by the bits tnpsc2~tnpsc0 in the timer control register. the timer- on bit, tnon must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overfows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. a timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the etni bits of the intcn register are reset to zero. event counter mode in this mode, a number of externally changing logic events, occurring on the external timer tcn pin, can be recorded by the timer/event counter. to operate in this mode, the operating mode select bit pair, tnm1/tnm0, in the timer control register must be set to the correct value as shown. control register operating ?ode bit7 bit6 select bits for the event counter ?ode 0 1 in this mode, the external timer tcn pin, is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit, tneg, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the tneg is high, the counter will increment each time the external timer pin receives a high to low transition. when it is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero.
rev. 1.10 58 ?a? 0?? ?01? rev. 1.10 59 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu as the external timer pin is shared with an i/o pin, to ensure that the pin is confgured to operate as an event counter input pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register confgures the pin as an input. it should be noted that in the event counting mode, even if the is in the idle/sleep mode, the timer/event counter will continue to record externally changing logic events on the timer input tcn pin. as a result when the timer overfows it will generate a timer interrupt and corresponding wake-up source.
timer mode timing chart
event counter mode timing chart (tneg=1) pulse width capture mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. to operate in this mode, the operating mode select bit pair, tnm1/ tnm0, in the timer control register must be set to the correct value as shown. control register operating ?ode bit7 bit6 select bits for the pulse width capture ?ode 1 1 in this mode the internal clock, f sys , f sys /4 or the lxt, is used as the internal clock for the 8-bit timer/event counter. however, the clock source, f sys , for the 8-bit timer is further divided by a prescaler, the value of which is determined by the prescaler rate select bits tnpsc2~tnpsc0, which are bits 2~0 in the timer control register. after the other bits in the timer control register have been setup, the enable bit tnon, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit tneg, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width capture mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control.
rev. 1.10 58 ?a? 0?? ?01? rev. 1.10 59 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the tcn pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. the timer cannot begin further pulse width capture until the enable bit is set high again by the program. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. when the timer/event counter is full and overfows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the corresponding interrupt control register, is reset to zero. as the tcn pin is shared with an i/o pin, to ensure that the pin is confgured to operate as a pulse width capture pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the pulse width capture mode, the second is to ensure that the port control register confgures the pin as an input. prescaler bits t0psc0~t0psc2 of the tmr0c register can be used to defne a division ratio for the internal clock source of the timer/event counter enabling longer time out periods to be setup. pfd function the programmable frequency divider provides a means of producing a variable frequency output suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise frequency generator. the timer/event counter overfow signal is the clock source for the pfd function, which is controlled by pfdcs bit in ctrl0. for applicable devices the clock source can come from either timer/event counter 0 or timer/event counter 1. the output frequency is controlled by loading the required values into the timer prescaler and timer registers to give the required division ratio. the counter will begin to count-up from this preload register value until full, at which point an overfow signal is generated, causing both the pfd outputs to change state. the counter will then be automatically reloaded with the preload register value and continue counting-up. if the ctrl0 register has selected the pfd function, then for pfd output to operate, it is essential for the port a control register pac, to setup the pfd pins as outputs. pa1 must be set high to activate the pfd. the output data bits can be used as the on/off control bit for the pfd outputs. note that the pfd outputs will all be low if the output data bit is cleared to zero. using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated.

? ? ? ? ? ? ? ? ? pulse width capture mode timing chart (tne=0)
rev. 1.10 60 ?a? 0?? ?01? rev. 1.10 61 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

pfd function i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width capture mode, requires the use of an external timer pin for its operation. as this pin is a shared pin it must be confgured correctly to ensure that it is setup for use as a timer/event counter input pin. this is achieved by ensuring that the mode select bits in the timer/event counter control register, select either the event counter or pulse width capture mode. additionally the corresponding port control register bit must be set high to ensure that the pin is setup as an input. any pull-high resistor connected to this pin will remain valid even if the pin is used as a timer/event counter input. programming considerations when confgured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program fow to the respective internal interrupt vector. for the pulse width capture mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is confgured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly initialised before using them for the frst time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly confgured for the required application. it is also important to ensure that an initial value is frst loaded into the timer registers before the timer is switched on; this is because after power- on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. when the timer/event counter overfows, its corresponding interrupt request fag in the interrupt control register will be set. if the timer/event counter interrupt is enabled this will in turn generate an interrupt signal. however irrespective of whether the interrupts are enabled or not, a timer/event counter overfow will also generate a wake-up signal if the device is in a power-down condition. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these external events and if an overfow occurs the device will be woken up from its power- down condition. to prevent such a wake-up from occurring, the timer interrupt request fag should frst be set high before issuing the "halt" instruction to enter the idle/sleep mode.
rev. 1.10 60 ?a? 0?? ?01? rev. 1.10 61 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu timer program example the program shows how the timer/event counter registers are setup along with how the interrupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counters to be in the timer mode, which uses the internal system clock as their clock source. pfd programming example org 04h ; external interrupt vector org 08h ; timer counter 0 interrupt vector s ul s huh h 7lhu yhu : : org 20h ; main program : : ;internal timer 0 interrupt routine tmr0int: : ; timer 0 main program placed here : : begin: ;setup timer 0 registers mov a,09bh ; setup timer 0 preload value mov tmr0,a mov a,081h ; setup timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ;setup interrupt register mov a,00dh ; enable master interrupt and both timer interrupts mov intc0,a : : set tmr0c.4 ; start timer 0 : : time base the device includes a time base function which is used to generate a regular time interval signal. the time base time interval magnitude is determined using an internal 13 stage counter sets the division ratio of the clock source. this division ratio is controlled by both the tbsel0 and tbsel1 bits in the ctrl1 register. the clock source is selected using the t0s bit in the tmr0c register. when the time base time out, a time base interrupt signal will be generated. it should be noted that as the time base clock source is the same as the timer/event counter clock source, care should be taken when programming.
rev. 1.10 6? ?a? 0?? ?01? rev. 1.10 63 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pulse width modulator every device includes a multiple output 8-bit pwm function. useful for such applications such as motor speed control, the pwm function provides outputs with a fxed frequency but with a duty cycle that can be varied by setting particular values into the corresponding pwm register.

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? ? pwm block diagram device channels mode pins registers ht46r068b ht46r069b 4 6+? 7+1 pa4 pc3 pc? pd1 pw?0 pw?1 pw?? pw?3
rev. 1.10 6? ?a? 0?? ?01? rev. 1.10 63 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pwm operation a single register, known as pwmn and located in the data memory is assigned to each pulse width modulator channel. it is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. to increase the pwm modulation frequency, each modulation cycle is subdivided into two or four individual modulation subsections, known as the 7+1 mode or 6+2 mode respectively. the required mode and the on/off control for each pwm channel is selected using the ctrl0 and ctrl2 registers. note that when using the pwm, it is only necessary to write the required value into the pwmn register and select the required mode setup and on/off control using the ctrl0 and ctrl2 registers, the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. the pwm clock source is the system clock f sys . this method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enable the generation of higher pwm frequencies which allow a wider range of applications to be served. the difference between what is known as the pwm cycle frequency and the pwm modulation frequency should be understood. as the pwm clock is the system clock, f sys , and as the pwm value is 8-bits wide, the overall pwm cycle frequency is f sys /256. however, when in the 7+1 mode of operation the pwm modulation frequency will be f sys /128, while the pwm modulation frequency for the 6+2 mode of operation will be f sys /64. pwm modulation pwm cycle frequency pwm cycle duty f sys /64 for (6+?) bits mode f sys /1?8 for (7+1) bits mode f sys /?56 [pw?]/?56 6+2 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 6+2 pwm mode, each pwm cycle is subdivided into four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. each one of these four sub-cycles contains 64 clock cycles. in this mode, a modulation frequency increase of four is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit2~bit7 is denoted here as the dc value. the second group which consists of bit0~bit1 is known as the ac value. in the 6+2 pwm mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. parameter ac (0~3) dc (duty cycle) ?odulation c?cle i (i=0~3) i < ac dc+1 64 l& dc 64 6+2 mode modulation cycle values the following diagram illustrates the waveforms associated with the 6+2 mode of pwm operation. it is important to note how the single pwm cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the ac value is related to the pwm value.
rev. 1.10 64 ?a? 0?? ?01? rev. 1.10 65 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

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6+2 pwm mode pwm register for 6+2 mode 7+1 pwm mode each full pwm cycle, as it is controlled by an 8-bit pwm register, has 256 clock periods. however, in the 7+1 pwm mode, each pwm cycle is subdivided into two individual sub-cycles known as modulation cycle 0 ~ modulation cycle 1, denoted as i in the table. each one of these two sub-cycles contains 128 clock cycles. in this mode, a modulation frequency increase of two is achieved. the 8-bit pwm register value, which represents the overall duty cycle of the pwm waveform, is divided into two groups. the frst group which consists of bit1~bit7 is denoted here as the dc value. the second group which consists of bit0 is known as the ac value. in the 7+1 pwm mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. parameter ac (0~1) dc (duty cycle) ?odulation c?cle i (i=0~1) i < ac dc+1 1?8 l& dc 1?8 7+1 mode modulation cycle values the following diagram illustrates the waveforms associated with the 7+1 mode pwm operation. it is important to note how the single pwm cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how the ac value is related to the pwm value.
rev. 1.10 64 ?a? 0?? ?01? rev. 1.10 65 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu pwm output control the pwm outputs are pin-shared with the i/o pins pa4, pc2 and pc3. to operate as a pwm output and not as an i/o pin, the correct bits must be set in the ctrl0 and ctrl2 register. a zero value must also be written to the corresponding bit in the i/o port control register pac.4, pcc.2 and pcc.3 to ensure that the corresponding pwm output pin is setup as an output. after these two initial steps have been carried out, and of course after the required pwm value has been written into the pwmn register, writing a high value to the corresponding bit in the output data register pa.4, pc.2 and pc.3 will enable the pwm data to appear on the pin. writing a zero value will disable the pwm output function and force the output low. in this way, the port data output registers can be used as an on/off control for the pwm function. note that if the ctrl0 and ctrl2 registers have selected the pwm function, but a high value has been written to its corresponding bit in the pac or pcc control register to confgure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options.

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7+1 pwm mode pwm register for 7+1 mode pwm programming example 7kh iroorzlqj vdpsoh surjudp vkrzv krz wkh 3:0 rxwsxw lv vhwxs dqg frqwuroohg pry dk vhwxs 3:0 ydoxh ri ghflpdo mov pwm0,a h fuo hohf h 3:0 h h fuo hohf sl 3 dyh d 3:0 ifl fou sdf hs sl 3 d d s h sd hdeoh h 3:0 s : : fou sd ldeoh h 3:0 sb sl 3 iufh o
rev. 1.10 66 ?a? 0?? ?01? rev. 1.10 67 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a , they must frst be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains an 4/8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. part no. input channels conversion bits input pins ht46r068b 16 1? pa0~pa3 pc0~pc1 pc6~pc7 pe0~pe7 ht46r069b the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. a/d converter data registers C adrl, adrh the device, which has an internal 12-bit a/d converter, requires two data registers, a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. only the high byte register, adrh, utilises its full 8-bit contents. the low byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. in the following table, d0~d11 is the a/d conversion data result bits. register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adrl d3 d? d1 d0 adrh d11 d10 d9 d8 d7 d6 d5 d4 a/d data registers a/d converter control registers C adcr, acsr, ancsr1, ancsr0 to control the function and operation of the a/d converter, four control registers known as adcr, acsr, ancsr1 and ancsr0 are provided. these 8-bit registers define functions such as the selection of which analog channel is connected to the internal a/d converter, which pins are used as analog inputs and which are used as normal i/os, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs3~acs0 bits in the adcr register defne the channel number. as the device contains only one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. it is the function of the acs3~acs0 bits in the adcr register to determine which analog channel is actually connected to the internal a/d converter.
rev. 1.10 66 ?a? 0?? ?01? rev. 1.10 67 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu the two control registers, ancsr1,ancsr0, determine which pins on pa0~pa3, pc0, pc1, pc6, pc7, pe0~pe7 are used as analog inputs for the a/d converter and which pins are to be used as normal i/o pins. if the 16-bit address on pcr15~pcr0 has a value of ffh, then all 16 pins, namely an0~an15 will all be set as analog inputs. to reduce the power consumption in normal run, the adc module can be turned off by setting adonb=1 in acsr. once the adc module is turned off, the adc module and analog channel have no power consumption no matter what voltage level is on analog input. if the i/o lines is selected as an i/o function and the analog input pin voltage is not equal to v dd or v ss , there user may have to take care idd/istb current consumed by the pin- shared logic input function no matter the adc module is on or off. if the adc module is turned off, then all the adc pin-shared i/o pins will be setup as normal i/os.

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rev. 1.10 68 ?a? 0?? ?01? rev. 1.10 69 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? adcr register bit 7 6 5 4 3 2 1 0 name start eocb acs3 acs? acs1 acs0 r/w r/w r r/w r/w r/w r/w por 0 1 0 0 0 0 0 0 %lw start 6wduwwkh frhuvlr ::vwduw :uhvhwwkh frhuwhudgvhw2wr 7klvelwlvxvhgwrllwldwhd frhuvlrsurfhvv 7khelwlvrupdooorzexw livhwklkdgwkhfohduhgorzddlwkh frhuwhuzloollwldwhdfrhuvlr surfhvv :khwkhelwlvvhwklkwkh frhuwhuzlooehuhvhw lw eocb gri frhuvlrd frhuvlrhghg frhuvlrlsuruhvv 7klvuhdgrodlvxvhgwrlglfdwhzkhd frhuvlrsurfhvvkdv frpsohwhg :khwkhfrhuvlrsurfhvvlvuxlwkhelwzlooehklk lwlw xlpsohphwhguhdgdv lw acs3, acs2, acs1, acs0 6hohfw fkdho 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7khvh duh wkh fkdho vhohfw frwuro elwv v wkhuh lv ro rh lwhudo kdugzduh frhuwhu hdfkriwkhhlkw lsxwvpxvwehurxwhgwrwkhlwhudofrhuwhuxvlwkhvhelwv
rev. 1.10 68 ?a? 0?? ?01? rev. 1.10 69 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? acsr register bit 7 6 5 4 3 2 1 0 name test adonb vrefs adcs? adcs1 adcs0 r/w r r/w r/w r/w r/w r/w por 1 1 0 0 0 0 %lw test iruwhvwprghxvhro lw adonb prgxohsrzhu rriifrwuroelw prgxohsrzhur prgxohsrzhu rii 7klv elw frwurov wkh srzhu wr wkh lwhudo ixfwlr 7klv elw vkrxog eh fohduhg wr hur wr hdeoh wkh frhuwhu ,i wkh elw lv vhw klk wkh wkh frhuwhu zloo eh vzlwfkhg rii uhgxfl wkh ghlfh srzhu frvxpswlr v wkh frhuwhu zloo frvxph d olplwhg dprxw ri srzhu hh zkh rw hhfxwl d frhuvlr wklv pd eh d lpsruwdw frvlghudwlr l srzhu vhvlwlh edwwhu srzhuhg dssolfdwlrv 1rwh ,w lv uhfrpphghg wr vhw adonb ehiruh hwhul wkh ,/6/3 0rgh iruvdl srzhu lw xlpsohphwhguhdgdv lw vrefs 6hohfw uhihuhfhrowdh 9 dd 95sl 7klv elw lv xvhg wr vhohfw wkh uhihuhfh rowdh iru wkh frhuwhu ,i wkh elw lv klk wkh wkh frhuwhu uhihuhfh rowdh lv vxssolhg r whk hwhudo 95 sl ,i wkh sl lv orz wkh wkh lwhudo uhihuhfh lv xvhg zklfk lv wdnh iurp wkh szrhu vxssosl 9 dd lw xlpsohphwhguhdgdv lw adcs2~adcs0 6hohfw frhuwhuforfnvrxufh vvwhpforfn vvwhpforfn vvwhpforfn xghhgfdwehxvhg vvwhpforfn vvwhpforfn vvwhpforfn xghhgfdwehxvhg 7khvhwkuhhelwvduhxvhgwrvhohfwwkhforfnvrxufhiruwkh frhuwhu
rev. 1.10 70 ?a? 0?? ?01? rev. 1.10 71 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? ancsr0 register bit 7 6 5 4 3 2 1 0 name pcr7 pcr6 pcr5 pcr4 pcr3 pcr? pcr1 pcr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw pcr7 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr6 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr5 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr4 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr3 hh 3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr2 hh 3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr1 hh 3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr0 hh 3lv lsxwrurw 1rw lsxw lsxw 1
rev. 1.10 70 ?a? 0?? ?01? rev. 1.10 71 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? ancsr1 register bit 7 6 5 4 3 2 1 0 name pcr15 pcr14 pcr13 pcr1? pcr11 pcr10 pcr9 pcr8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw pcr15 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr14 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr13 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr12 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr11 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr10 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr9 hh3lv lsxwrurw 1rw lsxw lsxw 1 lw pcr8 hh3lv lsxwrurw 1rw lsxw lsxw 1 7kh 6757 elw l wkh uhlvwhu lv xvhg wr vwduw dg uhvhw wkh frhuwhu :kh wkh vhwv wklv elw iurp orz wr klk dg wkh orz ddl d ddor wr gllwdo frhuvlr ffoh zloo eh llwldwhg :kh wkh 6757 elw lv eurxkw iurp orz wr klk exw rw orz ddl wkh 2 elw l wkh 5 uhlvwhu zloo eh vhw wrd dg wkh ddor wr gllwdo frhuwhu zloo eh uhvhw,w lv wkh 6757 elw wkdwlvxvhg wr frwurowkhrhudoovwduwrshudwlrriwkhlwhudoddorwrgllwdo frhuwhu 7kh 2 elw l wkh 5 uhlvwhu lv xvhg wr lglfdwh zkh wkh ddor wr gllwdo frhuvlr surfhvv lv frpsohwh 7klv elw zloo eh dxwrpdwlfdoo vhw wr e wkh plfurfrwuroohu diwhu d frhuvlr ffoh kdv hghg , dgglwlr wkh fruuhvsrgl lwhuuxsw uhtxhvw d zloo eh vhw l wkh lwhuuxsw frwuro uhlvwhu dg li wkh lwhuuxswv duh hdeohg d dssursuldwh lwhudo lwhuuxsw vldo zloo eh hhudwhg 7klv lwhudo lwhuuxsw vldo zloo gluhfw wkh surudp iorz wr wkh dvvrfldwhg lwhudo lwhuuxsw dgguhvv iru surfhvvl ,i wkh lwhudo lwhuuxsw lv glvdeohg wkh plfurfrwuroohu fd eh xvhg wr sroo wkh 2 elw l wkh 5 uhlvwhu wr fkhfn zkhwkhu lw kdv ehh fohduhgdvddowhudwlhphwkrgrighwhfwlwkhhgrid frhuvlrffoh 7kh forfn vrxufh iru wkh frhuwhu zklfk rulldwhv iurp wkh vvwhp forfn i ss lv uvw gllghg e d gllvlr udwlr wkh doxh ri zklfk lv ghwhuplhg e wkh 6 6 dg 6 elwv l wkh 65 uhlvwhu
rev. 1.10 7? ?a? 0?? ?01? rev. 1.10 73 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu controlling the power on/off function of the a/d converter circuitry is implemented using the value of the adonb bit. although the a/d clock source is determined by the system clock f sys , and by bits adcs2, adcs1 and adcs0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t ad , is 0.5s, care must be taken for system clock speeds in excess of 4mhz. for system clock speeds in excess of 4mhz, the adcs2, adcs1 and adcs0 bits should not be set to "000". doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t ad ) adcs2, adcs1, adcs0=000 (f sys /2) adcs2, adcs1, adcs0=001 (f sys /8) adcs2, adcs1, adcs0=010 (f sys /32) adcs2, adcs1, adcs0=100 (f sys ) adcs2, adcs1, adcs0=101 (f sys /4) adcs2, adcs1, adcs0=110 (f sys /16) adcs2, adcs1, adcs0=011, 111 1?hz ? s 8 s 3? s 1 s 4 s 16 s 8qghqhg ??hz 1 s 4 s 16 s 500ns ? s 8 s 8qghqhg 4?hz 500ns ? s 8 s qv 1 s 4 s 8qghqhg 8?hz qv 1 s 4 s qv 500ns ? s 8qghqhg 1??hz qv 667ns ?.67 s qv qv 1 s 8qghqhg a/d clock period examples a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a, port c and port e. bits pcr15~pcr0 in the ancsr0 and ancsr1 registers, determine whether the input pins are setup as normal input/output pins or whether they are setup as analog inputs. in this way, pins can be changed under program control to change their function from normal i/o operation to analog inputs and vice versa. pull-high resistors, which are setup through register programming, apply to the input pins only when they are used as normal i/o pins, if setup as a/d inputs the pull-high resistors will be automatically disconnected. note that it is not necessary to frst setup the a/d pin as an input in the pac, pcc and pec port control registers to enable the a/d input as when the pcr15~pcr0 bits enable an a/d input, the status of the port control register will be overridden. summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adcs2, adcs1 and adcs0 in the register. ? step 2 select which pins are to be used as a/d inputs and confgure them as a/d input pins by correctly programming the pcr15~pcr0 bits in the ancsr0, ancsr1 registers. ? step 3 enable the a/d by clearing the adonb in the acsr register to zero.
rev. 1.10 7? ?a? 0?? ?01? rev. 1.10 73 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? step 4 select which channel is to be connected to the internal a/d converter by correctly programming the acs3~acs0 bits which are also contained in the register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, the intc0 interrupt control register must be set to 1, the a/d converter interrupt bit, ade, must also be set to 1. ? step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr register from 0 to 1 and then to 0 again. note that this bit should have been originally set to 0. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. the setting up and operation of the a/d converter function is fully under the control of the application program as there are no confguration options associated with the a/d converter. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t ad where t ad is equal to the a/d clock period. programming considerations when programming, special attention must be given to the pcr[15:0] bits in the register. if these bits are all cleared to zero no external pins will be selected for use as a/d input pins allowing the pins to be used as normal i/o pins. when this happens the internal a/d circuitry will be power down. setting the adonb bit high has the ability to power down the internal a/d circuitry, which may be an important consideration in power sensitive applications. a/d transfer function as the device contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd voltage, this gives a single bit analog input value of v dd /4096. the diagram show the ideal transfer function between the analog input value and the digitised output value for the a/d converter. note that to reduce the quantisation error, a 0.5 lsb offset is added to the a/d converter input. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd level.
rev. 1.10 74 ?a? 0?? ?01? rev. 1.10 75 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

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rev. 1.10 74 ?a? 0?? ?01? rev. 1.10 75 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b y6d hohf i sys /8 as a/d clock and adonb=0 mov a,0fh ; hs 16 d 16 fuh sl 1a1 y 1 6 d mov a, 00h y 1 6 d mov a,00000000b ; y'd select an0 to be connected to the a/d converter : 6dubfyhul fou677 h677 uhh ' fou677 du ' 3oolb2 2 soo h ' uhlhu 2 el hhf h ; of a/d conversion ssoolb2 flh sool yd'/ uhd o eh fyhul uho ydoh yduobeiihud dyh uho hu hh uhlhu yd' uhd l eh fyhul uho ydoh ydubeiihud dyh uho hu hh uhlhu : sdubfyhul du h ' fyhul note: to power off adc module, it is necessary to set adonb as "1".
rev. 1.10 76 ?a? 0?? ?01? rev. 1.10 77 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu example: using the interrupt method to detect the end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; select f sys /8 as a/d clock and adonb=0 mov a,0fh ; setup ancsr0 and ancsr1 to confgure pins an0~an3 m o v a n c s r 0 , a mov a, 00h m o v a n c s r 1 , a ; mov a,00000000b ; mov adcr, a ; select an0 to be connected to the a/d converter : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set eadi ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory clr adf ; clear adc interrupt fag reti 1h 7 shu ii 'ohllhfhduh '21d
rev. 1.10 76 ?a? 0?? ?01? rev. 1.10 77 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer/event counter or time base requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains a single external interrupt and multiple internal interrupts. the external interrupt is controlled by the action of the external interrupt pin, while the internal interrupts are generated by the various functions such as timer/event counters, and time base. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by using two registers, intc0 and intc1. by controlling the appropriate enable bits in this registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request fag will be set by the microcontroller. the global enable fag if cleared to zero will disable all interrupts. ? intc0 register bit 7 6 5 4 3 2 1 0 name t1f t0f eif et1i et0i eei e?i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 t1f : timer/event counter 1 interrupt request fag 0: inactive 1: active bit 5 t0f : timer/event counter 0 interrupt request fag 0: inactive 1: active bit 4 eif : external interrupt request fag 0: inactive 1: active bit 3 et1i : timer/event counter 1 interrupt enable 0: disable 1: enable bit 2 et0i : timer/event counter 0 interrupt enable 0: disable 1: enable bit 1 eei : external interrupt enable 0: disable 1: enable bit 0 emi : master interrupt global enable 0: disable 1: enable
rev. 1.10 78 ?a? 0?? ?01? rev. 1.10 79 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? intc1 register bit 7 6 5 4 3 2 1 0 name p ?ff adf t?f p e?fi eadi et?i r/w p r/w r/w r/w p r/w r/w r/w por p 0 0 0 p 0 0 0 bit 7 unimplemented, read as 0 bit 6 mff : multi-function interrupt request fag 0: inactive 1: active bit 5 adf : a/d converter interrupt request fag 0: inactive 1: active bit 4 t2f : timer/event counter 2 interrupt request fag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 emfi : multi-function interrupt enable 0: disable 1: enable bit 1 eadi : a/d converter interrupt enable 0: disable 1: enable bit 0 et2i : timer/event counter 2 interrupt enable 0: disable 1: enable ? mfic register bit 7 6 5 4 3 2 1 0 name p sif si?f tbf p esii esi? etbi r/w p r/w r/w r/w p r/w r/w r/w por p 0 0 0 p 0 0 0 bit 7 unimplemented, read as 0 bit 6 sif : spia interrupt request fag 0: inactive 1: active bit 5 simf : sim interrupt request fag 0: inactive 1: active bit 4 tbf : time base interrupt request fag 0: inactive 1: active bit 3 unimplemented, read as 0 bit 2 esii : spia interrupt enable 0: disable 1: enable bit 1 esim : sim interrupt enable 0: disable 1: enable bit 0 etbi : time base interrupt enable 0: disable 1: enable
rev. 1.10 78 ?a? 0?? ?01? rev. 1.10 79 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu interrupt operation a timer/event counter overflow, an active edge on the external interrupt pin, a serial data byte transmitted or received completion, or a time base event will all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti instruction, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority.

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? once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full.
rev. 1.10 80 ?a? 0?? ?01? rev. 1.10 81 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu when an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps to the interrupt vector. if the device is in the sleep or idle mode and is woken up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector. wait for ? ~ 3 instruction c?cles ?ain program isr entr? ? ? enable bit set ? ?ain program reti ( it will set e?i automaticall? ) automaticall? disable interrupt clear e?i & request flag n y interrupt flow interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h 7lphu(yhqw&rxqwhu?yhurz ? 08h 7lphu(yhqw&rxqwhu?yhurz 3 0ch 7lphu(yhqw&rxqwhu?yhurz 4 10h a/d interrupt 5 14h ?ulti-function interrupt (time base ? si?? spia) 6 18h in cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced frst. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences.
rev. 1.10 80 ?a? 0?? ?01? rev. 1.10 81 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu external interrupt for an external interrupt to occur, the global interrupt enable bit, emi, and external interrupt enable bit, inte, must frst be set. an actual external interrupt will take place when the external interrupt request fag, intf, is set, a situation that will occur when an edge transition appears on the external int line. the type of transition that will trigger an external interrupt, whether high to low, low to high or both is determined by the integ0 and integ1 bits, which are bits 6 and 7 respectively, in the ctrl1 control register. these two bits can also disable the external interrupt function. integ1 integ0 edge trigger type 0 0 external interrupt disable 0 1 rising edge trigger 1 0 falling edge trigger 1 1 both edge trigger the external interrupt pin is pin-shared with the i/o pin pa3 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the intc0 register has been set and the edge trigger type has been selected using the ctrl1 register. the pin must also be setup as an input by setting the corresponding pac.3 bit in the port control register. when the interrupt is enabled, the stack is not full and an active transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04h, will take place. when the interrupt is serviced, the external interrupt request fag, eif, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, tne, must first be set. an actual timer/event counter interrupt will take place when the timer/event counter request fag, tnf, is set, a situation that will occur when the relevant timer/event counter overfows. when the interrupt is enabled, the stack is not full and a timer/event counter n overfow occurs, a subroutine call to the relevant timer interrupt vector, will take place. when the interrupt is serviced, the timer interrupt request fag, tnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt unlike the other independent interrupts, the multi-function interrupt has no independent source, but rather is formed from other existing interrupt sources, namely the time-base interrupt, sim interrupt and spia interrupt. a multi-function interrupt request will take place when the multi-function interrupt request fag, mff is set. the multi-function interrupt fag will be set when any of their included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to the multi-function interrupt vector will take place. when the interrupt is serviced, the multi- function interrupt request flag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt fag will be automatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupt, namely the time-base interrupt, sim interrupt and spia interrupt will not be automatically reset and must be manually reset by the application program. after a multi-function has been generated, the application program can determine which interrupt source has occurred by interrogating the interrupt request fags, sif, simf or tbf within the mfic register.
rev. 1.10 8? ?a? 0?? ?01? rev. 1.10 83 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will re- main in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within the multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request fag, mff, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before entering the sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.10 8? ?a? 0?? ?01? rev. 1.10 83 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu lcd scom function the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~scom3, are pin shared with the pb0~ pb3 pins. the lcd signals, com and seg, are generated using the application program. lcd operation an external lcd panel can be driven using this device by confguring the pb0~pb3 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd com driver to generate the necessaryv dd /2 voltage levels for lcd 1/2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port b pins are used for lcd driving. note that the port control register does not need to frst setup the pins as outputs to enable the lcd driver operation.
scom circuit scomen comnen pin function o/p level 0 x i/o 0 or 1 1 0 i/o 0 or 1 1 1 sco?n v dd /? output control
rev. 1.10 84 ?a? 0?? ?01? rev. 1.10 85 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and isel0 bits in the scomc register. ? scomc register bit 7 6 5 4 3 2 1 0 name isel1 isel0 sco?en co?3en co??en co?1en co?0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 reserved bit 1: unpredictable operation - bit must not be set high 0: correct level - bit must be reset to zero for correct operation bit 6,5 isel1, isel0 : scom operating current selection (v =5v) 00: 25a 01: 50a 10: 100a 11: 200a bit 4 scomen : scom module on/off control 0: disable 1: enable scomn can be enable by comnen if scomen=1 bit 3 com3en : pb3 or scom3 selection 0: i/o 1: scom3 bit 2 com2en : pb2 or scom2 selection 0: i/o 1: scom2 bit 1 com1en : pb1 or scom1 selection 0: i/o 1: scom1 bit 0 com0en : pb0 or scom0 selection 0: i/o 1: scom0
rev. 1.10 84 ?a? 0?? ?01? rev. 1.10 85 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu serial interface module C sim these devices contain a serial interface module, which includes both the four line spi interface or the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface function must frst be selected using a confguration option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o are selected using pull-high control registers, and also if the sim function is enabled. spi interface this spi interface function which is part of the serial interface module, should not be confused with the other independent spi function, known as spia, which is described in another section of this datasheet. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spi interface specifcation can control multiple slave devices from a single master, but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. ? spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must frst be enabled by selecting the sim enable confguration option and setting the correct bits in the simc0 and simc2 registers. after the spi confguration option has been confgured it can also be additionally disabled or enabled using the simen bit in the simc0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to "0" the scs pin will be foating state. spi master/slave connection
rev. 1.10 86 ?a? 0?? ?01? rev. 1.10 87 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

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? ?? ? ? ? ? spi block diagram the spi function in this device offers the following features: ? full duplex synchronous data transferboth master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? wcol and csen bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. there are several configuration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. another two spi confguration options determine if the csen and wcol bits are to be used.
rev. 1.10 86 ?a? 0?? ?01? rev. 1.10 87 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 si?c0 si?? si?1 si?0 pcken pckp1 pckp0 si?en si?d d7 d6 d5 d4 d3 d? d1 d0 si?c? d7 d6 ckpolb ckeg ?ls csen wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. ? simd regisater bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc.
rev. 1.10 88 ?a? 0?? ?01? rev. 1.10 89 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? simc0 register bit 7 6 5 4 3 2 1 0 name si?? si?1 si?0 pcken pckp1 pckp0 si?en r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 %lwa sim2, sim1, sim0 6,02shudwl0rghrwuro 63,pdvwhuprgh63,forfnlvi ss 63,pdvwhuprgh63,forfnlvi ss 63,pdvwhuprgh63,forfnlvi ss 63,pdvwhuprgh63,forfnlvi /7 63,pdvwhuprgh63,forfnlv 7lphuhw rxwhurxwsxw3 63,vodhprgh , vodhprgh 8xvhgprgh 7khvhelwvvhwxswkhrhudoorshudwlprghriwkh6,0ixfwlr vzhoodvvhohfwl li wkh , ru 63, ixfwlr wkh duh xvhg wr frwuro wkh 63, 0dvwhu6odh vhohfwlr dg wkh 63, 0dvwhu forfn iuhtxhf 7kh 63, forfn lv d ixfwlr ri wkh vvwhp forfn exw fd dovr eh fkrvh wr eh vrxufhg iurp wkh 7lphuhw rxwhu ,i wkh 63, 6odh0rghlvvhohfwhgwkhwkhforfnzlooehvxssolhgedhwhudo0dvwhughlfh lw pcken 3hulskhudoorfn3lrwuro hvfulehg hovhzkhuh lw pckp1, pckp0 6hohfw3rxwsxwsliuhtxhf hvfulehghovhzkhuh lw simen 6,0rwuro lvdeoh deoh 7kh elw lv wkh rhudoo rrii frwuro iru wkh 6,0 lwhuidfh :kh wkh 6,01 elw lv fohduhg wr hur wr glvdeoh wkh 6,0 lwhuidfh wkh 6, 62 6 dg 66 ru 6 dg 6/ olhv zloo eh l d rdwl frglwlr dg wkh 6,0 rshudwl fxuuhw zloo eh uhgxfhg wr d pllpxp doxh :kh wkh elw lv klk wkh 6,0 lwhuidfh lv hdeohg 7kh 6,0 frilxudwlr rswlr pxvw kdh iluvw hdeohg wkh 6,0 lwhuidfh iru wklv elw wr eh hiihfwlh ,i wkh 6,0 lv frxuhg wr rshudwh dv d 63, lwhuidfh ld wkh 6,06,0elwvwkhfrwhwvriwkh63,frwurouhlvwhuvzloouhpdldwwkhsuhlrxv vhwwlv zkh wkh 6,01 elw fkdhv iurp orz wr klk dg vkrxog wkhuhiruh eh uvw llwldolvhg e wkh dssolfdwlr surudp ,i wkh 6,0 lv frxuhg wr rshudwh dv d , lwhuidfh ld wkh 6,06,0 elwv dg wkh 6,01 elw fkdhv iurp orz wr klk wkh frwhwv ri wkh , frwuro elwv vxfk dv 7 dg 7 zloo uhpdl dw wkh suhlrxv vhwwlv dg vkrxog wkhuhiruh eh uvw llwldolvhg e wkh dssolfdwlr surudp zkloh wkh uhohdw , dv vxfk dv 6 65: dg 5 zloo eh vhw wr wkhlu ghidxowvwdwhv lw xlpsohphwhguhdgdv
rev. 1.10 88 ?a? 0?? ?01? rev. 1.10 89 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckpolb ckeg ?ls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 %lw a 8qghqhgelw 7khvh elwfdqehuhdgruzulwwhqexvhuvriwzduhsurjudp %lw ckpolb hwhuplhvwkhedvhfrglwlrriwkhforfn olh wkh6olhzlooehklkzkhwkhforfnlvldfwlh wkh6olhzlooehorzzkhwkhforfnlvldfwlh 7kh 32/ elw ghwhuplhv wkh edvh frglwlr ri wkh forfn olh li wkh elw lv klk wkh wkh 6 olh zloo eh orz zkh wkh forfn lv ldfwlh :kh wkh 32/ elw lv orz wkhwkh6olhzlooehklkzkhwkhforfnlvldfwlh lw ckeg hwhuplhv63,6dfwlhforfnhghwsh 32/ 6lvklkedvhohhodggdwdfdswxuhdw6ulvlhgh 6lvklkedvhohhodggdwdfdswxuhdw6idoolhgh 32/ 6lvorzedvhohhodggdwdfdswxuhdw6idoolhgh 6lvorzedvhohhodggdwdfdswxuhdw6ulvlhgh 7kh dg 32/ elwv duh xvhg wr vhwxs wkh zd wkdw wkh forfn vldo rxwsxwv dg lsxwv gdwd r wkh 63, exv 7khvh wzr elwv pxvw eh frxuhg ehiruh gdwd wudvihu lv hhfxwhg rwkhuzlvh d huurhrxv forfn hgh pd eh hhudwhg 7kh 32/ elw ghwhuplhv wkh edvh frglwlr ri wkh forfn olh li wkh elw lv klk wkh wkh 6 olh zloo eh orz zkh wkh forfn lv ldfwlh :kh wkh 32/ elw lv orz wkh wkh 6 olh zloo eh klk zkh wkh forfn lv ldfwlh 7kh elw ghwhuplhv dfwlh forfn hgh wsh zklfk ghshgv xsr wkh frglwlr ri32/elw lw mls 63,dwdvkliwrughu /6 06 7klv lv wkh gdwd vkliw vhohfw elw dg lv xvhg wr vhohfw krz wkh gdwd lv wudvihuuhg hlwkhu 06ru/6uvw6hwwlwkhelwklkzloovhohfw06uvwdgorziru/6uvw lw csen 63, 66 slrwuro lvdeoh deoh 7kh 61 elw lv xvhg dv d hdeohglvdeoh iru wkh 66 sl ,i wklv elw lv orz wkh wkh 66 sl zloo eh glvdeohg dg sodfhg lwr d iordwl frglwlr ,i wkh elw lv klk wkh 66 sl zloo eh hdeohg dg xvhg dv d vhohfw sl 1rwhwkdwxvlwkh61elwfdehglvdeohgruhdeohgldfrxudwlrrswlr lw wcol 63, :ulwh roolvlrd 1rfroolvlr roolvlr 7kh :2/ d lv xvhg wr ghwhfw li d gdwd froolvlr kdv rffxuuhg ,i wklv elw lv klk lw phdv wkdw gdwd kdv ehh dwwhpswhg wr eh zulwwh wr wkh 6,0 uhlvwhu gxul d gdwd wudvihu rshudwlr 7klv zulwl rshudwlr zloo eh lruhg li gdwd lv ehl wudvihuuhg 7khelwfdehfohduhgewkhdssolfdwlrsurudp1rwhwkdwxvlwkh :2/ elwfd ehglvdeohgruhdeohgldfrxudwlrrswlr
rev. 1.10 90 ?a? 0?? ?01? rev. 1.10 91 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu bit 0 trf : spi transmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete flag and is set "1" automatically when an spi data transmission is completed, but must set to "0" by the application program. it can be used to generate an interrupt. spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode.
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rev. 1.10 90 ?a? 0?? ?01? rev. 1.10 91 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

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rev. 1.10 9? ?a? 0?? ?01? rev. 1.10 93 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c mater slave bus connection ? i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode.

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rev. 1.10 9? ?a? 0?? ?01? rev. 1.10 93 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu there are several configuration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. a confguration option exists to allow a clock other than the system clock to drive the i 2 c interface. another confguration option determines the debounce time of the i 2 c interface. this uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 2 or 4 system clocks. i 2 c debounce time select i on i 2 c standard mode (100khz ) i 2 c fast mode (400khz) no debounce f sys > ??h z f sys > 5?hz ? s?stem clock debounce f sys > 4?hz f sys > 10 ?hz 4 s?stem clock debounce f sys > 8?hz f sys > ? 0 ?hz i 2 c minimum f sys frequency send slave address and r/w bit from ?aster start signal from ?aster acknowledge from slave send data b?te from ?aster acknowledge from slave stop signal from ?aster i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 si?c0 si?? si?1 si?0 pcken pckp1 pckp0 si?en si?c1 hcf haas hbb htx txak srw ia?wu rxak si?d d7 d6 d5 d4 d3 d? d1 d0 si?a iica6 iica5 iica4 iica3 iica? iica1 iica0 d0 i 2 c registers list
rev. 1.10 94 ?a? 0?? ?01? rev. 1.10 95 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? simc0 register bit 7 6 5 4 3 2 1 0 name si?? si?1 si?0 pcken pckp1 pckp0 si?en r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 %lwa sim2, sim1, sim0 6,02shudwl0rghrwuro 63,pdvwhuprgh63,forfnlvi ss 63,pdvwhuprgh63,forfnlvi ss 63,pdvwhuprgh63,forfnlvi ss 63,pdvwhuprgh63,forfnlvi /7 63,pdvwhuprgh63,forfnlv 7lphuhw rxwhurxwsxw3 63,vodhprgh , vodhprgh 8xvhgprgh 7khvh elwv vhwxs wkh rhudoo rshudwl prgh ri wkh 6,0 ixfwlr v zhoo dv vhohfwl li wkh , ru 63, ixfwlr wkh duh xvhg wr frwuro wkh 63, 0dvwhu6odh vhohfwlr dg wkh 63, 0dvwhu forfn iuhtxhf 7kh 63, forfn lv d ixfwlr ri wkh vvwhp forfn exw fd dovr eh fkrvh wr eh vrxufhg iurp 7lphuhw rxwhu ,i wkh 63, 6odh 0rghlvvhohfwhgwkhwkhforfnzlooehvxssolhgedhwhudo0dvwhughlfh lw pcken 3hulskhudoorfn3lfrwuro hvfulehghovhzkhuh lw pckp1, pckp0 6hohfw3rxwsxwsliuhtxhf hvfulehghovhzkhuh lw simen 6,0rwuro lvdeoh deoh 7khelwlvwkhrhudoo rriifrwuroiruwkh6,0 lwhuidfh :khwkh6,01elwlv fohduhgwrhurwrglvdeohwkh6,0lwhuidfhwkh6,626dg 66 ru6 dg6/ olhvzlooehldrdwlfrglwlrdgwkh6,0rshudwlfxuuhwzlooeh uhgxfhgwrdpllpxpdoxh :khwkhelwlvklkwkh6,0lwhuidfhlvhdeohg 7kh 6,0frxudwlrrswlrpxvwkdhuvwhdeohgwkh6,0lwhuidfhiruwklvelwwr eh hiihfwlh,iwkh6,0lvfrxuhgwrrshudwhdvd63,lwhuidfhld6,06,0 elwvwkhfrwhwvriwkh63,frwurouhlvwhuvzloouhpdldwwkhsuhlrxvvhwwlv zkhwkh6,01elwfkdhviurporzwrklkdgvkrxogwkhuhiruhehuvw llwldolvhgewkhdssolfdwlrsurudp,iwkh6,0lvfrxuhgwrrshudwhdvd, lwhuidfhldwkh6,06,0elwvdgwkh6,01elwfkdhviurporzwrklkwkh frwhwvriwkh, frwuroelwvvxfkdv7dg 7zloouhpdldw wkhsuhlrxv vhwwlvdgvkrxogwkhuhiruhehuvwllwldolvhgewkhdssolfdwlrsurudpzklohwkh uhohdw, dvvxfkdv 6 65: dg5zlooehvhwwrwkhlu ghidxowvwdwhv lw xlpsohphwhguhdgdv
rev. 1.10 94 ?a? 0?? ?01? rev. 1.10 95 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? simc1 register bit 7 6 5 4 3 2 1 0 name hcf haas hbb htx txak srw ia?wu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 %lw hcf , xvgdwdwudvihufrpsohwlrd dwdlvehlwudvihuuhg rpsohwlrridelwgdwdwudvihu 7khdlvwkhgdwdwudvihud 7klvdzlooeh hurzkhgdwdlvehl wudvihuuhg8srfrpsohwlrridelwgdwdwudvihuwkhdzloorklkdgd lwhuuxswzlooehhhudwhg lw haas , xvdgguhvvpdwfkd 1rwdgguhvvpdwfk gguhvvpdwfk 7kh6dlvwkhdgguhvvpdwfkd 7klvdlvxvhgwrghwhuplhliwkhvodh ghlfhdgguhvvlvwkhvdphdvwkhpdvwhuwudvplwdgguhvv,iwkhdgguhvvhvpdwfk wkhwklvelwzlooehklkliwkhuhlvrpdwfkwkhwkhdzlooeh orz lw hbb , xvexvd , xvlvrwexv , xvlvexv 7khdlvwkh, exvd 7klvdzlooehzkhwkh, exvlvexv zklfkzloorffxuzkhd 6757 vldolvghwhfwhg 7khdzlooehvhwwrzkh wkhexvlviuhhzklfkzloorffxuzkhd 6723 vldolvghwhfwhg lw htx 6hohfw, vodhghlfhlvwudvplwwhuruuhfhlhu 6odhghlfhlvwkhuhfhlhu 6odhghlfhlvwkhwudvplwwhu lw txak , xvwudvplwdfnrzohghd 6odhvhgdfnrzohghd 6odhgrrwvhgdfnrzohghd 7kh 7 elw lv wkh wudvplw dfnrzohgh d iwhu wkh vodh ghlfh uhfhlsw ri elwv ri gdwd wklv elw zloo eh wudvplwwhg wr wkh exv r wkh wk forfn iurp wkh vodh ghlfh 7kh vodh ghlfh pxvw dozdv vhw 7 elw wr ehiruh ixuwkhu gdwd lv uhfhlhg lw srw , 6odh 5hdg:ulwhd 6odhghlfhvkrxogehluhfhlhprgh 6odhghlfhvkrxogehlwudvplwprgh 7kh 65: iod lv wkh , 6odh 5hdg:ulwh iod 7klv iod ghwhuplhv zkhwkhu wkh pdvwhu ghlfh zlvkhv wr wudvplw ru uhfhlh gdwd iurp wkh , exv :kh wkh wudvplwwhg dgguhvv dg vodh dgguhvv lv pdwfk wkdw lv zkh wkh 6 d lv vhw klk wkh vodh ghlfh zloo fkhfn wkh 65: d wr ghwhuplh zkhwkhu lw vkrxog eh l wudvplw prgh ru uhfhlh prgh ,i wkh 65: d lv klk wkh pdvwhu lv uhtxhvwl wr uhdg gdwd iurp wkh exv vr wkh vodh ghlfh vkrxog eh l wudvplw prgh :kh wkh 65: d lv hur wkh pdvwhu zloo zulwh gdwd wr wkh exv wkhuhiruh wkh vodh ghlfh vkrxogehluhfhlhprghwruhdgwklvgdwd
rev. 1.10 96 ?a? 0?? ?01? rev. 1.10 97 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu bit 1 iamwu : i 2 c address match wake-up control 0: disable 1: enable C must be cleared byu the application program after wake-up the i 2 c module can run without using the internal clock, and generate an interrupt if the sim interrupt is enabled, which can be used in the sleep mode, idle mode, normal mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. note: if rnic=1 and mcu is powered down, the slave-receiver can remain operational but the slave-transmitter will not operate as it needs the system clock. bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag the rxak fag is the receiver acknowledge fag. when the rxak fag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak fag is "1". when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register.
rev. 1.10 96 ?a? 0?? ?01? rev. 1.10 97 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x " x " unknown ? sima register bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica4 iica3 iica? iica1 iica0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x " x " unknown %lwa iica6~ iica0 , vodhdgguhvv ,,,,lvwkh, vodhdgguhvvelwelw 7kh 6,0 uhlvwhu lv dovr xvhg e wkh 63, lwhuidfh exw kdv wkh dph 6,0 7kh 6,0 uhlvwhu lv wkh orfdwlr zkhuh wkh elw vodh dgguhvv ri wkh vodh ghlfh lv vwruhg lwv ri wkh 6,0 uhlvwhu ghh wkh ghlfh vodh dgguhvv lw lv rw ghhg :kh d pdvwhu ghlfh zklfk lv frhfwhg wr wkh , exv vhgv rxw d dgguhvv zklfk pdwfkhv wkh vodh dgguhvv l wkh 6,0 uhlvwhu wkh vodh ghlfh zloo eh vhohfwhg 1rwh wkdw wkh 6,0 uhlvwhu lv wkh vdph uhlvwhu dgguhvv dv 6,0 zklfk lv xvhgewkh63,lwhuidfh lw 8ghhgelw 7klvelwfdehuhdgruzulwwhexvhuvriwzduhsurudp i 2 c bus communication &rppxqlfdwlrq rq wkh , & exv uhtxluhv irxu vhsdudwh vwhsv d 6757 vljqdo d vodyh ghylfh dgguhvv wudqvplvvlrq d gdwd wudqvplvvlrq dqg ilqdoo d 6723 vljqdo :khq d 6757 vljqdo lv sodfhg rq wkh , & exv doo ghylfhv rq wkh exv zloo uhfhlyh wklv vljqdo dqg eh qrwlhg ri wkh lpplqhqw duulydo ri gdwd rq wkh exv 7kh uvw vhyhq elwv ri wkh gdwd zloo eh wkh vodyh dgguhvv zlwk wkh uvw elw ehlqj wkh 06 ,i wkh dgguhvv ri wkh vodyh ghylfh pdwfkhv wkdw ri wkh wudqvplwwhg dgguhvv wkh +6 elw lq wkh 6,0& uhjlvwhu zloo eh vhw dqg dq , & lqwhuuxsw zloo eh jhqhudwhg iwhu hqwhulqj wkh lqwhuuxsw vhuylfh urxwlqh wkh vodyh ghylfh pxvw uvw fkhfn wkh frqglwlrq ri wkh +6 elw wr ghwhuplqh zkhwkhu wkh lqwhuuxsw vrxufh ruljlqdwhv iurp dq dgguhvv pdwfk ru iurp wkh frpsohwlrq ri dq elw gdwd wudqvihu xulqj d gdwd wudqvihu qrwh wkdw diwhu wkh elw vodyh dgguhvv kdv ehhq wudqvplwwhg wkh iroorzlqj elw zklfk lv wkh wk elw lv wkh uhdgzulwh elw zkrvh ydoxh zloo eh sodfhg lq wkh 65: elw 7klv elw zloo eh fkhfnhg e wkh vodyh ghylfh wr ghwhuplqh zkhwkhu wr jr lqwr wudqvplw ru uhfhlyh prgh hiruh dq wudqvihu ri gdwd wr ru iurp wkh , & exv wkh plfurfrqwuroohu pxvw lqlwldolvh wkh exv wkh iroorzlqj duh vwhsvwrdfklhyhwklv 6whs 6hwwkh6,0a6,0dqg6,0(1elwvlqwkh6,0&uhjlvwhuwrwrhqdeohwkh, &exv 6whs :ulwh wkhvodyhdgguhvvriwkhghylfhwrwkh, &exvdgguhvvuhjlvwhu6,0 6whs 6hw wkh 6,0( dqg 6,0 0xwl)xqfwlrq lqwhuuxsw hqdeoh elw ri wkh lqwhuuxsw frqwuro uhjlvwhu wr hqdeohwkh6,0lqwhuuxswdqg0xowlixqfwlrqlqwhuuxsw
rev. 1.10 98 ?a? 0?? ?01? rev. 1.10 99 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

? ? ? ? ? ? - ? ? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.10 98 ?a? 0?? ?01? rev. 1.10 99 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to "1". if the srw fag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0". i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
rev. 1.10 100 ?a? 0?? ?01? rev. 1.10 101 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu
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- ? ? i 2 c communication timing diagram note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implemented a dummy read from the simd register to release the scl line.
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i 2 c bus isr flow chart
rev. 1.10 100 ?a? 0?? ?01? rev. 1.10 101 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originate from either the timer/event counter 0 output/2 or a divided ratio of the internal fsys clock. the pcken bit in the simc0 register is the overall on/off control, setting pcken bit to "1" enables the peripheral clock, setting pcken bit to "0" disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. ? simc0 register bit 7 6 5 4 3 2 1 0 name si?? si?1 si?0 pcken pckp1 pckp0 si?en r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control described elsewhere bit 4 pcken : peripheral clock pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f 01: f /4 10: f /8 11: timer/event counter 0 output /2 (pfd0) bit 1 simen : sim control described elsewhere bit 0 unimplemented, read as "0"
rev. 1.10 10? ?a? 0?? ?01? rev. 1.10 103 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu serial interface C spia the devices contain an independent spi function. it is important not to confuse this independent spi function with the additional one contained withing in the combined sim function, which is described in another section of this datasheet. this independent spi function will carry the name spia to distinguish it from the other one in the sim. this spia interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices, etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spia interface specifcation can control multiple slave devices from a single master, this device is provided only one scsa pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pins to select the slave devices. spia interface operation the spia interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdia, sdoa, scka and scsa . pins sdia and sdoa are the serial data input and serial data output lines, scka is the serial clock line and scsa is the slave select line. as the spia interface pins are pin-shared with other functions, the spia interface must frst be selected by the correct bits in the spiac0 and spiac1 registers. after the spia confguration option has been selected, it can also be additionally disabled or enabled using the spiaen bit in the spiac0 register. communication between devices connected to the spi1 interface is carried out in a slave/ master mode with all data transfer initiations being implemented by the master. the master also controls the clock/signal. as the device only contains a single sasa pin only one slave device can be utilised. the scsa pin is controlled by the application program, set the the sacsen bit to 1 to enable the scsa pin function and clear the sacsen bit to 0 to place the scsa pin into a foating state. spia master/slave connection
rev. 1.10 10? ?a? 0?? ?01? rev. 1.10 103 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu

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? ? ? ? ? spia block diagram the spia serial interface function includes the following features: ? full-duplex synchronous data transfer ? both master and slave mode ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge ? sawcol and sacsen bits enabled or disable select the status of the spia interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as sacsen and spiaen. there are several configuration options associated with the spia interface. one of these is to enable the spia function which selects the spia pins rather than normal i/o pins. note that if the confguration option does not select the spia function then the spiaen bit in the spiac0 register will have no effect. two confguration options, which are used to control the csen and wcol bit functions, are also used to determine if the sacsen and sawcol bits are to be used.
rev. 1.10 104 ?a? 0?? ?01? rev. 1.10 105 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu spia registers there are three registers which control the overall operation of the spia interface. these are the spiad data registers and two control registers spiac0 and spiac1. register name bit 7 6 5 4 3 2 1 0 spiac0 saspi? saspi1 saspi0 spiaen spiac1 sackpol sackeg sa?ls sacsen sawcol satrf spiad d7 d6 d5 d4 d3 d? d1 d0 spia registers list the spiad register is used to store the data being transmitted and received. before the device writes data to the spia bus, the actual data to be transmitted must be placed in the spiad register. after the data is received from the spia bus, the device can read it from the spiad register. any transmission or reception of data from the spia bus must be made via the spiad registers. ? spiad register bit 7 6 5 4 3 2 1 0 name spd7 spd6 spd5 spd4 spd3 spd? spd1 spd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por unknown there are also two control registers for the spia interface, spiac0 and spiac1. register spiac0 is used to control the enable/disable function and to set the data transmission clock frequency. register spiac1 is used for other control functions such as lsb/msb selection, write collision fag, etc. ? spiac0 register bit 7 6 5 4 3 2 1 0 name saspi? saspi1 saspi0 spiaen r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 0 bit 7 ~5 saspi2~saspi0: spia master/slave clock select 000: spia master, f /4 001: spia master, f /16 010: spia master, f /64 011: spia master, f lxt 100: spia master, timer 0 overfow/2 (pfd0) 101: spia slave 110: reserved : reserved bit 4~2 unimplemented, read as 0 bit spiaen: spia enable or disable 0: disable 1: enable the bit is the overall on/off control for the spi interface. when the s pia en bit is cleared to zero to disable the spia interface, the sdi , sdo , sck and scsa lines will lose their spi function and the s pia operating current will be reduced to a minimum value. when the bit i s high, the spia interface is enabled. bit 0 unimplemented, read as 0
rev. 1.10 104 ?a? 0?? ?01? rev. 1.10 105 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? spiac1 register bit 7 6 5 4 3 2 1 0 name sackpol sackeg sa?ls sacsen sawcol satrf r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 %lw a 8qlpsohphqwhg uhdgdv %lw sackpol: hwhuplhvwkhedvhfrglwlrriwkhforfnolh 6 olhzlooehklkzkhwkhforfnlvldfwlh 6 olhzlooehorzzkhwkhforfnlvldfwlh 7kh632/ elwghwhuplhvwkhedvhfrglwlrriwkhforfnolhliwkhelwlvklk wkhwkh6 olhzlooehorzzkhwkhforfnlvldfwlh :khwkh632/ elwlv orz wkhwkh6 olhzlooehklkzkhwkhforfnlvldfwlh lw sackeg: hwhuplhvwkh63, 6 dfwlhforfnhghwsh 632/ 6 kdvklkedvhohhozlwkgdwdfdswxuhr6 ulvlhgh 6 kdvklkedvhohhozlwkgdwdfdswxuhr6 idoolhgh 632/ 6 kdvorzedvhohhozlwkgdwdfdswxuhr6 idoolhgh 6 kdvorzedvhohhozlwkgdwdfdswxuhr6 ulvlhgh 7kh6dg632/ elwvduhxvhgwrvhwxswkhzdwkdwwkhforfnvldo rxwsxwvdglsxwvgdwdrwkh63, exv 7khvhwzrelwvpxvwehfrxuhgehiruhd gdwdwudvihulvhhfxwhgrwkhuzlvhdhuurhrxvforfnhghpdehhhudwhg 7kh 632/ elwghwhuplhvwkhedvhfrglwlrriwkhforfnolhliwkhelwlvklkwkh wkh6 olhzlooehorzzkhwkhforfnlvldfwlh :khwkh632/ elwlv orz wkhwkh6 olhzlooehklkzkhwkhforfnlvldfwlh 7kh6elw ghwhuplhv dfwlh forfn hgh wsh zklfk ghshgvxsr wkh frglwlrri wkh 632/ elw lw samls: gdwdvkliwrughu wkh/6rigdwdlvwudvplwwhguvw wkh06rigdwdlvwudvplwwhguvw 7klvlvwkhgdwdvkliwvhohfwelwdglvxvhgwrvhohfwkrzwkhgdwdlvwudvihuuhghlwkhu 06ru/6uvw6hwwlwkhelwklkzloovhohfw06uvwdgorziru/6uvw lw sacsen: 63, vhohfwvldo 66 hdeohrwuro lvdeoh deoh 7kh661elwlvxvhgdvdhdeohglvdeohiruwkh 66 sawcol 63, :ulwh roolvlrd roolvlriuhh roolvlrghw hfwhg 7kh 6:2/ dlvxvhgwrghwhfwlidgdwdfroolvlrkdvrffxuuhg,iwklvelwlvklk lwphdvwkdwgdwdkdvehhdwwhpswhgwrehzulwwhwrwkh63,uhlvwhugxuldgdwd wudvihurshudwlr 7klvzulwlrshudwlrzlooehlruhgligdwdlvehlwudvihuuhg 7khelwfdehfohduhgewkhdssolfdwlrsurudp1rwhwkdwwkh 6:2/ ixfwlr fdehhdeohgruglvdeohlddfrxudwlrrswlr lw satrf1: 63, 7udvplw5hfhlh rpsohwhd dwdlvehlwudvihuuhg 63, gdwdwudvplvvlrlvfrpsohwhg
rev. 1.10 106 ?a? 0?? ?01? rev. 1.10 107 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu the satrf bit is the transmit/receive complete fag and is set to1 automatically when an spia data transmission is completed, but must cleared to 0 by the application program. it can be used to generate an interrupt. spia communication after the spia interface is enabled by setting the spiaen bit high, then in the master mode, when data is written to the spiad register, transmission/reception will begin simultaneously. when the data transfer is complete, the satrf fag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the spiad register will be transmitted and any data on the sdia pin will be shifted into the spiad registers the master should output a scsa signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scsa signal depending upon the configurations of the sackpol bit and sackeg bit. the accompanying timing diagram shows the relationship between the slave data and scsa signal for various confgurations of the sackpol and sackeg bits. the spia will continue to function even in the idle mode. spia master mode
?
?? ?? ?? ? -? ? ?? - ?? ? ? ? ? ? ?? ?? ?? ? -? ? ?? - ?? ? ? ? ? ? ?
? spia slave mode (sackeg=0)

? ? ? ??? ? ? - ? ?
rev. 1.10 106 ?a? 0?? ?01? rev. 1.10 107 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu spia slave mode (sackeg=1)

??? ? ? ? ? ? ? ?? ?? ? - ? ? ? - ? ?? ?? ? ? ? ? - ? ? ?? ? ? ? ? ?? ? ? ??? ? ?? ? ? ? ? ? ? ?? spia master/slave modetiming diagram a write data into spiad clear sawcol sawcol=1? transmission completed ? satrf=1?) read data from spiad clear satrf transfer finished? end y n n y y n master or slave? spia transfer saspi[2:0 ]=000,001, 010,011 or 100 saspi[2:0]=101 configure sackpol, sackeg, sacsen and samls spiaen=1 a master slave spia transfer control flowchart
rev. 1.10 108 ?a? 0?? ?01? rev. 1.10 109 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu spia bus enable/disable to enable the spia bus, set sacsen = 1 and scsa=0, then wait for data to be written into the spiad (txrx buffer) register. for the master mode, after data has been written to the spiad (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred the satrf bit should be set. for the slave mode, when clock pulses are received on scka, data in the txrx buffer will be shifted out or data on sdia will be shifted in. to disable the spia bus scka, sdia, sdoa, scsa will become i/o pins or the other functions. spia operation all communication is carried out using the 4-line interface for either master or slave mode. the sacsen bit in the spiac1 register controls the overall function of the spia interface. setting this bit high will enable the spia interface by allowing the scsa line to be active, which can then be used to control the spia interface. if the sacsen bit is low, the spia interface will be disabled and the scsa line will be an i/o pin or other functions and can therefore not be used for control of the spia interface. if the sacsen bit and the spiaen bit in the spiac0 register are set high, this will place the sdia line in a foating condition and the sdoa line high. if in master mode the scka line will be either high or low depending upon the clock polarity selection bit sackpolb in the spiac1 register. if in slave mode the scka line will be in a foating condition. if spiaen is low then the bus will be disabled and scsa , sdia, sdoa and scka will all become i/o pins or other functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the spiad register. in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode: master mode ? step 1 select the clock source and master mode using the saspi2~saspi0 bits in the spiac0 control register ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb frst, this must be same as the slave device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buffer. then use the scka and scsa lines to output the data. after this go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt.
rev. 1.10 108 ?a? 0?? ?01? rev. 1.10 109 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4. slave mode ? step 1 select the spi slave mode using the saspi2~saspi0 bits in the spiac0 control register ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb frst, this setting must be the same with the master device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register, which will actually place the data into the txrx buffer. then wait for the master clock scka and scsa signal. after this, go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buffer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sawcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4. error detection the sawcol bit in the spiac register is provided to indicate errors during data transfer. the bit is set by the spia serial interface but must be cleared by the application program. this bit indicates a data collision has occurred which happens if a write to the spiad register takes place during a data transfer operation and will prevent the write operation from continuing. the sawcol and sacsen functions can be disabled or enabled by confguration options.
rev. 1.10 110 ?a? 0?? ?01? rev. 1.10 111 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enables the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. lvd register the low voltage detector is controlled using a single register, lvdc, and confguration options. the voltage threshold level to be detected is determined using a configuration option, therefore cannot be modifed by the application program. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. ? lvdc register bit 7 6 5 4 3 2 1 0 name lvdc lvden r/w r r/w por 0 0 bit 7~6 unimple mented, read as "0" bit 5 lvdo : lvd output flag 0: no low voltage detect 1: low voltage detect bit 4 lvden : low voltage detector control 0: disable 1: enable bit 3~0: unimplemented, read as "0" lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level voltage level setup using a confguration option. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of vlvd, there may be multiple bit lvdo transitions. lvd operation
rev. 1.10 110 ?a? 0?? ?01? rev. 1.10 111 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu confguration options confguration options refer to certain options within the mcu that are programmed into the otp program memory device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they can not be changed later by the application software. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed s?stem oscillator selection - f h : 1. hxt ?. erc 3. hirc ? low speed s?stem oscillator selection - f l : 1. lxt ?. lirc 3 wdt clock selection - f s : 1. lxt ?. lirc 3. f sys /4 4 hirc frequenc? selection: 1. 4?hz ?. 8?hz 3. 1??hz reset pin options 5 pa7/ res pin options: 1. res pin ?. i/o pin watchdog options 6 watchdog timer function: 1. enable ?. disable 7 clrwdt instructions selection: 1. 1 instructions ?. ? instructions lvr options 8 lvr function: 1. enable ?. disable 9 lvr/lvd voltage selection: 1. ?.1v/?.?v ?. 3.15v/3.3v 3. 4.?v/4.4v sim/spia options 10 si? function: 1. enable ?. disable 11 spi/spia - wcol/sawcol bits: 1. enable ?. disable 1? spi/spia - csen/sacsen bits: 1. enable ?. disable 13 i ? c debounce time selection: 1. no debounce ?. ? s?stem clock debounce 3. 4 s?stem clock debounce
rev. 1.10 11 ? ?a? 0?? ?01? rev. 1.10 113 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu no. options 14 spia function: 1. enable ?. disable dac options 15 dac function: 1. dac ?. i/o application circuit

? ? note: "*" it is recommended that this component is added for esd protection. "**" it is recommended that this component is added in environments where power line noise is signifcant.
rev. 1.10 11 ? ?a? 0?? ?01? rev. 1.10 113 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.10 114 ?a? 0?? ?01? rev. 1.10 115 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.10 114 ?a? 0?? ?01? rev. 1.10 115 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a?[m] add? a?[m] add a?x adc a?[m] adc? a?[m] sub a?x sub a?[m] sub? a?[m] sbc a?[m] sbc? a?[m] daa [m] add data ?emor? to acc add acc to data ?emor? add immediate data to acc add data ?emor? to acc with carr? add acc to data memor ? with carr? subtract immediate data from the acc subtract data ?emor? from acc subtract data ?emor? from acc with result in data ?emor? subtract data ?emor? from acc with carr? subtract data ?emor? from acc with carr ?? result in data ?emor? decimal adjust acc for addition with result in data ?emor? 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z? c? ac? ov z? c? ac? ov z? c? ac? ov z? c? ac? ov z? c? ac? ov z? c? ac? ov z? c? ac? ov z? c? ac? ov z? c? ac? ov z? c? ac? ov c logic operation and a?[m] or a?[m] xor a?[m] and? a?[m] or? a?[m] xor? a?[m] and a?x or a?x xor a?x cpl [m] cpla [m] logical and data ?emor? to acc logical or data ?emor? to acc logical xor data ?emor? to acc logical and acc to data ?emor? logical or acc to data ?emor? logical xor acc to data ?emor? logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data ?emor? complement data ?emor? with result in acc 1 1 1 1 note 1note 1note 1 1 1 1note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data ?emor? with result in acc increment data ?emor? decrement data ?emor? with result in acc decrement data ?emor? 1 1 note 1 1note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data ?emor? right with result in acc rotate data ?emor? right rotate data ?emor? right through carr? with result in acc rotate data ?emor? right through carr? rotate data ?emor? left with result in acc rotate data ?emor? left rotate data ?emor? left through carr? with result in acc rotate data ?emor? left through carr? 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move ? ov a?[m] ?ov [m]?a ? ov a?x ?ove data ?emor? to acc ? ove acc to data ?emor? ? ove immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data ?emor? set bit of data ?emor? 1 note 1 note none none
rev. 1.10 116 ?a? 0?? ?01? rev. 1.10 117 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu mnemonic description cycles flag affected branch j? p addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a ?x reti jump unconditionall? skip if data ?emor? is zero skip if data ?emor? is zero with data movement to acc skip if bit i of data ?emor? is zero skip if bit i of data ?emor? is not zero skip if increment data ?emor? is zero skip if decrement data ?emor? is zero skip if increment data ?emor? is zero with result in acc skip if decrement data ?emor? is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt ? 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note ? ? ? ? none none none none none none none none none none none none none table read tabrd [m] tabrdl [m] read table (current page) to tblh and data ?emor? read table (last page) to tblh and data ?emor? ? note ? note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt? swap [m] swapa [m] halt no operation clear data ?emor? set data ?emor? clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data ?emor? swap nibbles of data ?emor? with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to ? pdf to ? pdf to ? pdf none none to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf fags may be affected by the execution status. the to and pdf fags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.10 116 ?a? 0?? ?01? rev. 1.10 117 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.10 118 ?a? 0?? ?01? rev. 1.10 119 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternately with clr wdt2 to have effect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternately with clr wdt1 to have effect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z
rev. 1.10 118 ?a? 0?? ?01? rev. 1.10 119 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.10 1?0 ?a? 0?? ?01? rev. 1.10 1?1 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none
rev. 1.10 1?0 ?a? 0?? ?01? rev. 1.10 1?1 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected fag(s) none rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected fag(s) none
rev. 1.10 1?? ?a? 0?? ?01? rev. 1.10 1?3 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu rra [m] rotate data memory right with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected fag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m] = 0 affected fag(s) none
rev. 1.10 1?? ?a? 0?? ?01? rev. 1.10 1?3 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc = 0 affected fag(s) none set [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m] = 0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc = 0 affected fag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c
rev. 1.10 1?4 ?a? 0?? ?01? rev. 1.10 1?5 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7 ~ [m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m] = 0 affected fag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected fag(s) none
rev. 1.10 1?4 ?a? 0?? ?01? rev. 1.10 1?5 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu tabrd [m] read table to tblh and data memory description the low byte of the program code addressed by the table pointer (tblp/tbhp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp/tbhp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.10 1?6 ?a? 0?? ?01? rev. 1.10 1?7 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 1.375 D 1.395 b 0.?78 D 0.?98 c 0.1?5 D 0.135 d 0.1?5 D 0.145 e 0.016 D 0.0?0 f 0.050 D 0.070 g D 0.100 D h 0.?95 D 0.315 i D 0.375 D symbol dimensions in mm min. nom. max. a 34.93 D 35.43 b 7.06 D 7.57 c 3.18 D 3.43 d 3.18 D 3.68 e 0.41 D 0.51 f 1.?7 D 1.78 g D ?.54 D h 7.49 D 8.00 i D 9.53 D
rev. 1.10 1?6 ?a? 0?? ?01? rev. 1.10 1?7 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu 28-pin sop (300mil) outline dimensions ? ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0.?56 D 0.300 c 0.01? D 0.0?0 c 0.697 D 0.713 d D D 0.104 e D 0.050 D f 0.004 D 0.01? g 0.016 D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10.64 b 6.50 D 7.6? c 0.30 D 0.51 c 17.70 D 18.11 d D D ?.64 e D 1.?7 D f 0.10 D 0.30 g 0.41 D 1.?7 h 0.?0 D 0.33 0 D 8
rev. 1.10 1?8 ?a? 0?? ?01? rev. 1.10 1?9 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.??8 D 0.?44 b 0.150 D 0.157 c 0.008 D 0.01? c 0.386 D 0.394 d 0.054 D 0.060 e D 0.0?5 D f 0.004 D 0.010 g 0.0?? D 0.0?8 h 0.007 D 0.010 0 D 8 symbol dimensions in mm min. nom. max. a 5.79 D 6.?0 b 3.81 D 3.99 c 0.?0 D 0.30 c 9.80 D 10.01 d 1.37 D 1.5? e D 0.64 D f 0.10 D 0.?5 g 0.56 D 0.71 h 0.18 D 0.?5 0 D 8
rev. 1.10 1?8 ?a? 0?? ?01? rev. 1.10 1?9 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu 44-pin qfp (10mmx10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.51? D 0.5?8 b 0.390 D 0.398 c 0.51? D 0.5?8 d 0.390 D 0.398 e D 0.031 D f D 0.01? D g 0.075 D 0.087 h D D 0.106 i 0.010 D 0.0?0 j 0.0?9 D 0.037 k 0.004 D 0.008 l D 0.004 D 0 D 7 symbol dimensions in mm min. nom. max. a 13.00 D 13.40 b 9.90 D 10.10 c 13.00 D 13.40 d 9.90 D 10.10 e D 0.80 D f D 0.30 D g 1.90 D ?.?0 h D D ?.70 i 0.?5 D 0.50 j 0.73 D 0.93 k 0.10 D 0.?0 l D 0.10 D 0 D 7
rev. 1.10 130 ?a? 0?? ?01? rev. 1.10 131 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu 52-pin qfp (14mmx14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.681 D 0.689 b 0.547 D 0.555 c 0.681 D 0.689 d 0.547 D 0.555 e D 0.039 D f D 0.016 D g 0.098 D 0.1?? h D D 0.134 i D 0.004 D j 0.0?9 D 0.041 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 17.30 D 17.50 b 13.90 D 14.10 c 17.30 D 17.50 d 13.90 D 14.10 e D 1.00 D f D 0.40 D g ?.50 D 3.10 h D D 3.40 i D 0.10 D j 0.73 D 1.03 k 0.10 D 0.?0 0 D 7
rev. 1.10 130 ?a? 0?? ?01? rev. 1.10 131 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu 64-pin lqfp (7mmx7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.?7? D 0.?80 c 0.350 D 0.358 d 0.?7? D 0.?80 e D 0.016 D f 0.005 D 0.009 g 0.053 D 0.057 h D D 0.063 i 0.00? D 0.006 j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.13 D 0.?3 g 1.35 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.?0 0 D 7
rev. 1.10 13? ?a? 0?? ?01? rev. 1.10 133 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu reel dimensions product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 package information 2 april 1, 2010 ? sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.? d ke? slit width ?.00.5 t1 space between flange ?4.8 +0.3/-0.? t? reel thickness 30.?0.? ? ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.? d ke? slit width ?.00.5 t1 space between flange 16.8 +0.3/-0.? t? reel thickness ??.?0.?
rev. 1.10 13? ?a? 0?? ?01? rev. 1.10 133 ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu carrier tape dimensions carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 package information 3 april 1, 2010

? sop 28w (300mil) symbol description dimensions in mm w carrier tape width ?4.00.3 p cavit? pitch 1?.00.1 e perforation position 1.750.10 f cavit? to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavit? hole diameter 1.50 +0.?5/-0.00 p0 perforation pitch 4.00.1 p1 cavit? to perforation (length direction) ?.00.1 a0 cavit? length 10.850.10 b0 cavit? width 18.340.10 k0 cavit? depth ?.970.10 t carrier tape thickness 0.350.01 c cover tape width ?1.30.1 ? ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavit? pitch 8.00.1 e perforation position 1.750.1 f cavit? to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavit? hole diameter 1.50 +0.?5/-0.00 p0 perforation pitch 4.00.1 p1 cavit? to perforation (length direction) ?.00.1 a0 cavit? length 6.50.1 b0 cavit? width 10.30.1 k0 cavit? depth ?.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1
rev. 1.10 134 ?a? 0?? ?01? rev. 1.10 pb ?a? 0?? ?01? ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu ht46r068b/ht46r069b enhanced a/d type 8-bit otp mcu holtek semiconductor inc. (headquarters) no.3? creation rd. ii? science park? hsinchu? taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-?? no. 3-?? yuanqu st.? nankang software park? taipei 115? taiwan tel: 886- ?-?655-7070 fax: 886-?-?655-7373 fax: 886-?-?655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit a? productivit? building? no.5 gaoxin ? ?nd road? nanshan district? shenzhen? china 518057 tel: 86-755-8616-9908 ? 86-755-8616-9308 fax: 86-755-8616-97?? holtek semiconductor (usa), inc. (north america sales offce) 467?9 fremont blvd.? fremont? ca 94538? usa tel: 1-510- ?5?-9880 fax: 1-510-?5?-9885 http://www.holtek.com cop?right ? ?01? b? holtek se? iconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however ? holtek assumes no responsibilit ? arising from the use of the specifications described. the applications mentioned herein are used solel? for the purpose of illustration and holtek makes no warrant ? or representation that such applications will be suitable without further modification ? nor recommends the use of its products for application that ma ? present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information? please visit our web site at http://www.holtek.com.tw.

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