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vishay siliconix dg611, dg612, dg613 document number: 70057 s11-0154-rev. i, 31-jan-11 www.vishay.com 1 high-speed, low-glitch d/cmos analog switches features ? fast switching - t on : 12 ns ? low charge injection: 2 pc ? wide bandwidth: 500 mhz ? 5 v cmos logic compatible ? low r ds(on) : 18 ? ? low quiescent power : 1.2 nw ? single supply operation benefits ? improved data throughput ? minimal switching transients ? improved system performance ? easily interfaced ? low insertion loss ? minimal power consumption applications ? fast sample-and-holds ? synchronous demodulators ? pixel-rate video switching ? disk/tape drives ? dac deglitching ? switched capacitor filters ? gaas fet drivers ? satellite receivers description the dg611, dg612, dg613 feature high-speed low- capacitance lateral dmos switches. charge injection has been minimized to optimize performance in fast sample-and- hold applications. each switch conducts equally well in both directions when on and blocks up to 16 v p-p when off. capacitances have been minimized to ensure fast switching and low-glitch energy. to achieve such fast and clean switching performance, the dg611, dg612, dg613 are built on the vishay siliconix proprietary d/cmos proce ss. this process combines n-channel dmos switching fets with low-power cmos control logic and drivers. an epitaxial layer prevents latchup. the dg611 and dg612 differ only in that they respond to opposite logic levels. the versatile dg613 has two normally open and two normally closed switches. it can be given various configurations, includ ing four spst, two spdt, one dpdt. for additional information see applications note an207. functional block diagram and pin configuration four spst switches per package logic ?0? ? 1 v logic ?1? ?? 4 v * pb containing terminations are not rohs compliant, exemptions may apply 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view in 1 in 2 d 1 d 2 s 1 s 2 v- v+ gnd v l s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic dg611 top view s 1 s 2 v- v+ nc nc gnd v l s 4 s 3 lcc nc in 3 d 3 d 4 in 4 nc in 2 d 2 d 1 in 1 key 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 dg611 truth table logic dg611 dg612 0 on off 1offon
www.vishay.com 2 document number: 70057 s11-0154-rev. i, 31-jan-11 vishay siliconix dg611, dg612, dg613 functional block diagram and pin configuration four spst switches per package in 1 in 2 d 1 d 2 s 1 s 2 v- v+ gnd v l s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view dg613 nc s 3 nc d 4 nc in 1 v l in 4 s 2 key s 4 in 3 d 1 top view d 3 v- nc lcc in 2 v+ 9 gnd 10 11 12 13 4 d 2 5 6 7 8 1 2 3 19 20 14 15 16 17 18 s 1 dg613 truth table logic sw 1 , sw 4 sw 2 , sw 3 0 off on 1onoff ordering information temp. range package part number dg611, dg612 - 40 c to 85 c 16-pin plastic dip dg611dj dg611dj-e3 dg612dj dg612dj-e3 16-pin narrow soic dg611dy dg611dy-e3 dg611dy-t1 dg611dy-t1-e3 dg612dy dg612dy-e3 dg612dy-t1 dg612dy-t1-e3 dg613 - 40 c to 85 c 16-pin plastic dip dg613dj dg613dj-e3 16-pin narrow soic dg613dy dg613dy-e3 dg613dy-t1 dg613dy-t1-e3 logic ?0? ? 1 v logic ?1? ?? 4 v
document number: 70057 s11-0154-rev. i, 31-jan-11 www.vishay.com 3 vishay siliconix dg611, dg612, dg613 notes: a. signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes. limit forward di ode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/c above 75 c. d. derate 7.6 mw/c above 75 c. e. derate 12 mw/c above 75 c. absolute maximum ratings parameter limit unit v+ to v- - 0.3 to 21 v v+ to gnd - 0.3 to 21 v- to gnd - 19 to 0.3 v l to gnd - 1 to (v+) + 1 or 20 ma, whichever occurs first v in a (v-) - 1 to (v+) + 1 or 20 ma, whichever occurs first v s , v d a (v-) - 0.3 to (v+) + 16 or 20 ma, whichever occurs first continuous current (any terminal) 30 ma current, s or d (pulsed at 1 s, 10 % duty cycle) 100 storage temperature cerdip - 65 to 150 c plastic - 65 to 125 power dissipation (package) b 16-pin plastic dip c 470 mw 16-pin narrow soic d 600 16-pin cerdip e 900 20-pin lcc e 900 recommended operating range parameter limit unit v+ 5 to 21 v v- - 10 to 0 v l 4 to v+ v in 0 to v l v analog v- to (v+) - 5
www.vishay.com 4 document number: 70057 s11-0154-rev. i, 31-jan-11 vishay siliconix dg611, dg612, dg613 specifications a parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 3 v v l = 5 v, v in = 4 v, 1 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog v- = - 5 v, v+ = 12 v full - 5 7 - 5 7 v switch on-resistance r ds(on) i s = - 1 ma, v d = 0 v room full 18 45 60 45 60 ? resistance match bet ch. ? r ds(on) room 2 source off leakage i s(off) v s = 0 v, v d = 10 v room hot 0.001 - 0.25 - 20 0.25 20 - 0.25 - 20 0.25 20 na drain off leakage current i d(off) v s = 10 v, v d = 0 v room hot 0.001 - 0.25 - 20 0.25 20 - 0.25 - 20 0.25 20 switch on leakage current i d(on) v s = v d = 0 v room hot 0.001 - 0.4 - 40 0.4 40 - 0.4 - 40 0.4 40 digital control input voltage high v ih full 4 4 v input voltage low v il full 1 1 input current i in room hot 0.005 - 1 - 20 1 20 - 1 - 20 1 20 a input capacitance c in room 5 pf dynamic characteristics off state input capacitance c s(off) v s = 0 v room 3 pf off state output capacitance c d(off) v d = 0 v room 2 on state input capacitance c s(on) v s = v d = 0 v room 10 bandwidth bw r l = 50 ?? room 500 mhz tu r n - o n t i m e e t on r l = 300 ??? c l = 3 pf v s = 2 v, see test circuit, figure 2 room 12 25 25 ns tu r n - o f f t i m e e t off room 8 20 20 tu r n - o n t i m e t on r l = 300 ??? c l = 75 pf v s = 2 v, see test circuit, figure 2 room full 19 35 50 35 50 tu r n - o f f t i m e t off room full 16 25 35 25 35 charge injection e qc l = 1 nf, v s = 0 v room 4 pc ch. injection change e,g ? qc l = 1 nf, | v s | ? 3 v room 3 4 4 off isolation e oirr r in = 50 ??? r l = 50 ? f = 5 mhz room 74 db crosstalk e x ta l k r in = 10 ? , r l = 50 ? f = 5 mhz room 87 power supplies positive supply current i+ v in = 0 v or 5 v room full 0.005 1 5 1 5 a negative supply current i- room full - 0.005 - 1 - 5 - 1 - 5 logic supply current i l room full 0.005 1 5 1 5 ground current i gnd room full - 0.005 - 1 - 5 - 1 - 5
document number: 70057 s11-0154-rev. i, 31-jan-11 www.vishay.com 5 vishay siliconix dg611, dg612, dg613 notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, no t guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. ? q = | q at v s = 3 v - q at v s = - 3 v | . stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. typical characteristics (25 c, unless otherwise noted) specifications for unipolar supplies a parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 3 v v l = 5 v, v in = 4 v, 1 v f temp. b ty.p c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0 7 0 7 v switch on-resistance r ds(on) i s = - 1 ma, v d = 1 v room 25 60 60 ? dynamic characteristics tu r n - o n t i m e e t on r l = 300 ??? c l = 3 pf v s = 2 v, see test circuit, figure 2 room 15 30 30 ns turn-off time e t off room 10 25 25 r ds(on) vs. v d and power supply voltages r ds(on) - drain-source on-resistance ( ? ) - 4 - 2 0 2 4 6 8 10 12 - 5 400 350 300 250 200 150 100 50 0 v d - drain voltage (v) v+ = 5 v v- = - 5 v v+ = 12 v v- = - 5 v v+ = 15 v v- = - 3 v i s = - 1 ma leakage current vs. analog voltage - 4 - 2 0 2 4 6 8 1 0 3 2 1 0 - 1 - 2 - 3 - leakage current (pa) , i d v d or v s - drain or source voltage (v) i s(of f), i d(of f) i d(on) v+ = 15 v v- = - 3 v i s
www.vishay.com 6 document number: 70057 s11-0154-rev. i, 31-jan-11 vishay siliconix dg611, dg612, dg613 typical characteristics (25 c, unless otherwise noted) input switching threshold vs. v l r ds(on) vs. v d and temperature leakage currents vs. temperature 0 5 10 15 6 5 4 3 2 1 0 v l - logic supply voltage (v) v+ = 15 v v- = - 3 v v th - logic input voltage (v) r ds(on) - drain-source on-resistance ( ? ) - 4 - 2 02468 1 0 12 400 350 300 250 200 150 100 50 0 v d - drain voltage (v) 25 c v+ = 15 v v- = - 3 v i s = - 1 ma 125 c - 55 c - 55 0 125 temperature (c) - 25 25 50 75 100 10 na 0.1 pa 100 pa 10 pa 1 pa i s(of f), i d(of f) i d(on) 1 na - leakage (a) i , i s(off) d(off) switching times vs. temperature charge injection vs. analog voltage - 3 db bandwidth/insertion loss vs. frequency 16 14 12 10 8 6 4 2 0 24 22 20 18 - 55 - 35 - 15 5 25 45 65 85 105 125 v+ = 15 v v- = - 3 v r l = 300 ? c l = 10 pf t on t off time (ns) temperature (c) charge (pc) v analo g - analog voltage (v) 20 10 0 - 10 - 20 - 3 - 2 - 1 0123 456 789 1 0 qd qs v+ = 15 v v- = - 3 v insertion loss (db) 1 1 0 100 1000 - 24 - 20 - 16 - 12 - 8 - 4 0 f - frequency (mhz) r l = 50 ? - 3 db point
document number: 70057 s11-0154-rev. i, 31-jan-11 www.vishay.com 7 vishay siliconix dg611, dg612, dg613 typical characteristics (25 c, unless otherwise noted) schematic diagram (typical channel) test circuits crosstalk and off isolation vs. frequency 1 1 0 100 - 20 - 40 - 60 - 80 - 100 - 120 f - frequency (mhz) v+ = 15 v v- = - 3 v (db) crosstalk of f isolation supply currents vs. switching frequency supply current (ma) 6 5 4 3 2 1 0 - 1 - 2 - 3 - 4 - 5 1k 100k 100k 1m 10m v+ = 15 v v- = - 3 v v l = 5 v c x = 0, 5 v f - frequency (hz) i+ i l i- figure 1. v l v+ v- s d dmos switch level translator input logic in x driver figure 2. switching time c l (includes fixture and stray capacitance) v l r l r l + r ds(on) v o = v s v o 2 v v+ v- in v- s gnd r l 300 ? d c l + 15 v + 5 v 50 % 20 % 90 % t on t off logic input 0 v 5 v v s = 2 v 0 v switch output t r < 10 ns t f < 10 ns
www.vishay.com 8 document number: 70057 s11-0154-rev. i, 31-jan-11 vishay siliconix dg611, dg612, dg613 test circuits applications high-speed sample-and-hold in a fast sample-and-hold application, the analog switch characteristics are critical. a fast switch reduces aperture uncertainty. a low charge inject ion eliminates offset (step) errors. a low leakage reduces droop errors. the clc111, a fast input buffer, helps to shorten acquisition and settling times. a low leakage, low dielectric absorption hold capacitor must be used. polycarbonate, polystyrene and polypropylene are good choices. the jfet output buffer reduces droop due to its low input bias current. (see figure 5.) pixel-rate switch windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the dg613. for this application the two video sources must be sync locked. the glitch -less analog switch eliminates halos. (see figure 6.) gaas fet drivers figure 7 illustrates a high-speed gaas fet driver. to turn the gaas fet on 0 v are applied to its gate via s 1 , whereas to turn it off, - 8 v are applied via s 2 . this high-speed, low-power driver is especially suited for applications that require a large number of rf switches, such as phased array radars. figure 3. charge injection c l 1 nf d r g v o v+ s v- 5 v in v l v g - 3 v gnd + 15 v + 5 v figure 4. crosstalk s 1 d 2 s 2 v s 1 v, 4 v v o in 2 r g = 50 ? 1 v, 4 v x ta l k isolation = 20 log v s v l v o v+ in 1 50 ? c = rf bypass r l d 1 - 3 v gnd v- nc c + 15 v c + 5 v c figure 5. high-speed sample-and-hold clc111 75 ? + - lf356 1 / 4 dg611 5 v control analog input input buffer s in d output buffer 5 v output to a/d + 5 v + 12 v - 5 v c hold 650 pf polystyrene
document number: 70057 s11-0154-rev. i, 31-jan-11 www.vishay.com 9 vishay siliconix dg611, dg612, dg613 applications vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70057 . figure 6. a pixel-rate switch creates title overlays + - clc410 75 ? 1 / 2 dg613 background d output buffer composite output + 5 v + 12 v - 5 v 75 ? titles 5 v control 75 ? 250 ? 1 / 2 clc114 250 ? figure 7. a high-speed gaas fet driver that saves power 1 / 2 dg613 d 1 + 5 v - 8 v d 2 s 1 s 2 in 1 in 2 gnd v- gaas rf in rf out v l v+ 5 v
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 71194 02-jul-01 www.vishay.com 1
jedec part number: ms-012 dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-03946?rev. f, 09-jul-01 dwg: 5300
e 1 e q 1 a l a 1 e 1 b b 1 s c e a d 15 max 12345678 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71261 06-jul-01 www.vishay.com 1

dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 18.93 21.33 0.745 0.840 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 0.38 1.52 .015 0.060 ecn: s-03946?rev. d, 09-jul-01 dwg: 5482
e 1 e q 1 a l a 1 e 1 b b 1 l 1 s c e a d 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 package information vishay siliconix document number: 71282 03-jul-01 www.vishay.com 1
dim min max min max a 4.06 5.08 0.160 0.200 a 1 0.51 1.14 0.020 0.045 b 0.38 0.51 0.015 0.020 b 1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d 19.05 19.56 0.750 0.770 e 7.62 8.26 0.300 0.325 e 1 6.60 7.62 0.260 0.300 e 1 2.54 bsc 0.100 bsc e a 7.62 bsc 0.300 bsc l 3.18 3.81 0.125 0.150 l 1 3.81 5.08 0.150 0.200 q 1 1.27 2.16 0.050 0.085 s 0.38 1.14 0.015 0.045 0 15 0 15 ecn: s-03946?rev. g, 09-jul-01 dwg: 5403
d l 1 e b l e a 1 a 28 1 2 packaging information vishay siliconix document number: 71290 02-jul-01 www.vishay.com 1

dim min max min max 1.37 2.24 0.054 0.088 1.63 2.54 0.064 0.100 0.56 0.71 0.022 0.028 8.69 9.09 0.342 0.358 8.69 9.09 0.442 0.358 1.27 bsc 0.050 bsc 1.14 1.40 0.045 0.055 1.96 2.36 0.077 0.093 ecn: s-03946?rev. b, 09-jul-01 dwg: 5321
application note 826 vishay siliconix www.vishay.com document number: 72608 24 revision: 21-jan-08 application note recommended minimum pads for so-16 recommended minimum pads for so-16 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) 0.372 (9.449) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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