june 2011 ? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs nc7wz14 tinylogic ? uhs dual inverter with schmitt trigger inputs features ? ultra-high speed: t pd 3.2ns (typical) into 50pf at 5v v cc ? high output drive: 24ma at 3v v cc ? broad v cc operating range: 1.65v to 5.5v ? matches performance of lcx when operated at 3.3v v cc ? power down high impedance inputs/outputs ? over-voltage tolerance input s facilitate 5v to 3v translation ? proprietary noise/emi reduction circuitry ? ultra-small micropak? packages ? space-saving sc70 package description the nc7wz14 is a dual inverter with schmitt trigger input from fairchild's ultra-high speed (uhs) series of tinylogic. the device is f abricated with advanced cmos technology to achieve ultra-high speed with high output drive while maintaining low st atic power dissipation over a very broad v cc operating range. the devic e is specified to operate over the 1. 65v to 5.5v v cc range. the inputs and outputs are high-impedance when v cc is 0v. inputs tolerate voltages up to 7v independent of v cc operating voltage. schmitt trigger inputs achieve typically 1v hysteresis between the pos itive-and negative-going input threshold voltage at 5v. ordering information part number operating temperature top mark package packing method nc7wz14p6x -40 to +85c z14 6-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel nc7wz14ep6x -40 to +125c z14 6-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel nc7wz14l6x -40 to +85c a9 6-lead micropak?, 1.00mm wide 5000 units on tape & reel nc7wz14fhx -40 to +85c a9 6-lead, mi cropak2, 1x1mm body, .35mm pitch 5000 units on tape & reel
? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 2 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs connection diagrams ieec/iec figure 1. logic symbol pin configurations 1 a 1 2 gnd 3 6 5 4 a 2 y 1 v c c y 2 figure 2. sc70 (top view) figure 3. micropak (top through view) aaa pi n on e notes: 1. aaa represents product code top mark ( see ordering code). 2. orientation of top mark dete rmines pin one location. read the top product code mark left to right. pin one is the lower left pin. figure 4. sc70 pin 1 orientation pin definitions pin # sc70 pin # micropak name description 1 1 a 1 input 2 2 gnd ground 3 3 a 2 input 4 4 y 2 output 5 5 v cc supply voltage 6 6 y 1 output function table y= /a inputs output a y l h h l h = high logic level l = low logic level
? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 3 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 7.0 v v in dc input voltage -0.5 7.0 v v out dc output voltage -0.5 7.0 v i ik dc input diode current v in < -0.5v -50 ma i ok dc output diode current v out < -0.5v -50 ma i out dc output current 100 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature (sol dering, 10 seconds) +260 c p d power dissipation sc70-6 t a =85c 170 mw t a =125c 104 micropak-6 130 micropak2-6 120 esd human body model, jedec:jesd22-a114 4000 v charge device model, jedec:jesd22-c101 2000 recommended operating conditions (3) the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage oper ating 1.65 5.50 v supply voltage data re tention 1.5 5.5 v in input voltage 0 5.5 v v out output voltage 0 v cc v t a operating temperature sc70-6 -40 +125 c micropak-6 -40 +85 micropak2-6 -40 +85 ? ja thermal resistance sc70-6 390 c/w micropak-6 500 micropak2-6 560 note: 3. unused inputs must be held high or low. they may not float.
? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 4 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs dc electrical characteristics symbol parameter v cc (v) conditions t a =+25c t a =-40 to +85c t a =-40 to +125c units min. typ. max. min. max. min. max. v p positive threshold voltage 1.65 0.60 1.40 0.60 1.40 0.60 1.40 v 1.80 0.70 1.50 0.70 1.50 0.70 1.50 2.30 1.00 1.80 1.00 1.80 1.00 1.80 3.00 1.30 2.20 1.30 2.20 1.30 2.20 4.50 1.90 3.10 1.90 3.10 2.00 3.20 5.50 2.20 3.60 2.20 3.60 2.30 3.70 v n negative threshold voltage 1.65 0.20 0.50 0.80 0.20 0.80 0.30 0.90 v 1.80 0.25 0.56 0.90 0.25 0.90 0.35 1.00 2.30 0.40 0.75 1.15 0.40 1.15 0.50 1.20 3.00 0.60 0.98 1.50 0.60 1.50 0.70 1.60 4.50 1.00 1.42 2.00 1.00 2.00 1.10 2.20 5.50 1.20 1.68 2.30 1.20 2.30 1.40 2.50 v h hysteresis voltage 1.65 0.10 0.48 0.90 0.10 0.90 0.10 0.90 v 1.80 0.15 0.51 1.00 0.15 1.00 0.15 1.00 2.30 0.25 0.62 1.10 0.25 1.10 0.25 1.10 3.00 0.40 0.76 1.20 0.40 1.20 0.40 1.20 4.50 0.60 1.01 1.50 0.60 1.50 0.60 1.50 5.50 0.70 1.20 1.70 0.70 1.70 0.70 1.70 v oh high level output voltage 1.65 v in =v il , i oh =-100a 1.55 1.65 1.55 1.55 v 1.80 1.70 1.80 1.70 1.70 2.30 2.20 2.30 2.20 2.20 3.00 2.90 3.00 2.90 2.90 4.50 4.40 4.50 4.40 4.40 1.65 i oh =-4ma 1.29 1.52 1.29 1.26 2.30 i oh =-8ma 1.90 2.14 1.90 1.80 3.00 i oh =-16ma 2.40 2.75 2.40 2.30 3.00 i oh =-24ma 2.30 2.62 2.30 2.20 4.50 i oh =-32ma 3.80 4.13 3.80 3.70 v ol low level output voltage 1.65 v in =v ih , i ol =100a 0.00 0.10 0.10 0.10 v 1.80 0.00 0.10 0.10 0.10 2.30 0.00 0.10 0.10 0.10 3.00 0.00 0.10 0.10 0.10 4.50 0.00 0.10 0.10 0.10 1.65 i ol =4ma 0.08 0.24 0.24 0.26 2.30 i ol =8ma 0.10 0.30 0.30 0.32 3.00 i ol =16ma 0.16 0.40 0.40 0.43 3.00 i ol =24ma 0.24 0.55 0.55 0.60 4.50 i ol =32ma 0.25 0.55 0.55 0.60 i in input leakage current 0 to 5.5 v in =5.5v, gnd 0.1 1.0 2.0 a i off power off leakage current 0 v in or v out =5.5v 1 10 20 a i cc quiescent supply current 1.65 to 5.50 v in =5.5v, gnd 1.0 10 20 a
? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 5 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs ac electrical characteristics symbol parameter v cc (v) conditions t a =+25c t a =-40 to +85c t a =-40 to +125c units figure min. typ. max. min. max. min. max. t plh , t phl propagation delay 1.65 c l =15pf, r l =1m ? 2.5 7.6 13.1 2.5 14.5 2.5 14.7 ns figure 5 figure 6 1.80 2.5 6.3 10.9 2.5 12.0 2.5 12.3 2.50 0.20 1.8 4.3 7.4 1.8 8.1 1.8 8.4 3.30 0.30 1.5 3.3 5.0 1.5 5.5 1.5 5.8 5.00 0.50 1.0 2.7 4.1 1.0 4.5 1.0 4.8 3.30 0.30 c l =50pf, r l =500 ? 1.8 4.0 6.0 1.8 6.6 1.8 6.9 figure 5 figure 6 5.00 0.50 1.2 3.2 4.9 1.2 5.4 1.2 5.7 c in input capacitance 0.00 2.5 pf c pd power dissipation capacitance (4) 3.30 11.0 pf figure 7 5.00 12.5 note: 4. c pd is defined as the value of the internal equivalent capacitance which is deriv ed from dynamic operating current consumption (i ccd ) at no output loading and operat ing at 50% duty cycle. c pd is related to i ccd dynamic operating current by the expression: i ccd =(c pd )(v cc )(f in )+(i cc static). note: 5. cl includes load and stray capacitance; input prr=1.0mhz; t w =500ns figure 5. ac test circuit figure 6. ac waveforms note: 6. input=ac waveform; t r =t f =1.8ns; prr=variable; duty cycle =50%. figure 7. i ccd test circuit
? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 6 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs physical dimensions detail a scale: 60x b 1.90 2.00 0.20 0.50 min 1.00 0.80 1.10 0.80 0.10 c 0.25 0.10 0.46 0.26 0.20 gage plane (r0.10) 30 0 seating plane c 0.10 0.00 notes: unless otherwise specified a) this package conforms to eiaj sc-88, 1996. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. d) drawing filename: mkt-maa06arev6 2.100.30 0.10 ab 0.65 1.30 (0.25) 0.30 0.15 1 1.25 0.10 3 1.30 0.40 min see detail a land pattern recommendation 6 a 4 c 0.65 l symm pin one figure 8. 6-lead, sc70, eiaj sc-88a, 1.25mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf. package designator tape section cavity number cavity status cover type status p6x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 7 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs physical dimensions 2. dimensions are in millimeters 1. conforms to jedec st andard m0-252 va riation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 9. 6-lead, micropak?, 1.0mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 8 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 65 4 0.35 (0.08) 4x side view figure 10. 6-lead, micropak2, 1x1mm body, .35mm pitch package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 1999 fairchild semiconductor corporation www.fairchildsemi.com nc7wz14 ? rev. 1.0.7 9 nc7wz14 ? tinylogic ? uhs dual inverter with schmitt trigger inputs
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