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copyright ?2008 by zilog ? , inc. all rights reserved. www.zilog.com ps022825-0908 product specification high-performance 8-b it microcontrollers z8 encore! xp ? f082a series
ps022825-0908 do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical and mechanical engineering. z8, z8 encore!, and z8 encore! xp are registered trademarks of zilog, inc. all other product or service names are the property of their respective owners. warning:
ps022825-0908 revision history z8 encore! xp ? f082a series product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, re fer to the corresponding pages and appropriate links in the table below. date revision level description page number september 2008 25 added the references to f042a series back in table 1 , available packages , table 5 , table 7 , table 13 , ordering information sections. 3 , 9 , 16 , 19 , 37 , 251 may 2008 24 changed title to z8 encore! xp f082a series and removed references to f042a series in table 1 , available packages , table 5 , table 7 , table 13 , ordering information sections. all december 2007 23 updated figure 3 , table 14 , table 58 through table 60 . 10 , 41 , and 95 july 2007 22 updated table 15 and table 128 . updated power consumption in electrical characteristics chapter. 44 , 221 june 2007 21 revision number update. all
ps022825-0908 table of contents z8 encore! xp ? f082a series product specification iv table of contents overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ez8 cpu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 low-power operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 external crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 low voltage detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . 7 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 direct led drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 non-volatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ps022825-0908 table of contents z8 encore! xp ? f082a series product specification v reset, stop mode recovery, and low voltage detection . . . . . . . . . . . . . . 23 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 voltage brownout reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 external reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 external reset indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 on-chip debugger initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 stop mode recovery using watchdog timer time-out . . . . . . . . . . . . . . . 29 stop mode recovery using a gpio port pin transition . . . . . . . . . . . . . . . 29 stop mode recovery using the external reset pin . . . . . . . . . . . . . . . . . 30 low voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 reset register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 peripheral-level power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 power control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 direct led drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 shared reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 shared debug pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 crystal oscillator override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 v tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 external clock setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 port a?d address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 port a?d control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 port a?d data direction sub-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 port a?d alternate function sub-registers . . . . . . . . . . . . . . . . . . . . . . . . 47
ps022825-0908 table of contents z8 encore! xp ? f082a series product specification vi port a?c input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 port a?d output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 led drive enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 led drive level high register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 led drive level low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 watchdog timer interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 62 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 63 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 65 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 shared interrupt select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 timer pin signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timer 0?1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 timer 0?1 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . 87 timer 0-1 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 88 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 watchdog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
ps022825-0908 table of contents z8 encore! xp ? f082a series product specification vii watchdog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 watchdog timer reload unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . 93 watchdog timer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 watchdog timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 94 watchdog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 watchdog timer reload upper, high and low byte registers . . . . . . . . . . 94 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . 97 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . 99 transmitting data using the interrupt-driven method . . . . . . . . . . . . . . . . 100 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . 101 receiving data using the interrupt-driven method . . . . . . . . . . . . . . . . . . 102 clear to send (cts) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 uart control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . 108 uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 uart status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 uart receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 uart baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . 114 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 infrared encoder/decoder control register definitions . . . . . . . . . . . . . . . . . 120 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ps022825-0908 table of contents z8 encore! xp ? f082a series product specification viii hardware overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 automatic powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 calibration and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 adc compensation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 input buffer stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 adc control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 adc control/status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 adc data low byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 low power operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 comparator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 flash operation timing using the flash frequency registers . . . . . . . . . 145 flash code protection against external access . . . . . . . . . . . . . . . . . . . . 145 flash code protection against accidental program and erasure . . . . . . . 145 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . 148 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
ps022825-0908 table of contents z8 encore! xp ? f082a series product specification ix flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . 152 flash option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 option bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 reading the flash information page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 flash option bit control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . 155 trim bit address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 trim bit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 flash option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 flash program memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . 156 flash program memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . 158 trim bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 trim bit address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 trim bit address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 trim bit address 0002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 trim bit address 0003h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 trim bit address 0004h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 zilog calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 adc calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 temperature sensor calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 watchdog timer calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 serialization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 randomized lot identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 non-volatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 nvds code interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 power failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 optimizing nvds memory usage for execution speed . . . . . . . . . . . . . . 171 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
ps022825-0908 table of contents z8 encore! xp ? f082a series product specification x ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 ocd auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 ocd unlock sequence (8-pin devices only) . . . . . . . . . . . . . . . . . . . . . . 178 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 runtime counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . . . . 184 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 oscillator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 system clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 clock failure detection and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 oscillator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 oscillator operation with an exte rnal rc network . . . . . . . . . . . . . . . . . . . . . 195 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . . . . 199 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . 229 general purpose i/o port input data sample timing . . . . . . . . . . . . . . . . 234
ps022825-0908 table of contents z8 encore! xp ? f082a series product specification xi general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . 236 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
ps022825-0908 overview z8 encore! xp ? f082a series product specification 1 overview zilog?s z8 encore! ? mcu family of products are the first in a line of zilog ? microcon- troller products based upon the 8-bit ez8 cpu. zilog?s z8 encore! xp ? f082a series products expand upon zilog?s extensive line of 8-bit microcon trollers. the flash in-circuit programming capability allows for faster de velopment time and prog ram changes in the field. the new ez8 cpu is upwa rd compatible with existing z8 ? instructions. the rich peripheral set of the z8 enco re! xp f082a series makes it suitable for a variety of appli- cations including motor contro l, security systems, home a ppliances, personal electronic devices, and sensors. features the key features of z8 encore! xp f082a series products include: ? 20 mhz ez8 cpu ? 1 kb, 2 kb, 4 kb, or 8 kb flash memory with in-circuit programming capability ? 256 b, 512 b, or 1 kb register ram ? up to 128 b non-volatile data storage (nvds) ? internal precision oscillator trimmed to 1% accuracy ? external crystal oscillator, operating up to 20 mhz ? optional 8-channel, 10-bit anal og-to-digital converter (adc) ? optional on-chip temperature sensor ? on-chip analog comparator ? optional on-chip low-power op erational amplifier (lpo) ? full-duplex uart ? the uart baud rate generator (brg) can be configured and used as a basic 16-bit timer ? infrared data association (i rda)-compliant infrared en coder/decoders, integrated with uart ? two enhanced 16-bit timers with ca pture, compare, and pwm capability ? watchdog timer (wdt) with dedicated internal rc oscillator ? up to 20 vectored interrupts ? 6 to 25 i/o pins depending upon package
ps022825-0908 overview z8 encore! xp ? f082a series product specification 2 ? up to thirteen 5 v-tolerant input pins ? up to 8 ports capable of direct led dr ive with no current limit resistor required ? on-chip debugger (ocd) ? voltage brownout (vbo) protection ? programmable low battery detection (lvd) (8-pin devices only) ? bandgap generated precision vo ltage references available for the adc, comparator, vbo, and lvd ? power-on reset (por) ? 2.7 v to 3.6 v operating voltage ? 8-, 20-, and 28-pin packages ? 0 c to +70 c and -40 c to +105 c for operating temperature ranges part selection guide table 1 on page 3 identifies the basic features an d package styles available for each device within the z8 encore! xp ? f082a series product line.
ps022825-0908 overview z8 encore! xp ? f082a series product specification 3 table 1. z8 encore! xp ? f082a series family part selection guide part number flash (kb) ram (b) nvds 1 (b) i/o comparator advanced analog 2 adc inputs packages z8f082a 8 1024 0 6?23 yes yes 4?8 8-, 20- and 28-pin z8f081a 8 1024 0 6?25 yes no 0 8-, 20- and 28-pin z8f042a 4 1024 128 6?23 yes yes 4?8 8-, 20- and 28-pin z8f041a 4 1024 128 6?25 yes no 0 8-, 20- and 28-pin z8f022a 2 512 64 6?23 yes yes 4?8 8-, 20- and 28-pin z8f021a 2 512 64 6?25 yes no 0 8-, 20- and 28-pin z8f012a 1 256 16 6?23 yes yes 4?8 8-, 20- and 28-pin z8f011a 1 256 16 6?25 yes no 0 8-, 20- and 28-pin 1 non-volatile data storage. 2 advanced analog includes adc, temperature s ensor, and low-power operational amplifier.
ps022825-0908 overview z8 encore! xp ? f082a series product specification 4 block diagram figure 1 displays the block diagram of the architecture of the z8 encore! xp ? f082a series devices. figure 1. z8 encore! xp f082a series block diagram gpio irda uart timers adc flash memory flash controller ram ram controller interrupt controller on-chip debugger ez8 cpu wdt por/vbo and reset controller xtal/rc oscillator register bus memory busses system clock comparator temperature sensor nvds controller low power rc oscillator internal oscillator control oscillator precision low power op amp
ps022825-0908 overview z8 encore! xp ? f082a series product specification 5 cpu and peripheral overview ez8 cpu features the ez8 cpu, zilog?s latest 8-bit central processing unit (cpu), meets the continuing demand for faster and more code-efficient microcontrollers. the ez8 cpu executes a superset of the original z8 ? instruction set. the features of ez8 cpu include: ? direct register-to-register architecture allows each register to function as an accumulator, improving exec ution time and decreasing the required program memory. ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks. ? compatible with existing z8 code. ? expanded internal register file allows access of up to 4 kb. ? new instructions improve execution effici ency for code developed using higher- level programming languages, including c. ? pipelined instruction fetch and execution. ? new instructions for improved performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult, and srl. ? new instructions support 12-bit linear addressing of the register file. ? up to 10 mips operation. ? c-compiler friendly. ? 2 to 9 clock cycles per instruction. for more information on ez8 cpu, refer to ez8 cpu core user manual (um0128) avail- able for download at www.zilog.com . 10-bit analog-to-dig ital converter the optional analog-to-digital co nverter (adc) converts an analog input signal to a 10-bit binary number. the adc accepts inputs from ei ght different analog input pins in both single-ended and differential modes. the adc also features a unity gain buffer when high input impedance is required.
ps022825-0908 overview z8 encore! xp ? f082a series product specification 6 low-power operational amplifier the optional low-power operatio nal amplifier (lpo) is a general-purpose amplifier primarily targeted for current sense applications . the lpo output may be routed internally to the adc or externally to a pin. internal precision oscillator the internal precision oscillator (ipo) is a trimmable clock source that requires no external components. temperature sensor the optional temperature sensor produces an anal og output proportional to the device tem- perature. this signal can be sent to e ither the adc or the analog comparator. analog comparator the analog comparator compares the signal at an input pin with either an internal pro- grammable voltage reference or a second input pin. the comparat or output can be used to drive either an output pin or to generate an interrupt. external crystal oscillator the crystal oscillator circuit pr ovides highly accurate clock fre quencies with the use of an external crystal, ceramic resonator or rc network. low voltage detector the low voltage detector (lvd) is able to ge nerate an interrupt wh en the supply voltage drops below a user-programmable level. th e lvd is available on 8-pin devices only. on-chip debugger the z8 encore! xp ? f082a series products feature an integrated on-chip debugger (ocd) accessed via a single-pin interface. th e ocd provides a rich-set of debugging capabilities, such as reading and writing re gisters, programming flash memory, setting breakpoints, and executing code.
ps022825-0908 overview z8 encore! xp ? f082a series product specification 7 universal asynchronous receiver/transmitter the full-duplex universal asynchronous receiver /transmitter (uart) is included in all z8 encore! xp package types. the uart suppor ts 8- and 9-bit data modes and selectable parity. the uart also supports multi-drop address processing in hardware. the uart baud rate generator (brg) can be config ured and used as a basic 16-bit timer. timers two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provid e a 16-bit programmable reload counter and operate in one-shot, continuous, gated, capture, capture restart, compare, capture and compare, pwm single output and pwm dual output modes. general-purpose input/output the z8 encore! xp f082a series features 6 to 25 port pins (ports a?d) for general- pur- pose input/output (gpio). the number of gpio pins available is a function of package, and each pin is individually programmable. 5 v tolerant input pins are available on all i/os on 8-pin devices and most i/os on other package types. direct led drive the 20- and 28-pin devices supp ort controlled current sinking output pins capable of driving leds without the ne ed for a current limiting resistor. these led drivers are independently programm able to four different intensity levels. flash controller the flash controller programs and erases fl ash memory. the flash controller supports several protection mechanisms against accidental program and erasure, as well as factory serialization and read protection. non-volatile data storage the non-volatile data storage (nvds) uses a hybrid hardware/s oftware scheme to implement a byte programmable data memory and is capable of over 100,000 write cycles. devices with 8 kb flash memory do not include the nvds feature. note:
ps022825-0908 overview z8 encore! xp ? f082a series product specification 8 interrupt controller the z8 encore! xp ? f082a series products support up to 20 interrupts. these interrupts consist of 8 internal peripheral interrupts and 12 general-purpose i/o pin interrupt sources. the interrupts have three le vels of programmable interrupt priority. reset controller the z8 encore! xp f082a series pr oducts can be reset using the reset pin, power-on reset, watchdog timer (wdt) time-out, stop mode exit, or voltage brownout (vbo) warning signal. the reset pin is bi-directional, that is, it functions as reset source as well as a reset indicator.
ps022825-0908 pin description z8 encore! xp ? f082a series product specification 9 pin description the z8 encore! xp ? f082a series products are available in a variety of packages styles and pin configurations. this ch apter describes the signals and available pin configurations for each of the package styles. for informa tion on physical package specifications, see packaging on page 241. available packages the following package styles are available fo r each device in the z8 encore! xp f082a series product line: ? soic ? 8-, 20-, and 28-pin ? pdip ? 8-, 20-, and 28-pin ? ssop ? 20- and 28- pin ? qfn (this is an mlf-s, a qfn style pa ckage with an 8-pin soic footprint) ? 8-pin in addition, the z8 encore! xp f082a series devices are ava ilable both with and without advanced analog capability (adc, temperature sensor and op amp). devices z8f082a, z8f042a, z8f022a, and z8f012a contain the advanced analog, while devices z8f081a, z8f041a, z8f021a, and z8f011a do not have the advanced analog capability. pin configurations figure 2 through figure 4 display the pin configurat ions for all the packages available in the z8 enco re! xp f082a series. see table 2 on page 11 for a description of the signals. the analog input alternate functions (ana x ) are not available on the z8f081a, z8f041a, z8f021a, and z8f011 a devices. the analog supply pins (av dd and av ss ) are also not available on these parts, and are replaced by pb6 and pb7. at reset, all port a, b and c pins default to an input state. in addition, any alternate functionality is not enabled, so the pins function as general purpose input ports until programmed otherwise. at powerup, the pd0 pin defaults to the reset alternate function.
ps022825-0908 pin description z8 encore! xp ? f082a series product specification 10 the pin configurations listed are prelim inary and subject to change based on manufacturing limitations. figure 2. z8f08xa, z8f04xa, z8f02xa, and z8f01xa in 8-pin soic, qfn/mlf- s, or pdip package figure 3. z8f08xa, z8f04xa, z8f02xa, and z8 f01xa in 20-pin soic, ssop or pdip package figure 4. z8f08xa, z8f04xa, z8f02xa, and z8 f01xa in 28-pin soic, ssop or pdip package vss pa5/txd0/t1out /ana0/cinp/ampout pa4/rxd0/ana1/cinn/ampinn pa3/cts0 /ana2/cout/ampinp/t1in vdd pa0/t0in/t0out /xin//dbg pa1/t0out/xout/an a3/vref/clkin pa2/reset /de0/t1out 2 1 3 4 7 8 6 5 pb0/ana0/ampout pc3/cout/led pc2/ana6/led/vref pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset /pd0 pa7/t1out pa6/t1in/t1out pb1/ana1/ampinn pb2/ana2/ampinp pb3/clkin/ana3 vdd pa0/t0in/t0out /xin pa1/t0out/xout vss pa2/de0 1 pa5/txd0 pa3/cts0 5 10 pa4/rxd0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb1/ana1/ampinn pb0/ana0/ampout pc3/cout/led pc2/ana6/led pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset /pd0 pc7/led pb2/ana2/ampinp pb3/clkin/ana3 pb4/ana7 pb5/vref (pb6) avdd vdd pa0/t0in/t0out /xin pa1/t0out/xout 1 pc6/led vss 5 10 (pb7) avss pa2/de0 pa3/cts0 pa4/rxd0 14 pa5/txd0 2 3 4 6 7 8 9 11 12 13 pc5/led pc4/led pa7/t1out pa6/t1in/t1out 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps022825-0908 pin description z8 encore! xp ? f082a series product specification 11 signal descriptions table 2 describes the z8 encore! xp f082a series signals. see pin configurations on page 9 to determine the signals availa ble for the specific package styles. table 2. signal descriptions signal mnemonic i/o description general-purpose i/o ports a?d pa[7:0] i/o port a. these pins are used for general-purpose i/o. pb[7:0] i/o port b. these pins are used for general-purpose i/o. pb6 and pb7 are available only in those devices without an adc. pc[7:0] i/o port c. these pins are used for general-purpose i/o. pd[0] i/o port d. this pin is used for general-purpose output only. note: pb6 and pb7 are only available in 28-pin packages wi thout adc. in 28-pin packages with adc, they are replaced by av dd and av ss . uart controllers txd0 o transmit data. this signal is the tr ansmit output from the uart and irda. rxd0 i receive data. this signal is the receive input for the uart and irda. cts0 i clear to send. this signal is the flow control input for the uart. de o driver enable. this signal allows au tomatic control of external rs-485 drivers. this signal is approximat ely the inverse of the txe (transmit empty) bit in the uart status 0 register. the de signal may be used to ensure the external rs-485 driver is enabled when data is transmitted by the uart. timers t0out/t1out o timer output 0?1. these signals are outputs from the timers. t0out /t1out o timer complement output 0?1. these signals are output from the timers in pwm dual output mode. t0in/t1in i timer input 0?1. these signals are used as the capture, gating and counter inputs. comparator cinp/cinn i comparator inputs. these signals are the positive and negative inputs to the comparator. cout o comparator output.
ps022825-0908 pin description z8 encore! xp ? f082a series product specification 12 analog ana[7:0] i analog port. these signals are us ed as inputs to the analog-to-digital converter (adc). vref i/o analog-to-digital converter referenc e voltage input, or buffered output for internal reference. low-power operationa l amplifier (lpo) ampinp/ampinn i lpo inputs. if enabled, these pi ns drive the positive and negative amplifier inputs respectively. ampout o lpo output. if enabled, this pin is driven by the on-chip lpo. oscillators xin i external crystal input. this is the input pin to the crystal oscillator. a crystal can be connected between it and the xout pin to form the oscillator. in addition, this pin is used with external rc networks or external clock drivers to provide the system clock. xout o external crystal output. this pin is the output of the crystal oscillator. a crystal can be connected between it and the xin pin to form the oscillator. clock input clkin i clock input signal. this pin may be used to input a ttl-level signal to be used as the system clock. led drivers led o direct led drive capability. all port c pins have the cap ability to drive an led without any other external components. these pins have programmable drive strengths set by the gpio block. on-chip debugger dbg i/o debug. this signal is the control and data input and output to and from the on-chip debugger. the dbg pin is open-drain and requires a pull-up resis- tor to ensure proper operation. reset reset i/o reset. generates a reset when assert ed (driven low). also serves as a reset indicator; the z8 en core! xp forces this pin lo w when in reset. this pin is open-drain and features an enabled internal pull-up resistor. table 2. signal descriptions (continued) signal mnemonic i/o description caution:
ps022825-0908 pin description z8 encore! xp ? f082a series product specification 13 pin characteristics table 3 describes the characteristics for each pi n available on the z8 encore! xp f082a series 20- and 28-pin devices. data in table 3 is sorted alphabetica lly by the pin symbol mnemonic. table 4 on page 14 provides deta iled information about the ch aracteristics for each pin available on the z8 encore! xp f082a series 8-pin devices. all six i/o pins on the 8-pin packages are 5 v-tolerant (unless the pull-up devices are enabled). the column in table 3 below describes 5 v-tolera nce for the 20- and 28-pin packages only. power supply v dd i digital power supply. av dd i analog power supply. v ss i digital ground. av ss i analog ground. note: the av dd and av ss signals are available only in 28-pin packages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc. table 3. pin characteristics (20- and 28-pin devices) symbol mnemonic direction reset direction active low or active high tristate output internal pull- up or pull-down schmitt- trigger input open drain output 5 v tolerance avdd n/a n/a n/a n/a n/a n/a n/a n/a avss n/a n/a n/a n/a n/a n/a n/a na dbg i/o i n/a yes yes yes yes no pa[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pa[7:2] unless pullups enabled pb[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pb[7:6] unless pullups enabled table 2. signal descriptions (continued) signal mnemonic i/o description note:
ps022825-0908 pin description z8 encore! xp ? f082a series product specification 14 pb6 and pb7 are available only in those devices without adc. ) pc[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pc[7:3] unless pullups enabled reset/pd0 i/o i/o (defaults to reset ) low (in reset mode) yes (pd0 only) programmable for pd0; always on for reset yes programmable for pd0; always on for reset yes, unless pullups enabled vdd n/a n/a n/a n/a n/a n/a vss n/a n/a n/a n/a n/a n/a table 4. pin characteristics (8-pin devices) symbol mnemonic direction reset direction active low or active high tristate output internal pull- up or pull-down schmitt- trigger input open drain output 5 v tolerance pa0/dbg i/o i (but can change during reset if key sequence detected) n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled pa1 i/o i n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled reset /pa2 i/o i/o (defaults to reset ) low (in reset mode) yes programmable for pa2; always on for reset yes programmable for pa2; always on for reset yes, unless pull-ups enabled pa[5:3] i/o i n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled v dd n/a n/a n/a n/a n/a n/a n/a n/a v ss n/a n/a n/a n/a n/a n/a n/a n/a table 3. pin characteristics (20- and 28-pin devices) (continued) symbol mnemonic direction reset direction active low or active high tristate output internal pull- up or pull-down schmitt- trigger input open drain output 5 v tolerance note:
ps022825-0908 address space z8 encore! xp ? f082a series product specification 15 address space the ez8 cpu can access the following three distinct address spaces: 1. the register file contains addresses for the general-purpose registers and the ez8 cpu, peripheral, and general-purp ose i/o port control registers. 2. the program memory contains addresses fo r all memory locations having executable code and/or data. 3. the data memory contains addresses for all memory locations that contain data only. these three address spaces are covered brie fly in the following subsections. for more information on ez8 cpu and its address space, refer to ez8 cpu core user manual (um0128) available for download at www.zilog.com . register file the register file address space in the z8 encore! ? mcu is 4 kb (4096 bytes). the register file is composed of two sections: co ntrol registers and general-purpose registers. when instructions are executed, registers defined as sources are read, and registers defined as destinations are written. the architecture of the ez8 cpu allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 4 kb register file address space are reserved for control of the ez8 cpu, the on-chip peripherals, and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256 b control register section are reserved (unavailable). reading fro m a reserved register file address returns an undefined value. writing to reserved register file addr esses is not recommended and can produce unpredictable results. the on-chip ram always begins at address 000h in the register file address space. the z8 encore! xp ? f082a series devices contain 256 b to 1 kb of on-chip ram. reading from register file addresses outsid e the available ram addresses (and not within the control register address space) returns an undefined value. writing to these register file addresses produces no effect. program memory the ez8 cpu supports 64 kb of program memory address space. the z8 encore! xp f082a series devices contain 1 kb to 8 kb of on-chip flash memory in the program memory address space, depending on th e device. reading from program memory
ps022825-0908 address space z8 encore! xp ? f082a series product specification 16 addresses outside the available flash memory addresses returns ffh . writing to these unimplemented program memory addresses produces no effect. table 5 describes the program memory maps for the z8 en core! xp f082a se ries products. table 5. z8 encore! xp f082 a series program memory maps program memory address (hex) function z8f082a and z8f081a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?0039 reserved 003a?003d oscillator fail trap vectors 003e?1fff program memory z8f042a and z8f041a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?0039 reserved 003a?003d oscillator fail trap vectors 003e?0fff program memory
ps022825-0908 address space z8 encore! xp ? f082a series product specification 17 data memory the z8 encore! xp f082a series does not use the ez8 cpu?s 64 kb data memory address space. flash information area table 6 on page 18 describes the z8 encore! xp f082a series flash information area. this 128 b information area is accessed by settin g bit 7 of the flash page select register to 1. when access is enabled, the flash in formation area is mapped into the program memory and overlays the 128 bytes at addresses fe00h to ff7fh . when the information area access is enabled, all reads from thes e program memory addresses return the infor- z8f022a and z8f021a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?0039 reserved 003a?003d oscillator fail trap vectors 003e?07ff program memory z8f012a and z8f011a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?0039 reserved 003a?003d oscillator fail trap vectors 003e?03ff program memory * see table 32 on page 56 for a list of the interrupt vectors. table 5. z8 encore! xp f082a series program memory maps (continued) program memory address (hex) function
ps022825-0908 address space z8 encore! xp ? f082a series product specification 18 mation area data rather than the program me mory data. access to the flash information area is read-only. table 6. z8 encore! xp f082a series flash memory information area map program memory address (hex) function fe00?fe3f zilog option bits/calibration data fe40?fe53 part number 20-character ascii alphanumeric code left justified and filled with ffh fe54?fe5f reserved fe60?fe7f zilog calibration data fe80?ffff reserved
ps022825-0908 register map z8 encore! xp ? f082a series product specification 19 register map table 7 provides the address map for the re gister file of the z8 encore! xp ? f082a series devices. not all devices and package st yles in the z8 encore! xp f082a series support the adc, or all of the gpio ports. consider registers for unimplemented periph- erals as reserved. table 7. register file address map address (hex) register description mnemonic reset (hex) page no general-purpose ram z8f082a/z8f081a devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f042a/z8f041a devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f022a/z8f021a devices 000?1ff general-purpose register file ram ? xx 200?eff reserved ? xx z8f012a/z8f011a devices 000?0ff general-purpose register file ram ? xx 100?eff reserved ? xx timer 0 f00 timer 0 high byte t0h 00 87 f01 timer 0 low byte t0l 01 87 f02 timer 0 reload high byte t0rh ff 88 f03 timer 0 reload low byte t0rl ff 88 f04 timer 0 pwm high byte t0pwmh 00 88 f05 timer 0 pwm low byte t0pwml 00 89 f06 timer 0 control 0 t0ctl0 00 83 f07 timer 0 control 1 t0ctl1 00 84 timer 1 f08 timer 1 high byte t1h 00 87 f09 timer 1 low byte t1l 01 87 f0a timer 1 reload high byte t1rh ff 88 xx=undefined
ps022825-0908 register map z8 encore! xp ? f082a series product specification 20 f0b timer 1 reload low byte t1rl ff 88 f0c timer 1 pwm high byte t1pwmh 00 88 f0d timer 1 pwm low byte t1pwml 00 89 f0e timer 1 control 0 t1ctl0 00 83 f0f timer 1 control 1 t1ctl1 00 84 f10?f6f reserved ? xx uart f40 uart transmit/receive data registers txd, rxd xx 113 f41 uart status 0 register u0stat0 00 111 f42 uart control 0 register u0ctl0 00 108 f43 uart control 1 register u0ctl1 00 108 f44 uart status 1 register u0stat1 00 112 f45 uart address compare register u0addr 00 114 f46 uart baud rate high byte register u0brh ff 114 f47 uart baud rate low byte register u0brl ff 114 analog-to-digital converter (adc) f70 adc control 0 adcctl0 00 130 f71 adc control 1 adcctl1 80 130 f72 adc data high byte adcd_h xx 133 f73 adc data low bits adcd_l xx 133 f74?f7f reserved ? xx low power control f80 power control 0 pwrctl0 80 35 f81 reserved ? xx led controller f82 led drive enable leden 00 52 f83 led drive level high byte ledlvlh 00 53 f84 led drive level low byte ledlvll 00 54 f85 reserved ? xx oscillator control f86 oscillator control oscctl a0 190 f87?f8f reserved ? xx comparator 0 f90 comparator 0 control cmp0 14 136 table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page no xx=undefined
ps022825-0908 register map z8 encore! xp ? f082a series product specification 21 f91?fbf reserved ? xx interrupt controller fc0 interrupt request 0 irq0 00 60 fc1 irq0 enable high bit irq0enh 00 63 fc2 irq0 enable low bit irq0enl 00 63 fc3 interrupt request 1 irq1 00 61 fc4 irq1 enable high bit irq1enh 00 64 fc5 irq1 enable low bit irq1enl 00 64 fc6 interrupt request 2 irq2 00 62 fc7 irq2 enable high bit irq2enh 00 65 fc8 irq2 enable low bit irq2enl 00 65 fc9?fcc reserved ? xx fcd interrupt edge select irqes 00 67 fce shared interrupt select irqss 00 67 fcf interrupt control irqctl 00 67 gpio port a fd0 port a address paaddr 00 45 fd1 port a control pactl 00 47 fd2 port a input data pain xx 47 fd3 port a output data paout 00 47 gpio port b fd4 port b address pbaddr 00 45 fd5 port b control pbctl 00 47 fd6 port b input data pbin xx 47 fd7 port b output data pbout 00 47 gpio port c fd8 port c address pcaddr 00 45 fd9 port c control pcctl 00 47 fda port c input data pcin xx 47 fdb port c output data pcout 00 47 gpio port d fdc port d address pdaddr 00 45 fdd port d control pdctl 00 47 fde reserved ? xx table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page no xx=undefined
ps022825-0908 register map z8 encore! xp ? f082a series product specification 22 fdf port d output data pdout 00 47 fe0?fef reserved ? xx watchdog timer (wdt) ff0 reset status (read-only) rststat x0 30 watchdog timer control (write-only) wdtctl n/a 94 ff1 watchdog timer reload upper byte wdtu 00 95 ff2 watchdog timer reload high byte wdth 04 95 ff3 watchdog timer reload low byte wdtl 00 95 ff4?ff5 reserved ? xx trim bit control ff6 trim bit address trmadr 00 155 ff7 trim bit data trmdr 00 156 flash memory controller ff8 flash control fctl 00 149 ff8 flash status fstat 00 150 ff9 flash page select fps 00 151 flash sector protect fprot 00 151 ffa flash programming frequency high byte ffreqh 00 152 ffb flash programming frequency low byte ffreql 00 152 ez8 cpu ffc flags ? xx refer to ez8 cpu core user manual (um0128) ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx table 7. register file address map (continued) address (hex) register description mnemonic reset (hex) page no xx=undefined
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 23 reset, stop mode recovery, and low voltage detection the reset controller within the z8 encore! xp ? f082a series controls reset and stop mode recovery operation and provides indication of low su pply voltage conditions. in typical operation, the following events cause a reset: ? power-on reset (por) ? voltage brownout (vbo) ? watchdog timer time-out (when configur ed by the wdt_res flash option bit to initiate a reset) ? external reset pin assertion (when the alternate reset function is enabled by the gpio register) ? on-chip debugger initiated re set (ocdctl[0] set to 1) when the device is in stop mode, a stop mode recovery is initiated by either of the following: ? watchdog timer time-out ? gpio port input pin transition on an enabled stop mode recovery source the low voltage detection circuitry on the device (available on the 8-pin product versions only) performs the fo llowing functions: ? generates the vbo reset when the supply voltage drops below a minimum safe level. ? generates an interrupt when the supply voltage drops below a user-defined level (8-pin devices only). reset types the z8 encore! xp f082a series provides severa l different types of r eset operation. stop mode recovery is considered as a form of reset. table 8 lists the types of reset and their operating characteristics. the sy stem reset is longer if the external crystal oscillator is enabled by the flash option bits, allowing additional time for oscillator start-up.
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 24 during a system reset or stop mode recovery , the internal precision oscillator requires 4 s to start up. then the z8 encore! xp f082a series device is held in reset for 66 cycles of the internal precision oscillator. if th e crystal oscillator is enabled in the flash option bits, this reset period is increased to 5000 ipo cycles. when a reset occurs because of a low voltage condition or po wer-on reset (por), this dela y is measured from the time that the supply voltage first exceeds the po r level. if the external pin reset remains asserted at the end of the reset period, the device remains in reset until the pin is deas- serted. at the beginning of reset, all gpio pins are co nfigured as inputs with pull-up resistor dis- abled, except pd0 (or pa2 on 8-pin devices) wh ich is shared with the reset pin. on reset, the pd0 is configured as a bidirectional open-dr ain reset. the pin is internally driven low during port reset, after which the user code may reconfigure this pin as a general purpose output. during reset, the ez8 cpu and on-chip peripher als are idle; however, the on-chip crystal oscillator and watchdog timer oscillator continue to run. upon reset, control registers w ithin the register file that have a defined reset value are loaded with their reset values. other contro l registers (including the stack pointer, register pointer, and flags) and general- purpose ram are undefined following reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program coun ter. program execution begins at the reset vector address. as the control registers are re-i nitialized by a system reset, th e system clock after reset is always the ipo. the software must reconfigur e the oscillator control block, such that the correct system clock source is enabled and selected. table 8. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as app licable) reset 66 in ternal precision oscillator cycles system reset with crystal oscillator enabled reset (as applicable) res et 5000 internal precision oscillator cycles stop mode recovery un affected, except wdt_ctl and osc_ctl registers reset 66 internal precision oscillator cycles + ipo startup time stop mode recovery with crystal oscillator enabled unaffected, except wdt_ctl and osc_ctl registers reset 5000 internal prec ision oscillator cycles
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 25 reset sources table 9 lists the possible sources of a system reset. power-on reset z8 encore! xp f082a series devices co ntain an internal power-on reset circuit. the por circuit monitors the supply voltage and holds the device in the reset state until the supply voltage reaches a safe operating level. after the supply voltage exceeds the por voltage threshold (v por ), the device is held in the reset state until the por counter has timed out. if the crystal osc illator is enabled by the option bits, this timeout is longer. after the z8 encore! xp f082a series device exits the power-on reset state, the ez8 cpu fetches the reset vector. fo llowing power-on reset, the por status bit in the reset status (rststat) register is set to 1. figure 5 displays power-on reset operation. see electrical characteristics on page 221 for the por threshold voltage (v por ). table 9. reset sources and resulting reset type operating mode reset source special conditions normal or halt modes power-on reset/voltage brownout reset delay begins after supply voltage exceeds por level. watchdog timer time-out when configured for reset none. reset pin assertion all reset pulses less than three system clocks in width are ignored. on-chip debugger initiated reset (ocdctl[0] set to 1) system reset, except the on-chip debugger is unaffected by the reset. stop mode power-on reset/voltage brownout reset delay begins after supply voltage exceeds por level. reset pin assertion all reset pulses less than the specified analog delay are ignored. see table 131 on page 229 . dbg pin driven low none.
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 26 figure 5. power-on reset operation voltage brownout reset the devices in the z8 encore! xp f082a series provide low voltage brownout (vbo) protection. the vbo circuit senses when the supply voltage drops to an unsafe level (below the vbo threshold voltage) and forces the device into the reset state. while the supply voltage remains below the power-on reset voltage threshold (v por ), the vbo block holds the device in the reset. after the supply voltage again exceeds the po wer-on reset voltage threshold, the device progresses through a full system reset seque nce, as described in the power-on reset section. following power-on reset, the por status bit in the reset status (rststat) register is set to 1. figure 6 displays voltage brownout operation. see electrical charac- teristics on page 221 for the vbo and por threshold voltages (v vbo and v por ). the voltage brownout circuit can be either enabled or disabled during stop mode. operation during stop mode is set by the vbo_ao flash option bit. see flash option bits for information about configuring vbo_ao. v cc = 0.0 v v cc = 3.3 v v por v vbo internal precision internal reset signal program execution oscillator start-up por counter delay optional xtal counter delay oscillator crystal oscillator note: not to scale
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 27 figure 6. voltage brownout reset operation the por level is greater than the vbo leve l by the specified hysteresis value. this ensures that the device undergoes a powe r-on reset after recovering from a vbo condition. watchdog timer reset if the device is in normal or halt mode, the watchdog timer can initiate a system reset at time-out if the wdt_res flash optio n bit is programmed to 1. this is the unprogrammed state of the wdt_res flash option bit. if the bit is programmed to 0, it configures the watchdog timer to cause an interrupt, not a system reset, at time-out. the wdt bit in the reset status (rststat) regi ster is set to signify that the reset was initiated by the watchdog timer. external reset input the reset pin has a schmitt-triggered input and an internal pull-up resistor. once the reset pin is asserted for a minimum of four sy stem clock cycles, th e device progresses through the system reset sequen ce. because of the possible asynchronicity of the system clock and reset signals, the required reset duration may be as short as three clock periods vcc = 3.3 v v por v vbo internal reset signal program execution program execution voltage brownout vcc = 3.3 v system clock por counter delay note: not to scale
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 28 and as long as four. a reset pulse three cloc k cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. while the reset input pin is asserted low, the z8 encore! xp ? f082a series devices remain in the reset state. if the reset pin is held low beyond the system reset time- out, the device exits the reset state on th e system clock rising edge following reset pin deassertion. following a system re set initiated by the external reset pin, the ext sta- tus bit in the reset status (rststat) register is set to 1. external reset indicator during system reset or when enabled by the gpio logic (see port a?d control registers on page 46), the reset pin functions as an open-drain (a ctive low) reset mode indicator in addition to the input functionality. this reset output feature allows a z8 encore! xp f082a series device to reset other components to wh ich it is connected, even if that reset is caused by internal sources such as por, vbo or wdt events. after an internal reset even t occurs, the internal circu itry begins driving the reset pin low. the reset pin is held low by the internal circuitry until the appropriate delay listed in table 8 has elapsed. on-chip debugger initiated reset a power-on reset can be initiated usi ng the on-chip debugger by setting the rst bit in the ocd control register. the on-chip debugger block is not reset but the rest of the chip goes through a normal system reset. the rst bit automatically clears during the system reset. following the system reset the por bit in the reset status (rststat) register is set. stop mode recovery stop mode is entered by execution of a stop instruction by the ez8 cpu. see low- power modes on page 33 for detailed stop mode information. during stop mode recov- ery (smr), the cpu is held in reset for 66 ipo cy cles if the crystal oscillator is disabled or 5000 cycles if it is enabled. the smr delay (see table 131 on page 229) t smr , also includes the time required to start up the ipo. stop mode recovery does not affect on-chi p registers other than the watchdog timer control register (wdtctl) and the oscilla tor control register (oscctl). after any stop mode recovery, the ipo is enabled an d selected as the system clock. if another system clock source is required, the stop mo de recovery code must reconfigure the oscil- lator control block such that the correct sy stem clock source is enabled and selected. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program coun ter. program execution begins at the reset
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 29 vector address. following stop mode recovery, the stop bit in the reset status (rststat) register is set to 1. table 10 lists the stop mode recovery sources and result- ing actions. the text following provides more detailed information abou t each of the stop mode recovery sources. stop mode recovery usin g watchdog timer time-out if the watchdog timer times out during stop mode, the device undergoes a stop mode recovery sequence. in the reset status (rst stat) register, the wdt and stop bits are set to 1. if the watchdog timer is configured to generate an interrupt upon time-out and the z8 encore! xp f082a series device is c onfigured to respond to interrupts, the ez8 cpu services the watchdog timer interrupt request following the normal stop mode recovery sequence. stop mode recovery using a gpio port pin transition each of the gpio port pins may be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode recove ry source, a change in the input pin value (from high to low or from low to hi gh) initiates stop mode recovery. the smr pulses shorter than specified does not trigger a recovery (see table 131 on page 229). when this happens, the stop bit in the reset status (rststat) register is set to 1. in stop mode, the gpio port input data re gisters (pxin) are disabled. the port input data registers record the port transition only if the signal stays on the port pin through the end of the stop mode recovery delay. as a result, short pulses on the port pin can table 10. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watchdog timer time-out when configured for reset stop mode recovery watchdog timer time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery assertion of external reset pin system reset debug pin driven low system reset note: caution:
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 30 initiate stop mode recovery without being wr itten to the port input data register or without initiating an interrup t (if enabled for that pin). stop mode recovery us ing the external reset pin when the z8 encore! xp f082 a series device is in stop mode and the external reset pin is driven low, a system reset occurs. because of a glitch filter operating on the reset pin, the low pulse must be greater than the mi nimum width specified, or it is ignored. see electrical characteristics on page 221 for details. low voltage detection in addition to the voltage brownout (vbo) r eset described above, it is also possible to generate an interrupt when the supply voltage drops be low a user-selected value. for details about configuring the low voltage dete ction (lvd) and the threshold levels avail- able, see trim bit address 0003h on page 159. the lvd function is available on the 8- pin product versions only. when the supply voltage drops below the lvd threshold, the lvd bit of the reset status (rststat) register is set to one. this bit remains one until the low-voltage condition goes away. reading or writing this bit does not clear it. the lvd circuit can also generate an interrupt when so enabled, see interrupt vectors and priority on page 58. the lvd bit is not latched, so enabling the interrupt is the only way to guarantee detection of a transient low voltage event. the lvd functionality de pends on circuitry shared with the vbo block; therefore, disabling the vbo also disables the lvd. reset register definitions the following sections de fine the reset registers. reset status register the reset status (rststat) register is a read-o nly register that indicates the source of the most recent reset event, indicates a st op mode recovery ev ent, and indicates a watchdog timer time-out. reading this regi ster resets the upper four bits to 0. this register shares its address with the watchdog timer control register, which is write-only (see table 11 on page 31).
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 31 por?power-on reset indicator if this bit is set to 1, a power-on reset ev ent occurs. this bit is reset to 0 if a wdt time-out or stop mode recovery occurs. this bi t is also reset to 0 when the register is read. stop?stop mode recovery indicator if this bit is set to 1, a stop mode recovery occurs. if the stop and wdt bits are both set to 1, the stop mode recovery occu rs because of a wdt time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery was not caused by a wdt time-out. this bit is reset by a power-on reset or a wdt time-ou t that occurred while not in stop mode. reading this register also resets this bit. wdt?watchdog timer time-out indicator if this bit is set to 1, a wdt time-out occurs . a por resets this pin. a stop mode recov- ery from a change in an input pin also resets this bit. reading this register resets this bit. this read must occur before clearing the wdt interrupt. ext?external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurs. a power-on reset or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. reserved?must be 0. lvd?low voltage detection indicator if this bit is set to 1 the current state of the supply voltage is below the low voltage detection threshold. this value is not latched but is a real-time indicator of the supply volt- age level. table 11. reset status register (rststat) bits 7 6 5 4 3 2 1 0 field por stop wdt ext reserved lvd reset see descriptions below 0 0 0 0 0 r/w rrrrrrrr addr ff0h reset or stop mode recovery event por stop wdt ext power-on reset 1000 reset using reset pin assertion 0001 reset using watchdog timer time-out 0010 reset using the on-chip debugger (octctl[1] set to 1) 1000 reset from stop mode using dbg pin driven low 1000 stop mode recovery using gpio pin transition 0100 stop mode recovery using watchdog timer time-out 0110
ps022825-0908 reset, stop mode recovery, and low voltage detection z8 encore! xp ? f082a series product specification 32
ps022825-0908 low-power modes z8 encore! xp ? f082a series product specification 33 low-power modes the z8 encore! xp f082a series produc ts contain power-saving features. the highest level of power reduction is provided by the stop mode, in which nearly all device functions are powered down. the next lower level of power reduction is provided by the halt mode, in which the cpu is powered down. further power savings can be implemented by disabling individual peripheral blocks while in active mode (defined as be ing in neither stop nor halt mode). stop mode executing the ez8 cpu?s stop instruction pl aces the device into stop mode, powering down all peripherals except the voltage brow nout detector, the low-power operational amplifier and the watchdog timer. these thre e blocks may also be disabled for additional power savings. specifically, the operating characteristics are: ? primary crystal oscillator and internal pr ecision oscillator ar e stopped; xin and xout (if previously enabled) are disabl ed, and pa0/pa1 revert to the states programmed by the gpio registers. ? system clock is stopped. ? ez8 cpu is stopped. ? program counter (pc) stops incrementing. ? watchdog timer?s internal rc oscillator continues to operate if enabled by the oscillator control register. ? if enabled, the watchdog timer logic continues to operate. ? if enabled for operation in stop mode by the associated flash option bit, the voltage brownout protection ci rcuit continues to operate. ? low-power operational amplifier continue s to operate if enabled by the power control register to do so. ? all other on-chip peripherals are idle. to minimize current in stop mode, all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v cc or gnd). additionally, any gpios config- ured as outputs must also be driven to one of the supply rails. the device can be brought out of stop mode using stop mode recovery. for more information on stop mode recovery, see reset, stop mode recovery , and low voltage detection on page 23.
ps022825-0908 low-power modes z8 encore! xp ? f082a series product specification 34 halt mode executing the ez8 cpu?s halt instructio n places the device into halt mode, which powers down the cpu but leaves all other peripherals active. in halt mode, the operating characteristics are: ? primary oscillator is enable d and continues to operate. ? system clock is enabled and continues to operate. ? ez8 cpu is stopped. ? program counter (pc) stops incrementing. ? watchdog timer?s internal rc os cillator continues to operate. ? if enabled, the watchdog timer continues to operate. ? all other on-chip peripherals c ontinue to operate, if enabled. the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? watchdog timer time-out (interrupt or reset) ? power-on reset ? voltage brownout reset ? external reset pin assertion to minimize current in halt mode, all gpio pins that are configured as inputs must be driven to one of the supply rails (v cc or gnd). peripheral-level power control in addition to the stop and halt modes, it is possible to disable each peripheral on each of the z8 encore! xp f082a series devices. disabling a given peripheral minimizes its power consumption. power control register definitions the following sections define the power control registers. power control register 0 each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the bl ock. the default state of the low-power
ps022825-0908 low-power modes z8 encore! xp ? f082a series product specification 35 operational amplifier (lpo) is off. to use the lpo, clear the lpo bit, turning it on. clearing this bit might interfere with norm al adc measurements on ana0 (the lpo out- put). this bit enables the amplif ier even in stop mode. if the amplifier is not required in stop mode, disable it. failure to perform this results in st op mode currents greater than specified. this register is only reset during a por sequ ence. other system reset events do not affect it. lpo?low-power operational amplifier disable 0 = lpo is enabled (this ap plies even in stop mode). 1 = lpo is disabled. reserved?must be 0. vbo?voltage brownout detector disable this bit and the vbo_ao flas h option bit must both enable the vbo for the vbo to be active. 0 = vbo enabled 1 = vbo disabled temp?temperature sensor disable 0 = temperature sensor enabled 1 = temperature sensor disabled adc?analog-to-digital converter disable 0 = analog-to-digital converter enabled 1 = analog-to-digital converter disabled comp?comparator disable 0 = comparator is enabled 1 = comparator is disabled reserved?must be 0. asserting any power control bit disables the targeted block, regardless of any enable bits contained in the target block?s control registers. table 12. power control register 0 (pwrctl0) bits 7 6 5 4 3 2 1 0 field lpo reserved vbo temp adc comp reserved reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f80h note: note:
ps022825-0908 low-power modes z8 encore! xp ? f082a series product specification 36
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 37 general-purpose input/output the z8 encore! xp ? f082a series products support a maximum of 25 port pins (ports a? d) for general-purpose input/output (gpio) operations. each port contains control and data registers. the gpio cont rol registers determine data direction, open-drain, output drive current, programmable pull-ups, stop mode recovery functional- ity, and alternate pin functions. each port pin is individually programmable. in addition, the port c pins are capable of direct led drive at programmab le drive strengths. gpio port availability by device table 13 lists the port pins available w ith each device and package type. table 13. port availability by device and package type devices package adc port a port b port c port d total i/o z8f082asb, z8f082apb, z8f082aqb z8f042asb, z8f042apb, z8f042aqb z8f022asb, z8f022apb, z8f022aqb z8f012asb, z8f012apb, z8f012aqb 8-pin yes [5:0] no no no 6 z8f081asb, z8f081apb, z8f081aqb z8f041asb, z8f041apb, z8f041aqb z8f021asb, z8f021apb, z8f021aqb z8f011asb, z8f011apb, z8f011aqb 8-pin no [5:0] no no no 6 z8f082aph, z8f082ahh, z8f082ash z8f042aph, z8f042ahh, z8f042ash z8f022aph, z8f022ahh, z8f022ash z8f012aph, z8f012ahh, z8f012ash 20-pin yes [7:0] [3:0] [3:0] [0] 17 z8f081aph, z8f081ahh, z8f081ash z8f041aph, z8f041ahh, z8f041ash z8f021aph, z8f021ahh, z8f021ash z8f011aph, z8f011ahh, z8f011ash 20-pin no [7:0] [3:0] [3:0] [0] 17 z8f082apj, z8f082asj, z8f082ahj z8f042apj, z8f042asj, z8f042ahj z8f022apj, z8f022asj, z8f022ahj z8f012apj, z8f012asj, z8f012ahj 28-pin yes [7:0] [5:0] [7:0] [0] 23 z8f081apj, z8f081asj, z8f081ahj z8f041apj, z8f041asj, z8f041ahj z8f021apj, z8f021asj, z8f021ahj z8f011apj, z8f011asj, z8f011ahj 28-pin no [7:0] [7:0] [7:0] [0] 25
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 38 architecture figure 7 displays a simplified block diagram of a gpio port pin. in this figure, the ability to accommodate alternat e functions and variable port current drive strength is not displayed. figure 7. gpio port pin block diagram gpio alternate functions many of the gpio port pins can be used for general-purpose i/o and access to on-chip peripheral functions such as the timers and serial communication de vices. the port a?d alternate function sub-registers configure the se pins for either general-purpose i/o or alternate function operation. when a pin is conf igured for alternate fu nction, control of the port pin direction (input/output) is passed from the port a?d data direction registers to the alternate function ass igned to this pin. table 14 on page 41 lists th e alternate functions possible with each port pin. for those pins w ith more one alternate function, the alternate function is defined through alternate function sets sub-registers afs1 and afs2. the crystal oscillator fu nctionality is not controlled by th e gpio block. when the crystal oscillator is enabled in the os cillator control block, the gpio functionality of pa0 and pa1 is overridden. in that case, th ose pins function as input and output for the crystal oscillator. d q dq d q gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt-trigger
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 39 pa0 and pa6 contain two different timer fu nctions, a timer input and a complementary timer output. both of these fu nctions require the same gpio configuration, the selection between the two is based on the timer mode. see timers on page 69 for more details. for pin with multiple alternate functions, it is recommended to write to the afs1 and afs2 sub-registers before enabling the altern ate function via the af sub-register. this prevents spurious transitions throug h unwanted alternate function modes. direct led drive the port c pins provide a current sinked output capable of driving an led without requiring an external resistor. the output sink s current at programmable levels of 3 ma, 7 ma, 13 ma and 20 ma. this mode is enabled through the alternate function sub-register afs1 and is programmable through the led control registers. the led drive enable (leden) register turns on the drivers. the led drive level (ledlvlh and ledlvll) registers select the sink current. for correct function, the led anode must be connected to v dd and the cathode to the gpio pin. using all port c pins in led drive mode with maximum current may result in excessive total current. see electrical characteristics on page 221 for the maximum total current for the applicable package. shared reset pin on the 20- and 28-pin devices, the pd0 pin sh ares function with a bi-directional reset pin. unlike all other i/o pins, this pin does not de fault to gpio function on power-up. this pin acts as a bi-directional reset until the software re-configures it. the pd0 pin is output-only when in gpio mode. on the 8-pin product versions, the reset pin is shared with pa2, but the pin is not limited to output-only when in gpio mode. if pa2 on the 8-pin product is reconfigured as an input, ensure that no external stimulus drives the pin low during any reset sequence. since pa2 returns to its reset alternate function during system resets, driving it low holds the chip in a reset state un- til the pin is released. shared debug pin on the 8-pin version of this device only, the debug pin shares function with the pa0 gpio pin. this pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. if the unlock sequence is present, the debug func tion is unlocked and the pin no longer func- caution: caution:
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 40 tions as a gpio pin. if it is not present, the debug feature is disabled until/unless another reset event occurs. fo r more details, see on-chip debugger on page 173 . crystal oscillator override for systems using a crystal oscillator, pa0 and pa1 are used to connect the crystal. when the crystal oscillator is enabled (see oscillator control register definitions on page 190), the gpio settings are overridden and pa0 and pa1 are disabled. 5 v tolerance all six i/o pins on the 8-pin devices are 5 v-tolerant, unless the programmable pull-ups are enabled. if the pull-ups are en abled and inputs higher than v dd are applied to these parts, excessive current flows through thos e pull-up devices and can damage the chip. in the 20- and 28-pin versions of this devi ce, any pin which shares functionality with an adc, crystal or comparator port is not 5 v-tolerant, including pa[1:0], pb[5:0] and pc[2:0]. all other signal pins are 5 v-to lerant, and can safely handle inputs higher than v dd except when the programmable pull-ups are enabled. external clock setup for systems using an external ttl drive, pb 3 is the clock source for 20- and 28-pin devices. in this case, configure pb3 for a lternate function clkin. write the oscillator control (oscctl) register (see oscillator control register definitions on page 190) such that the external oscillator is selected as the system clock. for 8-pin devices use pa1 instead of pb3. note:
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 41 table 14. port alternate function mapping (non 8-pin parts) port pin mnemonic alternate function description alternate function set register afs1 port a pa0 t0in/t0out * timer 0 input/timer 0 output complement n/a reserved pa1 t0out timer 0 output reserved pa2 de0 uart 0 driver enable reserved pa3 cts0 uart 0 clear to send reserved pa4 rxd0/irrx0 uart 0/irda 0 receive data reserved pa5 txd0/irtx0 uart 0/irda 0 transmit data reserved pa6 t1in/t1out * timer 1 input/timer 1 output complement reserved pa7 t1out timer 1 output reserved note: because there is only a single alter nate function for each port a pin, t he alternate function set registers are not implemented for port a. enabling alte rnate function selections as described in port a?d alternate function sub-registers on page 47 automatically enables the associated alternate function. * whether pa0/pa6 take on the timer input or timer output complement function depends on the timer configuration as described in timer pin signal operation on page 82.
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 42 port b pb0 reserved afs1[0]: 0 ana0/ampout adc analog input/lpo output afs1[0]: 1 pb1 reserved afs1[1]: 0 ana1/ampinn adc analog input/lpo input (n) afs1[1]: 1 pb2 reserved afs1[2]: 0 ana2/ampinp adc analog input/lpo input (p) afs1[2]: 1 pb3 clkin external clock input afs1[3]: 0 ana3 adc analog input afs1[3]: 1 pb4 reserved afs1[4]: 0 ana7 adc analog input afs1[4]: 1 pb5 reserved afs1[5]: 0 vref* adc voltage reference afs1[5]: 1 pb6 reserved afs1[6]: 0 reserved afs1[6]: 1 pb7 reserved afs1[7]: 0 reserved afs1[7]: 1 note: because there are at most two choices of alternate func tion for any pin of port b, the alternate function set register afs2 is not used to select the function. also, alternate function selection as described in port a?d alternate function sub-registers on page 47 must also be enabled. * vref is available on pb5 in 28-pin products only. table 14. port alternate function mapping (non 8-pin parts) (continued) port pin mnemonic alternate function description alternate function set register afs1
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 43 port c pc0 reserved afs1[0]: 0 ana4/cinp/led drive adc or comparator input, or led drive afs1[0]: 1 pc1 reserved afs1[1]: 0 ana5/cinn/ led drive adc or comparator input, or led drive afs1[1]: 1 pc2 reserved afs1[2]: 0 ana6/led/ vref* adc analog input or led drive or adc voltage reference afs1[2]: 1 pc3 cout comparator output afs1[3]: 0 led led drive afs1[3]: 1 pc4 reserved afs1[4]: 0 led led drive afs1[4]: 1 pc5 reserved afs1[5]: 0 led led drive afs1[5]: 1 pc6 reserved afs1[6]: 0 led led drive afs1[6]: 1 pc7 reserved afs1[7]: 0 led led drive afs1[7]: 1 note: because there are at most two choices of alternate functi on for any pin of port c, the alternate function set register afs2 is not used to select the function. also, alternate function selection as described in port a?d alternate function sub-registers on page 47 must also be enabled. *vref is available on pc2 in 20-pin parts only. table 14. port alternate function mapping (non 8-pin parts) (continued) port pin mnemonic alternate function description alternate function set register afs1
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 44 table 15. port alternate function mapping (8-pin parts) port pin mnemonic alternate function description alternate function select register afs1 alternate function select register afs2 port a pa0 t0in timer 0 input afs1[0]: 0 afs2[0]: 0 reserved afs1[0]: 0 afs2[0]: 1 reserved afs1[0]: 1 afs2[0]: 0 t0out timer 0 output complement afs1[0]: 1 afs2[0]: 1 pa1 t0out timer 0 output afs1[1]: 0 afs2[1]: 0 reserved afs1[1]: 0 afs2[1]: 1 clkin external clock input afs1[1]: 1 afs2[1]: 0 analog functions* adc analog i nput/vref afs1[1]: 1 afs2[1]: 1 pa2 de0 uart 0 driver enable afs1[2]: 0 afs2[2]: 0 reset external reset afs1[2]: 0 afs2[2]: 1 t1out timer 1 output afs1[2]: 1 afs2[2]: 0 reserved afs1[2]: 1 afs2[2]: 1 pa3 cts0 uart 0 clear to send afs1[3]: 0 afs2[3]: 0 cout comparator output afs1[3]: 0 afs2[3]: 1 t1in timer 1 input afs1[3]: 1 afs2[3]: 0 analog functions* adc analog input/lpo input (p) afs1[3]: 1 afs2[3]: 1 pa4 rxd0 uart 0 receive data afs1[4]: 0 afs2[4]: 0 reserved afs1[4]: 0 afs2[4]: 1 reserved afs1[4]: 1 afs2[4]: 0 analog functions* adc/comparator input (n)/lpo input (n) afs1[4]: 1 afs2[4]: 1 pa5 txd0 uart 0 transmit da ta afs1[5]: 0 afs2[5]: 0 t1out timer 1 output complement afs1[5]: 0 afs2[5]: 1 reserved afs1[5]: 1 afs2[5]: 0 analog functions* adc/comparator input (p) lpo output afs1[5]: 1 afs2[5]: 1 * analog functions include adc inputs, adc refe rence, comparator inputs and lpo ports. note: also, alternate function selection as described in port a?d alternate function sub-registers on page 47 must be enabled.
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 45 gpio interrupts many of the gpio port pins can be used as interrupt sources. some port pins can be con- figured to generate an interrupt request on eith er the rising edge or falling edge of the pin input signal. other port pin interrupt sources generate an interrupt when any edge occurs (both rising and falling). see interrupt controller on page 55 for more information about interrupts using the gpio pins. gpio control register definitions four registers for each port provide access to gpio control, input data, and output data. table 16 lists these port registers. use the port a?d address and control registers together to provide access to sub-regist ers for port configuration and control. table 16. gpio port registers and sub-registers port register mnemonic port register name p x addr port a?d address register (selects sub-registers) p x ctl port a?d control register (provides access to sub-registers) p x in port a?d input data register p x out port a?d output data register port sub-register mnemonic port register name p x dd data direction p x af alternate function p x oc output control (open-drain) p x hde high drive enable p x smre stop mode recovery source enable p x pue pull-up enable pxafs1 alternate function set 1 pxafs2 alternate function set 2
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 46 port a?d address registers the port a?d address registers select the gp io port functionality accessible through the port a?d control registers. the port a?d address and control registers combine to pro- vide access to all gpio port controls ( table 17 ). paddr[7:0]?port address the port address selects one of the sub-regi sters accessible through the port control reg- ister. port a?d control registers the port a?d control registers set the gpio port operation. the value in the correspond- ing port a?d address register determines which sub-register is read from or written to by a port a?d control register transaction ( table 18 ). table 17. port a?d gpio address registers (p x addr) bits 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd0h, fd4h, fd8h, fdch paddr[7:0] port control sub-register accessible using the port a?d control registers 00h no function. provides some protection against accidental port reconfiguration. 01h data direction. 02h alternate function. 03h output control (open-drain). 04h high drive enable. 05h stop mode recove ry source enable. 06h pull-up enable. 07h alternate function set 1. 08h alternate function set 2. 09h?ffh no function.
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 47 pctl[7:0]?port control the port control register provides access to a ll sub-registers that configure the gpio port operation. port a?d data direction sub-registers the port a?d data direction sub-register is accessed through the port a?d control register by writing 01h to the port a?d address register ( table 19 ). dd[7:0]?data direction these bits control the direction of the ass ociated port pin. port alternate function operation overrides the data direction register setting. 0 = output. data in the port a?d output da ta register is driven onto the port pin. 1 = input. the port pin is sampled and the va lue written into the port a?d input data reg- ister. the output driver is tristated. port a?d alternate fu nction sub-registers the port a?d alternate fu nction sub-register ( table 20 ) is accessed through the port a?d control register by writing 02h to the port a?d addre ss register. the port a?d alternate function sub-registers enable the alternate function selection on pins. if dis- abled, pins functions as gpio. if enabled, se lect one of four alternate functions using alternate function set subregisters 1 and 2 as described in the port a?d alternate function table 18. port a?d control registers (pxctl) bits 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd1h, fd5h, fd9h, fddh table 19. port a?d data direction sub-registers (pxdd) bits 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 01h in port a?d address register, access ible through the port a?d control register
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 48 set 1 sub-registers on page 50, gpio alternate functions on page 38, and port a?d alternate function set 2 sub-registers on page 51 . see gpio alternate functions on page 38 to determine the alternate func tion associated with each port pin. do not enable alternate functions for gpio port pins for which there is no associated alternate function. failure to follow this guideline can result in unpredictable operation. af[7:0]?port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a?d data direction sub-register determines the direction of the pin. 1 = the alternate function se lected through alternate fu nction set sub-registers is enabled. port pin operation is co ntrolled by the alternate function. port a?d output control sub-registers the port a?d output control sub-register ( table 21 ) is accessed through the port a?d control register by writing 03h to the port a?d address regi ster. setting the bits in the port a?d output control sub-registers to 1 configures the specified port pins for open- drain operation. these sub-registers affect the pi ns directly and, as a result, alternate func- tions are also affected. poc[7:0]?port output control these bits function independently of the a lternate function bit and always disable the drains if set to 1. 0 = the source current is enabled for any outp ut mode (unless overridden by the alternate table 20. port a?d alternate function sub-registers (pxaf) bits 7 6 5 4 3 2 1 0 field af7 af6 af5 af4 af3 af2 af1 af0 reset 00h (ports a?c); 01h (port d); 04h (port a of 8-pin device) r/w r/w addr if 02h in port a?d address register, access ible through the port a?d control register table 21. port a?d output control sub-registers (pxoc) bits 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00h (ports a-c); 01h (port d) r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 03h in port a?d address register, access ible through the port a?d control register caution:
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 49 function). (push-pull output) 1 = the source current for the associated pin is disabled (open-drain mode). port a?d high drive enable sub-registers the port a?d high drive enable sub-register ( table 22 ) is accessed through the port a?d control register by writing 04h to the port a?d address register. setting the bits in the port a?d high drive enable sub-registers to 1 configures the spec ified port pins for high current output drive operation. the port a?d high drive enable sub-register affects the pins directly and, as a result, a lternate functions are also affected. phde[7:0]?port high drive enabled 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. port a?d stop mode recovery source enable sub-registers the port a?d stop mode recovery source enable sub-register ( table 23 ) is accessed through the port a?d cont rol register by writing 05h to the port a?d address register. setting the bits in the port a?d stop mode recovery source enable sub-registers to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enabled as a stop mode recovery source initiates stop mode recovery. psmre[7:0]?port stop mode recovery source enabled 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin table 22. port a?d high drive enable sub-registers (pxhde) bits 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 04h in port a?d address register, access ible through the port a?d control register table 23. port a?d stop mode recovery source enable sub-registers (pxsmre) bits 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 05h in port a?d address register, access ible through the port a?d control register
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 50 during stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mo de recovery source. an y logic transition on this pin during stop mode initiates stop mode recovery. port a?d pull-up enable sub-registers the port a?d pull-up enable sub-register ( table 24 ) is accessed through the port a?d control register by writing 06h to the port a?d address regi ster. setting the bits in the port a?d pull-up enable sub-registers enable s a weak internal resi stive pull-up on the specified port pins. ppue[7:0]?port pull-up enabled 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. port a?d alternate function set 1 sub-registers the port a?d alternate func tion set1 sub-register ( table 25 ) is accessed through the port a?d control register by writing 07h to the port a?d addres s register. the alternate function set 1 sub-registers selects the alternat e function available at a port pin. alternate functions selected by setting or clearing bits of this register are defined in gpio alternate functions on page 38. alternate function selection on port pins must also be enabled as described in port a?d alternate function sub-registers on page 47 . table 24. port a?d pull-up enable sub-registers (pxpue) bits 7 6 5 4 3 2 1 0 field ppue7 ppue6 ppue5 ppue4 ppue3 ppue2 ppue1 ppue0 reset 00h (ports a-c); 01h (port d); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 06h in port a ? d address register, accessible through the port a ? d control register table 25. port a?d alternate function set 1 sub-registers (pxafs1) bits 7 6 5 4 3 2 1 0 field pafs17 pafs16 pafs15 pafs14 pafs13 pafs12 pafs11 pafs10 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 07h in port a?d address register, access ible through the port a?d control register note:
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 51 pafs1[7:0]?port alternate function set 1 0 = port alternate function selected as defined in table 14 and table 15 on page 44. 1 = port alternate function selected as defined in table 14 and table 15 on page 44. port a?d alternate function set 2 sub-registers the port a?d alternate func tion set 2 sub-register ( table 26 ) is accessed through the port a?d control register by writing 08h to the port a?d address register. the alternate function set 2 sub-registers selects the alternat e function available at a port pin. alternate functions selected by setting or clearing bits of this register is defined in table 15 . alternate function selection on port pins must also be enabled as described in port a?d alternate function sub-registers on page 47 . pafs2[7:0]?port alternate function set 2 0 = port alternate function selected as defined in table 15 . 1 = port alternate function selected as defined in table 15 . port a?c input data registers reading from the port a?c input data registers ( table 27 ) returns the sampled values from the corresponding port pi ns. the port a?c input data registers are read-only. the value returned for any unused ports is 0. unused ports include those missing on the 8- and 28-pin packages, as well as those missing on the adc-enabled 28-pin packages. table 26. port a?d alternate function set 2 sub-registers (pxafs2) bits 7 6 5 4 3 2 1 0 field pafs27 pafs26 pafs25 pafs24 pafs23 pafs22 pafs21 pafs20 reset 00h (all ports of 20/28 pin devices); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 08h in port a?d address register, access ible through the port a?d control register table 27. port a?c input data registers (pxin) bits 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr addr fd2h, fd6h, fdah x = undefined. note:
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 52 pin[7:0]?port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). port a?d output data register the port a?d output data register ( table 28 ) controls the output data to the pins. pout[7:0]?port output data these bits contain the data to be driven to th e port pins. the values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1= drive a logical 1 (high). high value is no t driven if the drain has been disabled by setting the corresponding port outp ut control register bit to 1. led drive enable register the led drive enable register ( table 29 ) activates the controlled cu rrent drive. the port c pin must first be enabled by setting the a lternate function register to select the led function. table 28. port a?d output data register (p x out) bits 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd3h, fd7h, fdbh, fdfh table 29. led drive enable (leden) bits 7 6 5 4 3 2 1 0 field leden[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f82h
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 53 leden[7:0]?led drive enable these bits determine which port c pins are connected to an internal current sink. 0 = tristate the port c pin. 1= enable controlled current sink on the port c pin. led drive level high register the led drive level registers contain tw o control bits for each port c pin ( table 30 ). these two bits select between four programmab le drive levels. each pin is individually programmable. ledlvlh[7:0]?led level high bit {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. 00 = 3 ma 01= 7 ma 10= 13 ma 11= 20 ma led drive level low register the led drive level registers contain tw o control bits for each port c pin ( table 31 ). these two bits select between four programmab le drive levels. each pin is individually programmable. table 30. led drive level high register (ledlvlh) bits 7 6 5 4 3 2 1 0 field ledlvlh[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f83h
ps022825-0908 general-purpose input/output z8 encore! xp ? f082a series product specification 54 ledlvll[7:0]?led level low bit {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. 00 = 3 ma 01 = 7 ma 10 = 13 ma 11 = 20 ma table 31. led drive level low register (ledlvll) bits 7 6 5 4 3 2 1 0 field ledlvll[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f84h
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 55 interrupt controller the interrupt controller on the z8 encore! xp f082a series products prioritizes the inter- rupt requests from the on-chip peripherals and the gpio port pins. the features of inter- rupt controller include: ? 20 possible interrupt sources w ith 18 unique interrupt vectors: ? twelve gpio port pin interrupt sourc es (two interrupt vectors are shared). ? eight on-chip peripheral interrupt sources (two interrupt vectors are shared). ? flexible gpio interrupts: ? eight selectable rising and falling edge gpio interrupts. ? four dual-edge interrupts. ? three levels of individually programmable interrupt priority. ? watchdog timer and lvd can be confi gured to generate an interrupt. ? supports vectored as well as polled interrupts interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the cpu and the interrupting peripheral. when the service routine is completed, the cpu returns to the op eration from which it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt controller has no effect on opera tion. for more information on interrupt ser- vicing by the ez8 cpu, refer to ez8 cpu core user manual (um0128) available for download at www.zilog.com . interrupt vector listing table 32 on page 56 lists all of the interrupts av ailable in order of priority. the interrupt vector is stored with the most-significan t byte (msb) at the even program memory address and the least-significant byte ( lsb) at the following odd program memory address. some port interrupts are not available on the 8- and 20-pin packages. the adc interrupt is unavailable on devices not containing an adc. note:
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 56 table 32. trap and interrupt vectors in order of priority priority program memory vector address interrupt or trap source highest 0002h reset (not an interrupt) 0004h watchdog timer (see watchdog timer on page 91) 003ah primary oscillator fa il trap (not an interrupt) 003ch watchdog oscillator fa il trap (not an interrupt) 0006h illegal instruction trap (not an interrupt) 0008h reserved 000ah timer 1 000ch timer 0 000eh uart 0 receiver 0010h uart 0 transmitter 0012h reserved 0014h reserved 0016h adc 0018h port a pin 7, selectable risi ng or falling input edge or lvd (see reset, stop mode recovery, and low voltage detection on page 23) 001ah port a pin 6, selectable rising or falling input edge or comparator output 001ch port a pin 5, selectabl e rising or falling input edge 001eh port a pin 4, selectabl e rising or falling input edge 0020h port a pin 3, selectabl e rising or falling input edge 0022h port a pin 2, selectabl e rising or falling input edge 0024h port a pin 1, selectabl e rising or falling input edge 0026h port a pin 0, selectabl e rising or falling input edge 0028h reserved 002ah reserved 002ch reserved 002eh reserved 0030h port c pin 3, both input edges 0032h port c pin 2, both input edges
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 57 architecture figure 8 displays the interrupt controller block diagram. figure 8. interrupt controller block diagram operation master interrupt enable the master interrupt enable bit ( irqe ) in the interrupt control register globally enables and disables interrupts. 0034h port c pin 1, both input edges lowest 0036h port c pin 0, both input edges 0038h reserved table 32. trap and interrupt vectors in order of priority (continued) priority program memory vector address interrupt or trap source vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 58 interrupts are globally enabled by any of the following actions: ? execution of an ei (enable interrupt) instruction ? execution of an iret (return from interrupt) instruction ? writing a 1 to the irqe bit in the interrupt control register interrupts are globally disabled by any of the following actions: ? execution of a di (disable interrupt) instruction ? ez8 cpu acknowledgement of an interrupt service request from the interrupt controller ? writing a 0 to the irqe bit in the interrupt control register ? reset ? execution of a trap instruction ? illegal instruction trap ? primary oscillator fail trap ? watchdog oscillator fail trap interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest priority , and level 1 is the lowest priority. if all of the interrupts are enable d with identical interrupt prior ity (all as level 2 interrupts, for example), the interrupt priori ty is assigned from highest to lowest as specified in table 32 on page 56. level 3 interrupts are always assigned higher priority than level 2 interrupts which, in turn, always are assigned higher pr iority than level 1 interrupts. within each interrupt priority level (level 1, level 2, or level 3), priority is ass igned as specified in table 32 , above. reset, watchdog ti mer interrupt (if enabled) , primary oscillator fail trap, watchdog oscillator fail trap, and ille gal instruction trap always have highest (level 3) priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (sin- gle pulse). when the interrupt request is ac knowledged by the ez8 cpu, the correspond- ing bit in the interrupt request register is cl eared until the next interrupt occurs. writing a 0 to the corresponding bit in the interrupt re quest register likewise clears the interrupt request.
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 59 the following coding style that clears bits in the interru pt request registers is not recommended. all incoming interrupts re ceived between execution of the first ldx com- mand and the final ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 and r0, mask ldx irq0, r0 to avoid missing interrupts, use the followi ng coding style to clear bits in the interrupt request 0 register: good coding style that avoids lost interrupt requests: andx irq0, mask software interrupt assertion program code can generate interrupts directly. writing a 1 to the correct bit in the interrupt request register triggers an interrupt (assumi ng that interrupt is enabled). when the inter- rupt request is acknowledged by the ez8 cpu, the bit in the interrupt request register is automatically cleared to 0. the following coding style used to generate software interrupts by setting bits in the interrupt request registers is not recommended. all inco ming interrupts received be- tween execution of the first ldx command and the final ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 or r0, mask ldx irq0, r0 to avoid missing interrupts, use the following coding style to set bits in the interrupt request registers: good coding style that avoids lost interrupt requests: orx irq0, mask watchdog timer interrupt assertion the watchdog timer interrupt behavior is different from interrupts generated by other sources. the watchdog timer continues to assert an interru pt as long as the timeout condition continues. as it operates on a differ ent (and usually slowe r) clock domain than the rest of the device, the wa tchdog timer continues to as sert this interrupt for many system clocks until the counter rolls over. caution: caution: caution: caution:
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 60 to avoid re-triggerings of the watchdog ti mer interrupt after exiting the associated interrupt service routine, it is recommended that the service routine continues to read from the rststat register until the wdt bit is cleared as given in the following coding sample: clearwdt: ldx r0, rststat ; read reset status register to clear wdt bit btjnz 5, r0, clearwdt ; loop until bit is cleared interrupt control re gister definitions for all interrupts other than the watchdog timer interrupt, the primary oscillator fail trap, and the watchdog osc illator fail trap, the interrupt control registers enable individual interrupts, set interrupt prio rities, and indicate interrupt requests. interrupt request 0 register the interrupt request 0 (irq0) register ( table 33 ) stores the interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq0 register beco mes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 0 register to determine if any interrupt requests are pending. reserved?must be 0. t1i?timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. t0i?timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting service. table 33. interrupt request 0 register (irq0) bits 7 6 5 4 3 2 1 0 field reserved t1i t0i u0rxi u0txi reserved reserved adci reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc0h caution:
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 61 u0rxi?uart 0 receiver interrupt request 0 = no interrupt request is pe nding for the uart 0 receiver. 1 = an interrupt request from the ua rt 0 receiver is awaiting service. u0txi?uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. 1 = an interrupt request from the ua rt 0 transmitter is awaiting service. adci?adc interrupt request 0 = no interrupt request is pending for the analog-to-digital converter. 1 = an interrupt request from the analog-t o-digital converter is awaiting service. interrupt request 1 register the interrupt request 1 (irq1) register ( table 34 ) stores interrupt requ ests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq1 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending. pa 7v i?port a pin 7 or lvd interrupt request 0 = no interrupt request is pending for gpio port a or lvd. 1 = an interrupt request from gpio port a or lvd. pa6ci?port a pin 6 or comparator interrupt request 0 = no interrupt request is pendin g for gpio port a or comparator. 1 = an interrupt request from gpio port a or comparator. pa x i?port a pin x interrupt request 0 = no interrupt request is pending for gpio port a pin x . 1 = an interrupt request from gpio port a pin x is awaiting service. where x indicates the specific gp io port pin number (0?5). table 34. interrupt request 1 register (irq1) bits 7 6 5 4 3 2 1 0 field pa7vi pa6ci pa5i pa4i pa3i pa2i pa1i pa0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc3h
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 62 interrupt request 2 register the interrupt request 2 (irq2) register ( table 35 ) stores interrupt requ ests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq2 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 2 register to determine if any interrupt requests are pending. reserved?must be 0. pc x i?port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . 1 = an interrupt request from gpio port c pin x is awaiting service. where x indicates the specific gpio port c pin number (0?3). irq0 enable high and low bit registers table 36 describes the priority control for ir q0. the irq0 enable high and low bit registers ( table 37 and table 38 ) form a priority encoded en abling for interrupts in the interrupt request 0 register. table 35. interrupt request 2 register (irq2) bits 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc6h table 36. irq0 enable and priority encoding irq0enh[ x ] irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 1 1 level 3 high where x indicates the register bits from 0?7.
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 63 reserved?must be 0. t1enh?timer 1 interrupt re quest enable high bit t0enh?timer 0 interrupt re quest enable high bit u0renh?uart 0 receive interrupt request enable high bit u0tenh?uart 0 transmit interrupt request enable high bit adcenh?adc interrupt request enable high bit reserved?must be 0. t1enl?timer 1 interrupt request enable low bit t0enl?timer 0 interrupt request enable low bit u0renl?uart 0 receive interru pt request enable low bit u0tenl?uart 0 transmit interrupt request enable low bit adcenl?adc interrupt request enable low bit irq1 enable high and low bit registers table 39 describes the priority control for ir q1. the irq1 enable high and low bit registers ( table 40 and table 41 ) form a priority encoded en abling for interrupts in the interrupt request 1 register. table 37. irq0 enable high bit register (irq0enh) bits 7 6 5 4 3 2 1 0 field reserved t1enh t0enh u0renh u0tenh reserved reserved adcenh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc1h table 38. irq0 enable low bit register (irq0enl) bits 7 6 5 4 3 2 1 0 field reserved t1enl t0enl u0renl u0 tenl reserved reserved adcenl reset 00000000 r/w r r/w r/w r/w r/w r r r/w addr fc2h
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 64 pa7venh?port a bit[7] or lvd in terrupt request enable high bit pa6cenh?port a bit[7] or comparator interrupt request enable high bit pa x enh?port a bit[ x ] interrupt request enable high bit see shared interrupt select (irqss) register for selection of either the lvd or the comparator as the interrupt source. pa7venl?port a bit[7] or lvd interrupt request enable low bit pa6cenl?port a bit[6] or comparator interrupt request enable low bit pa x enl?port a bit[ x ] interrupt reques t enable low bit table 39. irq1 enable and priority encoding irq1enh[ x ] irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 1 1 level 3 high where x indicates the register bits from 0?7. table 40. irq1 enable high bit register (irq1enh) bits 7 6 5 4 3 2 1 0 field pa7venh pa6cenh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc4h table 41. irq1 enable low bit register (irq1enl) bits 7 6 5 4 3 2 1 0 field pa7venl pa6cenl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc5h
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 65 irq2 enable high and low bit registers table 42 describes the priority control for ir q2. the irq2 enable high and low bit registers ( table 43 and table 44 ) form a priority encoded en abling for interrupts in the interrupt request 2 register. reserved?must be 0. c3enh?port c3 interrupt request enable high bit c2enh?port c2 interrupt request enable high bit c1enh?port c1 interrupt request enable high bit c0enh?port c0 interrupt request enable high bit table 42. irq2 enable and priority encoding irq2enh[ x ] irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 1 1 level 3 high where x indicates the register bits from 0?7. table 43. irq2 enable high bit register (irq2enh) bits 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc7h table 44. irq2 enable low bit register (irq2enl) bits 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc8h
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 66 reserved?must be 0. c3enl?port c3 interrupt request enable low bit c2enl?port c2 interrupt request enable low bit c1enl?port c1 interrupt request enable low bit c0enl?port c0 interrupt request enable low bit interrupt edge select register the interrupt edge sele ct (irqes) register ( table 45 ) determines whether an interrupt is generated for the rising edge or falling edge on the selected gpio port a input pin. ies x ?interrupt edge select x 0 = an interrupt request is genera ted on the falling edge of the pa x input. 1 = an interrupt request is genera ted on the rising edge of the pa x input. where x indicates the specific gpio port pin number (0 through 7). shared interrupt select register the shared interrupt select (irqss) register ( table 46 ) determines the source of the padxs interrupts. the shared interrupt sele ct register selects between port a and alternate sources for the individual interrupts. because these shared interrupts are edge-trigger ed, it is possible to generate an interrupt just by switching from one shared source to another. for this reason, an interrupt must be disabled before switching between sources. table 45. interrupt edge select register (irqes) bits 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fcdh
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 67 pa7vs?pa 7 /lvd selection 0 = pa 7 is used for the interrupt for pa7vs interrupt request. 1 = the lvd is used for the inte rrupt for pa7vs interrupt request. pa6cs?pa6/comparator selection 0 = pa6 is used for the interru pt for pa6cs interrupt request. 1 = the comparator is used for the interrupt for pa6cs interrupt request. reserved?must be 0. interrupt control register the interrupt control (irqctl) register ( table 47 ) contains the master enable bit for all interrupts. irqe?interrupt request enable this bit is set to 1 by executing an ei (e nable interrupts) or iret (interrupt return) instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an interrupt request, reset or by a direct register write of a 0 to this bit. 0 = interrupts are disabled. 1 = interrupts are enabled. reserved?must be 0. table 46. shared interrupt select register (irqss) bits 7 6 5 4 3 2 1 0 field pa7vs pa6cs reserved reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fceh table 47. interrupt control register (irqctl) bits 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr addr fcfh
ps022825-0908 interrupt controller z8 encore! xp ? f082a series product specification 68
ps022825-0908 timers z8 encore! xp ? f082a series product specification 69 timers these z8 encore! xp ? f082a series products contain tw o 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (pwm) signals. the timers? feature include: ? 16-bit reload counter. ? programmable prescaler with pres cale values from 1 to 128. ? pwm output generation. ? capture and compare capability. ? external input pin for timer input, clock ga ting, or capture signal. external input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. ? timer output pin. ? timer interrupt. in addition to the timers described in this ch apter, the baud rate generator of the uart (if unused) may also provide basic timing func tionality. for information on using the baud rate generator as an additional timer, see universal asynchronous receiver/transmitter on page 97. architecture figure 9 on page 70 displays the architecture of the timers.
ps022825-0908 timers z8 encore! xp ? f082a series product specification 70 figure 9. timer block diagram operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer rolls over to 0000h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer counts up to th e 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system cl ock. upon reaching the reload value, the timer generates an interrupt and th e count value in the timer high and low byte registers is reset to 0001 h . the timer is automatica lly disabled and stops counting. 16-bit pwm/compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer block system timer data block output control bus clock input gate input capture input timer interrupt timer output complement
ps022825-0908 timers z8 encore! xp ? f082a series product specification 71 also, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high or from high to low) upon timer reload. if it is appropriate to have the timer output ma ke a state change at a one-shot time-out (rather than a single cycle pulse), first set th e tpol bit in the timer control register to the start value before enabling one-shot mode. after starting the timer, set tpol to the opposite bit value. follow the steps below for configuring a timer for one-shot mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode. ? set the prescale value. ? set the initial output level (high or lo w) if using the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in one-shot mode, the system clock always provides the timer input. the timer period is given by the following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload va lue stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the reload value, the timer generate s an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate func tion is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. follow the steps below for configuring a ti mer for continuous mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for continuous mode. one-shot mode time-out period s () reload value s tart value ? prescale system clock frequency hz () ----------------------------------------------------------------------------------------------------------------- - =
ps022825-0908 timers z8 encore! xp ? f082a series product specification 72 ? set the prescale value. ? if using the timer output alternate functio n, set the initial output level (high or low). 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this action only affects the first p ass in continuous mode. after the first timer reload in continuous mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt (if appropriate ) and set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pin (i f using the timer output function) for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in continuous mode, the system clock alwa ys provides the timer input. the timer period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equatio n to determine the first time-out period. counter mode in counter mode, the timer co unts input transitions from a gpio port pin. the timer input is taken from the gpio po rt pin timer input alternate function. the tpol bit in the timer control register selects whether the coun t occurs on the rising edge or the falling edge of the timer input signal. in c ounter mode, the prescaler is disabled. the input frequency of the timer input si gnal must not exceed one-fourth the system clock frequency. further, the high or low state of the input signal pulse must be no less than twice the system clock period. a shorter pulse may not be captured. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. continuous mode time-out period (s) reload value prescale system clock frequency (hz) ------------------------------------------------------------------------ = caution:
ps022825-0908 timers z8 encore! xp ? f082a series product specification 73 follow the steps below for configuring a timer for counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for counter mode. ? select either the rising edge or falling edge of the timer input signal for the count. this selection also sets the initial logic le vel (high or low) for the timer output alternate function. however, the timer ou tput function is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode. after the first timer reload in counter mode, counting always begins at the reset value of 0001h . in counter mode the timer high and low byte regi sters must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer. in counter mode, the number of timer input transitions since the timer start is given by the following equation: comparator counter mode in comparator counter mode , the timer counts input tr ansitions from the analog comparator output. the tpol bit in the timer control register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. in compar- ator counter mode, the prescaler is disabled. the frequency of the comparator output si gnal must not exceed one-fourth the system clock frequency. further, the high or low state of the comparator output signal pulse must be no less than twice the system clock period. a shorter pulse may not be captured. after reaching the reload value stored in th e timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. counter mode timer input tran sitions current count value - start value = caution:
ps022825-0908 timers z8 encore! xp ? f082a series product specification 74 follow the steps below for configuring a timer for comparator counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for co mparator counter mode. ? select either the rising edge or falling edge of the comparator output signal for the count. this also sets the initial logic le vel (high or low) for the timer output alternate function. however, the timer ou tput function is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this action only affects the first pass in co mparator counter mode. after the first timer reload in comparator counter mode, counting always begins at the reset value of 0001h . generally, in comparator counter mode the timer high and low byte registers mu st be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer. in comparator counter mode, the number of comparator output transitions since the timer start is given by the following equation: pwm single output mode in pwm single output mode, the timer outputs a pulse-width modulator (pwm) output signal through a gpio port pin. the timer input is the system clock. the timer first counts up to the 16-bit pwm match value st ored in the timer pwm high and low byte registers. when the timer count value matche s the pwm value, the timer output toggles. the timer continues coun ting until it reaches the reload va lue stored in th e timer reload high and low byte registers. upon reaching the reload va lue, the timer generates an interrupt, the count value in the timer hi gh and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer re aches the reload value and is reset to 0001h . comparator output transitions cu rrent count valu estart value ? =
ps022825-0908 timers z8 encore! xp ? f082a series product specification 75 if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . follow the steps below for configuring a timer for pwm single output mode and initiating the pwm operation: 1. write to the timer control register to: ? disable the timer. ? configure the timer for pwm single output mode. ? set the prescale value. ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equation to determine the first pwm time-out period. if tpol is set to 0, the ratio of the pwm outp ut high time to the total period is repre- sented by: if tpol is set to 1, the ratio of the pwm outp ut high time to the total period is repre- sented by: pwm period (s) reload value prescale system clock frequency (hz) ------------------------------------------------------------------------ = pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------ 100 = pwm output high time ratio (%) pwm value reload value -------------------------------- 100 =
ps022825-0908 timers z8 encore! xp ? f082a series product specification 76 pwm dual output mode in pwm dual output mode, the timer ou tputs a pulse-width modulated (pwm) output signal pair (basic pwm signal and its complement) through two gpio port pins. the timer input is the system clock. the timer first co unts up to the 16-bit pwm match value stored in the timer pwm high and low byte registers. when the timer count value matches the pwm value, the timer output t oggles. the timer con tinues counting until it reaches the reload value stored in the timer reload high and low byte registers. upon reaching the reload value, the timer generate s an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer re aches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . the timer also generates a second pwm outp ut signal timer output complement. the timer output complement is the compleme nt of the timer output pwm signal. a programmable deadband delay can be configured to time delay (0 to 128 system clock cycles) pwm output transitions on these two pins from a low to a high (inactive to active). this ensures a time gap between the deassertion of one pwm output to the assertion of its complement. follow the steps below for configuring a timer for pwm dual output mode and initi- ating the pwm operation: 1. write to the timer control register to: ? disable the timer. ? configure the timer for pwm dual outp ut mode by writing the tmode bits in the txctl1 register and the tmodehi bit in txctl0 register. ? set the prescale value. ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the pwm control register to set the pwm dead band delay value. the deadband delay must be less th an the duration of the pos itive phase of the pwm signal (as defined by the pwm high and low byte re gisters). it must also be less than the
ps022825-0908 timers z8 encore! xp ? f082a series product specification 77 duration of the negative phase of the pw m signal (as defined by the difference between the pwm registers and the timer reload registers). 5. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 6. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 7. configure the associated gpio port pin for the timer output and timer output complement alternate functio ns. the timer output comple ment function is shared with the timer input function for both tim ers. setting the timer mode to dual pwm automatically switches the function from timer in to timer out complement. 8. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation determines the first pwm time-out period. if tpol is set to 0, the ratio of the pwm outp ut high time to the total period is repre- sented by: if tpol is set to 1, the ratio of the pwm outp ut high time to the total period is repre- sented by: capture mode in capture mode, the current timer count valu e is recorded when the appropriate exter- nal timer input transition occu rs. the capture count value is written to the timer pwm high and low byte registers. the timer inpu t is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture ev ent occurs, an interrupt is generated and the timer continues counting. the inpcap bit in tx ctl0 register is set to indicate the timer interrupt is because of an input capture event. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching the reload va lue, the timer generates an interrupt and continues counting. the inpcap bit in txctl0 register clears indicating the timer interrupt is not because of an input capture event. pwm period (s) reload value x prescale system clock frequency (hz) ------------------------------------------------------------------------------- = pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------- 100 = pwm output high time ratio (%) pwm value reload value -------------------------------- 100 =
ps022825-0908 timers z8 encore! xp ? f082a series product specification 78 follow the steps below for configuring a timer for capture mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for capture mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . clearing these registers allows the software to determin e if interrupts were generated by either a capture event or a reload. if the pwm high and low byte registers still contain 0000h after the interrupt, the interru pt was generated by a reload. 5. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events. if appropri ate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: capture restart mode in capture restart mode, the current timer count value is recorded when the accept- able external timer input transition occurs. the capture count value is written to the timer pwm high and low byte registers. th e timer input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture event occurs, an interrupt is generated and the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txc tl0 register is set to indicate the timer interrupt is because of an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps022825-0908 timers z8 encore! xp ? f082a series product specification 79 0001h and counting resumes. the inpcap bit in txctl0 register is cleared to indicate the timer interrupt is not cause d by an input capture event. follow the steps below for configuring a timer for capture restart mode and initi- ating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for capture rest art mode by writing the tmode bits in the txctl1 register and the tmodehi bit in txctl0 register. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows the software to determine if interrupts were generated by either a capture event or a reload. if the pwm high and lo w byte registers still contain 0000h after the interrupt, the interrupt wa s generated by a reload. 5. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events. if appropri ate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to the 16-bit maximum compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and co unting continues (the timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) upon compare. if the timer reaches ffff h , the timer rolls over to 0000 h and continue counting. capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) -------------------------------------------------------------------------------------------------- - =
ps022825-0908 timers z8 encore! xp ? f082a series product specification 80 follow the steps below for configuring a timer for compare mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for compare mode. ? set the prescale value. ? set the initial logic level (high or low) fo r the timer output alternate function, if appropriate. 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in compare mode, the system clock always pr ovides the timer inpu t. the compare time can be calculated by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16 -bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when r eaching the relo ad value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal remains asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. follow the steps below for configuring a timer for gated mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for gated mode. ? set the prescale value. compare mode time (s) compare value start value ? () prescale system clock frequency (hz) ----------------------------------------------------------------------------------------------------- =
ps022825-0908 timers z8 encore! xp ? f082a series product specification 81 2. write to the timer high and low byte regist ers to set the starting count value. writing these registers only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input deassertion and reload events. if appropri ate, configure the timer interrupt to be generated only at the input deassertion even t or the reload event by setting ticonfig field of the txctl0 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the acceptable transition (ri sing edge or falling edge) is set by the tpol bit in the timer control register. th e timer input is th e system clock. every subsequent acceptable transition (after the first) of the timer input signal captures the current count value. the capture valu e is written to the timer pwm high and low byte registers. when the capt ure event occurs, an interrupt is generated, the count value in the timer high and low byte registers is reset to 0001h , and counting resumes. the inpcap bit in txctl0 register is set to indicat e the timer interrupt is caused by an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl0 register is cleared to indicate the timer interrupt is not because of an input capture event. follow the steps below for configuring a timer for capture/compare mode and initi- ating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for capture/compare mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the compare value.
ps022825-0908 timers z8 encore! xp ? f082a series product specification 82 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers.by defau lt, the timer interrupt are generated for both input capture and reload events. if appropri ate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. counting begins on the first appropriate transition of the timer input signal. no interrupt is generated by this first edge. in capture/compare mode, the elapsed time from timer start to capture event can be calculated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when th e timer is enabled and the timer high byte register is read, the contents of the timer lo w byte register are placed in a holding regis- ter. a subsequent read from the timer low byte register returns the value in the holding register. this operation allows accurate read s of the full 16-bit timer count value while enabled. when the timers are not enabled, a read from the timer low byte register returns the actual value in the counter. timer pin signal operation timer output is a gpio port pin alternate function. the timer outp ut is toggled every time the counter is reloaded. the timer input can be used as a selectable counting source. it shares the same pin as the complementary timer output. when selected by the gpio alternate function registers, this pin functions as a timer input in all modes except for the dual pwm output mode. for this mode, there is no timer input available. capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) ---------------------------------------------------------------------------------------------------------------------- =
ps022825-0908 timers z8 encore! xp ? f082a series product specification 83 timer control register definitions timer 0?1 control registers time 0?1 control register 0 the timer control register 0 (txctl0) and timer control register 1 (txctl1) deter- mine the timer operating mode ( table 48 ). it also includes a programmable pwm dead- band delay, two bits to configure timer interru pt definition, and a status bit to identify if the most recent timer interrupt is caused by an input capture event. tmodehi?timer mode high bit this bit along with the tmode field in txc tl1 register determines the operating mode of the timer. this is the most significant b it of the timer mode selection value. see the txctl1 register description for details of the full timer mode decoding. ticonfig?timer interrupt configuration this field configures timer interrupt definition. 0x = timer interrupt occurs on all de fined reload, compar e and input events 10 = timer interrupt only on defi ned input capture/deassertion events 11 = timer interrupt only on defined reload/compare events reserved?must be 0. pwmd?pwm delay value this field is a programmable delay to contro l the number of system clock cycles delay before the timer output and th e timer output complement are forced to their active state. 000 = no delay 001 = 2 cycles delay 010 = 4 cycles delay 011 = 8 cycles delay 100 = 16 cycles delay 101 = 32 cycles delay table 48. timer 0?1 control register 0 (txctl0) bits 7 6 5 4 3 2 1 0 field tmodehi ticonfig reserved pwmd inpcap reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/w r addr f06h, f0eh
ps022825-0908 timers z8 encore! xp ? f082a series product specification 84 110 = 64 cycles delay 111 = 128 cycles delay inpcap?input capture event this bit indicates if the most recent timer in terrupt is caused by a timer input capture event. 0 = previous timer interrupt is not a result of timer input capture event 1 = previous timer interrupt is a result of timer input capture event timer 0?1 control register 1 the timer 0?1 control (txctl1) registers en able/disable the timers, set the prescaler value, and determine the timer operating mode ( table 49 ). ten?timer enable 0 = timer is disabled. 1 = timer enabled to count. tpol?timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. continuous mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. counter mode if the timer is enabled the timer output si gnal is complemented after timer reload. 0 = count occurs on the rising edge of the timer input signal. 1 = count occurs on the falling edge of the timer input signal. table 49. timer 0?1 control register 1 (txctl1) bits 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f07h, f0fh
ps022825-0908 timers z8 encore! xp ? f082a series product specification 85 pwm single output mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced hi gh (1) upon pwm count matc h and forced low (0) upon reload. 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload. capture mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the timer input signal. compare mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the ti mer input signal is low (0) and interrupts are generated on the rising edge of the timer input. capture/compare mode 0 = counting is started on the first rising edge of the timer input signal. the current count is captured on subsequent risi ng edges of the timer input signal. 1 = counting is started on the first falling ed ge of the timer input signal. the current count is captured on subsequent fa lling edges of the timer input signal. pwm dual output mode 0 = timer output is forced low (0) and time r output complement is forced high (1) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. when enabled, the timer output complement is forced low (0) upon pwm count match an d forced high (1) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before th e timer output and the timer output complement is fo rced to high (1). 1 = timer output is forced high (1) and ti mer output complement is forced low (0) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload.when enabled, the timer output complement is forced high (1) upon p wm count match and forced low (0) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before th e timer output and the timer output complement is fo rced to low (0).
ps022825-0908 timers z8 encore! xp ? f082a series product specification 86 capture restart mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the timer input signal. comparator counter mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. also: 0 = count is captured on the rising edge of the comparator output. 1 = count is captured on the fallin g edge of the comparator output. when the timer output alternate function txout on a gpio port pin is enabled, txout changes to whatever state the tpol bit is in.the timer does not need to be en- abled for that to happen. also, the port data direction sub register is not needed to be set to output on txout. changing the tpol bit with the timer enabled and running does not immediately change the txout. pres?prescale value the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the prescaler is reset each time the timer is disabled. this reset ensures proper clock division each time the timer is restarted. 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 tmode?timer mode this field along with the tmodehi bit in txctl0 register determines the operating mode of the timer. tmodehi is the most si gnificant bit of the timer mode selection value. the entire operating mode bits ar e expressed as {tmodehi, tmode[2:0]}. the tmodehi is bit 7 of the txctl0 register wh ile tmode[2:0] is the lower 3 bits of the txctl1 register. 0000 = one-shot mode 0001 = continuous mode 0010 = counter mode 0011 = pwm single output mode 0100 = capture mode 0101 = compare mode 0110 = gated mode 0111 = capture/compare mode caution:
ps022825-0908 timers z8 encore! xp ? f082a series product specification 87 1000 = pwm dual output mode 1001 = capture restart mode 1010 = comparator counter mode timer 0?1 high and low byte registers the timer 0?1 high and low byte (txh and txl) registers ( table 50 and table 51 ) contain the current 16-bit timer count value. when the timer is enabled, a read from txh causes the value in txl to be stored in a temporary holding register. a read from txl always returns this temporary register when the timers are enabled. when the timer is disabled, reads from txl read the register directly. writing to the timer high and low byte regist ers while the timer is enabled is not recom- mended. there are no temporary holding regist ers available for write operations, so simul- taneous 16-bit writes are not possible. if eith er the timer high or low byte registers are written during counting, the 8- bit written value is placed in the counter (high or low byte) at the next clock edge. the coun ter continues counting from the new value. th and tl?timer high and low bytes these 2 bytes, {th[7:0], tl[7:0]}, cont ain the current 16-b it timer count value. timer reload high and low byte registers the timer 0?1 reload high and low byte (txrh and txrl) registers ( table 52 and table 53 ) store a 16-bit reload value, {trh[7:0], trl[7:0]}. values written to the timer reload high byte register are stored in a te mporary holding register. when a write to the table 50. timer 0?1 high byte register (txh) bits 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f00h, f08h table 51. timer 0?1 low byte register (txl) bits 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f01h, f09h
ps022825-0908 timers z8 encore! xp ? f082a series product specification 88 timer reload low byte register occurs, the te mporary holding register value is written to the timer high byte register. this operation allows simultaneous updates of the 16-bit timer reload value. in compare mode, the timer reload high and low byte registers store the 16-bit compare value. trh and trl?timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[ 7:0]}. this value sets the maximum count value which in itiates a timer reload to 0001h . in compare mode, these two bytes form the 16-bit compare value. timer 0-1 pwm high and low byte registers the timer 0-1 pwm high and low byte (txpwmh and txpwml) registers ( table 54 and table 55 ) control pulse-width modulator (pwm ) operations. these registers also store the capture values for the capture and capture/compare modes. table 52. timer 0?1 reload high byte register (txrh) bits 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f02h, f0ah table 53. timer 0?1 reload low byte register (txrl) bits 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f03h, f0bh table 54. timer 0?1 pwm high byte register (txpwmh) bits 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f04h, f0ch
ps022825-0908 timers z8 encore! xp ? f082a series product specification 89 pwmh and pwml?pulse-width mo dulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. when a match oc curs, the pwm output changes state. the pwm output value is set by the tpol bit in the timer control register (txctl1) regis- ter. the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. table 55. timer 0?1 pwm low byte register (txpwml) bits 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f05h, f0dh
ps022825-0908 timers z8 encore! xp ? f082a series product specification 90
ps022825-0908 watchdog timer z8 encore! xp ? f082a series product specification 91 watchdog timer the watchdog timer (wdt) protects against co rrupt or unreliable software, power faults, and other system-level problems which may place the z8 encore! xp ? f082a series devices into unsuitable operating states. the features of watchdog timer include: ? on-chip rc oscillator. ? a selectable time-out response: reset or interrupt. ? 24-bit programmable time-out value. operation the watchdog timer is a one-sh ot timer that resets or inte rrupts the z8 encore! xp f082a series devices when the wdt reaches its termin al count. the watchdog timer uses a ded- icated on-chip rc oscillator as its clock source. the watchdog timer operates in only two modes: on and off. once enabled, it always co unts and must be re freshed to prevent a time-out. perform an enable by executing th e wdt instruction or by setting the wdt_ao flash option bit. the wdt_ao bit forces th e watchdog timer to operate immediately upon reset, even if a wdt inst ruction has not been executed. the watchdog timer is a 24-bit reloadable downcounter that uses three 8-bit registers in the ez8 cpu register space to set the reload value. the nominal wdt time-out period is described by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and th e typical watchdog timer rc oscillator frequency is 10 khz. the watchdog time r cannot be refresh ed after it reaches 000002h . the wdt reload value must no t be set to values below 000004h . table 56 provides information about approxim ate time-out delays for the minimum and maximum wdt reload values. table 56. watchdog timer approximate time-out delays wdt reload value (hex) wdt reload value (decimal) approximate time-out delay (with 10 khz typical wdt oscillator frequency) typical description 000004 4 400 s minimum time-out delay ffffff 16,777,215 28 minutes maximum time-out delay wdt time-out period (ms) wdt reload value 10 ---------------- -------------- ------------ =
ps022825-0908 watchdog timer z8 encore! xp ? f082a series product specification 92 watchdog timer refresh when first enabled, the watchd og timer is loaded with the value in the watchdog timer reload registers. the watchdog timer counts down to 000000h unless a wdt instruction is executed by the ez8 cpu. ex ecution of the wdt instruction causes the downcounter to be reloaded with the wdt re load value stored in the watchdog timer reload registers. counting resume s following the reload operation. when the z8 encore! xp ? f082a series devices are operating in debug mode (using the on-chip debugger), the watchdog timer is continuously refreshed to prevent any watchdog timer time-outs. watchdog timer time-out response the watchdog timer times ou t when the counter reaches 000000h . a time-out of the watchdog timer generates either an interru pt or a system reset. the wdt_res flash option bit determines the time-out response of the watchdog time r. for information on programming the wdt_res flash option bit, see flash option bits on page 153. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occu rs, the watchdog timer issues an interrupt request to the interrupt controller and sets the wdt status bit in the reset status (rststat) register (see reset status register on page 30). if interrupts are enabled, the ez8 cpu responds to the inte rrupt request by fetching the watchdog timer interrupt vector and executing code from the ve ctor address. after time-out and interrupt generation, the watchdog timer counter rolls over to its maximum value of fffffh and continues counting. the watchdog timer coun ter is not automatically returned to its reload value. the reset status (rststat) register must be read before clearing the wdt interrupt. this read clears the wdt timeout flag and prevents further wdt interrupts from immediately occurring. wdt interrupt in stop mode if configured to generate an interrupt when a time-out oc curs and the z8 encore! xp f082a series devices are in stop mode, th e watchdog timer auto matically initiates a stop mode recovery and generates an interrupt request. both the wdt status bit and the stop bit in the reset status (rststat) register are set to 1 following a wdt time-out in stop mode. for more informatio n on stop mode recovery, see reset, stop mode recov- ery, and low voltage detection on page 23. if interrupts are enabled, following completi on of the stop mode recovery the ez8 cpu responds to the interrupt request by fetching the watchdog timer interrupt vector and exe- cuting code from the vector address.
ps022825-0908 watchdog timer z8 encore! xp ? f082a series product specification 93 wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the watchdog timer forces the device into the system reset state. the wd t status bit in the reset status (rststat) register is set to 1. for more information on system reset, see reset, stop mode recovery, and low voltage detection on page 23. wdt reset in stop mode if configured to generate a reset when a time- out occurs and the device is in stop mode, the watchdog timer initiates a stop mode recovery. both the wdt status bit and the stop bit in the reset status (rststat) regist er are set to 1 following wdt time-out in stop mode. watchdog timer reload unlock sequence writing the unlock sequence to the watchdog timer (wdtctl) control register address unlocks the three watc hdog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload registers. follow th e steps below to unlock the watchdog timer reload byte registers (wdtu, wdth, and wd tl) for write access. 1. write 55 h to the watchdog timer control register (wdtctl). 2. write aa h to the watchdog timer control register (wdtctl). 3. write the watchdog timer reload upper byte register (wdtu) with the desired time-out value. 4. write the watchdog timer reload high byte register (wdth) with the desired time-out value. 5. write the watchdog timer reload low by te register (wdtl) with the desired time-out value. all three watchdog timer reload registers must be written in the order just listed. there must be no other register writes between each of these operations. if a register write occurs, the lock state machine resets and no fu rther writes can occur unless the sequence is restarted. the value in the watchdog timer re load registers is loaded into the counter when the watchdog timer is first enabled and every time a wdt instruction is executed. watchdog timer calibration due to its extremely low oper ating current, the watchdog timer oscillator is somewhat inaccurate. this variation can be corrected us ing the calibration data stored in the flash information page (see table 97 and table 98 on page 165). loading these values into the
ps022825-0908 watchdog timer z8 encore! xp ? f082a series product specification 94 watchdog timer reload registers results in a one-second timeout at room temperature and 3.3 v supply voltage. timeouts other than one second may be obtained by scaling the calibration values up or down as required. the watchdog timer accuracy still degrades as temperature and supp ly voltage vary. see table 133 on page 230 for details. watchdog timer control register definitions watchdog timer control register the watchdog timer control (wdtctl) register is a write-only control register. writing the 55h , aah unlock sequence to the wdtctl register address unlocks the three watch- dog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register . the locking mechanis m prevents spurious writes to the reload registers. this register address is shared with the read-only reset status register. wdtunlk?watchdog timer unlock the software must write the correct unlocking se quence to this register before it is allowed to modify the contents of the watchdog timer reload registers. watchdog timer reload upper, high and low byte registers the watchdog timer reload upper, high and low byte (wdtu, wdth, wdtl) regis- ters ( table 58 through table 60 ) form the 24-bit reload value that is loaded into the watch- dog timer when a wdt instruction executes . the 24-bit reload value is {wdtu[7:0], wdth[7:0], wdtl[7:0]}. writing to these registers sets the appropriate reload value. reading from these registers returns th e current watchdog timer count value. table 57. watchdog timer control register (wdtctl) bits 7 6 5 4 3 2 1 0 field wdtunlk reset xxxxxxxx r/w wwwwwwww addr ff0h x = undefined. note:
ps022825-0908 watchdog timer z8 encore! xp ? f082a series product specification 95 the 24-bit wdt reload value must not be set to a value less than 000004h . wdtu?wdt reload upper byte most-significant byte (m sb), bits[23:16], of th e 24-bit wdt reload value. wdth?wdt reload high byte middle byte, bits[15:8], of the 24-bit wdt reload value. wdtl?wdt reload low least significant byte (lsb), bits[7 :0], of the 24-bit wdt reload value. table 58. watchdog timer reload upper byte register (wdtu) bits 7 6 5 4 3 2 1 0 field wdtu reset 00h r/w r/w* addr ff1h r/w* - read returns the current wdt count value. write sets the appropriate reload value. table 59. watchdog timer reload high byte register (wdth) bits 7 6 5 4 3 2 1 0 field wdth reset 04h r/w r/w* addr ff2h r/w* - read returns the current wdt count val ue. write sets the appropriate reload value. table 60. watchdog timer reload low byte register (wdtl) bits 7 6 5 4 3 2 1 0 field wdtl reset 00h r/w r/w* addr ff3h r/w* - read returns t he current wdt count value. write sets the appropriate reload value. caution:
ps022825-0908 watchdog timer z8 encore! xp ? f082a series product specification 96
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 97 universal asynchronous receiver/transmitter the universal asynchronous re ceiver/transmitter (uart) is a full-duplex communication channel capable of handling asynchronous data transfers. the uart uses a single 8-bit data mode with selectable parity . features of the uart include: ? 8-bit asynchronous data transfer. ? selectable even- and odd-parity generation and checking. ? option of one or two stop bits. ? separate transmit and receive interrupts. ? framing, parity, overrun and break detection. ? separate transmit and receive enables. ? 16-bit baud rate generator (brg). ? selectable multiprocessor (9-bit) mode with three configurable interrupt schemes. ? baud rate generator (brg) can be configured and used as a basic 16-bit timer. ? driver enable (de) output for external bus transceivers. architecture the uart consists of three primary functional blocks: transmitter, rece iver, and baud rate generator. the uart?s transmitter and receiv er function independently, but employ the same baud rate and data format. figure 10 on page 98 displays the uart architecture.
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 98 figure 10. uart block diagram operation data format the uart always transmits and receives data in an 8-bit data format, least-significant bit first. an even or odd parity bit can be added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figure 11 and figure 12 display the asynchronous data format employed by the uart without parity and with parity, respectively. receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status register register register register baud rate generator de with address compare
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 99 figure 11. uart asynchronous data format without parity figure 12. uart asynchronous da ta format with parity transmitting data using the polled method follow the steps below to transmit data using the polled method of operation: 1. write to the uart baud rate high and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register, if multiprocessor mode is appropriate, to enable multiprocessor (9-bit) mode functions. 4. set the multiprocessor mode select ( mpen ) bit to enable mu ltiprocessor mode. 5. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission. ? set the parity enable bit ( pen ), if parity is approp riate and multiprocessor mode is not enabled, and select either even or odd parity ( psel ). ? set or clear the ctse bit to enable or disable control from the remote receiver using the cts pin. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 100 6. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 7 . if the transmit data register is full (indicated by a 0), contin ue to monitor the tdre bit until the transmit data register becomes available to receive new data. 7. write the uart control 1 register to select the outgoing address bit. 8. set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 9. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 10. make any changes to the multiprocessor bit transmitter ( mpbt ) value, if appropriate and multiprocessor mode is enabled. 11. to transmit additional bytes, return to step 5 . transmitting data using th e interrupt-driven method the uart transmitter interrupt indicates the av ailability of the transmit data register to accept new data for transmission. follow the steps below to configure the uart for inter- rupt-driven data transmission: 1. write to the uart baud rate high and low byte registers to set the appropriate baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the acceptable priority. 5. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if multiprocessor mode is appropriate. 6. set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 7. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission. ? enable parity, if appropriate and if mu ltiprocessor mode is not enabled, and select either even or odd parity. ? set or clear ctse to enable or disable control fro m the remote receiver using the cts pin. 8. execute an ei instruc tion to enable interrupts.
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 101 the uart is now configured for interrupt-d riven data transmission. because the uart transmit data register is empty, an interr upt is generated immediately. when the uart transmit interrupt is detected, the associated interrupt service routine (isr) performs the following: 1. write the uart control 1 register to selec t the multiprocessor bit for the byte to be transmitted: 2. set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 3. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 4. clear the uart transmit interrupt bit in th e applicable interrupt request register. 5. execute the iret instruction to return from the interrupt-s ervice routine and wait for the transmit data register to again become empty. receiving data using the polled method follow the steps below to configur e the uart for polled data reception: 1. write to the uart baud rate high and low byte registers to set an acceptable baud rate for the incoming data stream. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiproc essor mode functions, if appropriate. 4. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multip rocessor mode is not enabled, and select either even or odd parity. 5. check the rda bit in the uart status 0 re gister to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to step 5 . if the receive data register is empty (indicated by a 0), continue to monitor the rda bit awaiting reception of the valid data. 6. read data from the uart receive data register. if operati ng in multiprocessor (9-bit) mode, further actions may be re quired depending on the multiprocessor mode bits mpmd[1:0]. 7. return to step 4 to receive additional data.
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 102 receiving data using the interrupt-driven method the uart receiver interrupt indicates the availability of new data (as well as error conditions). follow the steps below to config ure the uart receiver for interrupt-driven operation: 1. write to the uart baud rate high and low byte registers to set the acceptable baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the acceptable priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if appropriate. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. ? set the multiprocessor mode bits, mpmd[1:0] , to select the acceptable address matching scheme. ? configure the uart to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for z8 encore! ? devices without a dma block) 7. write the device address to the address compare register (automatic multipro- cessor modes only). 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multip rocessor mode is not enabled, and select either even or odd parity. 9. execute an ei instruc tion to enable interrupts. the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associat ed interrupt service rou tine (isr) performs the following: 1. checks the uart status 0 register to dete rmine the source of the interrupt - error, break, or received data. 2. reads the data from the uart receive data register if the interrupt was because of data available. if operating in multiproc essor (9-bit) mode, further actions may be required depending on the mult iprocessor mode bits mpmd[1:0].
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 103 3. clears the uart receiver interrupt in th e applicable interrupt request register. 4. executes the iret instruction to return from the interrupt-service routine and await more data. clear to send (cts ) operation the cts pin, if enabled by the ctse bit of the uart control 0 register, performs flow control on the outgoing transmit datastream. the clear to send (cts ) input pin is sam- pled one system clock before beginning any new character transmission. to delay trans- mission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data transm ission begins. for multiple character trans- missions, this action is typically perform ed during stop bit transmission. if cts deasserts in the middle of a character transmission, the current character is sent completely. multiprocessor (9-bit) mode the uart has a multiprocessor (9-bit) mode that uses an extra (9th) bit for selec- tive communication when a number of proce ssors share a common uart bus. in multi- processor mode (also referred to as 9- bit mode), the multiprocessor bit ( mp ) is transmitted immediately following the 8-bits of data and immediately preceding the stop bit(s) as displayed in figure 13 . the character format is: figure 13. uart asynchronous multiprocessor mode data format in multiprocessor (9-bit) mode, the pari ty bit location (9th bit) becomes the multiprocessor control bit. th e uart control 1 and status 1 registers provide multi- processor (9-bit) mode control and status in formation. if an automatic address match- ing scheme is enabled, the uart address comp are register holds the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is enabled, the uart only processes frames addressed to it. the determination of whether a frame of data is addressed to the uart can be made in hardware, software or so me combination of the two, depending on the multiprocessor start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 104 configuration bits. in general, the address co mpare feature reduces the load on the cpu, because it does not require access to the uart when it receives data directed to other devices on the multi-node network. the fo llowing three multip rocessor modes are available in hardware: 1. interrupt on all address bytes. 2. interrupt on matched address bytes and correctly framed data bytes. 3. interrupt only on corre ctly framed data bytes. these modes are selected with mpmd[1:0] in the uart control 1 register. for all mul- tiprocessor modes, bit mpen of the uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0]. in this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. the interrupt service routine must manually check the addre ss byte that caused triggered the interrupt. if it matches the uart address, the software clears mpmd[0]. each new incoming byte interrupts the cpu. the software is responsib le for determining the end of the frame. it checks for the end-o f-frame by reading the mprx bit of the uart status 1 register for each incoming byte. if mprx =1, a new frame has begun. if the address of this new frame is different from the uart?s address, mpmd[0] must be set to 1 causing the uart inter- rupts to go inactive until the next address byte. if the new frame?s address matches the uart?s, the data in the new frame is processed as well. the second scheme requires th e following: set mpmd[1:0] to 10b and write the uart?s address into the uart address co mpare register. this mode introduces additional hard- ware control, interrupting only on frames that match the uart?s address. when an incoming address byte does no t match the uart?s address, it is ignored. all successive data bytes in this frame are also ignored. wh en a matching address byte occurs, an inter- rupt is issued and further inte rrupts now occur on each successi ve data byte. when the first data byte in the frame is read, the newfrm bit of the uart status 1 register is asserted. all successive data bytes have newfrm =0. when the next address byte occurs, the hard- ware compares it to the uart?s address. if th ere is a match, the interrupts continues and the newfrm bit is set for the first byte of the new frame. if there is no match, the uart ignores all incoming bytes un til the next address match. the third scheme is enable d by setting mpmd[1:0] to 11b and by writing the uart?s address into the uart address co mpare register. this mode is identical to the second scheme, except that there are no interrupts on address bytes. the first data byte of each frame remains accompanied by a newfrm assertion. external driver enable the uart provides a driver enable (de) signal for off-chip bus transceivers. this feature reduces the software overhead associat ed with using a gpio pin to control the transceiver when communicating on a mu lti-transceiver bus, such as rs-485.
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 105 driver enable is an active high signal that envelopes the entire transmitted data frame including parity and stop bits as displayed in figure 14 . the driver enable signal asserts when a byte is written to the uart transmit data register. the driver enable signal asserts at least one uart bit period and no greater than two uart bit periods before the start bit is transmitted. this allows a setup time to enable the transceiver. the driver enable signal deasserts one system clock period after the final stop bit is transmitted. this one system clock delay allows both time for da ta to clear the transc eiver before disabling it, as well as the ability to dete rmine if another character follo ws the current character. in the event of back to back char acters (new data must be writte n to the transmit data regis- ter before the previous character is completely transmitted) the de signal is not deasserted between characters. the depol bit in the uar t control register 1 sets the polarity of the driver enable signal. figure 14. uart driver enable signal ti ming (shown with 1 stop bit and parity) the driver enable to start bit setup time is calculated as follows: uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disab led, the baud rate generator can also function as a basic timer with interrupt capability. transmitter interrupts the transmitter generates a single interrupt when the transmit data register empty bit ( tdre ) is set to 1. this indicates that the tran smitter is ready to acce pt new data for trans- mission. the tdre interrupt occurs after the transmit shift register has shifted the first bit of data out. the transmit data register can now be written with the next character to start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de 1 baud rate (hz) ---------------------------------------- - ?? ?? de to start bit setup time (s) 2 baud rate (hz) ---------------------------------------- - ?? ?? ?
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 106 send. this action provides 7 bit periods of la tency to load the transmit data register before the transmit shift register completes shifting the current character. writing to the uart transmit data register clears the tdre bit to 0. receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte is received and is available in the uart receive data register. this interrupt can be disabled independently of the other receiver interrupt sources. the received data interrupt occurs after the receive character has been received and placed in the receive data register. to avoid an overrun error, software must respond to this received data available condition before the next character is completely received. in multiprocessor mode ( mpen = 1 ), the receive data interrupts are depen- dent on the multiprocessor configuration and the mo st recent address byte. ? a break is received. ? an overrun is detected. ? a data framing error is detected. uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been read, the uart st atus 0 register is updated to indicate the overrun condition (and break detect, if applicable). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error occurred, this byte may not contain valid da ta and must be ignored. the brkd bit indi- cates if the overrun was caused by a break condition on the line. after reading the status byte indicating an overrun error, the receive data register must be read again to clear the error bits is the uart status 0 register. upda tes to the receive data register occur only when the next data word is received. uart data and error handling procedure figure 15 displays the recommended procedure for use in uart receiver interrupt service routines. note:
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 107 figure 15. uart receiver interrupt service routine flow baud rate generator interrupts if the baud rate generator (brg) interrupt enable is set, the uart receiver interrupt asserts when the uart baud rate generator reloads. this conditio n allows the baud rate generator to function as an additiona l counter if the uart functionality is not employed. uart baud rate generator the uart baud rate generator creates a lo wer frequency baud rate clock for data transmission. the input to the baud rate ge nerator is the system clock. the uart baud rate high and low byte registers combine to create a 16-bit baud rate divisor value receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 108 (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated usin g the following equation: when the uart is disabled, the baud rate generator functions as a basic 16-bit timer with interrupt on time-out. follow the steps below to configure the baud rate generator as a timer with interrupt on time-out: 1. disable the uart by clearing the ren and te n bits in the uart control 0 register to 0. 2. load the acceptable 16-bit count value into the uart ba ud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the brgctl bit in the uart control 1 register to 1. when configured as a general purpose timer, th e interrupt interval is calculated using the following equation: uart control register definitions the uart control registers support the uart and the associated infrared encoder/ decoders. for more informatio n on infrared operation, see infrared encoder/decoder on page 117. uart control 0 and co ntrol 1 registers the uart control 0 (uxctl0) and control 1 (uxctl1) registers ( table 61 and table 62 ) configure the properties of the uart?s transmit and receive operations. the uart control registers must not be written while the uart is enabled. ten?transmit enable this bit enables or di sables the transmitter. the enable is also controlled by the cts signal table 61. uart control 0 register (u0ctl0) bits 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f42h uart data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value -------------------- --------------------- --------------------- ------------------ - = interrupt interval s () system clock period (s) brg 15:0 [] =
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 109 and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled. 1 = transmitter enabled. ren?receive enable this bit enables or disables the receiver. 0 = receiver disabled. 1 = receiver enabled. ctse?cts enable 0 = the cts signal has no effect on the transmitter. 1 = the uart recognizes the cts signal as an enable control from the transmitter. pen?parity enable this bit enables or disables parity. even or odd is determined by the psel bit. 0 = parity is disabled. 1 = the transmitter sends data with an additio nal parity bit and the receiver receives an additional parity bit. psel?parity select 0 = even parity is transmitted an d expected on all received data. 1 = odd parity is transmitted an d expected on all received data. sbrk?send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending da ta before setting this bit. 0 = no break is sent. 1 = forces a break condition by setting th e output of the transmitter to zero. stop?stop bit select 0 = the transmitter sends one stop bit. 1 = the transmitter sends two stop bits. lben?loop back enable 0 = normal operation. 1 = all transmitted data is looped back to the receiver. table 62. uart control 1 register (u0ctl1) bits 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f43h
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 110 mpmd[1:0]?multip rocessor mode if multiprocessor (9-b it) mode is enabled, 00 = the uart generates an interrupt requ est on all received bytes (data and address). 01 = the uart generates an interrupt request only on received address bytes. 10 = the uart generates an interrupt reques t when a received address byte matches the value stored in the address compare register and on all successive data bytes until an address mismatch occurs. 11 = the uart generates an interrupt reques t on all received data bytes for which the most recent address byte matched the value in the address compare register. mpen?multiprocessor (9-bit) enable this bit is used to enable multiprocessor (9-bit) mode. 0 = disable multiprocessor (9-bit) mode. 1 = enable multiproce ssor (9-bit) mode. mpbt?multiprocessor bit transmit this bit is applicable only when multiproc essor (9-bit) mode is enabled. the 9th bit is used by the receiving device to determine if the data byte co ntains address or data infor- mation. 0 = send a 0 in the multipro cessor bit location of the data stream (data byte). 1 = send a 1 in the multipro cessor bit location of the data stream (address byte). depol?driver enable polarity 0 = de signal is active high. 1 = de signal is active low. brgctl?baud rate control this bit causes an alternate uart behavior de pending on the value of the ren bit in the uart control 0 register. when the uart receiver is not enabled (ren=0), this bit determines whether the baud rate generator issues interrupts. 0 = reads from the baud rate high and low byte registers return the brg reload value 1 = the baud rate generator generates a receive interrupt when it counts down to 0. reads from the baud rate high and low byte registers return the current brg count value. when the uart receiver is enabled (ren=1), this bit allows reads from the baud rate registers to return the brg count value instead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and low by te registers return the current brg count value. unlike the timers, there is no mechan ism to latch the low byte when the high byte is read. rdairq ?receive data interrupt enable 0 = received data and receiver errors generat es an interrupt request to the interrupt con- troller.
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 111 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. iren?infrared encoder/decoder enable 0 = infrared encoder/decoder is di sabled. uart operates normally. 1 = infrared encoder/decoder is enabled. the uart transmits and r eceives data through the infrared en coder/decoder. uart status 0 register the uart status 0 (uxstat0) and status 1(uxstat1) registers ( table 63 and table 64 ) identify the current uart operating configuration and status. rda?receive data available this bit indicates that the uart receive data register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty. 1 = there is a byte in the uart receive data register. pe?parity error this bit indicates that a parity error has occurred. reading the uart receive data regis- ter clears this bit. 0 = no parity error has occurred. 1 = a parity error has occurred. oe?overrun error this bit indicates that an overrun error has o ccurred. an overrun occurs when new data is received and the uart receive data register has not been read. if the rda bit is reset to 0, reading the uart receive da ta register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. fe?framing error this bit indicates that a framing error (no st op bit following data reception) was detected. reading the uart receive data register clears this bit. table 63. uart status 0 register (u0stat0) bits 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 000001 1 x r/w rrrrrr r r addr f41h
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 112 0 = no framing error occurred. 1 = a framing error occurred. brkd?break detect this bit indicates that a break occurred. if the data bits, parity/multip rocessor bit, and stop bit(s) are all 0s this bit is set to 1. readin g the uart receive data register clears this bit. 0 = no break occurred. 1 = a break occurred. tdre?transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit data register resets this bit. 0 = do not write to the uart transmit data register. 1 = the uart transmit data register is ready to receive an additional byte to be transmit- ted. txe?transmitter empty this bit indicates that the transmit shift regist er is empty and character transmission is fin- ished. 0 = data is currently transmitting. 1 = transmission is complete. cts?cts signal when this bit is read it re turns the level of the cts signal. this signal is active low. uart status 1 register this register contains multipro cessor control and status bits. reserved?must be 0. newfrm?status bit denoting the start of a new frame. reading the uart receive data register resets this bit to 0. 0 = the current byte is not the first data byte of a new frame. 1 = the current byte is the fi rst data byte of a new frame. table 64. uart status 1 register (u0stat1) bits 7 6 5 4 3 2 1 0 field reserved newfrm mprx reset 000000 0 0 r/w rrrrr/wr/wr r addr f44h
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 113 mprx?multiprocessor receive returns the value of the most recent multip rocessor bit received. reading from the uart receive data register resets this bit to 0. uart transmit data register data bytes written to the uart tr ansmit data (uxtxd) register ( table 65 ) are shifted out on the txdx pin. the write-only uart transmit data register shares a register file address with the read-only uart receive data register. txd?transmit data uart transmitter data byte to be shifted out through the txd x pin. uart receive data register data bytes received through the rxd x pin are stored in the uart receive data (uxrxd) register ( table 66 ). the read-only uart receive data register shares a regis- ter file address with the write-only uart transmit data register. rxd?receive data uart receiver data byte from the rxd x pin table 65. uart transmit data register (u0txd) bits 7 6 5 4 3 2 1 0 field txd reset xxxxxxxx r/w wwwwwwww addr f40h table 66. uart receive data register (u0rxd) bits 7 6 5 4 3 2 1 0 field rxd reset xxxxxxxx r/w rrrrrrrr addr f40h x = undefined.
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 114 uart address compare register the uart address compare (u xaddr) register stores th e multi-node network address of the uart (see table 67 ). when the mpmd[1] bit of uart control register 0 is set, all incoming address bytes are compared to the value stored in the address compare register. receive interrupts and rda assertio ns only occur in the event of a match. comp_addr?compare address this 8-bit value is compared to incoming address bytes. uart baud rate high and low byte registers the uart baud rate hi gh (uxbrh) and low byte (uxbrl) registers ( table 68 and table 69 ) combine to create a 16-bit baud rate divi sor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. table 67. uart address compare register (u0addr) bits 7 6 5 4 3 2 1 0 field comp_addr reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f45h table 68. uart baud rate high byte register (u0brh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f46h table 69. uart baud rate low byte register (u0brl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f47h
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 115 the uart data rate is calcula ted using the following equation: for a given uart data rate, calcu late the integer baud rate di visor value using the follow- ing equation: the baud rate error relative to the acceptable baud rate is calculated usin g the following equation: for reliable communication, the uart baud ra te error must never exceed 5 percent. table 70 provides information on th e data rate errors for popu lar baud rates and commonly used crystal osc illator frequencies. table 70. uart baud rates 10.0 mhz system clock 5.5296 mhz system clock acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 1 625.0 0.00 625.0 n/a n/a n/a 250.0 3 208.33 -16.67 250.0 1 345.6 38.24 115.2 5 125.0 8.51 115.2 3 115.2 0.00 57.6 11 56.8 -1.36 57.6 6 57.6 0.00 38.4 16 39.1 1.73 38.4 9 38.4 0.00 19.2 33 18.9 0.16 19.2 18 19.2 0.00 9.60 65 9.62 0.16 9.60 36 9.60 0.00 4.80 130 4.81 0.16 4.80 72 4.80 0.00 2.40 260 2.40 -0.03 2.40 144 2.40 0.00 1.20 521 1.20 -0.03 1.20 288 1.20 0.00 0.60 1042 0.60 -0.03 0.60 576 0.60 0.00 0.30 2083 0.30 0.2 0.30 1152 0.30 0.00 uart baud rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ----------------------------------------------------------------------------------------------- - = uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) ------------------------------------------------------------------------------- ?? ?? = uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate ---------------------------------------------------------------------------------------------------- ?? ?? =
ps022825-0908 universal asynchronous receiver/transmitter z8 encore! xp ? f082a series product specification 116 3.579545 mhz system clock 1.8432 mhz system clock acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 223.72 -10.51 250.0 n/a n/a n/a 115.2 2 111.9 -2.90 115.2 1 115.2 0.00 57.6 4 55.9 -2.90 57.6 2 57.6 0.00 38.4 6 37.3 -2.90 38.4 3 38.4 0.00 19.2 12 18.6 -2.90 19.2 6 19.2 0.00 9.60 23 9.73 1.32 9.60 12 9.60 0.00 4.80 47 4.76 -0.83 4.80 24 4.80 0.00 2.40 93 2.41 0.23 2.40 48 2.40 0.00 1.20 186 1.20 0.23 1.20 96 1.20 0.00 0.60 373 0.60 -0.04 0.60 192 0.60 0.00 0.30 746 0.30 -0.04 0.30 384 0.30 0.00 table 70. uart baud rates (continued)
ps022825-0908 infrared encoder/decoder z8 encore! xp ? f082a series product specification 117 infrared encoder/decoder the z8 encore! xp ? f082a series products co ntain a fully-functional, high-performance uart to infrared encode r/decoder (endec). th e infrared endec is integrated with an on-chip uart to allow easy communication be tween the z8 encore! and irda physical layer specification, ve rsion 1.3-compliant infrared transceivers. infrared communication provides secure, reliable, low-cost, po int-to-point communication between pcs, pdas, cell phones, printers , and other infrared enabled devices. architecture figure 16 displays the architecture of the infrared endec. figure 16. infrared data communication system block diagram operation when the infrared endec is en abled, the transmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infrared transceiver through the txd pin. likewise, data received from the infrared transceiver is passed to the infrared endec th rough the rxd pin, decoded by the infrared interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data infrared transceiver rxd txd baud rate clock (endec)
ps022825-0908 infrared encoder/decoder z8 encore! xp ? f082a series product specification 118 endec, and passed to the uart. commun ication is half-duplex, which means simultaneous data transmission and reception is not allowed. the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enabled to use the infrared endec. the infrared endec data rate is calculated us ing the following equation: transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16 clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16 clock period. if the data to be transmitted is 0, the transmitter first out- puts a 7 clock low period, followed by a 3 clock high pulse. finally, a 6 clock low pulse is output to complete the fu ll 16 clock data period. figure 17 displays irda data transmis- sion. when the infrared endec is enabled, the uart?s txd signal is internal to the z8 encore! xp ? f082a series products while the ir_txd signal is output through the txd pin. figure 17. infrared data transmission infrared data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------- --------------------- --------------------- ------------------- - = baud rate ir_txd uart?s 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3 clock pulse txd clock
ps022825-0908 infrared encoder/decoder z8 encore! xp ? f082a series product specification 119 receiving irda data data received from the infrare d transceiver using the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate th e demodulated signal (rxd) that drives the uart. each uart/infrared data bit is 16-clocks wide. figure 18 displays data reception. when the infrared endec is enabled, the uart?s rxd signal is internal to the z8 encore! xp ? f082a series products while the ir_rxd signal is received through the rxd pin. figure 18. irda data reception infrared data reception the system clock frequency must be at least 1.0 mhz to ensure proper reception of the 1.4 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is rese t. when the count reac hes a value of 8, the uart rxd value is updated to reflect the va lue of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the window remains open until th e count again reaches 8 (that is, 24 baud clock periods since the previous pulse was detected), giving the endec a sampling window of minus four baud rate uart?s ir_rxd 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8 clock delay clock rxd 16 clock period 16 clock period 16 clock period 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.4 s pulse caution:
ps022825-0908 infrared encoder/decoder z8 encore! xp ? f082a series product specification 120 baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. if an incoming pulse is detected inside this window th is process is repeated. if the incoming data is a logical 1 (no pulse), the endec returns to the in itial state and waits for the next falling edge. as each falling edge is detected, the endec clock counter is reset, resynchronizing the endec to th e incoming signal, allowing th e endec to tolerate jitter and baud rate errors in the incoming datastream . resynchronizing the endec does not alter the operation of the uart, which ultimately re ceives the data. the uart is only synchro- nized to the incoming data str eam when a start bit is received. infrared encoder/decoder c ontrol register definitions all infrared endec configuration and status information is set by the uart control registers as defined in universal asynchronous receiver/transmitter on page 97. to prevent spurious signals during irda dat a transmission, set the iren bit in the uart control 1 register to 1 to enable the infrared encoder/deco der before enabling the gpio port alternate func tion for the corresponding pin. caution:
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 121 analog-to-digital converter the analog-to-digital converter (adc) converts an analog input signal to its digital repre- sentation. the features of th is sigma-delta adc include: ? 11-bit resolution in differential mode. ? 10-bit resolution in single-ended mode. ? eight single-ended analog input sources ar e multiplexed with general-purpose i/o ports. ? 9 th analog input obtained from te mperature sensor peripheral. ? 11 pairs of differential inputs also mult iplexed with general-purpose i/o ports. ? low-power operational amplifier (lpo). ? interrupt on conversion complete. ? bandgap generated internal voltage re ference with two se lectable levels. ? manual in-circuit calibration is possible em ploying user code (offset calibration). ? factory calibrated for in-circuit error compensation. architecture figure 19 displays the major functional blocks of the adc. an analog multiplexer network selects the adc input from the av ailable analog pins, ana0 through ana7. the input stage of the adc allows both di fferential gain and buffering. the following input options are available: ? unbuffered input (single-ende d and differential modes). ? buffered input with unity gain (s ingle-ended and differential modes). ? lpo output with full pin acce ss to the feedback path.
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 122 figure 19. analog-to-digital converter block diagram operation data format in both single-ended and differential modes, the effective output of the adc is an 11-bit, signed, two?s complement digita l value. in differential mode, the adc temp analog input multiplexer internal voltage reference generator analog in + ref input sensor analog in - + - vref pin adc irq adc data 13 bit sigma-delta adc vrefsel 2 13 analog input multiplexer ana7 ana6 ana5 ana4 ana3 ana2 ana1 ana0 ana5 ana4 ana3 ana2 ana1 ana0 f or offset calibration anain 4 buffer amplifier + - low-power operational amplifier buffmode vrefext amplifier tristates when disabled
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 123 can output values across the entire 11 -bit range, from -1024 to +1023. in single-ended mode, the output generally ranges from 0 to +1023, but offset errors can cause small negative values. the adc registers actually return 13 bits of data, but the two lsbs are intended for com- pensation use only. when the software compensation routine is performed on the 13 bit raw adc value, two bits of reso lution are lost because of a rounding error. as a result, the final value is an 11-bit number. hardware overflow when the hardware overflow bit (ovf) is set in adc data low byte (adcd_l) register, all other data bits are invalid. the hardware ov erflow bit is set for values greater than v ref and less than -v ref (differential mode). automatic powerdown if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powe red down. from this powerdown state, the adc requires 40 system clock cycles to power up. the adc powers up when a conversion is requested by the adc control register. single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. follow the steps below for setting up the adc and initiating a single- shot conversion: 1. enable the desired analog inputs by configuring the general-purpose i/o pins for alternate analog function. this configura tion disables the digital input and output drivers. 2. write the adc control/status register 1 to configure the adc. ? write to bufmode[2:0] to select single-ended or differential mode, as well as unbuffered or buffered mode. ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refsell bit is. contained in the adc control register 0 . 3. write to the adc control register 0 to configure the adc and begin the conversion. the bit fields in the adc control regist er can be written simultaneously (the adc can be configured and enabled w ith the same write instruction): ? write to the anain[3:0] field to select from the available analog input sources (different input pins available depending on the device). ? clear cont to 0 to select a single-shot conversion.
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 124 ? if the internal voltage reference must be output to a pin, set the refext bit to 1. the internal voltage referenc e must be enabled in this case. ? write the refsell bit of the pair { refselh , refsell } to select the internal voltage reference level or to disab le the internal reference. the refselh bit is contained in the adc control/status register 1 . ? set cen to 1 to start the conversion. 4. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered-down state, the adc uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion. 5. when the conversion is complete, the adc control logic performs the following operations: ? 13-bit two?s-complement result writte n to {adcd_h[7:0], adcd_l[7:3]}. ? sends an interrupt request to the in terrupt controller denoting conversion complete. ? cen resets to 0 to indicate the conversion is complete. 6. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered-down. continuous conversion when configured for continuous conversion, the adc continuously performs an analog-to-digital conversion on the selected analog input. e ach new data value over-writes the previous value stored in the adc data registers. an in terrupt is generated after each conversion. in continuous mode, adc updates are limited by the input signal bandwidth of the adc and the latency of the adc and its digita l filter. step changes at the input are not immediately detected at the next output from the adc. the response of the adc (in all modes) is limited by the input signal bandwidth and the latency. follow the steps below for setting up the adc and initiating con tinuous conversion: 1. enable the desired analog input by configuring the general-purpose i/o pins for alternate function. this action disables the digital input and output driver. 2. write the adc control/status register 1 to configure the adc. ? write to bufmode [2:0] to select single-ended or differential mode, as well as unbuffered or buffered mode. ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disab le the internal reference. the refsell bit is contained in the adc control register 0 . caution:
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 125 3. write to the adc control register 0 to configure the adc fo r continuous conversion. the bit fields in the adc control re gister may be written simultaneously: ? write to the anain[3:0] field to select from the available analog input sources (different input pins available depending on the device). ? set cont to 1 to select continuous conversion. ? if the internal vref must be output to a pin, set the refext bit to 1. the internal voltage reference mu st be enabled in this case. ? write the refsell bit of the pair { refselh, refsell } to select the internal voltage reference level or to disable the intern al reference. the refselh bit is contained in adc control/status register 1 . ? set cen to 1 to start the conversions. 4. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation. ? an interrupt request is sent to the interrupt controller to indicate the conversion is complete. 5. the adc writes a new data result every 256 system clock cycles. for each completed conversion, the adc control logic performs the following operations: ? writes the 13-bit two?s complement result to {adcd_h[7:0], adcd_l[7:3]}. ? sends an interrupt request to the in terrupt controller denoting conversion complete. 6. to disable continuous conversion, clear the cont bit in the adc control register to 0. interrupts the adc is able to interrupt the cpu when a conversion has been completed. when the adc is disabled, no new interrupts are asserted ; however, an interrupt pending when the adc is disabled is not cleared. calibration and compensation the z8 encore! xp ? f082a series adc is factory calib rated for offset error and gain error, with the compensation data stored in flash memory. alternativ ely, you can perform your own calibration, storing the values into flash themselves. thirdly, the user code can perform a manual offset calibration during differential mode operation.
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 126 factory calibration devices that have been factory calibrated cont ain 30 bytes of calibration data in the flash option bit space. this data cons ists of 3 bytes for each inpu t mode, one for offset and two for gain correction. for a list of input modes for whic h calibration data exists, see zilog calibration data on page 161. user calibration if you have precision references available, its own external calibration can be performed using any input modes. this calibration data takes into account buffer offset and non-lin- earity, so it is recommended that this calibra tion be performed separately for each of the adc input modes planned for use. manual offset calibration when uncalibrated, the adc has significant offset (see table 135 on page 231). subse- quently, manual offset calib ration capability is built in to the block. when the adc con- trol register 0 sets the input mode ( anain[2:0] ) to manual offset calibration mode, the differential inputs to the adc are shorted together by an inter- nal switch. reading the adc value at this po int produces 0 in an id eal system. the value actually read is the adc offset. this value can be stored in non-volatile memory (see non-volatile data storage on page 169) and accessed by user code to compensate for the input offset error. there is no pr ovision for manual gain calibration. software compensation procedure using factory calibration data the value read from the adc high and low by te registers is uncompensated. the user mode software must apply gain and offset correction to this un compensated value for maximum accuracy. the following equa tion yields the compensated value: where gaincal is the gain calibration value, offcal is the offset calibration value and adc uncomp is the uncompensated value read from the adc. all values are in two?s com- plement format. the offset compensation is performed first, followed by the gain compensation. one bit of resolution is lost because of rounding on both the offset and gain computations. as a result the adc registers read back 13 b its: 1 sign bit, two calibration bits lost to rounding and 10 data bits. also note that in the second term, the mu ltiplication must be performed before the division by 2 16 . otherwise, the second term incorrectly evaluates to zero. adc comp adc uncomp offcal ? () adc uncomp offcal ? () gaincal () 2 16 ? + = note:
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 127 although the adc can be used without the ga in and offset compen sation, it does exhibit non-unity gain. designing the adc with su b-unity gain reduces noise across the adc range but requires the adc results to be scaled by a factor of 8/7. adc compensation details high efficiency assembly code that performs this compensation is av ailable for download on www.zilog.com . the following is a bit-specific d escription of the adc compensation process used by this code. the following data bit definitions are used: 0-9, a-f = bit indices in hexadecimal s = sign bit v = overflow bit - = unused input data msb lsb s b a 9 8 7 6 5 4 3 2 1 0 - - v (adc) adc output word; if v = 1, the data is invalid s 6 5 4 3 2 1 0 offset correction byte s s s s s 7 6 5 4 3 2 1 0 0 0 0 (offset) offset byte shifted to align with adc data s e d c b a 9 8 7 6 5 4 3 2 1 0 (gain) gain correction word caution:
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 128 compensation steps: 1. correct for offset adc msb adc lsb - offset msb offset lsb = #1 msb #1 lsb 2. take absolute value of the offset corrected adc value if negative ?the gain correction factor is computed assuming positive numb ers, with sign restoration afterward. #2 msb #2 lsb also take absolute value of the gain correction word if negative . again msb again lsb 3. multiply by gain correction word. if in differential mode, there are two gain correction values: one for positive adc va lues, another for negative adc values. based on the sign of #2, use the appropriate gain correction word. #2 msb #2 lsb * again msb again lsb = #3 #3 #3 #3 4. round the result and discard the least sign ificant two bytes (this is equivalent to dividing by 2 16 ). #3 #3 #3 #3 - 0x00 0x00 0x80 0x00 = #4 msb #4 lsb 5. determine sign of the gain correc tion factor using the sign bits from step 2 . if the offset corrected adc value and the gain correction word have the same sign, then the factor is positive and is left unchanged. if they have differing signs, then the factor is negative and must be multiplied by -1.
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 129 #5 msb #5 lsb 6. add the gain correction factor to the original offset corrected value. #5 msb #5 lsb + #1 msb #1 lsb = #6 msb #6 lsb 7. shift the result to the right, us ing the sign bit determined in step 1 . this allo ws for the detection of computational overflow. s-> #6 msb #6 lsb output data the following is the output form at of the corrected adc value. msb lsb s v b a 9 8 7 6 5 4 3 2 1 0 - - the overflow bit in the corrected output in dicates that the computed value was greater than the maximum logical valu e (+1023) or less than the minimum logical value (-1024). unlike the hardware overflow b it, this is not a simple binary flag. for a normal sample (non-overflow), the sign and the overflow bit matches. if the sign bit and overflow bit do not match, a computationa l overflow has occurred. input buffer stage many applications require the measurement of an input voltage source with a high output impedance. this adc provides a buffered inpu t for such situations. the drawback of the buffered input is a limitation of the input rang e. when using unity gain buffered mode, the input signal must be prevented fro m coming too close to either v ss or v dd . see table 135 on page 231 for details. this condition applie s only to the input voltage level (w ith respect to ground) of each dif- ferential input signal. the actual differential input voltage magnitude may be less than 300 mv. the input range of the unbuffered adc swings from v ss to v dd . input signals smaller than 300 mv must use the unbuffered input mode. if these signals do not contain low out- put impedances, they might require off-chip buffering. signals outside the allowable input range can be used without instability or device dam- age. any adc readings made outside the input range are su bject to greater inaccuracy than specified.
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 130 adc control register definitions adc control register 0 the adc control register 0 (adcctl0) sel ects the analog input channel and initiates the analog-to-digital conversion. it also se lects the voltage refe rence configuration. cen?conversion enable 0 = conversion is complete. writing a 0 produc es no effect. the adc automatically clears this bit to 0 when a co nversion is complete. 1 = begin conversion. writing a 1 to this bit st arts a conversion. if a conversion is already in progress, the conversion restarts. this bit remains 1 until the conversion is complete. refsell?voltage reference level select low bit; in conjunction with the high bit (refselh) in adc control/status register 1 , this determines the level of the internal voltage reference; the following details the effects of {refselh, refsell}; note that this reference is independent of the comparator reference. 00= internal reference disabled, reference comes from external pin 01= internal refere nce set to 1.0 v 10= internal reference set to 2.0 v (default) 11= reserved refout ? internal referenc e output enable 0 = reference buffer is disabled; vref pin is available for gpio or analog functions 1 = the internal adc reference is buff ered and driven out to the vref pin when the adc is used with an exter nal reference ({refselh,refsell}=00), the refout bit must be set to 0 . cont 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles (measurements of the internal temperature sensor take twice as long) 1 = continuous conversion. adc data updated every 256 system clock cycles after an initial 5129 clock conversion (measurements of th e internal temperature sensor take twice as long) table 71. adc control register 0 (adcctl0) bits 7 6 5 4 3 2 1 0 field cen refsell refout cont anain[3:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f70h warning:
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 131 anain[3:0]?analog input select these bits select the analog inpu t for conversion. not all port pins in this list are available in all packages for the z8 encore! xp ? f082a series. for information on port pins avail- able with each package style, see pin description on page 9. do not enable unavailable analog inputs. usage of these bits changes depending on the buffer mode selected in adc control/status register 1 . for the reserved values, all inpu t switches are disabled to avoid leakage or other undesir- able operation. adc samples taken with reserved bit settings are undefined. single-ended: 0000 = ana0 (transimpedance amp output when enabled) 0001 = ana1 (transimpedance amp inverting input) 0010 = ana2 (transimpedance amp non-inverting input) 0011 = ana3 0100 = ana4 0101 = ana5 0110 = ana6 0111 = ana7 1000 = reserved 1001 = reserved 1010 = reserved 1011 = reserved 1100 = hold transimpedance input nodes (ana1 and ana2) to ground. 1101 = reserved 1110 = temperature sensor. 1111 = reserved. differential (non-inverting input an d inverting input respectively): 0000 = ana0 and ana1 0001 = ana2 and ana3 0010 = ana4 and ana5 0011 = ana1 and ana0 0100 = ana3 and ana2 0101 = ana5 and ana4 0110 = ana6 and ana5 0111 = ana0 and ana2 1000 = ana0 and ana3 1001 = ana0 and ana4 1010 = ana0 and ana5 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = manual offset calibration mode
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 132 adc control/status register 1 the adc control/statu s register 1 (adcctl1) configures the input buffer stage, enables the threshold interrupts an d contains the status of both threshold triggers. it is also used to select the voltage reference configuration. refselh?voltage reference le vel select high bit; in co njunction with the low bit (refsell) in adc control register 0 , this determines the leve l of the internal voltage reference; the following details the effe cts of {refselh, refsell}; this reference is independent of the comparator reference. 00= internal reference disabled, reference comes from external pin 01= internal refere nce set to 1.0 v 10= internal reference set to 2.0 v (default) 11= reserved bufmode[2:0] - input buffer mode select 000 = single-ended, unbuffered input 001 = single-ended, buffered input with unity gain 010 = reserved 011 = reserved 100 = differential, unbuffered input 101 = differential, buffer ed input with unity gain 110 = reserved 111 = reserved adc data high byte register the adc data high byte (adcd_h) register contains the upper eight bits of the adc output. the output is an 13-bit two?s compleme nt value. during a single-shot conversion, this value is invalid. access to the adc data hi gh byte register is read-only. reading the adc data high byte regi ster latches data in th e adc low bits register. table 72. adc control/status register 1 (adcctl1) bits 7 6 5 4 3 2 1 0 field refselh reserved bufmode[2:0] reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f71h
ps022825-0908 analog-to-digital converter z8 encore! xp ? f082a series product specification 133 adcdh?adc data high byte this byte contains the upper eight bits of th e adc output. these bits are not valid during a single-shot conversion. during a continuous conversion, the most recent conversion out- put is held in this register. the se bits are undefined after a reset. adc data low byte register the adc data low byte (adcd_l) register c ontains the lower bits of the adc output as well as an overflow status bit. the output is a 13-bit two?s complement value. during a single-shot conversion, this valu e is invalid. access to the ad c data low byte register is read-only. reading the adc data high byte register latches data in the adc low bits register. adcdl?adc data low bits these bits are the least significant five bits of the 13-bits of the adc output. these bits are undefined after a reset. reserved?must be undefined. ovf?overflow status 0= a hardware overflow did not occu r in the adc for the current sample. 1= a hardware overflow did occur in the adc for the current sample, therefore the current sample is invalid. table 73. adc data high byte register (adcd_h) bits 7 6 5 4 3 2 1 0 field adcdh reset xxxxxxxx r/w rrrrrrrr addr f72h x = undefined. table 74. adc data low byte register (adcd_l) bits 7 6 5 4 3 2 1 0 field adcdl reserved ovf reset xxxxxxxx r/w rrrrrrrr addr f73h x = undefined.
ps022825-0908 low power operational amplifier z8 encore! xp ? f082a series product specification 134 low power operational amplifier overview the lpo is a general-purpose low power operatio nal amplifier. each of the three ports of the amplifier is accessible from the package pi ns. the lpo contains only one pin configu- ration: ana0 is the output/feedback node, ana1 is the inverting input and ana2 is the non-inverting input. operation to use the lpo, it must be enabled in the power control register 0 (pwrctl0) . the default state of the lpo is off. to use the lpo, the lpo bit must be cleared, turning it on ( power control register 0 (pwrctl0) on page 35). when making normal adc measurements on ana0 (measurements not invo lving the lpo output), the lpo bit must be off. turning the lpo bit on interfe res with normal adc measurements. the lpo bit enables the amplifier even in st op mode. if the amplifier is not required in stop mode, disable it. failing to perf orm this results in stop mode currents higher than necessary. as with other adc measurements, any pins u sed for analog purposes must be configured as such in the gpio registers (see port a?d alternate function sub-registers on page 47). lpo output measurements are made on ana0, as selected by the anain[3:0] bits of adc control register 0 . it is also possible to make single-ended measurements on ana1 and ana2 while the amplifier is enabled, whic h is often useful for determining offset con- ditions. differential measurements between ana0 and ana2 may be useful for noise cancellation purposes. if the lpo output is routed to the adc, then the buffmode [2:0] bits of adc control/sta- tus register 1 must also be configured for unity-g ain buffered operation. sampling the lpo in an unbuffered mode is not recommended. when either input is overdriv en, the amplifier output satura tes at the positive or negative supply voltage. no instability results. warning:
ps022825-0908 comparator z8 encore! xp ? f082a series product specification 135 comparator the z8 encore! xp ? f082a series devices feature a ge neral purpose comparator that compares two analog input sign als. these analog signals may be external stimulus from a pin (cinp and/or cinn) or internally genera ted signals. both a programmable voltage reference and the temperature sensor output vo ltage are available internally. the output is available as an interrupt source or can be routed to an external pin. figure 20. comparator block diagram operation when the positive comparator input exceeds th e negative input by more than the specified hysteresis, the output is a logic high. when the negative input ex ceeds the positive by more than the hysteresis, the output is a lo gic low. otherwise, the comparator output retains its present value. see table 137 on page 233 for details. the comparator may be powered down to reduce supply current. see power control reg- ister 0 on page 34 for details. because of the propagation delay of the comparator, it is not recommended to enable or reconfigure the comparator without first disabling interrupts and waiting for the comparator output to settle. doing so can re sult in spurious inte rrupts. the following example describes how to safe ly enable the comparator: di ld cmp0, r0 ; load some new configuration nop cinp pin temperature sensor inpsel innsel cinn pin comparator internal reference reflvl + - to cout pin to interrupt controller caution:
ps022825-0908 comparator z8 encore! xp ? f082a series product specification 136 nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei comparator control register definitions comparator control register the comparator control register (cmp0) co nfigures the comparator inputs and sets the value of the internal voltage reference. inpsel?signal select for positive input 0 = gpio pin used as positive comparator input 1 = temperature sensor used as positive comparator input innsel?signal select for negative input 0 = internal reference disabled, gpio pin used as negative comparator input 1 = internal reference enabled as negative comparator input reflvl?internal reference voltage level (t his reference is independent of the adc voltage reference). note that the 8-pin de vices contain two additional lsbs for increased resolution. for 20-/28-pin devices: 0000 = 0.0 v 0001 = 0.2 v 0010 = 0.4 v 0011 = 0.6 v 0100 = 0.8 v 0101 = 1.0 v (default) 0110 = 1.2 v 0111 = 1.4 v 1000 = 1.6 v table 75. comparator control register (cmp0) bits 7 6 5 4 3 2 1 0 field inpsel innsel reflvl reserved (20-/28-pin) reflvl (8-pin) reset 00010100 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f90h
ps022825-0908 comparator z8 encore! xp ? f082a series product specification 137 1001 = 1.8 v 1010?1111 = reserved for 8-pin devices: 000000 = 0.00 v 000001 = 0.05 v 000010 = 0.10 v 000011 = 0.15 v 000100 = 0.20 v 000101 = 0.25 v 000110 = 0.30 v 000111 = 0.35 v 001000 = 0.40 v 001001 = 0.45 v 001010 = 0.50 v 001011 = 0.55 v 001100 = 0.60 v 001101 = 0.65 v 001110 = 0.70 v 001111 = 0.75 v 010000 = 0.80 v 010001 = 0.85 v 010010 = 0.90 v 010011 = 0.95 v 010100 = 1.00 v (default) 010101 = 1.05 v 010110 = 1.10 v 010111 = 1.15 v 011000 = 1.20 v 011001 = 1.25 v 011010 = 1.30 v 011011 = 1.35 v 011100 = 1.40 v 011101 = 1.45 v 011110 = 1.50 v 011111 = 1.55 v 100000 = 1.60 v 100001 = 1.65 v 100010 = 1.70 v 100011 = 1.75 v 100100 = 1.80 v
ps022825-0908 comparator z8 encore! xp ? f082a series product specification 138
ps022825-0908 temperature sensor z8 encore! xp ? f082a series product specification 139 temperature sensor the on-chip temperature sensor allows you to measure temperature on the die with either the on-board adc or on-board comparator. this block is factory calibrated for in-circuit software correction. uncalibrated accuracy is significantly worse, therefore the tempera- ture sensor is not recomm ended for uncalibrated use. temperature sensor operation the on-chip temperature sensor is a propor tional to absolute temperature (ptat) topology. a pair of flash option bytes contai n the calibration data. the temperature sensor can be disabled by a bit in the power control register 0 on page 34 to reduce power consumption. the temperature sensor can be directly read by the adc to determine the absolute value of its output. the temperature sensor output is also available as an input to the comparator for threshold type measurement dete rmination. the accuracy of th e sensor when used with the comparator is substantially less than when measured by the adc. if the temperature sensor is routed to the adc , the adc must be configured in unity-gain buffered mode (see input buffer stage on page 129) the value read back from the adc is a signed number, although it is always positive. the sensor is factory-trimmed through the adc using the external 2.0 v reference. unless the sensor is re-trimmed for use with a differen t reference, it is most accurate when used with the external 2.0 v reference. because this sensor is an on-chip sensor it is recommended that the user account for the difference between ambient and die temper ature when inferring ambient temperature conditions. during normal operation, the die undergoes heating that causes a mismatch between the ambient temperature and that measured by the sensor. for best results, the z8 encore! xp ? device must be placed into stop mo de for sufficient time such that the die and ambient temperatures converge (this time is dependent on the thermal design of the system). the temperature sensor measureme nt must then be made immediately after recovery from stop mode. the following equation define s the transfer function betw een the temperature sensor output voltage and the die temperature. th is is needed for comparator threshold measurements. where, t is the temperature in c ; v is the sensor output in volts. v 0.01 t 0.65 + =
ps022825-0908 temperature sensor z8 encore! xp ? f082a series product specification 140 assuming a compensated adc measurement, th e following equation defines the relation- ship between the adc reading and the die temperature: where, t is the temperature in c; adc is the 10-bit compensated adc value; and tscal is the temperature sensor calibration value, ig noring the two least significant bits of the 12-bit value. see temperature sensor calibration data on page 164 for the location of tscal. calibration the temperature sensor undergoes calibration during the manufacturing process and is maximally accurate at 30 c. accuracy decr eases as measured temperatures move further from the calibration point. t25128 ? () adc tscal 11:2 [] ? () 30 + =
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 141 flash memory the products in the z8 encore! xp ? f082a series feature a non-volatile flash memory of 8 kb (8192), 4 kb (4096), 2 kb (2048 bytes), or 1 kb (1024) with read/write/ erase capability. the flash memory can be programmed and erased in-circuit by user code or through the on-chip debugger. the features include: ? user controlled read and write protec t capability ? sector-based write protection scheme ? additional protection schemes agains t accidental program and erasure architecture the flash memory array is arra nged in pages with 512 bytes per page. the 512 byte page is the minimum flash block size that can be era sed. each page is divided into 8 rows of 64 bytes. for program or data protection, the flash memory is also divided into sectors. in the z8 encore! xp f082a series, th ese sectors are either 1024 bytes (in the 8 kb devices) or 512 bytes (all other memory sizes) in size. page and sector sizes are not generally equal. the first 2 bytes of the flash program memo ry are used as flash option bits. for more information about their operation, see flash option bits on page 153. table 76 describes the flash memory configuration for each device in the z8 encore! xp f082a series. figure 21 displays the flash memory arrangement. table 76. z8 encore! xp f082a series flash memory configurations part number flash size kb (bytes) flash pages program memory addresses flash sector size (bytes) z8f08xa 8 (8192) 16 0000h?1fffh 1024 z8f04xa 4 (4096) 8 0000h?0fffh 512 z8f02xa 2 (2048) 4 0000h?07ffh 512 z8f01xa 1 (1024) 2 0000h?03ffh 512
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 142 figure 21. flash memory arrangement flash information area the flash information area is separate from program memory and is mapped to the address range fe00h to ffffh . this area is readable but can not be erased or overwritten. factory trim values for the anal og peripherals are stored here. factory calibration data for the adc is also stored here. 4 kb flash program memory 0000 01ff 0200 0fff addresses (hex) 03ff 0400 05ff 0600 07ff 0800 09ff 0a00 0bff 0c00 0dff 0e00 2 kb flash program memory 0000 addresses (hex) 07ff 05ff 0600 03ff 0400 01ff 0200 1 kb flash program memory 0000 addresses (hex) 03ff 01ff 0200 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 sector 0 sector 1 sector 0 sector 1 sector 2 sector 3 8 kb flash program memory 0000 03ff 0400 1fff addresses (hex) 07ff 0800 0bff 0c00 0fff 1000 13ff 1400 17ff 1800 1bff 1c00 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 143 operation the flash controller programs and erases fl ash memory. the flash controller provides the proper flash controls and timing for byte programming, page erase, and mass erase of flash memory. the flash controller contains several protec tion mechanisms to prevent accidental pro- gramming or erasure. these mechanism operat e on the page, sector and full-memory lev- els. the flow chart in figure 22 displays basic flash controlle r operation. the following sub- sections provide details about the various operations (lock, unlock, byte programming, page protect, page unprotect, page select , page erase, and mass erase) displayed in figure 22 .
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 144 figure 22. flash controller operation flow chart reset page 73h no yes 8ch no yes program/erase enabled 95h no yes write fctl lock state 0 lock state 1 write fctl write fctl byte program page erase write page select register write page select register page in no no unlocked protected sector? writes to page select register in lock state 1 result in a return to lock state 0 page select yes values match? yes
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 145 flash operation timing using the flash frequency registers before performing either a program or erase operation on flash memory, you must first configure the flash frequency high and lo w byte registers. the flash frequency registers allow programming and erasing of the flash with system clock frequencies ranging from 32 khz (32768 hz) through 20 mhz. the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control timing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system cl ock frequency (in khz). this value is calcu- lated using the following equation: flash programming and erasure are not supp orted for system clock frequencies below 32 khz (32768 hz) or above 20 mhz. the flash frequency high and low byte registers must be loaded with the correct value to ensure operation of the z8 encore! xp ? f082a series devices. flash code protection ag ainst external access the user code contained within the flash memory can be protected against external access by the on-chip debugger. programming the frp flash option bit prevents reading of the user code with the on-chip debugger. see flash option bits on page 153 and on-chip debugger on page 173 for more information. flash code protection against accidental program and erasure the z8 encore! xp f082a series provid es several levels of protection against accidental program and erasure of the flash me mory contents. this pr otection is provided by a combination of the flash option bits, th e register locking mech anism, the page select redundancy and the sector level protec tion control of the flash controller. flash code protection using the flash option bits the frp and fwp flash option bits combine to prov ide three levels of flash program memory protection as listed in table 77 . see flash option bits on page 153 for more information. ffreq[15:0] system clock frequency (hz) 1000 ------------------ ------------------ ----------------- ------------ - = caution:
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 146 . flash code protection using the flash controller at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory, first write the page select register with the target page. unlock the flash controlle r by making two consecutive writes to the flash control register with the values 73h and 8ch , sequentially. the page select register must be rewritten with the target page. if the two page select writes do not match, the con- troller reverts to a locked state. if the two writes match, the selected page becomes active. see figure 22 on page 144 for details. after unlocking a specific page, you can enab le either page program or erase. writing the value 95h causes a page erase only if the active page resides in a sector that is not pro- tected. any other value written to the flash co ntrol register locks the flash controller. mass erase is not allowed in the user co de but only in thro ugh the debug port. after unlocking a specific page, you can also wr ite to any byte on that page. after a byte is written, the page remains unlock ed, allowing for subsequent writes to other bytes on the same page. further writes to the flash control re gister cause the active page to revert to a locked state. sector based flash protection the final protection mechanism is implemente d on a per-sector basis. the flash memories of z8 encore! ? devices are divided into at most 8 sectors. a sector is 1/8 of the total size of the flash memory, unl ess this value is smaller than the page size, in which case the sec- tor and page sizes are equal. the sector protect register controls the prot ection state of each flash sector. this register is shared with the page select register. it is accessed by writing 73h followed by 5eh to the flash controller. the next write to the flas h control register targets the sector protect register. the sector protect register is initialized to 0 on reset, putting each sector into an unprotected state. when a bit in the sector pr otect register is writte n to 1, the correspond- ing sector is no longer written or erased by the cpu. external fl ash programming through table 77. flash code protection using the flash option bits fwp flash code protection description 0 programming and erasing disabled for all of flash program memory. in user code programming, page erase, and mass erase are all disabled. mass erase is available through the on-chip debugger. 1 programming, page erase, and mass erase are enabled for all of flash program memory.
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 147 the ocd or via the flash controller bypass mode are unaffected. after a bit of the sector protect register has been set, it cannot be cleared except by powering down the device. byte programming the flash memory is enabled for byte progr amming after unlocking the flash controller and successfully enabling either mass erase or page erase. when the flash controller is unlocked and mass erase is successfully co mpleted, all program memory locations are available for byte programming. in contrast , when the flash controller is unlocked and page erase is successfully completed, only the locations of the selected page are available for byte programming. an erased flash byte contains all 1?s ( ffh ). the programming operation can only be used to change bits fro m 1 to 0. to change a flash bit (or multiple bits) from 0 to 1 requires execution of eith er the page erase or mass erase commands. byte programming can be accomplished using the on-chip debugger's write memory command or ez8 cpu execution of the ldc or ldci instructions. refer to the ez8 cpu user manual (available for download at www.zilog.com ) for a description of the ldc and ldci instructions. while the flash contro ller programs the flash memory, the ez8 cpu idles but the system clock and on-chip peripherals continue to operate. to exit program- ming mode and lock the flash, write any va lue to the flash control register, except the mass erase or page erase commands. the byte at each address of the flash memory cannot be programmed (any bits written to 0) more than twice before an erase cy cle occurs. doing so may result in corrupted data at the target byte. page erase the flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the flash page select register identi- fies the page to be erased. only a page resi ding in an unprotected sector can be erased. with the flash controller unlocked and the active page set, writing the value 95h to the flash control register initiates the page er ase operation. while th e flash controller exe- cutes the page erase operation, the ez8 cp u idles but the system clock and on-chip peripherals continue to operate. the ez8 cpu resumes operation after the page erase operation completes. if the page erase operation is performed using the on-chip debug- ger, poll the flash status register to determin e when the page erase operation is complete. when the page erase is complete, the flash controller returns to its locked state. mass erase the flash memory can also be mass erased us ing the flash controller, but only by using the on-chip debugger. mass erasing the flas h memory sets all bytes to the value ffh . with the flash controller unlocked and the mass erase successfully enabled, writing the caution:
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 148 value 63h to the flash control register initiates the mass erase operation. while the flash controller executes the mass erase operation, the ez8 cpu idles but the system clock and on-chip peripherals continue to operate. us ing the on-chip debugger, poll the flash sta- tus register to determine wh en the mass erase operation is complete. when the mass erase is complete, the flash contro ller returns to its locked state. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster row program- ming algorithms by controlling the flash programming signals directly. row programming is recommended for gang pr ogramming applications and large volume customers who do not require in-circuit initia l programming of the flash memory. page erase operations are also supported wh en the flash controller is bypassed. for more information on bypassing the flash controller, refer to third-party flash pro- gramming support for z8 encore! ? mcu application note (an0117) available for down- load at www.zilog.com . flash controller beh avior in debug mode the following changes in behavior of the fl ash controller occur when the flash control- ler is accessed using the on-chip debugger: ? the flash write protect option bit is ignored. ? the flash sector protect register is ignored for programming and erase operations. ? programming operations are not limited to the page selected in the page select register. ? bits in the flash sector protect regi ster can be written to one or zero. ? the second write of the page select regist er to unlock the flash controller is not necessary. ? the page select register can be written when the flash controller is unlocked. ? the mass erase command is enabled th rough the flash control register. for security reasons, the flash controller allo ws only a single page to be opened for write/erase. when writing multiple flash pages, the flash controller must go through the unlock sequence again to select another page. caution:
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 149 flash control regi ster definitions flash control register the flash controller must be unlocked usin g the flash control (fctl) register before programming or erasing the fl ash memory. writing the sequence 73h 8ch , sequentially, to the flash control register unlocks the fl ash controller. when the flash controller is unlocked, the flash memory ca n be enabled for mass erase or page erase by writing the appropriate enable command to the fctl. pa ge erase applies only to the active page selected in flash page select register. mass erase is enabled only through the on-chip debugger. writing an invalid va lue or an invalid sequence re turns the flash controller to its locked state. the write-only flash contro l register shares its register file address with the read-only flash status register. fcmd?flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command (must be third co mmand in sequence to initiate page erase). 63h = mass erase command (mus t be third command in sequence to initiate mass erase). 5eh = enable flash sector protect register access table 78. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww addr ff8h
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 150 flash status register the flash status (fstat) register indicates the current state of the flash controller. this register can be read at any time. the read-only flash status register shares its register file address with the write-only flash control register. reserved?must be 0. fstat?flash controller status 000000 = flash controller locked 000001 = first unlock comm and received (73h written) 000010 = second unlock co mmand received (8ch written) 000011 = flash controller unlocked 000100 = sector protect register selected 001xxx = program operation in progress 010xxx = page erase operation in progress 100xxx = mass erase op eration in progress flash page select register the flash page select (fps) register shares address space with the flash sector protect register. unless the flash controller is unlo cked and written with 5eh, writes to this address target the flash page select register. the register is used to select one of the av ailable flash memory pages to be programmed or erased. each flash page contains 512 bytes of flash memory. during a page erase operation, all flash memory having addresses with the most significant 7 bits given by fps[6:0] are chosen fo r program/erase operation. table 79. flash status register (fstat) bits 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr addr ff8h
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 151 info_en?informat ion area enable 0 = information area us not selected. 1 = information area is selected. the inform ation area is mapped into the program mem- ory address space at addresses fe00h through ffffh . page?page select this 7-bit field identifies the flash memory page for page erase and page unlocking. program memory address[15:9] = page[6:0]. for the z8f08xx devices, the upper 3 bits must be zero. for the z8f04xx devices, the upper 4 bits must be zero. for z8f02xx devices, the upper 5 bits must always be 0. for the z8f01xx devices, the upper 6 bits must always be 0. flash sector protect register the flash sector protect (fprot) register is shared with the flash page select register. when the flash control register is written with 73h followed by 5eh, the next write to this address targets the flash sector protect re gister. in all other cases, it targets the flash page select register. this register selects one of the 8 available fl ash memory sectors to be protected. the reset state of each sector protect bit is an unprotected state. after a sector is protected by setting its corresponding register bit, it cannot be un protected (the register bit cannot be cleared) without powering down the device. table 80. flash page select register (fps) bits 7 6 5 4 3 2 1 0 field info_en page reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff9h table 81. flash sector protect register (fprot) bits 7 6 5 4 3 2 1 0 field sprot7 sprot6 sprot5 sprot4 sprot3 sprot2 sprot1 sprot0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff9h
ps022825-0908 flash memory z8 encore! xp ? f082a series product specification 152 sprot7-sprot0?sector protection each bit corresponds to a 512 byte flash secto r. for the z8f08xx devices, the upper 3 bits must be zero. for the z8f04xx devices all b its are used. for the z8f02xx devices, the upper 4 bits are unused. for the z8f01xx devices, the upper 6 bits are unused. flash frequency high and low byte registers the flash frequency high (ffreqh) and lo w byte (ffreql) registers combine to form a 16-bit value, ffreq, to control tim ing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz) and is calculated us ing the following equation: the flash frequency high and low byte registers must be loaded with the correct value to ensure proper operation of the device. al so, flash programming and erasure is not supported for system clock frequenci es below 20 khz or above 20 mhz. ffreqh?flash frequency high byte high byte of the 16-bit flash frequency value. ffreql?flash frequency low byte low byte of the 16-bit flash frequency value. table 82. flash frequency high byte register (ffreqh) bits 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffah table 83. flash frequency low byte register (ffreql) bits 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w addr ffbh ffreq[15:0] ffreqh[ 7:0],ffreql[7:0] {} system clock frequency 1000 --------------------- ------------------ ---------------- == caution:
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 153 flash option bits programmable flash option bits allow u ser configuration of certain aspects of z8 encore! xp ? f082a series operation. the feature configuration data is stored in the flash program memory and loaded into holding registers during reset. the features avail- able for control through the flash option bits include: ? watchdog timer time-out response sele ction?interrupt or system reset ? watchdog timer always on (enabled at reset) ? the ability to prevent unwanted read acce ss to user code in program memory ? the ability to prevent accident al programming and erasure of all or a portion of the user code in program memory ? voltage brownout configuration-always en abled or disabled during stop mode to reduce stop mode power consumption ? oscillator mode selection-for high, medium , and low power crystal oscillators, or external rc oscillator ? factory trimming information for the intern al precision oscillator and low voltage detection ? factory calibration values for adc, temperature sensor, and watchdog timer compensation ? factory serialization and random ized lot identifier (optional) operation option bit configuration by reset each time the flash option bits are programme d or erased, the device must be reset for the change to take effect. during any reset operation (system reset, power-on reset, or stop mode recovery), the flash option b its are automatically read from the flash program memory and written to option configuration registers. the option configuration registers control operation of the devices within the z8 encore! xp f082a series. option bit control is established befo re the device exits reset and the ez8 cpu begins code execution. the option configuration registers are not part of the register file and are not accessible for read or write access.
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 154 option bit types user option bits the user option bits are contained in the first two bytes of program memory. user access to these bits has been provided because these locations contain application-specific device configurations. the information contained here is lost when page 0 of the program mem- ory is erased. trim option bits the trim option bits are contained in the info rmation page of the flash memory. these bits are factory programmed values required to optimize the operation of onboard analog cir- cuitry and cannot be permanen tly altered. program memory may be erased without endan- gering these values. it is possible to alter working values of these bits by accessing the trim bit address and data registers, but thes e working values are lost after a power loss or any other reset event. there are 32 bytes of trim data. to modify on e of these values the user code must first write a value between 00h and 1fh into the trim bit address register. the next write to the trim bit data register changes the work ing value of the target trim data byte. reading the trim data requires the u ser code to write a value between 00h and 1fh into the trim bit address register. the next read from th e trim bit data register returns the work- ing value of the target trim data byte. the trim address range is from informati on address 20-3f only. the remainder of the information page is not accessible through the trim bit address and data registers. calibration option bits the calibration option bits are also contained in the information page. these bits are fac- tory programmed values intende d for use in software correc ting the device?s analog per- formance. to read these values, the user code must employ the ldc instruction to access the information area of the address space as defined in see flash information area on page 17. serialization bits as an optional feature, zilog ? is able to provide factory-programmed serialization. for serialized products, the individual devices are programmed with unique serial numbers. these serial numbers are binary values, four bytes in length. the numbers increase in size with each device, but gaps in the serial sequence may exist. these serial numbers are stored in the flash information page (see reading the flash information page on page 155 and serialization data on page 165 for more details) and are unaffected by mass erasure of the device's flash memory. note:
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 155 randomized lot identification bits as an optional feature, zilog is able to provide a factory-programmed random lot identifier. with this feature, all devices in a given production lot are programmed with the same random number. this random number is uniquely regenerated for each successive production lot and is not likely to be repeated. the randomized lot identifier is a 32 byte bi nary value, stored in the flash information page (see reading the flash information page on page 155 and randomized lot identifier on page 166 for more details) and is unaffe cted by mass erasure of the device's flash memory. reading the flash information page the following code example shows how to r ead data from the flash information area. ; get value at info address 60 (fe60h) ldx fps, #%80 ; enable access to flash info page ld r0, #%fe ld r1, #%60 ldc r2, @rr0 ; r2 now contains the calibration value flash option bit contro l register definitions trim bit address register the trim bit address (trmadr) register contains the target address for an access to the trim option bits ( table 84 ). table 84. trim bit address register (trmadr) bits 7 6 5 4 3 2 1 0 field trmadr - trim bit address (00h to 1fh) reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff6h
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 156 trim bit data register the trim bid data (trmdr) register contains th e read or write data for access to the trim option bits ( table 85 ). flash option bit address space the first two bytes of flash program memory at addresses 0000h and 0001h are reserved for the user-programmable flash option bits. flash program memory address 0000h wdt_res?watchdog timer reset 0 = watchdog timer time-out generates an interrupt request. interrupts must be globally enabled for the ez8 cpu to ackno wledge the interrupt request. 1 = watchdog timer time-out causes a system re set. this setting is the default for unpro- grammed (erased) flash. wdt_ao?watchdog timer always on 0 = watchdog timer is automa tically enabled upon applicat ion of system power. watch- dog timer can not be disabled. table 85. trim bit data register (trmdr) bits 7 6 5 4 3 2 1 0 field trmdr - trim bit data reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff7h table 86. flash option bits at program memory address 0000h bits 7 6 5 4 3 2 1 0 field wdt_res wdt_ao osc_sel[1:0] vbo_ao frp reserved fwp reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr program memory 0000h note: u = unchanged by reset. r/w = read/write.
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 157 1 = watchdog timer is enabled upon execution of the wdt instruction. once enabled, the watchdog timer can only be disabled by a reset or stop mode recovery. this setting is the default for unprogrammed (erased) flash. osc_sel[1:0]?oscillator mode selection 00 = on-chip oscillator configured for use with external rc networks (<4 mhz). 01 = minimum power for use with very low frequency crystals (32 khz to 1.0 mhz). 10 = medium power for use with medium frequ ency crystals or ceramic resonators (0.5 mhz to 5.0 mhz). 11 = maximum power for use with high frequen cy crystals (5.0 mhz to 20.0 mhz). this setting is the default for un programmed (erased) flash. vbo_ao?voltage brownout protection always on 0 = voltage brownout protection can be disab led in stop mode to reduce total power consumption. for the block to be disabled, the power control register bit must also be writ- ten (see power control register definitions on page 34). 1 = voltage brownout protection is always enabled including during stop mode. this setting is the default for un programmed (erased) flash. frp?flash read protect 0 = user program code is inaccessible. limite d control features are available through the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this setting is the default for un programmed (erased) flash. reserved?must be 1. fwp?flash write protect this option bit provides flash program memory protection: 0 = programming and erasure disabled for all of flash program memory. programming, page erase, and mass erase through user code is disabled. mass erase is available using the on-chip debugger. 1 = programming, page erase, and mass erase are enabled for all of flash program memory.
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 158 flash program memory address 0001h reserved?must be 1. xtldis?state of crystal oscillator at reset. this bit only enables the crystal oscillator. it s selection as system clock must be done man- ually. 0 = crystal oscillator is enabled during reset, resulting in longer reset timing 1 = crystal oscillator is disabled during reset, resu lting in shorter reset timing programming the xtldis bit to zero on 8-pin versions of this devi ce prevents any fur- ther communication via the debug pin. this is due to the fact that the xin and dbg functions are shared on pin 2 of this package. do not program this bit to zero on 8-pin devices unless no further debugging or flash programming is required. trim bit address space all available trim bit addresses and their functions are listed in table 88 through table 92 . trim bit address 0000h reserved?altering this register may result in incorrect device operation. table 87. flash options bits at program memory address 0001h bits 7 6 5 4 3 2 1 0 field reserved xtldis reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr program memory 0001h note: u = unchanged by reset. r/w = read/write. table 88. trim options bits at address 0000h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0020h note: u = unchanged by reset. r/w = read/write. note: warning:
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 159 trim bit address 0001h reserved?altering this register may result in incorrect device operation. trim bit address 0002h ipo_trim?internal precision oscillator trim byte contains trimming bits for in ternal precision oscillator. trim bit address 0003h the lvd is available on 8-pin devices only. table 89. trim option bits at 0001h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0021h note: u = unchanged by reset. r/w = read/write. table 90. trim option bits at 0002h (tipo) bits 7 6 5 4 3 2 1 0 field ipo_trim reset u r/w r/w addr information page memory 0022h note: u = unchanged by reset. r/w = read/write. table 91. trim option bits at address 0003h (tlvd) bits 7 6 5 4 3 2 1 0 field reserved lvd_trim reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0023h note: u = unchanged by reset. r/w = read/write. note:
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 160 reserved?must be 1. lvd_trim?low voltage detect trim this trimming affects the low voltage detectio n threshold. each lsb represents a 50 mv change in the threshold level. alternatively, the low voltage threshold may be computed from the options bit value by the following equation: lvd threshold (v) lvd_trim typical description 00000 3.60 maximum lvd threshold 00001 3.55 00010 3.50 00011 3.45 00100 3.40 00101 3.35 00110 3.30 00111 3.25 01000 3.20 01001 3.15 01010 3.10 default on reset 01011 3.05 01100 3.00 01101 2.95 01110 2.90 01111 2.85 10000 2.80 10001 2.75 10010 2.70 10011 to 11111 2.70 to 1.65 minimum lvd threshold lvd_lvl 3.6 v lvd_trim 0.05 v ? =
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 161 trim bit address 0004h reserved?altering this register may result in incorrect device operation. zilog calibration data adc calibration data adc_cal?analog-to-digital c onverter calibration values contains factory calibrated values for adc gain and offset compensation. each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration. these values are read by the software to compensate adc measurem ents as described in software compensation procedure using factory calibration data on page 126. the loca- tion of each calibration byte is provided in table 94 on page 162. table 92. trim option bits at 0004h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0024h note: u = unchanged by reset. r/w = read/write. table 93. adc calibration bits bits 7 6 5 4 3 2 1 0 field adc_cal reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0060h?007dh note: u = unchanged by reset. r/w = read/write.
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 162 table 94. adc calibration data location info page address memory address compensation usage adc mode reference type 60 fe60 offset single-ended unbuffered internal 2.0 v 08 fe08 gain high byte single-ended unbuffered internal 2.0 v 09 fe09 gain low byte single-ended unbuffered internal 2.0 v 63 fe63 offset single-ended unbuffered internal 1.0 v 0a fe0a gain high byte single-ended unbuffered internal 1.0 v 0b fe0b gain low byte single-ended unbuffered internal 1.0 v 66 fe66 offset single-ended unbuffered external 2.0 v 0c fe0c gain high byte single-ended unbuffered external 2.0 v 0d fe0d gain low byte single-ended unbuffered external 2.0 v 69 fe69 offset single-ended 1x buffered internal 2.0 v 0e fe0e gain high byte single-ended 1x buffered internal 2.0 v 0f fe0f gain low byte single-ended 1x buffered internal 2.0 v 6c fe6c offset single-ended 1x buffered external 2.0 v 10 fe10 gain high byte single-ended 1x buffered external 2.0 v 11 fe11 gain low byte single-ended 1x buffered external 2.0 v 6f fe6f offset differential unbuffered internal 2.0 v 12 fe12 positive gain high byte diffe rential unbuffered internal 2.0 v 13 fe13 positive gain low byte diffe rential unbuffered internal 2.0 v 30 fe30 negative gain high byte diffe rential unbuffered internal 2.0 v 31 fe31 negative gain low byte differential unbuffered internal 2.0 v 72 fe72 offset differential unbuffered internal 1.0 v 14 fe14 positive gain high byte diffe rential unbuffered internal 1.0 v 15 fe15 positive gain low byte diffe rential unbuffered internal 1.0 v 32 fe32 negative gain high byte diffe rential unbuffered internal 1.0 v 33 fe33 negative gain low byte differential unbuffered internal 1.0 v 75 fe75 offset differential unbuffered external 2.0 v 16 fe16 positive gain high byte diffe rential unbuffered external 2.0 v 17 fe17 positive gain low byte diffe rential unbuffered external 2.0 v
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 163 34 fe34 negative gain high byte differential unbuffered external 2.0 v 35 fe35 negative gain low byte differential unbuffered external 2.0 v 78 fe78 offset differential 1x buffered internal 2.0 v 18 fe18 positive gain high byte diffe rential 1x buffered internal 2.0 v 19 fe19 positive gain low byte diffe rential 1x buffered internal 2.0 v 36 fe36 negative gain high byte differential 1x buffered internal 2.0 v 37 fe37 negative gain low byte differential 1x buffered internal 2.0 v 7b fe7b offset differential 1x buffered external 2.0 v 1a fe1a positive gain high byte diffe rential 1x buffered external 2.0 v 1b fe1b positive gain low byte diffe rential 1x buffered external 2.0 v 38 fe38 negative gain high byte differential 1x buffered external 2.0 v 39 fe39 negative gain low byte differential 1x buffered external 2.0 v table 94. adc calibration data location (continued) info page address memory address compensation usage adc mode reference type
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 164 temperature sensor calibration data tscalh ? temperature sensor calibration high byte the tscalh and tscall bytes co mbine to form the 12-bit temperature sensor offset calibration value. fo r more details, see temperature sensor operation on page 139. tscall ? temperature sens or calibration low byte the tscalh and tscall bytes co mbine to form the 12-bit temperature sensor offset calibration value. fo r usage details, see temperature sensor operation on page 139. watchdog timer calibration data table 95. temperature sensor calibration high byte at 003a (tscalh) bits 7 6 5 4 3 2 1 0 field tscalh reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 003a note: u = unchanged by reset. r/w = read/write. table 96. temperature sensor calibration low byte at 003b (tscall) bits 7 6 5 4 3 2 1 0 field tscall reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 003b note: u = unchanged by reset. r/w = read/write. table 97. watchdog calibration high byte at 007eh (wdtcalh) bits 7 6 5 4 3 2 1 0 field wdtcalh reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 007eh note: u = unchanged by reset. r/w = read/write.
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 165 wdtcalh?watchdog timer calibration high byte the wdtcalh and wdtcall bytes, when lo aded into the watc hdog timer reload registers result in a one second timeout at ro om temperature and 3.3 v supply voltage. to use the watchdog timer calibra tion, user code must load wdtu with 0x00, wdth with wdtcalh and wdtl with wdtcall. wdtcall?watchdog timer calibration low byte the wdtcalh and wdtcall bytes, when lo aded into the watc hdog timer reload registers result in a one second timeout at ro om temperature and 3.3 v supply voltage. to use the watchdog timer calibra tion, user code must load wdtu with 0x00, wdth with wdtcalh and wdtl with wdtcall. serialization data s_num?serial number byte the serial number is a unique four-byte binary value. table 98. watchdog calibration low byte at 007fh (wdtcall) bits 7 6 5 4 3 2 1 0 field wdtcall reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 007fh note: u = unchanged by reset. r/w = read/write. table 99. serial number at 001c - 001f (s_num) bits 7 6 5 4 3 2 1 0 field s_num reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 001c-001f note: u = unchanged by reset. r/w = read/write.
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 166 randomized lot identifier rand_lot?randomized lot id the randomized lot id is a 32 byte binary value that changes for each production lot. table 100. serialization data locations info page address memory address usage 1c fe1c serial number byte 3 (most significant) 1d fe1d serial number byte 2 1e fe1e serial number byte 1 1f fe1f serial number byte 0 (least significant) table 101. lot identification number (rand_lot) bits 7 6 5 4 3 2 1 0 field rand_lot reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr interspersed throughout information page memory note: u = unchanged by reset. r/w = read/write. table 102. randomized lot id locations info page address memory address usage 3c fe3c randomized lot id byte 31 (most significant) 3d fe3d randomized lot id byte 30 3e fe3e randomized lot id byte 29 3f fe3f randomized lot id byte 28 58 fe58 randomized lot id byte 27 59 fe59 randomized lot id byte 26 5a fe5a randomized lot id byte 25 5b fe5b randomized lot id byte 24
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 167 5c fe5c randomized lot id byte 23 5d fe5d randomized lot id byte 22 5e fe5e randomized lot id byte 21 5f fe5f randomized lot id byte 20 61 fe61 randomized lot id byte 19 62 fe62 randomized lot id byte 18 64 fe64 randomized lot id byte 17 65 fe65 randomized lot id byte 16 67 fe67 randomized lot id byte 15 68 fe68 randomized lot id byte 14 6a fe6a randomized lot id byte 13 6b fe6b randomized lot id byte 12 6d fe6d randomized lot id byte 11 6e fe6e randomized lot id byte 10 70 fe70 randomized lot id byte 9 71 fe71 randomized lot id byte 8 73 fe73 randomized lot id byte 7 74 fe74 randomized lot id byte 6 76 fe76 randomized lot id byte 5 77 fe77 randomized lot id byte 4 79 fe79 randomized lot id byte 3 7a fe7a randomized lot id byte 2 7c fe7c randomized lot id byte 1 7d fe7d randomized lot id byte 0 (least significant) table 102. randomized lot id locations (continued) info page address memory address usage
ps022825-0908 flash option bits z8 encore! xp ? f082a series product specification 168
ps022825-0908 non-volatile data storage z8 encore! xp ? f082a series product specification 169 non-volatile data storage the z8 encore! xp ? f082a series devices contain a non-volatile data storage (nvds) element of up to 128 bytes. this memo ry can perform over 100,000 write cycles. operation the nvds is implemented by special purpose zilog ? software stored in areas of program memory, which are not user-accessible. thes e special-purpose routines use the flash memory to store the data. the routines incorporate a dynamic addressing scheme to maximize the write/erase endurance of the flash. different members of the z8 encore! xp f0 82a series feature multiple nvds array sizes. see z8 encore! xp ? f082a series family part selection guide on page 3 for details. also the members containing 8 kb of flas h memory do not include the nvds feature. nvds code interface two routines are required to access the nvds: a write routine and a read routine. both of these routines are accessed with a call instruc tion to a pre-defined address outside of the user-accessible program memory. both the nvds address and data are single-byte values. because these routines disturb the working regi ster set, user code must ensure that any required working register values are preser ved by pushing them onto the stack or by changing the working register pointer just prior to nvds execution. during both read and write accesses to the n vds, interrupt service is not disabled. any interrupts that occur during the nvds executio n must take care not to disturb the working register and existing stack contents or el se the array may become corrupted. disabling interrupts before executing nvds operations is recommended. use of the nvds requires 15 bytes of availa ble stack space. also, the contents of the working register set are overwritten. for correct nvds operation, the flash freque ncy registers must be programmed based on the system clock frequency (see flash operation timing using the flash frequency registers on page 145 ). byte write to write a byte to the nvds array, the user code must first push the ad dress, then the data byte onto the stack. th e user code issues a call instruction to the address of the byte-write routine (0x10b3). at the return from the sub-routine, the write status byte note:
ps022825-0908 non-volatile data storage z8 encore! xp ? f082a series product specification 170 resides in working register r0. the bit fiel ds of this status byte are defined in table 103 . the contents of the status byte are undefi ned for write operations to illegal addresses. also, user code must pop the addr ess and data bytes off the stack. the write routine uses 13 bytes of stack space in addition to the two bytes of address and data pushed by the user. su fficient memory must be available for this stack usage. because of the flash memory architecture, nvds writes exhibit a non-uniform execution time. in general, a write takes 251 s (assuming a 20 mhz system clock). every 400 to 500 writes, however, a maintena nce operation is necessary. in this rare occurrence, the write takes up to 61 ms to complete. slower system clock speeds result in proportionally higher execution times. nvds byte writes to invalid addresses (those exceeding the nvds array size) have no effect. illegal write operations have a 2 s execution time. reserved?must be 0. rcpy?recopy subroutine executed a recopy subroutine was executed. these oper ations take significantly longer than a normal write operation. pf?power failure indicator a power failure or system reset occurred duri ng the most recent attempted write to the nvds array. aw?address write error an address byte failure occurred during the most recent attempted write to the nvds array. dwe?data write error a data byte failure occurred during the mo st recent attempted write to the nvds array. byte read to read a byte from the nvds array, user co de must first push the address onto the stack. user code issues a call instruction to the address of th e byte-read routine (0x1000). at the return from the sub-routine, the read byte resides in work ing register r0, and the read status byte resides in working register r1. the contents of the status byte are undefined for table 103. write status byte bits 7 6 5 4 3 2 1 0 field reserved rcpy pf awe dwe default va l u e 00000000
ps022825-0908 non-volatile data storage z8 encore! xp ? f082a series product specification 171 read operations to illegal addresses. also, the user code must pop the address byte off the stack. the read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user. sufficient memory must be available for this stack usage. because of the flash memory architecture, nvds reads exhibit a non-uniform execution time. a read operation takes between 44 s and 489 s (assuming a 20 mhz system clock). slower system clock speeds result in proportionally higher execution times. nvds byte reads from invalid addresses (those exceeding the nvds array size) return 0xff. illegal read operations have a 2 s execution time. the status byte returned by the nvds read routine is zero for successful read, as determined by a crc check. if th e status byte is non-zero, there was a corrupted value in the nvds array at the location being read. in this case, the value returned in r0 is the byte most recently written to the arra y that does not have a crc error. power failure protection the nvds routines employ error checking mechanisms to ensure a power failure endangers only the most recen tly written byte. bytes previous ly written to the array are not perturbed. a system reset (such as a pin reset or watchdog timer reset) that occurs during a write operation also perturbs the byt e currently being written. all other bytes in the array are unperturbed. optimizing nvds memory usage for execution speed the nvds read time varies drastically, this di screpancy being a trade-off for minimizing the frequency of writes that require post-write page erases (see table 104 ). the nvds read time of address n is a function of the number of writes to addresses other than n since the most recent write to address n, as well as the number of writes since the most recent page erase. neglecting effects caused by page erases and results caused by the ini- tial condition in which the nvds is blank, a rule of thumb is that every write since the most recent page erase causes read times of unwritten addresses to increase by 1 s, up to a maximum of (511-nvds_size) s. table 104. nvds read time operation minimum latency maximum latency read (16 byte array) 875 9961 read (64 byte array) 876 8952
ps022825-0908 non-volatile data storage z8 encore! xp ? f082a series product specification 172 if nvds read performance is critical to your so ftware architecture, there are some things you can do to optimize your code for speed, listed in order from mo st helpful to least helpful: ? periodically refresh all addresses that are used. the optimal use of nvds in terms of speed is to rotate the writes evenly among all addresses planned to use, bringing all reads closer to the minimum read time. because the minimum read time is much less than the write time, however, actual speed benefits are not always realized. ? use as few unique addresses as possible: this helps to optimize the impact of refreshing as well as minimize the requirement for it. read (128 byte array) 883 7609 write (16 byte array) 4973 5009 write (64 byte array) 4971 5013 write (128 byte array) 4984 5023 illegal read 43 43 illegal write 31 31 table 104. nvds read time (continued) operation minimum latency maximum latency
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 173 on-chip debugger the z8 encore! xp ? f082a series devices contain an integrated on-chip debugger (ocd) that provides advanced debugging features including: ? single pin interface. ? reading and writing of the register file. ? reading and writing of program and data memory. ? setting of breakpoints and watchpoints. ? executing ez8 cpu instructions. ? debug pin sharing with general-purpose i nput-output function to maximize pins available to the user (8-pin product only). architecture the on-chip debugger consists of four primar y functional blocks: tr ansmitter, receiver, auto-baud detector/generat or, and debug controller. figure 23 displays the architecture of the on-chip debugger. figure 23. on-chip debugger block diagram auto-baud system clock transmitter receiver dbg pin debug controller ez8 tm cpu control detector/generator
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 174 operation ocd interface the on-chip debugger uses the dbg pin for co mmunication with an external host. this one-pin interface is a bi-directional, open-drain interface that transmits and receives data. data transmission is half-duplex, in that tr ansmit and receive cannot occur simultaneously. the serial data on the dbg pin is sent us ing the standard asynchronous data format defined in rs-232. this pin creates an interface from the z8 encore! xp ? f082a series products to the serial port of a host pc using minimal external hardware.two different methods for connectin g the dbg pin to an rs-232 interface are displayed in figure 24 and figure 25 . the recommended method is the buff ered implementation displayed in figure 25 . the dbg pin has a internal pull-up resist or which is sufficient for some appli- cations (for more details on the pull-up current, see electrical characteristics on page 221). for ocd operation at higher data rates or in noisy systems, an external pull-up resistor is recommended. for operation of the on-chip debugger, all power pins (v dd and av dd ) must be supplied with power, and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and may require an exter- nal pull-up resistor to ensure proper operation. figure 24. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (1) caution: rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10 kohm schottky diode
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 175 figure 25. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (2) debug mode the operating characteristics of the devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez8 cpu, unless directed by the ocd to execute specific instructions. ? the system clock operates unless in stop mode. ? all enabled on-chip peripherals operate unless in stop mode. ? automatically exits halt mode. ? constantly refreshes the wa tchdog timer, if enabled. entering debug mode the operating characteristics of th e devices entering debug mode are: ? the device enters debug mode after th e ez8 cpu executes a brk (breakpoint) instruction. ? if the dbg pin is held low during the final cl ock cycle of system re set, the part enters debug mode immediately (20-/28-pin products only). holding the dbg pin low for an additional 5000 (minimum) clock cycles after reset (making sure to account for any specified frequency error if using an internal oscillator) prevents a false interpretation of an autobaud sequence (see ocd auto-baud detector/ generator on page 176). rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10 k open-drain buffer note:
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 176 ? if the pa2/reset pin is held low while a 32-bit ke y sequence is issued to the pa0/ dbg pin, the dbg feature is unlocked. after releasing pa2/reset , it is pulled high. at this point, the pa0/dbg pin may be used to autobaud and cause the device to enter debug mode. see ocd unlock sequence (8-pin devices only) on page 178. exiting debug mode the device exits debug mode following any of these operations: ? clearing the dbgmode bit in the ocd control register to 0 ? power-on reset ? voltage brownout reset ? watchdog timer reset ? asserting the reset pin low to initiate a reset ? driving the dbg pin low while the device is in stop mode initiates a system reset ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character transmitted and received by the ocd consists of 1 start bit, 8 data bits (least-significant bit first), and 1 stop bit as displayed in figure 26 . figure 26. ocd data format when responding to a request for data, the ocd may comm ence transmitting immediately after receiving the stop bit of an incoming frame. therefore, when sending the stop bit, the host must not actively drive the dbg pin high for more than 0.5 bit times. it is recom- mended that, if possible, the host drives the dbg pin using an open drain output to avoid this issue. ocd auto-baud detector/generator to run over a range of baud rates (data b its per second) with various system clock frequencies, the on-chip debugger contains an auto-baud detector/generator. after a reset, the ocd is idle until it receives data. the ocd requires that the first character sent from the host is the character 80h . the character 80h has eight continuo us bits low (one start bit plus 7 data bits), framed between high bits. the auto-baud detector measures this period and sets the ocd ba ud rate generator accordingly. startd0d1d2d3d4d5d6d7stop note:
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 177 the auto-baud detector/generator is clocke d by the system clock. the minimum baud rate is the system clock frequency divi ded by 512. for optimal operation with asynchronous datastreams, the maximum reco mmended baud rate is the system clock frequency divided by 8. the maximum possible baud rate for asynchronous datastreams is the system clock frequency divided by 4, but th is theoretical maximum is possible only for low noise designs with clean signals. table 105 lists minimum and recommended maximum baud rates for sample crystal frequencies. if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. reconfigure the auto-baud detector/generator by sending 80h . ocd serial errors the on-chip debugger can detect any of th e following error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (ocd and host simultan eous transmission de tected by the ocd) when the ocd detects one of these errors, it aborts any command currently in progress, transmits a four character long serial brea k back to the host, and resets the auto-baud detector/generator. a framing error or tran smit collision may be caused by the host sending a serial break to the ocd. because of the open-drain natu re of the interface, returning a serial break break back to the host only extends the length of the serial break if the host releases the serial break early. the host transmits a serial break on the dbg pin when first connecting to the z8 encore! xp f082a series devices or when recovering from an error. a serial break from the host resets the auto-baud generator/detector but does not reset the ocd con- trol register. a serial break leaves the device in debug mode if that is the current mode. the ocd is held in reset until the end of the serial break when the dbg pin returns table 105. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbps) recommended standard pc baud rate (bps) minimum baud rate (kbps) 20.0 2500.0 1,843,200 39 1.0 125.0 115,200 1.95 0.032768 (32 khz) 4.096 2,400 0.064
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 178 high. because of the open-drain nature of the dbg pin, the host can send a serial break to the ocd even if the ocd is transmitting a character. ocd unlock sequence (8-pin devices only) because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the dbg pin. if this sequence is not completed during a system reset, then the pa0/ dbg pin functions only as a gpio pin. the following sequence unlocks the dbg pin: 1. hold pa2/reset low. 2. wait 5ms for the internal reset sequence to complete. 3. send the following bytes serially to the debug pin: dbg 80h (autobaud) dbg ebh dbg 5ah dbg 70h dbg cdh (32-bit unlock key) 4. release pa2/reset . the pa0/dbg pin is now identical in function to that of the dbg pin on the 20-/28-pin device. to en ter debug mode, re-autobaud and write 80h to the ocd control register (see on-chip debugger commands on page 179). between step 3 and step 4 , there is an interval during wh ich the 8-pin device is neither in reset nor debug mode. if a device ha s been erased or has not yet been programmed, all program memory bytes contain ffh . the cpu interprets this as an illegal instruction, so some irregular behavior can occur before entering debug mode, and the register values after entering de bug mode differs from their specified reset values. however, none of these irregulari ties prevent programming the flash memory. before beginning system debug, it is recommended that some legal code be programmed into the 8-pin device, and that a reset occurs. breakpoints execution breakpoints are generated using the brk instruction (opcode 00h ). when the ez8 cpu decodes a brk instruction, it signal s the on-chip debugger. if breakpoints are enabled, the ocd enters debug mode and id les the ez8 cpu. if breakpoints are not enabled, the ocd ignores the brk signal and the brk instruction operates as an nop instruction. caution:
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 179 breakpoints in flash memory the brk instruction is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the required break address, overwriting the current instruction. to remove a breakpoi nt, the corresponding page of flash memory must be erased an d reprogrammed with the original data. runtime counter the on-chip debugger contains a 16-bit run time counter. it counts system clock cycles between breakpoints. the counter starts co unting when the on-chip debugger leaves debug mode and stops counting when it ente rs debug mode again or when it reaches the maximum count of ffffh . on-chip debugger commands the host communicates to the on-chip debugger by sending ocd commands using the dbg interface. during normal operation, on ly a subset of the ocd commands are avail- able. in debug mode, all ocd commands beco me available unless the user code and control registers are protected by program ming the flash read protect option bit ( frp ). the flash read protect option bit prevents the code in memory from being read out of the z8 encore! xp f082a series products. when th is option is enabled, several of the ocd commands are disabled. table 106 on page 184 is a summary of the on-chip debugger commands. each ocd command is described in further detail in the bulleted list follow- ing this table. table 106 on page 184 also indicates those commands that operate when the device is not in debug mode (normal operation) and those commands that are disabled by programming the flash read protect option bit. debug command command byte enabled when not in debug mode? disabled by flash read protect option bit read ocd revision 00h yes ? reserved 01h ? ? read ocd status register 02h yes ? read runtime counter 03h ? ? write ocd control register 04h yes cannot clear dbgmode bit read ocd control register 05h yes ? write program counter 06h ? disabled read program counter 07h ? disabled
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 180 in the following bulleted list of ocd comman ds, data and commands sent from the host to the on-chip debugger are identified by ? dbg command/data ?. data sent from the on-chip debugger back to the host is identified by ? dbg data ? ? read ocd revision (00h) ?the read ocd revision command determines the version of the on-chip debugger. if oc d commands are added, removed, or changed, this revision number changes. dbg 00h dbg ocdrev[15:8] (major revision number) dbg ocdrev[7:0] (minor revision number) ? read ocd status register (02h) ?the read ocd status register command reads the ocdstat register. dbg 02h dbg ocdstat[7:0] ? read runtime counter (03h) ?the runtime counter co unts system clock cycles in between breakpoints. the 16-b it runtime counte r counts up from 0000h and stops at the maximum count of ffffh . the runtime counter is overwritten during the write register 08h ? only writes of the flash memory control registers are allowed. additionally, only the mass erase command is allowed to be written to the flash control register. read register 09h ? disabled write program memory 0ah ? disabled read program memory 0bh ? disabled write data memory 0ch ? yes read data memory 0dh ? ? read program memory crc 0eh ? ? reserved 0fh ? ? step instruction 10h ? disabled stuff instruction 11h ? disabled execute instruction 12h ? disabled reserved 13h?ffh ? ? debug command command byte enabled when not in debug mode? disabled by flash read protect option bit
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 181 write memory, read memory, write register, read register, read memory crc, step instruction, stuff instruction, and execute instruction commands. dbg 03h dbg runtimecounter[15:8] dbg runtimecounter[7:0] ? write ocd control register (04h) ?the write ocd contro l register command writes the data that follow s to the ocdctl register. when the flash read protect option bit is enabled, the dbgmode bit ( ocdctl [7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating mode is to reset the device. dbg 04h dbg ocdctl[7:0] ? read ocd control register (05h) ?the read ocd control register command reads the value of the ocdctl register. dbg 05h dbg ocdctl[7:0] ? write program counter (06h) ?the write program counter command writes the data that follows to the ez8 cpu?s program counter (pc). if the device is not in de- bug mode or if the flash read protect op tion bit is enabled, the program counter (pc) values are discarded. dbg 06h dbg programcounter[15:8] dbg programcounter[7:0] ? read program counter (07h) ?the read program count er command reads the value in the ez8 cpu?s program counter (p c). if the device is not in debug mode or if the flash read protect option bit is enabled, this command returns ffffh . dbg 07h dbg programcounter[15:8] dbg programcounter[7:0] ? write register (08h) ?the write register command writes data to the register file. data can be written 1?256 bytes at a time (256 bytes can be written by setting size to 0). if the device is not in debug mode, the address and data values are dis- carded. if the flash read protect option bit is enabled, only writes to the flash con- trol registers are allowed and all other re gister write data values are discarded. dbg 08h dbg {4?h0,register address[11:8]} dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 182 ? read register (09h) ?the read register command reads data from the register file. data can be read 1?256 bytes at a tim e (256 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is en- abled, this command returns ffh for all the data values. dbg 09h dbg {4?h0,register address[11:8] dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? write program memory (0ah) ?the write program memory command writes data to program memory. this command is equivalent to the ldc and ldci instruc- tions. data can be written 1?65536 bytes at a time (65536 bytes can be written by set- ting size to 0). the on-chip flash controlle r must be written to and unlocked for the programming operation to occur. if the flas h controller is not unlocked, the data is discarded. if the device is not in debug mo de or if the flash read protect option bit is enabled, the data is discarded. dbg 0ah dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read program memory (0bh) ?the read program memory command reads data from program memory. this command is equi valent to the ldc and ldci instruc- tions. data can be read 1?65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, this command returns ffh for the data. dbg 0bh dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? write data memory (0ch) ?the write data memory command writes data to data memory. this command is equivalent to the lde and ldei instructions. data can be written 1?65536 bytes at a time (65536 bytes can be written by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is en- abled, the data is discarded. dbg 0ch dbg data memory address[15:8] dbg data memory address[7:0]
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 183 dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read data memory (0dh) ?the read data memory command reads from data memory. this command is equivalent to th e lde and ldei instructions. data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read program memory crc (0eh) ?the read program memory crc com- mand computes and returns the cyclic redundancy chec k (crc) of program mem- ory using the 16-bit crc-ccitt polynomial. if the device is not in debug mode, this command returns ffffh for the crc value. unlike most other ocd read com- mands, there is a delay from issuing of th e command until the ocd returns the data. the ocd reads the program memory, calculates the crc value, and returns the re- sult. the delay is a function of the program memory size and is approximately equal to the system clock period multiplied by th e number of bytes in the program memory. dbg 0eh dbg crc[15:8] dbg crc[7:0] ? step instruction (10h) ?the step instruction command steps one assembly in- struction at the current program counter (pc) location. if the device is not in debug mode or the flash read protect option bit is enabled, the ocd ignores this command. dbg 10h ? stuff instruction (11h) ?the stuff instruction command steps one assembly in- struction and allows specification of the firs t byte of the instruction. the remaining 0- 4 bytes of the instruction are read from program memory. this command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a breakpoint. if the device is not in de bug mode or the flas h read protect option bit is enabled, the oc d ignores this command. dbg 11h dbg opcode[7:0] ? execute instruction (12h) ?the execute instruction command allows sending an entire instruction to be executed to the ez8 cpu. this command can also step over breakpoints. the number of bytes to send fo r the instruction depends on the opcode.
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 184 if the device is not in debug mode or th e flash read protect option bit is enabled, this command reads and discards one byte. dbg 12h dbg 1-5 byte opcode on-chip debugger control register definitions ocd control register the ocd control register controls the state of the on-chip debugger. this register is used to enter or exit debu g mode and to enable the brk instruction. it can also reset the z8 encore! xp ? f082a series device. a reset and stop function can be achieved by writing 81h to this register. a reset and go function can be achieved by writing 41h to this register. if the device is in debug mode, a run function can be implemented by writing 40h to this register. . dbgmode?debug mode the device enters debug mode when this b it is 1. when in debug mode, the ez8 cpu stops fetching new instructions. clearing this bit causes the ez8 cpu to restart. this bit is automatically set when a brk instruction is decoded and breakpoints are enabled. if the flash read protect option bit is enabled, th is bit can only be cleared by resetting the device. it cannot be written to 0. 0 = the z8 encore! xp f082a series de vice is operating in normal mode. 1 = the z8 encore! xp f082a series device is in debug mode. brken?breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h ). by default, break- points are disabled and the brk instruction behaves similar to an nop instruction. if this bit is 1, when a brk instruction is decoded, the dbgmode bit of the ocdctl register is automatically set to 1. 0 = breakpoints are disabled. 1 = breakpoints are enabled. table 106. ocd control register (ocdctl) bits 7 6 5 4 3 2 1 0 field dbgmode brken dbgack reserved rst reset 00000000 r/w r/wr/wr/wrrrrr/w
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 185 dbgack?debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, the ocd sends a debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. reserved?must be 0. rst?reset setting this bit to 1 resets th e z8f04xa family de vice. the device go es through a normal power-on reset sequence with the exception th at the on-chip debugger is not reset. this bit is automatically cleared to 0 at the end of reset. 0 = no effect. 1 = reset the flash read protect option bit device. ocd status register the ocd status register reports status inform ation about the current state of the debugger and the system. dbg?debug status 0 = normal mode 1 = debug mode halt?halt mode 0 = not in halt mode 1 = in halt mode frpenb?flash read protect option bit enable 0 = frp bit enabled, that allows disabling of many ocd commands 1 = frp bit has no effect reserved?must be 0 table 107. ocd status register (ocdstat) bits 7 6 5 4 3 2 1 0 field dbg halt frpenb reserved reset 00000000 r/w rrrrrrrr
ps022825-0908 on-chip debugger z8 encore! xp ? f082a series product specification 186
ps022825-0908 oscillator control z8 encore! xp ? f082a series product specification 187 oscillator control the z8 encore! xp ? f082a series devices uses five possible clocking schemes, each user-selectable: ? internal precision trimmed rc oscillator (ipo). ? on-chip oscillator using off-c hip crystal or resonator. ? on-chip oscillator usi ng external rc network. ? external clock drive. ? on-chip low power watchdog timer oscillator. ? clock failure detection circuitry. in addition, z8 encore! xp f082a series de vices contain clock failure detection and recovery circuitry, allowing continued oper ation despite a failure of the system clock oscillator. operation this chapter discusses the logic used to se lect the system clock and handle primary oscillator failures. system clock selection the oscillator control block selects from the available clocks. table 108 details each clock source and its usage.
ps022825-0908 oscillator control z8 encore! xp ? f082a series product specification 188 unintentional accesses to the oscillator control register c an actually stop the chip by switching to a non-functioning oscillator. to prevent this condition, the oscillator con- trol block employs a register unlocking/locking scheme. osc control register unlocking/locking to write the oscillator control register, unlo ck it by making two writes to the oscctl register with the values e7h followed by 18h . a third write to the oscctl register changes the value of the actual register and retu rns the register to a locked state. any other sequence of oscillator control register writes has no effect. the values written to unlock the register must be ordered correctly, but are not necessarily consecutive. it is possible to write to or read from other registers within the unlockin g/locking operation. table 108. oscillator configuration and selection clock source characteristics required setup internal precision rc oscillator ? 32.8 khz or 5.53 mhz ? high accuracy ? no external components required ? unlock and write oscillator control register (oscctl) to enable and select oscillator at either 5.53 mhz or 32.8 khz external crystal/ resonator ? 32 khz to 20 mhz ? very high accuracy (dependent on crystal or resonator used) ? requires external components ? configure flash option bits for correct external oscillator mode ? unlock and write oscctl to enable crystal oscillator, wait for it to stabilize and select as system clock (if the xtldis option bit has been de- asserted, no waiting is required) external rc oscillator ? 32 khz to 4 mhz ? accuracy dependent on external components ? configure flash option bits for correct external oscillator mode ? unlock and write oscctl to enable crystal oscillator and select as system clock external clock drive ? 0 to 20 mhz ? accuracy dependent on external clock source ? write gpio registers to configure pb3 pin for external clock function ? unlock and write oscctl to select external system clock ? apply external clock signal to gpio internal watchdog timer oscillator ? 10 khz nominal ? low accuracy; no external components required ? very low power consumption ? enable wdt if not enabled and wait until wdt oscillator is operating. ? unlock and write oscillator control register (oscctl) to enable and select oscillator caution:
ps022825-0908 oscillator control z8 encore! xp ? f082a series product specification 189 when selecting a new clock sour ce, the system clock oscillato r failure detection circuitry and the watchdog timer oscillator failure ci rcuitry must be di sabled. if sofen and wofen are not disabled prior to a clock switc h-over, it is possible to generate an inter- rupt for a failure of either oscillator. the failure detection circu itry can be enabled any- time after a successful write of oscsel in the oscctl register. the internal precision oscillator is enabled by default. if the user code changes to a differ- ent oscillator, it may be appr opriate to disable the ipo fo r power savings. disabling the ipo does not occur automatically. clock failure detection and recovery system clock oscillator failure the z8f04xa family devices can generate no n-maskable interrupt-like events when the primary oscillator fails. to maintain system fu nction in this situatio n, the clock failure recovery circuitry automatica lly forces the watchdog timer o scillator to drive the system clock. the watchdog timer oscillator must be enabled to allow th e recovery. although this oscillator runs at a much slower speed th an the original system clock, the cpu contin- ues to operate, allowing execution of a cloc k failure vector and software routines that either remedy the oscillator failure or issue a failure alert. this au tomatic switch-over is not available if the watchdog timer is selected as the system clock oscillator. it is also unavailable if the watchdog timer oscillator is disabled, though it is not necessary to enable the watchdog timer reset function (see watchdog timer on page 91). the primary oscillator failure detection circ uitry asserts if the system clock frequency drops below 1 khz 50%. if an external signal is selected as the system oscillator, it is possible that a very slow but non-failing cloc k can generate a failu re condition. under these conditions, do not enable the clock failure circuitry (s ofen must be deasserted in the oscctl register). watchdog timer failure in the event of a watchdog timer oscillator failure, a similar non-maskable interrupt-like event is issued. this event does not trigger an attendant clock switch-over, but alerts the cpu of the failure. after a watchdog timer failu re, it is no longer possible to detect a pri- mary oscillator failure. the failure detectio n circuitry does not function if the watchdog timer is used as the system clock oscillator or if the watchdog timer oscillator has been disabled. for either of these cases, it is ne cessary to disable the detection circuitry by deasserting the wdfen bit of the oscctl register. the watchdog timer oscillator failure detec tion circuit counts system clocks while looking for a watchdog timer clock. the logi c counts 8004 system clock cycles before determining that a failure has occurred. the system clock rate determines the speed at which the watchdog timer failur e can be detected. a very sl ow system clock results in very slow detection times.
ps022825-0908 oscillator control z8 encore! xp ? f082a series product specification 190 it is possible to disable the clock failure detection circuitry as well as all functioning clock sources. in this ca se, the z8 encore! xp f082a series device ceases functioning and can only be recovered by power-on-reset. oscillator control register definitions oscillator control register the oscillator control register (oscctl) enables/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry and selects the primary oscillator, which becomes th e system clock. the oscillator control register must be un locked before writing. writing the two step sequence e7h followed by 18h to the oscillator control regi ster unlocks it. the register is locked at successful completion of a register write to the oscctl. inten?internal precision oscillator enable 1 = internal precision oscillator is enabled 0 = internal precision oscillator is disabled xtlen?crystal oscillator enab le; this setting overrides the gpio register control for pa0 and pa1 1 = crystal oscillator is enabled 0 = crystal oscillator is disabled wdten?watchdog timer oscillator enable 1 = watchdog timer oscillator is enabled 0 = watchdog timer oscillator is disabled sofen?system clock oscillato r failure detection enable 1 = failure detection and recovery of system clock oscillator is enabled 0 = failure detection and recovery of system clock oscillator is disabled table 109. oscillator control register (oscctl) bits 7 6 5 4 3 2 1 0 field inten xtlen wdten sofen wdfen scksel reset 10100000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f86h caution:
ps022825-0908 oscillator control z8 encore! xp ? f082a series product specification 191 wdfen?watchdog timer oscillato r failure detection enable 1 = failure detection of watch dog timer oscillator is enabled 0 = failure detection of watch dog timer oscillator is disabled scksel?system clock oscillator select 000 = internal precision oscillator functions as system clock at 5.53 mhz 001 = internal precision oscillator functions as system clock at 32 khz 010 = crystal oscillator or external rc oscillator functions as system clock 011 = watchdog timer oscillator functions as system 100 = external clock signal on pb3 functions as system clock 101 = reserved 110 = reserved 111 = reserved
ps022825-0908 oscillator control z8 encore! xp ? f082a series product specification 192
ps022825-0908 crystal oscillator z8 encore! xp ? f082a series product specification 193 crystal oscillator the products in the z8 encore! xp ? f082a series contain an on-chip crystal oscillator for use with external crystals with 32 khz to 20 mhz fre quencies. in addition, the oscillator supports external rc networks with oscillation frequencies up to 4 mhz or ceramic resonators with frequencies up to 8 mhz. the on-chip crystal oscillator can be used to generate the primary sy stem clock for the internal ez 8 cpu and the majority of the on-chip peripherals. alternatively, the x in input pin can also accept a cmos-level clock input signal (32 khz?20 mhz). if an ex ternal clock generator is used, the x out pin must be left unconnected. the z8 encore! xp f082a series products do not contain an internal clock divider. the frequency of the signal on the x in input pin determines the frequency of the system clock. although the xin pin can be used as an inpu t for an external clock generator, the clkin pin is better suited for such use (see system clock selection on page 187). operating modes the z8 encore! xp f082a series prod ucts support four oscillator modes: ? minimum power for use with very low frequency crystals (32 khz?1 mhz). ? medium power for use with medium fre quency crystals or ceramic resonators (0.5 mhz to 8 mhz). ? maximum power for use with high freque ncy crystals (8 mhz to 20 mhz). ? on-chip oscillator configured for use w ith external rc ne tworks (<4 mhz). the oscillator mode is selected using user-programmable fl ash option bits. see flash option bits on page 153 for information. crystal oscillator operation the flash option bit xtldis controls whethe r the crystal oscillator is enabled during reset. the crystal may later be disabled after reset if a new oscillato r has been selected as the system clock. if the crystal is manually enabled after reset through the oscctl regis- ter, the user code must wait at least 1000 crystal oscillator cycles for the crystal to stabilize. after this, the crystal oscillat or may be selected as the system clock. the stabilization time varies depe nding on the crystal or resonator used, as well as on the feedback network. see table 111 for transconductance values to compute oscillator stabi- lization times. note: note:
ps022825-0908 crystal oscillator z8 encore! xp ? f082a series product specification 194 figure 27 displays a recommended configuration for connection with an external funda- mental-mode, parallel-resonant crystal oper ating at 20 mhz. recommended 20 mhz crys- tal specifications are provided in table 110 . printed circuit board layout must add no more than 4 pf of stray capacitance to either the x in or x out pins. if oscillation does not occur, reduce the values of capacitors c 1 and c 2 to decrease loading. figure 27. recommended 20 mhz crystal oscillator configuration table 110. recommended crystal oscillator specifications parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s )60 maximum load capacitance (c l ) 30 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum c2 = 15 pf c1 = 15 pf crystal xout xin on-chip oscillator
ps022825-0908 crystal oscillator z8 encore! xp ? f082a series product specification 195 oscillator operation with an external rc network figure 28 displays a recommended configuratio n for connection with an external resistor-capacitor (rc) network. figure 28. connecting the on-chip oscillator to an external rc network an external resistance value of 45 k is recommended for oscillator operation with an external rc network. the minimum resistan ce value to ensure operation is 40 k . the typical oscillator frequency can be esti mated from the values of the resistor ( r in k ) and capacitor ( c in pf) elements usi ng the following equation: table 111. transconductance values for low, medium, and high gain operating modes mode crystal frequency range function transconductance (ma/v) use this range for calculations low gain* 32 khz?1 mhz low power/frequency applications 0.02 0.04 0.09 medium gain* 0.5 mhz?10 mhz medium po wer/frequency applications 0.84 1.7 3.1 high gain* 8 mhz?20 mhz high power/frequency applications 1.1 2.3 4.2 note: *printed circuit board layout must not add more than 4 pf of stray capacitance to either xin or xout pins. if no oscillation occurs, reduce the values of t he capacitors c1 and c2 to decrease the loading. c x in r vdd oscillator frequency (khz) 1 6 10 0.4 r c () 4c () + ---------------------- ----------------- ---------------- =
ps022825-0908 crystal oscillator z8 encore! xp ? f082a series product specification 196 figure 29 displays the typical (3.3 v and 25 c) oscillator frequ ency as a function of the capacitor ( c in pf) employed in the rc network assuming a 45 k external resistor. for very small values of c, the pa rasitic capacitance of the osc illator xin pin and the printed circuit board must be included in the estimation of the oscillator frequency. it is possible to operate the rc oscillator usin g only the parasitic ca pacitance of the pack- age and printed circuit board. to minimize sensitivity to external parasitics, external capacitance values in excess of 20 pf are recommended. figure 29. typical rc oscillator frequency as a function of the external capacitance with a 45 k resistor when using the external rc oscillator mode, the oscillator can stop oscillating if the power su pply drops below 2.7 v, but before the power supply drops to the voltage brownout threshold. the oscillator resumes oscillation when the supp ly voltage exceeds 2.7 v. 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 c (pf) frequency (khz) caution:
ps022825-0908 internal precision oscillator z8 encore! xp ? f082a series product specification 197 internal precision oscillator the internal precision oscillator (ipo) is de signed for use without external components. you can either manually trim the oscillator fo r a non-standard frequency or use the auto- matic factory-trimmed version to achieve a 5.53 mhz frequency. ipo features include: ? on-chip rc oscillator that does not require external components ? output frequency of either 5.53 mhz or 32.8 khz (contains both a fast and a slow mode) ? trimmed through flash option bits with user override ? elimination of crystals or ce ramic resonators in applica tions where very high timing accuracy is not required operation an 8-bit trimming register, incorporated into the design, compensates for absolute variation of oscillator frequency . once trimmed the oscillator frequency is stable and does not require subsequent calibration. trimming is performed during manufacturing and is not necessary for you to repeat unless a frequ ency other than 5.53 mhz (fast mode) or 32.8 khz (slow mode) is required . this trimming is done at +3 0 oc and a supply voltage of 3.3 v, so accuracy of this operating point is optimal. if not used, the ipo can be disabled by the oscillator control register (see oscillator con- trol register definitions on page 190). by default, the oscillator fre quency is set by the factor y trim value stored in the write-protected flash informati on page. however, the user code can override these trim values as described in trim bit address space on page 158. select one of two frequencies for the oscillator: 5.53 mhz and 32.8 khz, using the oscsel bits in the oscillator control on page 187.
ps022825-0908 internal precision oscillator z8 encore! xp ? f082a series product specification 198
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 199 ez8 cpu instruction set assembly language programming introduction the ez8 cpu assembly language provides a me ans for writing an application program without concern for actual memory addresses or machine instruction formats. a program written in assembly language is called a sour ce program. assembly language allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to represent the inst ructions themselves. th e opcodes identify the instruction while the operands represent memo ry locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called statements. each statement can contain la bels, operations, oper ands and comments. labels can be assigned to a particular inst ruction step in a source program. the label identifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine language program called the obje ct code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example. assembly language source program example jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the de stination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, #%01 ; another load (ld) instruction with two operands. ; the first operand, extended mode register address 234h , ; identifies the destination. the second operand, immediate data ; value 01h , is the source. the value 01h is written into the ; register at address 234h .
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 200 assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. af ter assembly, the obj ect code usually has the operands in the order ?source, destination?, but ordering is opcode-dependent. the following instruction ex amples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler. this binary format must be followed if manual program coding is preferred or if you intend to implement your own assembler. example 1 : if the contents of registers 43h and 08h are added and the result is stored in 43h, the assembly syntax and resulting object code is: example 2 : in general, when an instruction format requires an 8-bit register address, that address can specify any regist er location in the range 0?255 or, using escaped mode addressing, a working register r0?r15. if th e contents of register 43h and working register r8 are added and the result is stor ed in 43h, the assembl y syntax and resulting object code is: see the device-specific product specification to determine the exact register file range available. the register file size va ries, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, th e operands, condition codes, status flags, and addr ess modes are represented by a notational shorthand that is described in table 114 . table 112. assembly language syntax example 1 assembly language code add 43h, 08h (add dst, src) object code 04 08 43 (opc src, dst) table 113. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst)
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 201 . table 115 lists additional symbols th at are used throughout th e instruction summary and instruction set description sections. table 114. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? refer to condition codes section in the ez8 cpu core user manual (um0128) . da direct address addrs addrs. represents a number in the range of 0000h to ffffh er extended addressing register reg reg. represents a number in the range of 000h to fffh im immediate data #data data is a number between 00h to ffh ir indirect working register @rn n = 0?15 ir indirect register @reg reg. represents a number in the range of 00h to ffh irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 irr indirect register pair @reg reg. represents an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0 ? 15 r register reg reg. represents a number in the range of 00h to ffh ra relative address x x represents an index in the range of +127 to ? 128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 rr register pair reg reg. represents an even number in the range of 00h to feh vector vector address vector vector represents a number in the range of 00h to ffh x indexed #index the register or register pair to be indexed is offset by the signed index value (#index) in a +127 to -128 range.
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 202 assignment of a value is indicated by an arrow. for example, dst dst + src indicates the source data is added to the destin ation data and the result is stored in the des- tination location. ez8 cpu instruction classes ez8 cpu instructions can be divided fu nctionally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift table 115. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 203 table 116 through table 123 lists the instructions belongin g to each group and the number of operands required for each instruction. some inst ructions appear in more than one table as these instruction can be considered as a subs et of more than one category. within these tables, the source operand is identified as ?s rc?, the destination operand is ?dst? and a con- dition code is ?cc?. table 116. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word mult dst multiply sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract us ing extended addressing
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 204 table 117. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test complement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 118. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto-increment addresses ldei dst, src load external data to/from data memory and auto- increment addresses table 119. cpu control instructions mnemonic operands instruction atm ? atomic execution ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 205 scf ? set carry flag srp src set register pointer stop ? stop mode wdt ? watchdog timer refresh table 120. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/fr om program memory and auto- increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/from data memory and auto- increment addresses ldwx dst, src load word using extended addressing ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing table 121. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or table 119. cpu control instructions (continued) mnemonic operands instruction
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 206 orx dst, src logical or using extended addressing xor dst, src logical exclusive or xorx dst, src logical exclusiv e or using extended addressing table 122. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decrement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap table 123. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry table 121. logical instructions (continued) mnemonic operands instruction
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 207 ez8 cpu instruction summary table 124 summarizes the ez8 cpu instructions . the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. . sra dst shift right arithmetic srl dst shift right logical swap dst swap nibbles table 124. ez8 cpu instruction summary assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h adc dst, src dst dst + src + c r r 12 ****0* 2 3 rir 13 24 rr 14 3 3 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 ****0* 4 3 er im 19 4 3 add dst, src dst dst + src r r 02 ****0* 2 3 rir 03 24 rr 04 3 3 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 ****0* 4 3 er im 09 4 3 flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 table 123. rotate and shift instructions (continued) mnemonic operands instruction
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 208 and dst, src dst dst and src r r 52 ? * * 0 ? ? 2 3 rir 53 24 rr 54 3 3 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 ? * * 0 ? ? 4 3 er im 59 4 3 atm block all interrupt and dma requests during execution of the next 3 instructions 2f ????? ? 1 2 bclr bit, dst dst[bit] 0 r e2 ????? ? 2 2 bit p, bit, dst dst[bit] p r e2 ????? ? 2 2 brk debugger break 00 ? ? ? ? ? ? 1 1 bset bit, dst dst[bit] 1 r e2 ????? ? 2 2 bswap dst dst[7:0] dst[0:7] r d5 x * * 0 ? ? 2 2 btj p, bit, src, dst if src[bit] = p pc pc + x r f6 ????? ? 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 pc pc + x r f6 ????? ? 3 3 ir f7 3 4 btjz bit, src, dst if src[bit] = 0 pc pc + x r f6 ????? ? 3 3 ir f7 3 4 call dst sp sp -2 @sp pc pc dst irr d4 ????? ? 2 6 da d6 3 3 ccf c ~c ef * ?????- 1 2 clr dst dst 00h r b0 ? ? ? ? ? ? 2 2 ir b1 2 3 table 124. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 209 com dst dst ~dst r 60 ? * * 0 ? ? 2 2 ir 61 2 3 cp dst, src dst - src r r a2 ****?? 2 3 rir a3 24 rr a4 3 3 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 ****?? 3 3 rir1f a3 34 rr1f a4 4 3 rir1f a5 4 4 rim1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 ****?? 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 ****?? 4 3 er im a9 4 3 da dst dst da(dst) r 40 * * * x ? ? 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 ?***?? 2 2 ir 31 2 3 decw dst dst dst - 1 rr 80 ?***?? 2 5 irr 81 2 6 di irqctl[7] 0 8f ????? ? 1 2 djnz dst, ra dst dst ? 1 if dst 0 pc pc + x r 0a-fa ????? ? 2 3 ei irqctl[7] 1 9f ????? ? 1 2 table 124. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 210 halt halt mode 7f ? ? ? ? ? ? 1 2 inc dst dst dst + 1 r 20 ? * * ? ? ? 2 2 ir 21 2 3 r0e-fe 12 incw dst dst dst + 1 rr a0 ?***?? 2 5 irr a1 2 6 iret flags @sp sp sp + 1 pc @sp sp sp + 2 irqctl[7] 1 bf ***** * 1 5 jp dst pc dst da 8d ????? ? 3 2 irr c4 2 3 jp cc, dst if cc is true pc dst da 0d-fd ????? ? 3 2 jr dst pc pc + x da 8b ????? ? 2 2 jr cc, dst if cc is true pc pc + x da 0b-fb ????? ? 2 2 ld dst, rc dst src r im 0c-fc ? ? ? ? ? ? 2 2 r x(r) c7 3 3 x(r) r d7 3 4 rir e3 23 rr e4 3 2 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 table 124. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 211 ldc dst, src dst src r irr c2 ????? ? 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst src r r + 1 rr rr + 1 ir irr c3 ????? ? 2 9 irr ir d3 2 9 lde dst, src dst src r irr 82 ????? ? 2 5 irr r 92 2 5 ldei dst, src dst src r r + 1 rr rr + 1 ir irr 83 ????? ? 2 9 irr ir 93 2 9 ldwx dst, src dst src er er 1fe8 ????? ? 5 4 ldx dst, src dst src r er 84 ????? ? 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst src + x r x(r) 98 ? ? ? ? ? ? 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] dst[15:8] * dst[7:0] rr f4 ????? ? 2 8 nop no operation 0f ? ? ? ? ? ? 1 2 table 124. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 212 or dst, src dst dst or src r r 42 ? * * 0 ? ? 2 3 rir 43 24 rr 44 3 3 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst dst or src er er 48 ? * * 0 ? ? 4 3 er im 49 4 3 pop dst dst @sp sp sp + 1 r 50 ????? ? 2 2 ir 51 2 3 popx dst dst @sp sp sp + 1 er d8 ????? ? 3 2 push src sp sp ? 1 @sp src r 70 ????? ? 2 2 ir 71 2 3 im if70 3 2 pushx src sp sp ? 1 @sp src er c8 ????? ? 3 2 rcf c 0 cf 0???? ? 1 2 ret pc @sp sp sp + 2 af ????? ? 1 4 rl dst r 90 ****?? 2 2 ir 91 2 3 rlc dst r 10 ****?? 2 2 ir 11 2 3 table 124. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 213 rr dst r e0 ****?? 2 2 ir e1 2 3 rrc dst r c0 ****?? 2 2 ir c1 2 3 sbc dst, src dst dst ? src - c r r 32 ****1* 2 3 rir 33 24 rr 34 3 3 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst dst ? src - c er er 38 ****1* 4 3 er im 39 4 3 scf c 1 df 1???? ? 1 2 sra dst r d0 * * * 0 ? ? 2 2 ir d1 2 3 srl dst r 1f c0 * * 0 * ? ? 3 2 ir 1f c1 3 3 srp src rp src im 01 ????? ? 2 2 stop stop mode 6f ? ? ? ? ? ? 1 2 sub dst, src dst dst ? src r r 22 ****1* 2 3 rir 23 24 rr 24 3 3 rir 25 3 4 rim 26 3 3 ir im 27 3 4 table 124. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 214 subx dst, src dst dst ? src er er 28 ****1* 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x ? ? 2 2 ir f1 2 3 tcm dst, src (not dst) and src r r 62 ? * * 0 ? ? 2 3 rir 63 24 rr 64 3 3 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 ? * * 0 ? ? 4 3 er im 69 4 3 tm dst, src dst and src r r 72 ? * * 0 ? ? 2 3 rir 73 24 rr 74 3 3 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 ? * * 0 ? ? 4 3 er im 79 4 3 trap vector sp sp ? 2 @sp pc sp sp ? 1 @sp flags pc @vector vector f2 ????? ? 2 6 wdt 5f ????? ? 1 2 table 124. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022825-0908 ez8 cpu instruction set z8 encore! xp ? f082a series product specification 215 xor dst, src dst dst xor src r r b2 ? * * 0 ? ? 2 3 rir b3 24 rr b4 3 3 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst dst xor src er er b8 ? * * 0 ? ? 4 3 er im b9 4 3 table 124. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022825-0908 opcode maps z8 encore! xp ? f082a series product specification 216 opcode maps a description of the opcode map data an d the abbreviations are provided in figure 30 . figure 31 and figure 32 displays the ez8 cpu instructions. table 125 lists opcode map abbreviations. figure 30. opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps022825-0908 opcode maps z8 encore! xp ? f082a series product specification 217 table 125. opcode map abbreviations abbreviation description abbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displacement r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps022825-0908 opcode maps z8 encore! xp ? f082a series product specification 218 figure 31. first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.1 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map 1, 2 atm
ps022825-0908 opcode maps z8 encore! xp ? f082a series product specification 219 figure 32. second opcode map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) 3, 2 push im ldwx 5, 4 er2,er1
ps022825-0908 opcode maps z8 encore! xp ? f082a series product specification 220
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 221 electrical characteristics the data in this chapter is pre-qualificatio n and pre-characterization and is subject to change. additional electrical characteristics may be found in the individual chapters. absolute maximum ratings stresses greater than those listed in table 126 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, tie unused in puts to one of the supply voltages (v dd or v ss ). table 126. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias -40 +105 c storage temperature -65 +150 c voltage on any pin with respect to v ss -0.3 +5.5 v 1 -0.3 +3.9 v 2 voltage on v dd pin with respect to v ss -0.3 +3.6 v maximum current on input and/or inactive output pin -5 +5 a maximum output current from active output pin -25 +25 ma 8-pin packages maximum ratings at 0 c to 70 c total power dissipation 220 mw maximum current into v dd or out of v ss 60 ma 20-pin packages maximum ratings at 0 c to 70 c total power dissipation 430 mw maximum current into v dd or out of v ss 120 ma
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 222 dc characteristics table 127 lists the dc characteristics of the z8 encore! xp ? f082a series products. all voltages are referenced to v ss , the primary system ground. 28-pin packages maximum ratings at 0 c to 70 c total power dissipation 450 mw maximum current into v dd or out of v ss 125 ma operating temperature is spec ified in dc characteristics. 1. this voltage applies to all pins except the following: v dd , av dd , pins supporting analog input (port b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1). on the 8-pin packages, this applies to all pins but v dd . 2. this voltage applies to pins on the 20-/28-pin packages supporting analog input (por t b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1). table 127. dc characteristics symbol parameter t a = -40 c to +105 c (unless otherwise specified) units conditions minimum typical maximum v dd supply voltage 2.7 ? 3.6 v v il1 low level input voltage -0.3 ? 0.3*v dd v v ih1 high level input voltage 0.7*v dd ? 5.5 v for all input pins without analog or oscillator function. for all signal pins on the 8-pin devices. programmable pull-ups must also be disabled. v ih2 high level input voltage 0.7*v dd ?v dd +0.3 v for those pins with analog or oscillator function (20-/28-pin devices only), or when programmable pull-ups are enabled. v ol1 low level output voltage ??0.4vi ol = 2 ma; v dd = 3.0 v high output drive disabled. v oh1 high level output voltage 2.4 ? ? v i oh = -2 ma; v dd = 3.0 v high output drive disabled. table 126. absolute maximum ratings (continued) parameter minimum maximum units notes
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 223 v ol2 low level output voltage ??0.6vi ol = 20 ma; v dd = 3.3 v high output drive enabled. v oh2 high level output voltage 2.4 ? ? v i oh = -20 ma; v dd = 3.3 v high output drive enabled. i ih input leakage current ?+ 0.002 + 5av in = v dd v dd = 3.3 v; i il input leakage current ?+ 0.007 + 5av in = v ss v dd = 3.3 v; i tl tristate leakage current ??+ 5a i led controlled current drive 1.8 3 4.5 ma {afs2,afs1} = {0,0} 2.8 7 10.5 ma {afs2,afs1} = {0,1} 7.8 13 19.5 ma {afs2,afs1} = {1,0} 12 20 30 ma {afs2,afs1} = {1,1} c pad gpio port pad capacitance ?8.0 2 ?pf c xin xin pad capacitance ?8.0 2 ?pf c xout xout pad capacitance ?9.5 2 ?pf i pu weak pull-up current 30 100 350 a v dd = 3.0 v?3.6 v v ram ram data retention voltage tbd v voltage at which ram retains static values; no reading or writing is allowed. notes 1. this condition excludes all pins that have on-chip pull-ups, when driven low. 2. these values are provided for design guid ance only and are not tested in production. table 127. dc characteristics (continued) symbol parameter t a = -40 c to +105 c (unless otherwise specified) units conditions minimum typical maximum
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 224 table 128. power consumption symbol parameter v dd = 2.7 v to 3.6 v units conditions typical 1 maximum 2 std temp maximum 3 ext temp i dd stop supply current in stop mode 0.1 a no peripherals enabled. all pins driven to v dd or v ss . i dd halt supply cu rrent in halt mode (with all peripherals disabled) 35 55 65 a 32 khz 520 a 5.5 mhz 2.1 2.85 2.85 ma 20 mhz i dd supply current in active mode (with all peripherals disabled) 2.8 ma 32 khz 4.5 5.2 5.2 ma 5.5 mhz 5.5 6.5 6.5 ma 10 mhz 7.9 11.5 11.5 ma 20 mhz i dd wdt watchdog timer supply current 0.9 1.0 1.1 a i dd xtal crystal oscillator supply current 40 a 32 khz 230 a 4 mhz 760 a 20 mhz i dd ipo internal precision oscillator supply current 350 500 550 a i dd vbo voltage brownout and low-voltage detect supply current 50 a for 20-/28-pin devices (vbo only); see notes 4 for 8-pin devices; see notes 4 i dd adc analog to digital converter supply current (with external reference) 2.8 3.1 3.2 ma 32 khz 3.1 3.6 3.7 ma 5.5 mhz 3.3 3.7 3.8 ma 10 mhz 3.7 4.2 4.3 ma 20 mhz i dd adcref adc internal reference supply current 0asee notes 4 i dd cmp comparator supply current 150 180 190 a see notes 4
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 225 i dd lpo low-power operational amplifier supply current 3 5 5 a driving a high- impedance load i dd ts temperature sensor supply current 60 a see notes 4 i dd bg band gap supply current 320 480 500 a for 20-/28-pin devices for 8-pin devices notes 1. typical conditions are defined as v dd = 3.3 v and +30 c. 2. standard temperature is defined as t a = 0 c to +70 c; these values not tested in production for worst case behavior, but are derived from product characte rization and provided for design guidance only. 3. extended temperature is defined as t a = -40 c to +105 c; these values not tested in production for worst case behavior, but are derived from product char acterization and provided for design guidance only. 4. for this block to operate, the bandgap circuit is autom atically turned on and must be added to the total supply current. this bandgap current is only added once, re gardless of how many peripherals are using it. table 128. power consumption (continued) symbol parameter v dd = 2.7 v to 3.6 v units conditions typical 1 maximum 2 std temp maximum 3 ext temp
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 226 figure 33 displays the typical current consumptio n while operating w ith all peripherals disabled, at 30 oc, versus the system clock frequency. figure 33. typical active mode i dd versus system clock frequency typical supply current - active mode 0 2 4 6 8 10 0 5 10 15 20 freq (mhz) idd (ma) vdd = 3.60v / 30c vdd = 3.30v / 30c vdd = 2.70v / 30c
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 227 ac characteristics the section provides information about the ac characteristics and timing. all ac timing information assumes a standard load of 50 pf on all outputs. table 129. ac characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c (unless otherwise stated) units conditions minimum maximum f sysclk system clock frequency ? 20.0 mhz read-only from flash memory 0.032768 20.0 mhz program or erasure of the flash memory f xtal crystal oscillator frequency ? 20. 0 mhz system clock frequencies below the crystal oscillator minimum require an external clock driver t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50 ns t xinl system clock low time 20 30 ns t clk = 50 ns t xinr system clock rise time ? 3 ns t clk = 50 ns t xinf system clock fall time ? 3 ns t clk = 50 ns
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 228 table 130. internal precision oscillator electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c (unless otherwise stated) units conditions minimum typical maximum f ipo internal precision oscillator frequency (high speed) 5.53 mhz v dd = 3.3 v t a = 30 c f ipo internal precision oscillator frequency (low speed) 32.7 khz v dd = 3.3 v t a = 30 c f ipo internal precision oscillator error + 1+ 4% t ipost internal precision oscillator startup time 3s
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 229 on-chip peripheral ac and dc electrical characteristics table 131. power-on reset and voltage brownout electrical characteristics and timing symbol parameter t a = -40 c to +105 c units conditions minimum typical 1 maximum v por power-on reset voltage threshold 2.20 2.45 2.70 v v dd = v por v vbo voltage brownout reset voltage threshold 2.15 2.40 2.65 v v dd = v vbo v por to v vbo hysteresis 50 75 mv starting v dd voltage to ensure valid power-on reset. ?v ss ?v t ana power-on reset analog delay ?70 ?sv dd > v por ; t por digital reset delay follows t ana t por power-on reset digital delay 16 s 66 internal precision oscillator cycles + ipo startup time (t ipost ) t por power-on reset digital delay 1 ms 5000 internal precision oscillator cycles t smr stop mode recovery with crystal oscillator disabled 16 s 66 internal precision oscillator cycles t smr stop mode recovery with crystal oscillator enabled 1 ms 5000 internal precision oscillator cycles t vbo voltage brownout pulse rejection period ? 10 ? s period of time in which v dd < v vbo without generating a reset. t ramp time for v dd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms t smp stop mode recovery pin pulse rejection period 20 ns for any smr pin or for the reset pin when it is asserted in stop mode. 1 data in the typical column is from characterization at 3.3 v and 30 c. these values are provided for design guidance only and are not tested in production.
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 230 table 132. flash memory electrical characteristics and timing parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c (unless otherwise stated) units notes minimum typical maximum flash byte read time 100 ? ? ns flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms writes to single address before next erase ?? 2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this parameter is only an issue when bypassing the flash controller. data retention 100 ? ? years 25 c endurance 10,000 ? ? cycles program/erase cycles table 133. watchdog timer electrical characteristics and timing symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c (unless otherwise stated) units conditions minimum typical maximum f wdt wdt oscillator frequency 10 khz f wdt wdt oscillator error + 50 % t wdtcal wdt calibrated timeout 0.98 1 1.02 s v dd = 3.3 v; t a = 30 c 0.70 1 1.30 s v dd = 2.7 v to 3.6 v t a = 0 c to 70 c 0.50 1 1.50 s v dd = 2.7 v to 3.6 v t a = -40 c to +105 c
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 231 table 134. non-volatile data storage parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c units notes minimum typical maximum nvds byte read time 34 ? 519 s with system clock at 20 mhz nvds byte program time 0.171 ? 39.7 ms with system clock at 20 mhz data retention 100 ? ? years 25 c endurance 160,000 ? ? cycles cumu lative write cycles for entire memory table 135. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0 v to 3.6 v t a = 0 c to +70 c (unless otherwise stated) units conditions minimum typical maximum resolution 10 ? bits differential nonlinearity (dnl) -1.0 ? 1.0 lsb 3 external v ref = 2.0 v; r s 3.0 k integral nonlinearity (inl) -3.0 ? 3.0 lsb 3 external v ref = 2.0 v; r s 3.0 k offset error with calibration + 1lsb 3 absolute accuracy with calibration + 3lsb 3 v ref internal reference voltage 1.0 2.0 1.1 2.2 1.2 2.4 v refsel=01 refsel=10 v ref internal reference variation with temperature + 1.0 % temperature variation with v dd = 3.0 v ref internal reference voltage variation with v dd + 0.5 % supply voltage variation with t a = 30 c r refout reference buffer output impedance 850 when the internal reference is buffered and driven out to the vref pin (refout = 1)
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 232 single-shot conversion time ? 5129 ? system clock cycles all measurements but temperature sensor 10258 temperature sensor measurement continuous conversion time ? 256 ? system clock cycles all measurements but temperature sensor 512 temperature sensor measurement signal input bandwidth ? 10 khz as defined by -3 db point r s analog source impedance 4 ??10k in unbuffered mode 500 k in buffered modes zin input impedance ? 150 k in unbuffered mode at 20 mhz 5 10 ? m in buffered modes vin input voltage range 0 v dd v unbuffered mode 0.3 v dd -1.1 v buffered modes these values define the range over which the adc performs within spec; exceeding these values does not cause damage or instability; see dc characteristics on page 222 for absolute pin voltage limits notes 1. analog source impedance affects the adc offset volt age (because of pin leakage) and input settling time. 2. devices are factory calibrated at v dd = 3.3 v and t a = +30 c, so the adc is maximally accurate under these conditions. 3. lsbs are defined assuming 10-bit resolution. 4. this is the maximum recommended resistance seen by the adc input pin. 5. the input impedance is inversely proportional to the system clock frequency. table 135. analog-to-digital converter electrical characteristics and timing (continued) symbol parameter v dd = 3.0 v to 3.6 v t a = 0 c to +70 c (unless otherwise stated) units conditions minimum typical maximum note:
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 233 table 137. comparator electrical characteristics table 136. low power operational amplifier electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c units conditions minimum typical maximum av open loop voltage gain 80 db gbw gain/bandwidth product 500 khz pm phase margin 50 deg assuming 13 pf load capacitance v oslpo input offset voltage + 1+ 4mv v oslpo input offset voltage (temperature drift) 110 v/c v in input voltage range 0.3 vdd - 1 v v out output voltage range 0.3 vdd - 1 v i out = 45 a symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c units conditions minimum typical maximum v os input dc offset 5 mv v cref programmable internal reference voltage + 5 % 20-/28-pin devices + 3 % 8-pin devices t prop propagation delay 200 ns v hys input hysteresis 4 mv v in input voltage range v ss v dd -1 v
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 234 table 138. temperature sensor electrical characteristics general purpose i/o port input data sample timing figure 34 displays timing of the gpio port i nput sampling. the input value on a gpio port pin is sampled on the rising edge of the system clock. the port value is available to the ez8 cpu on the second rising clock edge following the change of the port value. symbol parameter v dd = 2.7 v to 3.6 v units conditions minimum typical maximum t aerr temperature error + 0.5 + 2 c over the range +20 c to +30 c (as measured by adc) 1 + 1+ 5 c over the range +0 c to +70 c (as measured by adc) + 2+ 7 c over the range +0 c to +105 c (as measured by adc) + 7 c over the range -40 c to +105 c (as measured by adc) t aerr temperature error tbd c over the range -40 c to +105 c (as measured by comparator) t wake wakeup time 80 100 s time required for temperature sensor to stabilize after enabling 1 devices are factory calibrate d at for maximal accuracy between +20 c and +30 c, so the sensor is maximally accurate in that range. user re-calibration for a differen t temperature range is possible and increases accuracy near the new calibration point.
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 235 figure 34. port input sample timing table 139. gpio port input timing parameter abbreviation delay (ns) minimum maximum t s_port port input transition to xin rise setup time (not pictured) 5? t h_port xin rise to port input transition hold time (not pictured) 0? t smr gpio port pin pulse wi dth to ensure stop mode recovery (for gpio port pins enabled as smr sources) 1 s system tclk port pin port value changes to 0 0 latched into port input input value port input data register latch clock data register port input data read on data bus port input data register value 0 read by ez8
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 236 general purpose i/o port output timing figure 35 and table 140 provide timing information for gpio port pins. figure 35. gpio port output timing table 140. gpio port output timing parameter abbreviation delay (ns) minimum maximum gpio port pins t 1 xin rise to port output valid delay ? 15 t 2 xin rise to port output hold time 2 ? xin port output tclk t1 t2
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 237 on-chip debugger timing figure 36 and table 141 provide timing information for the dbg pin. the dbg pin timing specifications assume a 4 ns maximum rise and fall time. figure 36. on-chip debugger timing table 141. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 xin rise to dbg valid delay ? 15 t 2 xin rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 5 ? t 4 dbg to xin rise input hold time 5 ? xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 238 uart timing figure 37 and table 142 provide timing information for uart pins for the case where cts is used for flow control. the cts to de assertion delay (t1) assumes the transmit data register has been loaded with data prior to cts assertion. figure 37. uart timing with cts table 142. uart timing with cts parameter abbreviation delay (ns) minimum maximum uart t 1 cts fall to de output delay 2 * xin period 2 * xin period + 1 bit time t 2 de assertion to txd falling ed ge (start bit) delay 5 t 3 end of stop bit(s) to de deassertion delay 5 cts de t1 (output) txd t2 (output) (input) start bit 0 bit 1 bit 7 parity stop end of stop bit(s) t3
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 239 figure 38 and table 143 provide timing information for uart pins for the case where cts is not used for flow cont rol. de asserts after the transmit data register has been written. de remains asserted for multiple characters as long as th e transmit data register is written with the next character before the current character has completed. figure 38. uart timing without cts table 143. uart timing without cts parameter abbreviation delay (ns) minimum maximum uart t 1 de assertion to txd fa lling edge (start bit) delay 1 * xin period 1 bit time t 2 end of stop bit(s) to de deassertion delay (tx data register is empty) 5 de t1 (output) txd t2 (output) start bit0 bit 1 bit 7 parity stop end of stop bit(s)
ps022825-0908 electrical characteristics z8 encore! xp ? f082a series product specification 240
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 241 packaging figure 39 displays the 8-pin plastic dual inline package (pdip) available for z8 encore! xp ? f082a series devices. figure 39. 8-pin plastic dual inline package (pdip) ea e b1 q1 b s a2 l e a1 c d e1 1 8 4 5 controlling dimensions : mm.
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 242 figure 40 displays the 8-pin small outline integr ated circuit package (soic) available for the z8 encore! xp ? f082a series devices. figure 40. 8-pin small outline integrated circuit package (soic)
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 243 figure 41 displays the 8-pin quad flat no-lea d package (qfn)/mlf-s available for the z8 encore! xp f082a series devi ces. this package has a footpr int identical to that of the 8-pin soic, but with a lower profile. figure 41. 8-pin quad flat no-lead package (qfn)/mlf-s
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 244 figure 42 displays the 20-pin plastic dual in line package (pdip) available for the z8 encore! xp f082a series devices. figure 42. 20-pin plastic dual inline package (pdip)
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 245 figure 43 displays the 20-pin smal l outline integrated circuit package (soic) available for the z8 encore! xp f082a series devices. figure 43. 20-pin small outline integrated circuit package (soic)
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 246 figure 44 displays the 20-pin small shrink ou tline package (ssop) available for the z8 encore! xp f082a series devices. figure 44. 20-pin small shrink outline package (ssop)
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 247 figure 45 displays the 28-pin plastic dual in line package (pdip) available for the z8 encore! xp f082a series devices. figure 45. 28-pin plastic dual inline package (pdip)
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 248 figure 46 displays the 28-pin smal l outline integrated circuit package (soic) available in the z8 encore! xp f082a series devices. figure 46. 28-pin small outline integrated circuit package (soic)
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 249 figure 47 displays the 28-pin small shrink ou tline package (ssop) available for the z8 encore! xp f082a series devices. figure 47. 28-pin small shrink outline package (ssop) symbol a a1 b c a2 e millimeter inch min max min max 1.73 0.05 1.68 0.25 5.20 0.65 typ 0.09 10.07 7.65 0.63 1.86 0.0256 typ 0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 nom nom d e h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 114 seating plane a2 e a q1 a1 b l 0 - 8 detail 'a'
ps022825-0908 packaging z8 encore! xp ? f082a series product specification 250
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 251 ordering information order the z8 encore! xp ? f082a series from zilog ? , using the following part numbers . for more information on ordering, please cons ult your local zilog sales office. the zilog website ( www.zilog.com ) lists all regional offices and provides additional z8 encore! xp product information. ? part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description z8 encore! xp ? f082a series with 8 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70c z8f082apb020sc 8 kb 1 kb 0 6 14 2 4 1 1 1 pdip 8-pin package z8f082aqb020sc 8 kb 1 kb 0 6 14 2 4 1 1 1 qfn 8-pin package z8f082asb020sc 8 kb 1 kb 0 6 14 2 4 1 1 1 soic 8-pin package z8f082ash020sc 8 kb 1 kb 0 17 20 2 7 1 1 1 soic 20-pin package z8f082ahh020sc 8 kb 1 kb 0 17 20 2 7 1 1 1 ssop 20-pin package z8f082aph020sc 8 kb 1 kb 0 17 20 2 7 1 1 1 pdip 20-pin package z8f082asj020sc 8 kb 1 kb 0 23 20 2 8 1 1 1 soic 28-pin package z8f082ahj020sc 8 kb 1 kb 0 23 20 2 8 1 1 1 ssop 28-pin package z8f082apj020sc 8 kb 1 kb 0 23 20 2 8 1 1 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f082apb020ec 8 kb 1 kb 0 6 14 2 4 1 1 1 pdip 8-pin package z8f082aqb020ec 8 kb 1 kb 0 6 14 2 4 1 1 1 qfn 8-pin package z8f082asb020ec 8 kb 1 kb 0 6 14 2 4 1 1 1 soic 8-pin package z8f082ash020ec 8 kb 1 kb 0 17 20 2 7 1 1 1 soic 20-pin package z8f082ahh020ec 8 kb 1 kb 0 17 20 2 7 1 1 1 ssop 20-pin package z8f082aph020ec 8 kb 1 kb 0 17 20 2 7 1 1 1 pdip 20-pin package z8f082asj020ec 8 kb 1 kb 0 23 20 2 8 1 1 1 soic 28-pin package z8f082ahj020ec 8 kb 1 kb 0 23 20 2 8 1 1 1 ssop 28-pin package z8f082apj020ec 8 kb 1 kb 0 23 20 2 8 1 1 1 pdip 28-pin package replace c with g for lead-free packaging
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 252 z8 encore! xp ? f082a series with 8 kb flash standard temperature: 0 c to 70 c z8f081apb020sc 8 kb 1 kb 0 6 13 2 0 1 1 0 pdip 8-pin package z8f081aqb020sc 8 kb 1 kb 0 6 13 2 0 1 1 0 qfn 8-pin package z8f081asb020sc 8 kb 1 kb 0 6 13 2 0 1 1 0 soic 8-pin package z8f081ash020sc 8 kb 1 kb 0 17 19 2 0 1 1 0 soic 20-pin package z8f081ahh020sc 8 kb 1 kb 0 17 19 2 0 1 1 0 ssop 20-pin package z8f081aph020sc 8 kb 1 kb 0 17 19 2 0 1 1 0 pdip 20-pin package z8f081asj020sc 8 kb 1 kb 0 25 19 2 0 1 1 0 soic 28-pin package z8f081ahj020sc 8 kb 1 kb 0 25 19 2 0 1 1 0 ssop 28-pin package z8f081apj020sc 8 kb 1 kb 0 25 19 2 0 1 1 0 pdip 28-pin package extended temperature: -40 c to 105 c z8f081apb020ec 8 kb 1 kb 0 6 13 2 0 1 1 0 pdip 8-pin package z8f081aqb020ec 8 kb 1 kb 0 6 13 2 0 1 1 0 qfn 8-pin package z8f081asb020ec 8 kb 1 kb 0 6 13 2 0 1 1 0 soic 8-pin package z8f081ash020ec 8 kb 1 kb 0 17 19 2 0 1 1 0 soic 20-pin package z8f081ahh020ec 8 kb 1 kb 0 17 19 2 0 1 1 0 ssop 20-pin package z8f081aph020ec 8 kb 1 kb 0 17 19 2 0 1 1 0 pdip 20-pin package z8f081asj020ec 8 kb 1 kb 0 25 19 2 0 1 1 0 soic 28-pin package z8f081ahj020ec 8 kb 1 kb 0 25 19 2 0 1 1 0 ssop 28-pin package z8f081apj020ec 8 kb 1 kb 0 25 19 2 0 1 1 0 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 253 z8 encore! xp ? f082a series with 4 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f042apb020sc 4 kb 1 kb 128 b 6 14 2 4 1 1 1 pdip 8-pin package z8f042aqb020sc 4 kb 1 kb 128 b 6 14 2 4 1 1 1 qfn 8-pin package z8f042asb020sc 4 kb 1 kb 128 b 6 14 2 4 1 1 1 soic 8-pin package z8f042ash020sc 4 kb 1 kb 128 b 17 20 2 7 1 1 1 soic 20-pin package z8f042ahh020sc 4 kb 1 kb 128 b 17 20 2 7 1 1 1 ssop 20-pin package z8f042aph020sc 4 kb 1 kb 128 b 17 20 2 7 1 1 1 pdip 20-pin package z8f042asj020sc 4 kb 1 kb 128 b 23 20 2 8 1 1 1 soic 28-pin package z8f042ahj020sc 4 kb 1 kb 128 b 23 20 2 8 1 1 1 ssop 28-pin package z8f042apj020sc 4 kb 1 kb 128 b 23 20 2 8 1 1 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f042apb020ec 4 kb 1 kb 128 b 6 14 2 4 1 1 1 pdip 8-pin package z8f042aqb020ec 4 kb 1 kb 128 b 6 14 2 4 1 1 1 qfn 8-pin package z8f042asb020ec 4 kb 1 kb 128 b 6 14 2 4 1 1 1 soic 8-pin package z8f042ash020ec 4 kb 1 kb 128 b 17 20 2 7 1 1 1 soic 20-pin package z8f042ahh020ec 4 kb 1 kb 128 b 17 20 2 7 1 1 1 ssop 20-pin package z8f042aph020ec 4 kb 1 kb 128 b 17 20 2 7 1 1 1 pdip 20-pin package z8f042asj020ec 4 kb 1 kb 128 b 23 20 2 8 1 1 1 soic 28-pin package z8f042ahj020ec 4 kb 1 kb 128 b 23 20 2 8 1 1 1 ssop 28-pin package z8f042apj020ec 4 kb 1 kb 128 b 23 20 2 8 1 1 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 254 z8 encore! xp ? f082a series with 4 kb flash standard temperature: 0 c to 70 c z8f041apb020sc 4 kb 1 kb 128 b 6 13 2 0 1 1 0 pdip 8-pin package z8f041aqb020sc 4 kb 1 kb 128 b 6 13 2 0 1 1 0 qfn 8-pin package z8f041asb020sc 4 kb 1 kb 128 b 6 13 2 0 1 1 0 soic 8-pin package z8f041ash020sc 4 kb 1 kb 128 b 17 19 2 0 1 1 0 soic 20-pin package z8f041ahh020sc 4 kb 1 kb 128 b 17 19 2 0 1 1 0 ssop 20-pin package z8f041aph020sc 4 kb 1 kb 128 b 17 19 2 0 1 1 0 pdip 20-pin package z8f041asj020sc 4 kb 1 kb 128 b 25 19 2 0 1 1 0 soic 28-pin package z8f041ahj020sc 4 kb 1 kb 128 b 25 19 2 0 1 1 0 ssop 28-pin package z8f041apj020sc 4 kb 1 kb 128 b 25 19 2 0 1 1 0 pdip 28-pin package extended temperature: -40 c to 105 c z8f041apb020ec 4 kb 1 kb 128 b 6 13 2 0 1 1 0 pdip 8-pin package z8f041aqb020ec 4 kb 1 kb 128 b 6 13 2 0 1 1 0 qfn 8-pin package z8f041asb020ec 4 kb 1 kb 128 b 6 13 2 0 1 1 0 soic 8-pin package z8f041ash020ec 4 kb 1 kb 128 b 17 19 2 0 1 1 0 soic 20-pin package z8f041ahh020ec 4 kb 1 kb 128 b 17 19 2 0 1 1 0 ssop 20-pin package z8f041aph020ec 4 kb 1 kb 128 b 17 19 2 0 1 1 0 pdip 20-pin package z8f041asj020ec 4 kb 1 kb 128 b 25 19 2 0 1 1 0 soic 28-pin package z8f041ahj020ec 4 kb 1 kb 128 b 25 19 2 0 1 1 0 ssop 28-pin package z8f041apj020ec 4 kb 1 kb 128 b 25 19 2 0 1 1 0 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 255 z8 encore! xp ? f082a series with 2 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f022apb020sc 2 kb 512 b 64 b 6 14 2 4 1 1 1 pdip 8-pin package z8f022aqb020sc 2 kb 512 b 64 b 6 14 2 4 1 1 1 qfn 8-pin package z8f022asb020sc 2 kb 512 b 64 b 6 14 2 4 1 1 1 soic 8-pin package z8f022ash020sc 2 kb 512 b 64 b 17 20 2 7 1 1 1 soic 20-pin package z8f022ahh020sc 2 kb 512 b 64 b 17 20 2 7 1 1 1 ssop 20-pin package z8f022aph020sc 2 kb 512 b 64 b 17 20 2 7 1 1 1 pdip 20-pin package z8f022asj020sc 2 kb 512 b 64 b 23 20 2 8 1 1 1 soic 28-pin package z8f022ahj020sc 2 kb 512 b 64 b 23 20 2 8 1 1 1 ssop 28-pin package z8f022apj020sc 2 kb 512 b 64 b 23 20 2 8 1 1 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f022apb020ec 2 kb 512 b 64 b 6 14 2 4 1 1 1 pdip 8-pin package z8f022aqb020ec 2 kb 512 b 64 b 6 14 2 4 1 1 1 qfn 8-pin package z8f022asb020ec 2 kb 512 b 64 b 6 14 2 4 1 1 1 soic 8-pin package z8f022ash020ec 2 kb 512 b 64 b 17 20 2 7 1 1 1 soic 20-pin package z8f022ahh020ec 2 kb 512 b 64 b 17 20 2 7 1 1 1 ssop 20-pin package z8f022aph020ec 2 kb 512 b 64 b 17 20 2 7 1 1 1 pdip 20-pin package z8f022asj020ec 2 kb 512 b 64 b 23 20 2 8 1 1 1 soic 28-pin package z8f022ahj020ec 2 kb 512 b 64 b 23 20 2 8 1 1 1 ssop 28-pin package z8f022apj020ec 2 kb 512 b 64 b 23 20 2 8 1 1 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 256 z8 encore! xp ? f082a series with 2 kb flash standard temperature: 0 c to 70 c z8f021apb020sc 2 kb 512 b 64 b 6 13 2 0 1 1 0 pdip 8-pin package z8f021aqb020sc 2 kb 512 b 64 b 6 13 2 0 1 1 0 qfn 8-pin package z8f021asb020sc 2 kb 512 b 64 b 6 13 2 0 1 1 0 soic 8-pin package z8f021ash020sc 2 kb 512 b 64 b 17 19 2 0 1 1 0 soic 20-pin package z8f021ahh020sc 2 kb 512 b 64 b 17 19 2 0 1 1 0 ssop 20-pin package z8f021aph020sc 2 kb 512 b 64 b 17 19 2 0 1 1 0 pdip 20-pin package z8f021asj020sc 2 kb 512 b 64 b 25 19 2 0 1 1 0 soic 28-pin package z8f021ahj020sc 2 kb 512 b 64 b 25 19 2 0 1 1 0 ssop 28-pin package z8f021apj020sc 2 kb 512 b 64 b 25 19 2 0 1 1 0 pdip 28-pin package extended temperature: -40 c to 105 c z8f021apb020ec 2 kb 512 b 64 b 6 13 2 0 1 1 0 pdip 8-pin package z8f021aqb020ec 2 kb 512 b 64 b 6 13 2 0 1 1 0 qfn 8-pin package z8f021asb020ec 2 kb 512 b 64 b 6 13 2 0 1 1 0 soic 8-pin package z8f021ash020ec 2 kb 512 b 64 b 17 19 2 0 1 1 0 soic 20-pin package Z8F021AHH020EC 2 kb 512 b 64 b 17 19 2 0 1 1 0 ssop 20-pin package z8f021aph020ec 2 kb 512 b 64 b 17 19 2 0 1 1 0 pdip 20-pin package z8f021asj020ec 2 kb 512 b 64 b 25 19 2 0 1 1 0 soic 28-pin package z8f021ahj020ec 2 kb 512 b 64 b 25 19 2 0 1 1 0 ssop 28-pin package z8f021apj020ec 2 kb 512 b 64 b 25 19 2 0 1 1 0 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 257 z8 encore! xp ? f082a series with 1 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f012apb020sc 1 kb 256 b 16 b 6 14 2 4 1 1 1 pdip 8-pin package z8f012aqb020sc 1 kb 256 b 16 b 6 14 2 4 1 1 1 qfn 8-pin package z8f012asb020sc 1 kb 256 b 16 b 6 14 2 4 1 1 1 soic 8-pin package z8f012ash020sc 1 kb 256 b 16 b 17 20 2 7 1 1 1 soic 20-pin package z8f012ahh020sc 1 kb 256 b 16 b 17 20 2 7 1 1 1 ssop 20-pin package z8f012aph020sc 1 kb 256 b 16 b 17 20 2 7 1 1 1 pdip 20-pin package z8f012asj020sc 1 kb 256 b 16 b 23 20 2 8 1 1 1 soic 28-pin package z8f012ahj020sc 1 kb 256 b 16 b 23 20 2 8 1 1 1 ssop 28-pin package z8f012apj020sc 1 kb 256 b 16 b 23 20 2 8 1 1 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f012apb020ec 1 kb 256 b 16 b 6 14 2 4 1 1 1 pdip 8-pin package z8f012aqb020ec 1 kb 256 b 16 b 6 14 2 4 1 1 1 qfn 8-pin package z8f012asb020ec 1 kb 256 b 16 b 6 14 2 4 1 1 1 soic 8-pin package z8f012ash020ec 1 kb 256 b 16 b 17 20 2 7 1 1 1 soic 20-pin package z8f012ahh020ec 1 kb 256 b 16 b 17 20 2 7 1 1 1 ssop 20-pin package z8f012aph020ec 1 kb 256 b 16 b 17 20 2 7 1 1 1 pdip 20-pin package z8f012asj020ec 1 kb 256 b 16 b 23 20 2 8 1 1 1 soic 28-pin package z8f012ahj020ec 1 kb 256 b 16 b 23 20 2 8 1 1 1 ssop 28-pin package z8f012apj020ec 1 kb 256 b 16 b 23 20 2 8 1 1 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 258 z8 encore! xp ? f082a series with 1 kb flash standard temperature: 0 c to 70 c z8f011apb020sc 1 kb 256 b 16 b 6 13 2 0 1 1 0 pdip 8-pin package z8f011aqb020sc 1 kb 256 b 16 b 6 13 2 0 1 1 0 qfn 8-pin package z8f011asb020sc 1 kb 256 b 16 b 6 13 2 0 1 1 0 soic 8-pin package z8f011ash020sc 1 kb 256 b 16 b 17 19 2 0 1 1 0 soic 20-pin package z8f011ahh020sc 1 kb 256 b 16 b 17 19 2 0 1 1 0 ssop 20-pin package z8f011aph020sc 1 kb 256 b 16 b 17 19 2 0 1 1 0 pdip 20-pin package z8f011asj020sc 1 kb 256 b 16 b 25 19 2 0 1 1 0 soic 28-pin package z8f011ahj020sc 1 kb 256 b 16 b 25 19 2 0 1 1 0 ssop 28-pin package z8f011apj020sc 1 kb 256 b 16 b 25 19 2 0 1 1 0 pdip 28-pin package extended temperature: -40 c to 105 c z8f011apb020ec 1 kb 256 b 16 b 6 13 2 0 1 1 0 pdip 8-pin package z8f011aqb020ec 1 kb 256 b 16 b 6 13 2 0 1 1 0 qfn 8-pin package z8f011asb020ec 1 kb 256 b 16 b 6 13 2 0 1 1 0 soic 8-pin package z8f011ash020ec 1 kb 256 b 16 b 17 19 2 0 1 1 0 soic 20-pin package z8f011ahh020ec 1 kb 256 b 16 b 17 19 2 0 1 1 0 ssop 20-pin package z8f011aph020ec 1 kb 256 b 16 b 17 19 2 0 1 1 0 pdip 20-pin package z8f011asj020ec 1 kb 256 b 16 b 25 19 2 0 1 1 0 soic 28-pin package z8f011ahj020ec 1 kb 256 b 16 b 25 19 2 0 1 1 0 ssop 28-pin package z8f011apj020ec 1 kb 256 b 16 b 25 19 2 0 1 1 0 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 259 z8 encore! xp ? f082a series development kit z8f08a28100kitg z8 encore! xp f082 a series 28-pin development kit z8f04a28100kitg z8 encore! xp f042 a series 28-pin development kit z8f04a08100kitg z8 encore! xp f042 a series 8-pin development kit zusbsc00100zacg usb smart cable accessory kit zusboptsc01zacg usb opto-isolated smart cable accessory kit zenetsc0100zacg ethernet smart cable accessory kit part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022825-0908 ordering information z8 encore! xp ? f082a series product specification 260 part number suffix designations z8 f 04 2a s h 020 s c environmental flow c = standard plastic packaging compound g = green plastic packaging compound temperature range s = standard, 0 c to 70 c e = extended, -40 c to +105 c speed 020 = 20 mhz pin count b = 8 h = 20 j = 28 package h = ssop p = pdip q = qfn s = soic device type 2a = contains advanced analog peripherals 1a = does not contain advanced analog peripherals memory size 08 = 8 kb flash, 1 kb ram, 0 b nvds 04 = 4 kb flash, 1 kb ram, 128 b nvds 02 = 2 kb flash, 512 b ram, 64 b nvds 01 = 1 kb flash, 256 b ram, 16 b nvds memory type f = flash device family z8 = zilog?s 8-bit microcontroller
z8 encore! xp ? f082a series product specification ps022825-0908 index 261 index symbols # 202 % 202 @ 202 numerics 10-bit adc 7 40-lead plastic dual-inline package 248, 249 a absolute maximum ratings 221 ac characteristics 227 adc 203 architecture 121 automatic power-down 122 block diagram 122 continuous conversion 124 control register 130, 132 control register definitions 130 data high byte register 132 data low bits register 133 electrical characteristics and timing 231 operation 122 single-shot conversion 123 adcctl register 130, 132 adcdh register 132 adcdl register 133 adcx 203 add 203 add - extended addressing 203 add with carry 203 add with carry - extended addressing 203 additional symbols 202 address space 15 addx 203 analog signals 12 analog-to-digital converter (adc) 121 and 205 andx 205 arithmetic instructions 203 assembly language programming 199 assembly language syntax 200 b b 202 b 201 baud rate generator, uart 107 bclr 204 binary number suffix 202 bit 204 bit 201 clear 204 manipulation instructions 204 set 204 set or clear 204 swap 204 test and jump 206 test and jump if non-zero 206 test and jump if zero 206 bit jump and test if non-zero 206 bit swap 206 block diagram 4 block transfer instructions 204 brk 206 bset 204 bswap 204, 206 btj 206 btjnz 206 btjz 206 c call procedure 206 capture mode 85, 86 capture/compare mode 85 cc 201 ccf 204 characteristics, electrical 221 clear 205 clr 205 com 205
z8 encore! xp ? f082a series product specification ps022825-0908 index 262 compare 85 compare - extended addressing 203 compare mode 85 compare with carry 203 compare with carry - extended addressing 203 complement 205 complement carry flag 204 condition code 201 continuous conversion (adc) 124 continuous mode 84 control register definition, uart 108 control registers 15, 19 counter modes 84 cp 203 cpc 203 cpcx 203 cpu and peripheral overview 5 cpu control instructions 204 cpx 203 customer feedback form 271 d da 201, 203 data memory 17 dc characteristics 222 debugger, on-chip 173 dec 203 decimal adjust 203 decrement 203 decrement and jump non-zero 206 decrement word 203 decw 203 destination operand 202 device, port availability 37 di 204 direct address 201 disable interrupts 204 djnz 206 dst 202 e ei 204 electrical characteristics 221 adc 231 flash memory and timing 230 gpio input data sample timing 234 watchdog timer 230, 233 enable interrupt 204 er 201 extended addressing register 201 external pin reset 27 ez8 cpu features 5 ez8 cpu instruction classes 202 ez8 cpu instruction notation 200 ez8 cpu instruction set 199 ez8 cpu instruction summary 207 f fctl register 149, 155, 156 features, z8 encore! 1 first opcode map 218 flags 202 flags register 202 flash controller 7 option bit address space 156 option bit configuration - reset 153 program memory address 0000h 156 program memory address 0001h 158 flash memory 141 arrangement 142 byte programming 147 code protection 145 configurations 141 control register definitions 149, 155 controller bypass 148 electrical characteristics and timing 230 flash control register 149, 155, 156 flash option bits 146 flash status register 150 flow chart 144 frequency high and low byte registers 152 mass erase 147 operation 143 operation timing 145
z8 encore! xp ? f082a series product specification ps022825-0908 index 263 page erase 147 page select register 150, 151 fps register 150, 151 fstat register 150 g gated mode 85 general-purpose i/o 37 gpio 7, 37 alternate functions 38 architecture 38 control register definitions 45 input data sample timing 234 interrupts 45 port a-c pull-up enable sub-registers 50, 51 port a-h address registers 46 port a-h alternate function sub-registers 47 port a-h control registers 46 port a-h data direction sub-registers 47 port a-h high drive enable sub-registers 49 port a-h input data registers 51 port a-h output control sub-registers 48 port a-h output data registers 52 port a-h stop mode recovery sub-registers 49 port availability by device 37 port input timing 235 port output timing 236 h h 202 halt 204 halt mode 34, 204 hexadecimal number prefix/suffix 202 i i2c 7 im 201 immediate data 201 immediate operand prefix 202 inc 203 increment 203 increment word 203 incw 203 indexed 201 indirect address prefix 202 indirect register 201 indirect register pair 201 indirect working register 201 indirect working register pair 201 infrared encoder/decoder (irda) 117 instruction set 199 instruction set, ez8 cpu 199 instructions adc 203 adcx 203 add 203 addx 203 and 205 andx 205 arithmetic 203 bclr 204 bit 204 bit manipulation 204 block transfer 204 brk 206 bset 204 bswap 204, 206 btj 206 btjnz 206 btjz 206 call 206 ccf 204 clr 205 com 205 cp 203 cpc 203 cpcx 203 cpu control 204 cpx 203 da 203 dec 203 decw 203 di 204
z8 encore! xp ? f082a series product specification ps022825-0908 index 264 djnz 206 ei 204 halt 204 inc 203 incw 203 iret 206 jp 206 ld 205 ldc 205 ldci 204, 205 lde 205 ldei 204 ldx 205 lea 205 logical 205 mult 203 nop 204 or 205 orx 206 pop 205 popx 205 program control 206 push 205 pushx 205 rcf 204 ret 206 rl 206 rlc 206 rotate and shift 206 rr 206 rrc 206 sbc 203 scf 204, 205 sra 207 srl 207 srp 205 stop 205 sub 203 subx 203 swap 207 tcm 204 tcmx 204 tm 204 tmx 204 trap 206 watchdog timer refresh 205 xor 206 xorx 206 instructions, ez8 classes of 202 interrupt control register 67 interrupt controller 55 architecture 55 interrupt assertion types 58 interrupt vectors and priority 58 operation 57 register definitions 60 software interrupt assertion 59 interrupt edge select register 66 interrupt request 0 register 60 interrupt request 1 register 61 interrupt request 2 register 62 interrupt return 206 interrupt vector listing 55 interrupts uart 105 ir 201 ir 201 irda architecture 117 block diagram 117 control register definitions 120 operation 117 receiving data 119 transmitting data 118 iret 206 irq0 enable high and low bit registers 62 irq1 enable high and low bit registers 63 irq2 enable high and low bit registers 65 irr 201 irr 201 j jp 206 jump, conditional, relative, and relative condi- tional 206
z8 encore! xp ? f082a series product specification ps022825-0908 index 265 l ld 205 ldc 205 ldci 204, 205 lde 205 ldei 204, 205 ldx 205 lea 205 load 205 load constant 204 load constant to/from program memory 205 load constant with auto-increment addresses 205 load effective address 205 load external data 205 load external data to/from data memory and auto-increment addresses 204 load external to/from data memory and auto-in- crement addresses 205 load using extended addressing 205 logical and 205 logical and/extended addressing 205 logical exclusive or 206 logical exclusive or/extended addressing 206 logical instructions 205 logical or 205 logical or/extended addressing 206 low power modes 33 m master interrupt enable 57 memory data 17 program 15 mode capture 85, 86 capture/compare 85 continuous 84 counter 84 gated 85 one-shot 84 pwm 85 modes 85 mult 203 multiply 203 multiprocessor mode, uart 103 n nop (no operation) 204 notation b 201 cc 201 da 201 er 201 im 201 ir 201 ir 201 irr 201 irr 201 p 201 r 201 r 201 ra 201 rr 201 rr 201 vector 201 x 201 notational shorthand 201 o ocd architecture 173 auto-baud detector/generator 176 baud rate limits 177 block diagram 173 breakpoints 178 commands 179 control register 184 data format 176 dbg pin to rs-232 interface 174 debug mode 175 debugger break 206 interface 174 serial errors 177 status register 185
z8 encore! xp ? f082a series product specification ps022825-0908 index 266 timing 237 ocd commands execute instruction (12h) 183 read data memory (0dh) 183 read ocd control register (05h) 181 read ocd revision (00h) 180 read ocd status register (02h) 180 read program counter (07h) 181 read program memory (0bh) 182 read program memory crc (0eh) 183 read register (09h) 182 read runtime counter (03h) 180 step instruction (10h) 183 stuff instruction (11h) 183 write data memory (0ch) 182 write ocd control register (04h) 181 write program counter (06h) 181 write program memory (0ah) 182 write register (08h) 181 on-chip debugger (ocd) 173 on-chip debugger signals 12 on-chip oscillator 193 one-shot mode 84 opcode map abbreviations 217 cell description 216 first 218 second after 1fh 219 operational description 23, 33, 37, 55, 69, 91, 97, 117, 121, 134, 135, 139, 141, 153, 169, 173, 187, 193, 197 or 205 ordering information 251 orx 206 oscillator signals 12 p p 201 packaging 20-pin pdip 244, 245 20-pin ssop 246, 249 28-pin pdip 247 28-pin soic 248 8-pin pdip 241 8-pin soic 242 pdip 248, 249 part selection guide 2 pc 202 pdip 248, 249 peripheral ac and dc electrical characteristics 229 pin characteristics 13 pin descriptions 9 polarity 201 pop 205 pop using extended addressing 205 popx 205 port availability, device 37 port input timing (gpio) 235 port output timing, gpio 236 power supply signals 13 power-down, automatic (adc) 122 power-on and voltage brownout electrical characteristics and timing 229 power-on reset (por) 25 program control instructions 206 program counter 202 program memory 15 push 205 push using extended addressing 205 pushx 205 pwm mode 85 pxaddr register 46 pxctl register 47 r r 201 r 201 ra register address 201 rcf 204 receive irda data 119 receiving uart data-interrupt-driven method 102 receiving uart data-polled method 101
z8 encore! xp ? f082a series product specification ps022825-0908 index 267 register 201 adc control (adcctl) 130, 132 adc data high byte (adcdh) 132 adc data low bits (adcdl) 133 flash control (fctl) 149, 155, 156 flash high and low byte (ffreqh and freeql) 152 flash page select (fps) 150, 151 flash status (fstat) 150 gpio port a-h address (pxaddr) 46 gpio port a-h alternate function sub-regis- ters 48 gpio port a-h control address (pxctl) 47 gpio port a-h data direction sub-registers 47 ocd control 184 ocd status 185 uartx baud rate high byte (uxbrh) 114 uartx baud rate low byte (uxbrl) 114 uartx control 0 (uxctl0) 108, 114 uartx control 1 (uxctl1) 109 uartx receive data (uxrxd) 113 uartx status 0 (uxstat0) 111 uartx status 1 (uxstat1) 112 uartx transmit data (uxtxd) 113 watchdog timer control (wdtctl) 31, 94, 136, 190 watchdog timer reload high byte (wdth) 95 watchdog timer reload low byte (wdtl) 95 watchdog timer reload upper byte (wd- tu) 95 register file 15 register pair 201 register pointer 202 reset and stop mode characteristics 24 and stop mode recovery 23 carry flag 204 sources 25 ret 206 return 206 rl 206 rlc 206 rotate and shift instuctions 206 rotate left 206 rotate left through carry 206 rotate right 206 rotate right through carry 206 rp 202 rr 201, 206 rr 201 rrc 206 s sbc 203 scf 204, 205 second opcode map after 1fh 219 set carry flag 204, 205 set register pointer 205 shift right arithmatic 207 shift right logical 207 signal descriptions 11 single-shot conversion (adc) 123 software trap 206 source operand 202 sp 202 sra 207 src 202 srl 207 srp 205 stack pointer 202 stop 205 stop mode 33 stop mode 205 stop mode recovery sources 28 using a gpio port pin transition 29 using watchdog timer time-out 29 stop mode recovery sources 30 using a gpio port pin transition 30 sub 203 subtract 203 subtract - extended addressing 203 subtract with carry 203
z8 encore! xp ? f082a series product specification ps022825-0908 index 268 subtract with carry - extended addressing 203 subx 203 swap 207 swap nibbles 207 symbols, additional 202 t tcm 204 tcmx 204 technical support 271 test complement under mask 204 test complement under mask - extended ad- dressing 204 test under mask 204 test under mask - extended addressing 204 timer signals 11 timers 69 architecture 69 block diagram 70 capture mode 77, 78, 85, 86 capture/compare mode 81, 85 compare mode 79, 85 continuous mode 71, 84 counter mode 72, 73 counter modes 84 gated mode 80, 85 one-shot mode 70, 84 operating mode 70 pwm mode 74, 76, 85 reading the timer count values 82 reload high and low byte registers 87 timer control register definitions 83 timer output signal operation 82 timers 0-3 control registers 83, 84 high and low byte registers 87, 88 tm 204 tmx 204 transmit irda data 118 transmitting uart data-polled method 99 transmitting uart dat-interrupt-driven method 100 trap 206 u uart 7 architecture 97 baud rate generator 107 baud rates table 115 control register definitions 108 controller signals 11 data format 98 interrupts 105 multiprocessor mode 103 receiving data using interrupt-driven meth- od 102 receiving data using the polled method 101 transmitting data usin the interrupt-driven method 100 transmitting data using the polled method 99 x baud rate high and low registers 114 x control 0 and control 1 registers 108 x status 0 and status 1 registers 111, 112 uxbrh register 114 uxbrl register 114 uxctl0 register 108, 114 uxctl1 register 109 uxrxd register 113 uxstat0 register 111 uxstat1 register 112 uxtxd register 113 v vector 201 voltage brownout reset (vbr) 26 w watchdog timer approximate time-out delay 91 approximate time-out delays 135 cntl 26 control register 94, 136, 190
z8 encore! xp ? f082a series product specification ps022825-0908 index 269 electrical characteristics and timing 230, 233 interrupt in normal operation 92 interrupt in stop mode 92 operation 135 refresh 92, 205 reload unlock sequence 93 reload upper, high and low registers 94 reset 27 reset in normal operation 93 reset in stop mode 93 time-out response 92 wdtctl register 31, 94, 136, 190 wdth register 95 wdtl register 95 working register 201 working register pair 201 wtdu register 95 x x 201 xor 206 xorx 206 z z8 encore! block diagram 4 features 1 part selection guide 2
z8 encore! xp ? f082a series product specification ps022825-0908 index 270
ps022825-0908 customer support z8 encore! xp ? f082a series product specification 271 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offerings, please visit zilog?s knowledge base at http://www.zilog.com/kb . for any comments, detail technical questi ons, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .

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